OPA4202 [TI]
高容性驱动 (25nF)、精密 (200uV)、低噪声 (9nV/rtHz)、超 β 四路运算放大器;
| 型号： | OPA4202 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高容性驱动 (25nF)、精密 (200uV)、低噪声 (9nV/rtHz)、超 β 四路运算放大器 放大器 驱动 运算放大器 |
| 文件： | 总50页 (文件大小：3019K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA202, OPA2202, OPA4202
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
OPAx202 精密、低噪声、高电容驱动能力 36V 运算放大器
1 特性
3 说明
1
•
精密超级 ß 性能：
OPA202、OPA2202 和 OPA4202 (OPAx202) 是在 TI
业界领先的精密超级 ß 互补双极半导体工艺基础上构
建的一系列器件。此工艺提供超低闪烁噪声、低失调电
压、低失调电压温漂和优异线性度，并具有共模和电源
变化。这些器件具有一系列出色的特性：直流精度、高
容性负载驱动以及外部 EMI 保护、过热保护和短路保
护。
–
–
低失调电压：200µV（最大值）
超低温漂：1µV/°C（最大值）
•
•
出色的效率：
–
–
–
静态电流：580µA（典型值）
增益带宽积：1MHz
低输入电压噪声：9nV/√Hz
方便易用，简化设计：
±18V 时的电源电流为 580µA。OPAx202 系列不会出
现相位反转，并能够在高容性负载下保持稳定。
OPAx202 额定工作温度范围为 -40°C 至 +105°C。
–
–
–
高容性负载驱动：25nF 负载时具有 5µs 稳定时
间
超高输入阻抗：3000GΩ 和
0.5pF
器件信息(1)
器件型号
封装
SOIC (8)
封装尺寸（标称值）
4.90mm × 3.91mm
2.90mm × 1.60mm
3.00mm × 3.00mm
3.00mm × 3.00mm
8.65mm × 3.91mm
抗电磁干扰 (EMI)，具有过热保护和短路保护
•
稳定性能：
OPA202
SOT-23 (5)
–
–
高 CMRR 和 AOL：126dB（最小值）
高 PSRR：126dB（最小值）
VSSOP (8)（预览）
VSSOP (8)
OPA2202
OPA4202
•
•
•
•
低偏置电流：2nA（最大值）
0.1Hz 至 10Hz 低噪声：0.2µVPP
宽电源电压：±2.25V 至 ±18V
取代 OP-07 和 OP-27
SOIC (14)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
OPAx202 即使在直接驱动高容性负载时也表现优异
10
2 应用
8
•
•
•
•
•
数据采集 (DAQ)
6
实验室和现场仪表
商用网络和服务器 PSU
多参数患者监护仪
串式逆变器
4
2
25000 pF
0
œ2
œ4
œ6
œ8
CL = 28 pF to 25000 pF
œ10
0
1
2
3
4
5
Time (ꢀs)
C003
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS812
OPA202, OPA2202, OPA4202
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 25
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Application ................................................. 28
Power Supply Recommendations...................... 29
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information: OPA202 .................................. 7
6.5 Thermal Information: OPA2202 ................................ 7
6.6 Thermal Information: OPA4202 ................................ 7
6.7 Electrical Characteristics........................................... 8
6.8 Typical Characteristics............................................ 10
6.9 Typical Characteristics............................................ 11
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 19
8
9
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 30
11 器件和文档支持 ..................................................... 31
11.1 器件支持................................................................ 31
11.2 文档支持................................................................ 31
11.3 相关链接................................................................ 32
11.4 接收文档更新通知 ................................................. 32
11.5 支持资源................................................................ 32
11.6 商标....................................................................... 32
11.7 静电放电警告......................................................... 32
11.8 Glossary................................................................ 32
12 机械、封装和可订购信息....................................... 32
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (December 2019) to Revision E
Page
•
已添加 向数据表添加了 OPA202 8 引脚 VSSOP (DGK) 预发布封装和相关内容................................................................... 1
Changes from Revision C (October 2018) to Revision D
Page
•
已更改 将 OPA2202 和 OPA4202 器件从预告信息（预发布）更改为生产数据（正在供货） ............................................... 1
Changes from Revision B (December 2018) to Revision C
Page
•
•
已添加 向数据表添加了 OPA2202 和 OPA4202 预发布器件和相关内容................................................................................ 1
已删除 Operating Voltage section; redundant information ................................................................................................... 19
Changes from Revision A (September 2018) to Revision B
Page
•
已更改 将 SOT-23 封装从预发布更改为生产数据................................................................................................................... 1
Changes from Original (October 2017) to Revision A
Page
•
已添加 添加了适用于 SOT-23 封装产品的预发布内容............................................................................................................ 1
2
Copyright © 2017–2020, Texas Instruments Incorporated
OPA202, OPA2202, OPA4202
www.ti.com.cn
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
5 Pin Configuration and Functions
OPA202 D, DGK(1) Packages
8-Pin SOIC and VSSOP
Top View
OPA202 DBV Package
5-Pin SOT-23
Top View
NC
œIN
+IN
Vœ
1
2
3
4
8
7
6
5
NC
V+
OUT
Vœ
1
2
3
5
V+
œ
OUT
NC
+
+IN
4
œIN
Not to scale
Not to scale
(1) DGK package is preview.
Pin Functions: OPA202
PIN
NO.
I/O
DESCRIPTION
NAME
D (SOIC)
DGK (VSSOP)
DBV (SOT-23)
–IN
+IN
NC
OUT
V–
2
4
3
I
Inverting input
Noninverting input
3
I
1, 5, 8
—
1
—
O
—
—
No internal connection (can be left floating)
Output
6
4
7
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
Copyright © 2017–2020, Texas Instruments Incorporated
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OPA202, OPA2202, OPA4202
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OPA2202 DGK Package
8-Pin VSSOP
Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Pin Functions: OPA2202
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input channel A
3
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Output channel A
6
I
5
I
1
O
O
—
—
7
Output channel B
4
Negative supply
V+
8
Positive supply
4
Copyright © 2017–2020, Texas Instruments Incorporated
OPA202, OPA2202, OPA4202
www.ti.com.cn
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
OPA4202 D Package
14-Pin SOIC
Top View
OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
Pin Functions: OPA4202
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
I
I
Inverting input channel A
3
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Inverting input channel C
Noninverting input channel C
Inverting input channel D
Noninverting input channel D
Output channel A
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output channel B
8
Output channel C
14
11
4
Output channel D
Negative supply
V+
Positive supply
Copyright © 2017–2020, Texas Instruments Incorporated
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OPA202, OPA2202, OPA4202
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Single-supply
Dual-supply
Supply voltage,
VS = (V+) – (V–)
±20
Common-mode(2)
Differential(3)
(V–) – 0.5
(V+) + 0.5
±0.5
Voltage
Current
Signal input pins
±10
mA
Output short current(4)
Continuous
Operating temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
–40
125
125
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that swing more than 0.5 V beyond the supply rails must be
current-limited to 10 mA or less.
(3) Input terminals are anti-parallel diode-clamped to each other. Input signals that cause differential voltages of swing more than ± 0.5 V
must be current-limited to 10 mA or less.
(4) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
Single-supply
Dual-supply
VS
TA
Supply voltage, [ (V+) – (V–) ]
Specified temperature
V
±2.25
–40
±18
105
°C
6
Copyright © 2017–2020, Texas Instruments Incorporated
OPA202, OPA2202, OPA4202
www.ti.com.cn
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
6.4 Thermal Information: OPA202
OPA202
THERMAL METRIC(1)
D (SOIC)
8 PINS
136
DGK (VSSOP)
8 PINS
176.7
63.9
DBV (SOT-23)
5 PINS
206.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
74
121.8
62
99.4
65.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19.7
54.8
N/A
8.8
39.0
ΨJB
97.6
65.6
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2202
OPA2202
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
180.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
68.3
101.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.5
ΨJB
99.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4202
OPA4202
THERMAL METRIC(1)
D (SOIC)
14 PINS
87.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
42.7
44.6
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.9
ΨJB
44.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2020, Texas Instruments Incorporated
7
OPA202, OPA2202, OPA4202
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
www.ti.com.cn
6.7 Electrical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, and VOUT = VS / 2, RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = ±18 V
VS = ±18 V, TA = –40°C to +105°C
±20
±200
±250
±1
VOS
Input offset voltage
µV
OPA202, OPA4202ID
OPA2202IDGK
TA = –40°C to +105°C
TA = –40°C to +105°C
±0.5
±0.5
±0.1
µV/°C
µV/°C
dVOS/dT
PSRR
Input offset voltage drift
±1.5
±0.5
±0.5
VS = ±2.25 V to ±18 V
Input offset voltage
versus power supply
µV/V
VS = ±2.25 V to ±18 V, TA = –40°C to +105°C
INPUT BIAS CURRENT
±0.25
±15
±2
±2.1
IB
Input bias current
nA
TA = –40°C to +105°C
±150
±700
±250
±700
OPA202
TA = –40°C to +105°C
IOS
Input offset current
pA
±25
OPA2202IDGK,
OPA4202ID
TA = –40°C to +105°C
NOISE
0.2
0.03
9.5
µVPP
Input voltage noise
f = 0.1 Hz to 10 Hz
µVRMS
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 1 kHz
Input voltage noise
density
en
in
9.1
nV/√Hz
pA/√Hz
9
Input current noise
0.076
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
(V–) + 1.5
114
(V+) – 1.5
V
(V–) + 1.5 V < VCM < (V+) – 1.5 V
131
148
VS = ±2.25 V
VS = ±18 V
(V–) + 1.5 V < VCM < (V+) – 1.5 V,
TA = –40°C to +105°C
114
Common-mode rejection
ratio
CMRR
dB
(V–) + 1.5 V < VCM < (V+) – 1.5 V
126
(V–) + 1.5 V < VCM < (V+) – 1.5 V,
TA = –40°C to +105°C
119
INPUT CAPACITANCE
Differential
10 || 3.3
3 || 0.5
MΩ || pF
TΩ || pF
Common-mode
OPEN-LOOP GAIN
(V–) + 1.25 V ≤ VO ≤ (V+) – 1.25 V,
RL = 10 kΩ
120
119
126
126
120
119
126
126
135
150
133
150
VS = ±2.25 V
VS = ±18 V
VS = ±2.25 V
VS = ±18 V
(V–) + 1.25 V ≤ VO ≤ (V+) – 1.25 V,
RL = 10 kΩ, TA = –40℃ to +105℃
(V–) + 1.25 V ≤ VO ≤ (V+) – 1.25 V,
RL = 10 kΩ
(V–) + 1.25 V ≤ VO ≤ (V+) – 1.25 V,
RL = 10 kΩ, TA = –40℃ to +105℃
AOL
Open-loop voltage gain
dB
(V–) + 1.25 V ≤ VO ≤ (V+) – 1.25 V,
RL = 2 kΩ
(V–) + 1.25 V ≤ VO ≤ (V+) – 1.25 V,
RL = 2 kΩ, TA = –40℃ to +105℃
(V–) + 1.25 V ≤ VO ≤ (V+) – 1.25 V,
RL = 2 kΩ
(V–) + 1.25 V ≤ VO ≤ (V+) – 1.25 V,
RL = 2 kΩ, TA = –40℃ to +105℃
8
Copyright © 2017–2020, Texas Instruments Incorporated
OPA202, OPA2202, OPA4202
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ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
Electrical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, and VOUT = VS / 2, RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
1
0.35
30
MHz
V/µs
Slew rate
10-V step, G = 1
To 0.1%, 10-V step , G = 1
To 0.01%, 10-V step , G = 1
VIN × gain > VS
tS
Settling time
µs
µs
32
Overload recovery time
4
Total harmonic distortion
+ noise
THD+N
VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ
0.0002%
OUTPUT
TA = 25°C, No Load
650
800
750
900
1.15
1
mV
V
TA = 25°C, RL = 10 kΩ
TA = 25°C, RL = 2 kΩ
1.05
Voltage output swing
from rail
VS = ±18 V
TA = –40°C to +105°C, RL = 10 kΩ
AOL > 120 dB, RL = 10 kΩ
AOL > 120 dB, RL = 2 kΩ
1.05
1.25
Sinking
35
35
ISC
Short-circuit current
Capacitive load drive
mA
Ω
Sourcing
CLOAD
ZO
图 28
Open-loop output
impedance
IO = 0 mA, f = 1 MHz; see 图 27
50
POWER SUPPLY
IO = 0 mA
580
800
900
Quiescent current per
amplifier
IQ
µA
IO = 0 mA, TA = –40°C to +105°C
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6.8 Typical Characteristics
表 1. Table of Graphs
DESCRIPTION
Offset Voltage Production Distribution
Offset Voltage Drift Distribution From –40°C to +105°C
Input Bias Current Production Distribution
Input Offset Current Production Distribution
Offset Voltage vs Temperature
FIGURE
图 1
图 2
图 3
图 4
图 5
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Supply Voltage
图 6
图 7
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
图 8
图 9
Input Bias Current vs Common-Mode Voltage
Input Bias Current and Offset vs Temperature
Output Voltage Swing vs Output Current
Output Voltage Swing vs Output Current (Sourcing)
Output Voltage Swing vs Output Current (Sinking)
CMRR and PSRR vs Frequency
图 10
图 11
图 12
图 13
图 14
图 15
图 16
图 17
图 18
图 19
图 20
图 21
图 22
图 23
图 24
图 25, 图 26
图 27
图 28
图 29
图 30
图 31
图 32, 图 33
图 34, 图 35
图 36
图 37
图 38
图 39
CMRR vs Temperature
PSRR vs Temperature
0.1-Hz to 10-Hz Voltage Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open-Loop Gain vs Temperature (10-kΩ)
Open-Loop Gain vs Output Voltage Swing to Supply
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
No Phase Reversal
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (10-mV Step)
Large-Signal Step Response (10-V Step)
Settling Time (10-V Step)
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
10
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ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
6.9 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
20
15
10
5
30
25
20
15
10
5
0
0
Input Offset Voltage Drift (µV/°C)
σ = 177.41 nV/°C
Input Offset Voltage (µV)
C001
C002
µ = –18.23 nV/°C
N = 252
µ = –3.56 µV
σ = 32.09 µV
N = 252
TA = –40°C to +105°C
图 2. Offset Voltage Drift Distribution
图 1. Offset Voltage Production Distribution
œIN Bias Current
35
30
25
20
15
10
5
20
16
12
8
4
0
4
8
12
16
20
+IN Bias Current
0
Input Offset Current (pA)
Input Bias Current (pA)
C013
C013
µ = 0.112 pA
σ = 15.023 pA
N = 90
µ–IN = 112.335 pA
µ+IN = 112.448 pA
σ–IN = 154.946 pA
σ+IN = 152.739 pA
N = 90
图 4. Input Offset Current Production Distribution
图 3. Input Bias Current Production Distribution
400
300
120
80
40
200
100
0
0
œ100
œ200
œ300
œ400
œ40
œ80
œ120
VCM = 16.5 V
VCM = œ 16.5 V
œ15 œ10 œ5
0
25
50
75
100 125 150
0
5
10
15
20
œ75 œ50 œ25
œ20
Temperature (°C)
Input Common-mode Voltage (V)
C001
C003
5 typical units
图 5. Offset Voltage vs Temperature
5 typical units
图 6. Offset Voltage vs Common-Mode Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
150
100
50
120
100
80
180
150
120
90
Magnitude
VS = 4.5 V
60
0
40
60
Phase
œ50
œ100
œ150
20
30
0
0
œ20
-30
10M
0
9
18
27
36
1
10
100
1k
10k
100k
1M
Supply Voltage (V)
Frequency (Hz)
C001
C022
5 typical units
图 7. Offset Voltage vs Supply Voltage
图 8. Open-Loop Gain and Phase vs Frequency
25
20
15
10
5
40
20
0
G = +1
G= -1
G= +10
0
œ5
œ10
œ15
œ20
œ25
-20
-40
100
1k
10k
100k
1M
10M
0
5
10
15
20
œ20
œ15
œ10
œ5
Frequency (Hz)
Input Common-mode Voltage (V)
C004
C001
图 9. Closed-Loop Gain vs Frequency
图 10. Input Bias Current vs Common-Mode Voltage
1.0
0.8
10V
125°C
85°C
25°C
-40°C
0.5
IBN
0.3
1V
0.0
IBP
œ0.3
œ0.5
IOS
100mV
0
25
50
75
100 125 150
1
10
100
œ75 œ50 œ25
Temperature (°C)
Output Current (mA)
C001
C019
图 11. Input Bias Current and Offset vs Temperature
图 12. Output Voltage Swing vs Output Current
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
18
17.5
17
-14
-14.5
-15
85°C
125°C
25°C
œ40°C
16.5
16
-15.5
-16
15.5
15
-16.5
-17
25°C
40
85°C
125°C
14.5
14
-17.5
-18
œ40°C
0
5
10
15
20
25
30
35
45
50
0
5
10
15
20
25
30
35
40
45
50
Output Current (mA)
Output Current (mA)
C001
C001
图 13. Output Voltage Swing vs Output Current (Sourcing)
图 14. Output Voltage Swing vs Output Current (Sinking)
160
150
140
130
120
110
100
0.01
0.1
1
160
CMRR
140
+PSRR
120
œPSRR
100
80
60
40
20
0
10
1
10
100
1k
10k
100k
1M
10M
0
25
50
75 100 125 150
œ75 œ50 œ25
Frequency (Hz)
Temperature (°C)
C004
C001
图 15. CMRR and PSRR vs Frequency
图 16. CMRR vs Temperature
160
150
140
130
120
0.01
0.1
1
Time (1 s/div)
0
25
50
75 100 125 150
œ75 œ50 œ25
Temperature (°C)
C001
C017
图 17. PSRR vs Temperature
图 18. 0.1-Hz to 10-Hz Voltage Noise
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1000
100
10
1000
100
10
1
-40
G = -1, 2-kꢀ Load
G = -1, 600-ꢀ Load
G = -1, 10-kꢀ Load
G = +1, 2-kꢀ Load
G = +1, 600-ꢀ Load
G = +1, 10-kꢀ Load
Current Noise
0.1
-60
0.01
-80
0.001
0.0001
0.00001
-100
-120
-140
Voltage Noise
1
1
0.01 0.1
1.0 10.0 100.0 1k
Frequency (Hz)
10k 100k 1M
20
200
2k
20k
Frequency (Hz)
C002
C004
VOUT = 3.5 VRMS
BW = 90 kHz
图 19. Input Voltage Noise Spectral Density vs Frequency
图 20. THD+N Ratio vs Frequency
700
600
500
400
300
200
100
0.1
-60
0.01
-80
0.001
-100
-120
-140
VS = 4.5 V
G = -1, 600-ꢀ Load
G = -1, 2-kꢀ Load
G = -1, 10-kꢀ Load
G = +1, 600-ꢀ Load
G = +1, 2-kꢀ Load
G = +1, 10-kꢀ Load
0.0001
0.00001
0
0
0.001
0.01
0.1
1
10
9
18
27
36
Output Amplitude (VRMS
)
Supply Voltage (V)
C004
C001
f = 1 kHz
BW = 90 kHz
图 21. THD+N vs Output Amplitude
图 22. Quiescent Current vs Supply Voltage
1000
900
800
700
600
500
400
300
200
100
0
180
170
160
150
140
130
120
110
100
0.001
VS
=
18 V
0.01
0.1
1
VS
=
18 V
VS
=
2.25 V
VS
=
2.25 V
10
0
25
50
75
100 125 150
0
25
50
75
100 125 150
œ75 œ50 œ25
œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
图 23. Quiescent Current vs Temperature
图 24. Open-Loop Gain vs Temperature
(With 10-kΩ Load)
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
140
120
100
80
140
120
100
80
60
60
40
0
0.5
1
1.5
2
0
0.5
1
1.5
Output Voltage Swing from Rail (V)
Output Voltage Swing from Rail (V)
C001
C001
VS = ±18 V
VS = ±2.25 V
图 25. Open-Loop Gain vs Output Voltage
图 26. Open-Loop Gain vs Output Voltage Swing to Supply
Swing to Supply
1k
100
10
50
G = -1, RISO = 0
G = -1, RISO = 25
G = -1, RISO = 50
G = +1, RISO = 0
G = +1, RISO = 25
G = +1, RISO = 50
45
40
35
30
25
20
15
10
5
0
1
10
100
1k
10k 100k
1M
10M 100M
25
250
2500
25000
Frequency (Hz)
C021
Capacitive Load (pF)
10-mV step
C004
Unity-gain bandwidth = 1 MHz
图 27. Open-Loop Output Impedance vs Frequency
图 28. Small-Signal Overshoot vs Capacitive Load
VOUT
VIN
Time (1 ms/div)
Time (2 µs/div)
C017
C017
图 29. No Phase Reversal
图 30. Positive Overload Recovery
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
VIN
VOUT
Input
Output
Time (25 µs/div)
Time (2 µs/div)
C017
C017
C017
C017
G = +1
图 32. Small-Signal Step Response (10-mV Step)
图 31. Negative Overload Recovery
Output
Input
Input
Output
Time (25 µs/div)
Time (10 µs/div)
C017
G = –1
G = –1
10-V step
图 33. Small-Signal Step Response (10-mV Step)
图 34. Large-Signal Step Response
.01% Settling = ±1 mV
Output
Input
Time (10 µs/div)
Time (5 µs/div)
C017
G = +1
10-V step
10-V step
图 35. Large-Signal Step Response
图 36. Settling Time
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
50
40
Maximum output voltage without
slew-rate induced distortion.
Sinking
35
30
25
20
15
10
5
40
30
20
10
0
VS
=
18 V
Sourcing
VS
=
2.25 V
0
100
1k
10k
100k
1M
0
25
50
75
100
125
150
œ75
œ50
œ25
Frequency (Hz)
Temperature (°C)
C001
C001
图 37. Short-Circuit Current vs Temperature
图 38. Maximum Output Voltage Amplitude vs Frequency
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1000M
C004
PRF = –10 dBm
图 39. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPA202, OPA2202, and OPA4202 (OPAx202) family of devices is a series of low-power, super-beta, bipolar
junction transistor (super-β BJT), input amplifiers that features superior drift performance and low input bias
current. The low output impedance and heavy capacitive load drive abilities allow designers to interface to
modern, fast-acquisition, precision analog-to-digital converters (ADCs) and buffer precision voltage references
and drive power supply decoupling capacitors. The OPAx202 achieve a 1-MHz gain-bandwidth product and a
0.35-V/μs slew rate, and consumes only 580 µA (typical) of quiescent current, making the devices a great choice
for low-power applications. These devices operate on a single 4.5-V to 36-V supply, or dual ±2.25-V to ±18-V
supplies.
All versions are fully specified from –40°C to +105°C for use in the most challenging environments. The single-
channel OPA202 is available in 8-pin SOIC, 8-pin VSSOP, and 5-pin SOT-23 packages. The dual-channel
OPA2202 is available in an 8-pin VSSOP package. The quad-channel OPA4202 is available in a 14-pin SOIC
package.
The Functional Block Diagram shows the simplified diagram of the OPAx202.
7.2 Functional Block Diagram
V+
gm1
OUT
+IN
œIN
Vœ
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7.3 Feature Description
7.3.1 Capacitive Load and Stability
The dynamic characteristics of the OPAx202 are optimized for commonly encountered gains, loads, and
operating conditions. The OPAx202 feature a patented output stage capable of driving large capacitive loads. In
a unity-gain configuration, the series is capable of directly driving to 25 nF of pure capacitive load. Increase the
gain to enhance the ability of the devices to drive greater capacitive loads. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier is stable in operation.
The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier,
and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the
output. Add a small resistor (ROUT equal to 50 Ω, for example) in series with the output to achieve isolation. 图 40
shows the effects on small-signal overshoot for several capacitive loads and combinations of isolation resistance.
See the Feedback Plots Define Op Amp AC Performance application bulletin for details of analysis techniques
and application circuits, available for download from the www.TI.com. By using isolation resistors, driving
capacitive loads of 100 nF and beyond is possible.
50
G = -1, RISO = 0
45
G = -1, RISO = 25
40
G = -1, RISO = 50
35
G = +1, RISO = 0
G = +1, RISO = 25
G = +1, RISO = 50
30
25
20
15
10
5
0
25
250
2500
25000
Capacitive Load (pF)
C004
图 40. Small-Signal Overshoot vs Capacitive Load (10-mV Output Step)
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Feature Description (接下页)
For additional drive capability in unity-gain configurations, insert a small (10 Ω to 20 Ω) resistor (RISO) in series
with the output to improve capacitive load drive, as shown in 图 41. This resistor reduces ringing and maintains
dc performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then
a voltage divider is created, which introduces a gain error at the output and reduces the output swing. The error
is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive
makes the OPAx202 a great choice for applications such as reference buffers, MOSFET gate drives, and cable-
shield drives. The circuit shown in 图 41 uses an isolation resistor (RISO) to stabilize the output of an op amp.
RISO modifies the open-loop gain of the system for increased phase margin. 表 2 lists the results using the
OPAx202. For additional information on techniques to optimize and design using this circuit, TI Precision Design
TIPD128 details complete design goals, simulation, and test results.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
图 41. Extending Capacitive Load Drive With the OPAx202
表 2. OPAx202 Capacitive Load Drive Solution Using Isolation Resistor Measured Results
MEASURED OVERSHOOT (%)
PARAMETER
INVERTING CONFIGURATION
NONINVERTING CONFIGURATION
CLOAD (pF)
31
RISO = 0 Ω
RISO = 25 Ω
6.6
RISO = 50 Ω
RISO = 0 Ω
RISO = 25 Ω
9
RISO = 50 Ω
8.6
6.7
6.4
6.7
6.1
6.4
6.1
8.1
14.9
21.8
29.4
37
6.6
6.7
9.3
8.9
9.4
8.9
251
6.4
8.9
421
6.3
6.6
8.8
8.8
8.7
641
6.3
6.5
8.1
8.8
8.5
1079
1539
2579
3949
6269
10139
15729
25069
6.1
6.4
8.6
8.7
9.8
6.3
6.1
8.9
10.3
13.3
16
10.1
12
6.3
6.9
16
7.9
8.3
25
14.1
14.5
15.4
14.5
13.9
10.8
13.5
15.2
16.5
9.9
33.1
40.2
46.2
52.6
18.1
19.1
19.6
19.2
10.8
11.6
12.3
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results,
see TIPD128, Capacitive Load Drive Solution Using an Isolation Resistor verified reference design.
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7.3.2 Output Current Limit
The output current of the OPAx202 is limited by internal circuitry to ±35 mA (sinking or sourcing) to protect the
device if the output is accidentally shorted. This short-circuit current depends on temperature, as 图 37 shows.
7.3.3 Noise Performance
图 42 shows the total circuit noise for varying source impedances with the operational amplifier in a unity-gain
configuration (with no feedback resistor network and therefore no additional noise contributions). The OPAx202
and OPA211 are shown with total circuit noise calculated. The op amp itself contributes a voltage noise
component and a current noise component. The voltage noise is commonly modeled as a time-varying
component of the offset voltage. The current noise is modeled as the time-varying component of the input bias
current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest noise
op amp for a given application depends on the source impedance. For low source impedance, current noise is
negligible and voltage noise dominates. The OPAx202 have both low voltage noise and low current noise
because of the super-beta bipolar junction transistor (super-β BJT) input of the op amp. As a result, the current
noise contribution of the OPAx202 is negligible for most practical source impedances, which makes the series
the better choice for applications with high source impedance.
The equation in 图 42 shows the calculation of the total circuit noise with these parameters:
•
•
•
•
•
en = voltage noise
In = current noise
RS = source impedance
k = Boltzmann's constant = 1.38 × 10–23 J/K
T = temperature in kelvins (K)
For more details on calculating noise, see Basic Noise Calculations.
10µ
OPA211
1µ
100n
10n
OPA202
1n
RS = 6 kΩ
Resistor Noise
100 1k
0.1n
1
10
10k
100k
1M
10M
Source Resistance, RS (Ω)
C003
NOTE: For source resistances (RS) greater than 6 kΩ, the OPAx202 is a lower-noise option compared to the
OPA211, as shown in 图 42.
图 42. Noise Performance of the OPAx202 vs the OPA211 in a Unity-Gain Buffer Configuration
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7.3.4 Phase-Reversal Protection
The OPAx202 family has internal phase-reversal protection. Many FET- and bipolar-input op amps exhibit a
phase reversal when the input is driven beyond its linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input circuitry of the OPAx202 prevents phase reversal
with excessive common-mode voltage; instead, the output limits into the appropriate rail (see 图 29).
7.3.5 Thermal Protection
The OPAx202 family of op amps is capable of driving 2-kΩ loads with power-supply voltages of up to ±18 V
across the specified temperature range. In a single-supply configuration, where the load is connected to the
negative supply voltage, the minimum load resistance is 1.1 kΩ at a supply voltage of 36 V. For lower supply
voltages (either single-supply or symmetrical supplies), a lower load resistance may be used as long as the
output current does not exceed 35 mA; otherwise, the device short-circuit current protection circuit may activate.
Internal power dissipation increases when operating at high supply voltages. Copper leadframe construction
used in the OPAx202 devices improves heat dissipation. Printed-circuit-board (PCB) layout helps reduce a
possible increase in junction temperature. Wide copper traces help dissipate the heat by acting as an additional
heat sink. An increase in temperature is further minimized by soldering the devices directly to the PCB rather
than using a socket.
Although the output current is limited by internal protection circuitry, accidental shorting of one or more output
channels of a device can result in excessive heating. For instance, when an output is shorted to midsupply, the
typical short-circuit current of 35 mA leads to an internal power dissipation of over 600 mW at a supply of ±18 V.
To prevent excessive heating, the OPAx202 have an internal thermal shutdown circuit that shuts down the
device if the die temperature exceeds approximately 135°C. When this thermal shutdown circuit activates, a built-
in hysteresis of 10°C makes sure that the die temperature drops to approximately 125°C before the device
switches on again. Additional consideration must be given to the combination of maximum operating voltage,
maximum operating temperature, load, and package type.
7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and the relevance to an electrical overstress
event. See 图 43 for an illustration of the ESD circuits contained in the OPAx202 (indicated by the dashed line
area). The ESD protection circuitry involves several current-steering diodes connected from the input and output
pins and routed back to the internal power-supply lines, where they meet at an absorption device internal to the
operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse as the pulse discharges through a semiconductor device. The ESD protection circuits are designed
to provide a current path around the operational amplifier core to protect the core from damage. The energy
absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the
OPAx202 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device
quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (such as the one 图 43 shows), the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occurs, there is a risk that some of the internal ESD protection circuits may be biased on and
conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption
device.
22
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图 43 shows a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V.
It depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the supplies
appear as high impedance, then the operational amplifier supply current may be supplied by the input source
through the current steering diodes. This state is not a normal bias condition; the amplifier most likely does not
operate normally. If the supplies are low impedance, then the current through the steering diodes can become
quite high. The current level depends on the ability of the input source to deliver current, and any resistance in
the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be
added to the supply pins as shown in 图 43. The Zener voltage must be selected such that the diode does not
turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin rises above
the safe operating supply voltage level.
TVS(2)
RF
+VS
V+
RI
100 ꢀ
100 ꢀ
ESD Current-
Steering Diodes
-IN
OUT
Op Amp
Core
(3)
RS
+IN
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
Vœ
-VS
TVS(2)
Copyright © 2017, Texas Instruments Incorporated
(1) VIN = +VS + 500 mV.
(2) TVS: +VS(max) > VTVSBR (Min) > +VS
(3) Suggested value is approximately 5 kΩ in overvoltage conditions.
图 43. Equivalent Internal ESD Circuitry in a Typical Application Circuit
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23
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7.3.7 EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a
higher EMIRR and is quantified by a decibel value. Measuring EMIRR is performed in many ways, but this
section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
•
•
•
Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit matching EMIRR
performance
EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input pin
with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier may result in adverse
effects, as the amplifier does not have sufficient loop gain to correct for signals with spectral content outside
the bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected DC
offsets, transient voltages, or other unknown behavior. Take care to properly shield and isolate sensitive
analog nodes from noisy radio signals and digital clocks and interfaces. shows the effect of conducted EMI to
the power supplies on the input offset voltage of OPAx202.
The EMIRR IN+ of the OPAx202 is plotted versus frequency, as shown in 图 44. If available, any dual and
quad op-amp device versions have similar EMIRR IN+ performance. The OPAx202 unity-gain bandwidth is 1
MHz. EMIRR performance less than this frequency denotes interfering signals that fall within the op-amp
bandwidth.
See the EMI Rejection Ratio of Operational Amplifiers application report, available for download from
www.ti.com.
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1000M
C004
图 44. OPAx202 EMIRR IN+
24
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OPA202, OPA2202, OPA4202
www.ti.com.cn
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
表 3 lists the EMIRR IN+ values for the OPAx202 at particular frequencies commonly encountered in real-world
applications. 表 3 lists applications that may be centered on or operated near the particular frequency shown.
This information may be of special interest to designers working with these types of applications, or working in
other fields likely to encounter RF interference from broad sources, such as the industrial, scientific, and medical
(ISM) radio band.
表 3. OPAx202 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
41 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
47 dB
54 dB
67 dB
67 dB
81 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
7.3.8 EMIRR +IN Test Configuration
图 45 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the op amp
noninverting input pin using a transmission line. The op amp is configured in a unity-gain buffer topology with the
output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at the
op amp input causes a voltage reflection; however, this effect is characterized and accounted for when
determining the EMIRR IN+. The resulting DC offset voltage is sampled and measured by the multimeter. The
LPF isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
Ambient temperature: 25˘C
+VS
œ
50 ꢀ
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
-VS
Sample /
Averaging
Digital Multimeter
Not shown: 0.1 µF and 10 µF
supply decoupling
Frequency Sweep: 201 pt. Log
图 45. EMIRR +IN Test Configuration
7.4 Device Functional Modes
The OPAx202 have a single functional mode and are operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx202 is 36 V (±18 V).
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OPA202, OPA2202, OPA4202
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA202, OPA2202, and OPA4202 (OPAx202) are unity-gain stable operational amplifiers with low noise,
low input bias current, and low input offset voltage. Applications with noisy or high-impedance power supplies
require decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate.
Designers can use the low output impedance and heavy capacitive load drive abilities to interface to modern,
fast-acquisition, precision analog-to-digital converters (ADCs) and buffer precision voltage references and drive
power supply decoupling capacitors.
8.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources dominates in many
cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuit is
the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. 图 42 shows this function. The source impedance is usually fixed; consequently, select the op amp
and the feedback resistors to minimize the respective contributions to the total noise.
图 46 shows noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations
with gain, the feedback network resistors contribute noise. Typically, the current noise of the op amp reacts with
the feedback resistors to create additional noise components. However, the extremely low current noise of the
OPAx202 means that the current noise contribution is neglected.
The feedback resistor values are typically selected to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
26
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OPA202, OPA2202, OPA4202
www.ti.com.cn
ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
Application Information (接下页)
(A) Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
42
= l1 + p „ A5 + A0 + kA4 2 o + E0 „ 45 + lE0 „ d
41 „ 42
2
2
2
2
¨
:
: ;
1
;
:
;
:
;
>
?
84/5
'
1
hp
æ4
1
41
41 + 42
GND
œ
EO
8
: ;
2
A = 4 „ G$ „ 6(-) „ 45
d
h
¥
Thermal noise of RS
+
5
*V
¾
RS
41 „ 42
8
: ;
3
A4
= ¨4 „ G$ „ 6(-) „ d
2
h
d
h
Thermal noise of R1 || R2
æ4
1
41 + 42
*V
¾
+
,
h
VS
Source
GND
G$ = 1.38065 „ 10F23
: ;
4
d
œ
Boltzmann Constant
-
Temperature in kelvins
: ;
>
?
-
5
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
Noise at the output is given as EO, where
R1
R2
2
:
;
42
45 + 41 „ 42
'
1
= l1 +
p „ A0 2 + kA4
o2 + FE0 „ H
+4 æ4
5 2
IG
¨
: ;
6
:
;
>
84/5
?
1
45 + 41
45 + 41 + 42
RS
œ
EO
:
;
45 + 41 „ 42
8
+
: ;
7
¨
4 „ G$ „ 6(-) „ H
A4
=
I
d
h
Thermal noise of (R1 + RS) || R2
+4 æ4
5
1
2
45 + 41 + 42
*V
¾
+
VS
œ
,
GND
G$ = 1.38065 „ 10F23
d
h
: ;
8
Boltzmann Constant
Source
GND
-
: ;
9
>
?
6(-) = 237.15 + 6(°%)
-
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
(1) eN = the voltage noise of the amplifier = 9 nV/√Hz at 1 kHz.
(2) iN = the current noise of the amplifier = 76 fA/√Hz at 1 kHz.
(3) For additional resources on noise calculations, visit TI's Precision Labs.
图 46. Noise Calculation in Gain Configurations
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OPA202, OPA2202, OPA4202
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8.2 Typical Application
R4
2.94 kꢀ
C5
1 nF
œ
R1
590 ꢀ
R3
499 ꢀ
Output
+
Input
OPA202
C2
39 nF
Copyright © 2017, Texas Instruments Incorporated
图 47. 25-kHz, Low-Pass Filter
8.2.1 Design Requirements
Low-pass filters are used in signal processing applications to reduce noise and prevent aliasing. The OPAx202
devices are is designed to construct high-speed, high-precision active filters. 图 47 shows a second-order, low-
pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
•
•
•
Gain = 5 V/V (inverting gain)
Low-pass cutoff frequency = 25 kHz
Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in 图 47. Use 公式 1 to
calculate the voltage transfer function.
-1 R1R3C2C5
Output
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
Input
2
1
3
4
3 4 2 5
(1)
This circuit produces a signal inversion. For this circuit, the gain at DC and the low-pass cutoff frequency are
calculated by 公式 2:
R4
Gain =
R1
1
fC =
1 R R C C
(
3 4 2 5
)
2p
(2)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
28
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ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
Typical Application (接下页)
8.2.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
图 48. OPAx202 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
9 Power Supply Recommendations
The OPAx202 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +105°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown in the Typical Characteristics.
CAUTION
Supply voltages greater than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information, see The PCB is a component of op amp design.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close as possible to the device. As shown in 图 49, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
•
•
For best performance, TI recommends cleaning the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB
assembly to remove moisture introduced into the device packaging during the cleaning process. A low
temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
Place bypass
capacitors as close to
device as possible
(avoid use of vias)
Use ground pours for
shielding the input
signal pairs
GND
C3
C4
+V
R3
C3
C4
R3
INœ
+V
1
NC
œIN
+IN
Vœ
NC
V+
8
7
6
5
1
2
3
4
NC
œIN
+IN
Vœ
NC
V+
8
7
6
5
R1
R2
R1
2
3
4
INœ
œ
OUT
IN+
OUT
NC
OUT
OUT
NC
+
R2
-V
C1
C2
IN+
R4
GND
R4
-V
Place components
C1
C2
Use a low-
ESR,ceramic bypass
capacitor
close to device and to
each other to reduce
parasitic errors
Copyright © 2017, Texas Instruments Incorporated
图 49. Operational Amplifier Board Layout for Difference Amplifier Configuration
30
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OPA202, OPA2202, OPA4202
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ZHCSGW0E –OCTOBER 2017–REVISED FEBRUARY 2020
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 WEBENCH 滤波器设计器工具
WEBENCH® 滤波器设计器是一款简单、功能强大且便于使用的有源滤波器设计程序。借助 WEBENCH 滤波器设
计器，用户可使用精选 TI 运算放大器和 TI 供应商合作伙伴提供的无源组件来构建最佳滤波器设计方案。
11.1.1.3 TI 高精度设计
欲获取 TI 高精度设计，请访问 http://www.ti.com.cn/ww/analog/precision-designs/。TI 高精度设计是由 TI 公司高
精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选择、仿真、完整印刷电路板
(PCB) 电路原理图和布局布线、物料清单以及性能测量结果。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《运算放大器设计组件 PCB》
德州仪器 (TI)，《用直观方式补偿跨阻放大器》
德州仪器 (TI)，《运算放大器增益稳定性，第 3 部分：交流增益误差分析》
德州仪器 (TI)，《运算放大器增益稳定性，第 2 部分：直流增益误差分析》
德州仪器 (TI)，《在全差分有源滤波器中使用无限增益、MFB 滤波器拓扑》
德州仪器 (TI)，《运算放大器性能分析》
德州仪器 (TI)，《运算放大器的单电源运行》
德州仪器 (TI)，《放大器调优》
德州仪器 (TI)，《无铅组件涂层的储存寿命评估》
德州仪器 (TI)，《反馈曲线图定义运算放大器交流性能》
德州仪器 (TI)，《运算放大器的 EMI 抑制比》
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11.3 相关链接
表 4 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具与软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
立即订购
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
OPA202
OPA2202
OPA4202
11.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.5 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
32
版权 © 2017–2020, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA202ID
OPA202IDBVR
OPA202IDBVT
OPA202IDGKR
OPA202IDGKT
OPA202IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
D
DBV
DBV
DGK
DGK
D
8
5
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 120
-40 to 120
-40 to 120
-40 to 105
-40 to 105
-40 to 120
-40 to 150
-40 to 120
-40 to 120
-40 to 150
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA202
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
50 RoHS & Green
2500 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
1T72
5
1T72
8
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
1T2Q
8
1T2Q
8
OPA202
OP2202
1XDQ
OPA2202ID
SOIC
D
8
NIPDAU
OPA2202IDGKR
OPA2202IDGKT
OPA2202IDR
OPA4202ID
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
8
1XDQ
8
OP2202
OPA4202
OPA4202
OPA4202
OPA4202
SOIC
D
14
14
14
14
NIPDAU
OPA4202IDR
OPA4202IPW
OPA4202IPWR
SOIC
D
NIPDAU
TSSOP
TSSOP
PW
PW
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2023
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA202IDBVR
OPA202IDBVT
OPA202IDGKR
OPA202IDGKR
OPA202IDGKT
OPA202IDGKT
OPA202IDR
SOT-23
SOT-23
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
DGK
DGK
D
5
5
3000
250
180.0
180.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
8.4
3.23
3.23
5.3
5.3
5.3
5.3
6.4
5.3
5.3
5.3
5.3
6.4
6.5
6.9
3.17
3.17
3.4
3.4
3.4
3.4
5.2
3.4
3.4
3.4
3.4
5.2
9.0
5.6
1.37
1.37
1.4
1.4
1.4
1.4
2.1
1.4
1.4
1.4
1.4
2.1
2.1
1.6
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8.4
8.0
8
2500
2500
250
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
16.4
12.4
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
8
8
8
250
8
2500
2500
2500
250
OPA2202IDGKR
OPA2202IDGKR
OPA2202IDGKT
OPA2202IDGKT
OPA2202IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
250
8
2500
2500
2000
OPA4202IDR
SOIC
D
14
14
OPA4202IPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA202IDBVR
OPA202IDBVT
OPA202IDGKR
OPA202IDGKR
OPA202IDGKT
OPA202IDGKT
OPA202IDR
SOT-23
SOT-23
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
DGK
DGK
D
5
5
3000
250
213.0
213.0
366.0
366.0
366.0
366.0
356.0
366.0
366.0
366.0
366.0
356.0
356.0
356.0
191.0
191.0
364.0
364.0
364.0
364.0
356.0
364.0
364.0
364.0
364.0
356.0
356.0
356.0
35.0
35.0
50.0
50.0
50.0
50.0
35.0
50.0
50.0
50.0
50.0
35.0
35.0
35.0
8
2500
2500
250
8
8
8
250
8
2500
2500
2500
250
OPA2202IDGKR
OPA2202IDGKR
OPA2202IDGKT
OPA2202IDGKT
OPA2202IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
250
8
2500
2500
2000
OPA4202IDR
SOIC
D
14
14
OPA4202IPWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA202ID
OPA2202ID
OPA4202ID
OPA4202IPW
D
D
SOIC
SOIC
8
8
75
75
50
90
506.6
506.6
506.6
530
8
8
3940
3940
3940
3600
4.32
4.32
4.32
3.5
D
SOIC
14
14
8
PW
TSSOP
10.2
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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