OPA4277MDTEP [TI]
增强型产品高精度运算放大器 | D | 14 | -55 to 125;
| 型号： | OPA4277MDTEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品高精度运算放大器 | D | 14 | -55 to 125 放大器 运算放大器 |
| 文件： | 总25页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA4277-SP
SBOS771A –DECEMBER 2016–REVISED JANUARY 2019
OPA4277-SP Radiation Hardened High-Precision Operational Amplifier
The OPA4277-SP operates from ±2- to ±18-V
supplies with excellent performance. Unlike most
operational amplifiers which are specified at only one
1 Features
1
•
QMLV Qualified: 5962-16209
–
Radiation Hardness Assurance (RHA) up to
Total Ionizing Dose (TID) 50 krad(Si)
supply
voltage,
the
OPA4277-SP
precision
operational amplifier is specified for real-world
applications; a single limit applies over the ±5- to ±15-
V supply range. High performance is maintained as
the amplifier swings to the specified limits.
–
–
ELDRS-Free (See Radiation Report)
Single Event Latchup (SEL) Immune to LET =
85 MeV-cm2/mg
The OPA4277-SP is easy to use and free from phase
inversion and overload problems found in some
operational amplifiers. It is stable in unity gain and
provides excellent dynamic behavior over a wide
range of load conditions. The OPA4277-SP features
completely independent circuitry for lowest crosstalk
and freedom from interaction, even when overdriven
or overloaded.
•
•
•
•
•
•
•
•
Ultra-Low Offset Voltage: 20 µV
Ultra-Low Drift: ±0.15 µV/°C
High Open-Loop Gain: 134 dB
High Common-Mode Rejection: 140 dB
High-Power Supply Rejection: 130 dB
Wide Supply Range: ±2 to ±18 V
Low-Quiescent Current: 800 µA/Amplifier
Device Information(1)
Available in 14-lead CFP With Industry Standard
Quad Operational Amplifier Pinout
PART NUMBER
5962L1620901VYC
5962L1620901VXA
5962L1620901V9A
GRADE
PACKAGE
14-lead CFP (HFR)
28-lead CDIP (JDJ)
KGD(2)
50 krad(Si)
ELDRS-free
2 Applications
•
•
•
Space Satellite Temperature and Position Sensing
High-Accuracy Space Instrumentation
Engineering
Samples(3)
OPA4277HFR/EM
14-lead CFP (HFR)
Space Precision and Scientific Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
–
–
–
–
Transducer Amplifier
Bridge Amplifier
(2) KGD = known good die.
(3) These units are intended for engineering evaluation only.
They are processed to a noncompliant flow. These units are
not suitable for qualification, production, radiation testing or
flight use. Parts are not warrantied for performance over the
full MIL specified temperature range of –55°C to 125°C or
operating life.
Strain Gage Amplifier
Precision Integrator
3 Description
The OPA4277-SP precision operational amplifier
replaces the industry standard LM124-SP. It offers
improved noise and two orders of magnitude lower
input offset voltage. Features include ultra-low offset
voltage and drift, low-bias current, high common-
mode rejection, and high-power supply rejection.
Simplified Schematic
R2
R1
OPA4277-SP
No bias current
cancellation resistor
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA4277-SP
SBOS771A –DECEMBER 2016–REVISED JANUARY 2019
www.ti.com
Table of Contents
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
Power Supply Recommendations...................... 17
1
2
3
4
5
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
5.1 Bare Die Information................................................. 5
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions ...................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Typical Characteristics.............................................. 9
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
8
9
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1 Receiving Notification of Documentation Updates 19
11.2 Community Resources.......................................... 19
11.3 Trademarks........................................................... 19
11.4 Electrostatic Discharge Caution............................ 19
11.5 Glossary................................................................ 19
6
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Original (December 2016) to Revision A
Page
•
•
•
•
•
Changed Features section ..................................................................................................................................................... 1
Added new device packages.................................................................................................................................................. 1
Updated Pin Configurations and Functions section ............................................................................................................... 3
Updated Recommended Operating Conditions table............................................................................................................. 6
Updated Figure 3.................................................................................................................................................................... 9
2
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SBOS771A –DECEMBER 2016–REVISED JANUARY 2019
5 Pin Configuration and Functions
HFR Package
14-Pin CFP
Top View
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
–IN D
+IN D
V–
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
Not to scale
Pin Functions: CFP
PIN
I/O
DESCRIPTION
NO.
1
NAME
OUT A
–IN A
+IN A
V+
O
I
Output channel A.
2
Inverting input channel A.
Noninverting input channel A.
Positive (highest) power supply.
Noninverting input channel B.
Inverting input channel B.
Output channel B.
3
I
4
—
I
5
+IN B
–IN B
OUT B
OUT C
–IN C
+IN C
V–
6
I
7
O
O
I
8
Output channel C.
9
Inverting input channel C.
Noninverting input channel C.
Negative (lowest) power supply.
Noninverting input channel D.
Inverting input channel D.
Output channel D.
10
11
12
13
14
I
—
I
+IN D
–IN D
OUT D
I
O
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SBOS771A –DECEMBER 2016–REVISED JANUARY 2019
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JDJ Package
28-Pin CDIP
Top View
NC
OUT A
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
2
OUT D
NC
3
NC
4
NC
œIN A
+IN A
+VS
5
œIN D
+IN D
œVS
NC
6
7
NC
8
+IN B
œIN B
NC
9
œIN C
+IN C
NC
10
11
12
13
14
NC
NC
OUT B
NC
OUT C
NC
Not to scale
NC - no internal connection
Pin Functions: CDIP
PIN
I/O
DESCRIPTION
NO.
NAME
1, 3, 4, 8,
11, 12, 14,
15, 17, 18,
21, 25, 26,
28
NC
—
Not connected.
2
OUT A
–IN A
+IN A
+VS
O
I
Output (channel A).
5
Inverting input (channel A).
Noninverting input (channel A).
Positive (highest) power supply.
Inverting input (channel B).
Noninverting input (channel B).
Output (channel B).
6
I
7
—
I
9
+IN B
–IN B
OUT B
OUT C
+IN C
–IN C
–VS
10
13
16
19
20
22
23
24
27
I
O
O
I
Output (channel C).
Inverting input (channel C).
Noninverting input (channel C).
Negative (lowest) power supply.
Inverting input (channel D).
Noninverting input (channel D).
Output (channel D).
I
—
I
+IN D
–IN D
OUT D
I
O
4
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SBOS771A –DECEMBER 2016–REVISED JANUARY 2019
5.1 Bare Die Information
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
BOND PAD
THICKNESS
DIE THICKNESS
BACKSIDE FINISH
15 mils
Silicon with backgrind
Negative (lower) Power Supply
AlCu (0.5%)
990 to 1210 nm
Bond Pad Coordinates in Microns(1)
PAD
I/O
DESCRIPTION
X MIN
Y MIN
X MAX
Y MAX
NO.
1
NAME
OUT A
–IN A
+IN A
V+
O
I
Output channel A.
1791.042
1701.719
1701.719
1555.784
1706.752
1701.719
1796.074
3278.071
3362.361
3367.393
3407.651
3367.393
3362.361
3273.039
7290.340
6111.536
5326.505
4390.507
3462.057
2671.994
1498.222
1498.222
2671.994
3462.057
4391.765
5331.537
6111.536
7290.340
1901.751
1807.397
1812.429
1661.461
1807.397
1807.397
1896.719
3383.748
3473.071
3473.071
3513.329
3468.038
3468.038
3383.748
7401.049
6217.213
5437.215
4498.700
3562.702
2777.671
1598.867
1603.900
2782.704
3567.734
4497.442
5432.182
6217.213
7401.049
2
Inverting input channel A.
Noninverting input channel A.
Positive (higher) power supply.
Noninverting input channel B.
Inverting input channel B.
Output channel B.
3
I
4
—
I
5
+IN B
–IN B
OUT B
OUT C
–IN C
+IN C
V–
6
I
7
O
O
I
8
Output channel C.
9
Inverting input channel C.
Noninverting input channel C.
Negative (lower) power supply.
Noninverting input channel D.
Inverting input channel D.
Output channel D.
10
11
12
13
14
I
—
I
+IN D
–IN D
OUT D
I
O
(1) Substrate must be biased to V–, negative (lower) power supply.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
MAX
36
UNIT
V
Supply voltage = (V+) – (V–)
Input voltage
(V–) – 0.7
(V+) + 0.7
V
Output short circuit
Continuous
Operating temperature
Junction temperature
–55
125
150
300
125
°C
°C
°C
°C
Lead temperature (soldering, 10 s)
Storage temperature, Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±100
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Machine model (MM)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2
MAX
±18
±15
125
UNIT
Dual supply voltage
V
V
Tested supply voltage
±5
TJ
Operating junction temperature
–55
°C
6.4 Thermal Information
OPA4277-SP
THERMAL METRIC(1)
CDIP (JDJ)
28 PINS
66.3
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
19.3
26.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.1
ψJB
26.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6
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SBOS771A –DECEMBER 2016–REVISED JANUARY 2019
6.5 Electrical Characteristics
At TJ = 25°C, VS = ±5 V to ±15 V, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TJ = 25°C, pre- and post-irradiated
TJ = –55°C to 125°C, pre-irradiated
±20
±65
VOS
Input offset voltage
µV
±140
dVOS/dT
Input offset voltage temperature drift TJ = –55°C to 125°C, pre-irradiated
±0.15
0.2
µV/°C
vs time
µV/mo
vs power supply,
VS = ±2 V to ±18 V,
TJ = 25°C, pre- and post-irradiated
±0.3
±1
±1
PSRR
Input offset voltage
µV/V
µV/V
VS = ±2 V to ±18 V,
TJ = –55°C to 125°C
Channel separation
INPUT BIAS CURRENT
dc
0.1
TJ = –55°C to 125°C
±17.5
±17.5
±17.5
±17.5
IB
Input bias current
nA
nA
TJ = 25°C, pre- and post-irradiated
TJ = –55°C to 125°C
IOS
Input offset current
TJ = 25°C, pre- and post-irradiated
NOISE
Input voltage noise
ƒ = 0.1 to 10 Hz
ƒ = 10 Hz
0.22
12
8
µVpp
ƒ = 100 Hz
ƒ = 1 kHz
Input voltage noise density
Input noise current density
nV/√Hz
8
ƒ = 10 kHz
ƒ = 1 kHz
8
in
0.2
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage range
TJ = 25°C, pre- and post-irradiated
(V–) + 2
114
(V+) – 2
V
(V–) + 2 V < VCM < (V+) – 2 V,
TJ = 25°C, post-irradiated
140
CMRR
Common-mode rejection ratio
dB
(V–) + 2 V < VCM < (V+) – 2 V,
TJ = –55°C to 125°C
114
INPUT IMPEDANCE
Differential
Common mode
OPEN-LOOP GAIN
100 || 3
250 || 3
MΩ || pF
GΩ || pF
(V–) + 2 V < VCM < (V+) – 2 V
VO = (VO–) + 0.5 V to (VO+) – 1.2 V,
RL = 10 kΩ
140
134
VO = (VO–) + 1.5 V to (VO+) – 1.5 V,
RL = 2 kΩ, TJ = –55°C to 125°C
118
118
VO = (VO–) + 1.5 V to (VO+) – 1.5 V,
RL = 2 kΩ, TJ = 25°C,
pre- and post-irradiated
134
134
134
AOL
Open-loop voltage gain
dB
VO = (VO–) + 3.4 V to (VO+) – 3.4 V,
RL = 600 Ω, VS = ±7 V,
TJ = –55°C to 125°C
118
118
VO = (VO–) + 3.4 V to (VO+) – 3.4 V,
RL = 600 Ω, VS = ±7 V, TJ = 25°C,
pre- and post-irradiated
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Electrical Characteristics (continued)
At TJ = 25°C, VS = ±5 V to ±15 V, and RL = 2 kΩ (unless otherwise noted)
PARAMETER
FREQUENCY RESPONSE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GBW
SR
Gain-bandwidth product
Slew rate
1
0.8
MHz
V/µs
0.1%, 10-V step, VS = ±15 V, G = 1
0.01%, 10-V step, VS = ±15 V, G = 1
1 kHz, G = 1, VO = 3.5 Vrms
14
Settling time
µs
16
THD + N
Total harmonic distortion + noise
0.002%
OUTPUT
RL = 10 kΩ, TJ = 25°C,
pre- and post-irradiated
(V–) + 0.5
(V–) + 0.5
(V–) + 1.5
(V–) + 1.5
(V–) + 3.4
(V+) – 1.2
(V+) – 1.2
(V+) – 1.5
(V+) – 1.5
(V+) – 3.4
RL = 10 kΩ, TJ = –55°C to 125°C
RL = 2 kΩ, TJ = 25°C,
pre- and post-irradiated
VO
Output voltage
V
RL = 2 kΩ, TJ = –55°C to 125°C
TJ = 25°C, RL = 600 Ω,
pre- and post-irradiated
RL = 600 Ω, VS = ±7 V,
TJ = –55°C to 125°C
(V–) + 3.4
(V+) – 3.4
ISC
Short-circuit current
Capacitive load drive
±35
mA
CLOAD
ƒ = 350 kHz, IO = 0
See Typical Characteristics
POWER SUPPLY
TJ = –55°C to 125°C
±5
±5
±2
±2
±7
±7
±7
±7
±15
±15
±18
±18
VS
VS
Specified voltage
V
V
TJ = 25°C, pre- and post-irradiated
TJ = –55°C to 125°C
Operating voltage
TJ = 25°C, pre- and post-irradiated
IO = 0, TJ = 25°C,
pre- and post-irradiated
±790
±850
±900
IQ
Quiescent current per amplifier
µA
IO = 0, TJ = –55°C to 125°C
8
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SBOS771A –DECEMBER 2016–REVISED JANUARY 2019
6.6 Typical Characteristics
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, pre-irradiated (unless otherwise noted).
140
120
100
80
140
120
100
80
G
CL = 0
0
CL = 1500 pF
+PSR
–PSR
–30
–60
–90
–120
–150
–180
φ
60
CMR
60
40
40
20
20
0
0
–20
0.1
1
10
100
1k
10k
100k
1M
0.1
1
10
100
1k
10k 100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 2. Power Supply and Common-Mode Rejection vs
Frequency
Figure 1. Open-Loop Gain/Phase vs Frequency
INPUT NOISE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
1000
Current Noise
100
Voltage Noise
10
1
1 s/div
Noise signal is bandwidth limited to lie between 0.1 Hz and 10 Hz.
0.1
1
10
Frequency (Hz)
100
1k
Figure 4. Input Noise Voltage vs Time
Figure 3. Input Noise and Current Noise Spectral Density vs
Frequency
1
140
120
100
80
0.1
G = 10, RL = 2 kΩ, 10 kΩ
0.01
G = 1, RL = 2 kΩ, 10 kΩ
60
0.001
40
10
100
1k
10k
100k
10
100
1k
Frequency (Hz)
G = 1, measured channel A to D or B to C.
10k
100k
1M
Frequency (Hz)
VOUT = 3.5 Vrms
Other combinations yield similar or improved rejection.
Figure 6. Total Harmonic Distortion + Noise vs Frequency
Figure 5. Channel Separation vs Frequency
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, pre-irradiated (unless otherwise noted).
5
160
150
140
130
120
110
100
4
3
CMR
AOL
2
1
0
PSR
–1
–2
–3
–4
–5
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Curves represent typical production units.
Figure 8. Input Bias Current vs Temperature
Figure 7. AOL, CMR, PSR vs Temperature
100
90
80
70
60
50
40
30
20
10
0
1000
950
900
850
800
750
700
650
600
550
500
2.0
1.5
1.0
IQ
0.5
0.0
VCM = 0 V
–ISC
+ISC
–0.5
–1.0
–1.5
–2.0
–75
–50
–25
0
25
50
75
100
125
0
5
10
15
20
25
30
35
40
Temperature (°C)
Supply Voltage (V)
Curve shows normalized change in bias current with respect to VS
= ±10 V (+20 V). Typical IB may range from –0.5 nA to 0.5 nA at
VS = ±10 V.
Figure 10. Change in Input Bias Current vs Power Supply
Voltage
Figure 9. Quiescent Current and Short-Circuit Current vs
Temperature
2.0
1.5
1.0
1000
900
800
700
600
500
VS
= 5 V
0.5
0.0
–0.5
–1.0
–1.5
–2.0
VS
= 15 V
–15
–10
–5
0
5
10
15
0
5
10
15
20
Common-Mode Voltage (V)
Supply Voltage (V)
Curve shows normalized change in bias current with respect to
VCM = 0 V. Typical IB may range from –0.5 nA to 0.5 nA at
VCM = 0 V.
Per amplifier
Figure 11. Change in Input Bias Current vs Common-Mode
Voltage
Figure 12. Quiescent Current vs Supply Voltage
10
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, pre-irradiated (unless otherwise noted).
30
25
20
15
10
5
100
VS
= 15 V
50
0.01%
0.1%
20
10
VS
= 5 V
0
1k
10k
100k
1M
1
10
Gain (V/V)
100
Frequency (Hz)
10-V step
CL = 1500 pF
Figure 14. Maximum Output Voltage vs Frequency
Figure 13. Settling Time vs Closed-Loop Gain
60
50
40
30
20
10
0
(V+)
Gain = –1
(V+) – 1
(V+) – 2
(V+) – 3
(V+) – 4
(V+) – 5
–55°C
125°C
Gain = +1
25°C
(V–) + 5
(V–) + 4
(V–) + 3
(V–) + 2
(V–) + 1
(V–)
25°C
125°C
Gain = 10
–55°C
10
100
1k
10k
100k
0
5
10
15
20
25
30
Load Capacitance (pF)
Output Current (mA)
Figure 16. Small-Signal Overshoot vs Load Capacitance
Figure 15. Output Voltage Swing vs Output Current
10 µs/div
1 µs/div
G = 1
CL = 1500 pF
VS = ±15 V
G = 1
CL = 0 pF
VS = ±15 V
Figure 17. Large-Signal Step Response
Figure 18. Small-Signal Step Response
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, pre-irradiated (unless otherwise noted).
1 µs/div
G = 1
CL = 1500 pF
VS = ±15 V
Figure 19. Small-Signal Step Response
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7 Detailed Description
7.1 Overview
The OPA4277-SP precision operational amplifier replaces the industry standard LM124-SP. It offers improved
noise, wider output voltage swing, and is twice as fast with half the quiescent current. Features include ultra-low
offset voltage and drift, low bias current, high common-mode rejection, and high power supply rejection.
7.2 Functional Block Diagram
Vsupply+
Vin+
+
Vout
Vinœ
œ
Vsupplyœ
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7.3 Feature Description
The OPA4277-SP operates from ±2- to ±18-V supplies with excellent performance. Unlike most operational
amplifiers which are specified at only one supply voltage, the OPA4277-SP precision operational amplifier is
specified for real-world applications; a single limit applies over the ±5- to ±15-V supply range. High performance
is maintained as the amplifier swings to the specified limits. Because the initial offset voltage (±50-µV max) is so
low, user adjustment is usually not required.
7.3.1 Input Protection
The inputs of the OPA4277-SP are protected with 1-kΩ series input resistors and diode clamps. The inputs can
withstand ±30-V differential inputs without damage. The protection diodes conduct current when the inputs are
overdriven. This may disturb the slewing behavior of unity-gain follower applications, but will not damage the
operational amplifier.
1 kꢀ
+
1 kꢀ
œ
Figure 20. OPA4277-SP Input Protection
7.3.2 Input Bias Current Cancellation
The input stage base current of the OPA4277-SP is internally compensated with an equal and opposite
cancellation circuit. The resulting input bias current is the difference between the input stage base current and
the cancellation current. This residual input bias current can be positive or negative.
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Feature Description (continued)
When the bias current is canceled in this manner, the input bias current and input offset current are
approximately the same magnitude. As a result, it is not necessary to use a bias current cancellation resistor, as
is often done with other operational amplifiers (see Figure 21). A resistor added to cancel input bias current
errors may actually increase offset voltage and noise.
R2
R2
R1
R1
OPA4277-SP
Op Amp
RB = R2 || R1
No bias current
cancellation resistor
(see text)
(a)
(b)
Conventional op amp with external bias
current cancellation resistor.
OPA4277-SP with no external bias
current cancellation resistor.
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Figure 21. Input Bias Current Cancellation
7.4 Device Functional Modes
The OPA4277-SP has a single functional mode and is operational when the power-supply voltage, (V+) – (V–), is
less than 36 V.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA4277-SP is unity-gain stable and free from unexpected output phase reversal, making it easy to use in a
wide range of applications. Applications with noisy or high-impedance power supplies may require decoupling
capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
8.2 Typical Application
IREG ∼ 1 mA
5 V
14
12
1
V+
VLIN
1/4
IR1
13
4
11
VREG
VI+N
IR2
OPA4277-SP
10
V+
Type J
RF
10 kΩ
RG
RG
9
8
B
E
R
412 Ω
XTR105
1250 Ω
RF
10 kΩ
3
RG
VI–N
IO
1/4
2
7
1 kΩ
25 Ω
OPA4277-SP
IRET
IO = 4 mA + (VI+N – VI–N
)
40
V–
RG
6
50 Ω
RCM = 1250 Ω
2RF
R
(G = 1 +
= 50)
0.01 µF
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Figure 22. Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction
Compensation
8.2.1 Design Requirements
For the thermocouple low-offset, low-drift loop measurement with diode cold junction compensation shown in
Figure 22, a gain of 50 is desired.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
Equation 1 shows the equation used to determine the resistor values needed for a gain of 50. Table 1 lists the
design parameters.
2RF
G = 1 +
= 50
R
(1)
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
10 kΩ
RF
R
412 Ω
8.2.3 Application Curve
At TJ = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
35
30
25
20
15
10
5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Offset Voltage (µV/°C)
Typical distribution of packaged units. Single, dual, and quad included.
Figure 23. Warm-Up Offset Voltage Drift
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9 Power Supply Recommendations
OPA4277-SP operates from ±2- to ±18-V supplies with excellent performance. Unlike most operational amplifiers
which are specified at only one supply voltage, the OPA4277-SP is specified for real-world applications; a single
limit applies over the ±5- to ±15-V supply range. This allows a customer operating at VS = ±10 V to have the
same assured performance as a customer using ±15-V supplies. In addition, key parameters are assured over
the specified temperature range, –55°C to 125°C. Most behavior remains unchanged through the full operating
voltage range (±2 to ±18 V). Parameters which vary significantly with operating voltage or temperature are shown
in the typical performance curves.
10 Layout
10.1 Layout Guidelines
The leadframe die pad should be soldered to a thermal pad on the PCB. Mechanical drawings located in
Mechanical, Packaging, and Orderable Information show the physical dimensions for the package and pad.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
The OPA4277-SP has very-low offset voltage and drift. To achieve highest performance, optimize circuit layout
and mechanical conditions. Offset voltage and drift can be degraded by small thermoelectric potentials at the
operational amplifier inputs. Connections of dissimilar metals generate thermal potential, which can degrade the
ultimate performance of the OPA4277-SP. Cancel these thermal potentials by assuring that they are equal in
both input terminals.
•
•
•
Keep the thermal mass of the connections made to the two input terminals similar.
Locate heat sources as far as possible from the critical input circuitry.
Shield operational amplifier and input circuitry from air currents such as cooling fans.
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10.2 Layout Example
Figure 24. Board Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Jan-2019
PACKAGING INFORMATION
Orderable Device
5962L1620901V9A
5962L1620901VXA
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
XCEPT
KGD
0
50
Green (RoHS
& no Sb/Br)
Call TI
N / A for Pkg Type
ACTIVE
CDIP SB
JDJ
28
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962L1620901VX
A
OPA4277-SP
5962L1620901VYC
OPA4277HFR/EM
ACTIVE
ACTIVE
CFP
CFP
HFR
HFR
14
14
1
1
TBD
TBD
AU
AU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
25 to 25
5962L1620901VYC
OPA4277-SP
OPA4277HFR/EM
EVAL ONLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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26-Jan-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA4277-SP :
Catalog: OPA4277
•
Enhanced Product: OPA4277-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE OUTLINE
HFR0014A
CFP - 2.209 mm max height
S
C
A
L
E
1
.
0
0
0
CERAMIC FLATPACK
B
(7.09)
4X (R0.51)
6X 1.27
14
1
10.724
(9.58)
2X 7.62
10.224
7
8
0.482
8X
0.382
C A B
7.85
7.35
A
0.2
2.209 MAX
0.20
0.12
0.43 MAX
(5.498)
C
8
7
1
PIN 1 ID
14
25 MAX
4224229/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. The lid is not connected to any lead.
4. The leads are gold plated.
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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