OPA4325 [TI]
低噪声 (10nV/rtHz)、高带宽 (10MHz)、低功耗 (0.65mA)、四路零交叉运算放大器;
| 型号： | OPA4325 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低噪声 (10nV/rtHz)、高带宽 (10MHz)、低功耗 (0.65mA)、四路零交叉运算放大器 放大器 运算放大器 |
| 文件： | 总43页 (文件大小：3105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA325, OPA2325, OPA4325
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
OPAx325
精度、10MHz、低噪声、低功耗、RRIO、CMOS 运算放大器
1 特性
3 说明
1
•
零交叉失真时的精度：
OPA325、OPA2325 和 OPA4325 (OPAx325) 是精密
的低压互补金属氧化物半导体 (CMOS) 运算放大器，
经优化后具有极低噪声和高带宽，静态工作电流仅为
650μA。
–
–
–
低失调电压：150μV（最大值）
高共模抑制比 (CMRR)：114dB
轨至轨 I/O
•
•
•
•
•
•
•
高带宽：10MHz
OPAx325 具有零交叉失真的线性输入级，能够在整个
输入范围内提供 114dB（典型值）的出色共模抑制比
(CMRR)。共模输入范围将正负电源电压分别扩展了
100mV。输出电压摆幅通常在 10mV 电源轨内。
静态电流：650μA/每通道
单电源电压范围：2.2V 至 5.5V
低输入偏置电流：0.2pA
低噪声：10kHz 时为 9nV/√Hz
压摆率：5V/μs
OPAx325 同时拥有零交叉失真、高带宽 (10MHz)、高
压摆率 (5V/µs) 和低噪声 (9nV/√Hz) 等优秀特性，堪称
一款非常出色的逐次逼近寄存器 (SAR) 模数转换器
(ADC) 输入驱动放大器。此外，OPAx325 还具有
2.2V 至 5.5V 的宽电源电压范围，而且整个电源电压
范围内的电源抑制比 (PSRR) 都极为出色，因此该器
件非常适合不经稳压而直接由电池 供电的 高精度、低
功耗类应用。
单位增益稳定
2 应用
•
•
•
•
•
•
•
•
高阻抗传感器信号调节
跨阻放大器
测试和测量设备
可编程逻辑控制器 (PLC)
电机控制环路
OPA325（单通道版）采用 SOT23-5 封装。OPA2325
（双通道版）采用 SO-8 和 MSOP-8 封装。OPA4325
（四通道版）采用 TSSOP-14 封装。
通信
输入、输出 ADC 和 DAC 缓冲器
有源滤波器
器件信息(1)
器件型号
OPA325
封装
SOT-23 (5)
封装尺寸（标称值）
2.90mm × 1.60mm
4.90mm × 3.91mm
3.00mm × 3.00mm
5.00mm × 4.40mm
失调电压与输入共模电压间的关系
SOIC (8)
150
125
100
75
OPA2325
OPA4325
VSSOP (8)
TSSOP (14)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
50
25
可用作 ADC 驱动放大器的 OPAx325
3.3 V
0
œ25
œ50
œ75
VREF
R
VCM = œ2.85 V
œ100
ADC
VCM = 2.85 V
OPAx325
œ125
œ150
Input
+
VSS
VDD
5 V
C
0
1
2
3
œ3
œ2
œ1
VCM (V)
C003
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS637
OPA325, OPA2325, OPA4325
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
www.ti.com.cn
目录
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 20
Power Supply Recommendations...................... 25
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information: OPA325 .................................. 6
6.5 Thermal Information: OPA2325 ................................ 6
6.6 Thermal Information: OPA4325 ................................ 6
8
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
11 器件和文档支持 ..................................................... 27
11.1 文档支持................................................................ 27
11.2 相关链接................................................................ 27
11.3 接收文档更新通知 ................................................. 27
11.4 社区资源................................................................ 27
11.5 商标....................................................................... 27
11.6 静电放电警告......................................................... 27
11.7 Glossary................................................................ 27
12 机械、封装和可订购信息....................................... 27
6.7 Electrical Characteristics: VS = 2.2 V to 5.5 V or
±1.1 V to ±2.75 V ....................................................... 7
6.8 Typical Characteristics.............................................. 9
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (May 2019) to Revision D
Page
•
已添加 向数据表中添加了 OPA325 及相关内容 ..................................................................................................................... 1
Changes from Revision B (February 2019) to Revision C
Page
•
已更改 将 OPA4325 器件状态从预览更改为生产数据（正在供货）....................................................................................... 1
Changes from Revision A (July 2017) to Revision B
Page
•
•
•
已添加 向数据表中添加了 OPA4325 预告信息器件................................................................................................................ 1
Added operating temperature to Absolute Maximum Ratings table....................................................................................... 5
Deleted specified temperature from Absolute Maximum Ratings table; specified temperature already listed in
Recommended Operating Conditions table............................................................................................................................ 5
Changes from Original (October 2016) to Revision A
Page
•
•
已添加 针对双通道器件添加了新型 VSSOP 封装选项............................................................................................................ 1
已添加 针对 TI 参考设计添加了顶部导航图标......................................................................................................................... 1
2
Copyright © 2016–2019, Texas Instruments Incorporated
OPA325, OPA2325, OPA4325
www.ti.com.cn
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
5 Pin Configuration and Functions
OPA325: DBV Package
5-Pin SOT-23
Top View
OUT
Vœ
1
2
3
5
V+
+IN
4
œIN
Not to scale
Pin Functions: OPA325
PIN
I/O
DESCRIPTION
NAME
–IN
NO.
4
I
Inverting input
+IN
3
I
Noninverting input
OUT
V–
1
O
—
—
Output
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
OPA2325: D and DGK Packages
8-Pin SOIC, 8-Pin VSSOP
Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Pin Functions: OPA2325
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Output channel A
3
6
I
5
I
1
O
O
—
—
7
Output channel B
4
Negative supply
V+
8
Positive supply
Copyright © 2016–2019, Texas Instruments Incorporated
3
OPA325, OPA2325, OPA4325
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
www.ti.com.cn
OPA4325: PW Package
14-Pin TSSOP
Top View
OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
OUT D
œIN D
+IN D
Vœ
13
12
11
10
9
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
Pin Functions: OPA4325
PIN
I/O
DESCRIPTION
NAME
–IN A
NO.
2
I
I
Inverting input channel A
Noninverting input channel A
Inverting input channel B
Noninverting input channel B
Inverting input channel C
Noninverting input channel C
Inverting input channel D
Noninverting input channel D
Output channel A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
3
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output channel B
8
Output channel C
14
11
4
Output channel D
Negative supply
V+
Positive supply
4
Copyright © 2016–2019, Texas Instruments Incorporated
OPA325, OPA2325, OPA4325
www.ti.com.cn
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
VS = (V+) – (V–)
Voltage(2)
Current(2)
6
(V+) + 0.5
10
(V–) – 0.5
–10
V
Signal input pins
Output short-circuit(3)
mA
mA
Continuous
Operating, TA
Junction, TJ
Storage, Tstg
–40
150
150
150
Temperature
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2
NOM
MAX
5.5
UNIT
Single supply
Dual supply
VS
TA
Supply voltage
V
±1.1
–40
±2.75
125
Specified temperature
°C
Copyright © 2016–2019, Texas Instruments Incorporated
5
OPA325, OPA2325, OPA4325
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
www.ti.com.cn
6.4 Thermal Information: OPA325
OPA325
DBV (SOT)
5 PINS
205
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
200
113
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
38.2
ΨJB
104.9
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2325
OPA2325
THERMAL METRIC(1)
D (SOIC)
8 PINS
119
DGK (VSSOP)
UNIT
8 PINS
143
47
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
60
61
64
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
15.0
60.4
N/A
5.3
ΨJB
62.8
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4325
OPA4325
THERMAL METRIC(1)
PW (TSSOP)
UNIT
14 PINS
93
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
28
34
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.9
ΨJB
33.1
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2016–2019, Texas Instruments Incorporated
OPA325, OPA2325, OPA4325
www.ti.com.cn
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
6.7 Electrical Characteristics: VS = 2.2 V to 5.5 V or ±1.1 V to ±2.75 V
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
40
2
150
7.5
20
µV
dVOS/dT
Input offset voltage drift
VS = 5.5 V, TA = –40°C to +125°C
VS = 2.2 V to +5.5 V
µV/°C
6
PSRR
Power-supply rejection ratio
Channel separation
µV/V
dB
VS = 2.2 V to 5.5 V, TA = –40°C to +125°C
At 1 kHz
15
130
INPUT VOLTAGE
VCM
Common-mode voltage range
(V–) – 0.1
100
(V+) + 0.1
V
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V
TA = –40°C to +125°C
114
±0.2
±0.2
CMRR
Common-mode rejection ratio
dB
95
INPUT BIAS CURRENT
±10
±500
±10
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to +85°C
TA = –40°C to +125°C
±10
IOS
Input offset current
TA = –40°C to +85°C
TA = –40°C to +125°C
±500
±10
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
2.8
10
9
µVPP
en
in
Input voltage noise density
nV/√Hz
fA/√Hz
f = 10 kHz
Input current noise density
f = 1 kHz
1.3
INPUT CAPACITANCE
Differential
5
4
pF
pF
Common-mode
OPEN-LOOP GAIN
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
105
95
130
128
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ,
TA = –40°C to +125°C
AOL
PM
Open-loop voltage gain
dB
0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ
100
110
67
Phase margin
G = 1 V/V, VS = 5 V, CL = 15 pF
Degrees
FREQUENCY RESPONSE (VS = 5.0 V, CL = 50 pF)
GBP
SR
Gain bandwidth product
Slew rate
Unity gain
10
5
MHz
G = +1
V/μs
To 0.1%, 2-V step, G = +1
To 0.01%, 2-V step, G = +1
VIN × G > VS
0.6
tS
Settling time
µs
ns
1
Overload recovery time
Total harmonic distortion + noise(1)
200
VO = 4 VPP, G = +1, f = 10 kHz, RL = 10 kΩ
VO = 2 VPP, G = +1, f = 10 kHz, RL = 600 Ω
0.0005%
0.005%
THD+N
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
Copyright © 2016–2019, Texas Instruments Incorporated
7
OPA325, OPA2325, OPA4325
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
www.ti.com.cn
Electrical Characteristics: VS = 2.2 V to 5.5 V or ±1.1 V to ±2.75 V (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
RL = 10 kΩ
10
20
30
45
55
RL = 10 kΩ, TA = –40°C to +125°C
RL = 2 kΩ
VO
Voltage output swing from both rails
mV
25
RL = 2 kΩ, TA = –40°C to +125°C
VS = 5.5 V
ISC
CL
RO
Short-circuit current
See the Typical Characteristics
See the Typical Characteristics
180
mA
Capacitive load drive
Open-loop output resistance
IO = 0 mA, f = 1 MHz
Ω
POWER SUPPLY
IQ Quiescent current per amplifier
Power-on time
IO = 0 mA, VS = 5.5 V
0.65
28
0.75
0.8
mA
µs
IO = 0 mA, VS = 5.5 V, TA = –40°C to +125°C
V+ = 0 V to 5 V, to 90% IQ level
8
版权 © 2016–2019, Texas Instruments Incorporated
OPA325, OPA2325, OPA4325
www.ti.com.cn
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
6.8 Typical Characteristics
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
15
10
5
20
15
10
5
0
0
Offset Voltage Drift (µV/°C)
Offset Voltage (µV)
C002
C001
图 1. Offset Voltage Production Distribution Histogram
图 2. Offset Voltage Drift Distribution Histogram
500
400
150
125
100
75
300
200
50
100
25
0
0
œ25
œ50
œ100
œ200
œ300
œ400
œ500
œ75
VCM = œ2.85 V
œ100
VCM = 2.85 V
œ125
œ150
0
1
2
3
œ75 œ50 œ25
0
25
50
75
100 125 150
œ3
œ2
œ1
VCM (V)
Temperature (°C)
C003
C010
图 3. Offset Voltage vs Common-Mode Voltage
图 4. Offset Voltage vs Temperature
150
140
180
120
100
80
100
50
Gain
135
90
45
0
Phase
0
60
40
œ50
œ100
œ150
VS
=
1.1 V
20
VS
=
2.75 V
0
œ20
1
10
100
1k
10k
100k
1M
10M
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Frequency (Hz)
VSUPPLY (V)
C200
C017
CL = 15 pF
图 5. Open-Loop Gain and Phase vs Frequency
图 6. Offset Voltage vs Supply Voltage
版权 © 2016–2019, Texas Instruments Incorporated
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OPA325, OPA2325, OPA4325
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
40.0
40.0
30.0
30.0
20.0
20.0
VS
=
1.1 V
VS
=
1.1 V
10.0
10.0
0.0
0.0
VS
= 2.75 V
VS
=
2.75 V
œ10.0
œ20.0
œ30.0
œ40.0
œ10.0
œ20.0
œ30.0
œ40.0
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C006
C005
RL = 2 kΩ
图 8. Open-Loop Gain vs Temperature
RL = 10 kΩ
图 7. Open-Loop Gain vs Temperature
1000
900
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
VS
=
2.75 V
VS
=
1.1 V
0
25
50
75
100 125 150
œ75 œ50 œ25
0
0.5
1
1.5
2
2.5
3
Temperature (°C)
Supply Voltage (V)
C007
C004
图 9. Quiescent Current vs Temperature
图 10. Quiescent Current vs Supply Voltage
20
10
8
6
15
10
5
4
2
0
œ2
œ4
œ6
œ8
œ10
0
0
1
2
3
œ3
œ2
œ1
Input Bias Current (pA)
VCM (V)
C013
C015
图 11. Input Bias Current vs Common-Mode Voltage
图 12. Input Bias Current Distribution Histogram
10
版权 © 2016–2019, Texas Instruments Incorporated
OPA325, OPA2325, OPA4325
www.ti.com.cn
ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
Typical Characteristics (接下页)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
25
20
15
10
5
2.0
1.5
1.0
0.5
0.0
IOS
0
0
25
50
75
100 125 150
œ75 œ50 œ25
Input Offset Current (pA)
Temperature (°C)
C014
C016
图 14. Input Bias Current vs Temperature
图 13. Input Offset Current Distribution Histogram
3
0
-0.5
-1
125°C
85°C
2.5
2
1.5
1
-1.5
-2
25°C
125°C
œ40°C
œ40°C
85°C
0.5
0
-2.5
-3
25°C
0
10
20
30
40
50
60
0
10
20
30
40
50
60
IO (mA)
IO (mA)
C009A
C009B
图 15. Output Voltage Swing (Positive) vs
图 16. Output Voltage Swing (Negative) vs
Output Current
Output Current
60
50
40
30
20
10
0
120
100
80
60
40
20
0
ISC, Sink
PSRR+
CMRR
PSRR-
ISC, Source
1
10
100
1k
10k
100k
1M
0
25
50
75
100 125 150
œ75 œ50 œ25
Frequency (Hz)
Temperature (°C)
C203
C008
图 18. CMRR and PSRR vs Frequency
图 17. Short-Circuit Current vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
15
10
5
20
15
10
5
0
0
-5
-5
-10
-15
-20
-10
-15
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C011
C012
图 19. CMRR vs Temperature
图 20. PSRR vs Temperature
1k
100
10
1
1
10
100
1k
10k
100k
Time
(1 s/div)
Frequency (Hz)
C205
C204
图 21. Input Voltage Noise Spectral Density vs Frequency
图 22. 0.1-Hz to 10-Hz Input Voltage Noise
60
60
40
20
0
G = +100
G = +100
G = +10
40
G = +10
20
G = +1
G = +1
0
-20
-20
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C201
C202
VS = 1.8 V, RL = 10 kΩ, CL = 15 pF
图 23. Closed-Loop Gain vs Frequency
VS = 5.5 V, RL = 10 kΩ, CL = 15 pF
图 24. Closed-Loop Gain vs Frequency
12
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Typical Characteristics (接下页)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
10k
7
6
VS
=
2.5 V
5
4
3
2
1
0
1k
VS
= 0.9 V
100
100
1k
10k
100k
1M
10M
10m 100m
1
10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)
Frequency (Hz)
C218
C025
图 25. Maximum Output Voltage vs Frequency
图 26. Open-Loop Output Impedance vs Frequency
70
0.1
-60
G = -1, RL = 600 Ω
G = +1, RL = 600 Ω
60
50
40
30
20
10
0
0.01
-80
G = -1,
RL = 2 kΩ
G = 1, VS = 5.5 V
G = 10, VS = 5.5 V
G = 1, VS = 1.8 V
0.001
0.0001
-100
-120
G = -1,
RL = 10 kΩ
G = 10, VS = 5.5 V
G = +1, RL = 10 kΩ
0.1
G = +1, RL = 2 kΩ
0
200
400
600
800
1000
0.001
0.01
1
Capacitive Load (pF)
Output Amplitude (VRMS
)
C209
C208
f = 10 kHz, VS = ±2.5 V, filter bandwidth = 500 kHz
图 27. Small-Signal Overshoot vs Load Capacitance
图 28. THD+N vs Amplitude
1
-40
1
0.1
-40
G = -1, RL = 600 Ω
G = -1, RL = 600 Ω
G = +1, RL = 600 Ω
G = -1, RL = 2 kΩ
-60
G = +1, RL = 600 Ω
G = -1, RL = 2 kΩ
0.1
-60
-80
-80
G = -1, RL = 10 kΩ
G = +1, RL = 2 kΩ
0.01
0.01
G = -1, RL = 10 kΩ
G = +1, RL = 2 kΩ
-100
-120
-140
0.001
0.0001
0.001
0.0001
-100
-120
G = +1,
RL = 10 kΩ
G = +1, RL = 10 kΩ
10
100
1k
Frequency (Hz)
10k
100k
10
100
1k
Frequency (Hz)
10k
100k
C206
C004
VIN = 2 VPP, VS = ±2.5 V, filter bandwidth = 500 kHz
VIN = 4 VPP, VS = ±2.5 V, filter bandwidth = 500 kHz
图 29. THD+N vs Frequency
图 30. THD+N vs Frequency
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Typical Characteristics (接下页)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
VIN
VOUT
VIN
VOUT
Time (50 ms/div)
Time (100 µs/div)
C210
C212
图 31. No Phase Reversal
图 32. Positive Overload Recovery
6
Slew Rate (Rising)
5.8
VIN
5.6
5.4
5.2
5
Slew Rate (Falling)
VOUT
Time (100 µs/div)
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
C211
C219
CL = 15 pF
图 33. Negative Overload Recovery
图 34. Slew Rate vs Supply Voltage
VOUT
VIN
0.01% Settling = ±200 µV
Time (1 µs/div)
Time (2.5 µs/div)
C217
C213
VIN = 2-V step
VIN = 10 mVPP, G = +1, CL = 15 pF
图 36. 0.01% Positive Settling Time
图 35. Small-Signal Step Response
14
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Typical Characteristics (接下页)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
0.01% Settling = ±200 µV
VOUT
VIN
Time (1 µs/div)
Time (2.5 µs/div)
C216
C215
VIN = 2-V step
VIN = 4 VPP, G = +1, CL = 15 pF
图 37. 0.01% Negative Settling Time
图 38. Large-Signal Step Response
VOUT
VIN
Time (2.5 µs/div)
C214
VIN = 4 VPP, G = –1, CL = 15 pF
图 39. Large-Signal Step Response
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7 Detailed Description
7.1 Overview
The OPA325, OPA2325, and OPA4325 (OPAx325) belong to a new generation of low-noise, e-trim™ operational
amplifiers that provide outstanding dc precision. The OPAx325 also have a highly linear input stage with zero-
crossover distortion that delivers excellent CMRR and distortion performance across the full rail-to-rail input
range. In addition, this device has a wide supply range with excellent PSRR. This feature, combined with low
quiescent current, makes the OPAx325 an excellent choice for applications that are battery-powered without
regulation.
7.2 Functional Block Diagram
V+
OPAx325
Charge
pump
-IN
OUT
+IN
ꢀ
POR
e-trim™
V-
16
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7.3 Feature Description
7.3.1 Zero-Crossover Input Stage
Traditional complementary metal-oxide semiconductor (CMOS) rail-to-rail input amplifiers use a complementary
input stage: an N-channel input differential pair in parallel with a P-channel differential pair. This configuration
results in sudden change in offset voltage when the input stage transitions from the p-channel metal-oxide-
semiconductor field effect transistor (PMOS) to the n-type field effect transistor (NMOS), or vice-versa, as shown
in 图 40. This transition results in significant degradation of CMRR and PSRR performance of the amplifier.
.
3
2
1
0
-1
-2
-V
+V
-3
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common-Mode Voltage (V)
图 40. Input Common-Mode Voltage vs Input Offset Voltage
(Traditional Rail-to-Rail Input CMOS Amplifiers)
The OPAx325 series of amplifiers includes an internal charge pump that powers the amplifier input stage with an
internal supply rail that is higher than the external power supply. The internal supply rail allows a single
differential pair to operate and to be linear across the entire input common-mode voltage range, thus eliminating
crossover distortion. Rail-to-rail amplifiers that use this technique to eliminate crossover distortion are called
zero-crossover amplifiers.
The single differential pair combined with the charge pump allows the OPAx325 to provide superior CMRR
across the entire common-mode input range, which extends 100 mV beyond both power-supply rails. 图 41
shows the input offset voltage versus input common-mode voltage plot for the OPAx325. Note that unlike
traditional rail-to-rail CMOS amplifiers, there is no transition region for the OPAx325.
150
125
100
75
50
25
0
œ25
œ50
œ75
VCM = œ2.85 V
œ100
VCM = 2.85 V
œ125
œ150
0
1
2
3
œ3
œ2
œ1
VCM (V)
C003
图 41. Offset Voltage vs Common-Mode Voltage (Zero-Crossover)
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Feature Description (接下页)
7.3.2 Low Input Offset Voltage
The OPAx325 are manufactured using TI's e-trim technology. Each amplifier is trimmed in production, thereby
minimizing errors associated with input offset voltage. The e-trim technology is a TI proprietary method of
trimming internal device parameters during either wafer probing or final testing. This process allows the
OPAx325 to have an excellent offset specification of 150 µV (maximum). 图 42 shows the offset voltage
distribution for the OPAx325.
15
10
5
0
Offset Voltage (µV)
C002
图 42. Offset Voltage Distribution
7.3.3 Input and ESD Protection
The OPAx325 incorporate internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long
as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. 图 43 shows how a series
input resistor can be added to the driven input to limit the input current. The added resistor contributes thermal
noise at the amplifier input; thus, keep the value to a minimum in noise-sensitive applications.
Current-limiting resistor
required if input voltage
exceeds supply rails by
> 0.3V.
+5V
IOVERLOAD
10 mA max
VOUT
VIN
5 kΩ
Copyright © 2016, Texas Instruments Incorporated
图 43. Input Current Protection
7.4 Device Functional Modes
The OPAx325 have a single functional mode and are operational when the power-supply voltage is greater than
2.2 V (±1.1 V). The maximum power-supply voltage for the OPAx325 is 5.5 V (±2.75 V).
18
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx325 series features e-trim, a proprietary technique in which the offset voltage is adjusted during the
final steps of manufacturing. As a result, the OPAx325 deliver excellent offset voltage (40 μV, typical).
Additionally, the amplifier boasts a fast slew rate, low drift, low noise, and excellent PSRR and AOL. The
OPAx325 also feature a linear input stage with zero-crossover distortion, resulting in excellent CMRR over the
entire input range, which extends from 100 mV below the negative rail to 100 mV above the positive rail.
8.1.1 Operating Characteristics
The OPAx325 family of amplifiers has parameters that are fully specified from 2.2 V to 5.5 V (±1.1 V to ±2.75 V).
Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with
regard to operating voltage or temperature are presented in the Typical Characteristics section.
8.1.2 Basic Amplifier Configurations
The OPAx325 are unity-gain stable. The devices do not exhibit output phase inversion when the input is
overdriven. A typical single-supply connection is shown in 图 44. The OPAx325 are configured as a basic
inverting amplifier with a gain of –10 V/V. This single-supply connection has an output centered on the common-
mode voltage, VCM. For the circuit shown, this voltage is 2.5 V, but can be any value within the common-mode
input voltage range.
R1
1 kꢀ
R2
10 kꢀ
+5V
0 …F
+
VIN
œ
œ
OPAx325
+
OUT
+
VCM = 2.5 V
œ
Copyright © 2017, Texas Instruments Incorporated
图 44. Basic Single-Supply Connection
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Application Information (接下页)
8.1.3 Driving an Analog-to-Digital Converter
The low-noise and wide-gain bandwidth of the OPAx325, combined with rail-to-rail input/output and zero-
crossover distortion, make these devices an excellent input driver for ADCs. 图 45 shows the OPAx325 driving
an ADC. The amplifier is connected as a unity-gain, noninverting buffer.
3.3 V
VREF
R
ADC
OPAx325
Input
+
VSS
VDD
5 V
C
图 45. The OPAx325 as an Input Driver for ADCs
8.2 Typical Application
Operational amplifiers are commonly used as unity-gain buffers. 图 46 shows the schematic for an amplifier
configured as a unity-gain buffer. If the input signal range to the amplifier is very close to the rails or includes the
rails, a rail-to-rail amplifier must be used. However, regular rail-to-rail amplifiers introduce significant distortion to
the signal. This design compares the distortion introduced by a typical CMOS input amplifier with that of the
OPAx325 (a zero-crossover amplifier).
+2.5 V
œ
VOUT
+
OPAx325
4 VPP
-2.5 V
Sine Wave
GND
图 46. The OPAx325 Configured as a Unity-Gain Buffer Amplifier
8.2.1 Design Requirements
The following parameters are used for this design example:
•
•
•
Gain = +1 V/V (inverting gain)
V+ = 2.5 V, V– = –2.5 V
Input signal = 4 VPP, f = 1-kHz sine wave
20
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Typical Application (接下页)
8.2.2 Detailed Design Procedure
Traditional CMOS rail-to-rail input amplifiers use a complementary input stage: an N-channel input differential
pair in parallel with a P-channel differential pair, as shown in 图 47.
+Vsupply
IS1
VINœ
PCH1
PCH2
NCH3
NCH4
VIN+
e-trim™
œVsupply
图 47. Complementary Input Stage (Traditional Rail-to-Rail Input CMOS Amplifiers)
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Typical Application (接下页)
The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1 V to 200 mV above the
positive supply, and the P-channel pair is on for inputs from 200 mV below the negative supply to approximately
(V+) – 1 V. There is a small transition region, typically (V+) – 1.1 V to (V+) – 0.9 V, in which both pairs are on.
This transition region is shown in 图 48 for a traditional rail-to-rail input CMOS amplifier. Within this transition
region, PSRR, CMRR, offset voltage, offset drift, and THD can be degraded when compared to device operation
outside of this region.
3
2
1
0
-1
-2
-V
+V
-3
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common-Mode Voltage (V)
图 48. Input Offset Voltage vs Common-Mode Voltage
(For Traditional Rail-to-Rail Input CMOS Amplifiers)
The OPAx325 amplifiers include an internal charge pump that powers the amplifier input stage with an internal
supply rail that is higher than the external power supply. The internal supply rail allows a single differential pair to
operate and to be linear across the entire input common-mode voltage range, as shown in 表 1.
+VSUPPLY
Charge Pump
IS1
PCH1
PCH2
VIN+
VINœ
e-trimTM
œVsupply
图 49. Single Differential Input Pair with a Charge Pump (Zero-Crossover)
22
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Typical Application (接下页)
The unique zero-crossover topology shown in 表 1 eliminates the input offset transition region, typical of most
rail-to-rail input operational amplifiers. This topology allows the OPAx325 to provide superior CMRR across the
entire common-mode input range that extends 100 mV beyond both power-supply rails. 图 50 shows the input
offset voltage versus input common-mode voltage plot for the OPAx325.
150
125
100
75
50
25
0
œ25
œ50
œ75
VCM = œ2.85 V
œ100
VCM = 2.85 V
œ125
œ150
0
1
2
3
œ3
œ2
œ1
VCM (V)
C003
图 50. Offset Voltage vs Common-Mode Voltage (OPAx325, Zero-Crossover Amplifier)
The OPAx325 and a typical CMOS amplifier were used in identical circuits where these amplifiers were
configured as a unity-gain buffer amplifier; see 图 51 and 图 52. A pure sine wave with an amplitude of 2 V (4
VPP) was given as input to the two identical circuits of 图 51 and 图 52. The outputs of these circuits were
captured on a spectrum analyzer. 图 53 and 图 54 illustrate the output voltage spectrum for the OPAx325 and a
typical CMOS rail-to-rail amplifier, respectively. The output of the OPAx325 has very few spurs and harmonics
when compared to the typical rail-to-rail CMOS amplifier, as illustrated in 图 55.
+2.5 V
œ
VOUT
+
OPAx325
4 VPP
-2.5 V
Sine Wave
GND
图 51. OPAx325 as a Unity-Gain Buffer
2.5 V
œ
VOUT
+
Typical CMOS
4-VPP
-2.5 V
rail-to-rail amplifiers
Sine Wave
GND
图 52. Typical CMOS Rail-to-Rail Amplifier as a Unity-Gain Buffer
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Typical Application (接下页)
8.2.3 Application Curves
20
0
20
0
œ20
œ20
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ180
œ100
œ120
œ140
œ160
œ180
0.
5k
10k
15k
20k
0.
5k
10k
15k
20k
Frequency (Hz)
Frequency (Hz)
C051
C053
图 53. Output Voltage Spectrum (OPAx325)
图 54. Output Voltage Spectrum
(Typical CMOS Rail-to-Rail Amplifier)
0
œ20
œ40
œ60
œ80
Typical rail-to-rail CMOS amplifier
OPA2325
œ100
œ120
0.
5k
10k
15k
20k
Frequency (Hz)
C052
图 55. THD+N vs Frequency
24
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ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
9 Power Supply Recommendations
The OPAx325 are specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure
to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more
detailed information refer to, see Circuit Board Layout Techniques.
In order to reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close as possible to the device. As illustrated in 图 57, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
For best performance, clean the PCB following board assembly.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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www.ti.com.cn
10.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
图 56. Schematic Representation for 图 57
Place components
close to device and to
each other to reduce
parasitic errors.
OUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUT A
V+
RF
OUT B
GND
-IN A
+IN A
Vœ
OUT B
-IN B
RF
RG
GND
VIN A
RG
+IN B
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor. Place as
close to the device
as possible.
VSœ
Ground (GND) plane on another layer
as possible.
图 57. Layout Example
26
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ZHCSFL2D –OCTOBER 2016–REVISED JUNE 2019
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
德州仪器 (TI)，《电路板布局技巧》 应用报告
11.2 相关链接
表 1 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具与软件，以及立即订购快速访问。
表 1. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
立即订购
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
OPA325
OPA2325
OPA4325
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
e-trim, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2019, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2325ID
OPA2325IDGKR
OPA2325IDGKT
OPA2325IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
O2325
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
DGK
DGK
D
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
18L6
18L6
O2325
1UEV
1UEV
4325
4325
8
8
2500 RoHS & Green
3000 RoHS & Green
OPA325IDBVR
OPA325IDBVT
OPA4325IPW
OPA4325IPWR
SOT-23
SOT-23
TSSOP
TSSOP
DBV
DBV
PW
PW
5
NIPDAU
5
250
90
RoHS & Green
RoHS & Green
NIPDAU
14
14
NIPDAU
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2325IDGKR
OPA2325IDGKR
OPA2325IDGKT
OPA2325IDGKT
OPA2325IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
2500
2500
250
330.0
330.0
330.0
330.0
330.0
180.0
180.0
330.0
12.4
12.4
12.4
12.4
12.4
8.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
8.0
8.0
8.0
4.0
4.0
8.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q3
Q3
Q1
8
5.3
3.4
1.4
8
250
5.3
3.4
1.4
8
2500
3000
250
6.4
5.2
2.1
OPA325IDBVR
OPA325IDBVT
OPA4325IPWR
SOT-23
SOT-23
TSSOP
DBV
DBV
PW
5
3.23
3.23
6.9
3.17
3.17
5.6
1.37
1.37
1.6
5
8.4
8.0
14
2000
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2325IDGKR
OPA2325IDGKR
OPA2325IDGKT
OPA2325IDGKT
OPA2325IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
2500
2500
250
366.0
366.0
366.0
366.0
356.0
213.0
213.0
356.0
364.0
364.0
364.0
364.0
356.0
191.0
191.0
356.0
50.0
50.0
50.0
50.0
35.0
35.0
35.0
35.0
8
8
250
8
2500
3000
250
OPA325IDBVR
OPA325IDBVT
OPA4325IPWR
SOT-23
SOT-23
TSSOP
DBV
DBV
PW
5
5
14
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA2325ID
D
SOIC
8
75
90
506.6
530
8
3940
3600
4.32
3.5
OPA4325IPW
PW
TSSOP
14
10.2
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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