OPA4H014PWTSEP [TI]
采用空间增强型塑料的耐辐射 11MHz 低噪声精密 RRO JFET 放大器 | PW | 14 | -55 to 125;
| 型号： | OPA4H014PWTSEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用空间增强型塑料的耐辐射 11MHz 低噪声精密 RRO JFET 放大器 | PW | 14 | -55 to 125 放大器 |
| 文件： | 总33页 (文件大小：1743K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA4H014-SEP
ZHCSOR9A –NOVEMBER 2021 –REVISED APRIL 2022
OPA4H014-SEP 采用增强型航天塑料的11MHz、精密、低噪声、RRO、JFET 运
算放大器
1 特性
3 说明
• 抗辐射
OPA4H014-SEP 是一款低功耗 JFET 输入运算放大
器，具有良好漂移性能和较低的输入偏置电流。凭借其
包括 V– 在内的输入范围和轨至轨输出，设计人员可
以利用JFET 放大器的低噪声特性，同时还可以连接到
单电源精密模数转换器(ADC) 和数模转换器(DAC)。
– 单粒子锁定(SEL) 对于43MeV•cm2/mg 的抗扰
度
– 在30 krad(Si) 的条件下无ELDRS
– 每个晶圆批次的RLAT 总电离剂量(TID) 高达
30 krad(Si)
OPA4H014-SEP 可实现 11MHz 单位增益带宽和 20V/
μs 压摆率，同时仅消耗 1.8mA（典型值）的静态电
流。此器件由4.5V 至18V 单电源或±2.25V 至±9V 双
电源供电。
• 增强型航天塑料
– Au 键合线和NiPdAu 铅涂层
– 采用增强型模塑化合物实现低释气
– 制造、组装和测试一体化基地
– 延长了产品生命周期
– 延长了产品变更通知周期
– 产品可追溯性
运算放大器采用 14 引脚塑料 TSSOP 封装，可抵御高
达
43MeV•cm2/mg (SET) 的辐射， 并且在高达
30krad(Si) 的条件下无ELDRS
• 非常低的温漂：1 μV/°C（最大值）
• 极低的偏移：120 μV
• 低输入偏置电流：10 pA（最大值）
• 低噪声：5.1 nV/√Hz
封装信息
封装(1)
封装尺寸（标称值）
器件型号
OPA4H014-SEP
TSSOP (14)
5.00mm × 4.40mm
• 压摆率：20 V/μs
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
• 低电源电流：2 mA（最大值）
• 输入电压范围包括V–电源
• 宽电源电压范围：4.5V 至18V
2 应用
• 卫星运行状况监控和遥测
• 科学勘探有效载荷
• 姿态和轨道控制系统(AOCS)
• 卫星电力系统(EPS)
• 通信负载
• 雷达成像有效载荷
Time (1s/div)
0.1Hz 至10Hz 噪声
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA94
OPA4H014-SEP
ZHCSOR9A –NOVEMBER 2021 –REVISED APRIL 2022
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Table of Contents
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 21
8.3 Power Supply Recommendations.............................22
8.4 Layout....................................................................... 22
9 Device and Documentation Support............................24
9.1 Device Support......................................................... 24
9.2 Documentation Support............................................ 24
9.3 接收文档更新通知..................................................... 24
9.4 支持资源....................................................................24
9.5 Trademarks...............................................................25
9.6 Electrostatic Discharge Caution................................25
9.7 术语表....................................................................... 25
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................14
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2021) to Revision A (April 2022)
Page
• 将器件状态从“预告信息（预发布）”更改为“量产数据（正在供货）”.........................................................1
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5 Pin Configuration and Functions
OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
OUT D
14
13
œIN D
A
D
12 +IN D
11
Vœ
10
+ IN B
œIN B
OUT B
+ IN C
B
C
9
œIN C
8
OUT C
图5-1. PW (14-Pin TSSOP) Package, Top View
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
3
+IN A
Input
Input
Noninverting input, channel A
Inverting input, channel A
Noninverting input, channel B
Inverting input, channel B
Noninverting input, channel C
Inverting input, channel C
Noninverting input, channel D
Inverting input, channel D
Output, channel A
2
–IN A
+IN B
–IN B
+IN C
–IN C
+IN D
–IN D
OUT A
OUT B
OUT C
OUT D
V+
5
Input
6
Input
10
9
Input
Input
12
13
1
Input
Input
Output
Output
Output
Output
Power
Power
7
Output, channel B
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
11
V–
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Dual supply
±10
20
VS
V
Supply voltage, (V+) –(V–)
Single supply
Voltage
(V+) + 0.5
±10
V
(V–) –0.5
Signal input pins(2)
Current
mA
Output short-circuit(3)
Operating temperature
Junction temperature
Storage temperature
Continuous
Continuous
150
TA
°C
°C
°C
–55
TJ
150
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.25
4.5
NOM
MAX
±9
UNIT
Dual supply
VS
TA
V
Supply voltage, (V+) –(V–)
Single supply
18
Ambient temperature
25
125
°C
–55
6.4 Thermal Information
OPA4H014-SEP
THERMAL METRIC (1)
PW (TSSOP)
UNIT
8 PINS
135
45
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
66
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19
ΨJT
60
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, RL = 2 kΩ connected to midsupply, VS = ±2.25 V to ±9 V, and VCM = VOUT = midsupply (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±30
±120
±220
±4
μV
VOS
Input offset voltage
VS = ±9 V, TA = –55°C to +125°C
TA = –55°C to +125°C
VS = ±9 V, TA = –55°C to +125°C
TA = –55°C to +125°C
f = dc
μV/V
μV/°C
μV/V
dVOS/dT
PSRR
Drift
±0.35
±0.1
0.02
10
±1
Power-supply rejection ratio
±0.5
Channel separation
µV/V
f = 100 kHz
INPUT BIAS CURRENT
±0.5
±0.5
±10
±3
pA
nA
pA
nA
IB
Input bias current
TA = –55°C to +125°C
TA = –55°C to +125°C
±10
±1
IOS
Input offset current
Input voltage noise
NOISE
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 10 Hz
250
42
nVPP
nVRMS
8
en
Input voltage noise density
Input current noise density
f = 100 Hz
5.8
5.1
0.8
nV/√Hz
fA/√Hz
V
f = 1 kHz
In
INPUT VOLTAGE
f = 1 kHz
VCM
Common-mode voltage
TA = –55°C to +125°C
(V–) –0.1
(V+) –3.5
VS = ±9 V,
VCM = (V–) –0.1 V to (V+) –3.5 V
126
140
CMRR
Common-mode rejection ratio
dB
VS = ±9 V,
VCM = (V–) –0.1 V to (V+) –3.5 V,
TA = –55°C to +125°C
120
INPUT IMPEDANCE
Differential
Common-mode
OPEN-LOOP GAIN
1013 || 10
1013 || 7
Ω|| pF
VCM = (V–) –0.1 V to (V+) –3.5 V
VO = (V–) + 0.35 V to (V+) –0.35 V,
RL = 10 kΩ
120
114
108
126
126
AOL
Open-loop voltage gain
dB
VO = (V–) + 0.35 V to (V+) –0.35 V
VO = (V–) + 0.35 V to (V+) –0.35 V,
TA = –55°C to +125°C
FREQUENCY RESPONSE
BW
SR
Gain bandwidth product
11
20
MHz
Slew rate
V/μs
12 bits
16 bits
10-V step, gain = +1
0.88
Settling time
μs
10-V step, gain = +1
1.6
THD+N
Total harmonic distortion and noise
Overload recovery time
f = 1 kHz, gain = +1, VO = 3.5 VRMS
0.00005%
600
ns
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6.5 Electrical Characteristics (continued)
at TA = 25°C, RL = 2 kΩ connected to midsupply, VS = ±2.25 V to ±9 V, and VCM = VOUT = midsupply (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
RL = 10 kΩ, AOL ≥108 dB
(V–) + 0.2
(V+) –0.2
Output swing from rail
Short-circuit current
V
A
OL ≥108 dB
(V–) + 0.35
(V+) –0.35
Source
Sink
36
ISC
mA
–30
CLOAD
ZO
Capacitive load drive
See 图6-17 and 图6-18
Open-loop output impedance
f = 1 MHz, IO = 0 mA
16
Ω
POWER SUPPLY
IO = 0 mA
1.8
2
IQ Quiescent current (per amplifier)
mA
2.7
TA = –55°C to +125°C
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6.6 Typical Characteristics
at TA = 25°C, VS = ±9 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
表6-1. Table of Graphs
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
图6-1
Offset Voltage Drift Distribution
图6-2
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
IB vs Common-Mode Voltage
图6-3
图6-4
Output Voltage Swing vs Output Current
CMRR and PSRR vs Frequency (RTI)
Common-Mode Rejection Ratio vs Temperature
0.1-Hz to 10-Hz Noise
图6-5
图6-6
图6-7
图6-8
Input Voltage Noise Density vs Frequency
THD+N Ratio vs Frequency (80-kHz AP Bandwidth)
Quiescent Current vs Temperature
图6-9
图6-10
图6-11
图6-12
图6-13
图6-14
图6-15
图6-16
图6-17
图6-18
图6-19
图6-20
图6-21
图6-22
图6-23, 图6-24
图6-25
图6-26
图6-27
图6-28
图6-29
图6-30
Quiescent Current vs Supply Voltage
Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (G = 1)
Small-Signal Overshoot vs Capacitive Load (G = –1)
No Phase Reversal
Maximum Output Voltage vs Frequency
Positive Overload Recovery
Negative Overload Recovery
Large-Signal Positive and Negative Settling Time
Small-Signal Step Response (G = 1)
Small-Signal Step Response (G = –1)
Large-Signal Step Response (G = 1)
Large-Signal Step Response (G = –1)
Short-Circuit Current vs Temperature
Channel Separation vs Frequency
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±9 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
Offset Voltage (mV)
Offset Voltage Drift (mV/°C)
图6-1. Offset Voltage Production Distribution
图6-2. Offset Voltage Drift Distribution
120
10
8
18 Typical Units Shown
100
80
60
40
6
20
0
-20
-40
-60
-80
-100
-120
4
2
+IB
‒IB
0
-9
-9
-3
3
9
-6
-3
0
6
9
3
VCM (V)
VCM (V)
图6-3. Offset Voltage vs Common-Mode Voltage
图6-4. Bias Current vs Common-Mode Voltage
-9
8.5
8
180
CMRR
160
140
120
100
80
7.5
7
+25°C
–40°C
-PSRR
+85°C
+125°C
+PSRR
-7
-7.5
-8
60
40
20
-8.5
-9
0
1
10
100
1k
10k 100k
1M
10M 100M
0
10
20
30
40
50
60
70
Frequency (Hz)
Output Current (mA)
图6-6. CMRR and PSRR vs Frequency (Referred to Input)
图6-5. Output Voltage Swing vs Output Current
(Maximum Supply)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±9 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
0.12
0.10
0.08
0.06
0.04
0.02
0
-75
-50
-25
0
25
50
75
100 125 150
Time (1s/div)
Temperature (°C)
图6-7. Common-Mode Rejection Ratio vs Temperature
图6-8. 0.1-Hz to 10-Hz Noise
0.001
0.0001
–100
–120
–140
100
G = –1
10
G = +1
0.00001
10
100
1k
10k 20k
1
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
VOUT = 3 VRMS, BW = 80 kHz, RL = 2 kΩ
图6-9. Input Voltage Noise Density vs Frequency
图6-10. THD+N Ratio vs Frequency
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
2.5
2.0
1.5
1.0
0.5
0
Specified Supply-Voltage Range
8
18
16
12
4
-75
-50
-25
0
25
50
75
100 125 150
0
Temperature (°C)
Supply Voltage (V)
图6-11. Quiescent Current vs Temperature
图6-12. Quiescent Current vs Supply Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±9 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
40
30
140
120
100
80
180
135
90
45
0
G = +10
Gain
20
10
G = +1
60
0
–10
–20
–30
–40
40
Phase
20
G = –1
10M
0
-20
10
100
1k
10k
100k
1M
10M
100M
100k
1M
100M
Frequency (Hz)
Frequency (Hz)
CL = 30 pF
图6-14. Closed-Loop Gain vs Frequency
图6-13. Gain and Phase vs Frequency
0
1k
10-k Load
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
100
10
1
2-k Load
10
100
1k
10k
100k
1M
10M
100M
–75 –50 –25
0
25
50
75
100 125 150
Frequency (Hz)
Temperature (°C)
图6-15. Open-Loop Gain vs Temperature
图6-16. Open-Loop Output Impedance vs Frequency
40
35
30
25
20
15
10
5
50
45
ROUT = 0
+9 V
ROUT
ROUT = 0
40
ROUT = 24
RL CL
ꟷ9 V
35
30
25
20
ROUT = 24
RI
2 k
RF
2 k
ROUT = 51
15
10
5
+9 V
ROUT
ROUT = 51
CL
–9 V
0
0
0
200
400
600
800 1000 1200 1400 1600
0
500
1000
1500
2000
Capacitive Load (pF)
Capacitive Load (pF)
G = +1
G = –1
图6-17. Small-Signal Overshoot vs Capacitive Load
图6-18. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
(100-mV Output Step)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±9 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
35
Maximum Output
Voltage Range
Without Slew-Rate
Induced Distortion
30
Output
25
VS = ±± V
20
+9 V
15
VS = ±5 V
10
Output
–9 V
19-VPP
Sine Wave
(±9.5 V)
VS = ±2ꢀ25 V
5
0
Time (0.4 µs/div)
10k
100k
Frequency (Hz)
1M
10M
图6-19. No Phase Reversal
图6-20. Maximum Output Voltage vs Frequency
VOUT
VIN
20 k
20 k
2 k
2 k
VIN
VOUT
VOUT
VIN
V
IN
VOUT
Time (0.4 µs/div)
Time (0.4 µs/div)
G = –10
G = –10
图6-21. Positive Overload Recovery
图6-22. Negative Overload Recovery
1000
800
1000
800
600
600
400
400
16-bit Settling
16-bit Settling
200
200
0
0
-200
-400
-600
-800
-1000
-200
-400
-600
-800
-1000
( 1/2LSB = 0.00075%)
( 1/2LSB = 0.00075%)
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Time (ms)
Time (ms)
图6-23. Large-Signal Positive Settling Time (10-V Step)
图6-24. Large-Signal Negative Settling Time (10-V Step)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±9 V, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
RI
2 k
RF
2 k
+9 V
–9 V
+9 V
RL
CL
CL
–9 V
Time (100 ns/div)
Time (100 ns/div)
G = +1, CL = 100 pF
G = –1, CL = 100 pF
图6-25. Small-Signal Step Response (100 mV)
图6-26. Small-Signal Step Response (100 mV)
Time (400 ns/div)
Time (400 ns/div)
图6-27. Large-Signal Step Response
图6-28. Large-Signal Step Response
60
50
40
30
20
10
0
–90
ISC, Source
ISC, Sink
–100
–110
–120
–130
–140
–150
RL = 2 k
RL = 5 k
10k
10
100
1k
100k
–75 –50 –25
0
25
50
75
100 125 150
Frequency (Hz)
Temperature (°C)
VOUT = 3 VRMS
G = +1
Short-circuiting may cause thermal shutdown;
see Application Information section
图6-30. Channel Separation vs Frequency
图6-29. Short Circuit Current vs Temperature
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7 Detailed Description
7.1 Overview
The OPA4H014-SEP low-power, JFET-input operational amplifier features superior drift performance and low
input bias current. Additional features include capacitive load stability, an output current limit, phase-reversal
protection, and thermal protection. The rail-to-rail output swing and input range that includes V– allows for the
low-noise characteristics of JFET amplifiers while also interfacing to modern, single-supply, precision ADCs and
DACs.
节7.2 shows the simplified diagram of the OPA4H014-SEP.
7.2 Functional Block Diagram
V+
Pre-Output Driver
OUT
IN–
IN+
V–
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7.3 Feature Description
7.3.1 Capacitive Load and Stability
The dynamic characteristics of the OPA4H014-SEP are optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50
Ω, for example) in series with the output.
7.3.2 Output Current Limit
The output current of the OPA4H014-SEP is limited by internal circuitry to 36 mA (sourcing) and –30 mA
(sinking), to protect the device if the output is accidentally shorted. This short-circuit current depends on
temperature.
7.3.3 Phase-Reversal Protection
The OPA4H014-SEP family has internal phase-reversal protection. Many FET- and bipolar-input op amps exhibit
a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input circuitry of the OPA4H014-SEP prevents phase
reversal with excessive common-mode voltage; instead, the output limits into the appropriate rail.
7.3.4 Thermal Protection
Although the output current of the OPA4H014-SEP is limited by internal protection circuitry, accidental shorting of
one or more output channels of a device can result in excessive heating. For instance, when an output is shorted
to midsupply, the typical short-circuit current of 36 mA leads to an internal power dissipation of over 300 mW at a
supply of ±9 V.
To prevent excessive heating leading to device damage, the OPA4H014-SEP series has an internal thermal
shutdown circuit that shuts down the device if the die temperature exceeds approximately 180°C. When this
thermal shutdown circuit activates, a built-in hysteresis of 15°C makes sure that the die temperature must drop
to approximately 165°C before the device switches on again.
7.4 Device Functional Modes
The OPA4H014-SEP has a single functional mode and is operational when the power-supply voltage is greater
than 4.5 V (±2.25 V). The maximum power supply voltage for the OPA4H014-SEP is 18 V (±9 V).
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPA4H014-SEP is a unity-gain stable, operational amplifier with very low noise, input bias current, and input
offset voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors placed
close to the device pins. In most cases, 0.1-μF capacitors are adequate. Designers can easily use the rail-to-rail
output swing and input range that includes V– to take advantage of the low-noise characteristics of JFET
amplifiers while also interfacing to modern, single-supply, precision data converters.
8.1.1 Noise Performance
The OPA4H014-SEP contributes both a voltage noise component and a current noise component. The voltage
noise is commonly modeled as a time-varying component of the offset voltage. The current noise is modeled as
the time-varying component of the input bias current and reacts with the source resistance to create a voltage
component of noise. Therefore, the lowest noise op amp for a given application depends on the source
impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The
OPA4H014-SEP has both low voltage noise and extremely low current noise because of the FET input of the op
amp. As a result, the current noise contribution of the OPA4H014-SEP is negligible for any practical source
impedance, which makes it the better choice for applications with high source impedance.
方程式1 shows the calculation of the total circuit noise:
2
2
2
E
= e + i R
+ 4kTR
S
(1)
O
n
n S
where
• en = voltage noise
• In = current noise
• RS = source impedance
• k = Boltzmann's constant = 1.38 × 10–23 J/K
• T = temperature in kelvins (K)
For more details on calculating noise, see 节8.1.1.1.
10k
EO
1k
100
10
RS
OPA4H014-SEP
Resistor Noise
1
100
1k
10k
100k
)
1M
Source Resistance, RS
(
图8-1. Noise Performance of the OPA4H014-SEP in Unity-Gain Buffer Configuration
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8.1.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. The source impedance is usually fixed; consequently, select an op amp and feedback resistors that
minimize the respective contributions to the total noise.
图 8-2 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPA4H014-SEP means that its current noise contribution can be neglected.
Choose feedback resistor values that make these noise sources negligible. Low impedance feedback resistors
load the output of the amplifier. The equations for total noise are shown for both configurations.
A) Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
2
R2
R1
R2
R1
R2
R1
2
EO
2
en
2
2
es
e12 + e2
+
R1
1 +
1 +
=
+
EO
4kTRS
4kTR1
4kTR2
Where eS
=
= thermal noise of RS
= thermal noise of R1
= thermal noise of R2
RS
e1 =
e2 =
VS
B) Noise in Inverting Gain Configuration
Noise at the output:
R2
2
2
2
R2
R2
R2
R1 + RS
2
EO
2
2
2
e12 + e2
+
es
= 1 +
en
+
R1
R1 + RS
R1 + RS
EO
RS
4kTRS
4kTR1
4kTR2
Where eS
=
= thermal noise of RS
= thermal noise of R1
= thermal noise of R2
VS
e1 =
e2 =
Note: For the OPA4H014-SEP operational amplifier at 1 kHz, en = 5.1 nV/√Hz.
图8-2. Noise Calculation in Gain Configurations
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8.1.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is extremely
helpful. 图 8-3 shows an illustration of the ESD circuits contained in the OPA4H014-SEP (indicated by the larger
boxed area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
RF
TVS(2)
+VS
+V
ESD Current-
Steering
Diodes
RI
–IN
+IN
OUT
Op Amp
Core
(3)
RS
Edge-Triggered ESD
Absorption Circuit
RL
ID
+
–
(1)
VIN
–V
–VS
TVS(2)
(1) VIN = +VS + 500 mV.
(2) TVS: +VS(max) > VTVSBR (Min) > +VS
(3) Suggested value approximately 1 kΩ.
图8-3. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device has a trigger, or threshold voltage, that is greater than the normal operating voltage of the
OPA4H014-SEP but less than the device breakdown voltage level. When this threshold is exceeded, the
absorption device quickly activates and clamps the voltage across the supply rails to a safe level.
图 8-3 shows that when the operational amplifier connects into a circuit, the ESD protection components are
intended to remain inactive and not become involved in the application circuit operation. However, circumstances
may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs,
there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such
current flow occurs through steering diode paths and rarely involves the absorption device.
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图 8-3 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier,
and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise
to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, the answer depends on the supply characteristic while at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source through the current steering diodes. This state is
not a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance,
then the current through the steering diodes can become quite high. The current level depends on the ability of
the input source to deliver current, and any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be
added to the supply pins, as shown in 图 8-3. The Zener voltage must be selected such that the diode does not
turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
8.1.3 EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a
higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this
section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
• Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
• The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance
• EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input
pin with no complex interactions from other components or connecting PCB traces.
The EMIRR IN+ of the OPA4H014-SEP is plotted versus frequency as shown in 图8-4. If available, any dual and
quad op-amp device versions have nearly similar EMIRR IN+ performance. The OPA4H014-SEP unity-gain
bandwidth is 11 MHz. EMIRR performance less than this frequency denotes interfering signals that fall within the
op-amp bandwidth.
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120
100
80
60
40
20
0
PRF = –10 dBm
VS = ±9 V
VCM = 0 V
10
100
Frequency (MHz)
1k
10k
图8-4. OPA4H014-SEP EMIRR
For more information, see the EMI Rejection Ratio of Operational Amplifiers application report, available for
download from www.ti.com.
表 8-1 lists the EMIRR IN+ values for the OPA4H014-SEP at particular frequencies commonly encountered in
real-world applications. Applications listed in 表 8-1 may be centered on or operated near the particular
frequency shown. This information may be of special interest to designers working with these types of
applications, or working in other fields likely to encounter RF interference from broad sources, such as the
industrial, scientific, and medical (ISM) radio band.
表8-1. OPA4H014-SEP EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications
53.1 dB
Global system for mobile communications (GSM) applications, radio communication, navigation, GPS
(to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
72.2 dB
80.7 dB
86.8 dB
91.7 dB
96.6 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
8.1.4 EMIRR +IN Test Configuration
图 8-5 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the op-amp
noninverting input pin using a transmission line. The op amp is configured in a unity gain buffer topology with the
output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at the
op amp input causes a voltage reflection; however, this effect is characterized and accounted for when
determining the EMIRR IN+. The resulting dc offset voltage is sampled and measured by the multimeter. The
LPF isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
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Ambient temperature: 25 C
Low-Pass Filter
+VS
–VS
–
+
50 Ω
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
Sample
or
Average
Digital Multimeter
Not shown: 0.1-µF and
10-µF supply decoupling
图8-5. EMIRR +IN Test Configuration
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8.2 Typical Application
C5
1 nF
R4
2.94 k
R1
590
R3
499
–
TI Device
Output
C2
39 nF
Input
+
图8-6. 25-kHz Low-Pass Filter
8.2.1 Design Requirements
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPA4H014-SEP is an excellent choice to construct high-speed, high-precision active filters. 图 8-6 shows a
second-order, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the pass band
8.2.2 Detailed Design Procedure
图8-6 shows the infinite-gain multiple-feedback circuit for a low-pass network function. Use 方程式2 to calculate
the voltage transfer function.
-1 R1R3C2C5
Output
Input
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
2
1
3
4
3 4 2 5
(2)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by 方程式3:
R4
Gain =
R1
1
fC
=
1 R R C C
(
3 4 2 5
)
2p
(3)
Software tools are readily available to simplify filter design. The Filter Design Tool is a simple, powerful, and
easy-to-use active filter design program. The Filter Design Tool helps create optimized filter designs using a
selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the Design tools and simulation web page, the Filter Design Tool helps to
design, optimize, and simulate complete multistage active filter solutions within minutes.
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8.2.3 Application Curve
20
0
–20
–40
–60
100
1k
10k
100k
1M
Frequency (Hz)
图8-7. OPA4H014-SEP Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
8.3 Power Supply Recommendations
The OPA4H014-SEP op amp is used with single or dual supplies from an operating range of VS = 4.5 V (±2.25
V) to VS = 18 V (±9 V). This device does not require symmetrical supplies, but only a minimum supply voltage of
4.5 V (±2.25 V). For VS less than ±3.5 V, the common-mode input range does not include midsupply.
CAUTION
Supply voltages higher than 20 V can permanently damage the device; see 节6.1.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see 节8.4.
Key parameters are specified over the operating temperature range, TA = –55°C to +125°C.
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp.
Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in 图8-8, keep RF and RG
close to the inverting input to minimize parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
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• For best performance, clean the PCB following board assembly.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
8.4.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
RF
OUT A
OUT D
RG
GND
–IN A
+IN A
–IN D
+IN D
VIN
V+
V–
+IN B
+IN C
Use low-ESR,
ceramic bypass
capacitor
V+
V–
GND
GND
图8-8. Operational Amplifier Board Layout for Noninverting Configuration
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案，可降低开发成本并缩短上市时间。
9.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
备注
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
9.1.1.3 Filter Design Tool
The Filter Design Tool is a simple, powerful, and easy-to-use active filter design program. The Filter Design Tool
helps create optimized filter designs using a selection of TI operational amplifiers and passive components from
TI's vendor partners.
Available as a web-based tool from the Design tools and simulation web page, The Filter Design Tool helps to
design, optimize, and simulate complete multistage active filter solutions within minutes.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Compensate Transimpedance Amplifiers Intuitively application report
• Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis
• Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis
• Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters
• Texas Instruments, Op Amp Performance Analysis application bulletin
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report
• Texas Instruments, Feedback Plots Define Op Amp AC Performance application bulletin
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers Application Report application report
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
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Product Folder Links: OPA4H014-SEP
OPA4H014-SEP
ZHCSOR9A –NOVEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: OPA4H014-SEP
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA4H014PWSEP
OPA4H014PWTSEP
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
90
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
O4H01A
O4H01A
Samples
Samples
250
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA4H014PWTSEP
TSSOP
PW
14
250
180.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
OPA4H014PWTSEP
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA4H014PWSEP
14
90
530
10.2
3600
3.5
Pack Materials-Page 3
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