OPA547F/500G3 [TI]
具有关断功能的高电压、高电流运放 | KTW | 7 | -40 to 85;
| 型号： | OPA547F/500G3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有关断功能的高电压、高电流运放 | KTW | 7 | -40 to 85 放大器 运算放大器 放大器电路 |
| 文件： | 总36页 (文件大小：1139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBOS391–DECEMBER 2007
High-Voltage (100V), High-Current (50mA)
OPERATIONAL AMPLIFIERS, G = 1 Stable
1
FEATURES
DESCRIPTION
23
•
WIDE POWER-SUPPLY RANGE:
±5V (10V) to ±50V (100V)
The OPA454 is a low-cost operational amplifier with
high voltage (100V) and relatively high current drive
(25mA). It is unity-gain stable and has
gain-bandwidth product of 2.5MHz.
a
•
•
•
HIGH OUTPUT LOAD DRIVE: IO > ±50mA
WIDE OUTPUT VOLTAGE SWING: 1V to Rails
The OPA454 is internally protected against
over-temperature conditions and current overloads. It
is fully specified to perform over a wide power-supply
range of ±5V to ±50V or on a single supply of 10V to
100V. The status flag is an open-drain output that
allows it to be easily referenced to standard
low-voltage logic circuitry. This high-voltage op amp
provides excellent accuracy, wide output swing, and
is free from phase inversion problems that are often
found in similar amplifiers.
INDEPENDENT OUTPUT DISABLE OR
SHUTDOWN
•
•
WIDE TEMPERATURE RANGE: –40°C to +85°C
PACKAGES: SO and HSOP PowerPAD™
APPLICATIONS
•
•
TEST EQUIPMENT
AVALANCHE PHOTODIODE:
High-V Current Sense
The output can be independently disabled using the
Enable/Disable Pin that has its own common return
pin to allow easy interface to low-voltage logic
circuitry. This disable is accomplished without
disturbing the input signal path, not only saving power
but also protecting the load.
•
•
•
•
•
PIEZOELECTRIC CELLS
TRANSDUCER DRIVERS
SERVO DRIVERS
AUDIO AMPLIFIERS
HIGH-VOLTAGE COMPLIANCE CURRENT
SOURCES
Featured in a small exposed metal pad package, the
OPA454 is easy to heatsink over the extended
industrial temperature range, –40°C to +85°C.
•
GENERAL HIGH-VOLTAGE
REGULATORS/POWER
Status
Flag
Table 1. OPA454 RELATED PRODUCTS
V+
PRODUCT
DESCRIPTION
80V, 15mA
80V, 50mA
60V, 750mA
60V, 3A
(1)
Enable/Disable (E/D)
OPA445
-IN
OPA452
OPA547
OPA548
OPA549
OPA551
OPA567
OPA569
VO
OPA454
+IN
Enable/Disable Common
(E/D Com)
60V, 9A
V-
60V, 200mA
5V, 2A
5V, 2.4A
(1) The OPA445 is pin-compatible with the OPA445, except in
applications using the offset trim, and NC pins other than
open.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
OPA454
www.ti.com
SBOS391–DECEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
OPA454
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
OPA454
SO-8
DDA
OPA454
HSOP-20(2)
DWD
OPA454
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Available Q2, 2008.
ABSOLUTE MAXIMUM RATINGS(1)
OPA454
UNIT
V
Supply Voltage
VS = (V+) – (V–)
120
Signal Input Terminals, Voltage(2)
Signal Input Terminals, Current(2)
E/D to E/D Com Voltage
Output Short-Circuit(3)
(V–) – 0.3 to (V+) + 0.3
V
±10
mA
V
+5.5
ISC
TJ
Continuous
Operating Temperature
Storage Temperature
–55 to +125
–55 to +125
+150
°C
°C
°C
V
Junction Temperature
TJ
Human Body Model (HBM)
4000
ESD Rating:
Charged Device Model (CDM)
Machine Model (MM)
500
V
150
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3V beyond the supply rails should
be current limited to 10mA or less.
(3) Short-circuit to ground.
PIN ASSIGNMENTS
DWD PACKAGE(1)
DDA PACKAGE
SO-8 PowerPAD
HSOP-20 PowerPAD
(TOP VIEW)
(TOP VIEW)
E/D (Enable/Disable)
E/D Com (Enable/Disable Common)
1
2
3
4
8
7
6
5
V-
1
2
3
4
5
6
7
8
9
20 V-
PowerPAD(1)
Heat Sink
-IN
+IN
V-
NC(3)
19
NC(3)
V+
NC(3)
18 NC(3)
(Located on
bottom side)
OUT
V-
17 Status Flag
16 VOUT
Status Flag
PowerPAD(2)
Heat Sink
+IN
(Located on
top side)
NC(3)
15 V+
(1) PowerPAD is internally connected to V–.
Soldering the PowerPAD to the PCB is
always required, even with applications that
have low power dissipation.
-IN
NC(3)
14 NC(3)
13 NC(3)
E/D Com (Enable/Disable Common)
12 E/D (Enable/Disable)
11 V-
V- 10
(1) Available Q2, 2008.
(2) PowerPAD is internally connected to V–.
(3) NC = No internal connection
2
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): OPA454
OPA454
www.ti.com
SBOS391–DECEMBER 2007
ELECTRICAL CHARACTERISTICS: VS = ±50V
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP(1) = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
TYP
PARAMETER
CONDITIONS
IO = 0
MIN
MAX
UNIT
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature(2)
VOS
dVOS/dT
PSRR
±0.2
±1.6
25
±4
mV
±10
100
µV/°C
µV/V
vs Power Supply
VS = ±4V to ±60V, VCM = 0V
INPUT BIAS CURRENT
Input Bias Current
IB
IOS
en
±1.4
±100
pA
pA
vs Temperature
See Typical Characteristics
Input Offset Current
±0.2
±100
NOISE
Input Voltage Noise Density, f = 10Hz
Input Voltage Noise Density, f = 10kHz
f = 0.01Hz to 10Hz
300
35
nV/√Hz
nV/√Hz
µVPP
15
Current Noise Density, f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection
in
40
fA/√Hz
(3)
VCM
Linear Operation
(V–) + 2.5
100
See Note
146
(V+) – 2.5
V
CMRR
VS = ±50V, –25V ≤ VCM ≤ +25V
VS = ±50V, –45V ≤ VCM ≤ +45V
VS = ±50V, –25V ≤ VCM ≤ +25V
VS = ±50V, –45V ≤ VCM ≤ +45V
dB
dB
dB
dB
100
147
Over Temperature
Over Temperature
INPUT IMPEDANCE
Differential
80
88
72
82
1013 || 10
1013 || 9
Ω || pF
Ω || pF
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain(4)
AOL
(V–) + 1V < VO < (V+) – 1V,
RL = 49kΩ, IO = ±1mA
100
100
80
130
112
115
106
102
84
dB
dB
dB
dB
dB
dB
(V–) + 1V < VO < (V+) – 1V,
RL = 49kΩ, IO = ±1mA
(V–) + 1V < VO < (V+) – 2V,
RL = 4.8kΩ, IO = ±10mA
(V–) + 1V < VO < (V+) – 2V,
RL = 4.8kΩ, IO = ±10mA
(V–) + 2V < VO < (V+) – 3V,
RL = 1880Ω, IO = ±25mA
(V–) + 2V < VO < (V+) – 3V,
RL = 1880Ω, IO = ±25mA
(1) TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package.
(2) See typical characteristic curve, Offset Voltage Drift Production Distribution (Figure 14).
(3) Typical range is (V–) + 1.5V to (V+) – 1.5V.
(4) Measured using low-frequency (<10Hz) ±49V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 24).
Copyright © 2007, Texas Instruments Incorporated
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OPA454
www.ti.com
SBOS391–DECEMBER 2007
ELECTRICAL CHARACTERISTICS: VS = ±50V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
TYP
PARAMETER
FREQUENCY RESPONSE(5)
CONDITIONS
MIN
MAX
UNIT
Gain-Bandwidth Product
Slew Rate
Full-Power Bandwidth(6)
Settling Time: ±0.1%(7)
Settling Time: ±0.01%(7)
GBW
SR
Small-Signal
2.5
13
35
3
MHz
V/µs
kHz
µs
G = ±1, VO = 80V Step, RL = 3.27kΩ
G = ±1, VO = 20V Step
G = ±5 or ±10, VO = 80V Step
10
µs
VS = +40.6V/–39.6V, G = ±1,
f = 1kHz, VO = 77.2VPP
Total Harmonic Distortion + Noise(8)
THD+N
VO
0.0008
%
OUTPUT
Voltage Output Swing From Rail(9)
RL = 49kΩ, AOL ≥ 100dB, IO = 1mA
RL = 4.8kΩ, AOL ≥ 100dB, IO = 10mA
RL = 1880Ω, AOL ≥ 80dB, IO = 26mA
Depends on Circuit Conditions
(V–) + 1
(V–) + 1
(V–) + 2
(V+) – 1
(V+) – 2
(V+) – 3
V
V
V
Continuous Current Output, dc
See Figure 6
+120/–150
Maximum Peak Current Output, Current
Limit(10)
IO
mA
Over Temperature
Capacitive Load Drive(5)
Open-Loop Output Impedance
Output Disabled
+140/–170
200
mA
pF
Ω
CLOAD
RO
See Figure 5
Output Capacitance
Feedthrough Capacitance(11)
18
pF
fF
150
STATUS FLAG PIN (Referenced to E/D Com)(12)
Status Flag Delay
Enable → Disable
Disable → Enable
Over-Current Delay(13)
Over-Current Recovery Delay(13)
6
4
µs
µs
µs
µs
15
10
Junction Temperature
TJ
Alarm (status flag high)
+150
+130
°C
°C
V
Return to Normal Operation (status flag low)
Output Voltage(5)
Normal Operation
E/D Com + 2
RL = 100Ω During Thermal Overdrive,
(V+) – 2.5
V
Alarm
(5) See Typical Characteristic curves.
(6) See typical characteristic curve, Maximum Output Voltage vs Frequency (Figure 12).
(7) See the Applications Information section, Settling Time.
(8) Supplies reduced to allow closer swing to rails due to test equipment limitations. See typical characteristic curve Total Harmonic
Distortion + Noise vs Temperature (Figure 30 and Figure 31) for additional power levels.
(9) See typical characteristic curve, Output Voltage Swing vs Output Current (Figure 11).
(10) Measured using low-frequency (<10Hz) ±49V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 24).
(11) Measured using Figure 1.
(12) 100kΩ pull-up resistor to (V+). E/D common to (V–). Status flag indicates an over temperature or over-current condition.
(13) See Typical Characteristic curves for current limit behavior.
4
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): OPA454
OPA454
www.ti.com
SBOS391–DECEMBER 2007
ELECTRICAL CHARACTERISTICS: VS = ±50V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TP = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted.
OPA454
TYP
PARAMETER
E/D (ENABLE/DISABLE) PIN
CONDITIONS
MIN
MAX
UNIT
E/D Pin, Referenced to E/D Com Pin(14)(15)
High (output enabled)
VSD
VSD
Pin Open or Forced High
Pin Forced Low
E/D Com + 2.5
E/D Com
E/D Com + 5
V
V
E/D Com +
0.65
Low (output disabled)
Output Disable Time
Output Enable Time
E/D COM PIN
4
3
µs
µs
Voltage Range
(V–)
±5
(V+) – 5
V
POWER SUPPLY
Specified Range
VS
IQ
±50
V
V
Operating Voltage Range
Quiescent Current
±50
4
IO = 0
3.2
mA
µA
Quiescent Current in Shutdown Mode
TEMPERATURE RANGE
Specified Range
IO = 0, VE/D = 0.65V
150
210
TA
TA
–40
–55
+85
°C
°C
Operating Range
+125
Thermal Resistance, Junction-to-Case(16)
SO-8 PowerPAD(17)
HSOP-20
θJC
10
10
°C/W
°C/W
Thermal Resistance, Junction-to-Ambient
SO-8 PowerPAD(17)
HSOP-20(18)
θJA
24/52
65
°C/W
°C/W
(14) See typical characteristic curve, IENABLE vs VENABLE (Figure 46).
(15) High enables the outputs.
(16) TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package.
(17) Lower value is for land area of 1-inch × 1-inch, 2-oz copper. Upper value is for exposed-pad sized area of 1-oz copper.
(18) Value given is for DW-20 package, similar to the DWD package, but without an exposed pad. Actual θJA may approach θJC by selection
of external heatsink and airflow.
+50V
E/D
VOUT
RL
50kW
100VPP
E/D Com
10kHz
-50V
Figure 1. Feedthrough Capacitance Circuit
Copyright © 2007, Texas Instruments Incorporated
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OPA454
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SBOS391–DECEMBER 2007
TYPICAL CHARACTERISTICS
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
PHASE MARGIN vs TEMPERATURE
180
160
140
120
100
80
70
65
60
55
50
45
40
VCM = -45V
VCM = 0V
CL = 30pF
VCM = +45V
Phase
60
40
CL = 100pF
CL = 200pF
Gain
RLOAD = 4.87kW
CLOAD = 50pF
VCM = 0V
20
0
-20
0.1
1
10
100
1k
10k 100k
1M
10M
-75
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Exposed Thermal Pad Temperature (°C)
Figure 2.
Figure 3.
UNITY-GAIN BANDWIDTH
vs TEMPERATURE
OPEN-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1M
100k
10k
1k
VCM = 0V
VCM = 45V
100
10
VCM = -45V
CL = 30pF. 100pF, and 200pF
-50 -25 25
1
-75
0
50
75
100
125
1
10
100
1k
10k
100k
1M
10M
Exposed Thermal Pad Temperature (°C)
Frequency (Hz)
Figure 4.
Figure 5.
OPEN-LOOP GAIN vs PEAK-LOAD CURRENT
OPEN-LOOP GAIN vs TEMPERATURE
140
130
120
110
100
90
140
130
120
110
100
90
VS = ±50V
RLOAD = 48kW
VOUT = ±49V (dc)
IOUT = ±1mA
VS = ±15V
RL = 4.8kW
VOUT = +48V, -49V (dc)
IOUT = +9.9mA to -10mA
80
VS = ±4V
80
70
RL = 1.88kW
RL = 900W
VOUT = +47V, -48V (dc)
IOUT = ±25mA
70
VOUT = +45V, -47V (dc)
IOUT = 50mA to -52mA
60
60
50
0
5
10
15
20
25
-75
-50
-25
0
25
50
75
100
125
Peak IL (mA)
Exposed Thermal Pad Temperature (°C)
Figure 6.
Figure 7.
6
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OPA454
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SBOS391–DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
POWER-SUPPLY AND COMMON-MODE
REJECTION RATIO vs TEMPERATURE
COMMON-MODE REJECTION RATIO vs FREQUENCY
140
120
100
80
60
40
20
0
PSRR
120
100
80
60
40
20
0
1kHz, CMRR
10kHz, CMRR
VCM = -45V
100kHz, CMRR
1.3MHz, CMRR
VCM = +45V
VCM = +45V
VCM = -45V
0.001
0.01
0.1
1
10
100
1k
10k
-75
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Exposed Thermal Pad Temperature (°C)
Figure 8.
Figure 9.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(Measured When Status Flag Transitions From Low to High)
50
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
140
-55°C
120
100
80
60
40
20
0
49
48
47
+125°C
+85°C
+25°C
-47
-48
-49
-50
-55°C
1
10
100
1k
10k
100k
1M
0
10
20
IOUT (mA)
Figure 11.
30
40
50
Frequency (Hz)
Figure 10.
DDA PACKAGE OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
120
100
80
60
40
20
0
Average = 111mV
VOUT = ±49V
RL = 4.8kW
Standard Deviation = 142mV
IOUT = ±10mA
0
50
100
150
200
250
300
-4000 -3000 -2000 -1000
0
1000 2000 3000 4000
Frequency (kHz)
Offset Voltage (mV)
Figure 12.
Figure 13.
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SBOS391–DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
DDA PACKAGE OFFSET VOLTAGE
DRIFT PRODUCTION DISTRIBUTION
DDA PACKAGE, SOLDER-ATTACHED, VOS TC SHIFT
Average = 0.34mV/°C
Average = 1.57mV/°C
Standard Deviation = 0.44mV/°C
Standard Deviation = 0.84mV/°C
0
1
2
3
4
5
6
7
8
9
10
Offset Voltage Drift (mV/°C)
Output Voltage Shift (mV/°C)
Figure 14.
Figure 15.
OFFSET VOLTAGE WARMUP
(60 Devices)
DDA PACKAGE, SOLDER-ATTACHED, VOS SHIFT
200
Average = 48mV/°C
Standard
Deviation = 28mV/°C
150
100
50
VS = ±50V
PowerPAD Attached
9in ´ 12in 0.062
0
Layer Metal PCB FR10
-50
-100
-150
-200
100s/div
Offset Voltage Shift (mV)
Figure 16.
Figure 17.
QUIESCENT CURRENT PRODUCTION DISTRIBUTION
QUIESCENT CURRENT vs SUPPLY VOLTAGE
3.25
3.20
3.15
3.10
3.05
3.00
2.95
2.90
0
10 20 30 40 50 60 70 80 90 100 110 120
Total Supply Voltage (V)
Quiescent Current (mA)
Figure 18.
Figure 19.
8
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OPA454
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SBOS391–DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
SHUTDOWN CURRENT vs TEMPERATURE
5 Typical Units Shown
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
200
180
160
140
120
100
-75
-50
-25
0
25
50
75
100
125
-75
-50
-25
0
25
50
75
100
125
Exposed Thermal Pad Temperature (°C)
Exposed Thermal Pad Temperature (°C)
Figure 20.
Figure 21.
INPUT BIAS CURRENT vs TEMPERATURE
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
20
100
10
1
15
10
5
0
-5
Common-Mode Voltage Range
-10
-15
-20
0.1
-50 -40 -30 -20 -10
0
10
20
30
40
50
-75
-50
-25
0
25
50
75
100
125
VCM (V)
Exposed Thermal Pad Temperature (°C)
Figure 22.
Figure 23.
STATUS FLAG VOLTAGE vs TEMPERATURE
(E/D Com Connected to V–)(1)
CURRENT LIMIT vs TEMPERATURE
200
180
160
140
120
100
8
7
6
5
4
3
2
1
0
RP = 20kW, IP = 5mA
Sourcing
RP = 50kW, IP = 2mA
RP = 100kW, IP = 100mA
RP = 200kW, IP = 50mA
Sinking
-75
-50
-25
0
25
50
75
100
125
-75
-50
-25
0
25
50
75
100
125
Exposed Thermal Pad Temperature (°C)
Exposed Thermal Pad Temperature (°C)
Figure 24.
Figure 25.
(1) See Figure 57 in the Applications Information section.
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SBOS391–DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
MAXIMUM POWER DISSIPATION
vs TEMPERATURE WITH MINIMUM ATTACH AREA
SLEW RATE vs TEMPERATURE
2.0
1.5
1.0
0.5
0
16
15
14
13
12
11
10
9
SO-8 PowerPAD:
TJ(max) = +125°C
TJ (+125°C max) = TA + [(|VS| - |VO|) IO ´ qJA
JA = +52°C/W, SO-8 PowerPAD
]
q
G = +1
(1in ´ 0.5in [25.4mm x 12.7mm]
Heat-Spreader, 1oz Copper)
VS = ±45V
VIN = 80V Step
RLOAD = 4.8kW
TJ = +25°C + (1.93W ´ 52°C/W) = +125°C
8
-50
-25
0
25
50
75
100
125
-75
-50
-25
0
25
50
75
100
125
Exposed Thermal Pad Temperature (°C)
Exposed Thermal Pad Temperature (°C)
Figure 26.
Figure 27.
INPUT VOLTAGE NOISE SPECTRAL DENSITY
0.01Hz TO 10Hz INPUT VOLTAGE NOISE
1000
100
10
1
20s/div
10
100
1k
10k
100k
Frequency (Hz)
Figure 28.
Figure 29.
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.0030
0.0025
0.0020
0.0015
0.0010
0.0005
0
G = +10
G = +1
RI = 4.75kW
RI = 4.75kW
VPP = 38.6V
VPP = 38.6V
VS = +41.6, -40.6
VS = +40.6,
-39.6
VS = -55, +55
VS = -49, +50
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Figure 30.
Frequency (Hz)
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
VIN
VIN
G = +1
G = +1
TC = +60°C
CLOAD = 50pF
VCM = +30V
RF = 10kW
TC = +105°C
CLOAD = 50pF
VCM = +30V
RF = 10kW
VOUT
VOUT
Time (1ms/div)
Time (1ms/div)
Figure 33.
Figure 32.
LARGE-SIGNAL STEP RESPONSE
SMALL-SIGNAL STEP RESPONSE
TC = +125°C
TC = +25°C
TC = -55°C
G = +2
TC = +100°C
CLOAD = 100pF
VCM = +40V
RF = 10kW
G = +1
CLOAD = 100pF
VCM = 0V
VIN
VOUT
RF = 0W
Time (2.5ms/div)
Time (500ns/div)
Figure 34.
Figure 35.
GAIN PEAKING vs CLOAD
(G = +1, VCM = 0V)(2)
STEP RESPONSE
2.0
1.5
180
160
140
120
100
80
RF = 0W
G = +1
RF = 10kW
TC = -55°C
G = +2
1.0
TC = +25°C
TC = +85°C
0.5
TC = +125°C
0
-0.5
-1.0
-1.5
-2.0
60
40
RF = 10kW
CLOAD = 100pF, 125°C
20
VCM = +40V
0
0
100
200
CLOAD (pF)
Figure 37.
300
400
500
1ms/div
Figure 36.
(2) See Application section Unity-Gain Noninverting Configuration.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
GAIN PEAKING vs CLOAD
(G = +2, RF = 10kΩ, VCM = 0V)
GAIN OF +1 vs FREQUENCY(3)
30
25
20
15
10
5
10
8
CF = 0pF
TA = +25°C
TC = -55°C
TC = +25°C
CL = 200pF
CF = 2.5pF
CF = 5pF
6
CL = 100pF
TC = +85°C
4
TC = +125°C
2
0
-2
-4
-6
RF = 10kW, CF = 50pF
RF = 0W
0
CL = 50pF
1M
-5
0
100
200
300
400
500
10k
100k
10M
CLOAD (pF)
Frequency (Hz)
Figure 38.
Figure 39.
SETTLING TIME, POSITIVE STEP
GAIN OF +2 vs FREQUENCY(4)
(20V Step, Gain = 1, RF = 10kΩ)(5)(6)
20
15
0.08
0.06
0.04
0.02
0
10
8
TA = +25°C
CL = 500pF
V1 (Inverting)
10
6
5
4
V2 (Noninverting)
CL = 50pF
0
2
-5
-0.02
-0.04
-0.06
-0.08
0
-10
-15
-20
-2
-4
-6
CF = 0pF
CF = 2.5pF
CF = 5pF
VIN
Time (1ms/div)
10k
100k
Frequency (Hz)
1M
10M
Figure 40.
Figure 41.
(3) See Application section Unity-Gain Noninverting Configuration.
(4) See Application section Unity-Gain Noninverting Configuration.
(5) See the Settling Time section.
(6) The grid for voltage at V1 and V2 is scaled 20mV or 0.1% per division.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
SETTLING TIME, NEGATIVE STEP
(20V Step, Gain = 1, RF = 10kΩ)(7)(8)
ENABLE RESPONSE TIME
20
15
0.08
0.06
0.04
0.02
0
VIN
10
OUT
5
0
V2 (Noninverting)
V1 (Inverting)
Status Flag
-5
-0.02
-0.04
-0.06
-0.08
-10
-15
-20
Enable
Time (1ms/div)
Time (1ms/div)
Figure 42.
Figure 43.
DISABLE RESPONSE TIME
ENABLE RESPONSE
OUT
OUT
Status Flag
Status Flag
Enable
Enable
Time (1ms/div)
Time (1ms/div)
Figure 44.
Figure 45.
IENABLE vs VENABLE
ENABLE/DISABLE THRESHOLD vs TEMPERATURE
1.00
10
0
0.95
0.90
0.85
0.80
0.75
0.70
-40°C
-10
-20
-30
+25°C
+85°C
0
1
2
3
4
5
-75
-50
-25
0
25
50
75
100
125
VENABLE (V)
Temperature (°C)
Figure 46.
Figure 47.
(7) See the Settling Time section.
(8) The grid for voltage at V1 and V2 is scaled 20mV or 0.1% per division.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
ILIMIT SHOWING FLAG DELAY
ILIMIT SHOWING FLAG DELAY
(TP = +25°C)(10)
(TP = +125°C)(9)
60
50
40
30
20
10
0
200
150
100
50
60
50
40
30
20
10
0
150
100
50
VFLAG
VFLAG
IOUT
0
0
-50
-100
-150
-200
IOUT
-50
-100
-150
RP = 100kW
RP = 100kW
-10
-10
10ms/div
10ms/div
Figure 48.
Figure 49.
ILIMIT SHOWING FLAG DELAY
APPLY LOAD
(25mA Sink Response)
(TP = –55°C)(11)
60
50
40
30
20
10
0
150
100
50
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
+125°C
VFLAG
+50V
0.988VPP
0.01Hz
+85°C
+25°C
-55°C
-
OPA454
+
2Hz
2ms Pulse
-50V
Mercury
Wetted
Relay
IOUT
0
-50
-100
-150
-200
RP = 100kW
-10
-0.2
10ms/div
10ms/div
Figure 50.
Figure 51.
REMOVE LOAD
(25mA Sink Response)
APPLY LOAD
(25mA Source Response)
0.2
0
0.2
0
-0.2
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
+50V
+50V
-
0.988VPP
0.01Hz
0.988VPP
0.01Hz
-
+125°C
+85°C
+25°C
-55°C
+125°C
OPA454
+
OPA454
+
2Hz
2Hz
+85°C
+25°C
-55°C
2ms Pulse
2ms Pulse
-50V
-50V
Mercury
Wetted
Relay
Mercury
Wetted
Relay
10ms/div
10ms/div
Figure 52.
Figure 53.
(9) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.
(10) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.
(11) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown.
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TYPICAL CHARACTERISTICS (continued)
At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted.
REMOVE LOAD
(25mA Source Response)
1.6
POWER ON
+125°C
+85°C
+25°C
-55°C
RL = 1.8kW
V+
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VOUT
+50V
0.988VPP
0.01Hz
-
Flag
OPA454
+
2Hz
2ms Pulse
0
-50V
Mercury
Wetted
Relay
Delay in V- is due to
V-
test equipment.
Power supplies may be
applied in any sequence.
-0.2
20ms/div
10ms/div
Figure 54.
Figure 55.
POWER OFF
V+
RL = 1.8kW
VOUT
Flag
0
V-
20ms/div
Figure 56.
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APPLICATIONS INFORMATION
POWER SUPPLIES
Figure 57 shows the OPA454 connected as a basic
noninverting amplifier. The OPA454 can be used in
virtually any ±5V to ±50V op amp configuration. It is
especially useful for supply voltages greater than
36V.
The OPA454 may be operated from power supplies
up to ±50V or a total of 100V with excellent
performance. Most behavior remains unchanged
throughout the full operating voltage range.
Parameters that vary significantly with operating
voltage are shown in the Typical Characteristics.
Power-supply terminals should be bypassed with
0.1µF (or greater) capacitors, located near the
power-supply pins. Be sure that the capacitors are
appropriately rated for the power-supply voltage
used.
Some applications do not require equal positive and
negative output voltage swing. Power-supply voltages
do not need to be equal. The OPA454 can operate
with as little as 10V between the supplies and with up
to 100V between the supplies. For example, the
positive supply could be set to 90V with the negative
supply at –10V, or vice-versa (as long as the total is
less than or equal to 100V).
V+
IP
0.1mF
V+
(1)
RP
R2
R1
R1
R2
G = 1+
INPUT PROTECTION
Status
Flag
The OPA454 has increased protection against
damage caused by excessive voltage between op
amp input pins or input pin voltages that exceed the
power supplies; external series resistance is not
needed for protection. Internal series JFETs limit
input overload current to a non-destructive 4mA, even
with an input differential voltage as large as 120V.
Additionally, the OPA454 has dielectric isolation
between devices and the substrate. Therefore, the
amplifier is free from the limitations of junction
isolation common to many IC fabrication processes.
V+
-IN
VOUT
VOUT
OPA454
E/D
+IN
VIN
RL
E/D Com
V-
0.1mF
V-
V-
(1) Pull-up resistor with at least 10µA (choose
RP = 1MΩ with V+ = 50V for IP = 50µA).
LOWERING OFFSET VOLTAGE AND DRIFT
Figure 57. Basic Noninverting Amplifier
Configuration
The OPA454 can be used with an OPA735 zero-drift
series op amp to create a high-voltage op amp circuit
that has very low input offset temperature drift. This
circuit is shown in Figure 58.
Low Offset, 5mV, Drift,
0.05mV/°C, Self-Zeroing Op Amp
Gain 1st = 4.9V/V
High-Voltage Op Amp
Gain 2nd = 9.45V/V
R1, 2nd
R2, 2nd
10kW
84.5kW
R1, 1st
R2, 1st
10kW
39.1kW
V+
2nd Stage, +50V
V+
1st Stage, +5V
VOUT 2nd Stage
VOUT 1st Stage
OPA454
OPA735
A2, 2nd Stage
RLOAD
10kW
A1, 1st Stage
VOUT 1st Stage ±4.9V, Max
V-
VG = ±1V
2nd Stage, -50V
V-
1st Stage, -5V
VOUT 2nd Stage ±46V (92VPP), Max
VINPUT = ±1VPP
Figure 58. Two-Stage, High-Voltage Op Amp Circuit With Very Low Input Offset Temperature Drift
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INCREASING OUTPUT CURRENT
R1
R2
The OPA454 drives an output current of a few
milliamps to greater than 50mA while maintaining
(1)
RS
MASTER
10W
good op amp performance. See Figure
7 for
A1
OPA454
open-loop gain versus temperature at various output
current levels.
VIN
In applications where the 25mA output current is not
sufficient to drive the required load, the output current
can be increased by connecting two or more
OPA454s in parallel, as Figure 59 shows. Amplifier
A1 is the master amplifier and may be configured in
virtually any op amp circuit. Amplifier A2, the slave, is
(1)
RS
10W
OPA454
A2
RL
SLAVE
configured as
a unity-gain buffer. Alternatively,
external output transistors can be used to boost
output current. The circuit in Figure 60 is capable of
supplying output currents up to 1A, with the
transistors shown.
(1) RS resistors minimize the circulating current that always flows
between the two devices because of VOS errors.
Figure 59. Parallel Amplifiers Increase Output
Current Capability
UNITY-GAIN NONINVERTING
CONFIGURATION
When in the noninverting unity-gain configuration, the
OPA454 has more gain peaking with increasing
positive common-mode voltage and increasing
temperature. It has less gain peaking with more
negative common-mode voltage. As with all op amps,
gain peaking increases with increasing capacitive
load. A resistor and small capacitor placed in the
feedback path can reduce gain peaking and increase
stability.
R1
R2
+50V
NPN
TIP29C, MJL21194,
MJE15003, MJL3281
CF
R4
(1)
R3
0.2W
-IN
V+
(2)
VOUT
20W
VO(3) = VOUT - ILRL
OPA454
+IN
VIN
R5
V-
RL IL
0.2W
PNP
TIP30C, MJL21193,
MJE15004, MJL1302A
-50V
(1) Provides current limit for OPA454 and allows the amplifier to drive the load when the output is between +0.7V and –0.7V.
(2) Op amp VOUT swings from +47V to –48V.
(3) VO swings from +44.1V to –45.1V at IL = 1A.
Figure 60. External Output Transistors Boost Output Current Greater Than 1A
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INPUT RANGE
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
TA = +25°C
The OPA454 is specified to give linear operation with
input swing to within 2.5V of either supply. Generally,
a gain of +1 is the most demanding configuration.
Figure 61 and Figure 62 show output behavior as the
input swings to within 0V of the rail, using the circuit
shown in Figure 64. Figure 63 shows the behavior
with an input signal that swings beyond the specified
input range to within 1V of the rail, also using the
circuit in Figure 64. Notice that the beginning of the
phase reversal effect may be reduced by inserting
series resistance (RS) in the connection to the
positive input. Note that VOUT does not swing all the
way to the opposite rail.
VOUT
RS = 50kW
VOUT
VIN
RS = 0W
f = 1kHz
V-
0
20
40
60
Time (ms)
80
100
50.5
Figure 63. Output Voltage With Input Voltage
Down To (V–) + 1V
V+
TA = +25°C
50.0
49.5
49.0
48.5
48.0
47.5
47.0
VIN
f = 1kHz
VOUT
RS = 50kW
RF
10kW
V+ = +50V
RS
VOUT
VOUT
OPA454
RS = 0W
RL
4.8kW
V- = -50V
VIN
0
20
40
60
Time (ms)
80
100
Figure 61. Output Voltage With Input Voltage Up
To V+
Figure 64. Input Range Test Circuit
OUTPUT RANGE
-46.0
TA = +25°C
The OPA454 is specified to swing to within 1V of
either supply rail with a 49kΩ load while maintaining
excellent linearity. Swing to the rail decreases with
increasing output current. The OPA454 can swing to
within 2V of the negative rail and 3V of the positive
rail with a 1.88kΩ load. The typical characteristic
curve, Output Voltage Swing vs Output Current
(Figure 11), shows this behavior in detail.
-46.5
VOUT
-47.0
RS = 0W
-47.5
VOUT
-48.0
RS = 50kW
-48.5
-49.0
VIN
-49.5
f = 1kHz
-50.0
V-
-50.5
0
20
40
60
Time (ms)
80
100
Figure 62. Output Voltage With Input Voltage
Down To V–
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OPEN-LOOP GAIN LINEARITY
SETTLING TIME
Figure 65 shows the nonlinear relationship of AOL and
output voltage. As Figure 65 shows, open-loop gain is
lower with positive output voltage levels compared to
negative voltage levels. Specifications in the
Electrical Characteristics table are based upon the
average gain measured at both output extremes.
The circuit in Figure 66 is used to measure the
settling time response. The left half of the circuit is a
standard, false-summing junction test circuit used for
settling time and open-loop gain measurement. R1
and R2 provide the gain and allow for measurement
without connecting a scope probe directly to the
summing junction, which can disturb proper op amp
function by causing oscillation.
AOL is a Function of VOUT and ILOAD
TP = +25°C
The right half of the circuit looks at the combination of
both inverting and noninverting responses. R5 and R6
remove the large step response. The remaining
voltage at V2 shows the small-signal settling time that
is centered on zero. This test circuit can be used for
incoming inspection, real-time measurement, or in
RL = 1880W, 1mV/div
RL = 900W, 2mV/div
74dB
89dB
designing
compensation
circuits
in
system
applications.
106dB
20
RL = 4.87kW, 200mV/div
Table 2. Settling Time Measurement Circuit
Configuration Using Different Gain Settings for
Figure 66
-50 -40 -30 -20 -10
0
10
30
40
50
Output Voltage (V)
GAIN
COMPONENT
R1 (Ω)
1
5
10
1k
1k
9k
1k
8
Figure 65. Differential Input Voltage (+IN to –IN)
versus Output Voltage
10k
10k
10k
∞
2k
2k
4k
1k
16
R3 (Ω)
R7 (Ω)
R8 (Ω)
VIN (VPP
)
20
Inverting Response
Measured Here, V1
R2
R1
10kW
R4
Combination of Both
Inverting and
Noninverting Responses, V2
R3
R7
R8
10kW
R5
R6
-IN
-IN
10kW
10kW
VOUT
VOUT
OPA454
OPA454
+IN
+IN
A1
A2
VIN
Figure 66. Settling Time Test Measurement Circuit
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avoided to maximize reliability. It is always best to
provide proper heat-sinking (either by a physical plate
or by airflow) to remain considerably below the
thermal shutdown threshold. For longest operational
life of the device, keep the junction temperature
below +125°C.
ENABLE AND E/D Com
If left disconnected, E/D Com is pulled near V–
(negative supply) by an internal 10µA current source.
When left floating, ENABLE is held approximately 2V
above E/D Com by an internal 1µA source. Even
though active operation of the OPA454 results when
the ENABLE and E/D Com pins are not connected, a
moderately fast, negative-going signal capacitively
coupled to the ENABLE pin can overpower the 1µA
pull-up current and cause device shutdown. This
behavior can appear as an oscillation and is
encountered first near extreme cold temperatures. If
the enable function is not used, a conservative
approach is to connect ENABLE through a 30pF
THERMAL PROTECTION
Figure 68 shows the thermal shutdown behavior of a
socketed OPA454 that internally dissipates 1W.
Unsoldered and in a socket, θJA of the DDA package
is typically +128°C/W. With the socket at +25°C, the
output stage temperature rises to the shutdown
temperature of +150°C, which triggers automatic
thermal shutdown of the device. The device remains
in thermal shutdown (output is in a high-impedance
state) until it cools to +130°C where it again is
powered. This thermal protection hysteresis feature
typically prevents the amplifier from leaving the safe
operating area, even with a direct short from the
output to ground or either supply. The rail-to-rail
supply voltage at which catastrophic breakdown
occurs is typically 135V at +25°C. However, the
absolute maximum specification is 120V, and the
OPA454 should not be allowed to exceed 120V under
any condition. Failure as a result of breakdown,
caused by spiking currents into inductive loads
(particularly with elevated supply voltage), is not
prevented by the thermal protection architecture.
capacitor to
a low impedance source. Another
alternative is the connection of an external current
source from V+ (positive supply) sufficient to hold the
enable level above the shutdown threshold. Figure 67
shows a circuit that connects ENABLE and E/D Com.
Choosing RP to be 1MΩ with a +50V positive power
supply voltage results in IP = 50µA.
V+
(Positive Op Amp Supply)
IP
RP
DVDD
(Digital Supply)
40
20
140
120
100
80
V+
5V Logic
VOUT
-IN
E/D
0
VOUT
OPA454
E/D Com
+IN
-20
-40
-60
-80
-100
V-
60
40
20
VFLAG
0
V-
(Negative Op Amp Supply)
-120
-20
0
200
400
600
800
1000
(ms)
Figure 67. ENABLE and E/D Com
10kW
100kW
CURRENT LIMIT
+50V
+2.5V
10Hz Square Wave
Figure 24 and Figure 48 to Figure 50 show the
current limit behavior of the OPA454. Current limiting
is accomplished by internally limiting the drive to the
output transistors. The output can supply the limited
current continuously, unless the die temperature rises
to +150°C, which initiates thermal shutdown. With
adequate heat-sinking, and use of the lowest possible
supply voltage, the OPA454 can remain in current
limit continuously without entering thermal shutdown.
Although qualification studies have shown minimal
parametric shifts induced by 400 hours of thermal
shutdown cycling, this mode of operation should be
RP
1MW
VFLAG
Flag
VOUT
V+
-IN
VOUT
OPA454
+IN
E/D Com
V-
625W
-50V
Figure 68. Thermal Shutdown
20
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OPA454
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SBOS391–DECEMBER 2007
POWER DISSIPATION
HEATSINKING
Power dissipation depends on power supply, signal,
and load conditions. For dc signals, power dissipation
is equal to the product of the output current times the
voltage across the conducting output transistor,
PD = IL (VS – VO). Power dissipation can be
minimized by using the lowest possible power-supply
voltage necessary to assure the required output
voltage swing.
Power dissipated in the OPA454 causes the junction
temperature to rise. For reliable operation, junction
temperature should be limited to +125°C, maximum.
Maintaining a lower junction temperature always
results in higher reliability. Some applications require
a heatsink to assure that the maximum operating
junction temperature is not exceeded. Junction
temperature can be determined according to
Equation 1:
For resistive loads, the maximum power dissipation
occurs at a dc output voltage of one-half the
power-supply voltage. Dissipation with ac signals is
lower because the root-mean square (RMS) value
determines heating. Application Bulletin SBOA022
explains how to calculate or measure dissipation with
unusual loads or signals. For constant current source
circuits, maximum power dissipation occurs at the
minimum output voltage, as Figure 69 shows.
TJ = TA + PD qJA
(1)
Package thermal resistance, θJA, is affected by
mounting techniques and environments. Poor air
circulation and use of sockets can significantly
increase thermal resistance to the ambient
environment. Many op amps placed closely together
also increase the surrounding temperature. Best
thermal performance is achieved by soldering the op
amp onto a circuit board with wide printed circuit
traces to allow greater conduction through the op
amp leads. Increasing circuit board copper area to
approximately 0.5in2 decreases thermal resistance;
however, minimal improvement occurs beyond 0.5in2,
as shown in Figure 70.
The OPA454 can supply output currents of 25mA and
larger. Supplying this amount of current presents no
problem for some op amps operating from ±15V
supplies. However, with high supply voltages, internal
power dissipation of the op amp can be quite high.
Operation from a single power supply (or unbalanced
power supplies) can produce even greater power
dissipation because a large voltage is impressed
across the conducting output transistor. Applications
with high power dissipation may require a heatsink, or
heat spreader.
For additional information on determining heatsink
requirements, consult Application Bulletin SBOA021
(available for download at www.ti.com).
60
50
40
30
20
10
0
R1
R2
100kW
10kW
V1
+50V
V+
-IN
VOUT
OPA454
V-
+IN
R5
R3
100kW
R4
100W
9.9kW
-50V
V2
0
0.5
1.0
1.5
2.0
2.5
3.0
Copper Area (inches2), 2 oz
IL
RL
IL = [(V2 - V1)/R5] (R2/R1)
= (V2 - V1)/1kW
Figure 70. Thermal Resistance versus Circuit
Board Copper Area
Compliance Voltage Range = +47V, -48V
NOTE: R1 = R3 and R2 = R4 + R5.
Figure 69. Precision Voltage-to-Current Converter
with Differential Inputs
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SBOS391–DECEMBER 2007
PowerPAD THERMALLY-ENHANCED
PACKAGES
BOTTOM-SIDE PowerPAD PACKAGE
The OPA454 SO-8 PowerPAD is a standard-size
SO-8 package constructed using downset
The OPA454 comes in SO-8 and HSOP-20
PowerPAD versions that provide an extremely low
thermal resistance (θJC) path between the die and the
exterior of the package. These packages feature an
exposed thermal pad. This thermal pad has direct
thermal contact with the die; thus, excellent thermal
performance is achieved by providing a good thermal
path away from the thermal pad.
a
leadframe upon which the die is mounted, as
Figure 71a shows. This arrangement results in the
lead frame being exposed as a thermal pad on the
underside of the package. The thermal pad on the
bottom of the IC can then be soldered directly to the
PCB, using the PCB as a heatsink. In addition,
plated-through holes (vias) provide a low thermal
resistance heat flow path to the back side of the PCB.
This architecture enhances the OPA454 power
dissipation capability significantly, eliminates the use
of bulky heatsinks and slugs traditionally used in
thermal packages, and allows the OPA454 to be
easily mounted using standard PCB assembly
techniques. NOTE: Because the SO-8 PowerPAD is
pin-compatible with standard SO-8 packages, the
OPA454 is a drop-in replacement for operational
amplifiers in existing sockets. Soldering the
bottom-side PowerPAD to the PCB is always
required, even with applications that have low power
dissipation. Soldering the device to the PCB provides
the necessary thermal and mechanical connection
between the leadframe die pad and the PCB.
TOP-SIDE PowerPAD PACKAGE
The OPA454 DWD, HSOP-20, PowerPAD package
has the exposed pad on the top side of the package,
as Figure 71b shows. The top-side thermal pad can
be used with commercially available heat-sinks and
moving air to dissipate heat. The use of an external
top-side heat-sink increases the effective surface
area of the package face, which increases convection
and radiation off the top surface of the package.
Top-side heatsinking also avoids unnecessary
heating of the printed circuit board (PCB), and
permits installation of other PCB components onto
the side opposite of the OPA454.
Leadframe (Copper Alloy)
IC (Silicon)
Die Attach (Epoxy)
External Heatspreader
Die Pad
Thermal
Paste
Die
Chip
Attach
Power Transistor
Leadframe Die Pad
Exposed at Base of the Package
(Copper Alloy)
Mold Compound (Plastic)
Board
a) SO-8 PowerPAD cross-section view.
b) HSOP-20 PowerPAD cross-section view.
Figure 71. Cross-Section Views of a PowerPAD Package
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OPA454
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SBOS391–DECEMBER 2007
BOTTOM-SIDE PowerPAD LAYOUT
GUIDELINES
area to be soldered; thus, wicking is not a
problem.
6. Connect all holes to the internal power plane of
the correct voltage potential (V–).
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
must be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
7. When connecting these holes to the plane, do not
use the typical web or spoke via connection
methodology. Web connections have a high
thermal resistance connection that is useful for
slowing the heat transfer during soldering
operations, making the soldering of vias that have
plane connections easier. In this application,
however, low thermal resistance is desired for the
most efficient heat transfer. Therefore, the holes
under the OPA454 PowerPAD package should
make the connections to the internal plane with a
package into either
a ground plane or other
heat-dissipating device. Soldering the PowerPAD to
the PCB is always required, even with applications
that have low power dissipation. Follow these steps
to attach the device to the PCB:
1. The PowerPAD must be connected to the most
negative supply voltage on the device, V–.
complete
connection
around
the
entire
circumference of the plated-through hole.
2. Prepare the PCB with a top-side etch pattern.
There should be etching for the leads as well as
etch for the thermal pad.
8. The top-side solder mask should leave the
terminals of the package and the thermal pad
area exposed. The bottom-side solder mask
should cover the holes of the thermal pad area.
This masking prevents solder from being pulled
away from the thermal pad area during the reflow
process.
3. Use of thermal vias improves heat dissipation,
but are not required. The thermal pad can
connect to the PCB using an area equal to the
pad size with no vias, but externally connected to
V–.
9. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
4. Place recommended holes in the area of the
thermal pad. Recommended thermal land size
and thermal via patterns for the SO-8 DDA
package are shown in the thermal land pattern
mechanical drawing appended at the end of this
document. These holes should be 13 mils in
diameter. Keep them small, so that solder wicking
through the holes is not a problem during reflow.
The minimum recommended number of holes for
the SO-8 PowerPAD package is five.
10. With these preparatory steps in place, the
PowerPAD IC is simply placed in position and run
through the solder reflow operation as any
standard
surface-mount
component.
This
preparation results in a properly installed part.
For detailed information on the PowerPAD package,
including thermal modeling considerations and repair
procedures, see technical brief SLMA002 PowerPAD
Thermally-Enhanced Package, available for download
at www.ti.com.
5. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These vias help dissipate the heat
generated by the OPA454 IC. These additional
vias may be larger than the 13-mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
Copyright © 2007, Texas Instruments Incorporated
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OPA454
www.ti.com
SBOS391–DECEMBER 2007
TYPICAL APPLICATIONS
Figure 72 and Figure 73 illustrate the OPA454 in a programmable voltage source and a bridge circuit,
respectively.
+95V
0.1mF
45.3kW
0-2mA
V+
DAC8811
or
-IN
DAC7811
OPA454
+IN
VOUT = 0V to +91V
Protects DAC
During Slewing
RL
V-
0.1mF
-5V
Figure 72. Programmable Voltage Source
R1
R2
R3
1kW
9kW
10kW
R4
10kW
+50V
+50V
Up To
195V
-IN
-IN
V+
V+
VOUT
A1
VOUT
A2
MASTER
OPA454
OPA454
SLAVE
+IN
+IN
VIN
Piezo(1)
Crystal
V-
V-
±4V
-50V
-50V
(1) For transducers with large capacitance, stabilization may become an issue. Be certain that the Master amplifier is stable before stabilizing
the Slave amplifier.
Figure 73. Bridge Circuit Doubles Voltage for Exciting Piezo Crystals
24
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OPA454
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SBOS391–DECEMBER 2007
Figure 74 uses three OPA454s to create
a
V+
high-voltage instrumentation amplifier. VCM ± VSIG
must be between (V–) + 2.5V and (V+) – 2.5V. The
maximum supply voltage equals ±50V or 100V total.
V1
OPA454
A1
R4
R5
Figure 75 uses three OPA454s to measure current in
a high-side shunt application. VSUPPLY must be
greater than VCM. VCM must be between (V–) + 2.5V
and (V+) – 2.5V. Adhering to these restrictions keeps
V1 and V2 within the voltage range required for linear
operation of the OPA454. For example, if V+ = 50V
and V– = 50V, then V1 = +47.5V (maximum) and
V2 = –47.5V (minimum). The maximum supply
voltage equals ±50V, or 100V total.
V-
R2
V+
VSIG
OPA454
VOUT
(1)
R1
A3
R2
V-
R6
R7
V+
See Figure 76 and Figure 79 for example circuits that
use the OPA454 in an output voltage boost
configurations in three and six op amp output stages,
respectively.
OPA454
A2
V2
VOUT = (1 + 2R2/R1) (V2 - V1)
VCM
V-
(1) The linear input range is limited by the output swing on the
input amplifiers, A1 and A2.
Figure 74. High-Voltage Instrumentation Amplifier
RSHUNT
V+
Plus
or
V1
Load
VSUPPLY
Minus
OPA454
(1)
A1
R4
R5
V-
R2
V+
OPA454
VOUT
R1
(2)
A3
R2
V-
R7
R6
V+
OPA454
(1)
A2
V2
VOUT = (1 + 2R2/R1) (V2 - V1)
V-
(1) To increase the linear input voltage range, configure A1 and A2 as unity-gain followers.
(2) The linear input range is limited by the output swing on the input amplifiers, A1 and A2.
Figure 75. High-Voltage Instrumentation Amplifier for Measuring High-Side Shunt
Copyright © 2007, Texas Instruments Incorporated
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SBOS391–DECEMBER 2007
+100V
+100V
10kW
10kW
+100V
V+
+100V
V+
100kW
100kW
V01
V04
A4
OPA454
OPA454
A1
V-
V-
10kW
190kW
10kW
200kW
100kW
100kW
VLOAD = +97V, -98V
VLOAD = +97V, -98V
VIN
V+
V+
A3
VOUT
(195VPP
)
VOUT
(195VPP)
OPA454
OPA454
A6
RLOAD
RLOAD
V-
V-
3.75kW
3.75kW
VIN
10kW
10kW
100kW
100kW
V+
V+
V02
V05
OPA454
OPA454
A5
A2
V-
V-
100kW
100kW
-100V
-100V
-100V
-100V
a) Noninverting, G = +20V/V
b) Inverting, G = -20V/V
Figure 76. Output Voltage Boost With +97V, –98V (195VPP) Across Load Connected to Ground (3 Op Amp
Output Stage, see Figure 77 and Figure 78)
100
100
80
6
75
50
V01
VOUT
4
60
VIN
VLOAD
40
25
2
20
0
0
0
-20
-40
-60
-80
-100
-25
-50
-75
-100
V02
-2
-4
-6
Time (10ms/div)
Time (20ms/div)
Figure 78. 3.75kΩ Load to Ground
Figure 77. 195VPP On 3.75kΩ Load to Ground
G = +20, 3 OPA454s, 100V Supplies
20kHz, Uses 3 OPA454s, 100V Supplies
(Note SR of 18V/µs, which is slightly higher than
the specified 13V/µs due to tracking of the
power-supply voltage)
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OPA454
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SBOS391–DECEMBER 2007
+100V
+100V
10kW
10kW
+120V
V+
+120V
V+
100kW
100kW
OPA454
OPA454
A1
A4
V-
V-
10kW
190kW
200kW
10kW
100kW
RLOAD
100kW
V+
V+
7.5kW
(+97V, -98V)
(-98V, +97V)
OPA454
OPA454
V-
A3
A6
VLOAD
(±195V, 390VPP
)
V-
10kW
10kW
VIN
100kW
100kW
V+
V+
OPA454
OPA454
A2
A5
V-
V-
100kW
100kW
-100V
-100V
-100V
-100V
Figure 79. Output Voltage Boost With ±195V (390VPP) Across Bridge-Tied Load (6 Op Amps, see
Figure 80 and Figure 81)
200
VLOAD
200
150
100
50
6
150
100
50
4
VOUT
VIN
2
0
0
0
-50
-50
-100
-150
-200
-2
-4
-100
-150
-200
-6
Time (10ms/div)
Time (20ms/div)
Figure 81. 7.5kΩ Load
Figure 80. 390VPP Across 7.5kΩ Load
20kHz, Uses 6 OPA454s, 100V Supplies
G = +20, 6 OPA454s, 100V Supplies
(Note SR of 34V/µs, which is significantly higher
than the specified 13V/µs due to tracking of the
power-supply voltage)
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Product Folder Link(s): OPA454
OPA454
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SBOS391–DECEMBER 2007
A red light emitting diode (LED) was used to generate
Figure 84.
R1
R2
25kW
25kW
V1
Gain of the avalanche photodiode (APD) is adjusted
by changing the voltage across the APD. Gain starts
to increase when reverse voltage is increased beyond
130V for this API diode. Figure 85 shows this
structure.
VOUT = V2 - V1
OPA454
R3
R4
25kW
25kW
6V
14
12
10
8
V2
VOUT
Figure 82. High-Voltage Difference Amplifier
6
4
HIGH-COMPLIANCE VOLTAGE CURRENT
SOURCES
VLED
0V
2
0
This section describes four different applications
utilizing high compliance voltage current sources with
differential inputs. Figure 69 and Figure 83 illustrate
the different applications.
-2V
-2
5ms/div
Figure 84. Avalanche Photodiode Circuit
25kW
25kW
V1
OPA454
A1
25kW
25kW
R
V2
OPA454
A2
IO
Load
IO = (V2 - V1)/R
Figure 83. Differential Input Voltage-to-Current
Converter for Low IOUT
28
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OPA454
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SBOS391–DECEMBER 2007
R7
R1
10kW
90kW
+100V
+100V
R2
R4
V+
OPA454
V-
1kW
100kW
V+
OPA454
V-
A2
A1
+100V
VOUT = 100 ´ RSENSE ´ ID
V+
VOUT
OPA454
+100V
A4
+
Gain Adjust Voltage
2.5V to 9.5V
RSENSE
V-
V1
100W
+100V
V+
R8
198kW
R3
1kW
OPA454
R9
A3
4.9kW
V-
R5
100kW
LM4041D
Adjusted for 2.0V
100W
APD
R10
LED
VLED
3.1kW
-200V
Advanced Photonix, Inc.
SD 036-70-62-531
Digi-Key
Example Circuit For Reverse Biasing APD
(130V to 280V, max)
SD 036-70-62-531
Figure 85. APD Gain Adjustment Using the OPA454, High-Voltage Op Amp
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Dec-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
OPA454AIDDA
ACTIVE
SO
Power
PAD
DDA
8
75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA454AIDDAR
ACTIVE
SO
Power
PAD
DDA
8
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA454AIDWD
PREVIEW
PREVIEW
HSOP
HSOP
DWD
DWD
20
20
75
TBD
TBD
Call TI
Call TI
Call TI
Call TI
OPA454AIDWDR
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jan-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
OPA454AIDDAR
DDA
8
SITE 41
330
12
6.4
5.2
2.1
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jan-2008
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
OPA454AIDDAR
DDA
8
SITE 41
346.0
346.0
29.0
Pack Materials-Page 2
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Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright 2008, Texas Instruments Incorporated
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