OPA593DNTT [TI]
85V、100µV、宽带宽 (10MHz)、高输出电流 (250mA) 精密运算放大器 | DNT | 12 | -40 to 125;
| 型号： | OPA593DNTT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 85V、100µV、宽带宽 (10MHz)、高输出电流 (250mA) 精密运算放大器 | DNT | 12 | -40 to 125 放大器 运算放大器 |
| 文件： | 总41页 (文件大小：3030K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA593
ZHCSMD4C –JANUARY 2022 –REVISED DECEMBER 2022
OPA593 85V、250mA 输出电流、精密、功率运算放大器
1 特性
3 说明
• 宽电源范围：
OPA593 是一款高压 (85V) 、高精度、宽带宽
(10MHz)、高输出电流 (250mA)、单位增益稳定功率运
算放大器。
– 8V (±4V) 至85V (±42.5V)
• 低失调电压：±20µV
• 低失调电压漂移：±0.4µV/°C
• 高输出电流：250mA
• 宽增益带宽：10MHz
• 高压摆率：45V/µs，上升
• 低噪声：10 kHz 时为7nV/√Hz
• 多路复用器友好型输入
• 轨到轨输出
OPA593 采用激光修整技术来改善失调电压（20µV，
典型值）和失调电压温漂（0.4µV/°C，典型值），因
此无需校准。该器件具有多路复用器友好型 输入，可
实现电源轨的差分输入电压范围，并有助于提高多通道
系统的稳定性能。
可以使用一个外部电阻器来限制具有指定精度的电流，
从而提供更为精确的测量。在过流或过热条件下，该器
件会通过状态标志来指示错误操作。所含的禁用功能用
于关断该器件，从而实现省电并将输出置于高阻抗状
态。
• 静态电流：
– 启用：3.25mA
– 禁用：250μA
• 额定电流限制精度
• 过热和过流标志
• 温度范围：–40°C 至+125°C
• 封装：12 引脚WSON
该器件具有单位增益稳定特性，可用作高阻抗缓冲器。
宽带宽和高压摆率可实现高信号增益。由于具有高输出
电流和容性驱动，该器件能够驱动用于提供更高系统电
流的外部场效应晶体管(FET)，例如在数字电源中。
2 应用
封装信息
封装(1)
• 半导体测试
• 半导体制造
• 可编程直流电源
• LCD 测试
封装尺寸（标称值）
器件型号
OPA593
DNT (WSON, 12)
4.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• CT 和PET 扫描仪
1.47 k
10 k
45 V
260
220
180
140
100
60
GND
–
+
Output
+
–
20
–5 V
Input
-20
-60
GND
-100
-140
-180
-220
-260
配置为增益8 的输出驱动器
0
50 100 150 200 250 300 350 400 450 500 550
Current Limit Resistor, RCL (kꢀ)
输出电流与电流限制电阻器配置
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS659
OPA593
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ZHCSMD4C –JANUARY 2022 –REVISED DECEMBER 2022
Table of Contents
7.4 Device Functional Modes..........................................26
8 Application and Implementation..................................27
8.1 Application Information............................................. 27
8.2 Typical Application.................................................... 27
8.3 Power Supply Recommendations.............................30
8.4 Layout....................................................................... 30
9 Device and Documentation Support............................33
9.1 Device Support......................................................... 33
9.2 接收文档更新通知..................................................... 33
9.3 支持资源....................................................................33
9.4 Trademarks...............................................................33
9.5 Electrostatic Discharge Caution................................33
9.6 术语表....................................................................... 33
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................22
7.1 Overview...................................................................22
7.2 Functional Block Diagram.........................................22
7.3 Feature Description...................................................23
Information.................................................................... 33
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (August 2022) to Revision C (November 2022)
Page
• 从预告信息（预发布）更改为量产数据（正在供货）.........................................................................................1
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5 Pin Configuration and Functions
E/D Com
NC
1
2
3
4
5
6
12
11
10
9
E/D
ILIMIT
–IN
+IN
V+
Thermal Pad
OUT
NC
8
Thermal Flag
Current Flag
V–
7
Not to scale
图5-1. DNT (12-Pin WSON) Package, Top View
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
Current Flag
E/D
NO.
7
Output
Input
Input
Input
Input
Input
Overcurrent status flag
Enable and disable
Enable and disable common
Current limit
12
1
E/D Com
ILIMIT
+IN
11
4
Noninverting input
Inverting input
3
–IN
NC
2, 5
9
No internal connection
Output
—
OUT
Output
Output
Thermal Flag
8
Overtemperature status flag
The thermal pad is internally connected to V–. The thermal pad must be soldered to a
printed-circuit board (PCB) connected to V–, even with applications that have low
power dissipation.
Thermal Pad
Thermal pad
—
V+
10
6
Power
Power
Positive (highest) power supply
Negative (lowest) power supply
V–
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
(V–) –0.3
V–
MAX
93
UNIT
V
VS
Supply voltage, VS = (V+) –(V–)
Signal input pin voltage(2)
Status flag and E/D pin voltage(3)
ILIMIT pin voltage
(V+) + 0.3
E/D Com + 7
(V–) + 3.35
3
V
V
V
Status flag pins current(3)
Input current, all pins(2)
mA
mA
±10
Output short circuit current(4)
Continuous
150
TJ
Junction temperature
°C
°C
–55
–65
TSTG
Storage temperature
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input, E/D Com, and output pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the
supply rails must be current-limited to less 10 mA.
(3) Status flag and E/D pins are diode clamped to E/D Com –0.3 V and E/D Com + 7 V. Pullup signals must be current-limited to < 3 mA.
(4) Short-circuit to ground.
6.2 ESD Ratings
VALUE
±1500
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
8
NOM
MAX
85
UNIT
Single supply voltage
Dual supply voltage
VS
V
Supply voltage, VS = (V+) –(V–)
±4
±42.5
5.5
VE/D
E/D pin voltage(1)
V
V
Status flag pin voltage(1)
Current limit set
5.5
ILIMIT
TA
±25
±250
125
mA
°C
Operating temperature
–40
(1) Recommended voltage must be current limited to below the listed value in the Absolute Maximum Ratings.
6.4 Thermal Information
OPA593
THERMAL METRIC(1)
DNT (WSON)
12 PINS
40.8
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
℃/W
℃/W
℃/W
℃/W
℃/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
30.2
17.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
17.7
ψJB
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OPA593
THERMAL METRIC(1)
DNT (WSON)
12 PINS
4.3
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
℃/W
(1) For information on traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics
at VS = 85 V, TA = 25°C, RL = 10 kΩ to mid-supply, IOUT limit set to 100 mA, and VCM = VOUT = mid-supply (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
±20
±100
±2
µV
Input offset voltage
drift
dVOS/dT
±0.4
µV/°C
TA = –40°C to +125°C
Power supply
rejection ratio
PSRR
VS = ±4 V to ±42.5 V
0.1
±1
1
µV/V
INPUT BIAS CURRENT
±10
±350
±5
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to +85°C
TA = –40°C to +125°C
±1
±5
±250
±1
IOS
Input offset current TA = –40°C to +85°C
TA = –40°C to +125°C
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz
f = 10 Hz
2.9
75
10
7
µVPP
Input voltage noise
density
en
f = 1 kHz
nV/√Hz
f = 10 kHz
Current noise
f = 1 kHz
in
12
fA/√Hz
density
INPUT VOLTAGE
Common-mode
voltage
VCM
Linear operation
V
(V–) –0.1
124
(V+) –3.5
140
124
Common-mode
rejection
CMRR
dB
(V–) ≤VCM ≤(V+) –3.5 V
TA = –40°C to
+125°C
108
INPUT IMPEDANCE
Differential
1013 || 0.3
1013 || 9.4
Ω || pF
Ω || pF
Common-mode
OPEN-LOOP GAIN
134
130
132
130
130
125
140
140
140
135
135
130
(V–) + 0.3 V < VO < (V+) –0.3
V,
RL = 10 kΩ
TA = –40°C to
+125°C
Open-loop voltage (V–) + 1 V < VO < (V+) –1 V,
AOL
dB
TA = –40°C to
+125°C
gain
RL = 2 kΩ
(V–) + 2.5 V < VO < (V+) –2.5
V,
RL = 600 Ω
TA = –40°C to
+125°C
FREQUENCY RESPONSE
Gain-bandwidth
product
GBW
10
MHz
Rising
Falling
45
35
SR
Slew rate
Gain = ±1, VOUT = 70-V step
V/µs
µs
tS
Settling time
2.9
To ±0.01%, gain = –1, VOUT = 70-V step, CL = 100 pF
RL = 600 Ω
RL = 2 kΩ
–105
–110
Total harmonic
distortion + noise
Gain = +1, VOUT = 70 VPP
f = 1 kHz
,
THD+N
OUTPUT
dB
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6.5 Electrical Characteristics (continued)
at VS = 85 V, TA = 25°C, RL = 10 kΩ to mid-supply, IOUT limit set to 100 mA, and VCM = VOUT = mid-supply (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
No load
MIN
TYP
10
MAX
25
UNIT
IOUT = 50 mA
IOUT = 100 mA
IOUT = 250 mA
50
125
750
2
mV
Voltage output
swing from rail
VO
RCL = 0 Ω connected to V–
400
1.2
V
Continuous output
current, dc
±250
See typical curves
See typical curves
mA
VS = 85 V, RCL = 2.29 kΩ, ILIMIT = 250 mA
Capacitive load
drive
CLOAD
ZO
pF
Open-loop output
impedance
Ω
Output impedance
100
56
Output disabled, V–< VOUT < V+
MΩ
Output capacitance Output disabled
CURRENT LIMIT
ILIMIT Current limit
pF
±25
17
±250
29
mA
ILIMIT = 25 mA,
VLIMIT = 3.33 V
ILIMIT = 50 mA,
VLIMIT = 2.98 V
42
94
55
107
263
45
Sourcing,
RL = 10 Ω to mid-supply
ILIMIT = 100 mA,
VLIMIT = 2.27V
ILIMIT = 250 mA,
VLIMIT = 0.14 V
237
10
Current limit
accuracy(3)
mA
ILIMIT = 25 mA,
VLIMIT = 3.33 V
ILIMIT = 50 mA,
VLIMIT = 2.98 V
35
68
Sinking,
RL = 10 Ω to mid-supply
ILIMIT = 100 mA,
VLIMIT = 2.27 V
85
115
275
ILIMIT = 250 mA,
VLIMIT = 0.14 V
235
Resistor set, RCL connected between ILIMIT pin and V–
(3.687 V × 4000) / (56.7 kΩ + RCL)
Current limit
equation
mA
Voltage set, VLIMIT connected to ILIMIT pin and
referenced to V–
4000 × (3.687 V –VLIMIT) / 56.7 kΩ
STATUS FLAG PIN (Referenced to E/D Com)
Overcurrent delay
Status flag delay
10
10
µs
°C
Overcurrent recovery delay
Alarm (status flag high)
170
150
Thermal shutdown
Return to normal operation (status flag low)
Status flag output
voltage
Normal operation
See typical curves
E/D PIN
VE/D
Enable, pin open or forced high(2)
Disable, pin forced low(2)
E/D Com + 1.5
E/D Com
E/D Com + 5.5
E/D Com + 0.5
E/D voltage(1)
V
IE/D
E/D input current
Output disable time
Output enable time
50
12
18
µA
µs
µs
E/D COM PIN
E/D Com voltage
POWER SUPPLY
V
(V–)
(V+) –6
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6.5 Electrical Characteristics (continued)
at VS = 85 V, TA = 25°C, RL = 10 kΩ to mid-supply, IOUT limit set to 100 mA, and VCM = VOUT = mid-supply (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.75
4
UNIT
3.25
IQ
Quiescent current
mA
TA = –40°C to +125°C
Output disabled
0.25
(1) For information on the output enable and disable feature see 节7.3.4.
(2) Enable and disable voltage thresholds can vary near the maximum temperature range; see 图6-67.
(3) Proper output swing headroom is necessary to maintain current limit accuracy; see 图6-19. to 图6-34.
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6.6 Typical Characteristics
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
12
9
6
3
0
-100
-75
-50
-25
0
25
50
75
100
300
10
Offset Voltage (µV)
VS = 85 V, 160 typical units
VS = 8 V, 160 typical units
图6-2. Input Offset Production Distribution
图6-1. Input Offset Production Distribution
25
20
15
10
5
0
-300 -225 -150
-75
0
75
150
225
Offset Voltage (µV)
TA = 125ºC, 30 typical units
图6-4. Input Offset Production Distribution
TA = −40ºC, 30 typical units
图6-3. Input Offset Production Distribution
40
30
20
10
0
50
40
30
20
10
0
-10
-5
0
5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Input Bias Current (pA)
Offset Voltage Drift (µV/°C)
360 typical units
TA = –40ºC to +125ºC
图6-6. Input Bias Current Production Distribution
图6-5. Input Offset Voltage Drift Distribution
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
100
75
100
75
50
50
25
25
0
0
-25
-50
-75
-100
-25
-50
-75
-100
-42
-33
-24
-15
-6
3
12
21
30
39
8
18
28
38
48
58
68
78 85
Common-Mode voltage (V)
Supply Voltage (V)
5 typical units
图6-7. Input Offset Voltage vs Common-Mode Voltage
图6-8. Input Offset Voltage vs Supply Voltage
100
180
160
140
120
0.001
0.01
0.1
VS = 85 V
VS = 8 V
75
50
25
0
-25
-50
-75
-100
1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-50
-25
0
25
50
75
100
125
Temperature (°C)
5 typical units
图6-9. Input Offset Voltage vs Temperature
图6-10. CMRR vs Temperature
180
160
140
120
0.001
0.01
0.1
40
20
0
-20
1
-40
-50
-25
0
25
50
75
100
125
-40
-30
-20
-10
0
10
20
30
39
Temperature (°C)
Common-Mode Voltage (V)
图6-11. PSRR vs Temperature
图6-12. Input Bias Current vs Common-Mode Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
10
5
180
160
140
120
100
80
IB-
IB+
IOS
CMRR
PSRR−
PSRRꢀ
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
60
0.002
0.001
40
0.0005
20
0.0002
0.0001
0
-40
-15
10
35
60
85
110 125
10m 100m
1
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
Temperature (°C)
图6-13. Input Bias Current and Current Offset vs Temperature
图6-14. PSRR and CMRR vs Frequency
180
160
140
0.001
0.01
0.1
RL = 10 kꢀ
RL = 2 kꢀ
RL = 600 ꢀ
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图6-15. Open-Loop Gain and Phase vs Frequency
图6-16. Open Loop Gain vs Temperature
60
110
100
90
80
70
60
50
40
30
20
10
0
VS = 85 V
VS = 8 V
40
20
0
-20
-40
Gain = −1 V/V
Gain = ꢀ1 V/V
-60
Gain = ꢀ10 V/V
Gain = ꢀ100 V/V
-80
100
1
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
图6-18. Maximum Output Voltage vs Frequency
图6-17. Closed-Loop Gain vs Frequency
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
4
3.5
3
-1.5
-2
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
-2.5
-3
2.5
2
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
-3.5
-4
1.5
0
20
40
60
80
100
120
140
140
140
0
20
40
60
80
100
120
140
Output current (mA)
Output current (mA)
VS = 8 V, ILIMIT = 100 mA
VS = 8 V, ILIMIT = 100 mA
图6-20. Output Voltage vs Output Sinking Current
图6-19. Output Voltage vs Output Sourcing Current
24
-21.5
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
23.5
-22
-22.5
-23
23
22.5
22
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
-23.5
-24
21.5
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
Output current (mA)
Output current (mA)
VS = 48 V, ILIMIT = 100 mA
VS = 48 V, ILIMIT = 100 mA
图6-21. Output Voltage vs Output Sourcing Current
42.5
图6-22. Output Voltage vs Output Sinking Current
42
41.5
41
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
40.5
40
0
20
40
60
80
100
120
Output current (mA)
VS = 85 V, ILIMIT = 100 mA
VS = 85 V, ILIMIT = 100 mA
图6-24. Output Voltage vs Output Sinking Current
图6-23. Output Voltage vs Output Sourcing Current
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
4
3
1
0
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
2
-1
-2
-3
-4
1
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
0
-1
0
50
100
150
200
250
300
0
50
100
150
200
250
300 325
Output Current (mA)
Output Current (mA)
VS = 8 V, ILIMIT = 250 mA
图6-25. Output Voltage vs Output Sourcing Current
24
VS = 8 V, ILIMIT = 250 mA
图6-26. Output Voltage vs Output Sinking Current
-19
-20
-21
-22
-23
-24
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
23
22
21
20
19
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
0
50
100
150
200
250
300
0
50
100
150
200
250
300 325
Output Current (mA)
Output Current (mA)
VS = 48 V, ILIMIT = 250 mA
图6-27. Output Voltage vs Output Sourcing Current
43
VS = 48 V, ILIMIT = 250 mA
图6-28. Output Voltage vs Output Sinking Current
-37.5
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
42
41
40
39
38
37
-38.5
-39.5
-40.5
-41.5
-42.5
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
0
50
100
150
200
250
300 325
0
50
100
150
200
250
300 325
Output Current (mA)
Output Current (mA)
VS = 85 V, ILIMIT = 250 mA
VS = 85 V, ILIMIT = 250 mA
图6-29. Output Voltage vs Output Sourcing Current
图6-30. Output Voltage vs Output Sinking Current
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
4
3
4
3
ILIMIT = 50 mA
ILIMIT = 100 mA
ILIMIT = 150 mA
ILIMIT = 200 mA
ILIMIT = 250 mA
2
2
1
1
0
0
-1
-2
-3
-4
ILIMIT = 50 mA
ILIMIT = 100 mA
ILIMIT = 150 mA
ILIMIT = 200 mA
ILIMIT = 250 mA
-1
-2
-3
0
25 50 75 100 125 150 175 200 225 250 275 300
Output Current (mA)
0
25 50 75 100 125 150 175 200 225 250 275 300
Output Current (mA)
VS = 8 V, RL = 10 Ωto mid-supply
VS = 8 V, RL = 10 Ωto mid-supply
图6-31. Output Voltage vs Current Limit Set
图6-32. Output Voltage vs Current Limit Set
44
42
40
38
36
34
32
-32.5
-35
ILIMIT = 50 mA
ILIMIT = 100 mA
ILIMIT = 150 mA
ILIMIT = 200 mA
ILIMIT = 250 mA
-37.5
-40
ILIMIT = 50 mA
ILIMIT = 100 mA
ILIMIT = 150 mA
ILIMIT = 200 mA
ILIMIT = 250 mA
-42.5
0
25 50 75 100 125 150 175 200 225 250 275 300
Output Current (mA)
0
25 50 75 100 125 150 175 200 225 250 275 300
Output Current (mA)
VS = 85 V, RL = 10 Ωto mid-supply
VS = 85 V, RL = 10 Ωto mid-supply
图6-33. Output Voltage vs Output Sourcing Current
25
图6-34. Output Voltage vs Output Sinking Current
20
TA = −40°C
TA = 25°C
TA = 85°C
TA = 125°C
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
20
15
10
5
15
10
5
0
0
-5
-5
20 40 60 80 100 120 140 160 180 200 220 240 260
Current Limit Set (mA)
20 40 60 80 100 120 140 160 180 200 220 240 260
Current Limit Set (mA)
VS = 8 V, RL = 10 Ωto mid-supply
VS = 8 V, RL = 10 Ωto mid-supply
图6-35. Output Sourcing Current Error vs Current Limit Set
图6-36. Output Sinking Current Error vs Current Limit Set
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
15
13
11
9
8
7
TA = -40°C
TA = 25°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 85°C
6
5
4
3
7
2
5
1
3
0
-1
-2
-3
-4
-5
1
-1
-3
-5
20 40 60 80 100 120 140 160 180 200 220 240 260
Current Limit Set (mA)
20 40 60 80 100 120 140 160 180 200 220 240 260
Current Limit Set (mA)
VS = 85 V, RL = 10 Ωto mid-supply
VS = 85 V, RL = 10 Ωto mid-supply
图6-37. Output Sourcing Current Error vs Current Limit Set
图6-38. Output Sinking Current Error vs Current Limit Set
97
258
Sinking
Sourcing
96.9
96.8
96.7
96.6
257
256
255
254
253
Sinking
Sourcing
96.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
ILIMIT = 250 mA
ILIMIT = 100 mA
图6-40. Short Circuit Current vs Temperature
图6-39. Short Circuit Current vs Temperature
10000
5000
3000
2000
1000
500
300
200
100
50
30
20
10
1m 10m 100m
1
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
Time (1 s/div)
图6-41. Open-Loop Output Impedance vs Frequency
图6-42. 0.1-Hz to 10-Hz Noise
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
1000
500
1000
500
300
200
300
200
100
100
50
50
30
20
30
20
10
10
5
5
3
2
3
2
1
1
100m
1
10
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
图6-43. Input Voltage Noise Spectral Density
图6-44. Input Current Noise Spectral Density
1
-40
0.1
-60
0.01
-80
0.001
0.0001
1E-5
1E-6
-100
-120
-140
-160
Gain = −1, 10-kꢁ Load
Gain = −1, 600-ꢁ Load
Gain = −1, 25-ꢁ Load
Gain = ꢀ1, 10-kꢁ Load
Gain = ꢀ1, 600-ꢁ Load
Gain = ꢀ1, 25-ꢁ Load
1m
10m
100m
1
10
Output Amplitude (VRMS
)
VOUT = 3 VRMS
VOUT = 3 VRMS
图6-46. Total Harmonic Distortion + Noise vs Amplitude
图6-45. Total Harmonic Distortion + Noise vs Frequency
1
-40
0.5
0.2
0.1
-60
0.05
0.02
0.01
-80
0.005
0.002
0.001
0.0005
-100
-120
-140
VS= 85 V, 10-kꢁ Load
VS = 85 V, 2-kꢁ Load
VS = 85 V, 100-ꢁ Load
VS = 48 V, 10-kꢁ Load
VS = 48 V, 2-kꢁ Load
VS = 48 V, 100-ꢁ Load
0.0002
0.0001
5E-5
2E-5
1E-5
10m
100m
1
10
Output Amplitude (VRMS
)
Gain = 10 V/V, VOUT = 15 VRMS
Gain = 10 V/V, VOUT = 15 VRMS
图6-48. Total Harmonic Distortion + Noise vs Amplitude
图6-47. Total Harmonic Distortion + Noise vs Frequency
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
120
VIN
VOUT
100
80
60
40
20
10M
100M
Frequency (Hz)
1G
10G
Time (200 ms/div)
图6-50. No Phase Reversal
图6-49. EMIRR vs Frequency
75
70
65
60
55
50
45
40
35
30
25
RISO = 0 ꢁ
RISO = 25 ꢁ
RISO = 50 ꢁ
20
30 40 50 70 100
200 300
500 700 1000
Capacitance (pF)
Gain = 1 V/V
Gain = 10 V/V
图6-52. Small-Signal Overshoot vs Capacitive Load
图6-51. Phase Margin vs Capacitive Load
50
45
40
35
30
25
20
15
10
5
VIN
VOUT
RISO = 0 ꢁ
RISO = 25 ꢁ
RISO = 50 ꢁ
0
20
30 40 50 70 100
200 300
500 700 1000
Time (2 µs/div)
Capacitance (pF)
10-mV step, f = 100 kHz, gain = 1 V/V
Gain = −1 V/V
图6-54. Small-Signal Step Response
图6-53. Small-Signal Overshoot vs Capacitive Load
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
VIN
VIN
VOUT
VOUT
Time (2 µs/div)
Time (200 ns/div)
10-mV step, f = 100 kHz, gain = −1 V/V
图6-55. Small-Signal Step Response
10-mV step, f = 1 MHz, gain = 1 V/V
图6-56. Small-Signal Step Response
VIN
VOUT
VIN
VOUT
Time (200 ns/div)
Time (2 µs/div)
10-V step, f = 100 kHz, gain = 1 V/V
10-mV step, f = 1 MHz, gain = −1 V/V
图6-58. Large-Signal Step Response
图6-57. Small-Signal Step Response
VIN
VOUT
VIN
VOUT
Time (2 µs/div)
Time (2 µs/div)
70-V step, f = 100 kHz, gain = 1 V/V
10-V step, f = 100 kHz, gain = −1 V/V
图6-60. Large-Signal Step Response
图6-59. Large-Signal Step Response
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
Rising
VIN
Falling
VOUT
Time (2 µs/div)
Time (1 µs/div)
70-V step, f = 100 kHz, gain = −1 V/V
12-bit settling (0.01%), 70-V step
图6-61. Large-Signal Step Response
图6-62. Settling Time
VIN
VOUT
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
Gain = −10 V/V
Gain = −10 V/V
图6-63. Positive Overload Recovery
图6-64. Negative Overload Recovery
3.5
3.4
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
3.5
3
Cooling
Heating
2.5
2
Thermal shutdown
1.5
1
0.5
0
140
145
150
155
160
165
170
175
180
8
16
24
32
40
48
56
64
72
80 85
Temperature (°C)
Supply Voltage (V)
5 typical units
图6-66. Quiescent Current Temperature Response
图6-65. Quiescent Current vs Supply Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
3.5
3
140
130
120
110
100
90
3.5
3
Output Current
Flag Voltage
2.5
2
2.5
2
1.5
1
1.5
1
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
0.5
0
80
0.5
0
70
0
1
2
3
4
5
5.5
Time (5 µs/div)
Enable/Disable Voltage (V)
ILIMIT = 100 mA
图6-68. Current Limit Response
图6-67. Quiescent Current vs Enable Voltage
60
50
40
30
20
10
0
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Enable/Disable Pin Voltage (V)
VE/D = 5 V
图6-69. Enable/Disable Pin Current vs Temperature
图6-70. Enable Pin Current vs Enable Pin Voltage
0.8
Output
Enable
0.6
0.4
0.2
0
TA = -40°C
TA = 25°C
TA = 85°C
TA = 125°C
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Overcurrent Flag Pin Volage (V)
Time (200 ꢀs/div)
Flag is asserted
图6-71. Enable Response
图6-72. Current-Limit Flag Pin vs Current-Limit Flag Pin Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩconnected to VS/2 (unless
otherwise noted)
6
5
1
0.8
0.6
0.4
0.2
0
Cooling
Heating
4
3
2
1
0
-1
140
145
150
155
160
165
170
175
180
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Overtemperature Flag Pin Voltage (V)
Temperature (°C)
E/D Com = 0 V
Flag is asserted
图6-73. Overtemperature Flag Pin Voltage vs Temperature
图6-74. Overtemperature Flag Pin Current vs Overtemperature
Flag Pin Voltage
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7 Detailed Description
7.1 Overview
The OPA593 is a precision, high-voltage (85 V), wide bandwidth (10 MHz), power operational amplifier (op amp)
with a high output current drive of ±250 mA. The device features a current limit that helps protect the system in
the event of an output short to ground. Unlike other power op amps, the current limit is specified for specific
current ranges from ±25 mA to ±250 mA. Additionally, the device has two flags that indicate an overcurrent fault
condition (beyond the configured limit) and an overtemperature fault condition (when the output stage shuts
down to protect the device from overheating). Lastly, the output can be disabled to save system power and
reduce thermal dissipation.
The unity-gain stable OPA593 has no phase inversion, a common-mode voltage range that includes the negative
rail, a wide output swing range, and high dc precision. All these features make the OPA593 an excellent choice
as an output driver for a device under test (DUT) in automated test equipment (ATE) systems, or for signal
processing in industrial systems using signals greater than 36 V.
7.2 Functional Block Diagram
V+
OPA593
Slew
Thermal
Flag
Boost
Current
Flag
Status
Control
Current
Limit
Control
−IN
E/D Com
Vbias 1
Class-AB
Biasing
OUT
Mux
Friendly
Mux
Friendly
Vbias 2
+IN
Current
Limit
Set
ILIMIT
Current
Limit
Control
Laser
Trim
Enable/
Disable
Control
E/D
V–
E/D Com
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7.3 Feature Description
7.3.1 Current Limit
The OPA593 current limit is set through the ILIMIT pin and is programmable from ±25 mA to ±250 mA, typical.
The device is specified and tested for current limits of ±25 mA, ±50 mA, ±100 mA, ±250 mA. A resistor can be
used to limit the current to a fixed value or a digital-to-analog converter (DAC) can be used to vary the current
limit during operation. 图 7-1 shows a simplified diagram of the current-limit mirror configurations, as well as
common resistor or DAC settings and the respective output current limit.
56.7 k
56.7 k
3.687 V
V–
3.687 V
V–
ILIMIT
ILIMIT
DAC
RCL
V– Supply
V– Supply
图7-1. OPA593 Internal Current Limit Configurations
The most common configuration is to set the current limit using a resistor (RCL) connected between the ILIMIT
pin and the negative supply (V–). With this configuration, 方程式 1 and 方程式 2 are used to calculate the
current limit based on the external resistor value or the resistor needed given the desired current limit value:
3.687 V × 4000
I
=
(1)
(2)
LIMIT
56.7 kΩ + R
CL
3.687 V × 4000
R
=
–56.7 kΩ
CL
I
LIMIT
An alternative to fixing the current limit to a single value using an external resistor is to use a source measure
unit (SMU) or digital-to-analog converter (DAC), which enables a variable current limit.
CAUTION
With this configuration, the output of the SMU or DAC must not exceed the ILIMIT specification in 节
6.1 to avoid reverse biasing the internal current limit circuitry and potentially damaging the device.
Use 方程式3 to set the current limit when a DAC is used (VLIMIT = DAC output voltage):
I
× 56.7 kΩ
LIMIT
V
= 3.687 V –
(3)
LIMIT
4000
Be aware that the SMU or DAC output voltage must be referenced to the negative supply of the OPA593.
Several nominal current-limit values along with the respective external resistor values and DAC output voltages
are listed in 表7-1.
表7-1. Nominal Current-Limit Values
CURRENT LIMIT, ILIMIT(mA)
DAC VOLTAGE, VLIMIT (V)(1)
RESISTOR, RCL (kΩ)
25
50
536
237
3.33
2.98
2.27
0.85
0.14
100
200
250
90.9
16.9
2.29
(1) Voltages are referenced to the negative supply, V−
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While the current limit tolerance of the OPA593 is specified for specific current limit levels, any resistor, SMU, or
DAC inaccuracies add to the listed tolerance. To achieve the desired system level accuracy, take care when
selecting these external components. 图 7-2 shows a correlation between the ideal or calculated output current
limit and the actual current limit as measured on the OPA593.
260
220
180
140
100
60
20
-20
-60
-100
-140
-180
-220
-260
0
50 100 150 200 250 300 350 400 450 500 550
Current Limit Resistor, RCL (kꢀ)
图7-2. Typical Output Current vs Current-Limit Resistor Value
7.3.2 Overcurrent Flag
The OPA593 features an overcurrent flag (Current Flag pin) that indicates a condition where the output current
exceeds the limit established by the ILIMIT pin. For example, in an output short-to-ground fault condition, the
overcurrent flag asserts, which pulls the flag pin low to E/D Com, and the output current is limited to the value set
by ILIMIT. This flag is an open-drain output compatible with standard low-voltage logic circuitry, such as a
microcontroller (MCU). Use a 5‑kΩto 10‑kΩpullup resistor to limit the input current when the flag is asserted. If
this feature is not used, leave this pin floating.
7.3.3 Overtemperature Flag
The OPA593 has internal thermal protection. When the junction temperature reaches approximately 170°C, the
op amp output stage disables and the overtemperature flag (Thermal Flag pin) is asserted, which pulls the flag
pin low to E/D Com. When the junction temperature cools to a safe operating temperature, approximately 150°C,
the output stage is enabled, and the op amp resumes normal operation. This flag is an open-drain output
compatible with standard low-voltage logic circuitry, such as an MCU. Use a 5‑kΩ to 10‑kΩ pullup resistor to
limit the input current when the flag is asserted. If this feature is not used, leave this pin floating.
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7.3.4 Output Enable and Disable
The OPA593 incorporates an enable and disable feature that uses the E/D pin to disable the output stage of the
amplifier, which reduces the power consumption of the op amp and switches the output to a high-impedance
state.
The E/D pin is referenced to the E/D Com pin. If left floating, the E/D pin is internally pulled up to enable the
device. If externally controlled, the E/D pin must be supplied with a voltage between 1.5 V and 5.5 V greater than
the E/D Com pin voltage. Even though the OPA593 output is enabled with a floating E/D pin, a moderately fast,
negative-going signal capacitively coupled to the E/D pin can overpower the internal pullup and cause device
shutdown. If the enable function is not used, a conservative and recommended approach is to connect E/D
through a 47-pF capacitor to E/D Com. 图7-3 shows different ways to connect the E/D and E/D Com pins.
DVDD
(Digital Supply)
3-V or
5-V
Logic
V+
V+
GND
47 pF
VIN+
VIN+
+
+
GND
E/D
E/D
VOUT
VOUT
E/D
OPA593
E/D
OPA593
Com
Com
VIN
VIN
–
–
GND
GND
V
V
图7-3. E/D and E/D Com Pin Connections
When the E/D pin is dropped to a voltage between 0 V and 0.5 V greater than the E/D Com pin voltage, the
output of the OPA593 is disabled. When disabled, the output of the OPA593 is set to a high-impedance state.
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7.3.5 Mux-Friendly Inputs
The OPA593 uses a unique input architecture to eliminate the need for input protection diodes but still provides
robust input protection under transient conditions. Conventional input diode protection schemes shown in 图 7-4
can be activated by fast transient step responses and can introduce signal distortion and settling time delays
because of alternate current paths, as shown in 图 7-5. For low-gain circuits, these fast-ramping input signals
forward-bias back-to-back diodes that cause an increase in input current, resulting in extended settling time.
V+
V+
VIN+
VIN+
VOUT
VOUT
OPA593
~0.7 V
85 V
VIN-
VIN-
V-
V-
OPA593 Provides Full 85-V Differential Input Range
Conventional Input Protection Limits Differential Input Range
图7-4. OPA593 Input Protection Does Not Limit Differential Input Capability
1
Ron_mux
Vn = 10 V
RFILT
10 V
Sn
D
1
2
~–9.3 V
10 V
CFILT
CS
CD
VIN–
2
Ron_mux
Sn+1
V
n+1 = –10 V RFILT
–10 V
~0.7 V
VOUT
CFILT
CS
Idiode_transient
VIN+
–10 V
Input Low-Pass Filter
Simplified Mux Model
Buffer Amplifier
图7-5. Back-to-Back Diodes Create Settling Issues
The OPA593 a true high-impedance differential input capability for high-voltage applications. This patented input
protection architecture does not introduce additional signal distortion or delayed settling time, making this device
an excellent choice for multichannel, high-switched, input applications. The OPA593 tolerates a maximum
differential swing (voltage between inverting and noninverting pins of the op amp) of up to 85 V, making this
device a great choice for use as a comparator or in applications with fast-ramping or switched input signals.
7.4 Device Functional Modes
The OPA593 has two modes of operation. The first mode is normal operation where the amplifier is enabled,
either by supplying a voltage to the enable-disable (E/D) pin that is between 2.5 V and 5 V greater than the E/D
Com pin or by leaving the E/D pin floating. The second mode of operation is a low-power, disabled state where
the E/D pin is driven between 0 V and 0.65 V greater than the E/D Com pin. In this state, the amplifier output is
disabled and enters a high-output-impedance state.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPA593 is a precision, high-voltage, high-output-current op amp. The device is capable of operating with
supplies as low as ±4 V (8 V) and as high as ±42.5 V (85 V). The current limit feature limits the output current, up
to ±250 mA, to a specified accuracy. With a small size, high operating voltage range, output current, and high dc
precision, the device is designed to operate as a high-gain stage, capable of driving heavy loads and condition
large signals. The additional features of the OPA593, including the current limit, overcurrent and
overtemperature flags, thermal protection, output disable, and mux-friendly inputs, help protect both the op amp
and the system from potential damage due to various fault conditions.
8.2 Typical Application
8.2.1 Output Driver
1.47 k
10 k
45 V
GND
–
+
Output
+
–
–5 V
Input
GND
图8-1. Output Driver Configured With a Gain of 8
8.2.1.1 Design Requirements
The OPA593 is designed for use as an output driver stage with gain and provides a wide supply voltage and high
output current with programmable current limit. Combined with the small size of the 4-mm × 4-mm WSON
package, these features make this device a great choice for high-channel density systems, such as
semiconductor test and manufacturing platforms where many channels are present. In this design example, the
OPA593 is configured for a gain of 8 V/V. A small negative supply is provided if the application requires a small
output voltage. For example, in the case of a device under test (DUT) continuity check, the amplifier is able to
provide the output without being limited by the negative rail (that is, saturating the output).
表8-1. Design Parameters
PARAMETER
Supply voltage
Input voltage
Output voltage
System gain
VALUE
+45 V, –5 V
0 V to 5 V
0 V to 40 V
8
Output current
Up to 250 mA
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8.2.1.2 Detailed Design Procedure
In this design example, the OPA593 is configured as both a gain stage and output driver. The input signal to the
amplifier is 0 V to 5 V, and the device is configured with a positive gain of 8. This configuration results in an
output voltage of 0 V to 40 V. Select supply voltages that provide adequate headroom so that the amplifier can
sink or source up to 250 mA without slamming the output into the rail. Minimize the swing from the supply to the
output to minimize the thermal dissipation of the device.
This simple design example is common in many systems that use a DAC to provide the input signal and require
a wide output signal with high output current. Such systems include test and measurement platforms and power
supplies.
图8-2 shows the input and output signal of this OPA593 circuit.
8.2.1.3 Application Curve
40
Input
Output
35
30
25
20
15
10
5
0
0
0.004
0.008
0.012
0.016
0.02
Time (s)
图8-2. OPA593 Output Driver Circuit, Input and Output Signals
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8.2.2 High Voltage 2:1 Multiplexer With Unity Gain
V+
GND
E/D Com
–
VOUT
OPA593
E/D
600
VIN_1
+
ILIMIT
10 k
V
GND
GND
DVDD
SN74LVC1G04
Select:
3-V or
5-V logic
GND
V+
VIN_2
10 k
E/D
OPA593
GND
E/D Com
+
ILIMIT
V
GND
图8-3. High Voltage 2:1 Multiplexer With Unity Gain
8.2.2.1 Design Requirements
The OPA593 operates on high-voltage supplies up to 85 V and is used to create a high voltage multiplexer
(MUX) with a gain of 1 or higher. This design example uses two OPA593 op amps and makes use of the disable
function. The high-impedance state of the output while the amplifier is disabled allows for the outputs of two
OPA593 op amps to be connected together.
8.2.2.2 Detailed Design Procedure
In this design example, two OPA593 precision op amps are configured as a unity gain buffers powered with a
±42.5-V dual supply. The input signal to either amplifier can range from –40 V to +39 V to remain in linear
operation. The output of the amplifiers are connected together and a 3-V or 5-V logic signal, serving as the
output select, is used to toggle between the enable and disable modes of operation. The logic control signal is
directly applied to one OPA593 E/D pin, and an inverter gate is used to drive the other OPA593 E/D pin. 图 8-3
shows a simplified representation of this circuit.
A clear benefit of this design is the high-voltage capability, along with the thermal protection, overcurrent
protection, and current-limit features. The mux-friendly input of the OPA593 provides a full input differential
range, avoiding the pitfalls of other amplifiers with traditional back-to-back diodes in this configuration. This
design can also be reconfigured to include signal gain, but careful selection of the input and feedback resistors is
required to minimize current leakage paths.
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8.3 Power Supply Recommendations
The OPA593 operates from power supplies up to ±42.5 V, or a total of 85 V, with excellent performance. Most
behavior remains unchanged throughout the full operating voltage range. A power-supply bypass capacitor of at
least 0.1 µF is required for proper operation. Make sure that the capacitor voltage is rated for high voltage across
the full operating temperature range. Parameters that vary significantly with operating voltage are shown in 节
6.6.
Some applications do not require an equal positive and negative output voltage swing. Power-supply voltages do
not have to be equal. The OPA593 operates with as little as 8 V between the supplies, and with up to 85 V
between the supplies.
8.4 Layout
8.4.1 Layout Guidelines
During the surface-mount solder operation (when the pins are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat is conducted away from the package into a V− plane. Always solder the thermal pad to the PCB, even with
applications that have low power dissipation. Follow these steps to attach the device to the PCB:
1. Connect the thermal pad to the most negative supply voltage on the device, V–.
2. Prepare the PCB with a top-side pattern. There must be patterning for the pins and thermal pad.
3. Thermal vias improve heat dissipation, but are not required.
4. Place recommended vias in the area of the thermal pad. Recommended thermal land size and thermal via
patterns for the SON-12 DNT package are shown in the thermal land pattern mechanical drawing appended
at the end of this document. Keep the vias small, so that solder wicking through the vias is not a problem
during reflow. Use a 0.2-mm size via with a minimum of five connected directly below the thermal pad.
5. Additional vias can be placed anywhere along the thermal plane outside of the thermal pad area. These vias
help dissipate the heat generated by the OPA593 device. These additional vias can be larger than the vias
directly under the thermal pad because the additional vias are not in the thermal pad area to be soldered;
thus, wicking is not a problem.
6. Connect all vias to the internal power plane of the correct voltage potential, V–.
7. When connecting these vias to the plane, do not use the typical web or spoke via connection methodology.
Web connections have a high thermal resistance connection that is useful for slowing the heat transfer
during soldering operations, making the soldering of vias that have plane connections easier. In this
application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
vias under the OPA593 WSON package must make the connections to the internal plane with a complete
connection around the entire circumference of the plated-through hole.
8. The top-side solder mask must leave the pins of the package and the thermal pad area exposed. The
bottom-side solder mask must cover the vias of the thermal pad area. This masking prevents solder from
being pulled away from the thermal pad area during the reflow process.
9. Apply solder paste to the exposed thermal pad area and all of the device pins.
10. With these preparatory steps in place, simply place the device in position, and run through the solder reflow
operation as with any standard surface-mount component.
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8.4.1.1 Thermal Considerations
Through normal operation, the OPA593 self-heats. Self-heating is a natural increase in the die junction
temperature that occurs in every amplifier. The maximum allowed junction temperature sets the maximum
allowed internal power dissipation (PD) as described in the following paragraph. Design efforts should be made
to prevent TJ from exceedeing the maximum temperature listed in the Absolute Maximum Ratings table.
Operating junction temperature (TJ) is determined by the ambient temperature (TA), the internal PD under the
operating conditions, and the junction-to-ambient thermal resistance (RθJA). This relationship is given by TA +
(PD × RθJA). PD is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL)
when delivering power to the load. PDQ is the specified no-load supply current times the total supply voltage
across the part. PDL depends on the required output signal and load, but for a grounded resistive load the PDL is
at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for balanced bipolar
supplies, V+ and V−). Under this condition PDL = (V+)2 / (4 × RL), where RL includes feedback network loading.
The power in the output stage and not into the load determines internal power dissipation.
As a worst-case example, compute the maximum TJ using the OPA593 in the circuit of 图 8-1 operating at a
maximum specified temperature of 125°C and driving a grounded 600-Ωload.
P
= P
+ P
DL
(4)
D
DQ
2
22.5
V
P
T
= 50 V × 4 mA +
(5)
(6)
D
4 × 600 Ω
11.47 kΩ
max = 125°C + 0.422 W × 40.8°C/W = 142.2°C
J
To enhance semiconductor long-term operating life, minimize TJ. Take proper measures to provide maximum
heat removal through both heat conduction and radiation to help keep TJ to the lowest possible level. These
proper measures include maximizing the PCB copper area to which the package thermal pad is soldered. The
copper area serves as the traditional heat sink. The top layer copper is often easiest to route and is most often
exposed to open air. PCB internal planes and the exposed bottom plane can also be used as heat sinks, but the
connections are made with vias having higher thermal resistance. The OPA593EVM uses a board design that
provides a highly effective thermal layout. The board design encompasses a large top-side copper area, and has
heat conduction paths to other planes on the board. Additionally, other higher power-dissipating components are
kept physically distant from the OPA593 to better accommodate heat removal by radiation.
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8.4.2 Layout Example
V
V+
ILIMIT
E/D
+IN
+
OUT
E/D
Com
TFlag
IFlag
RG
V
RF
图8-4. Schematic Representation
RF
E/D Com
Typically V– or GND
E/D
V–
GND
E/D Com
E/D
ILIMIT
V+
NC
RG
V+
–IN
+IN
–IN
Thermal Pad
(must connect to
V–)
OUT
OUT
+IN
Thermal
Flag
(Tflag)
Thermal
Flag
NC
Current
Flag
(Iflag)
Current
Flag
V–
V–
Thermal
Plane
GND
图8-5. OPA593 Board Layout for Noninverting Configuration
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案，可降低开发成本并缩短上市时间。
9.1.1.2 TINA-TI™ 仿真软件（免费下载）
TINA-TI™ 仿真软件是一款简单易用、功能强大且基于 SPICE 引擎的电路仿真程序。TINA-TI 仿真软件是 TINA™
软件的一款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 仿
真软件提供所有传统的SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 仿真软件提供全面的后处理能力，便于用户以多种方式获得结果，用户可从设计工具和仿真网页免费下
载。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的能力，从而构建一个动态的快速启动工具。
备注
必须安装 TINA 软件或者 TINA-TI 软件后才能使用这些文件。请从 TINA-TI™ 软件文件夹中下载免费的
TINA-TI 仿真软件。
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA593DNTR
OPA593DNTT
XOPA593DNTR
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
DNT
DNT
DNT
12
12
12
5000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
OPA593
OPA593
Samples
Samples
Samples
250
RoHS & Green
TBD
NIPDAU
Call TI
5000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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5-Jan-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA593DNTR
OPA593DNTT
WSON
WSON
DNT
DNT
12
12
5000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA593DNTR
OPA593DNTT
WSON
WSON
DNT
DNT
12
12
5000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DNT0012B
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.1) TYP
2.6 0.1
6
7
2X
2.5
3
0.1
10X 0.5
12
1
0.3
0.2
12X
0.1
C A B
C
0.5
0.3
PIN 1 ID
(45 X 0.25)
12X
0.05
4214928/C 10/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DNT0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
SYMM
12X (0.6)
1
12
12X (0.25)
(1.25)
SYMM
(3)
10X (0.5)
7
6
(R0.05) TYP
(
0.2) VIA
TYP
(1.05)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214928/C 10/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DNT0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
(0.68)
12X (0.6)
1
12
12X (0.25)
(0.76)
SYMM
10X (0.5)
4X
(1.31)
(R0.05) TYP
6
7
4X (1.15)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4214928/C 10/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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