OPA607IDBVR [TI]
适用于成本敏感型系统的低功耗、精密、50MHz 解补偿 CMOS 运算放大器 | DBV | 5 | -40 to 125;
| 型号： | OPA607IDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于成本敏感型系统的低功耗、精密、50MHz 解补偿 CMOS 运算放大器 | DBV | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总49页 (文件大小：2899K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA607, OPA2607
ZHCSKG0J –OCTOBER 2019 –REVISED APRIL 2021
适用于成本敏感型系统的OPAx607 50MHz、低功耗、轨至轨输出CMOS 运算
放大器
1 特性
3 说明
• 增益带宽积(GBW)：50MHz
• 静态电流：900µA（典型值）
• 宽带噪声：3.8nV/√Hz
• 输入温漂：1.5μV/°C（最大值）
• 失调电压：120µV（典型值）
• 输入偏置电流：10pA（最大值）
• 轨至轨输出(RRO)
OPA607 和 OPA2607 器件是一款解补偿通用 CMOS
运算放大器，最小稳定增益为 6V/V，具有 3.8nV/√Hz
的低噪声和 50MHz 的GBW。OPAx607 器件具有低噪
声和高带宽特性，因此非常适合要求在成本和性能之间
达到良好平衡的通用应用。高阻抗 CMOS 输入使得
OPAx607 放大器适合连接具有高输出阻抗的传感器
（例如，压电式传感器）。
• 解补偿增益≥6V/V（稳定）
• 关断电流：1µA（最大值）
• 电源电压范围：2.2V 至5.5V
OPAx607 器件具有断电模式，最大静态电流小于
1µA，因此，该器件适用于便携式电池供电型应用。
OPAx607 器件的轨至轨输出 (RRO) 相对于电源轨具有
高达8mV 的摆幅，从而更大限度提高动态范围。
2 应用
OPAx607 经过优化，适合在低至 2.2V (±1.1V) 和高达
5.5V (±2.75V) 的低电源电压下工作，且额定工作温度
范围为–40°C 至+125°C。
• 电流感应
• 探鱼器和声纳
• 超声波流量计
• 园艺和电动工具
• 打印机
器件信息(1)
封装尺寸（标称值）
器件型号
OPA607
封装
SC70 (6)
• 光幕和安全防护装置
• 光学模块
• 手持测试设备
• PM2.5 和PM10 颗粒传感器
2.00mm × 1.25mm
2.90mm × 1.60mm
4.90mm × 3.91mm
3.00mm × 3.00mm
1.50mm x 2.00mm
SOT23 (5)
SOIC (8)
OPA2607
VSSOP (8)
X2QFN (10)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Short Circuit
Detection
Transimpedance
stage
VTH
œ
LOAD
+
VREF
RF
TLV3201
OPA607
ADS7042
LED driver
+
Þ
VS+
VS+
RG
RF
ISH
œ
REXT
ADS7042
OPA607
RG
CEXT
+
Photodiode
CF
VREF
适用于跨阻应用的OPAx607
适用于电流感应应用的OPAx607
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS981
OPA607, OPA2607
ZHCSKG0J –OCTOBER 2019 –REVISED APRIL 2021
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Table of Contents
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Applications.................................................. 22
10 Power Supply Recommendations..............................29
11 Layout...........................................................................30
11.1 Layout Guidelines................................................... 30
11.2 Layout Examples.....................................................30
12 Device and Documentation Support..........................31
12.1 Device Support....................................................... 31
12.2 Documentation Support.......................................... 31
12.3 Related Links.......................................................... 31
12.4 Receiving Notification of Documentation Updates..31
12.5 支持资源..................................................................31
12.6 Trademarks.............................................................31
12.7 Electrostatic Discharge Caution..............................31
12.8 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings ....................................... 7
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions ........................7
7.4 Thermal Information ...................................................8
7.5 Electrical Characteristics ............................................9
7.6 Typical Characteristics.............................................. 11
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................21
Information.................................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision I (February 2021) to Revision J (April 2021)
Page
• 删除了器件信息表中VSSOP (8) 和X2QFN (10) 封装的预发布声明.................................................................1
• Removed the preview statement from the OPA2607 X2QFN (RUG) package and VSSOP (DGK) in the
Device Comparison section................................................................................................................................4
• Removed the preview statement from the OPA2607 D, DGK and OPA2607 RUG package in the Pin
Configuration and Functions section.................................................................................................................. 5
Changes from Revision H (December 2020) to Revision I (February 2021)
Page
• 更新了数据表标题。........................................................................................................................................... 1
Changes from Revision G (October 2020) to Revision H (December 2020)
Page
• Updated the I/O and Descriptions in the Pin Functions—Single Channel table................................................. 5
Changes from Revision F (September 2020) to Revision G (October 2020)
Page
• Removed the RUG Package 8-Pin X2QFN pinout to the Pin Configuration and Functions section...................5
• Removed the N/C pin decription from the Pin Functions –Single Channel table.............................................5
• Changed Overdrive Recovery Time from 0.25µs to 0.3µs ...............................................................................9
• Updated the Turn-On and Turn-Off Time figure in the Typical Characteristics section.....................................11
• Updated the Power Down Pin Bias Current vs Power Down Pin Voltage figure in the Typical Characteristics
section...............................................................................................................................................................11
• Updated the Input Offset Voltage vs Temperature figure in the Typical Characteristics section.......................11
• Updated the Common Mode Rejection Ratio vs Temperature figure in the Typical Characteristics section.....11
• Updated the Short-Circuit Current vs Temperature figure in the Typical Characteristics section......................11
• Updated the Input Bias and Offset Current vs Temperature figure in the Typical Characteristics section........11
• Updated the Output Voltage vs Output Current Sourcing and Sinking figure in the Typical Characteristics
section...............................................................................................................................................................11
• Added the Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs
Frequency figure to the Typical Characteristics section....................................................................................11
• Added the Crosstalk vs Frequency figure to the Typical Characteristics section..............................................11
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• Added the Quiescent Current vs Temperature figure to the Typical Characteristics section............................ 11
• Updated the Simulated Closed-Loop Bandwidth of TIA figure in the Application Curves section.................... 23
• Updated the Simulated Time Domain Response figures in the Application Curves section.............................23
• Updated the Small-Signal Frequency Response in Gains of 3V/V (a) and 6V/V (b) figure in the Noninverting
Gain of 3 V/V section........................................................................................................................................24
• Updated the Small-Signal Frequency Response of Difference Amplifier (c) With and Without Noise Gain
Shaping figures in the Noninverting Gain of 3 V/V section...............................................................................24
Changes from Revision E (August 2020) to Revision F (September 2020)
Page
• Deleted blank CMRR specifications from Electrical Characteristics table..........................................................9
Changes from Revision D (May 2020) to Revision E (August 2020)
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• 将OPA2607 SOIC (8) 封装的状态从预发布更改为正在供货............................................................................ 1
Changes from Revision C (April 2020) to Revision D (May 2020)
Page
• 将状态从预告信息更改为量产数据....................................................................................................................1
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SOT-23 (DBV)
5 Device Comparison
PACKAGE LEADS
VSSOP (DGK)
NO. OF
CHANNELS
DEVICE
SOIC
(D)
X2QFN
SC-70
(RUG)(1)
(DCK)(1)
OPA607
1
2
6(1)
5
—
—
—
OPA2607
8
10(1)
8
—
—
(1) Package with Power Down mode.
VOLTAGE
NOISE
(nV/√Hz)
OFFSET
DRIFT
(µV/°C, TYP)
MINIMUM
STABLE GAIN
(V/V)
IQ / CHANNEL
(mA, TYP)
GBW
(MHz)
SLEW RATE
(V/µs)
DEVICE
INPUT
OPAx365
OPAx607
OPAx837
CMOS
CMOS
Bipolar
1
1
6
1
4.6
0.9
0.6
50
50
50
25
24
4.5
3.8
4.7
0.3
0.4
105
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6 Pin Configuration and Functions
VS+
IN-
VS+
6
OUT
VSœ
5
VSœ
5
PD
IN+
OUT
图6-1. DBV Package
图6-2. DCK Package
6-Pin SC70
5-Pin SOT-23
Top View
Top View
Pin Functions –Single Channel
PIN
I/O
DESCRIPTION
NAME
DBV
DCK
4
3
1
3
1
4
5
2
6
I
I
Inverting input
IN–
IN+
Non inverting input
Output
OUT
PD
O
I
Power down (can be left floating)
—
2
VS–
VS+
Negative supply or ground (for single-supply operation)
Positive supply
—
—
5
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VS+
10
1
8
7
OUT1
IN1-
VS+
OUT1
IN1-
1
2
3
4
OUT2
IN2-
9
8
2
3
OUT2
œ
A
6
5
IN1+
+
œ
IN2-
B
B
A
IN1+
VS-
IN2+
4
+
IN2+
PD2
7
6
PD1
图6-3. OPA2607 D, DGK Package
8-Pin SOIC, VSSOP
Top View
5
VS-
图6-4. OPA2607 RUG Package
10-Pin X2QFN
Top View
Pin Functions –Dual Channel
PIN
I/O
DESCRIPTION
NAME
IN1–
D, DGK
RUG
2
3
6
5
1
7
4
8
2
3
I
I
Inverting input, channel 1
IN1+
IN2–
IN2+
OUT1
OUT2
VS–
Noninverting input, channel 1
Inverting input, channel 2
8
I
7
I
Noninverting input, channel 2
Output, channel 1
1
O
O
—
—
9
Output, channel 2
5
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
VS+
10
Low = amplifier 1 disabled, high = amplifier 1 enabled; see the Power Down
Mode section for more information.
PD1
PD2
4
6
I
I
—
—
Low = amplifier 2 disabled, high = amplifier 2 enabled; see the Power Down
Mode section for more information.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage, Vs
6
(VS+) –(VS–
)
VIN+, VIN–
Input voltage
(VS+) + 0.5
V
(VS–) –0.5
(VS–) –0.5
VPD
VID
II
PD voltage
6
±5
V
Differential input voltage(4)
Continuous input current(2)
Continuous output current(3)
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature
Storage temperature
V
±10
±20
mA
mA
IO
See Thermal Information
TJ
150
125
150
°C
°C
°C
TA
–40
–65
Tstg
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails
should be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
(4) Long term drift of offset voltage (> 1mV) if a differential input in excess of ≈2V is applied continuously between the IN+ and IN- pins at
elevated temperatures.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
V
D Package , Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2
NOM
MAX
5.5
UNIT
V
VS
TA
Supply voltage (VS+) –(VS–
)
±1.1
–40
±2.75
125
Ambient operating temperature
25
°C
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7.4 Thermal Information
OPAx607
DGK
(VSSOP)
DBV
(SOT23)
RUG
THERMAL METRIC(1)
D (SOIC)
DCK (SC70)
UNIT
(X2QFN)
10 PINS
152
8 PINS
131.1
73.2
8 PINS
179
71
5 PINS
196.5
118.7
64.5
6 PINS
219.7
182.6
105.7
87
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
58
RθJB
ψJT
Junction-to-board thermal resistance
74.5
101
13
77
Junction-to-top characterization parameter
Junction-to-board characterization parameter
24.5
41.1
1.2
73.3
100
64.2
105.4
77
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At TA = 25°C, VS = 2.2 V to 5.5 V, G = 6 V/V(5), RF = 5 kΩ, CF = 2.5 pF, VCM = (VS / 2) –0.5 V, CL = 10 pF,
kΩ connected to (VS / 2) –0.5 V, and, PD connected to (VS+) (unless otherwise noted)(1)
RL = 10
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Input offset voltage
Input offset voltage
0.12
0.12
±0.3
120
0.6
0.7
–0.6
–0.7
VOS
mV
TA = –40°C to +125°C
dVOS/dT
PSRR
Input offset voltage drift
±1.5 µV/°C
dB
TA = –40°C to +125°C
Power-supply rejection ratio
VS = 2.2 V to 5.5 V
95
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio(3)
(VS–
)
V
(VS+)–1.1
CMRR
90
100
dB
(VS–) < VCM < (VS+) –1.1 V
INPUT BIAS CURRENT
±3
See Fig. 29
±3
±10
±10
IB
Input bias current(2)
pA
TA = –40℃to 125℃
IOS
Input offset current(2)
NOISE
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
f = 0.1 Hz to 10 Hz
f = 10 kHz, 1/f corner at 1 kHz
f = 1 kHz
1.6
3.8
46
µVPP
eN
iN
nV/√Hz
fA/√Hz
INPUT IMPEDANCE
Differential
Common-mode
OPEN-LOOP GAIN
AOL
Open-loop voltage gain(3)
Phase margin
AC Characteristics (VS = 5 V)
11.5
5.5
CIN
pF
110
130
65
dB
°
(VS–) + 400 mV < VOUT < (VS+) –400 mV
SSBW
GBW
SR
Small-signal bandwidth
VOUT = 20 mVpp
9
50
MHz
V/µs
µs
Gain-bandwidth product
Slew rate
G = 20 V/V
3-V output step (10-90%), VOCM = mid-supply
To 0.1%, 3-V step, G = 40, VOCM = mid-supply
To 0.01%, 3-V step, G = 40, VOCM = mid-supply
VIN+ × Gain > VS
24
1
tS
Settling time
1.8
Overdrive recovery time
0.3
µs
-103
-91.5
-96
VOUT = 2 VPP, f = 1 kHz , RL = 10 kΩ
VOUT = 2 VPP, f = 20 kHz , RL = 10 kΩ
VOUT = 2 VPP, f = 1 kHz , RL = 1 kΩ
VOUT = 2 VPP, f = 20 kHz , RL = 1 kΩ
VOUT = 2 VPP f = 20 kHz
THD + N
Total Harmonic Distortion + Noise(6)
dB
-72.8
-105
-95
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
Channel-to-channel crosstalk
dBc
dBc
VOUT = 2 VPP f = 20 kHz
VOUT = 2 VPP, f = 100 kHz
-114
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7.5 Electrical Characteristics (continued)
At TA = 25°C, VS = 2.2 V to 5.5 V, G = 6 V/V(5), RF = 5 kΩ, CF = 2.5 pF, VCM = (VS / 2) –0.5 V, CL = 10 pF,
kΩ connected to (VS / 2) –0.5 V, and, PD connected to (VS+) (unless otherwise noted)(1)
RL = 10
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
8
12
12
Output voltage swing from supply rails
mV
TA = –40℃to +125℃
ISC
ZO
Output Short-circuit current
Open-loop output impedance
60
mA
f = 1 MHz
500
Ω
POWER SUPPLY
IO = 0 mA
900
1100
1200
IQ
Quiescent current per amplifier
µA
IO = 0 mA, TA = –40°C to +125°C
POWER DOWN (Device Enabled When Floating)
Power Down quiescent current per amplifier(4) PD = VS–
750
1000
–1000
0.7 x VS
nA
V
Power Down pin bias current per amplifier(7)
Enable voltage threshold
PD = VS–
–750
Logic-High threshold
Logic-Low threshold
Disable voltage threshold
0.2 x VS
tON
Turn-on time delay(2)
Turn-off time delay
10
15
µs
tOFF
0.5
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over
temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization or both ; not production tested.
(3) Production Tested at VS = 5.5V
(4) In Power Down mode current drawn by the opamp is equal to the bias current sourced on the PD pin
(5) All Gains (G) mentioned are in V/V unless otherwise noted.
(6) Lowpass-filter bandwidth is 92kHz for f = 20 kHz and 20 kHz for f = 1 kHz.
(7) Negative value of the Power Down bias current indicates current being sourced from the opamp's PD pin towards external circuit.
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7.6 Typical Characteristics
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply –0.5 V, G = 6 V/V (unless otherwise
noted).
140
120
100
80
180
150
120
90
100
10
1
60
60
40
30
20
0
0
-30
-60
Magnitude (dB)
Phase (è)
-20
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
10
100
1k
Frequency (Hz)
10k
100k
D002
D010
.
.
.
.
.
.
图7-1. Open Loop Gain and Phase vs Frequency
图7-2. Input Voltage Noise Density vs Frequency
100
3
0
-3
-6
10
1
-9
0.1
0.01
Gain = 6 V/V
Gain = -5 V/V
Gain = 10 V/V
Gain = 20 V/V
-12
-15
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
100k
1M
10M
100M
Frequency (Hz)
D003
D101
.
.
.
.
VOUT = 20 mVPP
.
图7-3. Input Current Noise Density vs Frequency
图7-4. Small-Signal Frequency Response vs Gain
3
3
0
-3
-6
0
-3
-6
-9
-9
CL = 10 pF
CL = 5 pF
CL = 22 pF
-12
RL = 10 kW
RL = 2 kW
-12
100k
1M
10M
100M
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D005
D004
.
VOUT = 20 mVPP
.
.
VOUT = 20 mVPP
.
图7-5. Small-Signal Frequency Response vs Capacitive Load
图7-6. Small-Signal Frequency Response vs Output Load
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7.6 Typical Characteristics (continued)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply –0.5 V, G = 6 V/V (unless otherwise
noted).
3
0
1
0.8
0.6
0.4
0.2
0
-3
-6
-0.2
-0.4
-0.6
-0.8
-1
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
-9
-12
100k
1M
10M
100M
100k
1M
Frequency (Hz)
10M
Frequency (Hz)
D006
D007
.
.
.
.
.
.
.
.
图7-7. Large-Signal Frequency Response vs Output Voltage
图7-8. Large-Signal Response Flatness vs Frequency
-40
-40
HD2, RL = 10kW
HD2
HD3
-50
HD3, RL = 10kW
-50
-60
HD2, RL = 2kW
-60
HD3, RL = 2kW
-70
-70
-80
-90
-80
-100
-110
-120
-130
-140
-90
-100
-110
-120
10
100
1k 10k
Freuency (Hz)
100k
1M
1
1.5
2
2.5
3
Output Voltage (VPP
3.5
4
4.5
5
)
D008
DPLO
.
VOUT = 2 VPP
.
.
Frequency = 20 kHz
图7-9. Harmonic Distortion vs Frequency
图7-10. Harmonic Distortion vs Output Voltage
140
120
100
80
1000
CMRR
PSRR -
PSRR +
900
800
700
600
500
400
300
200
100
0
60
40
20
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D019
D011
.
.
.
.
.
图7-11. Rejection Ratio vs frequency
图7-12. Open Loop Output Impedance vs Frequency
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7.6 Typical Characteristics (continued)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply –0.5 V, G = 6 V/V (unless otherwise
noted).
4
3
2
1.5
1
VOUT
VIN ì 6
2
1
0.5
0
0
-1
-2
-3
-4
-0.5
-1
-1.5
-2
VOUT
VIN x 6 V/V
0
500
1000
1500
Time (nsec)
2000
2500
3000
0
500
1000
Time (nsec)
1500
2000
D012
D013
.
.
.
.
.
.
TRISE = 1 µsec , TFALL = 0.7 µsec
图7-14. Large-Signal Transient Response
.
.
.
图7-13. Output Overdrive Recovery
0.15
0.1
80
70
60
50
40
30
20
10
0
VIN ì 6
VOUT
VS = 2.2V
VS = 5.5V
0.05
0
-0.05
-0.1
-0.15
0
500
1000
Time (nsec)
1500
2000
10p
100p
Capacitive Load (F)
D014
D020
.
TRISE = TFALL = 40 nsec
.
.
图7-15. Small-Signal Transient Response
图7-16. Phase Margin vs Capacitive Load
3.3
3
100
90
80
70
60
50
40
30
20
10
0
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 40 V/V
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
VIN
VOUT Gain = 6 V/V
VOUT Gain = 10 V/V
VOUT Gain = 20 V/V
VOUT Gain = 40 V/V
10p
100p
1n
10n
Time (100 nsec/div)
CLOAD (F)
D026
D025
.
Simulated
.
.
图7-17. Step Settling Time
图7-18. Recommended Isolation Resistor vs Capacitive Load
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7.6 Typical Characteristics (continued)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply –0.5 V, G = 6 V/V (unless otherwise
noted).
27
24
21
18
15
12
9
6
5
VS = 5 V, Overshoot
VS = 5 V, Undershoot
VS = 2.2 V, Overshoot
VS = 2.2 V, Undershoot
4
3
2
1
6
0
VOUT
PD
3
0
-1
10
20
30
40
50
60
Capacitive Load (pF)
70
80
90
100
0
5
10
Time (msec)
15
20
D015
D016
.
VOUT = 200 mVPP
.
.
.
.
图7-19. Overshoot vs Capacitive Load
图7-20. Turn-On and Turn-Off Time
0
-0.5
-1
4000
3500
3000
2500
2000
1500
1000
500
VS = 5.5V
VS = 2.2V
-1.5
-2
-2.5
-3
PD Sweep from VS- to VS+
PD Sweep from VS+ to VS-
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
D033
D022
PD Pin Voltage (V)
Input Offset Voltage (mV)
.
.
.
.
9000 units
.
图7-21. Power Down Pin Bias Current vs Power Down Pin
图7-22. Input Offset Voltage Distribution
Voltage
100
80
12
11
10
9
60
40
8
20
7
6
0
5
-20
-40
-60
-80
-100
4
3
2
1
0
-50
-25
0
25
50
75
100
125
Ambient Temperature (èC)
D024
D023
Offset Voltage Drift (mV/èC)
.
32 Units, Normalized to
VOS = 0V at 25°C
.
.
.
32 Units, –40°C to
+125°C
图7-23. Input Offset Voltage vs Temperature
图7-24. Input Offset Drift Distribution
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7.6 Typical Characteristics (continued)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply –0.5 V, G = 6 V/V (unless otherwise
noted).
8
6
4
2
350
300
250
200
150
100
50
0
-2
-4
-6
-8
-50
-100
-150
-200
-250
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
Input Common Mode Voltage (V)
1
1.5
2
2.5
3
2
2.5
3
3.5
4
VS (V)
4.5
5
5.5
6
D028
D029
.
VS = ±2.75 V
.
.
.
.
32 Units
.
.
.
图7-25. Input Offset vs Common Mode Voltage
图7-26. Input Offset vs Supply
120
100
90
80
70
60
50
40
117
114
111
108
105
102
99
96
VCM = (VS-) to (VS+ - 1.1)
VCM = (VS- + 0.25) to (VS+ - 1.1)
VCM = (VS- - 0.1) to (VS+ - 1.1)
93
90
-50
-25
0
25
50
75
100
125
-75
-50
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (èC)
D100
D021
.
.
.
.
图7-27. Common Mode Rejection Ratio vs Temperature
图7-28. Short-Circuit Current vs Temperature
400
1000
IB+
IB-
IOS
VS = 2.2 V
VS = 5.5 V
950
900
850
800
750
700
650
600
550
500
350
300
250
200
150
100
50
0
-50
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D030
D031
.
.
.
.
图7-29. Input Bias and Offset Current vs Temperature
图7-30. Quiescent Current vs Temperature
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7.6 Typical Characteristics (continued)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply –0.5 V, G = 6 V/V (unless otherwise
noted).
2.75
2.25
1.75
1.25
0.75
0.25
-0.25
-0.75
-1.25
-1.75
-2.25
-2.75
120
110
100
90
80
-40èC
+25èC
+125èC
70
60
50
40
30
20
0
10
20
30
Output Current (mA)
40
50
60
1M
10M
100M
Frequency (Hz)
1G
10G
D032
D001
.
.
.
.
.
.
图7-31. Output Voltage vs Output Current Sourcing and Sinking 图7-32. Electromagnetic Interference Rejection Ratio Referred
to Noninverting Input (EMIRR+) vs Frequency
-70
-75
-80
-85
-90
-95
-100
-105
-110
Ch B to Ch A
Ch A to Ch B
-115
-120
100k
1M
10M
Frequency (MHz)
100M
D001
.
.
.
图7-33. Crosstalk vs Frequency
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8 Detailed Description
8.1 Overview
The OPAx607 devices are low-noise, rail-to-rail output (RRO) operational amplifiers (op amp). The devices
operate from a supply voltage of 2.2 V to 5.5 V. The input common-mode voltage range also extends down to
the negative rail allowing the OPAx607 to be used in most single-supply applications. Rail-to-rail output swing
significantly increases dynamic range, especially in low-supply, voltage-range applications, which results in
complete usage of the full-scale range of the consecutive analog-to-digital converters (ADCs). The
decompensated architecture allows for a favorable tradeoff of low-quiescent current for a very-high gain-
bandwidth product (GBW) and low-distortion performance in high-gain applications.
8.2 Functional Block Diagram
V+
7.5M ꢀ
Reference
PD block
PD
Current
VIN+
VINÛ
NMOS input pair
for phase reversal
protection only
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
VÛ
(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The OPAx607 operational amplifiers are fully specified and assured for operation from 2.2 V to 5.5 V, applicable
from –40°C to +125°C. The OPAx607 devices are completely operational with asymmetric, symmetric and
single supply voltages applied across the supply pins. The total voltage (that is, (VS+) – (VS–)) must be less
than the supply voltage mentioned in 节7.1.
8.3.2 Rail-to-Rail Output and Driving Capacitive Loads
Designed as a low-power, low-voltage operational amplifier, the OPAx607 devices are capable of delivering a
robust output drive. For resistive loads of 10 kΩ, the output swings to within a few millivolts of either supply rail,
regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to
swing close to the rails. The OPAx607 devices drive up to a nominal capacitive load of 47 pF on the output with
no special consideration and without the need of a series isolation resistor RISO while still being able to achieve
45° of phase margin. When driving capacitive loads greater than 47 pF, TI recommends using RISO as shown in
图8-1 in series with the output as close to the device as possible. Refer to 图7-18 for looking up different values
of RISO required for CL to achieve 45° phase margin. Without RISO, the external capacitance (CL) interacts with
the output impedance (ZO) of the amplifier, resulting in stability issues. Inserting RISO isolates CL from ZO and
restores the phase margin. 图8-1 shows the test circuit.
IOVERLOAD
10mA max
RISO
OPAx607
Rf
+
VIN
VOUT
10 kꢀ
œ
Rg
CL
Cf
图8-1. Input Current Protection and Driving Capacitive Loads
图8-2 and 图8-3 show the phase margin achieved with varying RISO with different values of CL.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
10pF
22pF
47pF
0.1nF
1nF
10pF
22pF
47pF
0.1nF
1nF
10nF
10nF
0
50 100 150 200 250 300 350 400 450 500
RISO (W)
0
50 100 150 200 250 300 350 400 450 500
RISO (W)
D018
D017
Gain = 10 V/V,
Cf = 2.5 pF,
Gain = 20 V/V,
Cf = 2.5 pF,
RL = 10 kΩ
RL = 10 kΩ
图8-2. Phase Margin vs. Series Isolation Resistor 图8-3. Phase Margin vs. Series Isolation Resistor
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8.3.3 Input and ESD Protection
When the primary design goal is a linear amplifier with high CMRR, do not exceed the op amp input common-
mode voltage range (VCM). This CMRR is used to set the common-mode input range specifications in 节 7.5.
The typical VCM specifications for the OPAx607 devices are from the negative rail to 1.1 V below the positive rail.
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally 0 V)
and the input common-mode voltage can be analyzed at either input pin; the other input pin is assumed to be at
the same potential. The voltage at VIN+ is easy to evaluate. In a noninverting configuration (图 8-1) the input
signal, VIN+, must not exceed the VCM rating. However, in an inverting amplifier configuration, VIN+ must be
connected to the voltage within VCM. The input signal applied at VIN- can be any voltage, such that the output
voltage swings with a headroom of 10 mV from either of the supply rails.
The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For single
5-V supply, the linear input voltage range is 0 V to 3.9 V and with a 2.2-V supply this range is 0 V to 1.1 V. The
headroom to each power-supply rail is the same in either case: 0 V and 1.1 V. A weak NMOS input pair from
VIN+ to VIN+ –1.1 V ensures that an output phase reversal issue does not occur when the VCM is violated.
VS+
TVS
VDD
OPAx607
PD
IN+
œ
OUT
IN-
+
Power-Supply
ESD Cell
VSS
VS¤
图8-4. Internal ESD Structure
The OPAx607 devices also incorporate internal electrostatic discharge (ESD) protection circuits on all pins. For
the input and output pins, this protection primarily consists of current-steering diodes connected between the
input and power-supply pins. These ESD protection diodes provides input overdrive protection, as long as the
current is limited with a series resistor to 10 mA, as stated in 节 7.1. 图 8-1 shows a series input resistor can be
added to the driven input to limit the input current.
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8.3.4 Decompensated Architecture with Wide Gain-Bandwidth Product
Amplifiers such as the OPAx607 devices are not unity-gain stable are referred to as decompensated amplifiers.
The decompensated architecture typically allows for higher GBW, higher slew rate, and lower noise compared to
a unity-gain stable amplifier with similar quiescent currents. The increased available bandwidth reduces the rise
time and the settling time of the op amp, allowing for sampling at faster rates in an ADC-based signal chain.
As shown in 图 8-5, the dominant pole fd is moved to the frequency f1 in the case of a decompensated op amp.
The solid AOL plot is the open-loop gain plot of a traditional unity-gain stable op amp. The change in internal
compensation in a decompensated amp such as the OPAx607, increase the bandwidth for the same amount of
power. That is, the decompensated op amp has an increased bandwidth to power ratio when compared to a
unity-gain stable op amp of equivalent architecture. Besides the advantages in the above mentioned
parameters, an increased slew rate and a better distortion (HD2 and HD3) value is achieved because of the
higher available loop-gain, compared to its unity-gain counterpart. The most important factor to consider is
ensuring that the op amp is in a noise gain (NG) greater than Gmin. A value of NG lower than Gmin results in
instability, as shown in 图 8-5, because the 1/ß curve intersects the AOL curve at 40 dB/decade. This method of
analyzing stability is called the rate of closure method. See the precision lab training videos from TI for a better
understanding on device stability and for different techniques of ensuring stability.
Unity Gain Stable Op Amp
Decompensated Op Amp
A
OL
G
min
“
‘
GBP
“
“
“
“
‘d
‘1
‘u
‘2
“
Å
‘u
图8-5. Gain vs Frequency Characteristics for a Unity-Gain Stable Op Amp and a Decompensated Op
Amp
The OPAx607 devices are stable in a noise gain of 6 V/V (15.56 dB) or higher in conventional gain circuits; see
图 8-6. The device has 9 MHz of small-signal bandwidth (SSBW) in this gain configuration with approximately
65° of phase margin. The high GBW and low voltage noise of the OPAx607 devices make them suitable for
general-purpose, high-gain applications.
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8.4 Device Functional Modes
The OPAx607 devices have two functional modes: normal operating mode and Power Down ( PD) mode.
8.4.1 Normal Operating Mode
The OPAx607 devices are operational when the power-supply voltage is between 2.2 V (±1.1 V) and 5.5 V
(±2.75 V). Most newer systems use a single power supply to improve efficiency and simplify the power tree
design. The OPAx607 devices can be used with a single-supply power (VS– connected to GND) with no change
in performance from split supply, as long as the input and output pins are biased within the linear operating
region of the device. The valid input and output voltage ranges are given in 节 7.5. The outputs nominally swing
rail-to-rail with approximately 10-mV headroom required for linear operation. The inputs can typically swing up to
the negative rail (typically ground) and to within 1.1 V from the positive supply. 图 8-6 shows changing from a
±2.5-V split supply to a 5-V single-supply.
VSIG
VSIG
Bias
Bias
5 V
2.5 V
Signal and bias from
previous stage
Signal and bias from
previous stage
OPA607
OPA607
+
+
VOUT
Gain × VSIG
Gain × Bias
VOUT
œ
œ
Gain × VSIG
-2.5 V
Gain × Bias
Signal and bias to
next stage
Signal and bias to
next stage
RG
RF
RG
RF
图8-6. Single-Supply and Dual-Supply Operation
8.4.2 Power Down Mode
The OPAx607 devices feature a Power Down mode for power critical applications. Under logic control, the
amplifier can be switched from normal operation (consuming ≤ 1 mA) to a Power Down current of less than 1
µA. When the PD pin is connected high, the amplifier is active. Connecting the PD pin to logic low disables the
amplifier and places the output in a high-impedance state. The output of an op amp is high impedance similar to
a tri-state high-impedance gate under a Power Down condition; however, the feedback network behaves as a
parallel load.
If the Power Down mode is not used, connect PD to the positive supply pin or leave floating. See the Power
Down (Device Enabled When Floating) section in 节7.5 table for the enable and disable threshold voltages. The
PD pin can be left floating to keep the op amp always enabled, which is primarily possible because of the
presence of an internal pullup resistor within the op amp that, by default, always keeps the PD pin weakly tied to
VS+. However it is also acceptable to strengthen the pull up from the PD pin by connecting a low value
resistance from the PD pin to VS+. This helps make the part less susceptible to noise and transient pick up on
the PD pin. Looking at the PD pin bias current in 图 7-21 can help us get an accurate understanding of the
voltage required to be applied on the PD pin for enabling and powering down. Note: the hysteresis present in 图
7-21 help with single shot power up and power down of OPAx607 devices.
The PD pin exhibits a special type of ESD protection which allows users to apply any voltage between VS– to 6
V irrespective of the voltage at the VS+. Special ESD structure at the PD pin helps in relaxing the requirements
on power sequencing during power up and power down condition. Refer to 图 8-4 for details of the internal ESD
structure. The absolute voltage limits applicable on PD pin can be found in 节 7.1 table. Another key care about
in PD condition is to ensure the IN+ and IN– are not exposed to a high differential voltage continuously. In a
power up condition the op-amp's loop gain ensure the IN+ pin and the IN– track each other closely. However in
PD condition the op-amp is inactive and IN– will be usually weakly tied to GND through the RG resistor.
Exposing the IN+ pin continuously to a high voltage in such a condition will result in irreversible offset voltage
(VOS) shift.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPAx607 devices feature a 50-MHz GBW with 900 µA of supply current, providing good AC performance at
low-power consumption. The low input noise voltage of 3.8 nV/√ Hz, the approximate pA of bias current, and a
typical input offset voltage of 0.1 mV make the device very suitable for both AC and DC applications.
9.2 Typical Applications
9.2.1 100-kΩGain Transimpedance Design
The high GBW and low input voltage and current noise for the OPAx607 devices make it an excellent wideband
transimpedance amplifier for moderate to high transimpedance gains.
Supply decoupling
not shown
+5 V
OPAx607
+0.5 V
+
VOUT
œ
GND
RF
100 kꢀ
CD
3 pF
IPD
CCM
5.5 pF
CDIFF
11.5 pF
CF
1.1 pF
VOUT = IPD X RF
OPA607's input differential and
common-mode capacitance
图9-1. Wideband, High-Sensitivity, Transimpedance Amplifier
9.2.1.1 Design Requirements
Design a high-bandwidth, high-transimpedance-gain amplifier with the design requirements shown in 表9-1.
表9-1. Design Requirements
PHOTODIODE CAPACITANCE
TARGET BANDWIDTH (MHz)
TRANSIMPEDANCE-GAIN (kΩ)
(pF)
2
100
3
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9.2.1.2 Detailed Design Procedure
Designs that require high bandwidth from a large area detector with relatively high transimpedance-gain benefit
from the low input voltage noise of the OPAx607 devices. Use the Excel™ calculator available at What You Need
To Know About Transimpedance Amplifiers – Part 1 to help with the component selection based on total input
capacitance and CTOT. CTOT is referred as CIN in the calculator. CTOT is the sum of CD, CDIFF, and CCM which is
20 pF. Using this value of CTOT, and the targeted closed-loop bandwidth (f–3dB) of 2 MHz and transimpedance
gain of 100 kΩresults in amplifier GBW of approximately 50 MHz and a feedback capacitance (CF) of 1.1 pF as
shown in 图 9-2. These results are for a Butterworth response with a Q = 0.707 and a phase margin of
approximately 65° which corresponds to 4.3% overshoot.
Calculator II
Closed-loop TIA Bandwidth (f-3dB
Feedback Resistance (RF)
Input Capacitance (CIN)
)
2.00
100.00
20.00
50.27
1.110
MHz
kOhm
pF
Opamp Gain Bandwidth Product (GBP)
Feedback Capacitance (CF)
MHz
pF
图9-2. Results of Inputting Design Parameters in the TIA Calculator
The OPA607's 50 MHz GBW, is suitable for the above design requirements. If the required feedback
capacitance CF comes out to be a very low value capacitor to be practically achievable, a T-Network capacitor
circuit as shown below can be used. A very low capacitor value (CEQ) can be achieved between Port1 and Port2
using standard value capacitors in a T-Network circuit as shown in 图9-3.
C1 ì C2
C1 + C2 + CT
CEQ
=
(1)
Port1
Port2
C1
C2
CT
GND
图9-3. T-Network
9.2.1.3 Application Curves
120
110
100
90
80
6
5
4
3
2
1
0
VOUT
IPD
40
0
-40
80
-80
70
-120
-160
-200
-240
-280
-320
-360
-400
60
50
40
30
20
Gain (dB)
Phase (è)
10
0
10k
100k
1M
Frequency (Hz)
10M
100M
Time (50 msec/Div)
TIA_
OPA6
图9-5. Simulated Time Domain Response
图9-4. Simulated Closed-Loop Bandwidth of TIA
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9.2.2 Noninverting Gain of 3 V/V
The OPAx607 devices are normally stable in noise gain configurations (see SBOA066) of greater than 6 V/V
when conventional feedback networks are used, which is discussed in 节 8.3.4. The OPAx607 devices can be
configured in noise gains of less than 6 V/V by using capacitors in the feedback path and between the inputs to
maintain the desired gain at lower frequencies and increase the gain greater that 6 V/V at higher frequencies
such that the amplifier is stable. Configuration (a) in 图 9-6 shows OPAx607 devices configured in a gain of 3
V/V by using capacitors and resistors to shape the noise gain and achieve a phase margin of approximately 56°
that is very close to the phase margin achieved for the conventional 6 V/V configuration (b) in 图9-6.
The key benefit of using a decompensated amplifier (such as the OPAx607) below the minimum stable gain, is
that it takes advantage of the low noise and low distortion performance at quiescent powers smaller than
comparable unity-gain stable architectures. By reducing the 100-pF input capacitor, higher closed-loop
bandwidth can be achieved at the expense of increased peaking and reduced phase margin. Ensure that low
parasitic capacitance layout techniques on the IN– pin are as small as 1 pF to 2 pF of parasitic capacitance on
the inverting input, which will require tweaking the noise-shaping component values to get a flat frequency
response and the desired phase margin. Configurations in 图 9-6 does not take into account this parasitic
capacitance but it must be considered for practical purposes. Details on the benefits of decompensated
architectures are discussed in Using a decompensated op amp for improved performance. The one-capacitor,
externally compensated type method is used for noise gain shaping in the below circuit.
In a difference amplifier circuit, typically used for low side current sensing applications, the (noise gain) = (signal
gain + 1).
2.5 pF
2 kΩ
LOAD
GND
OPAx607
+5 V
+5 V
+5 V
1kΩ
ISH
OPAx607
OPAx607
VIN
VIN
+
+
+
VO
100 pF
VO
RSH
œ
œ
470 ꢀ
œ
470 ꢀ
100 pF
0 V
0 V
0V
2 kΩ
1kΩ
1 kꢀ
5 kꢀ
2 kꢀ
1 kꢀ
GND
2.5 pF
2.5 pF
2.5 pF
(b) G = 6 V/V
(c) G = 2 V/V
(a) G = 3 V/V
图9-6. Noninverting Gain of 3 V/V, 6 V/V Configurations and Difference Amplifier in Signal Gain of 2 V/V
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30
24
18
12
6
18
12
6
0
0
-6
-6
-12
-18
-24
-30
-12
-18
-24
-30
Gain = 3 V/V with Noise Gain Shaping
Gain = 3 V/V without Noise Gain Shaping
Gain = 6 V/V
Without Noise Gain Shaping
With Noise Gain Shaping
100k
1M
10M
100M
Freq
100k
1M
10M
100M
OPA6
Frequency (Hz)
Frequency (Hz)
图9-7. Small-Signal Frequency Response in Gains
图9-8. Small-Signal Frequency Response of
Difference Amplifier (c) With and Without Noise
Gain Shaping
of 3V/V (a) and 6V/V (b)
9.2.3 High-Input Impedance (Hi-Z), High-Gain Signal Front-End
0.4 nF
9 kΩ
SW
300 Ω
1.8 kΩ
40 kΩ
+2.5V
+2.5V
0.4 nF
œ
2 kΩ
0.1 ꢀF
œ
OPA607
+
To ADC/FDA
OPA837
+
105 Ω
-2.5V
100 kΩ
Ultrasonic Sensor
-2.5V
图9-9. Hi-Z, High-Gain Front-End Circuit
9.2.3.1 Design Requirements
The objective is to design a high-input impedance, high-dynamic range, signal-conditioning front-end. An
example application for such a front-end circuit is the receive signal chain in an ultrasonic-based end equipment
(EE) such as fish finders, printers and flow meters. 表9-2 lists the design requirements for this application.
表9-2. Design Parameters
PARAMETER
Amplifier supply
DESIGN REQUIREMENT
±2.5 V
Input signal frequency
Minimum voltage
200 kHz
300 µVrms
40 dB
Minimum SNR at 300 µVrms
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9.2.3.2 Detailed Design Procedure
To achieve a SNR of greater than 40 dB for signals from 300 uVrms to 30 mV the front-end stage has two gain
settings: 6 V/V and 31 V/V. The SW (switch, relay, or analog mux) can be dynamically toggled to ensure
maximum sensitively to the receiving signal. The OPAx607 devices prove to be an attractive solution for this
front-end signal chain because of the right balance of low noise and high input impedance. The ultrasonic
sensors (Ex. piezo crystal) have high output impedance. The OPAx607 devices have an input bias current of 20
pA (maximum). This small bias current results in reduced distortion and signal loss across the source impedance
when compared with a bipolar amplifier with input bias currents in the range of a few hundreds of nano-amperes.
The OPAx607's high-gain front-end is followed by a narrowband band-pass filter that is tuned to a 200-kHz
center frequency. The narrowband filter is designed using the OPA837. OPA837 can be used as a variable gain
mux / PGA as shown in TIDA-01565. In this application section the OPA837-based band-pass filter was
designed using the techniques mentioned in the Filter Design in Thirty Seconds application report.
图 9-11 shows the frequency response of circuit in 图 9-9. As shown in 图 9-11, the frequency response is a
high-Q factor band-pass filter centered around 200 kHz. Designing such a high-Q band-pass filter helps
eliminate white band noise along with other interferences present in the circuitry, resulting in a high SNR signal
chain. The OPAx607's front-end combined with the OPA837-based band-pass filter help to achieve a total gain
of 33 dB (44 V/V) or 50 dB (316 V/V) based on the SW (switch) position.
9.2.3.3 Application Curves
100
90
60
50
Gain setting = 33 dB
Gain setting = 50 dB
50 dB Gain
33 dB Gain
80
40
70
60
30
20
50
40
10
0
-10
-20
-30
-40
-50
30
20
100m
1m
Input RMS voltage (V)
10m
100m
100
1k
10k 100k
Frequency (Hz)
1M
10M
D001
D005
图9-10. Hi-Z, High-Gain Front-End Circuit SNR vs 图9-11. Hi-Z, High-Gain Front-End Circuit Gain vs
Input
Frequency
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9.2.4 Low-Cost, Low Side, High-Speed Current Sensing
VREF =1.24V
LOAD
CF
3.3V
3.3V
ISH
+
688 Ω
VOUT
VADC
1kΩ
1kΩ
ADS7042
RSH
OPA607
œ
GND
GND
240 pF
GND
GND
20 kΩ
CF
图9-12. Low Side Current Sensing
9.2.4.1 Design Requirements
The objective is to design a high-speed, high-gain bidirectional current-sensing circuit for power systems and
motor drive systems. 节9.2.4.2 lists the design requirements of this application.
表9-3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Amplifier and ADC supply
3.3 V
20 A
Peak current to be measured from load to ground
Peak current to be measured from ground to load
Required Accuracy of current measurement
Signal-Setting time at ADC input
12 A
0.1%
< 1 µs
Current sensing direction
Bidirectional
9.2.4.2 Detailed Design Procedure
The aim of this application section is to measure bidirectional current with relatively high accuracy in a low-side-
sensing-based, high-frequency switching system.
As shown in 图 9-12, a single op amp of high bandwidth is capable of sensing current in a high gain
configuration as well as have the required effective bandwidth to drive the consecutive SAR ADC input. The SAR
ADC can be a standalone ADC or integrated inside a Micro-controller.
VOUT = (20 kΩ/ 1 kΩ× VDIFF) + VREF, where VDIFF = ISH X RSH
(2)
The reference voltage is 1.24 V. When the ISH flowing across RSH equals zero, the VOUT of the difference
amplifier sits ideal at 1.24 V.
When the current (ISH) flows from LOAD to GND, the output of the OPAx607 increase above 1.24 V with a value
equal to 20 × VSH and when the current flows from GND to LOAD (in the opposite direction) the output of the
OPAx607 decrease below 1.24 V with a value proportional to 20 × VSH
.
One of the main challenges in a high speed current sensing design is to choose an op amp of with sufficient
GBW that can drive a SAR ADC, while still being able to gain the signal by the required amount. The 0.1% and
0.01% settling of OPAx607 can found in 节 7.5. Another key care about is to ensure the op amp output rises in
less than 1 µs so as to feed the output to a comparator for short-circuit protection. This comparator based short
circuit protection loop is extremely fast and enables to turn off the switching devices very quickly. This
requirement makes a low cost high speed part like the OPAx607 very desirable in a current-sensing circuit.
Equation of the rise time as a function of bandwidth is shown below.
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tR (10% to 90%) = 0.35 Hz / BW
(3)
For an ADC like ADS7042 running at a sampling rate of 500 kSPS of a clock of 12.5 MHz, the effective
bandwidth of the op amp required to drive such an ADC is approximately 2.7 MHz. See the TI precision lab
videos on driving SAR ADCs to understand the underlying calculation. The OPAx607 has a GBW of 50 MHz.
With a gain of 20 V/V, the closed loop bandwidth turns out to approximately 2.5 MHz, making this device the
most suitable, cost-optimized amplifier for this application. The RC charge bucket (240 Ωand 688 pF in 图9-12)
designed at the input of the SAR ADC is derived from the calculations provided in the SAR ADC precision lab
videos. The fundamental concept behind the design of this charge bucket filter is to ensure that the sample and
hold capacitor is charged to the required final voltage within the acquisition window of the ADC.
As shown in 图 9-14, a DC accuracy of higher than 0.05% is achieved with the OPAx607. The simulations are
captured with and without voltage offset calibration. Frequency response shown in 图 9-13 indicate different
signal bandwidth at VOUT, VADC and with and without CF of 220 pF.
9.2.4.3 Application Curves
6
5.2
4.4
3.6
2.8
2
0.2
30
24
18
12
6
0.16
0.12
0.08
0.04
0
0
1.2
0.4
-0.4
-1.2
-2
-0.04
-0.08
-0.12
-0.16
-0.2
-6
-12
-18
-24
-30
Measured Output
Ideal Output
% Error w/o callibration
% Error with callibration
VADC
VOUT
VOUT , CF = 220 pF
-20 -15 -10
-5
0
5
10
Current across RSH (A)
15
20
25
30
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D003
D010
图9-14. DC Current-Sense Transfer Function
图9-13. Frequency Response of Low Side Current
Sensing
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9.2.5 Ultrasonic Flow Meters
OPA607
OPA607
图9-15. High-Gain Ultrasonic Front-End
9.2.5.1 Design Requirements
The OPAx607 devices have a wide operating voltage range of 2.2 V to 5.5 V with a maximum quiescent current
of 1 mA. The availability of the inbuilt shutdown function enables designers to power cycle the front-end signal
chain, reducing the net quiescent current even further. The minimum operating voltage range of 2.2 V proves to
be very suitable for battery-powered and power sensitive applications such as the ultrasonic-based flow meters.
The high GBW of the OPAx607 devices enable the gain stages and the ADC drive stages to be designed and
combined, thereby reducing component count. A schematic similar to that of 图 9-12 can be used in ultrasonic
flow meters for the front-end signal chain.
The Ultrasonic sensing subsystem reference design for gas flow measurement design guide has a detailed
design procedure for ultrasonic-based sensing for gas flow measurement. The OPAx607 devices are very
suitable op amps for the discrete front-end design described in this design guide.
10 Power Supply Recommendations
The OPAx607 devices are specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V), applicable from –40°C
to +125°C. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from
noisy or high-impedance power supplies.
CAUTION
Supply voltages larger than 6 V can permanently damage the device (see 节7.1).
For more detailed information on bypass capacitor placement, see 节11.1.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power-supply pins of the circuit as a whole and of the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-equivalent series resistance (ESR), 0.1-µF ceramic bypass capacitors between each supply
pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is
applicable for single-supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make
sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than
crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance; see 图11-1 and 图11-2.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Examples
U1
OPAx607
INPUT
V-
C3
4
OUTPUT
2
GND
GND
1
3
R3
+
5
œ
OUTPUT
C4
6
V-
C2
V+
R1
GND
R2
C1
图11-1. Operational Amplifier Board Layout for a
图11-2. Layout Example Schematic
Noninverting Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
Texas Instruments, precision lab videos
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA2834 50-MHz, 170-μA, Negative-Rail In, Rail-to-Rail Out, Voltage-Feedback
Amplifier data sheet
• Texas Instruments, ADS7042 Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC data sheet
• Texas Instruments, Ultrasonic Sensing Subsystem Reference Design For Gas Flow Measurement design
guide
• Texas Instruments, OPAx836 Very-Low-Power, Rail-to-Rail Out, Negative Rail In, Voltage-Feedback
Operational Amplifiers data sheet
• Texas Instruments, Filter Design in Thirty Seconds application report
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.6 Trademarks
Excel™ is a trademark of Microsoft Coproration.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
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22-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2607IDGKR
OPA2607IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2FRT
NIPDAU
NIPDAUAG
NIPDAU
NIPDAU
NIPDAU
NIPDAU
OP2607
KJF
OPA2607SIRUGR
OPA607IDBVR
OPA607IDBVT
OPA607IDCKR
OPA607IDCKT
X2QFN
SOT-23
SOT-23
SC70
RUG
DBV
DBV
DCK
DCK
10
5
O6BV
O6BV
1G4
5
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
6
SC70
6
1G4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jul-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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OTHER QUALIFIED VERSIONS OF OPA2607, OPA607 :
Automotive : OPA2607-Q1, OPA607-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2607IDGKR
OPA2607IDR
VSSOP
SOIC
DGK
D
8
8
2500
2500
3000
3000
250
330.0
330.0
178.0
180.0
180.0
180.0
180.0
12.4
12.4
8.4
5.3
6.4
3.4
5.2
2.25
3.2
3.2
2.3
2.3
1.4
2.1
8.0
8.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
8.0
Q1
Q1
Q1
Q3
Q3
Q3
Q3
OPA2607SIRUGR
OPA607IDBVR
OPA607IDBVT
OPA607IDCKR
OPA607IDCKT
X2QFN
SOT-23
SOT-23
SC70
RUG
DBV
DBV
DCK
DCK
10
5
1.75
3.2
0.56
1.4
8.4
8.0
5
8.4
3.2
1.4
8.0
6
3000
250
8.4
2.47
2.47
1.25
1.25
8.0
SC70
6
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2607IDGKR
OPA2607IDR
VSSOP
SOIC
DGK
D
8
8
2500
2500
3000
3000
250
366.0
356.0
205.0
210.0
210.0
213.0
213.0
364.0
356.0
200.0
185.0
185.0
191.0
191.0
50.0
35.0
33.0
35.0
35.0
35.0
35.0
OPA2607SIRUGR
OPA607IDBVR
OPA607IDBVT
OPA607IDCKR
OPA607IDCKT
X2QFN
SOT-23
SOT-23
SC70
RUG
DBV
DBV
DCK
DCK
10
5
5
6
3000
250
SC70
6
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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