OPA658NB/3K [TI]
Wideband, Low Power Current Feedback Operational Amplifier 5-SOT-23;
| 型号： | OPA658NB/3K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Wideband, Low Power Current Feedback Operational Amplifier 5-SOT-23 放大器 光电二极管 |
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OPA658
OPA658
OPA658
SBOS045A – MARCH 1994 – REVISED JUNE 2003
Wideband, Low-Power, Current-Feedback
Operational Amplifier
FEATURES
DESCRIPTION
● UNITY-GAIN STABLE BANDWIDTH: 900MHz
The OPA658 is an ultra-wideband, low power current feed-
back video operational amplifier featuring high slew rate and
low differential gain/phase error. The current feedback de-
sign allows for superior large signal bandwidth, even at high
gains. The low differential gain/phase errors, wide bandwidth
and low quiescent current make the OPA658 a perfect
choice for numerous video, imaging and communications
applications.
● LOW POWER: 50mW
● LOW DIFFERENTIAL GAIN/PHASE ERRORS:
0.025%/0.02°
● HIGH SLEW RATE: 1700V/µs
● GAIN FLATNESS: 0.1dB to 135MHz
● HIGH OUTPUT CURRENT (80mA)
The OPA658 is optimized for low gain operation and is also
available in dual (OPA2658) configurations.
APPLICATIONS
● MEDICAL IMAGING
● HIGH-RESOLUTION VIDEO
● HIGH-SPEED SIGNAL PROCESSING
● COMMUNICATIONS
+VS
Current Mirror
● PULSE AMPLIFIERS
IBIAS
● ADC/DAC GAIN AMPLIFIER
● MONITOR PREAMPLIFIER
● CCD IMAGING AMPLIFIER
In+
In–
VOUT
Buffer
CCOMP
IBIAS
Current Mirror
–VS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1994-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Supply ............................................................................................... ±5.5V
Internal Power Dissipation........................... See Thermal Characteristics
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range............................................................................ ±VS
Storage Temperature Range: P, U, UB, N ....................–40°C to +125°C
Lead Temperature (soldering, 10s) ............................................... +300°C
(soldering, SO 3s) .......................................... +260°C
Junction Temperature (TJ) ............................................................ +150°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA658
"
SO-8 Surface-Mount
D
"
–40°C to +85°C
"
OPA658U
"
OPA658U
OPA658U/2K5
OPA658UB
Rails, 100
Tape and Reel, 2500
Rails, 100
"
OPA658
SO-8 Surface-Mount
D
–40°C to +85°C
OPA658UB
"
OPA658
"
"
SOT23-5
"
"
DBV
"
"
"
A58
OPA658UB/2K5
OPA658N/250
OPA658N/3K
OPA658P
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Rails, 50
–40°C to +85°C
"
"
OPA658
DIP-8
P
–40°C to +85°C
OPA658P
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View
DIP, SO
Top View
SOT23
NC
1
8
NC
Output
–VS
1
5
4
+VS
–Input
+Input
–VS
2
3
4
7
6
5
+VS
2
3
Output
NC
+Input
–Input
NC = No Connection
OPA658
2
SBOS045A
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
OPA658P, U, N
OPA658UB
TYP
PARAMETER
CONDITION
MIN
TYP
MAX
MIN
MAX
UNITS
FREQUENCY RESPONSE
(3)
Closed-Loop Bandwidth(1)
G = +1(2)
G = +2
G = +5
900
680
370
200
1700
1500
15
11.5
6
68
56
40
0.025
0.02
135(5)
✻
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
400
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
G = +10
G = +2, 2V Step
Slew Rate(4)
At Minimum Specified Temperature
Settling Time: 0.01%
1000
900
G = +2, 2V Step
G = +2, 2V Step
G = +2, 2V Step
0.1%
1%
ns
ns
Spurious-Free Dynamic Range
f = 5MHz, G = +2, VO = 2VPP
f = 20MHz, G= +2, VO = 2VPP
f = 10MHz, 4dBm Each Tone
G = +2, NTSC, VO = 1.4VPP, RL = 150Ω
G = +2, NTSC, VO = 1.4VPP, RL = 150Ω
G = +2
dBc
dBc
dBm
%
degrees
MHz
3rd-Order Intercept Point
Differential Gain
Differential Phase
Bandwidth for 0.1dB Flatness
OFFSET VOLTAGE
Input Offset Voltage
Over Temperature Range
Power-Supply Rejection Ratio
VCM = 0V
±3
±5
64
±5.5
±8
±2
±4
67
±4.5
±7
mV
mV
dB
VS = ±4.7 to ±5.5V
55
58
INPUT BIAS CURRENT
Noninverting
Over Temperature Range
Inverting
VCM = 0V
VCM = 0V
±5.7
±10
±1.1
±30
±30
±80
±35
±75
✻
✻
✻
✻
±18
±35
✻
µA
µA
µA
µA
Over Temperature Range
✻
NOISE
Input Voltage Noise Density
f = 100Hz
f = 2kHz
f = 10kHz
f = 1MHz
fB = 100Hz to 200MHz
Input Bias Current Noise Density
Inverting: f = 1MHz
Noninverting: f = 1MHz
16
4.9
3.2
3.2
45.3
✻
✻
✻
✻
✻
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
32
11.9
✻
✻
pA/√Hz
pA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Input Range
Over Temperature Range
Common-Mode Rejection
±2.5
45
±2.9
50
✻
✻
✻
✻
V
dB
VCM = ±1V
INPUT IMPEDANCE
Noninverting
Inverting
500 || 1
50
✻
✻
kΩ || pF
Ω
OPEN-LOOP TRANSRESISTANCE
Open-Loop Transresistance
Over Temperature Range
VO = ±2V, RL = 100Ω
VO = ±2V, RL = 100Ω
150
100
190
200
150
250
kΩ
kΩ
OUTPUT
Voltage Output
Over Temperature Range
Voltage Output
Over Temperature Range
Voltage Output
Over Temperature Range
Output Current, Sourcing
Over Temperature
Output Current, Sinking
Over Temperature
Short Circuit Current
Output Resistance
No Load
RL = 250Ω
RL = 100Ω
±2.7
±2.5
±2.7
±2.5
±2.2
±2.0
80
70
60
35
±2.9
±2.75
±2.9
±2.7
±2.8
±2.5
120
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
V
V
V
mA
mA
mA
mA
mA
Ω
80
✻
150
0.02
✻
✻
0.1MHz, G = +2
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
±5
✻
V
V
mA
mA
±4.5
±5.5
±7.75
±8.5
✻
✻
✻
±5.75
±6.5
VS = ±5V
±5
±5.5
±4.5
±4.7
Over Temperature Range
TEMPERATURE RANGE
Specification: P, U, N, UB
Thermal Resistance, θJA
–40
+85
✻
°C
P
U
N
DIP-8
SO-8
SOT23-5
100
125
150
✻
✻
✻
°C/W
°C/W
°C/W
(1) Frequency response can be strongly influenced by PC board parasitics. The demonstration boards show low parasitic layouts for this part. Refer to the
demonstration board layout for details.
(2) At G = +1, RFB = 560Ω for DIP and 402Ω for SO-8.
(3) An asterisk (✻) specifies the same value as the grade to the left.
(4) Slew rate is rate of change from 10% to 90% of output voltage step.
(5) This specification is PC board layout dependent.
OPA658
SBOS045A
3
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO AND
COMMON-MODE REJECTION
COMMON-MODE REJECTION vs TEMPERATURE
75
vs INPUT COMMON-MODE VOLTAGE
55
50
45
40
35
30
25
70
PSRR
65
60
PSR+
55
PSR–
50
CMR
45
–4
–75
–75
–3
–2
–1
0
1
2
3
4
–75
–50
–25
0
25
50
75
100
125
Common-Mode Voltage (V)
Temperature (°C)
SUPPLY CURRENT vs TEMPERATURE
OUTPUT CURRENT vs TEMPERATURE
IO+
5.5
5.0
4.5
4.0
3.5
120
110
100
90
80
IO–
70
–50
–25
0
25
50
75
100 125
–75
–50
–25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
NONINVERTING INPUT BIAS CURRENT
vs TEMPERATURE
OUTPUT SWING vs TEMPERATURE
3.20
3.10
3.00
2.90
2.80
2.70
2.60
2.50
2.40
2.30
10
9
RL = 250Ω
+VO
8
–VO
7
6
–VO
RL = 100Ω
+VO
5
4
3
2
–60
–40
–20
0
20
40
60
80
100
–50
–25
0
25
50
75
100
125
Temperature (°C)
Ambient Temperature (°C)
OPA658
4
SBOS045A
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
INVERTING INPUT BIAS CURRENT
vs TEMPERATURE
OPEN-LOOP TRANSIMPEDANCE AND PHASE
vs FREQUENCY
106
105
104
103
102
101
1
45
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
Transimpedance
0
–45
–90
–135
Phase
–180
–225
1k
10k
100k
1M
10M
100M
1G
–75
–50
–25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
Gain
CLOSED-LOOP BANDWIDTH
60
40
45
6
3
G = +1
SO-8 Bandwidth = 881MHz, RFB = 402Ω
0
20
–45
–90
–135
–180
–225
0
Phase
0
–3
–6
–9
–20
–40
–60
DIP Bandwidth = 949MHz, RFB = 560Ω
1k
10k
100k
1M
10M
100M
1G
1M
10M
100M
Frequency (Hz)
1G
Frequency (Hz)
CLOSED-LOOP BANDWIDTH
DIP Bandwidth = 682MHz
CLOSED-LOOP BANDWIDTH
SO-8/DIP Bandwidth= 372MHz
20
17
14
11
8
9
6
G = +5
G = +2
3
0
SO-8 Bandwidth = 680MHz
–3
–6
5
2
1M
10M
100M
1G
1M
10M
100M
Frequency (Hz)
1G
Frequency (Hz)
OPA658
SBOS045A
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
SMALL-SIGNAL TRANSIENT RESPONSE
G = +2
CLOSED-LOOP BANDWIDTH
26
160
120
80
G = +10
23
SO-8/DIP Bandwidth = 200MHz
20
40
17
14
11
8
0
–40
–80
–120
–160
1M
10M
100M
Frequency (Hz)
1G
Time (5ns/div)
RECOMMENDED ISOLATION RESISTANCE
vs CAPACITIVE LOAD
LARGE-SIGNAL TRANSIENT RESPONSE
40
35
30
25
20
15
10
1.6
1.2
G = +2
G = +2
0.8
0.4
0
RISO
–0.4
–0.8
–1.2
–1.6
OPA658
CL
1kΩ
402Ω
402Ω
10
20
30
40 50 60 70 80 90100
Time (5ns/div)
Capacitive Load (pF)
HARMONIC DISTORTION vs FREQUENCY
5MHz HARMONIC DISTORTION vs OUTPUT SWING
G = +2
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
3fO
2fO
2fO
3fO
0
1
2
3
4
100k
1M
10M
Frequency (Hz)
100M
Output Swing (VPP
)
OPA658
6
SBOS045A
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
HARMONIC DISTORTION vs TEMPERATURE
10MHz HARMONIC DISTORTION vs OUTPUT SWING
–60
–60
–65
–70
–75
–80
–85
VO = 2VPP
G = +2
3fO
2fO
–70
2fO
–80
3fO
–90
–100
–75
–50
–25
0
25
50
75
100 125
0.01
0.1
Output Swing (VPP
1
4V
10
Temperature (°C)
)
INPUT VOLTAGE AND CURRENT NOISE
vs FREQUENCY
HARMONIC DISTORTION vs GAIN
100
10
1
–50
–55
–60
–65
–70
–75
fO = 5MHz
VO = 2VPP
Inverting Current Noise
Noninverting Noise
3fO
Voltage Noise
2fO
102
103
104
105
106
107
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Noninverting Gain (V/V)
OPA658
SBOS045A
7
www.ti.com
For noninverting operation, the input signal is applied to the
noninverting (high impedance buffer) input. The output (buffer)
error current (IE) is generated at the low impedance inverting
input. The signal generated at the output is fed back to the
inverting input such that the overall gain is (1 + RFB/RFF).
Where a voltage-feedback amplifier has two symmetrical
high impedance inputs, a current-feedback amplifier has a
low inverting (buffer output) impedance and a high noninverting
(buffer input) impedance.
APPLICATIONS INFORMATION
THEORY OF OPERATION
Conventional op amps depend on feedback to drive their
inputs to the same potential, however the current-feedback
op amp’s inverting and noninverting inputs are connected by
a unity-gain buffer, thus enabling the inverting input to
automatically assume the same potential as the noninverting
input. This results in very low impedance at the inverting
input to sense the feedback as an error current signal.
The closed-loop gain for the OPA658 can be calculated
using Equations 1 and 2.
DISCUSSION OF PERFORMANCE
RFB
−
RFF
The OPA658 is a low-power, unity-gain stable, current-
feedback operational amplifier which operates on ±5V power
supply. The current-feedback architecture offers the follow-
ing important advantages over voltage-feedback architec-
tures: (1) the high slew rate allows the large-signal perfor-
mance to approach the small-signal performance, and (2)
there is very little bandwidth degradation at higher gain
settings.
Inverting Gain =
(1)
1
1+
Loop Gain
RFB
1+
RFF
Noninverting Gain =
1
1+
Loop Gain
The current-feedback architecture of the OPA658 provides
the traditional strength of excellent large-signal response
plus wide bandwidth, making it a good choice for use in high-
resolution video, medical imaging and Digital-to-Analog Con-
verter (DAC) I/V Conversion. The low-power requirements
make it an excellent choice for numerous portable applica-
tions.
(2)
TO
where Loop Gain =
RFB
RFB
+
1+
RFF
RS
At higher gains, the small value inverting input impedance
causes an apparent loss in bandwidth. This can be seen from
Equation 3.
DC GAIN TRANSFER CHARACTERISTICS
The circuit in Figure 1 shows the equivalent circuit for
calculating the DC gain. When operating the device in the
inverting mode, the input signal error current (IE) is amplified
by the open loop transimpedance gain (TO). The output
signal generated is equal to TO x IE. Negative feedback is
applied through RFB such that the device operates at a gain
equal to –RFB/RFF.
f
BW × 1.25
(
)
[
A
= +2
]
(
)
V
f ACTUALBW ≈
RS
RFB
RFF
(3)
1+
× 1+
RFB
This loss in bandwidth at high gains can be corrected without
affecting stability by lowering the value of the feedback
resistor from the specified value of 402Ω.
OFFSET VOLTAGE AND NOISE
The output offset is the algebraic sum of the input offset
voltage and bias current errors. The output offset for the
model of Figure 2 is calculated by Equation 4.
Output Offset Voltage =
CC
+
IE
RS
LS
RFF
RFB
RFF
RFB
RFF
VO
(4)
TO
±IbN × RN 1+
± VIO 1+
±IbN × RFB
–
VN
(50Ω)
C1
VI
RFB
RFF
IbI
RFB
IbN
RN
VIO
FIGURE 1. Equivalent Circuit.
8
FIGURE 2. Output Offset Voltage Equivalent Circuit.
OPA658
SBOS045A
www.ti.com
If all terms are divided by the gain (1 + RFB/RFF) it can be
observed that input referred offsets improve as gain in-
creases. The effective noise at the output can be determined
by taking the root sum of the squares of Equation 4 and
applying the spectral noise values found in the Typical
Characteristics section. This applies to noise from the op
amp only. Note that both the noise figure (NF) and the
equivalent input offset voltages improve as the closed-loop
gain increases (by keeping RFB fixed and reducing RFF with
RN = 0Ω).
The feedback resistor value acts as the frequency response
compensation element for a current-feedback type amplifier.
The 402Ω used in setting the specification achieves a nomi-
nal maximally-flat butterworth response while assuming a
2pF output pin parasitic. Increasing the feedback resistor will
overcompensate the amplifier, rolling off the frequency re-
sponse, while decreasing it will decrease phase margin,
peaking up the frequency response. Note that a noninverting,
unity-gain buffer application still requires a feedback resistor
for stability (560Ω for SO-8, 402Ω for DIP, and 324Ω for
SOT23).
INCREASING BANDWIDTH AT HIGH GAINS
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RISO from the
plot of recommended RISO vs capacitive load. Low parasitic
loads may not need an RISO since the OPA658 is nominally
compensated to operate with a 2pF parasitic load.
The closed-loop bandwidth can be extended at high gains by
reducing the value of the feedback resistor RFB. This band-
width reduction is caused by the feedback current being split
between RS and RFF (refer to Figure 1). As the gain increases
(for a fixed RFB), more feedback current is shunted through
RFF, which reduces closed-loop bandwidth.
CIRCUIT LAYOUT AND BASIC OPERATION
Achieving optimum performance with a high-frequency am-
plifier such as the OPA658 requires careful attention to
layout parasitics and selection of external components. Rec-
ommendations for PC board layout and component selection
include:
If a long trace is required and the 6dB signal loss intrinsic to
doubly-terminated transmission lines is acceptable, imple-
ment a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environ-
ment is not necessary onboard, and in fact a higher imped-
ance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance de-
fined based on board material and desired trace dimensions,
a matching series resistor into the trace from the output of the
amplifier is used as well as a terminating shunt resistor at the
input of the destination device. Remember also that the
terminating impedance will be the parallel combination of the
shunt resistor and the input impedance of the destination
device; the total effective impedance should match the trace
impedance. Multiple destination devices are best handled as
separate transmission lines, each with their own series and
shunt terminations.
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability; on the noninverting
input it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes. Otherwise, ground and
power planes should be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25") from the two power pins
to high-frequency 0.1µF decoupling capacitors. At the pins,
the ground and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2µF to 6.8µF) decou-
pling capacitors, effective at lower frequencies, should also
be used. These may be placed somewhat farther from the
device and may be shared among several devices in the
same area of the PC board.
If the 6dB attenuation loss of a doubly-terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly-terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA658. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded resis-
tors can also provide good high-frequency performance.
Again, keep their leads as short as possible. Never use wire-
wound type resistors in a high-frequency application.
e) Socketing a high-speed part like the OPA658 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost
impossible to achieve a smooth, stable response. Best re-
sults are obtained by soldering the part onto the board. If
socketing for the DIP package is desired, high-frequency,
flush-mount pins (for instance, McKenzie Technology #710C)
can give good results.
Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feed-
back and series output resistor, if any, as close as possible
to the package pins. Other network components, such as
noninverting input termination resistors, should also be placed
close to the package.
OPA658
SBOS045A
9
www.ti.com
The OPA658 is nominally specified for operation using
±5V power supplies. A 10% tolerance on the supplies, or an
ECL –5.2V for the negative supply, is within the maximum
specified total supply voltage of 11V. Higher supply voltages
can break down internal junctions possibly leading to cata-
strophic failure. Single-supply operation is possible as long
as common-mode voltage constraints are observed. The
common-mode input and output voltage specifications can
be interpreted as a required headroom to the supply voltage.
Observing this input and output headroom requirement will
allow non-standard or single-supply operation. Figure 3 shows
one approach to single-supply operation.
100
10
1
0.1
G = +2
0.01
0.001
10k
100k
1M
Frequency (Hz)
10M
100M
+VS
+VS
FIGURE 4. Closed-Loop Output Impedance vs Frequency.
VS
2
VS
2
VOUT
=
+ AV VAC
ROUT
THERMAL CONSIDERATIONS
The OPA658 will not require heatsinking under most operat-
ing conditions. Maximum desired junction temperature will
set a maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
VAC
OPA658
RL
Operating junction temperature (TJ) is given by TA + PD × θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition PDL = VS2/(4 × RL) where RL
includes feedback network loading.
402Ω
AV = +2
402Ω
FIGURE 3. Single-Supply Operation.
ESD PROTECTION
ESD static damage has been well recognized for MOSFET
devices, but any semiconductor device deserves protection
from this potentially damaging source. This is particularly true
for very high-speed, fine geometry processes.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an example, compute the maximum TJ for an OPA658N
at AV = +2, RL = 100Ω, RFB = 402Ω, ±VS = ±5V, and the
specified maximum TA = +85°C.
ESD static damage can cause subtle changes in amplifier
input characteristics without necessarily destroying the de-
vice. In precision operational amplifiers, this may cause a
noticeable degradation of offset voltage and drift. Therefore,
static protection is strongly recommended when handling the
OPA658.
PD = 10V × 8.5mA + 52/[4 × (100Ω || 804Ω)] = 155mW
Maximum TJ = 85°C + 0.155W × 150°C/W = 108°C
DRIVING CAPACITIVE LOADS
The OPA658’s output stage has been optimized to drive low
resistive loads. Capacitive loads, however, will decrease the
amplifier’s phase margin which may cause high-frequency
peaking or oscillations. Capacitive loads greater than 5pF
should be buffered by connecting a small resistance, usually
10Ω to 35Ω, in series with the output as illustrated in Figure 5.
This is particularly important when driving high capacitance
loads such as flash ADCs.
OUTPUT DRIVE CAPABILITY
The OPA658 has been optimized to drive 75Ω and 100Ω
resistive loads. The device can drive 2VPP into a 75Ω load.
This high-output drive capability makes the OPA658 an ideal
choice for a wide range of RF, IF, and video applications. In
many cases, additional buffer amplifiers are unneeded.
Many demanding high-speed applications such as Analog-to-
Digital Converter (ADC)/DAC buffers require op amps with low
wideband output impedance. For example, low output imped-
ance is essential when driving the signal-dependent capaci-
tances at the inputs of flash ADCs. As shown in Figure 4, the
OPA658 maintains very low closed-loop output impedance
over frequency. Closed-loop output impedance increases with
frequency since loop gain is decreasing with frequency.
In general, capacitive loads should be minimized for opti-
mum high-frequency performance. Coaxial lines can be
driven if the cable is properly terminated. The capacitance of
coaxial cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable or transmission line is terminated with
its characteristic impedance.
OPA658
10
SBOS045A
www.ti.com
appear at fO ± 3 × Df. The 2-tone, 3rd-order spurious plot
shown in Figure 7 indicates how far below these two equal
power, closely-spaced tones the intermodulation spurious
will be. The single-tone power is at a matched 50Ω load. The
unique design of the OPA658 provides much greater spuri-
ous free range than what a 2-tone, 3rd-order intermodulation
intercept specification would predict. This can be seen in
Figure 7 as the spurious-free range actually increases at the
higher output power levels.
402Ω
402Ω
10Ω to 35Ω
RISO
OPA658
RL
CL
50Ω
FIGURE 5. Driving Capacitive Loads.
2-TONE, 3RD-ORDER SPURIOUS LEVELS
–65
COMPENSATION
20MHz
The OPA658 is internally compensated and is stable in unity
gain with a phase margin of approximately 62°, and approxi-
mately 64° in a gain of +2V/V when used with the recom-
mended feedback resistor value. Frequency response for
other gains are shown in the Typical Characteristics.
–70
10MHz
–75
5MHz
–80
The high-frequency response of the OPA658 in a good
layout is very flat with frequency.
–85
–90
DISTORTION
–18 –16 –14 –12 –10 –8 –6 –4 –2
Single-Tone Power (dBm)
0
2
4
The OPA658’s Harmonic Distortion characteristics into a
100Ω load are shown versus frequency and power output in
the Typical Characteristics. Distortion can be further im-
proved by increasing the load resistance as illustrated in
Figure 6. Remember to include the contribution of the feed-
back resistance when calculating the effective load resis-
tance seen by the amplifier.
FIGURE 7. 3rd-Order Spurious Level vs Frequency.
DIFFERENTIAL GAIN AND PHASE
Differential Gain (dG) and Differential Phase (dP) are among
the more important specifications for video applications. dG
is defined as the percent change in closed-loop gain over a
specified change in output voltage level. dP is defined as the
change in degrees of the closed-loop phase over the same
output voltage change. Both dG and dP are specified at the
NTSC sub-carrier frequency of 3.58MHz and the PAL sub-
carrier of 4.43MHz. All NTSC measurements were performed
using a Tektronix model VM700A Video Measurement Set.
5MHz HARMONIC DISTORTION vs
LOAD RESISTANCE (G = +2)
–55
G = +2
VO = 2VPP
–60
fO = 5MHz
–65
–70
dG/dP of the OPA658 were measured with the amplifier in a
gain of +2V/V with 75Ω input impedance and the output
back-terminated in 75Ω. The input signal selected from the
generator was a 0V to 1.4V modulated ramp with sync pulse.
With these conditions the test circuit shown in Figure 8
delivered a 100IRE modulated ramp to the 75Ω input of the
videoanalyzer. The signal averaging feature of the analyzer
was used to establish a reference against which the perfor-
3fO
2fO
–75
–80
–85
10
100
1k
Load Resistance (Ω)
FIGURE 6. 5MHz Harmonic Distortion vs Load Resistance.
75Ω
75Ω
Narrowband communication channel requirements will ben-
efit from the OPA658’s wide bandwidth and low
intermodulation distortion on low quiescent power. If output
signal power at two closely spaced frequencies is required,
3rd-order nonlinearities in any amplifier will cause spurious
power at frequencies very near the two fundamental frequen-
cies. If the two test frequencies, f1 and f2, are specified in
terms of average and delta frequency, fO = (f1 + f2)/2 and
Df = Ωf2 – f1Ω, the two, 3rd-order, close-in spurious tones will
OPA658
75Ω
402Ω
75Ω
402Ω
TEK TSG 130A
TEK VM700A
FIGURE 8. Configuration for Testing Differential Gain/Phase.
OPA658
SBOS045A
11
www.ti.com
mance of the amplifier was measured. Signal averaging was
also used to measure the dg and dp of the test signal in order
to eliminate the generator’s contribution to measured ampli-
fier performance. Typical performance of the OPA658 is
0.025% differential gain and 0.02° differential phase to both
NTSC and PAL standards.
BOARD
PART
NUMBER
LITERATURE
REQUEST
NUMBER
PRODUCT
PACKAGE
OPA658U
OPA658N
OPA658P
SO-8
SOT23-5
DIP-8
DEM-OPA68xU
DEM-OPA6xxN
DEM-OPA68xP
SBOU009
SBOU010
SBOU008
TABLE I. Demo Board Part/Ordering Numbers.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
To request any of these boards, check the Texas Instru-
ments web site at www.ti.com.
Several PC boards are available to assist in the initial
evaluation of circuit performance using the OPA658 in its
three package styles. All of these are available free as an
unpopulated PC board delivered with descriptive documen-
tation. The summary information for these boards is shown
in Table I.
OPA658
12
SBOS045A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
OPA658N/250
OPA658N/3K
OPA658NB/250
OPA658NB/3K
OPA658P
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
SOT-23
SOT-23
SOT-23
SOT-23
PDIP
DBV
DBV
DBV
DBV
P
5
5
5
5
8
8
8
8
8
8
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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0 to 70
OPA658U
SOIC
D
OPA658U-1
SOIC
D
OPA658U/2K5
OPA658UB
SOIC
D
SOIC
D
OPA658UB/2K5
SOIC
D
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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