OPA726AID [TI]
具有关断功能的单路、12V、20MHz 运算放大器 | D | 8 | -40 to 125;
| 型号： | OPA726AID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有关断功能的单路、12V、20MHz 运算放大器 | D | 8 | -40 to 125 放大器 运算放大器 |
| 文件： | 总31页 (文件大小：1155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA725, OPA2725
OPA726, OPA2726
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
Very Low Noise, High-Speed, 12V CMOS
Operational Amplifier
FD EATURES
DESCRIPTION
The OPA725 and OPA726 series op amps use a
state-of-the-art 12V analog CMOS process, and combine
outstanding ac performance with low bias current and
excellent CMRR, PSRR, and AOL
Gain-Bandwidth (GBW) Product is achieved by using a
proprietary and patent-pending output stage design.
These characteristics allow excellent 16-bit settling times
for driving 16-bit Analog-to-Digital converters (ADCs).
BANDWIDTH: 20MHz
SLEW RATE: 30V/µs
D
D
D
D
D
D
D
D
D
D
FAST 16-BIT SETTLING TIME
LOW NOISE: 6nV/√Hz (typ) at 100kHz
EXCELLENT CMRR, PSRR, and A
OL
RAIL-TO-RAIL OUTPUT
.
The 20MHz
CM RANGE INCLUDES GND
THD+N: 0.0003% (typ) at 1kHz
QUIESCENT CURRENT: 5.5mA/ch (max)
SUPPLY VOLTAGE: 4V to 12V
SHUTDOWN MODE (OPAx726): 6µA/ch
Excellent ac characteristics, such as 20MHz GBW, 30V/µs
slew rate and 0.0003% THD+N make the OPA725 and
OPA726 well-suited for communication, high-end audio,
and active filter applications. With a bias current of less
than 200pA, they are well-suited for use as
transimpedance (I/V-conversion) amplifiers for monitoring
optical power in ONET applications.
AD PPLICATIONS
OPTICAL NETWORKING
D
D
D
D
D
D
D
D
TRANSIMPEDANCE AMPLIFIERS
INTEGRATORS
ACTIVE FILTERS
A/D CONVERTER BUFFERS
I/V CONVERTER FOR DACs
PORTABLE AUDIO
PROCESS CONTROL
TEST EQUIPMENT
The OPA725 and OPA726 op amps can be used in
single-supply applications from 4V up to 12V, or
dual-supply from 2V to 6V. The output swings to within
150mV of the rails, maximizing dynamic range. The
shutdown versions (OPAx726) reduce the quiescent
current to less than 6µA and feature a reference pin for
easy shutdown operation with standard CMOS logic in
dual-supply applications.
OPA725 RELATED PRODUCTS
FEATURES
The OPA725 (single) is available in SOT23-5 and SO-8
packages, and the OPA2725 (dual) is available in MSOP-8
and SO-8 packages. The OPA726 (single with shutdown)
is available in MSOP-8 and SO-8. The OPA2726 (dual with
shutdown) is available in MSOP-10. All versions are
specified for operation from −40°C to +125°C.
PRODUCT
10MHz, 16V, 16V/µs, 8.5nV/√Hz at 1kHz
TLC080
OPA132
OPA380
OPA656
OPA743
ADS8342
8MHz, 36V, FET Input, 20V/µs, 8.5nV/√Hz at 1kHz
100MHz, 5.5V, Precision Transimpedance Amplifier
500MHz, 5V, FET Input, 290V/µs, 7nV/√Hz at 100kHz
7MHz, 12V, RRIO, 10V/µs, 30nV/√Hz at 10kHz
16-Bit, 250kSPS, 4-Channel, Parallel Output ADC
+5V
+5V
+12V
Ω
75
OPA725
AIN
VIN
OPA726
VOUT
ADS8342
16−Bit ADC
Common
λ
2.5V
330pF
−
5V
Enable
−
V
5V
−
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2003−2004, Texas Instruments Incorporated
www.ti.com
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
(1)
Non-Shutdown
OPA725
SOT23-5
DBV
−40°C to +125°C
OALI
″
OPA725A
OPA725AIDBVT
OPA725AIDBVR
OPA725AID
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
″
″
SO-8
″
″
D
″
″
OPA725
−40°C to +125°C
″
″
″
OPA725AIDR
Tape and Reel, 2500
OPA2725
SO-8
″
MSOP-8
D
−40°C to +125°C
OPA2725A
OPA2725AID
OPA2725AIDR
OPA2725AIDGKT
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
″
″
DGK
″
″
″
BGM
″
OPA2725
−40°C to +125°C
″
″
″
OPA2725AIDGKR Tape and Reel, 2500
Shutdown
OPA726
SO-8
″
MSOP-8
D
−40°C to +125°C
OPA726A
OPA726AID
OPA726AIDR
OPA726AIDGKT
OPA726AIDGKR Tape and Reel, 2500
OPA2726AIDGST Tape and Reel, 250
OPA2726AIDGSR Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
″
″
DGK
″
″
″
BHC
″
OPA726
−40°C to +125°C
″
″
″
OPA2726
MSOP-10
DGS
″
−40°C to +125°C
BHB
″
″
″
″
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
(1)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.2V
(2)
Signal Input Terminals, Voltage
. . . . . . . . . −0.5V to (V+) + 0.5V
. . . . . . . . . . . . . . . . . . . 10mA
proper handling and installation procedures can cause damage.
(2)
Current
(3)
Output Short Circuit
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
. . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C
Storage Termperature . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . 1000 V
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2)
(3)
Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails should be current limited to 10mA or less.
Short-circuit to ground, one amplifier per package.
2
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
PIN CONFIGURATIONS
OPA725
OPA726
OPA725
NC(1)
V+
Enable
V+
NC(1)
1
2
3
4
8
7
6
5
DGND(2)
1
2
3
4
8
7
6
5
Out
1
2
3
5
4
V+
−
−
IN
IN
−
V
OUT
NC(1)
OUT
NC(1)
+IN
+IN
−
+IN
IN
−
V
−
V
SOT23−5
SO−8
SO−8, MSOP−8
OPA2725
OPA2726
OUT A
1
2
3
4
8
V+
OUT A
1
2
3
4
5
10 V+
A
A
−
−
IN A
7
6
5
OUT B
IN A
9
8
7
6
OUT B
B
B
−
−
IN B
+IN A
IN B
+IN A
−
−
V
V
+IN B
+IN B
DGND(2)
Enable
SO−8, MSOP−8
MSOP−10
(1)
(2)
NC denotes no internal connection.
DGND = reference voltage for Enable Reference pin. Voltage on this pin
will be the voltage to which the Enable Reference pin is referenced.
3
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS: V = +4V to +12V or V = 2V to 6V
S
S
Boldface limits apply over the specified temperature range, T = −40°C to +125°C.
A
At T = +25°C, R = 10kΩ connected to V /2, and V
= V /2, unless otherwise noted.
A
L
S
OUT
S
OPA725, OPA726, OPA2725, OPA2726
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
OFFSET VOLTAGE
Input Offset Voltage
OPA725, OPA726
OPA2725, OPA2726
Drift
V
OS
V
V
=
=
6V, V
6V, V
= 0V
= 0V
1.2
1.5
4
3
5
mV
mV
S
S
CM
CM
dV /dT
OS
µV/°C
µV/V
mV/V
µV/V
vs Power Supply
Over Temperature
Channel Separation, DC
PSRR
V
=
2V to 6V, V
= V−
30
100
S
CM
V
=
2V to 6V, V
= V−
150
S
CM
1
INPUT BIAS CURRENT
Input Bias Current
I
30
200
pA
pA
B
Over Temperature
Input Offset Current
See Typical Characteristics
I
10
50
OS
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz
Input Voltage Noise Density, f = 10kHz
Input Voltage Noise Density, f = 100kHz
Input Current Noise Density, f = 1kHz
e
n
V
V
V
V
=
=
=
=
6V, V
6V, V
6V, V
6V, V
= 0V
= 0V
= 0V
= 0V
10
10
6
µV
S
S
S
S
CM
CM
CM
CM
PP
e
n
nV/√Hz
nV/√Hz
fA/√Hz
e
n
i
2.5
n
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Over Temperature
V
(V−)
88
(V+) − 2
V
CM
CMRR
(V−) ≤ V
(V−) ≤ V
(V−) ≤ V
(V−) ≤ V
≤ (V+) − 2V
≤ (V+) − 2V
≤ (V+) − 3V
≤ (V+) − 3V
94
dB
dB
dB
dB
CM
CM
CM
CM
84
94
100
Over Temperature
84
INPUT IMPEDANCE
Differential
11
10 5
Ω pF
Ω pF
11
Common-Mode
10 4
OPEN-LOOP GAIN
Open-Loop Voltage Gain
OPA725, OPA726
Over Temperature
OPA2725, OPA2726
Over Temperature
OPA725, OPA726
Over Temperature
OPA2725, OPA2726
Over Temperature
A
OL
R = 100kΩ, 0.15V < V < (V+) − 0.15V
110
100
110
100
106
96
120
120
116
116
dB
dB
dB
dB
dB
dB
dB
dB
L
O
R = 100kΩ, 0.15V < V < (V+) − 0.15V
L
O
R = 100kΩ, 0.175V < V < (V+) − 0.175V
L
O
R = 100kΩ, 0.175V < V < (V+) − 0.175V
L
O
R = 1kΩ, 0.25V < V < (V+) − 0.25V
L
O
R
L
= 1kΩ, 0.25V < V < (V+) − 0.25V
O
R = 2kΩ, 0.25V < V < (V+) − 0.25V
106
96
L
O
R
L
= 2kΩ, 0.25V < V < (V+) − 0.25V
O
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
C = 20pF
L
GBW
SR
20
30
MHz
V/µs
ns
G = +1
Settling Time, 0.1%
0.01%
t
V
V
=
=
6V, 5V Step, G = +1
6V, 5V Step, G = +1
350
450
50
S
S
S
ns
Overload Recovery Time
Total Harmonic Distortion + Noise
V
• Gain > V
ns
IN
S
THD+N
V
=
6V, V
= 2V
, R = 600Ω,
0.0003
%
S
OUT
RMS
L
G = +1, f = 1kHz
4
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS: V = +4V to +12V or V = 2V to 6V (continued)
S
S
Boldface limits apply over the specified temperature range, T = −40°C to +125°C.
A
At T = +25°C, R = 10kΩ connected to V /2, and V
= V /2, unless otherwise noted.
A
L
S
OUT
S
OPA725, OPA726, OPA2725, OPA2726
PARAMETER
OUTPUT
CONDITIONS
UNIT
MIN
TYP
MAX
Voltage Output Swing from Rail
OPA725, OPA726
R = 100kΩ, A > 110dB
100
125
200
200
150
150
175
175
250
250
250
250
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
L
OL
Over Temperature
OPA2725, OPA2726
Over Temperature
OPA725, OPA726
R
L
= 100kΩ, A > 100dB
OL
R = 100kΩ, A > 110dB
L
OL
R
L
= 100kΩ, A > 100dB
OL
R = 1kΩ, A > 106dB
L
OL
Over Temperature
OPA2725, OPA2726
Over Temperature
Output Current
R
L
= 1kΩ, A > 96dB
OL
R = 2kΩ, A > 106dB
L
OL
R
L
= 2kΩ, A > 96dB
OL
I
V − V < 1V
OUT
40
55
OUT
S
Short-Circuit Current
Capacitive Load Drive
Open-Loop Output Impedance
I
SC
LOAD
C
See Typical Characteristics
40
f = 1MHz, I = 0
Ω
O
ENABLE/SHUTDOWN (OPAx726)
t
5
µs
µs
V
OFF
t
30
ON
Enable Reference (DGND) Voltage Range
V
DGND
V−
(V+) − 2
V (shutdown)
L
< V
+0.8V
V
DGND
V
(amplifier is active)
> V
+2V
DGND
V
H
Input Disable Current
(per amplifier)
Ref Pin = Enable Pin = V−
5
6
µA
µA
I
15
12
QSD
POWER SUPPLY
Specified Voltage Range
Operating Voltage Range
Quiescent Current (per amplifier)
Over Temperature
V
V
4
V
V
S
S
Q
3.5 to 13.2
4.3
I
I
= 0
5.5
mA
mA
O
6
TEMPERATURE RANGE
Specified Range
−40
−55
−55
125
125
150
°C
°C
°C
Operating Range
Storage Range
Thermal Resistance
SOT23-5
q
JA
200
150
°C/W
°C/W
MSOP-8, MSOP-10, SO-8
5
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
At T = +25°C, V
=
6V, R = 10kΩ connected to V /2, and V
= V /2, unless otherwise noted.
OUT S
A
S
L
S
COMMON−MODE REJECTION RATIO vs FREQUENCY
GAIN AND PHASE vs FREQUENCY
120
100
80
60
40
20
0
180
160
140
120
100
80
180
160
140
120
100
80
Phase
60
60
Gain
40
40
20
20
0
0
−
≤
≤
−
(V ) VCM (V+) 2V
−20
−20
100M
10
100
1k
10k
100k
1M
10M
10 100 1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
VS 6V
7
100
90
80
70
60
50
40
30
20
10
0
=
6
5
4
3
2
1
0
Indicates maximum output
for no visible distortion.
100k
10M
100
1k
10k
100k
1M
10M
100M
10k
1M
Frequency (Hz)
Frequency (Hz)
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
CHANNEL SEPARATION vs FREQUENCY
140
120
100
80
1000
100
10
60
40
20
1
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
6
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SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
At T = +25°C, V
=
6V, R = 10kΩ connected to V /2, and V = V /2, unless otherwise noted.
OUT S
A
S
L
S
−
INPUT BIAS CURRENT vs COMMON MODE VOLTAGE
OFFSET CURRENT vs TEMPERATURE
100k
10k
1k
10k
1k
_
+125 C
_
+85 C
100
10
100
10
_
+25 C
IB
< 10pA
−
10
_
+25 C
−
100
1
−
1k
_
+85 C
0.1
0.01
−
10k
_
+125 C
−
100k
−
−
25
50
0
25
50
75
100
125
150
_
Temperature ( C)
Common−Mode Voltage (V)
OPEN−LOOP GAIN vs TEMPERATURE
POWER−SUPPLY REJECTION RATIO vs TEMPERATURE
140
130
120
110
100
90
120
100
80
Ω
RL = 100k
Ω
RL = 1k
80
−
60
−
−
−
25
50
25
50
0
25
50
75
100
125
150
0
25
50
75
100
125
150
_
_
Temperature ( C)
Temperature ( C)
QUIESCENT CURRENT vs TEMPERATURE
COMMON−MODE REJECTION RATIO vs TEMPERATURE
5
110
100
90
4
3
2
1
0
80
70
−
≤
≤
−
(V ) VCM (V+) 2V
60
−
−
25
50
0
25
50
75
100
125
150
−
−
25
50
0
25
50
75
100
125
150
_
Temperature ( C)
_
Temperature ( C)
7
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www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
At T = +25°C, V
=
6V, R = 10kΩ connected to V /2, and V = V /2, unless otherwise noted.
OUT S
A
S
L
S
SHORT−CIRCUIT CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
90
80
70
60
50
40
30
20
10
0
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
Sourcing
Sinking
−
−
25
50
0
25
50
75
100
125
150
3
4
5
6
7
8
9
10 11 12 13 14
_
Temperature ( C)
Supply Voltage (V)
SHORT−CIRCUIT CURRENT vs SUPPLY VOLTAGE
Sourcing
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
90
80
70
60
50
40
30
20
10
0
6
4
2
0
−
_
40 C
Sinking
_
25 C
_
125 C
−
−
−
2
4
6
−
_
40 C
0
10
20
30
40
50
60
70
80
Output Current (mA)
Supply Voltage (V)
SETTLING TIME vs GAIN
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0.01
Ω
RL = 600
VOUT = 2Vrms
BW = 80kHz
0.001
0.01%
0.1%
0
0.0001
1
10
100
10
100
1k
10k
100k
Noninverting Gain (V/V)
Frequency (Hz)
8
ꢂ ꢀꢉꢠ ꢡ ꢢ ꢣ ꢂ ꢀꢉ ꢡꢠꢡ ꢢ
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www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
At T = +25°C, V
=
6V, R = 10kΩ connected to V /2, and V = V /2, unless otherwise noted.
OUT S
A
S
L
S
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
SMALL−SIGNAL OVERSHOOT vs CAPACITIVE LOAD
90
80
70
60
50
40
30
20
10
0
G = +1
−
G =
CF = 3pF
1
G = +5
CF = 1pF
10
100
Capacitive Load (pF)
1000
Offset Voltage (mV)
VOLTAGE OFFSET DRIFT PRODUCTION DISTRIBUTION
SMALL−SIGNAL STEP RESPONSE
G = +1
Typical production distribution
of packaged units.
Ω
RL = 10k
L = 20pF
C
0
2
4
6
8
10
12
14
16
100ns/div
µ
_
Voltage Offset Drift ( V/ C)
LARGE−SIGNAL STEP RESPONSE
SMALL−SIGNAL STEP RESPONSE
CF = 3pF
G = +1
RL = 10k
CF = 2pF
Ω
CL = 20pF
CF = 4pF
CF
G = −1
R
F
10k
Ω
10k
Ω
O PA725
CL
20pF
400ns/div
200ns/div
9
ꢂꢀꢉꢠ ꢡꢢ ꢣ ꢂꢀꢉ ꢡꢠꢡ ꢢ
ꢂꢀꢉ ꢠꢡ ꢤ ꢣ ꢂꢀꢉ ꢡꢠꢡ ꢤ
www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
At T = +25°C, V
=
6V, R = 10kΩ connected to V /2, and V = V /2, unless otherwise noted.
OUT S
A
S
L
S
LARGE−SIGNAL STEP RESPONSE
CF
4pF
−
G =
1
RF
Ω
10k
Ω
10k
OPA725
CL
20pF
400ns/div
10
ꢂ ꢀꢉꢠ ꢡ ꢢ ꢣ ꢂ ꢀꢉ ꢡꢠꢡ ꢢ
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www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
APPLICATIONS INFORMATION
a) Single−Supply Configuration
Enable
OPA725 and OPA726 series 20MHz CMOS op amps have
a fast slew rate, low noise, and excellent PSRR, CMRR,
and AOL. These op amps can operate on typically 4.3mA
quiescent current from a single (or split) supply in the range
of 4V to 12V ( 2V to 6V), making them highly versatile
and easy to use. They are stable in a unity-gain
configuration.
+12V
Digital
Logic
OPA726
VOUT
DGND
Power-supply pins should be bypassed with 1nF ceramic
capacitors in parallel with 1µF tantalum capacitors.
b) Dual−Supply Configuration
Enable
OPERATING VOLTAGE
OPA725 series op amps are specified from 4V to 12V
supplies over a temperature range of −40°C to +125°C.
They will operate well in 5V or +5V to +12V power-supply
systems. Parameters that vary significantly with operating
voltage or temperature are shown in the Typical
Characteristics.
+5V
Digital
Logic
OPA726
VOUT
−
5V
DGND
ENABLE/SHUTDOWN
OPA725 series op amps require approximately 4.3mA
quiescent current. The enable/shutdown feature of the
OPA726 allows the op amp to be shut off to reduce this
current to approximately 6µA.
Figure 1. Enable Reference Pin Connection for
Single- and Dual-Supply Configurations
The enable/shutdown input is referenced to the Enable
Reference Pin, DGND (see Pin Configurations). This pin
can be connected to logic ground in dual-supply op amp
configurations to avoid level-shifting the enable logic
signal, as shown in Figure 1.
INPUT OVER-VOLTAGE PROTECTION
Device inputs are protected by ESD diodes that will
conduct if the input voltages exceed the power supplies by
more than approximately 300mV. Momentary voltages
greater than 300mV beyond the power supply can be
tolerated if the current is limited to 10mA. This is easily
accomplished with an input resistor in series with the op
amp, as shown in Figure 2. The OPA725 series features
no phase inversion when the inputs extend beyond
supplies, if the input is current limited.
The Enable Reference Pin voltage, VDGND, must not
exceed (V+) − 2V. It may be set as low as V−. The amplifier
is enabled when the Enable Pin voltage is greater than
V
DGND + 2V. The amplifier is disabled (shutdown) if the
Enable Pin voltage is less than VDGND + 0.8V. The Enable
Pin is connected to internal pull-up circuitry and will enable
the device if left unconnected.
V+
COMMON-MODE VOLTAGE RANGE
IOVERLOAD
The input common-mode voltage range of the OPA725
and OPA726 series extends from V− to (V+) − 2V.
10mA max
VOUT
OPA725
R
VIN
Common-mode rejection is excellent throughout the input
voltage range from V− to (V+) − 3V. CMRR decreases
somewhat as the common-mode voltage extends to
(V+) − 2V, but remains very good and is tested throughout
this range. See the Electrical Characteristics table for
details.
−
V
Figure 2. Input Current Protection for Voltages
Exceeding the Supply Voltage
11
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www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
RAIL-TO-RAIL OUTPUT
+5V
OPA725
−5V
+5V
A class AB output stage with common-source transistors
is used to achieve rail-to-rail output. This output stage is
capable of driving heavy loads connected to any point
between V+ and V−. For light resistive loads ( > 100kΩ ),
the output voltage can swing to 150mV (175mV for dual)
from the supply rail, while still maintaining excellent
linearity (AOL > 110dB). With 1kΩ (2kΩ for dual) resistive
loads, the output is specified to swing to within 250mV from
the supply rails with excellent linearity (see the Typical
Characteristics curve Output Voltage Swing vs Output
Current).
75
Ω
AIN
VIN
2.5V
ADS8342
16−Bit ADC
330pF
Common
5V
−
Figure 4. OPA725 Driving an ADC
CAPACITIVE LOAD AND STABILITY
TRANSIMPEDANCE AMPLIFIER
Capacitive load drive is dependent upon gain and the
overshoot requirements of the application. Increasing the
gain enhances the ability of the amplifier to drive greater
capacitive loads (see the Typical Characteristics curve
Small-Signal Overshoot vs Capacitive Load).
Wide bandwidth, low input bias current, and low input
voltage and current noise make the OPA725 an ideal
wideband photodiode transimpedance amplifier. Low-
voltage noise is important because photodiode capaci-
tance causes the effective noise gain of the circuit to
increase at high frequency.
One method of improving capacitive load drive in the
unity-gain configuration is to insert a 10Ω to 20Ω resistor
inside the feedback loop, as shown in Figure 3. This
reduces ringing with large capacitive loads while
maintaining DC accuracy.
The key elements to a transimpedance design, as shown
in Figure 5, are the expected diode capacitance (CD),
which should include the parasitic input common-mode
and differential-mode input capacitance (4pF + 5pF for the
OPA725); the desired transimpedance gain (RF); and the
GBW for the OPA725 (20MHz). With these three variables
set, the feedback capacitor value (CF) can be set to control
the frequency response. CF includes the stray capacitance
of RF, which is 0.2pF for a typical surface-mount resistor.
V+
RS
Ω
20
OPA725
VOUT
VIN
CL
RL
(1)
CF
< 1pF
Figure 3. Series Resistor in Unity-Gain Buffer
Configuration Improves Capacitive Load Drive
RF
Ω
10M
DRIVING FAST 16-BIT ADCs
The OPA725 series is optimized for driving fast 16-bit
ADCs such as the ADS8342. The OPA725 op amps buffer
the converter input capacitance and resulting charge
injection, while providing signal gain. Figure 4 shows the
OPA725 in a single-ended method of interfacing to the
ADS8342 16-bit, 250kSPS, 4-channel ADC with an input
range of 2.5V. The OPA725 has demonstrated excellent
settling time to the 16-bit level within the 600ns acquisition
time of the ADS8342. The RC filter, shown in Figure 4, has
been carefully tuned for best noise and settling
performance. It may need to be adjusted for different op
amp configurations. Please refer to the ADS8342 data
sheet (available for download at www.ti.com) for additional
information on this product.
+5V
λ
VOUT
CD
OPA725
−
5V
NOTE: (1) CF is optional to prevent gain peaking.
It includes the stray capacitance of RF.
Figure 5. Dual-Supply Transimpedance Amplifier
12
ꢂ ꢀꢉꢠ ꢡ ꢢ ꢣ ꢂ ꢀꢉ ꢡꢠꢡ ꢢ
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www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
To achieve a maximally-flat, 2nd-order Butterworth
frequency response, the feedback pole should be set to:
For additional information, refer to Application Bulletin
SBOA055, Compensate Transimpedance Amplifiers
Intuitively, available for download at www.ti.com.
GBW
4pRFCD
1
+
Ǹ
2pRFCF
(1)
OPTIMIZING THE TRANSIMPEDANCE
CIRCUIT
Bandwidth is calculated by:
f*3dB
To achieve the best performance, components should be
selected according to the following guidelines:
GBW
2pRFCD
+
Hz
Ǹ
(2)
1. For lowest noise, select RF to create the total required
gain. Using a lower value for RF and adding gain after
the transimpedance amplifier generally produces
poorer noise performance. The noise produced by RF
increases with the square-root of RF, whereas the
signal increases linearly. Therefore, signal-to-noise
ratio is improved when all the required gain is placed
in the transimpedance stage.
For even higher transimpedance bandwidth, the
high-speed CMOS OPA354 (100MHz GBW), OPA300
(180 MHz GBW), OPA355 (200MHz GBW), or OPA656,
OPA657 (400MHz GBW) may be used.
For single-supply applications, the +IN input can be biased
with a positive dc voltage to allow the output to reach true
zero when the photodiode is not exposed to any light, and
respond without the added delay that results from coming
out of the negative rail. (Refer to Figure 6.) This bias
voltage also appears across the photodiode, providing a
reverse bias for faster operation.
2. Minimize photodiode capacitance and stray
capacitance at the summing junction (inverting input).
This capacitance causes the voltage noise of the op
amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to
reverse-bias a photodiode can significantly reduce its
capacitance. Smaller photodiodes have lower
capacitance. Use optics to concentrate light on a small
photodiode.
(1)
CF
< 1pF
RF
3. Noise increases with increased bandwidth. Limit the
circuit bandwidth to only that required. Use a capacitor
across the RF to limit bandwidth, even if not required
for stability.
Ω
10M
4. Circuit board leakage can degrade the performance of
an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that
encircles the summing junction and is driven at the
same voltage can help control leakage.
V+
λ
VOUT
OPA725
+VBias
For additional information, refer to the Application Bulletins
Noise Analysis of FET Transimpedance Amplifiers
(SBOA060), and Noise Analysis for High-Speed Op Amps
(SBOA066), available for download at the TI web site.
NOTE: (1) CF is optional to prevent gain peaking.
It includes the stray capacitance of RF.
Figure 6. Single-Supply Transimpedance
Amplifier
13
ꢂꢀꢉꢠ ꢡꢢ ꢣ ꢂꢀꢉ ꢡꢠꢡ ꢢ
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www.ti.com
SBOS278B − SEPTEMBER 2003 − REVISED JANUARY 2004
C3
2.2nF
C1
1nF
R3
2.07k
R4
22.3k
1/2
OPA2725
Ω
VOUT
Ω
R1
1.93k
R2
15.9k
1/2
OPA2725
Ω
Ω
C4
C2
100pF
330pF
DC Gain = 1
Cutoff Frequency = 50kHz
NOTE: FilterPro is a low-pass filter design program available for download at no cost from TI’s web site (www.ti.com). The program can be used
to determine component values for other cutoff frequencies or filter types.
Figure 7. Four-Pole Butterworth Sallen-Key Low-Pass Filter
14
PACKAGE OPTION ADDENDUM
www.ti.com
6-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2725AID
ACTIVE
SOIC
SOIC
D
D
8
8
75
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
OPA
2725A
Samples
Samples
OPA2725AIDG4
ACTIVE
75
NIPDAU
OPA
2725A
OPA2725AIDGKR
OPA2725AIDGKT
OPA2725AIDR
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500 RoHS & Green Call TI | NIPDAUAG
250 RoHS & Green Call TI | NIPDAUAG
2500 RoHS & Green NIPDAU
RoHS & Green Call TI | NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
BGM
Samples
Samples
Samples
BGM
OPA
2725A
OPA2726AIDGST
OPA2726AIDGSTG4
OPA725AID
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGS
DGS
D
10
10
8
250
250
75
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
BHB
Samples
Samples
Samples
RoHS & Green
RoHS & Green
Call TI
BHB
NIPDAU
OPA
725A
OPA725AIDBVR
OPA725AIDBVRG4
OPA725AIDBVT
OPA725AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
D
5
5
5
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OALI
OALI
OALI
Samples
Samples
Samples
Samples
250
RoHS & Green
2500 RoHS & Green
OPA
725A
OPA726AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
726A
Samples
OPA726AIDGKT
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
250
250
RoHS & Green Call TI | NIPDAUAG
RoHS & Green Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
BHC
Samples
Samples
OPA726AIDGKTG4
BHC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-May-2022
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2725AIDR
OPA725AIDBVR
OPA725AIDBVT
OPA725AIDR
SOIC
SOT-23
SOT-23
SOIC
D
8
5
5
8
2500
3000
250
330.0
178.0
178.0
330.0
12.4
9.0
6.4
3.3
3.3
6.4
5.2
3.2
3.2
5.2
2.1
1.4
1.4
2.1
8.0
4.0
4.0
8.0
12.0
8.0
Q1
Q3
Q3
Q1
DBV
DBV
D
9.0
8.0
2500
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2725AIDR
OPA725AIDBVR
OPA725AIDBVT
OPA725AIDR
SOIC
SOT-23
SOT-23
SOIC
D
8
5
5
8
2500
3000
250
356.0
180.0
180.0
356.0
356.0
180.0
180.0
356.0
35.0
18.0
18.0
35.0
DBV
DBV
D
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA2725AID
OPA2725AIDG4
OPA725AID
D
D
D
D
SOIC
SOIC
SOIC
SOIC
8
8
8
8
75
75
75
75
506.6
506.6
506.6
506.6
8
8
8
8
3940
3940
3940
3940
4.32
4.32
4.32
4.32
OPA726AID
Pack Materials-Page 3
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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Copyright © 2023, Texas Instruments Incorporated
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