OPA727AIDGKR [TI]
e-trim 20MHz, High Precision CMOS; 电子微调20MHz ，高精度CMOS
| 型号： | OPA727AIDGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | e-trim 20MHz, High Precision CMOS |
| 文件： | 总28页 (文件大小：1017K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA727, OPA2727
OPA4727, OPA728
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SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
e-trim™ 20MHz, High Precision CMOS
Operational Amplifier
FEATURES
DESCRIPTION
•
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•
•
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•
•
OFFSET: 15µV (typ), 150µV (max)
DRIFT: 0.3µV/°C (typ), 1.5µV/°C (max)
BANDWIDTH: 20MHz
The OPA727 and OPA728 series op amps use a
state-of-the-art 12V analog CMOS process and
e-trim, a package-level trim, offering outstanding dc
precision and ac performance. The extremely low
offset (150µV max) and drift (1.5µV/°C) are achieved
by trimming the IC digitally after packaging to avoid
the shift in parameters as a result of stresses during
package assembly. To correct for offset drift, the
OPA727 and OPA728 family is trimmed over
temperature. The devices feature very high CMRR
and open-loop gain to minimize errors.
SLEW RATE: 30V/µs
BIAS CURRENT: 500pA (max)
LOW NOISE: 6nV/√Hz at 100kHz
THD+N: 0.0003% at 1kHz
QUIESCENT CURRENT: 4.3mA/ch
SUPPLY VOLTAGE: 4V to 12V
SHUTDOWN MODE (OPA728): 6µA
Excellent ac characteristics, such as 20MHz GBW,
30V/µs slew rate and 0.0003% THD+N make the
OPA727 and OPA728 well-suited for communication,
high-end audio, and active filter applications. With a
bias current of less than 500pA, they are well suited
for use as transimpedance (I/V-conversion)
amplifiers for monitoring optical power in ONET
applications.
APPLICATIONS
•
•
•
•
•
•
•
•
•
OPTICAL NETWORKING
TRANSIMPEDANCE AMPLIFIERS
INTEGRATORS
ACTIVE FILTERS
A/D CONVERTER DRIVERS
I/V CONVERTER FOR DACs
HIGH PERFORMANCE AUDIO
PROCESS CONTROL
Optimized for single-supply operation up to 12V, the
input common-mode range extends to GND for true
single-supply functionality. The output swings to
within 150mV of the rails, maximizing dynamic range.
The low quiescent current of 4.3mA makes it
well-suited for use in battery-operated equipment.
The OPA728 shutdown version reduces the
quiescent current to typically 6µA and features a
reference pin for easy shutdown operation with
standard CMOS logic in dual-supply applications.
TEST EQUIPMENT
OPAx727 AND OPAx728 RELATED PRODUCTS
FEATURES
PRODUCT
20MHz, 3mV, 4µV/°C
OPA725
(non-e-trim version of OPA727)
For ease of use, the OPA727 and OPA728 op amp
families are fully specified and tested over the supply
range of 4V to 12V. The OPA727 (single) and
OPA728 (single with shutdown) are available in
MSOP-8 and DFN-8; the OPA2727 (dual) is
available in DFN-8 and SO-8; and the quad version
OPA4727 in TSSOP-14. All versions are specified for
operation from –40°C to +125°C.
20MHz, 3mV, 4µV/°C, Shutdown
(non-e-trim version of OPA728)
OPA726
+12V
OPA727
VOUT
l
-VB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
e-trim is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
Non-Shutdown
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
MSOP-8
DFN-8
DGK
DRB
DRB
D
AUE
NSF
OPA727
DFN-8
NSD
OPA2727
OPA4727
SO-8
O2727A
OPA4727
TSSOP-14
PW
Shutdown
MSOP-8
DFN-8
DGK
DRB
AUF
NSG
OPA728
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
OPA727, OPA2727
OPA4727, OPA728
UNIT
V
Supply Voltage
+13.2
Voltage(2)
Current(2)
–0.5 to (V+) + 0.5
±10
V
Signal Input Terminals
mA
Output Short-Circuit(3)
Operating Temperature
Storage Temperature
Junction Temperature
Continuous
–55 to +125
–55 to +150
+150
°C
°C
°C
V
Human Body Model
2000
ESD Rating
Charged Device Model
1000
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10mA or less.
(3) Short-circuit to ground, one amplifier per package.
2
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
PIN CONFIGURATIONS
OPA727
MSOP-8
(TOP VIEW)
OPA2727
SO-8
(TOP VIEW)
(1)
(1)
NC
V+
NC
1
2
3
4
8
7
6
5
V+
OUT A
1
2
3
4
8
7
6
5
A
-IN
+IN
V-
OUT B
-IN B
+IN B
-IN A
+IN A
V-
OUT
B
(1)
NC
OPA727
DFN-8
(TOP VIEW)
OPA2727
DFN-8
(TOP VIEW)
(1)
(1)
NC
NC
1
2
3
4
8
7
6
5
V+
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
Exposed
Thermal
Die Pad
Exposed
Thermal
Die Pad
V+
-IN
+IN
V-
OUT B
-IN B
+IN B
OUT
on
on
(2)
(2)
Underside
(1)
Underside
NC
OPA728
MSOP-8
(TOP VIEW)
OPA4727
TSSOP-14
(TOP VIEW)
(3)
Enable
REF
1
8
7
6
5
OUT A
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
D
V+
A
-IN
+IN
V-
2
3
4
-IN A
+IN A
V+
OUT
(1)
NC
+IN B
-IN B
OUT B
10 +IN C
OPA728
DFN-8
(TOP VIEW)
9
8
-IN C
B
C
OUT C
(3)
Enable
REF
1
2
3
4
8
7
6
5
Exposed
Thermal
Die Pad
on
Notes:
V+
-IN
+IN
V-
1. NC denotes no internal connection.
2. Connect thermal die pad to V–.
OUT
Underside(2)
(1)
NC
3. REF is the reference voltage for ENABLE pin.
3
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA727, OPA728,
OPA2727, OPA4727
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Input Offset Voltage
VOS
VS = ±5V, VCM = 0V
OPA727 DFN, OPA728 DFN Packages
15
15
15
15
0.3
0.6
30
150
300
150
175
1.5
3
µV
µV
OPA727 MSOP, OPA728 MSOP Packages
OPA2727
OPA4727
Drift
µV
µV
dVOS/dT
PSRR
0°C to +85°C
µV/°C
µV/°C
µV/V
µV/V
µV/V
–40°C to +125°C
vs Power Supply
VS = ±2V to ±6V, VCM = V–
VS = ±2V to ±6V, VCM = V–
150
150
Over Temperature
Channel Separation, dc
1
INPUT BIAS CURRENT
Input Bias Current
±85
±500
pA
pA
Over Temperature
See Typical Characteristics
Input Ofset Current
IOS
±10
±100
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz
Input Voltage Noise Density, f = 10kHz
Input Voltage Noise Density, f = 100kHz
Input Current Noise Density, f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Over Temperature
en
en
en
in
VS = ±6V, VCM = 0V
VS = ±6V, VCM = 0V
VS = ±6V, VCM = 0V
VS = ±6V, VCM = 0V
10
10
6
µVPP
nV/√Hz
nV/√Hz
fA/√Hz
2.5
VCM
(V–)
86
(V+)–2.5
V
CMRR
(V–) ≤ VCM ≤ (V+) – 2.5V
(V–) ≤ VCM ≤ (V+) – 2.5V
(V–) ≤ VCM ≤ (V+) – 3V
(V–) ≤ VCM ≤ (V+) – 3V
94
dB
dB
dB
dB
84
94
100
Over Temperature
INPUT IMPEDANCE
Differential
84
1011 || 5
1011 || 4
Ω || pF
Ω || pF
Common-Mode
OPEN-LOOP GAIN
RL = 100kΩ, 0.15V < VO < (V+)
Open-Loop Voltage Gain
AOL
110
120
116
dB
–0.15V
RL = 100kΩ, 0.15V < VO < (V+)
Over Temperature
100
dB
–0.15V
RL = 1kΩ, 0.25V < VO < (V+) –0.25V
RL = 1kΩ, 0.25V < VO < (V+) –0.25V
RL = 1kΩ, 0.35V < VO < (V+) –0.35V
CL = 20 pF
106
96
dB
dB
dB
Over Temperature, OPA727, OPA728
Over Temperature, OPA2727, OPA4727
FREQUENCY RESPONSE
Gain-Bandwidth Product
96
GBW
SR
ts
20
30
MHz
V/µs
ns
Slew Rate
G = +1
Settling Time, 0.1%
VS = ±6V, 5V Step, G = +1
VS = ±6V, 5V Step, G = +1
350
450
50
Settling Time,
0.01%
ns
Overload Recovery Time
VIN × Gain > VS
ns
Total Harmonic Distortion + Noise
THD+N VS = ±6V, VOUT = 2VRMS, RL = 600Ω,
0.003
%
G = +1, f = 1kHz
4
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
ELECTRICAL CHARACTERISTICS: VS = +4V to +12V or VS = ±2V to ±6V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
OPA727, OPA728,
OPA2727, OPA4727
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Voltage Output Swing from Rail
RL = 100kΩ, AOL > 110dB
RL = 100kΩ, AOL > 100dB
RL = 1kΩ, AOL > 106dB
RL = 1kΩ, AOL > 96dB
RL = 1kΩ, AOL > 96dB
|VS – VOUT| < 1V
100
200
150
150
250
250
350
mV
mV
mV
mV
mV
mA
mA
Over Temperature
Over Temperature, OPA727, OPA728
Over Temperature, OPA2727, OPA4727
Output Current
IOUT
ISC
40
Short-Circuit Current
±55
Capacitive Load Drive
Open-Loop Output Impedance
ENABLE/SHUTDOWN (OPA728)
tOFF
CLOAD
See Typical Characteristics
40
f = 1MHz, IO = 0
Ω
5
µs
µs
V
tON
80
Enable Reference (Ref Pin) Voltage Range
VL (amplifier is disabled)
VH (amplifier is enabled)
Input Bias Current of Enable Pin
IQSD
V–
(V+) –2
< VDGND+0.8V
V
> VDGND+2V
V
5
6
pA
µA
Amplifier Disabled
15
12
POWER SUPPLY
Specified Voltage Range
VS
VS
IQ
4
V
V
3.5 to
13.2
Operating Voltage Range
Quiescent Current (per amplifier)
Over Temperature
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
4.3
6.5
mA
6.5
mA
–40
–55
–55
+125
+125
+150
°C
°C
°C
Thermal Resistance
MSOP-8, SO-8
θJA
150
100
46
°C/W
°C/W
°C/W
TSSOP-14
DFN-8
5
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
GAIN AND PHASE vs FREQUENCY
COMMON-MODE REJECTION RATIO vs FREQUENCY
180
160
140
120
100
80
180
160
140
120
100
80
120
100
80
60
40
20
0
Phase
60
60
40
40
Gain
20
20
0
0
(V–) £ VCM £ (V+) – 2V
10 100 1k
–20
–20
100M
10
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 1.
Figure 2.
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
100
7
6
5
4
3
2
1
0
VS = ±6V
90
80
70
60
50
40
30
20
10
0
Indicates maximum output
for no visible distortion.
10k
100k
Frequency (Hz)
1M
10M
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 3.
Figure 4.
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
CHANNEL SEPARATION vs FREQUENCY
140
120
100
80
1000
100
10
60
40
20
1
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 5.
Figure 6.
6
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
INPUT BIAS CURRENT
vs COMMON-MODE VOLTAGE
OFFSET CURRENT vs TEMPERATURE
100k
10k
10k
1k
+125°C
+85°C
+25°C
1k
100
100
10
10
IB < ± 10pA
–10
+25°C
–100
–1k
1
0.1
0.01
+85°C
–10k
–100k
+125°C
–50
–25
0
25
50
75
100
125
150
–6
–4
–2
0
2
4
6
Temperature (°C)
Common--Mode Voltage (V)
Figure 7.
Figure 8.
OPEN-LOOP GAIN vs TEMPERATURE
POWER-SUPPLY REJECTION RATIO vs TEMPERATURE
140
130
120
110
100
90
120
RL = 100kW
100
80
RL = 1kW
80
60
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
Figure 9.
Figure 10.
COMMON-MODE REJECTION RATIO vs TEMPERATURE
QUIESCENT CURRENT vs TEMPERATURE
110
5
4
3
2
1
0
100
90
80
70
(V–) £ VCM £ (V+) – 2V
60
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
Figure 11.
Figure 12.
7
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
QUIESCENT CURRENT vs SUPPLY VOLTAGE
SHORT-CIRCUIT CURRENT vs TEMPERATURE
90
80
70
60
50
40
30
20
10
0
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
Sourcing
Sinking
–50
–25
0
25
50
75
100
125
150
3
4
5
6
7
8
9
10 11 12 13 14
Supply Voltage (V)
Temperature (°C)
Figure 13.
Figure 14.
SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
90
80
70
60
50
40
30
20
10
0
6
–40°C
Sourcing
4
2
25°C
Sinking
125°C
0
–2
–4
–6
–40°C
0
10
20
30
40
50
60
70
80
Output Current (mA)
Supply Voltage (V)
Figure 15.
Figure 16.
TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
SETTLING TIME vs GAIN
0.01
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
RL = 600W
VOUT = 2Vrms
BW = 80kHz
0.001
0.01%
0.1%
0.0001
0
10
100
1k
10k
100k
1
10
100
Frequency (Hz)
Noninverting Gain (V/V)
Figure 17.
Figure 18.
8
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
90
VS = ±5V
80
70
60
50
40
30
20
10
0
G = +1
G = –1
CF = 3pF
G = +5
CF = 1pF
10
100
1000
Capacitive Load (pF)
Offset Voltage (mV)
Figure 19.
Figure 20.
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
(0°C TO +85°C)
(–40°C TO +125°C)
VS = ±5V
VS = ±5V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Offset Voltage Drift (mV/°C)
Offset Voltage Drift (mV/°C)
Figure 21.
OFFSET VOLTAGE vs TEMPERATURE
VS = ±5V
Figure 22.
SMALL-SIGNAL STEP RESPONSE
300
200
100
0
G = +1
RL = 10kW
CL = 20pF
4s
–100
–200
–300
4s
7 Representative Units Shown
100ns/div
–50
–25
0
25
50
75
100
125
Temperature (°C)
Figure 23.
Figure 24.
9
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±6V, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
SMALL-SIGNAL STEP RESPONSE
CF = 2pF
G = +1
RL = 10kW
CF = 3pF
CL = 20pF
CF = 4pF
CF
G = –1
RF
10kW
10kW
O PA 7 27
CL
20pF
400ns/div
200ns/div
Figure 25.
Figure 26.
LARGE-SIGNAL STEP RESPONSE
CF
4pF
G = –1
RF
10kW
10kW
O PA 7 27
CL
20pF
400ns/div
Figure 27.
10
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OPA4727, OPA728
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SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
APPLICATIONS INFORMATION
Common-mode rejection is excellent throughout the
input voltage range from V– to (V+) – 3V. CMRR
decreases somewhat as the common-mode voltage
extends to (V+) – 2.5V, but remains very good and is
tested throughout this range. See the Electrical
Characteristics table for details.
The OPA727 and OPA728 family of op amps use
e-trim, an adjustment to offset voltage and
temperature drift made during the final steps of
manufacturing after the plastic molding is completed.
This compensates for performance shifts that can
occur during the molding process. Through e-trim,
the OPA727 and OPA728 deliver excellent offset
voltage (150µV max) and extremely low offset
voltage drift (1.5µV/°C). Additionally, these 20MHz
CMOS op amps have a fast slew rate, low noise, and
excellent PSRR, CMRR, and AOL. They can operate
on typically 4.3mA quiescent current from a single (or
split) supply in the range of 4V to 12V (±2V to ±6V),
making them highly versatile and easy to use. They
are stable in a unity-gain configuration.
a) Single-Supply Configuration
Enable
+12V
Digital
Logic
OPA728
REF
VOUT
VREF = DGND
Power-supply pins should be bypassed with 1nF
ceramic capacitors in parallel with 1µF tantalum
capacitors.
b) Dual-Supply Configuration
Enable
OPERATING VOLTAGE
+5V
Digital
Logic
OPA727 series op amps are specified from 4V to
12V supplies over a temperature range of –40°C to
+125°C. They will operate well in ±5V or +5V to
+12V power-supply systems. Parameters that vary
significantly with operating voltage or temperature
are shown in the Typical Characteristics.
OPA728
REF
VOUT
VREF = DGND
-5V
ENABLE/SHUTDOWN
Figure 28. Enable Reference Pin Connection for
Single- and Dual-Supply Configurations
OPA727 series op amps require approximately
4.3mA quiescent current. The enable/shutdown
feature of the OPA728 allows the op amp to be shut
off to reduce this current to approximately 6µA.
INPUT OVER-VOLTAGE PROTECTION
The enable/shutdown input is referenced to the
Enable Reference Pin, REF (see Pin Configurations).
This pin can be connected to logic ground in
dual-supply op amp configurations to avoid
level-shifting the enable logic signal, as shown in
Figure 28.
Device inputs are protected by ESD diodes that will
conduct if the input voltages exceed the power
supplies by more than approximately 300mV.
Momentary voltages greater than 300mV beyond the
power supply can be tolerated if the current is limited
to 10mA. This is easily accomplished with an input
resistor in series with the op amp, as shown in
Figure 29. The OPA727 series features no phase
inversion when the inputs extend beyond supplies, if
the input is current limited.
The Enable Reference Pin voltage, VREF, must not
exceed (V+) – 2V. It may be set as low as V–. The
amplifier is enabled when the Enable Pin voltage is
greater than VREF + 2V. The amplifier is disabled
(shutdown) if the Enable Pin voltage is less than
VREF + 0.8V. The Enable Pin is connected to internal
pull-up circuitry and will enable the device if left
unconnected.
V+
IOVERLOAD
10mA max
VOUT
OPA727
R
COMMON-MODE VOLTAGE RANGE
VIN
The input common-mode voltage range of the
OPA727 and OPA728 series extends from V– to
(V+) – 2.5V.
V-
Figure 29. Input Current Protection for Voltages
Exceeding the Supply Voltage
11
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
RAIL-TO-RAIL OUTPUT
+5V
OPA727
-5V
+5V
A
class AB output stage with common-source
75W
transistors is used to achieve rail-to-rail output. This
output stage is capable of driving heavy loads
connected to any point between V+ and V–. For light
resistive loads (>100kΩ), the output voltage can
swing to 150mV from the supply rail, while still
maintaining excellent linearity (AOL > 110dB). With
1kΩ resistive loads, the output is specified to swing
to within 250mV from the supply rails with excellent
linearity (see the Typical Characteristics curve,
Output Voltage Swing vs Output Current).
AIN
VIN
ADS8342
±2.5V
16-Bit ADC
330pF
Common
-5V
Figure 31. OPA727 Driving an ADC
TRANSIMPEDANCE AMPLIFIER
CAPACITIVE LOAD AND STABILITY
Wide bandwidth, low input bias current, and low
input voltage and current noise make the OPA727 an
ideal wideband photodiode transimpedance amplifier.
Low-voltage noise is important because photodiode
capacitance causes the effective noise gain of the
circuit to increase at high frequency.
Capacitive load drive is dependent upon gain and
the overshoot requirements of the application.
Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads (see the
Typical
Characteristics
curve,
Small-Signal
Overshoot vs Capacitive Load).
The key elements to a transimpedance design, as
shown in Figure 32, are the expected diode
capacitance (CD), which should include the parasitic
input common-mode and differential-mode input
capacitance (4pF + 5pF for the OPA727); the desired
transimpedance gain (RF); and the GBW for the
OPA727 (20MHz). With these three variables set, the
feedback capacitor value (CF) can be set to control
the frequency response. CF includes the stray
capacitance of RF, which is 0.2pF for a typical
surface-mount resistor.
One method of improving capacitive load drive in the
unity-gain configuration is to insert a 10Ω to 20Ω
resistor inside the feedback loop, as shown in
Figure 30. This reduces ringing with large capacitive
loads while maintaining DC accuracy.
V+
RS
20W
OPA727
VOUT
VIN
CL
RL
(1)
CF
< 1pF
Figure 30. Series Resistor in Unity-Gain Buffer
Configuration Improves Capacitive Load Drive
RF
10MW
DRIVING FAST 16-BIT ADCs
+5V
The OPA727 series is optimized for driving fast
16-bit ADCs such as the ADS8342. The OPA727 op
amps buffer the converter input capacitance and
resulting charge injection, while providing signal gain.
Figure 31 shows the OPA727 in a single-ended
method of interfacing to the ADS8342 16-bit,
250kSPS, 4-channel ADC with an input range of
±2.5V. The OPA727 has demonstrated excellent
settling time to the 16-bit level within the 600ns
acquisition time of the ADS8342. The RC filter,
shown in Figure 31, has been carefully tuned for best
noise and settling performance. It may need to be
adjusted for different op amp configurations. Refer to
the ADS8342 data sheet (available for download at
www.ti.com) for additional information on this
product.
l
VOUT
CD
OPA727
-5V
NOTE: (1) CF is optional to prevent gain peaking.
It includes the stray capacitance of RF.
Figure 32. Dual-Supply Transimpedance
Amplifier
12
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
To achieve a maximally-flat, 2nd-order Butterworth
frequency response, the feedback pole should be set
to:
For additional information, refer to Application
Bulletin (SBOA055), Compensate Transimpedance
Amplifiers Intuitively, available for download at
www.ti.com.
GBW
4pRFCD
1
+
Ǹ
2pRFCF
(1)
OPTIMIZING THE TRANSIMPEDANCE
CIRCUIT
Bandwidth is calculated by:
To achieve the best performance, components
should be selected according to the following
guidelines:
GBW
2pRFCD
f*3dB
+
Hz
Ǹ
(2)
1. For lowest noise, select RF to create the total
required gain. Using a lower value for RF and
adding gain after the transimpedance amplifier
generally produces poorer noise performance.
The noise produced by RF increases with the
square-root of RF, whereas the signal
increases linearly. Therefore, signal-to-noise
ratio is improved when all the required gain is
placed in the transimpedance stage.
For even higher transimpedance bandwidth, the
high-speed CMOS OPA380 (90MHz GBW), OPA354
(100MHz GBW), OPA300 (180MHz GBW), OPA355
(200MHz GBW), or OPA656, OPA657 (400MHz
GBW) may be used.
For single-supply applications, the +IN input can be
biased with a positive dc voltage to allow the output
to reach true zero when the photodiode is not
exposed to any light, and respond without the added
delay that results from coming out of the negative
rail; this is shown in Figure 33. This bias voltage also
appears across the photodiode, providing a reverse
bias for faster operation.
2. Minimize photodiode capacitance and stray
capacitance at the summing junction (inverting
input). This capacitance causes the voltage
noise of the op amp to be amplified
(increasing amplification at high frequency).
Using
a
low-noise voltage source to
(1)
reverse-bias a photodiode can significantly
reduce its capacitance. Smaller photodiodes
have lower capacitance. Use optics to
concentrate light on a small photodiode.
CF
< 1pF
3. Noise increases with increased bandwidth.
Limit the circuit bandwidth to only that
required. Use a capacitor across the RF to
limit bandwidth, even if not required for
stability.
RF
10MW
4. Circuit board leakage can degrade the
performance of an otherwise well-designed
amplifier. Clean the circuit board carefully. A
circuit board guard trace that encircles the
summing junction and is driven at the same
voltage can help control leakage.
V+
l
VOUT
OPA727
+VBias
For additional information, refer to the Application
Bulletins Noise Analysis of FET Transimpedance
Amplifiers (SBOA060), and Noise Analysis for
High-Speed Op Amps (SBOA066), available for
download at the TI web site.
NOTE: (1) CF is optional to prevent gain peaking.
It includes the stray capacitance of RF.
Figure 33. Single-Supply Transimpedance
Amplifier
13
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OPA727, OPA2727
OPA4727, OPA728
www.ti.com
SBOS314H–SEPTEMBER 2004–REVISED APRIL 2007
C3
2.2nF
C1
1nF
R3
R4
22.3kW
1/2
2.07kW
VO
R1
1.93kW
OPA2727
R2
15.9kW
1/2
OPA2727
C4
C2
330pF
100pF
DC Gain = 1
Cutoff Frequency = 50kHz
Note: FilterPro is a low-pass filter design program available for download at no cost from TI’s web site (www.ti.com). The
program can be used to determine component values for other cutoff frequencies or filter types.
Figure 34. Four-Pole Butterworth Sallen-Key Low-Pass Filter
DFN PACKAGE
LAYOUT GUIDELINES
The OPA727 series uses the DFN-8 (also known as
SON), which is a QFN package with lead contacts on
only two sides of the bottom of the package. This
leadless, near-chip-scale package maximizes board
space and enhances thermal and electrical
characteristics through an exposed pad.
The leadframe die pad should be soldered to a
thermal pad on the PCB. A mechanical data sheet
showing an example layout is attached at the end of
this data sheet. Refinements to this layout may be
required based on assembly process requirements.
Mechanical drawings located at the end of this data
sheet list the physical dimensions for the package
and pad. The five holes in the landing pattern are
optional, and are intended for use with thermal vias
that connect the leadframe die pad to the heatsink
area on the PCB.
DFN packages are physically small, have a smaller
routing area, improved thermal performance, and
improved electrical parasitics, with a pinout scheme
that is consistent with other commonly-used
packages, such as SO and MSOP. Additionally, the
absence of external leads eliminates bent-lead
issues.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests.
Even with applications that have low-power
dissipation, the exposed pad must be soldered to the
PCB to provide structural integrity and long-term
reliability.
The DFN package can be easily mounted using
standard printed circuit board (PCB) assembly
techniques. See Application Note, QFN/SON PCB
Attachment (SLUA271) and Application Report,
Quad Flatpack No-Lead Logic Packages (SCBA017),
both available for download at www.ti.com.
The exposed leadframe die pad on the bottom of
the package should be connected to V–.
14
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
OPA2727AID
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
O2727A
2727A
OPA2727AIDG4
OPA2727AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
75
Green (RoHS
& no Sb/Br)
O2727A
2727A
SOIC
D
8
2500
2500
2500
250
Green (RoHS
& no Sb/Br)
O2727A
2727A
OPA2727AIDRBR
OPA2727AIDRBRG4
OPA2727AIDRBT
OPA2727AIDRBTG4
OPA2727AIDRG4
OPA4727AIPW
SON
DRB
DRB
DRB
DRB
D
8
Green (RoHS
& no Sb/Br)
NSD
NSD
NSD
NSD
SON
8
Green (RoHS
& no Sb/Br)
SON
8
Green (RoHS
& no Sb/Br)
SON
8
250
Green (RoHS
& no Sb/Br)
SOIC
8
2500
90
Green (RoHS
& no Sb/Br)
O2727A
2727A
TSSOP
TSSOP
TSSOP
TSSOP
VSSOP
VSSOP
VSSOP
VSSOP
SON
PW
14
14
14
14
8
Green (RoHS
& no Sb/Br)
OPA4727
OPA4727
OPA4727
OPA4727
AUE
OPA4727AIPWG4
OPA4727AIPWR
OPA4727AIPWRG4
OPA727AIDGKR
OPA727AIDGKRG4
OPA727AIDGKT
OPA727AIDGKTG4
OPA727AIDRBT
PW
90
Green (RoHS
& no Sb/Br)
PW
2000
2000
2500
2500
250
Green (RoHS
& no Sb/Br)
PW
Green (RoHS
& no Sb/Br)
DGK
DGK
DGK
DGK
DRB
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU | Call TI Level-2-260C-1 YEAR
8
Green (RoHS
& no Sb/Br)
AUE
8
Green (RoHS
& no Sb/Br)
AUE
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
AUE
8
250
Green (RoHS
& no Sb/Br)
NSF
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OPA727AIDRBTG4
OPA728AIDGKT
ACTIVE
SON
VSSOP
VSSOP
SON
DRB
8
8
8
8
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
NSF
AUF
AUF
NSG
NSG
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGK
DGK
DRB
DRB
250
250
250
250
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA728AIDGKTG4
OPA728AIDRBT
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
OPA728AIDRBTG4
SON
Green (RoHS
& no Sb/Br)
CU NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2727AIDR
OPA2727AIDRBR
OPA2727AIDRBT
OPA4727AIPWR
OPA727AIDGKR
OPA727AIDGKT
OPA727AIDRBT
OPA728AIDGKT
OPA728AIDRBT
SOIC
SON
D
8
8
2500
2500
250
330.0
330.0
180.0
330.0
330.0
180.0
180.0
180.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.4
3.3
3.3
6.9
5.3
5.3
3.3
5.3
3.3
5.2
3.3
3.3
5.6
3.4
3.4
3.3
3.4
3.3
2.1
1.1
1.1
1.6
1.4
1.4
1.1
1.4
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q2
Q2
Q1
Q1
Q1
Q2
Q1
Q2
DRB
DRB
PW
SON
8
TSSOP
VSSOP
VSSOP
SON
14
8
2000
2500
250
DGK
DGK
DRB
DGK
DRB
8
8
250
VSSOP
SON
8
250
8
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2727AIDR
OPA2727AIDRBR
OPA2727AIDRBT
OPA4727AIPWR
OPA727AIDGKR
OPA727AIDGKT
OPA727AIDRBT
OPA728AIDGKT
OPA728AIDRBT
SOIC
SON
D
8
8
2500
2500
250
367.0
367.0
210.0
367.0
367.0
210.0
210.0
210.0
210.0
367.0
367.0
185.0
367.0
367.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
DRB
DRB
PW
SON
8
TSSOP
VSSOP
VSSOP
SON
14
8
2000
2500
250
DGK
DGK
DRB
DGK
DRB
8
8
250
VSSOP
SON
8
250
8
250
Pack Materials-Page 2
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e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
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