OPA810 [TI]
单通道、高性能、27V、140MHz、RRIO FET 输入运算放大器;
| 型号： | OPA810 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单通道、高性能、27V、140MHz、RRIO FET 输入运算放大器 放大器 运算放大器 |
| 文件： | 总52页 (文件大小：3437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA810
ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
OPA810 140MHz、轨到轨输入和输出、FET 输入运算放大器
1 特性
3 说明
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增益带宽积：70MHz
小信号带宽：140MHz
压摆率：200V/µs
宽电源电压范围：4.75V 至 27V
低噪声：
– 输入电压噪声：6.3nV/√Hz (f = 500kHz)
– 输入电流噪声：5fA/√Hz (f = 10kHz)
轨到轨输入和输出：
OPA810 是一款具有偏置电流（皮安 (pA) 范围内）的
单通道、场效应晶体管 (FET) 输入、电压反馈运算放
大器。OPA810 具有 140MHz 的小信号单位增益带宽
和单位增益稳定性，并且可在每通道 3.7mA 的低静态
电流 (I Q) 下提供出色的直流精度和动态交流性能。
OPA810 采用德州仪器 (TI) 专有的高速 SiGe BiCMOS
工艺制造，在类似的静态功耗级别下与同等的 FET 输
入放大器相比，性能得到显著提高。OPA810 具有
70MHz 的增益带宽积 (GBWP)、200V/µs 的压摆率和
6.3nV/√Hz 的低噪声电压，非常适合用于各种高保真
数据采集和信号处理应用。
•
– FET 输入级：2pA 输入偏置电流（典型值）
– 高线性输出电流：75mA
输入失调电压：±500µV（最大值）
温漂：±2.5µV/°C（典型值）
低功耗：3.7mA/通道
OPA810 具有轨到轨输入和输出，可提供 75mA 的线
性 输 出 电 流 ， 适 用 于 驱 动 光 电 组 件 和 模 数 转 换 器
(ADC) 输入或将数模转换器 (DAC) 输出缓冲至重负载
中。
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工作温度范围：
OPA810 的额定工业工作温度范围为 –40°C 至
+125°C。OPA2810 是该器件的双通道版本，可采用 8
引脚 SOIC、SOT-23 和 VSSOP 封装。
–40°C 至 +125°C
•
双通道版本：OPA2810
2 应用
器件信息
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宽带光电二极管跨阻放大器
器件型号(1)
封装尺寸（标称值）
4.90mm × 3.91mm
2.90mm × 1.60mm
2.00mm × 1.25mm
封装
模拟输入和输出模块
阻抗测量
SOIC (8)
OPA810
SOT-23 (5)
SC70 (5)
功率分析仪和仪表
高阻抗电压和电流测量
数据采集
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
多通道传感器接口
光电驱动器
CF
12V
RF
œ
1.8V
1.8V
OPA810
+
RG
12V
RS
VIN+
AVDD
DVDD
R
C
œ
-12V
CCB
ADS9110
18-bit
VOCM
THS4561
+
2 MSPS
12V
CCB
RG
VREF
œ
-0.2V
OPA810
+
VIN-
RF
R‘
R
C
R‘
-12V
5V
CF
5V
œ
12V
œ
OPA837
+
OPA378
+
REF5050
5.0 V
RFILT
Reference
CFILT
高阻抗输入数据采集前端
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS799
OPA810
www.ti.com.cn
ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
Table of Contents
8 Detailed Description......................................................22
8.1 Overview...................................................................22
8.2 Functional Block Diagram.........................................22
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................24
9 Application and Implementation..................................25
9.1 Application Information............................................. 25
9.2 Typical Applications.................................................. 30
10 Power Supply Recommendations..............................34
11 Layout...........................................................................34
11.1 Layout Guidelines................................................... 34
11.2 Layout Example...................................................... 36
12 Device and Documentation Support..........................37
12.1 Third-Party Products Disclaimer............................. 37
12.2 Documentation Support.......................................... 37
12.3 Receiving Notification of Documentation Updates..37
12.4 Support Resources................................................. 37
12.5 Trademarks.............................................................37
12.6 Electrostatic Discharge Caution..............................37
12.7 Glossary..................................................................38
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics: 10 V................................... 5
7.6 Electrical Characteristics: 24 V................................... 7
7.7 Electrical Characteristics: 5 V..................................... 9
7.8 Typical Characteristics: VS = 10 V.............................11
7.9 Typical Characteristics: VS = 24 V............................ 14
7.10 Typical Characteristics: VS = 5 V............................ 17
7.11 Typical Characteristics: ±2.375-V to ±12-V Split
Supply......................................................................... 19
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (June 2020) to Revision C (July 2020)
Page
•
将 DCK 封装的状态从预发布 更改为量产 .......................................................................................................... 1
Changes from Revision A (December 2019) to Revision B (June 2020)
Page
•
将 DBV 封装的状态从预发布 更改为量产 .......................................................................................................... 1
• Added noise corner information to 10 V, 24 V and 5 V electrical characteristics tables..................................... 5
• Changed offset voltage test conditions for 10 V, 24 V and 5 V supplies for SOIC, SOT23 and SC70 packages.
............................................................................................................................................................................5
• Updated Figure 62. Noninverting Amplifier ......................................................................................................25
Changes from Revision * (August 2019) to Revision A (December 2019)
Page
•
将文档状态从预告信息 更改为生产数据 .............................................................................................................1
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ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
5 Device Comparison Table
IQ
/
SLEW RATE VOLTAGE NOISE (nV/
GBWP
(MHz)
DEVICE
VS ± (V)
CHANNEL
(mA)
AMPLIFIER DESCRIPTION
(V/μs)
√ Hz)
OPA2810
OPA607
±12
3.6
0.9
70
50
192
6
Unity-gain stable FET input
Gain of 6, stable, low-cost CMOS
amplifier
±2.5
24
3.8
THS4631
OPA859
OPA818
±15
±2.625
±6.5
13
210
1800
2700
900
1150
1400
7
Unity-gain stable FET input
Unity-gain stable FET input
Gain of 7, stable FET input
20.5
27.7
3.3
2.2
6 Pin Configuration and Functions
NC
VINœ
VIN+
VSœ
1
2
3
4
8
7
6
5
NC
VS+
VO
NC
VO
VS+
1
2
3
5
4
VSœ
VIN+
VINœ
Not to scale
图 6-2. 5-Pin SOT23 (DBV) and SC70 (DCK)
图 6-1. 8-Pin SOIC (D) Package
Packages
Pin Functions
PIN
SOIC
TYPE(1)
DESCRIPTION
NAME
NC
SOT-23 and SC70
1
2
3
4
5
6
7
8
No internal connection
Inverting input pin
—
4
—
I
VIN–
VIN+
VS–
NC
3
I
Noninverting input pin
Negative power-supply pin
No internal connection
Output pin
2
P
—
1
—
O
P
VO
VS+
NC
5
Positive power-supply pin
No internal connection
—
—
(1) I = input, O = output, and P = power.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).(1)
MIN
MAX
±14
UNIT
V
VS
Supply voltage (total bipolar supplies)(4)
Input voltage
VIN
VIN,Diff
II
VS+ + 0.5
±7
V
VS– – 0.5
Differential input voltage(2)
Continuous input current
V
±10
mA
mA
mA
±40
TA = –40℃ to +85℃
TA = 125℃
IO
Continuous output current(3)
±15
PD
TJ
Continuous power dissipation
Junction temperature
See 节 7.4
150
125
°C
°C
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Equal to the lower of ±7 V or total supply voltage.
(3) Long-term continuous output current for electromigration limits.
(4) VS is the total supply voltage given by VS = VS+ – VS–
.
7.2 ESD Ratings
VALUE
±2500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
4.75
–40
NOM
MAX
UNIT
VS
TA
Total supply voltage
Ambient temperature
27
V
25
125
°C
7.4 Thermal Information
OPA810
DBV (SOT-23)
5 PINS
174.3
THERMAL METRIC(1)
D (SOIC)
8 PINS
134.8
75.2
DCK (SC70)
5 PINS
190.8
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
94.7
140.1
78.2
45.4
69.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
25.2
21.6
45.9
77.4
45.0
68.8
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics: 10 V
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, common-mode voltage (VCM) = mid-supply, RL =
1 kΩ connected to mid-supply(5)
.
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(3)
AC PERFORMANCE
135
140
C
C
G = 1, VO = 20 mVPP, RF = 0 Ω
G = 1, VO = 20 mVPP, RF = 0 Ω,
CL = 10 pF
SSBW Small-signal bandwidth
MHz
68
41
70
16
200
4
C
C
C
C
C
C
C
C
C
C
C
G = –1, VO = 20 mVPP
LSBW Large-signal bandwidth
GBWP Gain-bandwidth product
G = 2, VO = 2 VPP
MHz
MHz
MHz
V/µs
ns
Bandwdith for 0.1-dB flatness G = 2, VO = 20 mVPP
Slew rate (20%-80%)(4)
SR
G = 2, VO = –2-V to 2-V step
Rise time
Fall time
VO = 200-mV step
VO = 200-mV step
4
ns
G = 2, VO = 2-V step
G = 2, VO = 8-V step
G = 2, VO = 2-V step
G = 2, VO = 8-V step
47
65
330
230
Settling time to 0.1%
ns
ns
Settling time to 0.001%
G = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+
Input overdrive recovery
Output overdrive recovery
55
55
ns
ns
C
C
+ 0.5 V) input
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
input
C
C
C
C
C
C
f = 100 kHz, RL = 1 kΩ, VO = 2 VPP
f = 1 MHz, RL = 1 kΩ, VO = 2 VPP
f = 100 kHz, RL = 1 kΩ, VO = 2 VPP
f = 1 MHz, RL = 1 kΩ, VO = 2 VPP
Flatband, 1/f corner at 1.5 kHz
f = 10 kHz
–120
–101
–137
–101
6.3
Second-order harmonic
distortion
HD2
HD3
dBc
dBc
Third-order harmonic
distortion
en
in
Input-referred voltage noise
Input-referred current noise
nV/√ Hz
fA/√ Hz
5
Closed-loop output
impedance
zO
f = 100 kHz
0.007
C
Ω
DC PERFORMANCE
AOL
Open-loop voltage gain
f = DC, VO = ±2.5 V
SOIC package
108
120
100
100
2.5
2
dB
µV
A
A
500
715
VOS
Input offset voltage
DBV and DCK packages
TA = –40°C to +125°C
Input offset voltage drift
Input bias current
10 µV/°C
B
A
A
20
20
pA
pA
Input offset current
1
f = DC, VCM = –3 V to 1 V, SOIC
package
80
80
100
A
B
CMRR Common-mode rejection ratio
dB
TA = –40°C to +125°C, SOIC package
INPUT
Allowable input differential
voltage
±7
V
C
C
See 图 7-54
Common-mode input
impedance
In closed-loop configuration
12 || 2
GΩ||pF
Differential input capacitance In open-loop configuration
Most positive input voltage
0.5
pF
V
C
A
ΔVOS < 5 mV(1)
VS+ + 0.2
VS+ + 0.3
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Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, common-mode voltage (VCM) = mid-supply, RL =
1 kΩ connected to mid-supply(5)
.
TEST
PARAMETER
TEST CONDITIONS
ΔVOS < 5 mV(1)
MIN
VS– – 0.2 VS– – 0.3
S+ – 2.9 S+ – 2.5
TYP
MAX
UNIT
V
LEVEL(3)
Most negative input voltage
A
C
Most positive input voltage
for main-JFET stage
V
See 图 7-17
V
V
OUTPUT
VOCRH Output voltage range high
VOCRH Output voltage range high
V
V
A
B
RL = 667 Ω
VS+ – 0.18 VS+ – 0.11
TA = –40°C to +125°C, RL = 667 Ω
V
S+ – 0.2
VS–
0.15
+
VOCRL
VOCRL
IO(max)
Output voltage range low
Output voltage range low
VS– + 0.08
V
V
A
B
A
RL = 667 Ω
VS–
+
TA = –40°C to +125°C, RL = 667 Ω
VO = 2.65 V, RL = 51 Ω, ΔVOS < 1 mV
0.2
Linear output drive (sourcing
and sinking)
52
75
mA
ISC
CL
Output short-circuit current
Capacitive load drive
100
10
mA
pF
B
C
< 3-dB peaking, RS = 0 Ω
POWER SUPPLY
Quiescent current per
channel
IQ
3.7
4.6
mA
dB
A
ΔVS = ±2 V(2), SOIC package
79
79
100
A
B
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C, SOIC package
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product
27
20
MHz
C
C
Input-referred voltage noise
f = 1 MHz
nV/√ Hz
VCM = VS+ – 1.5 V, no load, SOIC
Package
Input offset voltage
Input bias current
1.6
20
mV
pA
A
A
2
VCM = VS+ – 1.5 V
(1) Change in input offset from its value when input is biased to midsupply.
(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
(3) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).
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7.6 Electrical Characteristics: 24 V
Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, common-mode voltage (VCM) = mid-supply, RL
= 1 kΩ connected to mid-supply(5)
.
Test
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Level(3)
AC PERFORMANCE
135
140
C
C
G = 1, Vo = 20 mVPP, RF = 0 Ω
G = 1, Vo = 20 mVPP, RF = 0 Ω,
CL= 10 pF
SSBW Small-signal bandwidth
MHz
MHz
68
44
C
C
C
C
C
C
C
C
C
C
C
C
C
C
G = –1, Vo = 20 mVPP
G = 2 Vo = 2 VPP
LSBW Large-signal bandwidth
GBWP Gain-bandwidth product
G = 2 Vo = 10 VPP
14
70
MHz
MHz
Bandwdith for 0.1-dB flatness G = 2, Vo = 20 mVPP
G = 2, Vo = –2-V to 2-V step
16
237
222
254
4
SR
Slew rate (20%-80%)(4)
V/µs
G = –1, Vo = –2-V to 2-V step
G = 2, Vo = –4.5-V to 3.5-V step
Vo = 200-mV step
Rise time
Fall time
ns
ns
Vo = 200-mV step
4
G = 2, Vo = 2-V step
47
Settling time to 0.1%
ns
ns
G = 2, Vo = 10-V step
G = 2, Vo = 2-V step
70
320
200
Settling time to 0.001%
G = 2, Vo = 10-V step
G = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+
Input overdrive recovery
Output overdrive recovery
35
45
ns
ns
C
C
+ 0.5 V) input
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
input
C
C
C
C
C
C
C
C
C
C
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
f = 100 kHz, RL =1 kΩ, Vo = 10 VPP
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
f = 1 MHz, RL=1 kΩ, Vo = 10 VPP
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
f = 100 kHz, RL =1 kΩ, Vo = 10 VPP
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
f = 1 MHz, RL =1 kΩ, Vo = 10 VPP
Flatband, 1/f corner at 1.5 kHz
f = 10 kHz
–118
–108
–112
–91
–136
–130
–104
–91
6.3
Second-order harmonic
distortion
HD2
HD3
dBc
dBc
Third-order harmonic
distortion
en
in
Input-referred voltage noise
Input-referred current noise
nV/√ Hz
fA/√ Hz
5
Closed-loop output
impedance
zO
f = 100 kHz
0.007
C
Ω
DC PERFORMANCE
AOL
Open-loop voltage gain
f = DC, Vo = ±8 V
108
120
100
100
2.5
2
dB
µV
A
A
SOIC package
500
550
VOS
Input offset voltage
DBV and DCK packages
TA = –40°C to +125°C
Input offset voltage drift
Input bias current
10 µV/°C
B
A
A
20
20
pA
pA
Input offset current
1
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Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, common-mode voltage (VCM) = mid-supply, RL
= 1 kΩ connected to mid-supply(5)
.
Test
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Level(3)
f = DC, VCM = ±5 V, SOIC package
90
90
105
A
B
CMRR Common-mode rejection ratio
dB
TA = –40°C to +125°C, SOIC package
INPUT
Allowable input differential
voltage
±7
V
C
C
see 图 7-54
Common-mode input
impedance
In closed-loop configuration
12 || 2.5
GΩ||pF
Differential input capacitance In open-loop configuration
0.5
pF
V
C
A
A
ΔVOS < 5 mV(1)
ΔVOS < 5 mV(1)
Most positive input voltage
Most negative input voltage
VS+ + 0.2
VS+ + 0.3
V
VS– – 0.2 VS– – 0.3
S+ – 2.9 S+ – 2.5
Most positive input voltage
for main-JFET stage
V
V
C
See 图 7-33
V
V
OUTPUT
A
B
RL = 667 Ω
V
V
S+ – 0.33 VS+ – 0.22
S+ – 0.36
VOCRH Output voltage range high
TA = –40°C to +125°C, RL = 667 Ω
VS–
0.23
+
VS– + 0.15
A
B
A
RL = 667 Ω
VOCRL
Output voltage range low
V
VS–
0.33
+
TA = –40°C to +125°C, RL = 667 Ω
Vo = 7.25 V, RL = 151 Ω, ΔVOS < 1 mV
Linear output drive (sourcing
and sinking)
IO(max)
48
64
mA
ISC
CL
Output short-circuit current
Capacitive load drive
108
10
mA
pF
B
C
< 3-dB peaking, RS = 0 Ω
POWER SUPPLY
Quiescent current per
channel
IQ
3.8
4.7
mA
dB
A
ΔVS = ±2 V(2), SOIC package
90
90
105
A
B
PSRR
Power supply rejection ratio
TA = –40°C to +125°C, SOIC package
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product
27
20
MHz
C
C
Input-referred voltage noise
f = 1 MHz
nV/√ Hz
VCM = VS+ – 1.5 V, no load, SOIC
Package
Input offset voltage
Input bias current
1.6
24
mV
pA
A
A
2
VCM = VS+ – 1.5 V
(1) Change in input offset from its value when input is biased to midsupply.
(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and -PSRR.
(3) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).
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ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
7.7 Electrical Characteristics: 5 V
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25 V, RL = 1 kΩ
connected to 1.25 V(5)
.
Test
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Level(1)
133
135
C
C
G = 1, Vo = 20 mVPP, RF = 0 Ω
G = 1, Vo = 20 mVPP, RF= 0 Ω,
CL= 10 pF
SSBW Small-signal bandwidth
MHz
65
36
C
C
C
C
C
G = –1, Vo = 20 mVPP
LSBW Large-signal bandwidth
GBWP Gain-bandwidth product
G = 2 Vo = 2 VPP
MHz
MHz
MHz
70
Bandwdith for 0.1-dB flatness G = 2, Vo = 20 mVPP
16
134
G = 2, Vo = –1-V to 1-V step
SR
Slew rate (20%-80%)(4)
V/µs
G = 2, Vo = –2-V to 2-V step,
VS = ±2.5 V
78
C
Rise time
Fall time
Vo = 200-mV step
Vo = 200-mV step
4
4
ns
ns
C
C
G = 2, Vo = –2-V to 0-V step,
VS = ±2.5 V
Settling time to 0.1%
100
565
76
ns
ns
ns
ns
C
C
C
C
G = 2, Vo = –2-V to 0-V step,
VS = ±2.5 V
Settling time to 0.001%
Input overdrive recovery
Output overdrive recovery
G = 1, (VS– – 0.5 V) to (VS+ + 0.5 V)
input, VS = ±2.5 V
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
input, VS = ±2.5 V
93
C
C
C
C
C
C
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP
Flatband, 1/f corner at 1.5 kHz
f = 10 kHz
–102
–81
–114
–92
6.3
Second-order harmonic
distortion
HD2
HD3
dBc
dBc
Third-order harmonic
distortion
en
in
Input-referred voltage noise
Input-referred current noise
nV/√ Hz
fA/√ Hz
5
Closed-loop output
impedance
zO
f = 100 kHz
0.007
C
Ω
DC PERFORMANCE
AOL
Open-loop voltage gain
f = DC, Vo = 1.25 V to 3.25 V
SOIC package
104
118
100
100
2.5
2
dB
µV
A
A
550
760
VOS
Input offset voltage
DBV and DCK packages
TA = –40°C to +125°C
Input offset voltage drift
Input bias current
10 µV/°C
B
A
A
20
20
pA
pA
Input offset current
1
f = DC, VCM = 0.75 V to 1.75 V, SOIC
package
73
73
92
A
B
CMRR Common-mode rejection ratio
dB
TA = –40°C to +125°C, SOIC package
INPUT
Allowable input differential
voltage
±5
V
C
C
See 图 7-54
Common-mode input
impedance
In closed-loop configuration
12 || 2.5
GΩ||pF
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ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25 V, RL = 1 kΩ
connected to 1.25 V(5)
.
Test
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Level(1)
Differential input capacitance In open-loop configuration
0.5
pF
V
C
A
A
ΔVOS < 5 mV(2)
ΔVOS < 5 mV(2)
Most positive input voltage
Most negative input voltage
VS+ + 0.2
VS+ + 0.3
V
VS- – 0.2
V
S- – 0.3
Most positive input voltage
for main-JFET stage
V
V
C
See 图 7-41
V
S+ – 2.9
VS+ – 2.5
OUTPUT
A
B
RL = 667 Ω
V
S+ – 0.12 VS+ – 0.09
VOCRH Output voltage range high
TA = –40°C to +125°C, RLOAD = 667 Ω VS+ – 0.15
RL = 667 Ω
VS–
0.11
+
VS–+ 0.06
A
B
A
VOCRL
Output voltage range low
V
VS–
0.15
+
TA = –40°C to +125°C, RL = 667 Ω
Linear output drive (sourcing VO = 1.4 V, RL = 27.5 Ω, ΔVOS < 1
and sinking)
IO(max)
50
64
mA
mV, VS+ = 3 V and VS– = –2 V
ISC
CL
Output short-circuit current
Capacitive load drive
96
10
mA
pF
B
C
< 3-dB peaking, RS = 0 Ω
POWER SUPPLY
Quiescent current per
channel
IQ
3.15
3.7
4.5
mA
dB
A
ΔVS = ±0.5 V(3), SOIC package
78
78
100
A
B
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C, SOIC package
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product
27
20
MHz
C
C
Input-referred voltage noise
f = 1 MHz
nV/√ Hz
VCM = VS+ – 1.5 V, no load, SOIC
Package
Input offset voltage
Input bias current
1.6
20
mV
pA
A
A
2
VCM = VS+ – 1.5 V
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) Change in input offset from its value when input is biased to 0 V.
(3) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and -PSRR.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, VS+ = 3.5 V, VS– = –1.5 V, G = 2 V/V, RF = 1 kΩ, CL = 4.7 pF, VCM = 0 V (unless otherwise noted).
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ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
7.8 Typical Characteristics: VS = 10 V
At VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC
specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted).
3
0
3
0
-3
-3
-6
-9
-6
-12
-15
-18
-21
-9
Gain = -1 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-12
-15
RL = 500 W
RL = 1 kW
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D041
D042
See 图 9-1 and 图 9-2, VO = 20 mVPP
See 图 9-1, VO = 20 mVPP, gain = 1 V/V, RF = 0 Ω
图 7-1. Small-Signal Frequency Response vs Gain
图 7-2. Small-Signal Frequency Response vs
Output Load
6
3
6
3
0
0
-3
-6
-9
-3
-6
-9
-12
-12
RS = 0 W, CL = 4.7 pF
RS = 0 W, CL = 10 pF
RS = 56 W, CL = 22 pF
RS = 40 W, CL = 33 pF
RS = 47 W, CL = 47 pF
RS = 0 W, CL = 4.7 pF
RS = 0 W, CL = 10 pF
RS = 0 W, CL = 22 pF
RS = 56 W, CL = 47 pF
-15
-18
-21
-15
-18
-21
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D044
D045
See 图 9-1 and 图 8-1,
See 图 9-1and 图 8-1, VO = 20 mVPP, gain = 2 V/V
VO = 20 mVPP, gain = 1 V/V, RF = 0 Ω
图 7-4. Small-Signal Frequency Response vs CL
图 7-3. Small-Signal Frequency Response vs CL
3
3
0
0
-3
-3
-6
-6
-9
-9
-12
-12
-15
-15
VO = 200 mVPP
VO = 1 VPP
VO = 200 mVPP
VO = 1 VPP
-18
-21
-18
-21
VO = 2 VPP
VO = 4 VPP
VO = 2 VPP
VO = 4 VPP
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D046
D047
See 图 9-1, gain = 1 V/V, RF = 0 Ω
See 图 9-1, gain = 2 V/V
图 7-5. Large-Signal Frequency Response vs
图 7-6. Large-Signal Frequency Response vs
Output Voltage
Output Voltage
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ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
1
-60
-70
Gain = -1 V/V
Gain = 1 V/V
HD2, RL = 1 kW
HD3, RL = 1 kW
HD2, RL = 500 W
HD3, RL = 500 W
0.8
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
0.6
-80
0.4
0.2
0
-90
-100
-110
-120
-130
-140
-150
-160
-0.2
-0.4
-0.6
-0.8
-1
100k
1M
10M
Frequency (Hz)
100M
1k
10k
100k
Frequency (Hz)
1M
D051
D048
See 图 9-1 and 图 9-2, VO = 20 mVPP
See 图 9-1, gain = 2 V/V
图 7-7. Small-Signal Response Flatness vs Gain
图 7-8. Harmonic Distortion vs Frequency
-60
-60
HD2, RL = 1 kW
HD2, Gain = 1
HD3, Gain = 1
HD2, Gain = 2
HD3, Gain = 2
-70
-70
HD3, RL = 1 kW
HD2, RL = 500 W
HD3, RL = 500 W
-80
-80
HD2, Gain = -1
HD3, Gain = -1
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
1k
10k
100k
Frequency (Hz)
1M
1k
10k
100k
Frequency (Hz)
1M
D049
D050
See 图 9-2, gain = –1 V/V
See 图 9-1 and 图 9-2, RF = 0 Ω
图 7-9. Harmonic Distortion vs Frequency
图 7-10. Harmonic Distortion vs Gain
0.15
45
Overshoot, VO = 2 VPP
Undershoot, VO = 2 VPP
Overshoot, VO = 200 mVPP
Undershoot, VO = 200 mVPP
40
35
30
25
20
15
10
5
0.1
0.05
0
-0.05
-0.1
0
Time (100 ns/div)
5
10
15
20
25
30
35
Load Capacitance (pF)
40
45
50
D052
D053
See 图 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF
See 图 9-1, gain = 1 V/V, RF = 0 Ω
图 7-11. Small-Signal Transient Response
图 7-12. Overshoot and Undershoot vs CL
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6
4
6
4
2
2
0
0
-2
-4
-2
-4
-6
VIN
VOUT
VIN x -1 Gain
VO
-6
0
200
400
600
Time (nsec)
800 1000 1200 1400 1600
0
200
400
600 800
Time (nsec)
1000 1200 1400
D054
D055
See 图 9-1, gain = 1 V/V, RF = 0 Ω
See 图 9-2, gain = –1 V/V
图 7-13. Input Overdrive Recovery
图 7-14. Output Overdrive Recovery
6
4
120
90
60
2
30
0
Sourcing
Sinking
Sourcing
Sinking
0
-30
-60
-90
-120
-150
-2
-4
-6
0
10
20
30
40
Output Current (mA)
50
60
70
80
90
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D056
D057
Output saturated and then short-circuited
图 7-15. Output Voltage vs Load Current
图 7-16. Output Short-Circuit Current vs Ambient
Temperature
1200
800
400
0
-400
-800
-1200
-6
-4
-2
0
2
Input Common-Mode Voltage (V)
4
6
D058
Measured for 12 units
图 7-17. Input Offset Voltage vs Input Common-Mode Voltage
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ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
7.9 Typical Characteristics: VS = 24 V
At VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC
specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted).
3
0
3
0
-3
-3
-6
-6
-9
-9
-12
-15
-18
-21
-12
-15
-18
-21
Gain = -1 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
VCM = 0 V
VCM = 9 V
VCM = 11 V
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D071
D072
See 图 9-1 and 图 9-2, VO = 20 mVPP
See 图 9-1, VO = 20 mVPP, gain = 1 V/V, CL = 4.7 pF, RF = 0 Ω
图 7-18. Noninverting Small-Signal Frequency
图 7-19. Small-Signal Frequency Response vs
Response vs Gain
Output Common-Mode Voltage
3
0
3
0
-3
-3
-6
-9
-6
-9
-12
-12
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
VO = 10 VPP
-15
-15
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
-18
-21
-18
-21
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D074
D075
See 图 9-1, gain = 1 V/V, RF = 0 Ω
See 图 9-1, gain = 2 V/V
图 7-20. Large-Signal Frequency Response vs
图 7-21. Large-Signal Frequency Response vs Vo
Output Voltage
-20
-40
HD2, VO = 2 VPP
HD3, VO = 2 VPP
HD2, VO = 10 VPP
HD3, VO = 10 VPP
HD2, VO = 20 VPP
HD3, VO = 20 VPP
HD2, VO = 2 VPP
HD3, VO = 2 VPP
HD2, VO = 10 VPP
HD3, VO = 10 VPP
HD2, VO = 20 VPP
HD3, VO = 20 VPP
-40
-60
-80
-60
-80
-100
-120
-140
-160
-100
-120
-140
-160
1k
10k
100k
Frequency (Hz)
1M
1k
10k
100k
Frequency (Hz)
1M
D076
D077
See 图 9-1, gain = 2 V/V
See 图 9-2, gain = –1 V/V
图 7-22. Harmonic Distortion vs Frequency vs Vo
图 7-23. Harmonic Distortion vs Frequency vs Vo
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0.15
6
4
0.1
0.05
0
2
0
-2
-4
-6
-0.05
-0.1
Time (100 ns/div)
Time (100 ns/div)
D078
D079
See 图 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF
See 图 9-1, gain = 1 V/V, RF = 0 Ω
图 7-24. Small-Signal Transient Response
图 7-25. Large-Signal Transient Response
12
6
VO = 2 VPP
VO = 10 VPP
VO = 20 VPP
VO = 4 VPP
VO = 10 VPP
8
4
4
2
0
0
-4
-8
-12
-2
-4
-6
Time (100 ns/div)
Time (50 ns/div)
D080
D081
See 图 9-1, gain = 2 V/V
See 图 9-2, gain = –1 V/V
图 7-26. Large-Signal Transient Response
图 7-27. Large-Signal Transient Response
25
15
12
9
20
6
15
3
Overshoot, VO = 2 VPP
Undershoot, VO = 2 VPP
Overshoot, VO = 200 mVPP
Undershoot, VO = 200 mVPP
0
10
5
-3
-6
-9
VIN
VOUT
-12
-15
0
5
10 15 20 25 30 35 40 45 50 55 60
Load Capacitance (pF)
0
200
400
Time (nsec)
600
800
D082
D083
See 图 9-1, gain = 1 V/V, RF = 0 Ω
See 图 9-1, gain = 1 V/V, RF = 0 Ω
图 7-28. Overshoot and Undershoot vs CL
图 7-29. Input Overdrive Recovery
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ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
15
12
9
14
10
6
6
3
2
Sourcing
Sinking
0
-2
-3
-6
-9
-12
-15
-6
-10
-14
VIN x -1 Gain
VO
0
200
400
600 800
Time (nsec)
1000 1200 1400
0
10
20
30
40
Output Current (mA)
50
60
70
80
90
D084
D085
See 图 9-2, gain = –1 V/V
图 7-31. Output Voltage Range vs Load Current
图 7-30. Output Overdrive Recovery
150
1500
120
90
1000
500
60
30
Sourcing
Sinking
0
0
-30
-60
-90
-120
-150
-180
-500
-1000
-1500
-40
-20
0
20
40
60
80
100 120 140
-12.5 -10 -7.5 -5 -2.5
0
Input Common-Mode Voltage (V)
2.5
5
7.5 10 12.5
Ambient Temperature (èC)
D086
D087
Output saturated and then short-circuited
Measured for 12 units
图 7-32. Output Short-Circuit Current vs Ambient
图 7-33. Input Offset Voltage vs Input Common-
Temperature
Mode Voltage
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ZHCSK40D – AUGUST 2019 – REVISED JULY 2020
7.10 Typical Characteristics: VS = 5 V
At VS+ = 5 V, VS– = 0 V, VCM= 1.25 V, RL = 1 kΩ, output is biased to midsupply, and TA ≈ 25°C. For AC
specifications, VS+ = 3.5 V, VS– = –1.5 V, VCM= 0 V, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless
otherwise noted).
3
0
0.15
0.1
-3
-6
0.05
0
-9
-12
-15
-18
-21
Gain = -1 V/V
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
-0.05
-0.1
100k
1M
10M
Frequency (Hz)
100M
Time (100 ns/div)
D010
D011
See 图 9-1 and 图 9-2, VO = 20 mVPP
See 图 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF
图 7-34. Small-Signal Response vs Gain
图 7-35. Small-Signal Transient Response
60
3
Overshoot, VO = 2 VPP
Undershoot, VO = 2 VPP
Overshoot, VO = 200 mVPP
Undershoot, VO = 200 mVPP
55
50
45
40
35
30
25
20
15
10
5
2
1
0
-1
-2
VIN
VOUT
0
-3
5
10
15
20
Load Capacitance (pF)
25
30
35
40
45
50
0
200
400
600 800
Time (nsec)
1000 1200 1400
D012
D014
See 图 9-1, gain = 1 V/V, RF = 0 Ω
See 图 9-1, gain = 1 V/V, RF = 0 Ω
图 7-36. Overshoot and Undershoot vs CL
图 7-37. Input Overdrive Recovery
3
3
2
2
1
1
Sourcing
Sinking
0
0
-1
-1
-2
-3
-2
VIN x -1 Gain
VO
-3
0
200
400
600 800
Time (nsec)
1000 1200 1400
0
10
20
30
40
Output Current (mA)
50
60
70
80
90
D013
D015
See 图 9-2, gain = –1 V/V
图 7-39. Output Voltage Range vs Output Current
图 7-38. Output Overdrive Recovery
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125
100
75
1000
500
50
25
0
0
-25
-50
-75
-100
-125
-500
-1000
-40
-20
0
20
40
60
80
100 120 140
-3
-2
-1
Input Common-Mode Voltage (V)
0
1
2
3
Ambient Temperature (èC)
D016
D017
Output saturated and then short-circuited
Measured for 12 units
图 7-40. Output Short-Circuit Current vs Ambient
图 7-41. Input Offset Voltage vs Input Common-
Temperature
Mode Voltage
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7.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply
At VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted).
130
110
90
180
160
140
120
100
80
3
0
Magnitude
Phase
-3
70
-6
50
-9
30
VS = 5 V
VS = 10 V
VS = 24 V
-12
-15
10
60
-10
40
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
100k
1M
10M
Frequency (Hz)
100M
D109
D101
Simulated with no output load
See 图 9-1, gain = 1 V/V, RF = 0 Ω
图 7-42. Open-Loop Gain and Phase vs Frequency
图 7-43. Large-Signal Response vs Supply Voltage
3
-60
HD2, VS = 5 V
HD3, VS = 5 V
HD2, VS = 10 V
HD3, VS = 10 V
HD2, VS = 24 V
HD3, VS = 24 V
-70
0
-3
-6
-9
-80
-90
-100
-110
-120
-130
-140
-150
-160
VS= 5 V
VS= 10 V
VS= 24 V
-12
-15
100k
1M
10M
Frequency (Hz)
100M
1k
10k
100k
Frequency (Hz)
1M
D102
D103
See 图 9-1, gain = 2 V/V
See 图 9-1, gain = 2 V/V
图 7-44. Large-Signal Response vs Supply Voltage
图 7-45. Harmonic Distortion vs Frequency vs
Supply Voltage
-60
100
10
1
HD2, VS = 5 V
HD3, VS = 5 V
HD2, VS = 10 V
HD3, VS = 10 V
HD2, VS = 24 V
HD3, VS = 24 V
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
1k
10k
100k
Frequency (Hz)
1M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D104
D103
Measured then fit to ideal 1/f model
See 图 9-2, gain = –1 V/V
图 7-47. Input Voltage Noise Density vs Frequency
图 7-46. Harmonic Distortion vs Frequency vs
Supply Voltage
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10000
1000
100
100
90
80
70
60
50
40
30
20
10
0
10
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
D106
D108
Measured then fit to ideal 1/f model
图 7-48. Auxiliary Input Stage Voltage Noise
图 7-49. Open-Loop Output Impedance vs
Density vs Frequency
Frequency
120
100
80
120
100
80
60
40
20
0
60
40
20
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
D110
D111
VS = 10 V and 24 V
VS = 5 V and 10 V
图 7-50. Common-Mode Rejection Ratio vs
图 7-51. Power Supply Rejection Ratio vs
Frequency
Frequency
120
20
16
12
8
PSRR VS+
PSRR VS-
100
80
60
40
20
0
4
0
-4
-8
-12
-16
-20
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
-12.5 -10 -7.5 -5 -2.5
0
Input Common-Mode Voltage (V)
2.5
5
7.5 10 12.5
D112
D118
Simulated curves, VS = 24 V
VS = ±12 V
图 7-52. Power Supply Rejection Ratio vs
图 7-53. Input Bias Current vs Input Common-Mode
Frequency
Voltage
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300
200
100
0
4.2
4
3.8
3.6
3.4
-100
-200
-300
TA = 25èC
TA = 125èC
-7.5 -6 -4.5 -3 -1.5
0
1.5
Differential Input Voltage (V)
3
4.5
6
7.5
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
D115
D117
Abs (VIN,Diff (max)) = VS when VS < 7 V
32 units, SOIC package, VS = ±5 V
图 7-54. Input Bias Current vs Differential Input
图 7-55. Quiescent Current vs Ambient
Voltage
Temperature
600
400
200
0
24000
22000
20000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
-200
-400
-600
-800
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
D120
D116
Quiescent Current (mA)
32 units, SOIC package
27000 units, µ = 3.82 mA, σ = 17 µA, VS = 24 V
图 7-56. Input Offset Voltage vs Ambient
图 7-57. Quiescent Current Distribution
Temperature
14000
12000
10000
8000
6000
4000
2000
0
14
12
10
8
6
4
2
0
Input Offset Voltage Drift (mV/èC)
D113
D114
Input Offset Voltage (mV)
–40°C to +125°C fit, 32 units, µ = –0.15 µV/°C, σ = 2.5
27000 units, µ = 16 µV, σ = 63 µV, VS = 24 V
µV/°C
图 7-58. Input Offset Voltage Distribution
图 7-59. Input Offset Voltage Drift Distribution
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8 Detailed Description
8.1 Overview
The OPA810 is a single-channel, field-effect transistor (FET)-input, unity-gain stable, voltage-feedback
operational amplifier with extremely low input bias current across its common-mode input voltage range. The
OPA810, characterized to operate over a wide supply range of 4.75 V to 27 V, has a small-signal, unity-gain
bandwidth of 140 MHz and offers both excellent DC precision and dynamic AC performance at low quiescent
power. The OPA810 is fabricated on Texas Instrument's proprietary, high-speed SiGe BiCMOS process and
achieves significant performance improvements over comparable FET-input amplifiers at similar levels of
quiescent power. With a gain-bandwidth product (GBWP) of 70 MHz, extremely high slew rate (200 V/µs), and
low noise (6.3 nV/√ Hz), the OPA810 is ideal in a wide range of data acquisition and signal processing
applications. The OPA810 includes input clamps to allow maximum input differential voltage of up to 7 V, making
the device suitable for use with multiplexers and for processing signals with fast transients. The device achieves
these benchmark levels of performance while consuming a typical quiescent current (IQ) of 3.7 mA per channel.
The OPA810 can source and sink large amounts of current without degradation in its linearity performance. The
wide bandwidth of the OPA810 implies that the device has low output impedance across a wide frequency
range, thereby allowing the amplifier to drive capacitive loads up to 10 pF without requiring output isolation. This
device is suitable for a wide range of data acquisition, test and measurement front-end buffer, impedance
measurement, power analyzer, wideband photodiode transimpedance, and signal processing applications.
8.2 Functional Block Diagram
VS+
OPA810
VIN+
Aux-Stage
+
œ
EN
CC
JFET-Stage
EN
VO
+
œ
œ
œ
+
VS+ œ2.5 V
VINœ
VSœ
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8.3 Feature Description
8.3.1 OPA810 Architecture
The OPA810 features a true high-impedance input stage including a JFET differential-input pair main stage and
a CMOS differential-input auxiliary (aux) stage operational within 2.5 V of the positive supply voltage. The bias
current is limited to a maximum of 20 pA throughout the common-mode input range of the amplifier. The 节 8.2
section provides a block diagram representation for the input stage of the OPA810. The amplifier exhibits
superior performance for high-speed signals (distortion, noise, and input offset voltage) while the aux stage
enables rail-to-rail inputs and prevents phase reversal. The device exhibits a CMRR and PSRR of 75 dB (typical)
when the input common-mode is in aux stage.
The OPA810 also includes input clamps that enable the maximum input differential voltage of up to 7 V (lower of
7 V and total supply voltage). This architecture offers significantly greater differential input voltage capability as
compared to one to two times the diode forward voltage drop maximum rating in standard amplifiers, and makes
this device suitable for use with multiplexers and processing of signals with fast transients. The input bias
currents are also clamped to maximum 300 µA, as 图 7-54 shows, which does not load the previous driver stage
or require current-limiting resistors (except limiting current through the input ESD diodes when input common-
mode voltages are greater than the supply voltages). This feature also enables this amplifier to be used as a
comparator in systems that require an amplifier and a comparator for signal gain and fault detection,
respectively. For the lowest offset, distortion, and noise performance, limit the common-mode input voltage to the
main JFET-input stage (greater than 2.5 V away from the positive supply).
The OPA810 is a rail-to-rail output amplifier and swings to either of the rails at the output, as shown in 图 7-15 for
10-V supply operation. This is particularly useful for inputs biased near the rails or when the amplifier is
configured in a closed-loop gain such that the output approaches the supply voltage. When the output saturates,
it recovers with 55 ns when inputs exceed the supply voltages by 0.5 V in an G = –1 V/V inverting gain with a
10–V supply. The outputs are short-circuit protected with the limits of 图 7-16.
As 图 8-1 shows, an amplifier phase margin reduces and becomes unstable when driving a capacitive load (CL)
at its output. Using a series resistor (RS) between the amplifier output and load capacitance introduces a zero
that cancels the pole formed by the amplifier output impedance and CL in the open-loop transfer function. The
OPA810 drives capacitive loads of up to 10 pF without causing instability. It is recommended to use a series
resistor for larger load capacitance values, as 图 7-3 shows for OPA810 configured as a unity-gain buffer. As 图
7-4 shows, when used in a gain larger than 1 V/V, the OPA810 is able to drive a load capacitance larger than 10
pF without the need for a series resistor at its output.
RS
VO
+
VIN
CL
RL
图 8-1. OPA810 Driving Capacitive Load
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8.3.2 ESD Protection
As 图 8-2 shows, all device pins are protected with internal ESD protection diodes to the power supplies. These
diodes provide moderate protection to input overdrive voltages above the supplies. The protection diodes can
typically support 10-mA continuous input and output currents. The differential input clamps only limit the bias
current when the input common-mode voltages are within the supply voltage range, whereas current-limiting
series resistors must be added at the inputs if common-mode voltages higher than the supply voltages are
possible. Keep these resistor values as low as possible because using high values degrades noise performance
and frequency response.
VS+
Power Supply
ESD Cell
VIN+
+
300 ꢀA
ICLAMP
œ
VO
VINœ
VSœ
图 8-2. Internal ESD Protection
8.4 Device Functional Modes
8.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
To facilitate testing with common lab equipment, the OPA810 can be configured to allow for split-supply
operation (see the OPA2810DGK Evaluation Module user guide). This configuration eases lab testing because
the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes,
spectrum analyzers, and other lab equipment reference the inputs and outputs to ground. 图 9-1 depicts the
OPA810 configured as a noninverting amplifier and 图 9-2 illustrates the OPA810 configured as an inverting
amplifier. For split-supply operation referenced to ground, the power supplies V S+ and V S- are symmetrical
around ground and V REF is at GND. Split-supply operation is preferred in systems where the signals swing
around ground because of the ease-of-use; however, the system requires two supply rails.
8.4.2 Single-Supply Operation (4.75 V to 27 V)
Many newer systems use a single power supply to improve efficiency and reduce the cost of the extra power
supply. The OPA810 can be used with a single supply (with the negative supply set to ground) with no change in
performance if the input and output are biased within the linear operation of the device. To change the circuit
from split supply to a balanced, single-supply configuration, level shift all voltages by half the difference between
the power-supply rails. An additional advantage of configuring an amplifier for single-supply operation is that the
effects of PSRR are minimized because the low-supply rail is grounded. See the Single-Supply Op Amp Design
Techniques application report for examples of single-supply designs.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Amplifier Gain Configurations
The OPA810 is a classic voltage-feedback amplifier with each channel having two high-impedance inputs and a
low-impedance output. Standard application circuits (as shown in 图 9-1 and 图 9-2) include the noninverting and
inverting gain configurations. The DC operating point for each configuration is level-shifted by the reference
voltage VREF that is typically set to midsupply in single-supply operation. VREF is often connected to ground in
split-supply applications.
VSIG
VS+
(1+RF/RG)VSIG
VREF
VIN
+
VREF
VO
VREF
-
RG
VSœ
RF
图 9-1. Noninverting Amplifier
VS+
œ(RF/RG)VSIG
VREF
+
VSIG
VO
VREF
VREF
VIN
œ
RG
VSœ
RF
图 9-2. Inverting Amplifier
Equation 1 shows the closed-loop gain of an amplifier in a noninverting configuration.
≈
’
÷
RF
VO = V 1+
+ V
∆
IN
REF
RG ◊
«
(1)
(2)
Equation 2 shows the closed-loop gain of an amplifier in an inverting configuration.
≈
∆
«
’
÷
RF
VO = V
-
+ V
IN
REF
RG ◊
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9.1.2 Selection of Feedback Resistors
The OPA810 is a classic voltage feedback amplifier with each channel having two high-impedance inputs and a
low-impedance output. Standard application circuits (as shown in 图 9-3 and 图 9-4) include the noninverting and
inverting gain configurations. The DC operating point for each configuration is level-shifted by the reference
voltage VREF which is typically set to midsupply in single-supply operation. VREF is often connected to ground in
split-supply applications.
VSIG
VS+
(1+RF/RG)VSIG
VREF
VREF
VIN
+
VO
œ
RG
VS-
RF
VREF
图 9-3. Noninverting Amplifier
VS+
-(RF/RG)VSIG
VREF
VREF
+
VSIG
VO
VREF
VIN
œ
RG
VS-
RF
图 9-4. Inverting Amplifier
Equation 3 shows the closed-loop gain of an amplifier in noninverting configuration.
≈
’
÷
RF
VO = V 1+
+ V
∆
IN
REF
RG ◊
«
(3)
(4)
Equation 4 shows the closed-loop gain of an amplifier in an inverting configuration.
≈
∆
«
’
÷
RF
VO = V
-
+ V
IN
REF
RG ◊
The magnitude of the low-frequency gain is determined by the ratio of the magnitudes of the feedback resistor
(RF) and the gain setting resistor RG. The order of magnitudes of the individual values of RF and RG offer a
trade-off between amplifier stability, power dissipated in the feedback resistor network, and total output noise.
The feedback network increases the loading on the amplifier output. Using large values of the feedback resistors
reduces the power dissipated at the amplifier output. On the other hand, this increases the inherent voltage and
amplifier current noise contribution seen at the output while lowering the frequency at which a pole occurs in the
feedback factor (β). This pole causes a decrease in the phase margin at zero-gain crossover frequency and
potential instability. Using small feedback resistors increases power dissipation and also degrades amplifier
linearity due to a heavier amplifier output load. 图 9-5 illustrates a representative schematic of the OPA810 in an
inverting configuration with the input capacitors shown.
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VS+
CCM
-(RF/RG)VSIG
+
VSIG
CDIFF
VO
VREF
VIN
œ
VREF
RG
CPCB
CCM
VS-
RF
图 9-5. Inverting Amplifier with Input Capacitors
The effective capacitance at the amplifier inverting input pin is shown in Equation 5, which forms a pole in β at a
cut-off frequency of Equation 6.
CIN = CCM + CDIFF + CPCB
(5)
where
• CCM is the amplifier common-mode input capacitance
• CDIFF is the amplifier differential input capacitance
• CPCB is the PCB parasitic capacitance
1
FC =
2pRFCIN
(6)
For low-power systems, greater the values of the feedback resistors, the earlier in frequency does the phase
margin begin to reduce and cause instability. 图 9-6 and 图 9-7 illustrate the loop gain magnitude and phase
plots, respectively, for the OPA810 simulation in TINA-TI configured as an inverting amplifier with values of
feedback resistors varying by orders of magnitudes.
120
110
100
90
100
90
80
70
60
50
40
30
20
10
0
RF = 200 W, RG = 50 W
RF = 10 kW, RG = 2.5 kW
RF = 1 MW, RG = 250 kW
80
70
60
50
40
30
20
10
RF = 200 W, RG = 50 W
RF = 10 kW, RG = 2.5 kW
RF = 1 MW, RG = 250 kW
0
-10
-20
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D802
D801
图 9-7. Loop-Gain Phase vs Frequency for Circuit
of 图 9-5
图 9-6. Loop-Gain vs Frequency for Circuit of 图 9-5
A lower phase margin results in peaking in the frequency response and lower bandwidth as 图 9-8 shows, which
is synonymous with overshoot and ringing in the pulse response results. The OPA810 offers a flat-band voltage
noise density of 6.3 nV/√ Hz. TI recommends selecting an RF so the voltage noise contribution does not exceed
that of the amplifier. 图 9-9 shows the voltage noise density variation with value of resistance at 25°C. A 2-kΩ
resistor exhibits a thermal noise density of 5.75 nV/√ Hz which is comparable to the flatband noise of the
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OPA810. Hence, TI recommends using an R F lower than 2 kΩ while being large enough to not dissipate
excessive power for the output voltage swing and supply current requirements of the application. The 节 9.1.3
section shows a detailed analysis of the various contributors to noise.
30
20
10
0
1000
100
10
RF = 200 W, RG = 50 W
RF = 10 kW, RG = 2.5 kW
RF = 1 MW, RG = 250 kW
1
0.1
-10
10
100
1k
10k
Resistance (W)
100k
1M
10M
10k
100k
1M
Frequency (Hz)
10M
100M
D803
D806
图 9-9. Thermal Noise Density vs Resistance
图 9-8. Closed-Loop Gain vs. Frequency for Circuit
of 图 9-5
9.1.3 Noise Analysis and the Effect of Resistor Elements on Total Noise
The OPA810 provides a low input-referred broadband noise voltage density of 6.3 nV/√ Hz while requiring a low
3.7-mA quiescent supply current. To take full advantage of this low input noise, careful attention to the other
possible noise contributors is required. 图 9-10 shows the operational amplifier noise analysis model with all the
noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in
nV/√ Hz or pA/√ Hz.
ENI
+
EO
RS
IBN
œ
ERS
4kTR S
RF
4kT
R G
4kTRF
IBI
RG
4kT = 1.6E - 20J
at 290è K
图 9-10. Operational Amplifier Noise Analysis Model
The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation adds all the contributing noise powers at the output by superposition,
then calculates the square root to get back to a spot noise voltage. 图 9-10 shows the general form for this
output noise voltage using the terms shown in Equation 7.
2
2
)
2
EO
=
ENI + IBNRS + 4kTRS NG2 + I R
+ 4kTR NG
F
(
(BI F )
)
(
(7)
Dividing this expression by the noise gain (NG = 1 + RF / RG) shows the equivalent input referred spot noise
voltage at the noninverting input; see Equation 8.
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ö2
÷
ø
I R
4kTRF
NG
æ
ç
è
2
2
BI
F
EN
=
ENI + IBNRS + 4kTRS +
+
(
)
NG
(8)
Substituting large resistor values into Equation 8 can quickly dominate the total equivalent input referred noise. A
source impedance on the noninverting input of 2-kΩ adds a Johnson voltage noise term similar to that of the
amplifier (6.3 nV/√ Hz).
表 9-1 compares the noise contributions from the various terms when the OPA810 is configured in a noninverting
gain of 5 V/V as 图 9-11 shows. Two cases are considered where the resistor values in case 2 are 10x the
resistor values in case 1. The total output noise in case 1 is 34 nV/√ Hz while the noise in case 2 is 51.5 nV/√
Hz. The large value resistors in case 2 dilute the benefits of selecting a low noise amplifier like the OPA810. To
minimize total system noise, reduce the size of the resistor values. This increases the amplifiers output load and
results in a degradation of distortion performance. The increased loading increases the dynamic power
consumption of the amplifier. The circuit designer must make the appropriate tradeoffs to maximize the overall
performance of the amplifier to match the system requirements.
VS+ = 5V
+
EO
œ
Case1: 200 ꢀ
Case2: 2 kꢀ
RS
VS- = -5V
RG
RF
Case1: 1 kꢀ
Case2: 10 kꢀ
Case1: 250 ꢀ
Case2: 2.5 kꢀ
图 9-11. Comparing Noise Contributors for Two Cases with the Amplifier in a Noninverting Gain of 5 V/V
表 9-1. Comparing Noise Contributions for the Circuit in 图 9-11
CASE 1
CASE 2
OUTPUT
NOISE
EQUATION
VOLTAGE
NOISE
CONTRIBUTIO
VOLTAGE
NOISE
CONTRIBUTIO
NOISE
NOISE
NOISE
SOURCE
NOISE
SOURCE
VALUE
NOISE
SOURCE
VALUE
POWER
CONTRIBUTIO
N (nV2/Hz)
CONTRIBUTIO
N (%)
POWER
CONTRIBUTIO
N (nV2/Hz)
CONTRIBUTIO
N (%)
N (nV/√ Hz)
N (nV/√ Hz)
Source resistor,
RS
ERS (1 +
RF /RG)
1.82 nV/√
5.76 nV/√
9.1
82.81
66.59
16.57
7.15
5.75
1.43
28.8
25.76
12.87
829.44
663.58
165.64
31.29
25.03
6.25
Hz
Hz
2.04 nV/√
6.44 nV/√
Gain resistor, RG ERG (RF / RG)
8.16
4.07
Hz
Hz
12.87 nV/
√ Hz
Feedback
ERF
4.07 nV/√
resistor, RF
Hz
Amplifier
voltage noise,
ENI
ENI (1 + RF
RG)
/
6.3 nV/√
6.3 nV/√
31.5
992.25
85.67
31.5
992.25
37.43
Hz
Hz
Inverting
current noise, IBI
IBI (RF || RG)
5.0E-3
1.0E-3
50E-3
10E-3
5 fA/√ Hz
5 fA/√ Hz
5 fA/√ Hz
5 fA/√ Hz
—
—
—
—
—
—
—
—
Noninverting
current noise, IBN
IBNRS (1 +
RF/ RG)
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9.2 Typical Applications
9.2.1 Transimpedance Amplifier
The high GBWP and low input voltage and current noise for the OPA810 make the device an ideal wideband
transimpedance amplifier for moderate to high transimpedance gains.
Supply Decoupling not
shown
VBIAS
+5 V
OPA810
+
Oscilloscope
with 50-ꢀ Inputs
-
CD
20 pF
CPCB
0.3 pF
-5 V
RF
100 kꢀ
CF + CPCB
1.03 pF
图 9-12. Wideband, High-Sensitivity, Transimpedance Amplifier
9.2.1.1 Design Requirements
表 9-2 lists the design requirements for a high-bandwidth, high-gain transimpedance amplifier circuit.
表 9-2. Design Requirements
PARAMETER
Target bandwidth
DESIGN REQUIREMENT
> 2 MHz
100 kΩ
20 pF
Transimpedance gain
Photodiode capacitance
9.2.1.2 Detailed Design Procedure
Designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit
from the low input voltage noise of the OPA810. This input voltage noise is peaked up over frequency by the
diode source capacitance, and can (in many cases) become the limiting factor to input sensitivity. The key
elements to the design are the expected diode capacitance (CD) with the reverse bias voltage (VBIAS) applied,
the desired transimpedance gain, R , and the GBWP for the OPA810 (70 MHz). 图 9-12 shows a
F
transimpedance circuit with the parameters as described in 表 9-2. With these three variables set (and including
the parasitic input capacitance for the OPA810 and the printed circuit board (PCB) added to CD), the feedback
capacitor value (CF) can be set to control the frequency response. The Transimpedance Considerations for High-
Speed Amplifiers application report discusses using high-speed amplifiers for transimpedance applications. Set
the feedback pole according to Equation 9 in order to achieve a maximally-flat second-order Butterworth
frequency response:
1
GBWP
RFCD
=
2p
RFCF
4
p
(9)
The input capacitance of the amplifier is the sum of the common-mode and differential capacitance (2.0 +
0.5) pF. The parasitic capacitance from the photodiode package and the PCB is approximately 0.3 pF. Using
Equation 5 gives a total input capacitance of CD = 22.8 pF. From Equation 9, set the feedback pole at 1.55 MHz.
Setting the pole at 1.55 MHz requires a total feedback capacitance of 1.03 pF.
Equation 10 shows the approximate –3-dB bandwidth of the transimpedance amplifier circuit:
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f-3dB = GBWP / (2
p
RFCD )Hz
(10)
Equation 10 estimates a closed-loop bandwidth of 2.19 MHz. 图 9-13 and 图 9-14 show the loop-gain magnitude
and phase plots from the TINA-TI simulations of the transimpedance amplifier circuit of 图 9-12. The 1/β gain
curve has a zero from RF and CIN at 70 kHz and a pole from RF and CF cancelling the 1/β zero at 1.5 MHz,
resulting in a 20-dB per decade rate-of-closure at the loop-gain crossover frequency (the frequency where AOL
equals 1/β), ensuring a stable circuit. A phase margin of 62° is obtained with a closed-loop bandwidth of 3 MHz
and a 100-kΩ transimpedance gain.
9.2.1.3 Application Curves
120
110
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
AOL
1/b
AOL
b
AOL
1/b
AOLb
-10
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D804
D805
图 9-13. Loop-Gain Magnitude vs Frequency for the
Transimpedance Amplifier Circuit of 图 9-12
图 9-14. Loop-Gain Phase vs Frequency for the
Transimpedance Amplifier Circuit of 图 9-12
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9.2.2 High-Z Input Data Acquisition Front-End
An ideal data acquisition system must measure a parameter without altering the measurand. When measuring a
voltage or current from sensors with a large output impedance, an extremely high input impedance front-end with
a pA range bias current is needed. 图 9-15 shows an example circuit with the OPA810 used at the front-end. For
systems with large input voltage attenuated with the MΩ range resistor divider, the OPA810 with its pA range
bias currents adds negligible offset voltage and distortion because of the bias current induced resistor voltage
drops. This circuit shows a funneling architecture with the OPA810 FET-input amplifier used as a unity-gain
buffer, followed by attenuation to the ADS9110 5-V, full-scale input range and the ADC input drive using the
THS4561 fully-differential amplifier (FDA). The THS4561 helps achieve better SNR and ENOB than a similar 5-V
FDA, with a higher 12.6-V supply voltage and signal swings up to the ADC full-scale input range.
As a result of the capacitive switching and current inrush on the ADC VREF input pin, a wide bandwidth amplifier
such as the OPA837 is used with the OPA378 in a composite loop as a reference buffer. The OPA378, driven
from the REF5050 5-V voltage reference, offers high precision and the OPA837 gives fast-settling performance
for the ADC reference input drive. See the Reference Design Maximizing Signal Dynamic Range for True 10 Vpp
Differential Input to 20 bit ADC design guide for more a detailed analysis of this high-Z front-end.
CF
12V
RF
œ
1.8V
1.8V
OPA810
+
RG
12V
RS
VIN+
AVDD
DVDD
R
C
œ
-12V
CCB
ADS9110
18-bit
VOCM
THS4561
+
2 MSPS
12V
CCB
RG
VREF
œ
-0.2V
OPA810
+
VIN-
RF
R‘
R
C
R‘
-12V
5V
CF
5V
œ
12V
œ
OPA837
+
OPA378
+
REF5050
5.0 V
RFILT
Reference
CFILT
图 9-15. High-Z Input Data Acquisition Front-End
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9.2.3 Multichannel Sensor Interface
High-Z input amplifiers are particularly useful when interfaced with sensors that have relatively high output
impedance. Such multichannel systems usually interface these sensors with the signal chain through a
multiplexer. 图 9-16 shows one such implementation using an amplifier for the interface with each sensor, and
driving into an ADC through a multiplexer. An alternate circuit, shown in 图 9-17, can use a single higher GBWP
and fast-settling amplifier at the output of the multiplexer. This architecture gives rise to large signal transients
when switching between channels, where the settling performance of the amplifier and maximum allowed
differential input voltage limits signal chain performance and amplifier reliability, respectively.
+
+
MUX
ADC
+
图 9-16. Multichannel Sensor Interface Using Multiple Amplifiers
OPA810
-
ADC
+
MUX
图 9-17. Multichannel Sensor Interface Using a Single Higher GBWP Amplifier
图 9-18 shows the output voltage and input differential voltage when a 8-V step is applied at the noninverting
terminal of the OPA810 configured as a unity-gain buffer of 图 9-17.
7.5
5
2.5
0
-2.5
VIN
VO
VIN,Diff
-5
Time (10 ns/div)
BD_M
图 9-18. Large-Signal Transient Response Using the OPA810
Because of the fast input transient, the amplifier is slew-limited and the inputs cease to track each other (a
maximum VIN,Diff of 7 V is shown in 图 9-18) until the output reaches its final value and the negative feedback
loop is closed. For standard amplifiers with a 0.7-V to 1.5-V maximum VIN,Diff rating, current-limiting resistors
must be used in series with the input pins to protect the device from irreversible damage, which also limits the
device frequency response. The OPA810 has built-in input clamps that allow the application of as much as 7 V of
VIN,Diff, with no external resistors required and no damage to the device or a shift in performance specifications.
Such an input-stage architecture, coupled with its fast settling performance, makes the OPA810 a good fit for
multichannel sensor multiplexed systems.
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10 Power Supply Recommendations
The OPA810 is intended for operation on supplies ranging from 4.75 V to 27 V. The OPA810 can be operated on
single-sided supplies, split and balanced bipolar supplies, or unbalanced bipolar supplies. Operating from a
single supply can have numerous advantages. With the negative supply at ground, the DC errors resulting from
the –PSRR term can be minimized. Typically, AC performance improves slightly at 10-V operation with minimal
increase in supply current. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency, 0.01-
µF decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-frequency, 0.01-µF,
supply-decoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has
these capacitors. When a split supply is used, use these capacitors from each supply to ground. If necessary,
place the larger capacitors further from the device and share these capacitors among several devices in the
same area of the printed circuit board (PCB). An optional supply decoupling capacitor across the two power
supplies (for split-supply operation) reduces second harmonic distortion.
11 Layout
11.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the OPA810 requires careful attention
to board layout parasitics and external component types. The OPA2810EVM can be used as a reference when
designing the circuit board. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any AC ground for all signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability—on the noninverting input, this capacitance can react with the
source impedance to cause unintentional band-limiting. To reduce unwanted capacitance, open a window
around the signal I/O pins in all ground and power planes around those pins. Otherwise, ground and power
planes must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency, 0.01-µF decoupling
capacitors. At the device pins, do not allow the ground and power plane layout to be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the
supply pins. These capacitors can be placed somewhat farther from the device and shared among several
devices in the same area of the PC board.
3. Careful selection and placement of external components preserve the high-frequency performance of
the OPA810. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-
frequency performance. Again, keep their leads and PCB trace length as short as possible. Never use
wirewound type resistors in a high-frequency application. Because the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as
close as possible to the output pin. Other network components, such as noninverting input termination
resistors, must also be placed close to the package. Even with a low parasitic capacitance shunting the
external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values greater than 10 kΩ, this parasitic capacitance can add a pole or zero close to the
GBWP of 70 MHz and subsequently affects circuit operation. Keep resistor values as low as possible and
consistent with load driving considerations. Lowering the resistor values keeps the resistor noise terms low,
and minimizes the effect of parasitic capacitance, however lower resistor values increase the dynamic power
consumption because RF and RG become part of the amplifiers output load network. Transimpedance
applications (see the 节 9.2.1 section) can use whatever feedback resistor is required by the application as
long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the
inverting node.
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4. Connections to other wideband devices on the board can be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground and
power planes opened up around them. Estimate the total capacitive load and set RS for sufficient phase
margin and stability. Low parasitic capacitive loads (< 10 pF) may not need an RS because the OPA810 is
nominally compensated to operate with a 10-pF parasitic load. Higher parasitic capacitive loads without an
RS are allowed with increase in signal gain (increasing the unloaded phase margin). If a long trace is
required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement
a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary
onboard, and a higher impedance environment improves distortion. With a characteristic board trace
impedance defined based on board material and trace dimensions, a matching series resistor into the trace
from the output of the OPA810 is used as well as a terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and
the input impedance of the destination device—this total effective impedance must be set to match the trace
impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the
series resistor value to obtain sufficient phase margin and stability. This does not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of the destination device is low, the signal attenuates
because of the voltage divider formed by the series output into the terminating impedance.
5. Take care to design the PCB layout for optimal thermal dissipation. For the extreme case of 125°C
operating ambient, using the approximate 134.8°C/W for the SOIC package, and an internal power of 24-V
supply × 4.7-mA 125°C supply current gives a maximum internal power dissipation of 113 mW. This power
gives a 15°C increase from ambient to junction temperature. Load power adds to this value and this
dissipation must also be calculated to determine the worst-case safe operating point.
6. Socketing a high-speed device such as the OPA810 is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network
that can almost make achieving a smooth, stable frequency response impossible. Best results are obtained
by soldering the OPA810 onto the board.
11.1.1 Thermal Considerations
The OPA810 does not require heat sinking or airflow in most applications. Maximum allowed junction
temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction
temperature to exceed 150°C.
Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the
sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is the specified no-load supply current times the total supply voltage across the part. P DL
depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to half of either supply voltage (for equal split-supplies). Under this
condition PDL = VS 2 / (4 × RL) where RL includes feedback network loading.
The power in the output stage and not into the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using a DCK (SC70 package) configured as a unity gain
buffer, operating on ±12-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω load.
PD = 24 V × 4.7 mA + 122 /(4 × 500 Ω) = 184.8 mW
Maximum T J = 25°C + (0.185 W × 190.8°C/W) = 60°C, which is well below the maximum allowed junction
temperature of 150oC.
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11.2 Layout Example
VS+
Representative schematic of a
single channel
CBYP
RS
+
œ
CBYP
VS-
RF
RG
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
1
8
7
CBYP
RG
Place bypass capacitors
close to power pins
Place input resistor close to pin 2 to
minimize parasitic capacitance
2
Place output resistors close to
output pin to minimize
parasitic capacitance
RS
Place feedback resistor on the
bottom of PCB between pins 2 and 6
3
6
5
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
Place bypass capacitors
close to power pins
4
CBYP
图 11-1. Layout Recommendation
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12 Device and Documentation Support
12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA2810 Dual-Channel, 27-V, Rail-to-Rail Input/Output FET-Input Operational Amplifier
data sheet.
• Texas Instruments, ADS9110 18-Bit, 2-MSPS, 15-mW, SAR ADC With Enhanced Performance Features data
sheet
• Texas Instruments, THS4561 Low-Power, High Supply Range, 70-MHz, Fully Differential Amplifier data sheet
• Texas Instruments, OPAx837 Low-Power, Precision, 105-MHz, Voltage-Feedback Op Amp data sheet
• Texas Instruments, OPAx378 Low-Noise, 900kHz, RRIO, Precision Operational Amplifier Zerø-Drift Series
data sheet
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, OPA2810DGK Evaluation Module user's guide
• Texas Instruments, Single-Supply Op Amp Design Techniques application report
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
• Texas Instruments, Blog: What you need to know about transimpedance amplifiers – part 1
• Texas Instruments, Blog: What you need to know about transimpedance amplifiers – part 2
• Texas Instruments, Noise Analysis for High-Speed Op Amps application report
• Texas Instruments, TINA model and simulation tool
• Texas Instruments, TIDA-01057 Reference Design Maximizing Signal Dynamic Range for True 10 Vpp
Differential Input to 20 bit ADC
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA810IDBVR
OPA810IDBVT
OPA810IDCKR
OPA810IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SC70
DBV
DBV
DCK
D
5
5
5
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1ZQ5
1ZQ5
1GG
810
NIPDAU
NIPDAU
NIPDAU
NIPDAU
3000 RoHS & Green
2500 RoHS & Green
SOIC
OPA810IDT
SOIC
D
250
RoHS & Green
810
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA810IDBVR
OPA810IDBVT
OPA810IDCKR
OPA810IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
D
5
5
5
8
8
3000
250
178.0
178.0
180.0
330.0
180.0
9.0
9.0
3.3
3.3
3.2
3.2
2.3
5.2
5.2
1.4
1.4
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q1
Q1
3000
2500
250
8.4
2.47
6.4
1.25
2.1
8.0
SOIC
12.4
12.4
12.0
12.0
OPA810IDT
SOIC
D
6.4
2.1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA810IDBVR
OPA810IDBVT
OPA810IDCKR
OPA810IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
D
5
5
5
8
8
3000
250
190.0
190.0
213.0
356.0
210.0
190.0
190.0
191.0
356.0
185.0
30.0
30.0
35.0
35.0
35.0
3000
2500
250
SOIC
OPA810IDT
SOIC
D
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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