OPA817 [TI]

800MHz、高精度、单位增益稳定、FET 输入运算放大器;


型号：	OPA817
厂家：	TEXAS INSTRUMENTS
描述：	800MHz、高精度、单位增益稳定、FET 输入运算放大器放大器运算放大器
文件：	总29页 (文件大小：2664K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

OPA817

ZHCSOI9A –JULY 2022 –REVISED DECEMBER 2022

OPA817 800MHz、高精度、单位增益稳定、FET 输入运算放大器

1 特性

3 说明

• 高带宽：

OPA817 是一款单位增益稳定的电压反馈运算放大器、

适用于高速、高精度和宽动态范围的应用。

– 增益带宽积：400MHz

– 带宽(G = 1V/V)：800MHz

– 大信号带宽(2V_PP)：250MHz

– 压摆率：1000V/µs

OPA817 具有一个低噪声结型栅场效应管 (JFET) 输入

级，该输入级具有 400MHz 的宽增益带宽和 6V 至

12.6V 的电源电压范围。当在高速数字转换器、有源探

头及其他测试和测量应用中用作高阻抗缓冲器时，

1000V/µs 的快速压摆率可实现大信号宽带宽和低失

真。

• 高精度：

– 输入失调电压：250μV（最大值）

– 输入失调电压温漂：3.5μV/°C（最大值）

• 输入电压噪声：4.5nV/√Hz

• 输入偏置电流：2pA

• 低失真（R_L= 100Ω，V_O= 2V_PP）：

– 10MHz 时的HD2、HD3：–86dBc、–100dBc

• 电源电压范围：6V 至12.6V

• 电源电流：23.5mA

OPA817 提供 ±250μV 的超低输入失调电压和

±3.5μV/°C 的失调电压温漂。皮安级输入偏置电流和

低输入电压噪声 (4.5nV/√Hz) 相结合，使得 OPA817

十分适合在光学测试和通信设备以及医疗和科学仪器中

用作宽带跨阻放大器。

OPA817 采用带有裸露散热垫的 8 引脚 WSON 封装。

此器件可在 –40°C 至 +105°C 的工业温度范围内正常

运行。

• 关断电流：55µA

• 性能提升至OPA656

2 应用

封装信息⁽¹⁾⁽²⁾

• 高速数据采集(DAQ)

• 有源探头

• 示波器

封装尺寸（标称值）

器件型号

OPA817

封装

DTK（WSON，8） 3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

(2) 请参阅器件比较表。

• 宽带跨阻放大器(TIA)

• 晶圆扫描设备

• 光学通信模块

• 光时域反射法(OTDR)

• 测试和测量前端

• 医学和化学分析器

R_F1

+5 V

ADS4149

ADC

–

THS4541

R_G1

OPA817

Input

V_CM

–

ꢀ5 V

R_G2

V_REF

R_F2

高输入阻抗数字转换器前端

大信号频率响应

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBOS847

OPA817

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ZHCSOI9A –JULY 2022 –REVISED DECEMBER 2022

Table of Contents

9 Application and Implementation..................................17

9.1 Application Information............................................. 17

9.2 Typical Applications.................................................. 18

10 Power Supply Recommendations..............................19

11 Layout...........................................................................19

11.1 Layout Guidelines................................................... 19

11.2 Layout Example...................................................... 21

12 Device and Documentation Support..........................22

12.1 Device Support....................................................... 22

12.2 Documentation Support.......................................... 22

12.3 接收文档更新通知................................................... 22

12.4 支持资源..................................................................22

12.5 Trademarks.............................................................22

12.6 Electrostatic Discharge Caution..............................22

12.7 术语表..................................................................... 22

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions.........................4

7.4 Thermal Information....................................................4

7.5 Electrical Characteristics: V_S= ±5 V...........................5

7.6 Typical Characteristics: V_S= ±5 V.............................. 8

8 Detailed Description......................................................14

8.1 Overview...................................................................14

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................14

Information.................................................................... 22

4 Revision History

Changes from Revision * (July 2022) to Revision A (December 2022)

Page

• 将数据表的状态从预告信息更改为“量产数据”.............................................................................................. 1

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5 Device Comparison Table

VOLTAGE NOISE (nV/√

MINIMUM STABLE

GAIN (V/V)

DEVICE

OPA817

OPA818

OPA657

OPA656

OPA659

OPA858

THS4631

Supply Voltage (V) BW (MHz)

Input

FET

SLEW RATE (V/μs)

Hz)

±6.3

±6.5

±5

400

2700

1600

230

1000

1400

700

4.5

2.2

4.8

FET

±5

FET

290

±6

350

FET

2550

2000

1000

8.9

2.5

±2.5

±15

5500

210

CMOS

FET

6 Pin Configuration and Functions

VS+

OUT

IN+

Not to scale

NC - no internal connection

图6-1. DTK Package, 8-Pin WSON With Thermal Pad (Top View)

表6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Feedback resistor connection (optional)

Inverting input

IN–

IN+

Noninverting input

No connect (no internal connection to die)

Output of amplifier

—

OUT

Power down (low = amplifier enabled, high = amplifier disabled); internal 2-MΩpull-up allows floating

this pin

Negative power supply

Positive power supply

VS–

VS+

Electrically isolated from the die substrate. The thermal pad can be connected to any potential

between the device power-supplies, but it is recommended to connect it to a heat-spreading plane,

typically ground.

Thermal pad

—

(1) I = input, O = output, P = power

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_S

Total supply voltage (V_S+– V_S–

)

Maximum dV_S/dT for supply turn-on and turn-off⁽²⁾

V/µs

V_I

V_ID

I_I

Input voltage

V_S–

V_S+

±V_S

±10

±30

Differential input voltage

Continuous input current

I_O

Continuous output current⁽³⁾

Continuous power dissipation

Maximum junction temperature

Operating free-air temperature

Storage temperature

See Thermal Information

150

T_J

°C

T_A

105

125

–40

–65

T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) Staying below this specification ensures that the edge-triggered ESD absorption devices across the supply pins remain off

(3) Long-term continuous current for electromigration limits.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

Electrostatic

discharge

V_(ESD)

Charged-device model (CDM), per ANSI/ESDA/JEDEC

JS-002⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

12.6

105

UNIT

Total supply voltage

Ambient temperature

V_S+–V_S–

T_A

°C

–40

7.4 Thermal Information

OPA817

THERMAL METRIC⁽¹⁾

DTK (WSON)

8 PINS

64.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

53.0

32.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.3

Ψ_JT

Y_JB

32.8

R_θJC(bot)

9.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics: V_S= ±5 V

At G = 1 V/V, R_F= 0, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≈25°C

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AC PERFORMANCE

V_OUT= 200 mV_PP

800

400

100

V_OUT= 200 mV_PP, G = 2 V/V

V_OUT= 200 mV_PP, G = 5 V/V

V_OUT= 200 mV_PP, G = 10 V/V

V_OUT= 200 mV_PP, G = 100 V/V

V_OUT= 2 V_PP

SSBW

Small-signal bandwidth

MHz

GBWP

LSBW

Gain-bandwidth product

Large-signal bandwidth

400

250

140

100

1000

750

0.7

MHz

V/µs

V_OUT= 4 V_PP

Bandwidth for 0.1-dB flatness

Slew rate (10% to 90%)

Rise, fall time

V_OUT= 2 V_PP

V_OUT= 4–V step

V_OUT= 1–V step, Gain = 2 V/V

V_OUT= 200–mV step

V_OUT= 2–V step

t_R, t_F

Settling time to 0.1%,

Overshoot and undershoot

Output Overdrive recovery time

V_OUT= 2–V step

V_OUT= V_S–to V_S+, G = 2 V/V,

f = 1 MHz, V_OUT= 2 V_PP

f = 10 MHz, V_OUT= 2 V_PP

f = 50 MHz, V_OUT= 2 V_PP

–110

–86

–76

–97

–120

–100

–68

–102

4.5

HD2

Second-order harmonic distortion

Third-order harmonic distortion

dBc

f = 10 MHz, V_OUT= 2 V_PP, R_L= 1 kΩ

f = 1 MHz, V_OUT= 2 V_PP

f = 10 MHz, V_OUT= 2 V_PP

f = 50 MHz, V_OUT= 2 V_PP

f = 10 MHz, V_OUT= 2 V_PP, R_L= 1 kΩ

f ≥200 kHz

HD3

e_N

Input voltage noise

nV/√Hz

kHz

Voltage noise 1/f corner frequency

Input current noise

2.6

fA/√Hz

DC PERFORMANCE

V_OUT= ±1 V

A_OL

Open-loop voltage gain

T_A= –40°C to +85°C

T_A= –40°C to +105°C

±250

±500

±600

±3.5

V_OS

Input-referred offset voltage

Input offset voltage drift

Input bias current

T_A= –40°C to +85°C

T_A= –40°C to +105°C

T_A= –40°C to +85°C

T_A= –40°C to +105°C

µV

µV/°C

±3.5

±20

±1000

±1500

±20

I_B

T_A= –40°C to +85°C

T_A= –40°C to +105°C

±500

±750

I_OS

Input offset current

T_A= –40°C to +85°C

T_A= –40°C to +105°C

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7.5 Electrical Characteristics: V_S= ±5 V (continued)

At G = 1 V/V, R_F= 0, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≈25°C

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Device turned OFF, OUT to FB pin

resistance

Internal feedback trace resistance

0.7

INPUT

2.1

2.0

2.7

-3.9

110

Most positive input voltage⁽¹⁾

Most negative input voltage⁽¹⁾

Common-mode rejection ratio

T_A= –40°C to +85°C

T_A= –40°C to +105°C

-3.5

-3.4

T_A= –40°C to +85°C

T_A= –40°C to +105°C

V_CM= ±0.5 V

CMRR

T_A= –40°C to 85°C

T_A= –40°C to 105°C

Input impedance common-mode

Input capacitance differential mode

60 || 2.9

0.1

GΩ|| pF

OUTPUT

no-load

-3.9

-3.7

-3.6

-3.4

-3.3

-3.2

R_L= 100 Ω

V_OL

Output voltage, low

T_A= –40°C to +85°C

T_A= –40°C to +105°C

no-load

3.7

3.4

3.9

3.7

R_L= 100 Ω

V_OH

Output voltage, high

3.3

T_A= –40°C to +85°C

T_A= –40°C to +105°C,

V_OUT= ±1 V, ΔV_OS< 2 mV

T_A= –40 to 85°C, ΔV_OS< 3 mV

T_A= –40 to 105°C, ΔV_OS< 3 mV

3.2

±58

±40

±35

Linear output drive (sourcing/sinking)

Short-circuit current

±100

0.04

Z_O

Closed loop output Impedance

f = 100 kHz

Ω

POWER SUPPLY

23.5

100

24.5

24.7

24.9

I_Q

Quiescent current

T_A= –40°C to +85°C

T_A= –40°C to +105°C

ΔV_S+= ±0.5 V

PSRR+ Power-supply rejection ratio

T_A= –40°C to +85°C

T_A= –40°C to +105°C

ΔV_S-= ±0.5 V,

PSRR-

Power-supply rejection ratio

T_A= –40°C to +85°C

T_A= –40°C to +105°C

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7.5 Electrical Characteristics: V_S= ±5 V (continued)

At G = 1 V/V, R_F= 0, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≈25°C

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER DOWN

Enable voltage threshold

Disable voltage threshold

Power-down quiescent current

Specified on above (V_S+) –1 V

Specified off below (V_S+) –3 V

PD ≤(V_S+) –3V

100

Power-down pin bias current in shutdown

mode

µs

PD = 0 V to (V_S+) –3 V

Power-down pin bias current in active

mode

0.5

0.3

PD = (V_S+) –1 V to (V_S+

)

Time from PD voltage exceeds threshold

to V_OUT= 90% of final value, V_IN= 1V

Turn-on time delay

Turn-off time delay

Time from PD voltage reduces below

threshold to I_Q= 10% of active mode

value

0.1

µs

(1) Input range for CMRR > 77-dB.

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7.6 Typical Characteristics: V_S= ±5 V

At G = 1 V/V, R_F= 0 Ω, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≅ 25°C

(unless otherwise noted).

-3

-6

-9

G = 1 V/V

G = 2 V/V

G = 5 V/V

G = 10 V/V

G = − 1 V/V

G = − 2 V/V

G = − 5 V/V

-12

-15

100k

10M

Frequency (Hz)

100M

100k

10M

100M

Frequency (Hz)

V_OUT= 200 mV_PP

图7-1. Noninverting Small-Signal Frequency Response

图7-2. Inverting Small-Signal Frequency Response

1.5

-3

-6

0.5

-0.5

-1

-9

-1.5

V_OUT= 0.5 V_PP

V_OUT= 1 V_PP

V_OUT= 2 V_PP

V_OUT= 4 V_PP

V_OUT= 0.5 V_PP

-2

V_OUT= 1 V_PP

V_OUT= 2 V_PP

V_OUT= 4 V_PP

-12

-2.5

-3

100k

-15

100k

10M

Frequency (Hz)

100M

10M

100M

Frequency (Hz)

图7-4. Gain Flatness vs Frequency

图7-3. Noninverting Large-Signal Frequency Response

-3

-6

-9

G = − 5 V/V

G = − 1 V/V

G = 1 V/V

-9

V_OUT= 0.5 V_PP

V_OUT= 1 V_PP

V_OUT= 2 V_PP

-12

G = 2 V/V

V_OUT= 4 V_PP

G = 10 V/V

-15

100k

-15

100k

10M

100M

10M

100M

Frequency (Hz)

G = －1 V/V

V_OUT= 2 V_PP

图7-5. Inverting Large-Signal Frequency Response

图7-6. Large-Signal Frequency Response Over Gain

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7.6 Typical Characteristics: V_S= ±5 V (continued)

At G = 1 V/V, R_F= 0 Ω, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≅ 25°C

(unless otherwise noted).

1.4

1.2

0.8

0.6

0.4

0.2

-3

-6

-0.2

-0.4

-0.6

-0.8

-1

-9

V_S= 6.5 V

V_S= 8 V

V_S= 10 V

V_S= 12 V

-12

V_OUT= 400 mV-step

V_OUT= 2 V-step

-1.2

-1.4

-15

100k

90 100

10M

Frequency (Hz)

100M

Time (ns)

V_OUT= 200 mV_PP

图7-8. Noninverting Large-Signal Pulse Response

图7-7. Noninverting Small-Signal Frequency Response Over

Supply

1.4

1.2

-60

HD2

HD3

-65

-70

0.8

0.6

0.4

0.2

-75

-80

-85

-0.2

-0.4

-0.6

-0.8

-90

-95

-100

-105

-110

-1

V_OUT= 400 mV-step

V_OUT= 2 V-step

-1.2

-1.4

90 100

100

Time (ns)

Load Resistance ()

G = －1 V/V

f = 10 MHz

V_OUT= 2 V_PP

图7-9. Inverting Large-Signal Pulse Response

图7-10. Harmonic Distortion vs Load Resistance

-40

-50

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-100

-110

-120

-130

-140

HD2

HD3

HD2

HD3

100k

10M

100M

Frequency (Hz)

V_OUT= 2 V_PP

Output Voltage (V_PP

)

f = 10 MHz

图7-12. Harmonic Distortion vs Frequency

图7-11. Harmonic Distortion vs Output Voltage

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7.6 Typical Characteristics: V_S= ±5 V (continued)

At G = 1 V/V, R_F= 0 Ω, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≅ 25°C

(unless otherwise noted).

-60

-65

-60

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

HD2

HD3

HD2

HD3

Noninverting Gain (V/V)

V_OUT= 2 V_PP

Inverting Gain (V/V)

V_OUT= 2 V_PP

f = 10 MHz

图7-13. Harmonic Distortion vs Noninverting Gain

图7-14. Harmonic Distortion vs Inverting Gain

-60

100

HD2

HD3

-70

-80

-90

-100

-110

-120

-130

100

10k

100k

Total Supply Voltage (V)

Frequency (Hz)

f = 10 MHz

V_OUT= 2 V_PP

图7-15. Harmonic Distortion vs Supply Voltage

图7-16. Voltage Noise Density vs Frequency

10k

-50

-60

2 MHz

5 MHz

10 MHz

17 MHz

-70

-80

100

-90

-100

-110

-120

10k

100k

10M

100M

-10

-8

-6

-4

-2

Frequency (Hz)

Single-Tone Load Power (dBm)

图7-17. Current Noise Density vs Frequency

图7-18. Intermodulation Distortion vs Load Power

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7.6 Typical Characteristics: V_S= ±5 V (continued)

At G = 1 V/V, R_F= 0 Ω, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≅ 25°C

(unless otherwise noted).

120

110

100

A_OLMagnitude (dB)

A_OLPhase ()

-15

-30

-45

-60

-75

-90

-105

-120

-135

-150

-165

-180

-195

-10

-20

10k

100k

10M

100M

Frequency (Hz)

图7-20. Open-Loop Gain Magnitude and Phase vs Frequency

图7-19. Common-Mode and Power-Supply Rejection Ratio vs

Frequency

100

-3

-6

-9

C_L= 10 pF, R_ISO= 33 

C_L= 20 pF, R_ISO= 22 

C_L= 33 pF, R_ISO= 15 

C_L= 100 pF, R_ISO= 8.6 

-12

-15

100

100k

10M

Frequency (Hz)

100M

Load Capacitance (pF)

V_OUT= 200 mV_PP

图7-22. Recommended Isolation Resistor vs Capacitive Load

图7-21. Frequency Response vs Capacitive Load

24.5

T_A= −40C

T_A= 25C

23.5

T_A= 85C

T_A= 105C

-1

-2

-3

-4

-5

−40C

22.5

25C

105C

90 100

Supply Voltage (V)

Output Current (mA)

图7-23. Quiescent Current vs Voltage Supply Over Temperature

图7-24. Output Voltage vs Output Current Over Temperature

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7.6 Typical Characteristics: V_S= ±5 V (continued)

At G = 1 V/V, R_F= 0 Ω, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≅ 25°C

(unless otherwise noted).

200

150

100

500

450

400

350

300

250

200

150

100

-50

-100

-150

-200

-250

-300

-40

-20

100

Ambient Temperature (C)

Input offset voltage (V)

40 units, delta from 25°C

4000 units, μ= 40 μV, σ= 60 μV

图7-25. Input Offset Voltage vs Temperature

图7-26. Input Offset Voltage Histogram

600

500

400

300

200

100

-100

-200

-300

-400

-500

-600

−40C

25C

105C

-4 -3.2 -2.4 -1.6 -0.8

0.8 1.6 2.4 3.2

Common-Mode Voltage (V)

Input offset voltage drift (V/C)

40 units, μ= 1.2 μV/°C, σ= 0.5 μV/°C

图7-28. Input Offset Voltage vs Common-Mode Voltage Over

图7-27. Input Offset Voltage Drift Histogram

Temperature

-50

-5

-100

-150

-200

-10

-15

-20

-25

-30

-40

-20

100

-40

-20

100

Ambient Temperature (C)

40 units

图7-29. Input Bias Current vs Temperature

图7-30. Input Offset Current vs Temperature

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7.6 Typical Characteristics: V_S= ±5 V (continued)

At G = 1 V/V, R_F= 0 Ω, R_F= 250 Ωfor other gains, R_L= 100 Ω, input and output referenced to mid-supply, and T_A≅ 25°C

(unless otherwise noted).

100

-50

-100

-150

-200

-250

-300

-350

-400

-450

-500

-2

-4

-6

-8

-10

−40C

25C

85C

Input x 2

Output

105C

-4

-3

-2

-1

100

150

200

Time (ns)

250

300

350

400

Common-Mode Voltage (V)

G = 2 V/V

图7-31. Input Bias Current vs Common-Mode Voltage Over

图7-32. Noninverting Output Overdrive Recovery

Temperature

Input x −1

Output

1.5

0.5

-1

-2

-3

-4

-5

-6

-0.5

-1

V_OUT

-1

-1.5

4.5

0.5

1.5

2.5

Time (s)

3.5

100

150

200

Time (ns)

250

300

350

400

G = －1 V/V

图7-34. Turn-On and Turn-Off Waveform

图7-33. Inverting Output Overdrive Recovery

10k

Z_OL

Z_CL

100

0.1

0.01

0.001

100

10k

100k

10M

100M

Frequency (Hz)

图7-35. Open-Loop and Closed-Loop Output Impedance vs Frequency

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8 Detailed Description

8.1 Overview

The OPA817 is a high voltage, unity gain stable, 400 MHz gain-bandwidth product (GBWP), voltage feedback

operational amplifier (op amp) featuring a 4.5 nV/√Hz low noise JFET input stage. The low offset voltage (250

μV maximum), offset voltage drift (3.5 μV/°C maximum), and unity gain bandwidth of 800 MHz makes it ideal

for high input impedance, high-speed data acquisition front-ends. The high voltage capability combined with

1000 V/µs slew rate enables applications needing wide output swings (9 V_PPat V_S= 12 V) for high-frequency

signals such as those often found in medical instrumentation, optical front-end, test, and measurement

applications. The low noise JFET input with pico-amperes of bias current makes the device attractive in high-

gain TIA applications and in test and measurement front-ends. OPA817 also features a power-down mode that

disables the core amplifier for power savings.

The OPA817 is built using TI's proprietary high-voltage, high-speed, complementary bipolar SiGe process.

8.2 Functional Block Diagram

The OPA817 is a conventional voltage feedback op amp with two high-impedance inputs and a low-impedance

output. 图8-1 and 图8-2 shows two standard amplifier configuration examples that are supported for this device.

The reference voltage (V_REF) level shifts the DC operating point for each configuration, which is typically set to

mid-supply in single-supply operation. V_REFis typically set to ground in split-supply applications.

V_S+

V_SIG

œ(R_F/ R_G) × V_SIG

V_S+

V_REF

V_SIG

(1 + R_F/ R_G) × V_SIG

V_REF

V_OUT

V_REF

V_IN

V_REF

V_IN

V_OUT

R_G

V_Sœ

R_F

R_G

V_Sœ

R_F

V_REF

图8-2. Inverting Amplifier

图8-1. Noninverting Amplifier

8.3 Feature Description

8.3.1 Input and ESD Protection

The OPA817 is built using a very high-speed complementary bipolar process. The internal junction breakdown

voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the

Absolute Maximum Ratings. As 图 8-3 shows, all device pins are protected with internal ESD protection diodes

to the power supplies.

The diodes provide moderate protection to input overdrive voltages beyond the supplies as well. The protection

diodes can typically support a 10-mA continuous current. Where higher currents are possible (for example, in

systems with ±12-V supply parts driving into the OPA817), current limiting series resistors should be added in

series with the two inputs to limit the current. Keep these resistor values as low as possible because high values

degrade both noise performance and frequency response. There are no back-to-back ESD diodes between V_IN+

and V_IN–. As a result, the differential input voltage between V_IN+and V_IN–is entirely absorbed by the V_GSof the

input JFET differential pair and must not exceed the voltage ratings shown in the Absolute Maximum Ratings.

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VS+

VIN+

Power Supply

ESD Cell

Internal

Circuitry

VOUT

VIN

图8-3. Internal ESD Protection

8.3.2 Feedback Pin

For high speed analog design, minimizing parasitic capacitances and inductances is critical to get the best

performance from a high-speed amplifier such as the OPA817. Parasitic capacitance and inductance are

especially detrimental in the feedback path and at the inverting input. They result in undesired poles and zeroes

in the feedback that could result in reduced phase margin or instability. Techniques used to correct this phase

margin reduction often result in reduced application bandwidth. To keep system engineers from making these

tradeoff choices and to simplify the PCB layout, OPA817 features an FB pin on the same side as the inverting

input pin (IN–). 图8-4 shows how this feature allows for a very short feedback resistor (R_F) connection between

the FB and the IN– pin, which minimizes parasitic capacitance and inductance with minimal PCB design effort.

Internally the FB pin is connected to OUT pin through metal routing on the silicon. Due to the fixed metal sizing

of this connection, the FB pin has limited current carrying capability. Therefore, the specifications in the Absolute

Maximum Ratings section must be adhered to for continuous operation. For applications requiring high accuracy,

the metal routing resistance from OUT to FB can be considered and added to R_Fto set the desired gain. For

more information, see 节7.5.

VS+

OUT

R_F

INÞ

VSÞ

IN+

图8-4. R_FConnection Between FB and IN–Pins

8.3.3 FET-Input Architecture with Wide Gain-Bandwidth Product

图 8-5 shows the open-loop gain and phase response of the OPA817. The GBWP of an op amp is measured in

the 20 dB/decade constant slope region of the A_OLmagnitude plot. The open-loop gain of 60 dB for the OPA817

is along this 20 dB/decade slope and the corresponding frequency intercept is at 400 kHz. Converting 60 dB to

linear units (1000 V/V) and multiplying it with the 400 kHz frequency intercept gives the GBWP of OPA817 as

400 MHz. As can be inferred from the A_OLBode plot, the second pole in the A_OLresponse occurs after A_OL

magnitude drops below 0 dB (1 V/V). This results in phase change of less than 180° at 0 dB A_OLindicating that

the amplifier will be stable in a gain of 1 V/V. Amplifiers like OPA817 that are JFET-input, low noise and unity-

gain stable can be used as high input impedance buffers and gain stages with minimal degradation in SNR. It

has 800 MHz of SSBW in gain of 1V/V configuration with approximately 55° phase margin.

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The low input offset voltage and offset voltage drift of OPA817 makes it a very suitable amplifier for high

precision, high input impedance, wideband data acquisition system front-ends. As 图 9-2 shows, the system

benefits from the low noise JFET input stage with pico-amperes of input bias current to achieve higher precision

at 1-MΩ input impedance settings and higher SNR at 50-Ω input impedance setting simultaneously in a typical

data acquisition front-end circuit.

120

110

100

120

110

100

A_OLMagnitude (dB)

A_OLPhase ()

T_A= −40C

T_A= 25 C

T_A= 105 C

-15

-30

-45

-60

-75

-90

-105

-120

-135

-150

-165

-180

-195

-10

-20

-30

-40

-10

-20

10k

100k

10M

100M

Frequency (Hz)

10k

100k

10M

100M

R_L= 100 Ω

Frequency (Hz)

R_L= 100 Ω

图8-5. Open-Loop Gain Magnitude and Phase Vs

Frequency

图8-6. Open-Loop Gain Magnitude vs Temperature

8.3.4 Device Functional Modes

8.3.4.1 Power-Down (PD) Pin

The OPA817 includes a power-down mode for low-power or standby operation and only consumes 55 μA

(typical) of current when placed in power-down mode. Low-power systems that are only active for small periods

of time benefit from this feature. The OPA817 can transition from low-power mode to active-mode in 300 ns

(typical). For power-down pin control thresholds, refer to 节 7.5. An internal pull-up resistor of 2-MΩ provides a

weak pull-up to V_S+if PD is left unconnected. An external 1-nF capacitor to V_S+may be used to avoid external

noise coupling and false triggering. If the power-down mode is not used in an application, then connect the PD

pin to V_S+.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

9.1.1 Wideband, High-Input Impedance DAQ Front-End

The OPA817 features a unique combination of high GBWP, low-input voltage noise, and the DC precision of a

trimmed JFET-input stage to provide a high input impedance for a voltage-feedback amplifier. 图 9-2 shows how

its very high GBWP of 400 MHz and high large signal bandwidth of 250 Mhz can be used to either deliver wide

signal bandwidths at high gains or to extend the achievable bandwidth or gain in typical high-speed, high-input

impedance data acquisition front-end applications. To achieve the full performance of the OPA817, careful

attention to the printed circuit board (PCB) layout and component selection is required as discussed in the

following sections of this data sheet. OPA817 also features a wider supply range thereby enabling a wider

common-mode input range to support higher input signal swings.

图 9-1 shows the noninverting gain of +2 V/V circuit used as the basis for most of the Typical Characteristics.

Most of the curves were characterized using signal sources with 50-Ω driving impedance, and with

measurement equipment presenting a 50-Ω load impedance. As 图 9-1 shows, the 49.9-Ω shunt resistor at the

V_INterminal matches the source impedance of the test generator, while the 49.9-Ω series resistor at the V_O

terminal provides a matching resistor for the measurement equipment load. Generally, data sheet voltage swing

specifications are at the output pin (V_Oin 图 9-1) while output power specifications are at the matched 50-Ω

load. As shown in 图 9-1, the total 100-Ω load at the output combined with the 250-Ω total feedback network

load presents the OPA817 with an effective output load of 83.3 Ωfor the circuit.

+5 V

0.01 μF

0.22 μF

0.01 μF

50 Source

V_IN

50 Load

OPA817

To FDA or VGA

–

V_OUT

V_O

V_IN

49.9

1 M

0.01 μF

0.22 μF

0.01 μF

–5 V

图9-2. High Input Impedance DAQ Front-End

R_G

250

R_F

250

图9-1. Noninverting G = +2 V/V Configuration and

Test Circuit

Voltage-feedback operational amplifiers, unlike current feedback amplifiers, can use a wide range of resistor

values to set their gain. As 图 9-1 shows, the parallel combination of R_F|| R_Gshould always be kept to a lower

value to retain a controlled frequency response for the noninverting voltage amplifier. In the noninverting

configuration, the parallel combination of R_F|| R_Gwill form a pole with the parasitic input capacitance at the

inverting node of the OPA817 (including layout parasitic capacitance). For best performance, this pole should be

at a frequency greater than the closed loop bandwidth for the OPA817.

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9.2 Typical Applications

9.2.1 High Input Impedance, 200 MHz, Digitizer Front-End Amplifier Design

The OPA817 offers a wide large-signal bandwidth, high-slew rate along with high-input impedance making it

ideal for data acquisition systems. The trimmed DC precision of the OPA817 enables its use directly as front-end

amplifier where low offset and offset voltage drift is needed.

+5 V

0.01 μF

0.22 μF

V_IN

R_S

OPA817

–

V_OUT

900 k

100 k

0.01 μF

0.22 μF

100

To FDA or VGA

–5 V

图9-3. High Input Impedance, 200 MHz, Digitizer Front-End Amplifier

9.2.2 Design Requirements

表9-1 lists the design requirements for a High Input Impedance, 200 MHz, Digitizer Front-End Amplifier.

表9-1. Design Requirements

Specification

Value

Input Impedance

1 MΩ/ 50Ω

20 V_PP/ 2 V_PP

3.5 µV/°C maximum

80 µV_RMS

Input Range (1 MΩ/ 50 Ω)

Offset Drift

Noise at Highest Resolution (50 ΩInput)

9.2.3 Detailed Design Procedure

• Input Impedance: The JFET-input stage of the OPA817 offers giga ohm's of input impedance and therefore

enables the front-end to be terminated with a 1 MΩresistor while achieving excellent precision. A 50 Ω

resistance can also be switched in offering matched termination for high-frequency signals. The OPA817

therefore enables the designer to use both 1 MΩand 50 Ωtermination in the same signal chain.

• Noise: The total noise of the front-end amplifier is the function of the voltage and current noise of the

OPA817, input termination, and the resistors thermal noise. In 50 Ωmode, the dominant noise source,

however, is contributed by the voltage noise of the OPA817 due to its presence across the complete

bandwidth. Thus, the total RMS noise of the front-end amplifier shall be approximately equal to the voltage

noise of OPA817 over 200 MHz.

The specified input referred voltage noise of the OPA817 is 4.5 nV/√Hz; for more information see 节7.5. The

total integrated RMS noise at the input in a bandwidth of 200 MHz is given by the following equation:

En_RMS= 4.5 nV/√Hz × √(200 MHz × 1.57) = 80 µV_RMS

(1)

The Brickwall correction factor of 1.57 is applied assuming the bandwidth will be limited to 200 MHz with a

single pole RC-filter before digitizing the signal with the ADC. Detailed calculations can be found on TI

Precision Labs –Op Amps: Noise –Spectral Density.

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• Optimizing Overshoot: The OPA817 features an internal slew-boost circuit to deliver fast rise-time in

applications needing high slew rates such as when configured as a transimpedance amplifier. For

applications where overshoot needs to be limited, the input slew rates can be limited with introducing a series

resistance (R_S) as shown in 图9-3. The resistance R_Sforms a low pass filter with the input capacitance of

approximately 2.6 pF at the noninverting pin of the OPA817 limiting the input slew rate to the amplifier. 图9-4

shows how limiting the input slew rate to the amplifier results in good overshoot performance, and 图9-5

shows how this achieves a small signal and large signal bandwidth of 200 MHz.

9.2.4 Application Curves

0.8

0.6

0.4

0.2

-3

-6

-0.2

-0.4

-0.6

-0.8

-1

-9

V_IN=  0.5 V-step

V_OUT, R_S= 0 

-12

V_OUT= 100 mV_PP

V_OUT= 1 V_PP

V_OUT, R_S= 250 

-15

100k

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

10M

Frequency (Hz)

100M

D106

D105

Time (ns)

图9-4. Step Response of Digitizer Front-End

图9-5. Frequency Response for R_S= 250 Ω

10 Power Supply Recommendations

The OPA817 is intended to operate on supplies ranging from 6 V to 12.6 V. OPA817 supports single-supply, split,

balanced, and unbalanced bipolar supplies. When operating at supplies below 8 V, consideration must be given

to the input common-mode range of the amplifier. Under these supply conditions, the common-mode must be

biased appropriately for linear operation. Thus, the limit to lower supply voltage operation is the usable input

voltage range for the JFET-input stage.

11 Layout

11.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier like the OPA817 requires careful attention to

board layout parasitics and external component types. Recommendations that will optimize performance include

the following:

1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on

the output and inverting input pins can cause instability. On the noninverting input, parasitic capacitance can

react with the source impedance to cause unintentional bandlimiting. Ground and power metal planes act as

one of the plates of a capacitor while the signal trace metal acts as the other separated by PCB dielectric. To

reduce this unwanted capacitance, care must be taken to minimize the routing of the feedback network. A

plane cutout around and underneath the inverting input pin on all ground and power planes is recommended.

Otherwise, ground and power planes should be unbroken elsewhere on the board.

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2. Minimize the distance (less than 0.25-in) from the power-supply pins to high-frequency decoupling

capacitors. Use high quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage

ratings at least three times greater than the amplifiers maximum power supplies to ensure that there is a low-

impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth specification. At

the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O

pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling

capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must be used on

the supply pins. These can be placed further from the device and are shared among several devices in the

same area of the PC board.

3. Careful selection and placement of external components will preserve the high frequency

performance of the OPA817. Use low-reactance resistors. Surface-mount resistors work best and allow a

tighter overall layout. Never use wirewound type resistors in a high frequency application. Because the

output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the

feedback and series output resistor, if any, as close as possible to the inverting input and the output pin,

respectively.

Other network components, such as noninverting input termination resistors, should also be placed close to

the package. Even with a low parasitic capacitance at the noninverting input, high external resistor values

can create significant time constants that can degrade performance. When OPA817 is configured as a

conventional voltage amplifier, keep the resistor values as low as possible and consistent with the load

driving considerations. Decreasing the resistor values keeps the resistor noise terms low and minimizes the

effect of the parasitic capacitance. However, lower resistor values increase the dynamic power consumption

because R_Fand R_Gbecome part of the output load network of the amplifier.

4. Heat dissipation is important for a high voltage device like OPA817. For good thermal relief, the thermal

pad should be connected to a heat spreading plane that is preferably on the same layer as OPA817 or

connected by as many vias as possible, if the plane is on a different layer. It is recommended to have at

least one heat spreading plane on the same layer as the OPA817 that makes a direct connection to the

thermal pad with wide metal for good thermal conduction when operating at high ambient temperatures. If

more than one heat spreading plane is available, then connect them by a number of vias to further improve

the thermal conduction.

11.1.1 Thermal Considerations

The OPA817 will not require heatsinking or airflow in most applications. Maximum allowed junction temperature

will set the maximum allowed internal power dissipation as described in the following paragraph. In no case

should the maximum junction temperature be allowed to exceed 150°C.

Operating junction temperature (T_J) is given by T_A+ P_D× R_θJA. The total internal power dissipation (P_D) is the

sum of quiescent power (P_DQ) and additional power dissipated in the output stage (P_DL) to deliver load power.

Quiescent power is the specified no-load supply current times the total supply voltage across the part. P_DLwill

depend on the required output signal and load, but for a grounded resistive load the P_DLwill be at a maximum

when the output is fixed at a voltage equal to 1/2 of either supply voltage (for balanced bipolar supplies). Under

this condition P_DL= V_S²/(4 × R_L) where R_Lincludes feedback network loading.

Note that it is the power in the output stage and not into the load that determines internal power dissipation.

As a worst-case example, compute the maximum T_Jusing OPA817 in the circuit of 图 9-1 operating at the

maximum specified ambient temperature of +105°C and driving a grounded 100-Ωload.

P_D= 10 V × 23.5 mA + 5²/(4 × (100 Ω|| 500 Ω)) ≅ 310 mW

Maximum T_J= 105°C + (0.310 W × 64.9°C/W) = 125.1°C.

All actual applications will be operating at lower internal power and junction temperature.

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11.2 Layout Example

Representative schematic

V_S+

Connect PD to VS+ to enable the

amplifier

C_BYP

R_S

Load

Thermal

Pad

R_S

R_F

C_BYP

Place gain and feedback resistors

close to pins to minimize stray

capacitance

V_Sœ

R_F

No Connect

R_G

C_BYP

Connect the thermal pad to a heat

spreading plane, generally ground

Ground and power plane exist on

inner layers.

Ground and power plane removed

from inner layers. Ground fill on

outer layers also removed.

Place bypass capacitor

close to power pins

图11-1. Layout Recommendation

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

• Texas Instruments, Wide Bandwidth Optical Front-end Reference Design

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, OPA817EVM User's Guide

• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report

• Texas Instruments, Maximizing the Dynamic Range of Analog TIA Front-End techincal brief

• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 1

• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 2

• Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits

• Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: OPA817

PACKAGE OPTION ADDENDUM

www.ti.com

19-May-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

OPA817DTKR

ACTIVE

WSON

DTK

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

817

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OPA817DTKR

WSON

DTK

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Dec-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

WSON DTK

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

OPA817DTKR

3000

Pack Materials-Page 2

PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

DTK0008A

3.1

2.9

3.1

2.9

PIN 1 INDEX AREA

0.8 MAX

SEATING PLANE

0.05

0.00

0.08 C

(0.1) TYP

1.5

1.4

6X 0.5

1.75

PKG

1.84

1.64

0.3

0.2

0.1

0.05

C A B

0.5

0.3

PIN 1 ID

(OPTIONAL)

PKG

4224357 / A 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

WSON - 0.8 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

DTK0008A

(2.8)

(1.45)

8X (0.25)

6X (0.5)

(0.475)

(0.62)

PKG

(1.74)

(1.5)

(R0.05) TYP

(Ø0.2) VIA

(TYP)

PKG

8X(0.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

SOLDER MASK

OPENING

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED METAL

NON- SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224357 / A 07/2018

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

WSON - 0.8 mm max height

DTK0008A

PLASTIC QUAD FLATPACK- NO LEAD

(2.8)

(1.34)

8X (0.25)

6X (0.5)

PKG

(1.5) (1.58)

(R0.05) TYP

8X(0.6)

PKG

EXPOSED METAL

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 9: 84%

SCALE: 20X

4224357 / A 07/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

www.ti.com

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