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OPA847IDBVT [TI]

具有关断状态的宽带超低噪声电压反馈运算放大器 | DBV | 6 | -40 to 85;
OPA847IDBVT
型号： OPA847IDBVT
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有关断状态的宽带超低噪声电压反馈运算放大器 | DBV | 6 | -40 to 85

放大器 PC 光电二极管 运算放大器 放大器电路
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OPA847  
O
P
A
8
4
7
www.ti.com  
SBOS251E – JULY 2002 – REVISED DECEMBER 2008  
Wideband, Ultra-Low Noise, Voltage-Feedback  
OPERATIONAL AMPLIFIER with Shutdown  
DESCRIPTION  
FEATURES  
The OPA847 combines very high gain bandwidth and large  
signal performance with an ultra-low input noise voltage  
(0.85nV/√Hz) while using only 18mA supply current. Where  
power saving is critical, the OPA847 also includes an op-  
tional power shutdown pin that, when pulled low, disables the  
amplifier and decreases the supply current to < 1% of the  
powered-up value. This optional feature may be left discon-  
nected to ensure normal amplifier operation when no power-  
down is required.  
● HIGH GAIN BANDWIDTH: 3.9GHz  
● LOW INPUT VOLTAGE NOISE: 0.85nV/  
√Hz  
● VERY LOW DISTORTION: –105dBc (5MHz)  
● HIGH SLEW RATE: 950V/µs  
● HIGH DC ACCURACY: VIO < ±100µV  
● LOW SUPPLY CURRENT: 18.1mA  
● LOW SHUTDOWN POWER: 2mW  
● STABLE FOR GAINS ≥ 12  
The combination of very low input voltage and current noise,  
along with a 3.9GHz gain bandwidth product, make the  
OPA847 an ideal amplifier for wideband transimpedance  
applications. As a voltage gain stage, the OPA847 is opti-  
mized for a flat frequency response at a gain of +20V/V and  
is stable down to gains as low as +12V/V. New external  
compensation techniques allow the OPA847 to be used at  
any inverting gain with excellent frequency response control.  
Using this technique in a differential Analog-to-Digital Con-  
verter (ADC) interface application, shown below, can deliver  
one of the highest dynamic-range interfaces available.  
APPLICATIONS  
● HIGH DYNAMIC RANGE ADC PREAMPS  
● LOW NOISE, WIDEBAND, TRANSIMPEDANCE  
AMPLIFIERS  
● WIDEBAND, HIGH GAIN AMPLIFIERS  
● LOW NOISE DIFFERENTIAL RECEIVERS  
● ULTRASOUND CHANNEL AMPLIFIERS  
● IMPROVED UPGRADE FOR THE OPA687,  
CLC425, AND LMH6624  
OPA847 RELATED PRODUCTS  
INPUT NOISE  
VOLTAGE (nV/√Hz)  
GAIN BANDWIDTH  
PRODUCT (MHz)  
SINGLES  
OPA842  
OPA843  
OPA846  
2.6  
2.0  
1.2  
200  
800  
+5V  
+5V  
0.001µF  
20Ω  
1750  
OPA847  
100Ω  
1.7pF  
DIFFERENTIAL OPA847 DRIVER DISTORTION  
2VPP, at converter input.  
INP  
–5V  
2kΩ  
–70  
–75  
50Ω Source  
100pF  
VCM  
39pF  
39pF  
850Ω  
1:2  
ADS5500  
14-Bit  
125MSPS  
< 5.1dB  
Noise  
850Ω  
–80  
0.1µF  
Figure  
–85  
2kΩ  
+5V  
OPA847  
–5V  
INN  
100Ω  
1.7pF  
100pF  
–90  
0.001µF  
20Ω  
2nd-Harmonic  
–95  
3rd-Harmonic  
–100  
–105  
–110  
24.6dB Gain  
Ultra-High Dynamic Range  
Differential ADC Driver  
10  
20  
30  
40  
50  
Frequency (MHz)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
Copyright © 2002-2008, Texas Instruments Incorporated  
www.ti.com  
ABSOLUTE MAXIMUM RATINGS(1)  
ELECTROSTATIC  
DISCHARGE SENSITIVITY  
This integrated circuit can be damaged by ESD. Texas Instru-  
ments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling  
and installation procedures can cause damage.  
Power Supply ............................................................................... ±6.5VDC  
Internal Power Dissipation........................ See Thermal Analysis Section  
Differential Input Voltage .................................................................. ±1.2V  
Input Voltage Range............................................................................ ±VS  
Storage Temperature Range: D, DBV ...........................–65°C to +125°C  
Lead Temperature (soldering, 10s) .............................................. +300°C  
Junction Temperature (TJ ) ........................................................... +150°C  
ESD Rating (Human Body Model) .................................................. 1500V  
(Charge Device Model) ............................................... 1500V  
ESD damage can range from subtle performance degradation  
tocompletedevicefailure. Precisionintegratedcircuitsmaybe  
more susceptible to damage because very small parametric  
changes could cause the device not to meet its published  
specifications.  
(Machine Model) ........................................................... 100V  
NOTE: (1) Stresses above these ratings may cause permanent damage.  
Exposure to absolute maximum conditions for extended periods may degrade  
device reliability. These are stress ratings only, and functional operation of the  
device at these or any other conditions beyond those specified is not implied.  
PACKAGE/ORDERING INFORMATION(1)  
SPECIFIED  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
PRODUCT  
PACKAGE-LEAD  
OPA847  
SO-8  
D
"
DBV  
"
–40°C to +85°C  
OPA847  
OPA847ID  
OPA847IDR  
OPA847IDBVT  
OPA847IDBVR  
Rails, 100  
"
OPA847  
"
"
"
"
OATI  
"
Tape and Reel, 2500  
Tape and Reel, 250  
Tape and Reel, 3000  
SOT23-6  
–40°C to +85°C  
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI web site  
at www.ti.com.  
PIN CONFIGURATIONS  
Top View  
SO Top View  
SOT  
Output  
1
6
+VS  
–VS  
DIS  
2
3
5
4
Noninverting Input  
Inverting Input  
NC  
1
2
3
4
8
7
6
5
DIS  
Inverting Input  
+VS  
Noninverting Input  
Output  
NC  
–VS  
NC = No Connection  
OATI  
Pin Orientation/Package Marking  
OPA847  
2
SBOS251E  
www.ti.com  
ELECTRICAL CHARACTERISTICS: VS = ±5V  
Boldface limits are tested at +25°C.  
RL = 100Ω, RF = 750Ω, RG = 39.2Ω, and G = +20 (see Figure 1 for AC performance only), unless otherwise noted.  
OPA847ID, IDBV  
MIN/MAX OVER TEMPERATURE  
TYP  
0
°
C to  
–40  
°
C to  
MIN/  
TEST  
PARAMETER  
CONDITIONS  
+25°C  
+25°C(1)  
70°C(2)  
+85°C(2)  
UNITS  
MAX LEVEL(3)  
AC PERFORMANCE (see Figure 1)  
Closed-Loop Bandwidth  
G = +12, RG = 39.2Ω, VO = 200mVPP  
G = +20, RG = 39.2Ω, VO = 200mVPP  
G = +50, RG = 39.2Ω, VO = 200mVPP  
G ≥ +50  
600  
350  
78  
3900  
60  
MHz  
MHz  
MHz  
MHz  
MHz  
dB  
typ  
min  
min  
min  
min  
max  
C
B
B
B
B
B
230  
63  
3100  
40  
210  
60  
3000  
35  
195  
57  
2800  
30  
Gain Bandwidth Product (GBP)  
Bandwidth for 0.1dB Gain Flatness  
Peaking at a Gain of +12  
Harmonic Distortion  
G = +20, RL = 100Ω  
4.5  
7
10  
12  
G = +20, f = 5MHz, VO = 2VPP  
RL = 100Ω  
2nd-Harmonic  
–74  
–105  
–103  
–110  
39  
–70  
–90  
–96  
–105  
37  
–69  
–89  
–91  
–100  
36  
–68  
–88  
–88  
–90  
35  
dBc  
dBc  
dBc  
dBc  
dBm  
max  
max  
max  
max  
min  
B
B
B
B
B
B
B
RL = 500Ω  
RL = 100Ω  
RL = 500Ω  
3rd-Harmonic  
2-Tone, 3rd-Order Intercept  
Input Voltage Noise Density  
Input Current Noise Density  
Pulse Response  
Rise-and-Fall Time  
Slew Rate  
G = +20, f = 20MHz  
f > 1MHz  
√Hz  
√Hz  
0.85  
2.5  
0.92  
3.5  
0.98  
3.6  
1.0  
3.7  
nV/  
pA/  
max  
max  
f > 1MHz  
0.2V Step  
2V Step  
2V Step  
2V Step  
2V Step  
1.2  
950  
20  
10  
6
1.75  
700  
2.0  
625  
2.2  
535  
ns  
V/µs  
ns  
ns  
ns  
max  
min  
typ  
max  
max  
B
B
C
B
B
Settling Time to 0.01%  
0.1%  
12  
8
14  
10  
18  
12  
1%  
DC PERFORMANCE(4)  
Open-Loop Voltage Gain (AOL  
Input Offset Voltage  
Average Offset Voltage Drift  
Input Bias Current  
Input Bias Current Drift (magnitude)  
Input Offset Current  
Input Offset Current Drift  
)
VO = 0V  
VCM = 0V  
VCM = 0V  
VCM = 0V  
VCM = 0V  
VCM = 0V  
VCM = 0V  
98  
±0.1  
±0.25  
–19  
–15  
±0.1  
±0.1  
90  
±0.5  
±0.25  
–39  
–15  
±0.6  
±0.1  
89  
±0.58  
±1.5  
–41  
–40  
±0.7  
±2  
88  
dB  
mV  
µV/°C  
µA  
nA/°C  
µA  
nA/°C  
min  
max  
max  
max  
max  
max  
max  
A
A
B
A
B
A
B
±0.60  
±1.5  
–42  
–70  
±0.85  
±3.5  
INPUT  
Common-Mode Input Range (CMIR)(5)  
Common-Mode Rejection Ratio (CMRR)  
Input Impedance  
±3.3  
110  
±3.1  
95  
±3.0  
93  
±2.9  
90  
V
dB  
min  
min  
A
A
VCM = ±0.5V, Input-Referred  
Differential  
Common-Mode  
VCM = 0V  
VCM = 0V  
2.7 || 2.0  
2.3 || 1.7  
kΩ || pF  
MΩ || pF  
typ  
typ  
C
C
OUTPUT  
Output Voltage Swing  
≥ 400Ω Load  
100Ω Load  
VO = 0V  
±3.5  
±3.4  
100  
–75  
0.003  
±3.3  
±3.2  
60  
±3.1  
±3.0  
56  
±3.0  
±2.9  
52  
V
V
mA  
mA  
Ω
min  
min  
min  
min  
typ  
A
A
A
A
C
Current Output, Sourcing  
Current Output, Sinking  
Closed-Loop Output Impedance  
VO = 0V  
G = +20, f = < 100kHz  
–60  
–56  
–52  
POWER SUPPLY  
Specified Operating Voltage  
Maximum Operating Voltage  
Maximum Quiescent Current  
Minimum Quiescent Current  
Power-Supply Rejection Ratio  
+PSRR, –PSRR  
±5  
±6  
18.1  
18.1  
V
V
mA  
mA  
typ  
max  
max  
min  
C
A
A
A
±6  
18.4  
17.8  
±6  
18.7  
17.5  
±6  
18.9  
17.1  
VS = ±5V  
VS = ±5V  
|VS| = 4.5V to 5.5V, Input-Referred  
(Pin 8 on SO-8; Pin 5 on SOT23-6)  
100  
95  
93  
90  
dB  
min  
A
POWER-DOWN (disabled low)  
Power-Down Quiescent Current (+VS)  
On Voltage (enabled high or floated)  
Off Voltage (disabled asserted low)  
Power-Down Pin Input Bias Current  
Power-Down Time  
–200  
3.5  
1.8  
150  
200  
60  
–270  
3.75  
1.7  
–320  
3.85  
1.6  
–370  
3.95  
1.5  
µA  
V
V
µA  
ns  
ns  
dB  
max  
min  
max  
max  
typ  
A
A
A
A
C
C
C
(VDIS = 0)  
190  
200  
210  
Power-Up Time  
Off Isolation  
typ  
typ  
5MHz, Input to Output  
70  
THERMAL  
Specification ID, IDBV  
Thermal Resistance, θJA  
–40 to +85  
°C  
typ  
C
Junction-to-Ambient  
D
SO-8  
125  
150  
°C/W  
°C/W  
typ  
typ  
C
C
DBV SOT23  
NOTES:(1)Junctiontemperature=ambientfor+25°Cspecifications. (2)Junctiontemperature=ambientatlowtemperaturelimit:junctiontemperature=ambient+23°C  
at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation.  
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input common-mode  
voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits.  
OPA847  
SBOS251E  
3
www.ti.com  
TYPICAL CHARACTERISTICS: VS = ±5V  
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.  
NONINVERTING SMALL-SIGNAL  
FREQUENCY RESPONSE  
INVERTING SMALL-SIGNAL  
FREQUENCY RESPONSE  
6
3
6
3
VO = 0.2VPP  
RG = 39.2Ω  
RL = 100Ω  
RF Adjusted  
VO = 0.2VPP  
RL = 100Ω  
RG = RS = 50Ω  
RF Adjusted  
G = +12  
G = –30  
G = –20  
0
0
–3  
–6  
–9  
–12  
–15  
–3  
–6  
–9  
–12  
–15  
G = +20  
G = +30  
G = +50  
G = –40  
G = –50  
See Figure 1  
See Figure 2  
1
10  
100  
Frequency (MHz)  
1000  
1
10  
100  
Frequency (MHz)  
1000  
INVERTING LARGE-SIGNAL  
FREQUENCY RESPONSE  
NONINVERTING LARGE-SIGNAL  
FREQUENCY RESPONSE  
35  
32  
29  
26  
23  
20  
17  
14  
29  
26  
23  
20  
17  
14  
11  
8
RG = 39.2Ω  
RL = 100Ω  
G = +20V/V  
See Figure 2  
VO = 200mVPP  
VO = 0.2VPP  
VO = 1VPP  
VO = 2VPP  
VO = 5VPP  
VO = 1VPP  
VO = 2VPP  
VO = 5VPP  
RL = 100Ω  
RG = RS = 50Ω  
G = –40V/V  
See Figure 1  
10  
10  
100  
Frequency (MHz)  
1000  
100  
1000  
Frequency (MHz)  
NONINVERTING PULSE RESPONSE  
INVERTING PULSE RESPONSE  
0.25  
0.20  
0.15  
0.10  
0.05  
0
1.25  
0.25  
0.20  
0.15  
0.10  
0.05  
0
1.25  
Large Signal ± 1V  
Large Signal ± 1V  
G = +20V/V  
1.00  
0.75  
0.50  
0.25  
0
1.00  
0.75  
0.50  
0.25  
0
Right Scale  
Right Scale  
Small Signal ± 100mV  
Small Signal ± 100mV  
Left Scale  
Left Scale  
–0.05  
–0.10  
–0.15  
–0.20  
–0.25  
–0.25  
–0.50  
–0.75  
–1.00  
–1.25  
–0.05  
–0.10  
–0.15  
–0.20  
–0.25  
–0.25  
–0.50  
–0.75  
–1.00  
–1.25  
G = –40V/V  
See Figure 2  
RG = RS = 50Ω  
L = 100Ω  
See Figure 1  
R
Time (5ns/div)  
Time (5ns/div)  
OPA847  
4
SBOS251E  
www.ti.com  
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)  
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.  
5MHz HARMONIC DISTORTION vs LOAD RESISTANCE  
G = +20V/V  
1MHz HARMONIC DISTORTION vs LOAD RESISTANCE  
G = +20V/V  
–70  
–75  
–75  
–80  
VO = 2VPP  
VO = 5VPP  
–80  
2nd-Harmonic  
–85  
–85  
–90  
–90  
2nd-Harmonic  
–95  
–100  
–105  
–110  
–115  
–95  
3rd-Harmonic  
3rd-Harmonic  
–100  
–105  
See Figure 1  
400 450 500  
See Figure 1  
100 150 200  
100  
150  
200  
250  
300  
350  
250  
300  
350  
400  
450  
500  
Load Resistance (Ω)  
Load Resistance (Ω)  
HARMONIC DISTORTION vs OUTPUT VOLTAGE  
G = +20V/V  
HARMONIC DISTORTION vs FREQUENCY  
G = +20V/V  
VO = 2VPP  
RL = 200Ω  
–65  
–75  
–75  
–80  
F = 5MHz  
L = 200Ω  
R
–85  
2nd-Harmonic  
2nd-Harmonic  
–90  
–85  
–95  
–95  
–100  
–105  
–110  
–115  
3rd-Harmonic  
3rd-Harmonic  
–105  
–115  
See Figure 1  
0.1  
See Figure 1  
1
10  
0.1  
1
10  
Frequency (MHz)  
100  
Output Voltage Swing (VPP  
)
HARMONIC DISTORTION vs NONINVERTING GAIN  
2nd-Harmonic  
HARMONIC DISTORTION vs INVERTING GAIN  
–75  
–80  
–70  
–75  
–80  
–85  
2nd-Harmonic  
VO = 2VPP  
RL = 200Ω  
F = 5MHz  
–85  
VO = 2VPP  
RL = 200Ω  
F = 5MHz  
–90  
–90  
RF = 750Ω  
–95  
–95  
RG = 50Ω  
RG Adjusted  
RF Adjusted  
–100  
–105  
–110  
–100  
–105  
–110  
3rd-Harmonic  
3rd-Harmonic  
40  
See Figure 2  
45 50  
See Figure 1  
50 55 50  
15  
20  
25  
30  
35  
40  
45  
20  
25  
30  
35  
Gain –V/V  
Gain (V/V)  
OPA847  
SBOS251E  
5
www.ti.com  
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)  
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.  
INPUT VOLTAGE AND CURRENT NOISE  
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT  
50  
45  
40  
35  
30  
25  
20  
10  
G = +20V/V  
20dB to matched load.  
2.7pA/√Hz  
Current Noise  
1
50Ω  
0.85nV/√Hz  
Voltage Noise  
PO  
PI  
OPA847  
50Ω  
50Ω  
750Ω  
39.2Ω  
0
101  
102  
103  
104  
105  
106  
107  
5
1
1
10  
15  
20  
25  
30  
35  
40  
45  
50  
Frequency (Hz)  
Frequency (MHz)  
NONINVERTING GAIN FLATNESS TUNE  
LOW GAIN INVERTING BANDWIDTH  
1
0
0.5  
0.4  
V
O = 200mVPP  
NG = 12  
NG = 14  
NG = 16  
AV = +12V/V  
NG = Noise Gain  
G = –8  
–1  
–2  
–3  
–4  
–5  
–6  
–7  
–8  
–9  
0.3  
VO = 0.2VPP  
RF = 750Ω  
0.2  
0.1  
0
G = –1  
G = –2  
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
NG = 18  
NG = 20  
G = –4  
External Compensation  
See Figure 8  
External Compensation  
See Figure 6  
1
10  
100  
1000  
10  
100  
Frequency (MHz)  
1000  
Frequency (MHz)  
RECOMMENDED RS vs CAPACITIVE LOAD  
FREQUENCY RESPONSE vs CAPACITIVE LOAD  
100  
10  
1
29  
26  
23  
20  
17  
14  
G = +20V/V  
RS adjusted for capacitive load.  
C = 10pF  
C = 22pF  
C = 47pF  
C = 100pF  
RS  
VO  
VI  
OPA847  
50Ω  
CL  
1kΩ  
750Ω  
(1kΩ is optional.)  
39.2Ω  
1
10  
100  
1000  
10  
100  
Frequency (MHz)  
1000  
Capacitive Load (pF)  
OPA847  
6
SBOS251E  
www.ti.com  
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)  
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.  
COMMON-MODE REJECTION RATIO AND  
OPEN-LOOP GAIN AND PHASE  
POWER-SUPPLY REJECTION RATIO vs FREQUENCY  
120  
110  
100  
90  
120  
100  
80  
0
CMRR  
+PSRR  
–30  
–60  
–90  
–120  
–150  
–180  
–210  
20log (AOL  
)
AOL  
80  
60  
–PSRR  
70  
40  
60  
50  
20  
40  
0
30  
–20  
20  
102  
103  
104  
105  
Frequency (Hz)  
106  
107  
108  
102  
103  
104  
105  
106  
107  
108  
109  
Frequency (Hz)  
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY  
G = +20V/V  
OUTPUT VOLTAGE AND CURRENT LIMITATIONS  
4
3
10  
1
VDIS  
ZO  
RL = 100Ω  
OPA847  
2
1
750Ω  
RL = 50Ω  
RL = 25Ω  
0
0.1  
39.2Ω  
–1  
–2  
–3  
–4  
0.01  
0.001  
–150  
–100  
–50  
0
50  
100  
150  
103  
104  
105  
106  
107  
108  
I
O (mA)  
Frequency (Hz)  
INVERTING OVERDRIVE RECOVERY  
NONINVERTING OVERDRIVE RECOVERY  
10  
8
0.25  
0.20  
0.15  
0.10  
0.05  
0
10  
0.5  
G = –40V/V  
G = 50Ω  
L = 100Ω  
Input  
Right Scale  
G = +20V/V  
L = 100Ω  
8
6
0.4  
R
R
R
6
0.3  
Input  
4
4
0.2  
Right Scale  
Output  
Left Scale  
2
2
0.1  
0
0
0
–2  
–4  
–6  
–8  
–10  
–0.05  
–0.10  
–0.15  
–0.20  
–0.25  
–2  
–4  
–6  
–8  
–10  
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
Output  
Left Scale  
See Figure 2  
See Figure 1  
Time (40ns/div)  
Time (40ns/div)  
OPA847  
SBOS251E  
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)  
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.  
PHOTODIODE TRANSIMPEDANCE  
FREQUENCY RESPONSE  
SETTLING TIME  
0.25  
0.20  
0.15  
0.10  
0.05  
0
89  
86  
83  
80  
77  
74  
71  
RF = 20kΩ  
CF Adjusted  
G = +20V/V  
RL = 100Ω  
O = 2V Step  
CD = 10pF  
[20log 20kΩ]  
V
CD = 20pF  
CD = 50pF  
CD = 100pF  
VO  
0.01µF  
OPA847  
20kΩ  
–0.05  
–0.10  
–0.15  
–0.20  
–0.25  
20kΩ  
IO  
CF  
CDIODE  
[CD]  
See Figure 1  
30 35  
0
5
10  
15  
20  
25  
40  
1
10  
Frequency (MHz)  
100  
Time (ns)  
TYPICAL DC DRIFT OVER TEMPERATURE  
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE  
100  
90  
80  
70  
60  
50  
20  
18  
16  
14  
12  
10  
0.2  
0.1  
25.0  
12.5  
0
Supply Current  
100 x IOS  
Sourcing Output Current  
VIO  
0
Sinking Output Current  
–0.1  
–0.2  
–12.5  
–25.0  
Ib  
–50  
–25  
0
25  
50  
75  
100  
125  
–50  
–25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
Ambient Temperature (°C)  
COMMON-MODE INPUT RANGE AND OUTPUT SWING  
vs SUPPLY VOLTAGE  
COMMON-MODE AND DIFFERENTIAL  
INPUT IMPEDANCE  
107  
106  
105  
104  
103  
102  
5
4
RL = 100Ω  
Common-Mode  
(2.3MΩ, DC)  
3
Positive Output  
2
1
Positive Input  
Negative Input  
0
Differential  
(2.7kΩ, DC)  
–1  
–2  
–3  
–4  
–5  
Negative Output  
102  
103  
104  
105  
106  
107  
108  
Frequency (Hz)  
Supply Voltage (±V)  
OPA847  
8
SBOS251E  
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TYPICAL CHARACTERISTICS: VS = ±5V  
TA = 25°C, GD = 40V/V, RG = 50Ω, and RL = 400Ω, unless otherwise noted.  
DIFFERENTIAL SMALL-SIGNAL  
FREQUENCY RESPONSE  
DIFFERENTIAL PERFORMANCE TEST CIRCUIT  
3
+5V  
DIS  
0
–3  
GD = +20V/V  
OPA847  
GD = +30V/V  
GD = +40V/V  
VO  
VI  
RF  
GD  
=
=
–6  
RG  
–5V  
RF  
RG  
50Ω  
GD = +50V/V  
–9  
RG  
50Ω  
VI  
RL  
VO  
–12  
–15  
–18  
RF  
RG = 50Ω  
O = 400mVPP  
RF Adjusted  
V
+5V  
OPA847  
10  
100  
1000  
Frequency (MHz)  
DIS  
–5V  
DIFFERENTIAL LARGE-SIGNAL  
FREQUENCY RESPONSE  
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE  
–55  
–60  
35  
32  
29  
26  
23  
GD = 40V/V  
VO = 4VPP  
F = 5MHz  
GD = 40V/V  
–65  
–70  
VO = 400mVPP  
–75  
2nd-Harmonic  
3rd-Harmonic  
VO = 5VPP  
–80  
–85  
VO = 8VPP  
–90  
–95  
–100  
–105  
–110  
1
10  
100  
Frequency (MHz)  
1000  
50  
100 150 200 250 300 350 400 450 500  
Resistance (Ω)  
DIFFERENTIAL DISTORTION vs FREQUENCY  
GD = 40V/V  
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE  
–65  
–75  
–75  
–80  
GD = 40V/V  
L = 400Ω  
F = 5MHz  
RL = 400Ω  
R
V
O = 4VPP  
–85  
2nd-Harmonic  
2nd-Harmonic  
–85  
–90  
–95  
–95  
3rd-Harmonic  
–100  
–105  
–110  
3rd-Harmonic  
–105  
–115  
1
10  
Frequency (MHz)  
100  
1
10  
Differential Output Voltage Swing (VPP  
)
OPA847  
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voltage noise for the op amp itself. This RG is suggested as a  
good starting point for design. Other values are certainly  
acceptable, if required by the design.  
APPLICATIONS INFORMATION  
WIDEBAND, NONINVERTING OPERATION  
The OPA847 provides a unique combination of a very low  
input voltage noise along with a very low distortion output  
stage to give one of the highest dynamic range op amps  
available. Its very high gain bandwidth product (GBP) can be  
used to either deliver high signal bandwidths at high gains, or  
to deliver very low distortion signals at moderate frequencies  
and lower gains. To achieve the full performance of the  
OPA847, careful attention to PC board layout and compo-  
nent selection is required, as discussed in the following  
sections of this data sheet.  
WIDEBAND, INVERTING GAIN OPERATION  
There can be significant benefits to operating the OPA847 as  
an inverting amplifier. This is particularly true when a matched  
input impedance is required. Figure 2 shows the inverting  
gain of a –40V/V circuit used as a starting point for the  
Typical Characteristics showing inverting mode performance.  
Driving this circuit from a 50Ω source, and constraining the gain  
resistor (RG) to equal 50Ω, gives both a signal bandwidth and  
a noise advantage. RG, in this case, acts as both the input  
termination resistor and the gain setting resistor for the circuit.  
Although the signal gain for the circuit of Figure 2 is double that  
for Figure 1, their noise gains are nearly equal when the 50Ω  
source resistor is included. This has the interesting effect of  
approximately doubling the equivalent GBP for the amplifier.  
This can be seen by observing that the gain of –40 bandwidth  
of 240MHz shown in the Typical Characteristics implies a gain  
bandwidth product of 9.6GHz, giving a far higher bandwidth at  
a gain of –40 than at a gain of +40. While the signal gain from  
RG to the output is –40, the noise gain for bandwidth setting  
purposes is 1 + RF/(2 • RG). In the case of a –40V/V gain, using  
an RG = RS = 50Ω gives a noise gain = 1 + 2kΩ/100Ω = 21. This  
inverting gain of –40V/V therefore has a frequency response  
that more closely matches the gain of a +20 frequency re-  
sponse.  
Figure 1 shows the noninverting gain of a +20V/V circuit used  
as the basis for most of the Typical Characteristics. Most of  
the curves are characterized using signal sources with a 50Ω  
driving impedance and with measurement equipment pre-  
senting a 50Ω load impedance. In Figure 1, the 50Ω shunt  
resistor at the VI terminal matches the source impedance of  
the test generator, while the 50Ω series resistor at the VO  
terminal provides a matching resistor for the measurement  
equipment load. Generally, data sheet voltage swing speci-  
fications are at the output pin (VO in Figure 1) while output  
power specifications are at the matched 50Ω load. The total  
100Ω load at the output combined with the 790Ω total  
feedback network load presents the OPA847 with an effec-  
tive output load of 89Ω for the circuit of Figure 1.  
Voltage-feedback op amps, unlike current-feedback designs,  
can use a wide range of resistor values to set their gain. The  
circuit of Figure 1, and the specifications at other gains, use an  
RG set to 39.2Ω and RF adjusted to get the desired gain. Using  
this guideline ensures that the noise added at the output due  
to the Johnson noise of the resistors does not significantly  
increase the total over that due to the 0.85nV/√Hz input  
If the signal source is actually the low impedance output of  
another amplifier, RG should be increased to be greater than  
the minimum value allowed at the output for that amplifier  
and RF adjusted to get the desired gain. It is critical for stable  
operation of the OPA847 that this driving amplifier show a  
very low output impedance through frequencies exceeding  
the expected closed-loop bandwidth for the OPA847.  
+5V  
+VS  
+5V  
+VS  
0.1µF  
6.8µF  
+
+
0.1µF  
6.8µF  
50Ω Source  
VDIS  
50Ω Load  
VDIS  
50Ω Load  
50Ω  
VI  
VO  
VO  
50Ω  
50Ω  
OPA847  
0.01µF  
95.3Ω  
OPA847  
RF  
750Ω  
RG  
50Ω  
RF  
2kΩ  
50Ω Source  
VI  
RG  
39.2Ω  
0.1µF  
6.8µF  
6.8µF  
0.1µF  
+
+
–VS  
–5V  
–VS  
–5V  
FIGURE 1. Noninverting G = +20 Specification and Test Circuit.  
FIGURE 2. Noninverting G = –40 Specification and Test Circuit.  
OPA847  
10  
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WIDEBAND, HIGH SENSITIVITY,  
TRANSIMPEDANCE DESIGN  
Equation 2 gives the approximate –3dB bandwidth that  
results if CF is set using Equation 1.  
The high GBP and low input voltage and current noise for the  
OPA847 make it an ideal wideband transimpedance ampli-  
fier for low to moderate transimpedance gains. Very high  
transimpedance gains (> 100kΩ) will benefit from the low  
input noise current of a JFET input op amp such as the  
OPA657. Unity-gain stability in the op amp is not required for  
application as a transimpedance amplifier. Figure 3 shows  
one possible transimpedance design example that would be  
particularly suitable for the 155Mbit data rate of an OC-3  
receiver. Designs that require high bandwidth from a large  
area detector with relatively low transimpedance gain will  
benefit from the low input voltage noise for the OPA847. The  
amplifier’s input voltage noise is peaked up over frequency  
by the diode source capacitance, and can (in many cases)  
become the limiting factor to input sensitivity. The key ele-  
ments to the design are the expected diode capacitance (CD)  
with the reverse bias voltage (–VB) applied, the desired  
transimpedance gain (RF), and the GBP for the OPA847  
(3900MHz). With these three variables set (including the  
parasitic input capacitance for the OPA847 added to CD), the  
feedback capacitor value (CF) can be set to control the  
frequency response.  
GBP  
f−3dB  
=
Hz  
(
)
(2)  
2πRF CD  
The example of Figure 3 gives approximately 104MHz flat  
bandwidth using the 0.18pF feedback compensation capaci-  
tor. This bandwidth easily supports an OC-3 receiver with  
exceptional sensitivity.  
If the total output noise is bandlimited to a frequency less  
than the feedback pole frequency, a very simple expression  
for the equivalent input noise current is shown as Equation 3.  
(3)  
2
2
E 2πC F  
(
)
4kT  
RF  
N
D
2
iEQ  
=
iN  
+
+
3
where:  
iEQ = Equivalent input noise current if the output noise is  
bandlimited to f < 1/2πRFCF  
iN = Input current noise for the op amp inverting input  
eN = Input voltage noise for the op amp  
CD = Total Inverting Node Capacitance  
f = Bandlimiting frequency in Hz (usually a post filter prior  
to further signal processing)  
+5V  
Evaluating this expression up to the feedback pole frequency  
at 74MHz for the circuit of Figure 3 gives an equivalent input  
noise current of 3.0pA/√Hz. This is slightly higher than the  
2.5pA/√Hz input current noise for the op amp. This total  
equivalent input current noise is slightly increased by the last  
term in the equivalent input noise expression. It is essential  
in this case to use a low-voltage noise op amp. For example,  
if a slightly higher input noise voltage, but otherwise identical,  
op amp were used instead of the OPA847 in this application  
(say 2.0nV/√Hz), the total input referred current noise would  
increase to 3.7pA/√Hz. Low input voltage noise is required  
for the best sensitivity in these wideband transimpedance  
applications. This is often unspecified for dedicated transim-  
pedance amplifiers with a total output noise for a specified  
source capacitance given instead. It is the relatively high  
input voltage noise for those components that cause higher  
than expected output noise if the source capacitance is  
higher than specified.  
Power-supply  
decoupling not shown.  
100pF  
0.1µF  
12kΩ  
OPA847  
VDIS  
RF  
12kΩ  
–5V  
λ
CF  
1pF  
Photodiode  
0.18pF  
–VB  
FIGURE 3. Wideband, High Sensitivity, OC-3 Transimpedance  
Amplifier.  
To achieve a maximally flat 2nd-order Butterworth frequency  
response, set the feedback pole as shown in Equation 1.  
The output DC error for the circuit of Figure 3 is minimized by  
including a 12kΩ to ground on the noninverting input. This  
reduces the contribution of input bias current errors (for total  
output offset voltage) to the offset current times the feedback  
resistor. To minimize the output noise contribution of this  
resistor, 0.01µF and 100pF capacitors are included in paral-  
lel. Worst-case output DC error for the circuit of Figure 3 at  
25°C is:  
1
GBP  
=
(1)  
2πRFCF  
4πRFCD  
Adding the common-mode and differential mode input ca-  
pacitance (1.2 + 2.5)pF to the 1pF diode source capacitance  
of Figure 3, and targeting a 12kΩ transimpedance gain using  
the 3900MHz GBP for the OPA847 requires a feedback pole  
set to 74MHz to get a nominal Butterworth frequency re-  
sponse design. This requires a total feedback capacitance of  
0.18pF. That total is shown in Figure 3, but recall that typical  
surface-mount resistors have a parasitic capacitance of 0.2pF,  
leaving no external capacitor required for this design.  
VOS = ±0.5mV (input offset voltage) ± 0.6µA (input offset  
current) • 12kΩ = ±7.2mV  
Worst-case output offset DC drift (over the 0°C to 70°C span) is:  
dVOS/dT = ±1.5µV/°C (input offset drift) ± 2nA/°C (input  
offset current drift) • 12kΩ = ±21.5µV/°C.  
OPA847  
SBOS251E  
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Even with bias current cancellation, the output DC errors are  
dominated in this example by the offset current term. Im-  
proved output DC precision and drift are possible, particularly  
at higher transimpedance gains, using the JFET input  
OPA657. The JFET input removes the input bias current  
from the error equation (eliminating the need for the resistor  
to ground on the noninverting input), leaving only the input  
offset voltage and drift as an output DC error term.  
Considering only the noise gain (which is the same as the  
noninverting signal gain) for the circuit of Figure 5, the low-  
frequency noise gain (NG1) is set by the resistor ratio, while  
the high-frequency noise gain (NG2) is set by the capacitor  
ratio. The capacitor values set both the transition frequencies  
and the high-frequency noise gain. If the high-frequency  
noise gain, determined by NG2 = 1 + CS/CF, is set to a value  
greater than the recommended minimum stable gain for the  
op amp, and the noise gain pole (set by 1/RFCF) is placed  
correctly, a very well controlled 2nd-order low-pass fre-  
Included in the Typical Characteristics are transimpedance  
frequency response curves for a fixed 20kΩ gain over vari-  
ous detector diode capacitance settings. These curves are  
repeated in Figure 4, along with the test circuit. As the  
photodiode capacitance changes, the feedback capacitor  
must change to maintain a stable and flat frequency re-  
sponse. Using Equation 1, CF is adjusted to give the  
Butterworth frequency responses shown in Figure 4.  
+5V  
VDIS  
VO  
OPA847  
RG  
200Ω  
RF  
850Ω  
PHOTODIODE TRANSIMPEDANCE  
FREQUENCY RESPONSE  
VI  
89  
RF = 20kΩ  
CD = 10pF  
CS  
39pF  
CF  
1.7pF  
CF Adjusted  
[20 log(20kΩ)]  
86  
83  
80  
77  
74  
71  
CD = 20pF  
CD = 50pF  
–5V  
CD = 100pF  
FIGURE 5. Broadband, Low-Inverting Gain External  
Compensation.  
VO  
0.01µF  
OPA847  
20kΩ  
20kΩ  
IO  
quency response results.  
CF  
CD  
To choose the values for both CS and CF, two parameters and  
only three equations need to be solved. The first parameter is  
the target high-frequency noise gain (NG2), which should be  
greater than the minimum stable gain for the OPA847. Here, a  
target of NG2 = 24 is used. The second parameter is the desired  
low-frequency signal gain, which also sets the low-frequency  
noise gain (NG1). To simplify this discussion, we will target a  
maximally flat, 2nd-order, low-pass Butterworth frequency re-  
sponse (Q = 0.707). The signal gain shown in Figure 5 sets the  
low-frequency noise gain to NG1 = 1 + RF/RG (= 5.25 in this  
example). Then, using only these two gains and the GBP for the  
OPA847 (3900MHz), the key frequency in the compensation is  
set by Equation 4.  
1
10  
Frequency (MHz)  
100  
FIGURE 4. Transimpedance Bandwidth vs CD.  
LOW-GAIN COMPENSATION FOR IMPROVED SFDR  
Where a low gain is desired, and inverting operation is  
acceptable, a new external compensation technique can be  
used to retain the full slew rate and noise benefits of the  
OPA847, while giving increased loop gain and the associ-  
ated distortion improvements offered by a non-unity-gain  
stable op amp. This technique shapes the loop gain for good  
stability, while giving an easily controlled 2nd-order low-pass  
frequency response. This technique is used for the circuit on  
the front page of this data sheet in a differential configuration  
to achieve extremely low distortion through high frequencies  
(< –90dBc through 30MHz). The amplifier portion of this  
circuit is set up for a differential gain of 8.5V/V from a  
differential input signal to the output. Using the input trans-  
former shown improves the noise figure and translates from  
a single-ended to a differential signal. If the source is differ-  
ential already, it can be fed directly into the gain setting  
resistors. To set the compensation capacitors (CS and CF),  
consider the half circuit of Figure 5, where the 50Ω source is  
reflected through the 1:2 transformer, then cut in half, and  
grounded to give a total impedance to the AC ground for the  
circuit on the front page equal to 200Ω.  
GBP  
NG21  
NG1  
NG2  
NG1  
NG2  
ZO  
=
1−  
− 1− 2  
(4)  
Physically, this ZO (4.4MHz for the values shown above) is  
set by 1/(2πRF(CF + CS)) and is the frequency at which the  
rising portion of the noise gain would intersect the unity gain  
if projected back to a 0dB gain. The actual zero in the noise  
gain occurs at NG1 • ZO and the pole in the noise gain occurs  
at NG2 • ZO. That pole is physically set by 1/(RFCF). Since  
GBP is expressed in Hz, multiply ZO by 2π and use to get CF  
by solving Equation 5.  
1
CF  
=
= 1.76pF  
(
)
(5)  
2πRFZONG2  
OPA847  
12  
SBOS251E  
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Finally, since CS and CF set the high-frequency noise gain,  
determine CS using Equation 6 (solving for CS by using NG2 = 24):  
LOW GAIN INVERTING BANDWIDTH  
1
0
CS = NG − 1C  
(6)  
(
)
2
F
G = –8  
which gives CS = 40.6pF.  
–1  
–2  
–3  
–4  
–5  
–6  
–7  
–8  
–9  
VO = 0.2VPP  
Both of these calculated values have been reduced slightly  
in Figure 5 to account for parasitics. The resulting closed-  
loop bandwidth is approximately equal to Equation 7.  
G = –1  
G = –2  
(7)  
f–3dB  
ZO • GBP  
G = –4  
For the values shown in Figure 5, f–3dB is approximately  
131MHz. This is less than that predicted by simply dividing  
the GBP product by NG1. The compensation network controls  
the bandwidth to a lower value, while providing the full slew  
rate at the output and an exceptional distortion performance  
due to increased loop gain at frequencies below NG1 • ZO.  
1
10  
100  
1000  
Frequency (MHz)  
+5V  
Using this low-gain inverting compensation, along with the  
differential structure for the circuit shown on the front page of  
this data sheet, gives a significant reduction in harmonic  
distortion. The measured distortion at 2VPP output does not  
rise above –95dB until frequencies > 20MHz are applied.  
VDIS  
VO  
OPA847  
RF  
750Ω  
The Typical Characteristics show the exceptional bandwidth  
control possible using this technique at low inverting gains.  
Figure 6 repeats the measured results with the test circuit shown.  
RG  
–5V  
VI  
0Ω Source  
CS  
CF  
The compensation capacitors, CS and CF, are set by targeting  
a high-frequency noise gain of 21 and using equations 4 through  
6. This approach allows relatively low inverting gain applications  
to use the full slew rate and low input noise of the OPA847.  
FIGURE 6. Low-Gain Inverting Performance.  
figures in the 10dB range (for a matched 50Ω input) are  
easily achieved with just the OPA847, Figure 7 illustrates a  
technique to reduce the noise figure even further, while  
providing a broadband, high-gain HF amplifier stage using  
two stages of the OPA847.  
LOW-NOISE FIGURE,  
HIGH DYNAMIC RANGE AMPLIFIER  
The low input noise voltage of the OPA847 and its very high  
2-tone, 3rd-order intermodulation intercept can be used to  
good advantage as a fixed-gain amplifier. While input noise  
6.19kΩ  
+5V  
Input match  
set by this  
feedback path  
PO  
OPA847  
> 55dBm  
intercept  
to 30MHz  
+5V  
–5V  
50Ω Source  
750Ω  
1.5kΩ  
1:2  
PI  
OPA847  
200Ω  
1.6pF  
4.3dB  
Noise  
Figure  
–5V  
46pF  
10pF  
420Ω  
PO  
PI  
Overall Gain  
= 35.6dB  
30.1Ω  
FIGURE 7. Very High Dynamic Range HF Amplifier.  
OPA847  
SBOS251E  
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This circuit uses two stages of forward gain with an overall  
feedback loop to set the input impedance match. The input  
transformer provides both a noiseless voltage gain and a  
signal inversion to retain an overall noninverting signal path  
from PI to PO. The second amplifier stage is inverting to  
provide the correct feedback polarity through the 6.19kΩ  
resistor. To achieve a 50Ω input match at the primary of the  
1:2 transformer, the secondary must see a 200Ω load imped-  
ance. At higher frequencies, the match is provided by the  
200Ω resistor in series with 10pF. The low-noise figure  
(4.3dB) for this circuit is achieved by using the transformer,  
the low-voltage noise OPA847, and the input match set by  
the feedback at lower frequencies intended for this HF  
design. The 1st-stage amplifier provides a gain of +15V/V.  
The very high SFDR is provided by operating the output  
stage at a low signal gain of –2 and using the inverting  
compensation technique to shape the noise gain to hold it  
stable. This 2nd-stage compensation is set to intentionally  
bandlimit the overall response to approximately 100MHz. For  
output loads > 400Ω, this circuit can give a 2-tone SFDR that  
exceeds 90dB through 30MHz. In narrowband applications,  
the 3rd-order intercept exceeds 55dBm. Besides offering a  
very high dynamic range, this circuit improves on standard  
HF amplifiers by offering a precisely controlled gain and a  
very flexible output interface capability.  
+5V  
VI  
VDIS  
50Ω  
50Ω  
R1  
50Ω  
VO  
OPA847  
–5V  
RF  
750Ω  
RG  
66.5Ω  
FIGURE 8. Low Noninverting Gain Flatness Trim.  
The effect of this noninverting gain flatness tune is shown in  
Figure 9. At an NG of 12, R1 is removed and only RF and RG  
are present in Figure 8. The peaking is typically 4.5dB, as  
shown in the small-signal frequency response curves versus  
gain curves at this setting. As R1 is decreased, the operating  
noise gain (NG) increases, reducing the peaking and band-  
width until the nominal design point of +20 noise gain gives  
a non-peaked response.  
NONINVERTING GAIN FLATNESS TUNE  
0.5  
NONINVERTING GAIN FLATNESS COMPENSATION  
V
O = 200mVPP  
NG = 12  
NG = 14  
NG = 16  
Decreasing the operating gain from the nominal design point of  
+20 decreases the phase margin. This increases Q for the  
closed-loop poles, peaks up the frequency response, and  
extends the bandwidth. A peaked frequency response shows  
overshoot and ringing in the pulse response, as well as higher  
integrated output noise. When operating the OPA847 at a  
noninverting gain < +12V/V, increased peaking and possible  
sustained oscillations may result. However, operation at low  
gains may be desirable to take advantage of the higher slew  
rate and exceptional DC precision of the OPA847. Numerous  
external compensation techniques are suggested for operating  
a high-gain op amp at low gains. Most of these give zero/pole  
pairs in the closed-loop response that cause long term settling  
tails in the pulse response and/or phase nonlinearity in the  
frequency response.  
0.4  
0.3  
AV = +12V/V  
NG = Noise Gain  
0.2  
0.1  
0
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
NG = 18  
NG = 20  
1
10  
100  
Frequency (MHz)  
1000  
FIGURE 9. Frequency Response Flatness with External  
Tuning Resistor.  
Figure 8 shows a resistor-based compensation technique  
that allows the flatness at low noninverting signal gains to be  
controlled separately from the signal gain. This approach  
retains the full slew rate to the output but gives up some of  
the low-noise benefit of the OPA847. Including the effect of  
the total source impedance (25Ω in Figure 8), tuning resistor  
R1 can be set using Equation 8.  
DIFFERENTIAL OPERATION  
Operating two OPA847 amplifiers in a differential inverting  
configuration can further suppress even-order harmonic terms.  
The Typical Characteristics show measured performance for  
this condition. These measurements were done at the relatively  
high gain of 40V/V. Even lower distortion is possible operating  
at lower gains using the external inverting compensation tech-  
niques, as discussed previously. For the distortion data pre-  
sented in Figure 10, the output swing is increased to 4VPP into  
400Ω to allow direct comparison to the single-channel data at  
2VPP into 200Ω. Comparing the 2nd- and 3rd-harmonics at  
20MHz in Figure 10 to the gain of +20, 2VPP, 200Ω data, shows  
the 2nd-harmonic is reduced to –76dBc (from –67dBc) and the  
3rd-harmonic is reduced from –80dBc to –85dBc. Using the two  
RF + RSAV  
R1 =  
(8)  
NG − AV  
where:  
AV = desired signal gain (+12V/V in Figure 8)  
NG = target noise gain (adjusted in Figure 9)  
RS = total source impedance  
OPA847  
14  
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supply of +5V and up to a single supply of +12V. If shutdown  
is desired for single-supply operation, it is important to realize  
that the shutdown pin is referenced from the positive supply  
pin. Open collector (drain) interfaces are suggested for  
single-supply operation above +5V.  
–65  
–75  
GD = 40V/V  
L = 400Ω  
O = 4VPP  
R
V
2nd-Harmonic  
–85  
DESIGN-IN TOOLS  
–95  
DEMONSTRATION FIXTURES  
3rd-Harmonic  
–105  
–115  
Two printed circuit boards (PCBs) are available to assist in  
the initial evaluation of circuit performance using the OPA847  
in its two package options. Both of these are offered free  
of charge as unpopulated PCBs, delivered with a user’s  
guide. The summary information for these fixtures is shown  
in Table I.  
1
10  
Frequency (MHz)  
100  
FIGURE 10. Differential Distortion vs Frequency.  
ORDERING  
NUMBER  
LITERATURE  
NUMBER  
amplifiers in this configuration has significantly reduced the  
2nd-harmonic, even after doubling the output voltage swing (to  
4VPP) and the gain (to 40V/V).  
PRODUCT  
PACKAGE  
OPA847ID  
SO-8  
DEM-OPA-SO-1B  
DEM-OPA-SOT-1B  
SBOU026  
SBOU027  
OPA847IDBV  
SOT23-6  
TABLE I. Demonstration Fixtures by Package.  
SINGLE-SUPPLY OPERATION  
The OPA847 can be operated from a single power supply if  
system constraints require it. Operation from a single +5V to  
+12V supply is possible with minimal change in AC perfor-  
mance. The Typical Characteristics show the input and  
output voltage ranges for a bipolar supply range from ±2.5V  
to ±6.0V. The Common-Mode Input Range and Output Swing  
vs Supply Voltage curve shows that the required headroom  
on both the input and output pins remains at approximately  
1.5V over this entire range. On a single +5V supply, for  
instance, this means the noninverting input should remain  
centered at +2.5V ± 1V, as should the output pin. Figure 11  
shows an example application biasing the noninverting input  
at mid-supply and running an AC-coupled input to the invert-  
ing gain path. Since the gain resistor is blocked off for DC,  
the bias point on the noninverting input appears at the output,  
centering up the output as well as on the power supply. The  
OPA847 can support this mode of operation down to a single  
The demonstration fixtures can be requested at the Texas  
Instruments web site (www.ti.com) through the OPA847  
product folder.  
MACROMODELS AND APPLICATIONS SUPPORT  
Computer simulation of circuit performance using SPICE is  
often a quick way to analyze the performance of the OPA847  
in its intended application. This is particularly true for video  
and RF amplifier circuits where parasitic capacitance and  
inductance can play a major role in circuit performance. A  
SPICE model for the OPA847 is available through the TI web  
site (www.ti.com). These models do a good job of predicting  
small-signal AC and transient performance under a wide  
variety of operating conditions. They do not do as well in  
predicting the harmonic distortion characteristics. These  
models do not attempt to distinguish between the package  
types in their small-signal AC performance.  
+VCC  
OPERATING SUGGESTIONS  
SETTING RESISTOR VALUES TO MINIMIZE NOISE  
+5V  
+12V  
Range  
2RF  
2RF  
The OPA847 provides a very low input noise voltage while  
requiring a low 18.1mA of quiescent current. To take full  
advantage of this low input noise, careful attention to the other  
possible noise contributors is required. See Figure 12 for the  
op amp noise analysis model with all the noise terms included.  
In this model, all the noise terms are taken to be noise voltage  
Power-supply decoupling  
not shown.  
VCC  
RF  
VO  
=
OPA847  
– VI  
0.01µF  
2
RG  
VDIS  
or current density terms in either nV/√Hz or pA/√Hz  
.
RG  
RF  
The total output spot noise voltage is computed as the  
square root of the squared contributing terms to the output  
noise power. This computation adds all the contributing noise  
powers at the output by superposition, then takes the square  
VI  
FIGURE 11. Single-Supply Inverting Amplifier.  
OPA847  
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practice, this only holds true when the phase margin ap-  
proaches 90°, as it does in high-gain configurations. At low  
gains (increased feedback factors), most high-speed ampli-  
fiers exhibit a more complex response with lower phase  
margin. The OPA847 is compensated to give a maximally flat  
2nd-order Butterworth closed-loop response at a noninverting  
gain of +20 (see Figure 1). This results in a typical gain of  
+20 bandwidth of 350MHz, far exceeding that predicted by  
dividing the 3900MHz GBP by 20. Increasing the gain causes  
the phase margin to approach 90° and the bandwidth to more  
closely approach the predicted value of (GBP/NG). At a gain  
of +50, the OPA847 very nearly matches the 78MHz band-  
width predicted using the simple formula and the typical GBP  
of 3900MHz.  
ENI  
EO  
OPA847  
RS  
IBN  
ERS  
RF  
√4kTRS  
√4kTRF  
IBI  
RG  
4kT  
RG  
4kT = 1.6E – 20J  
at 290°K  
FIGURE 12. Op Amp Noise Analysis Model.  
Inverting operation offers some interesting opportunities to  
increase the available GBP. When the source impedance is  
matched by the gain resistor (see Figure 2), the signal gain  
is (1 + RF/RG), while the noise gain for bandwidth purposes  
is (1 + RF/2RG). This cuts the noise gain almost in half,  
increasing the minimum operating gain for inverting opera-  
tion under these condition to –22 and the equivalent gain  
bandwidth product to > 7.8GHz.  
root to get back to a spot noise voltage. Equation 9 shows the  
general form for this output noise voltage using the terms  
illustrated in Figure 11.  
(9)  
2
2
EO  
=
E2 + IBNRS + 4kTRS NG2 + I R  
+ 4kTRFNG  
(
)
(
)
(
)
NI  
BI  
F
Dividing this expression by the noise gain (NG = 1 + RF/RG)  
gives the equivalent input-referred spot noise voltage at the  
noninverting input, as shown in Equation 10.  
DRIVING CAPACITIVE LOADS  
One of the most demanding, and yet very common, load  
conditions for an op amp is capacitive loading. Often, the  
capacitive load is the input of an ADC, including additional  
external capacitance that may be recommended to improve  
ADC linearity. A high-speed, high open-loop gain amplifier  
like the OPA847 can be very susceptible to decreased  
stability and may give closed-loop response peaking when a  
capacitive load is placed directly on the output pin. When the  
amplifier’s open-loop output resistance is considered, this  
capacitive load introduces an additional pole in the signal  
path that can decrease the phase margin. Several external  
solutions to this problem are suggested. When the primary  
considerations are frequency response flatness, pulse re-  
sponse fidelity, and/or distortion, the simplest and most  
effective solution is to isolate the capacitive load from the  
feedback loop by inserting a series isolation resistor between  
the amplifier output and the capacitive load. This does not  
eliminate the pole from the loop response, but rather shifts it  
and adds a zero at a higher frequency. The additional zero  
acts to cancel the phase lag from the capacitive load pole,  
thus increasing the phase margin and improving stability.  
(10)  
2
IBIRF  
NG  
4kTRF  
NG  
2
EN  
=
EN2I + IBNRS + 4kTRS  
+
+
(
)
Putting high resistor values into Equation 10 can quickly  
dominate the total equivalent input-referred noise. A 45Ω  
source impedance on the noninverting input adds a Johnson  
voltage noise term equal to the amplifier’s voltage noise by  
itself. As a simplifying constraint, set RG = RS in Equation 10  
and assume an RS/2 source impedance at the noninverting  
input, where RS is the signal source impedance and another  
matching RS to ground is at the noninverting input. This  
results in Equation 11, where NG > 12 is assumed to further  
simplify the expression.  
5
4
3RS  
2
EN = EN2I  
+
I R 2 + 4kT  
B
S
(
)
(11)  
Evaluating this expression for RS = 50Ω gives a total equiva-  
lent input noise of 1.4nV/√Hz. Note that at these higher  
gains, the simplified input referred spot noise expression of  
Equation 11 does not include the gain. This is a good  
approximation for NG > 12, as is typically required by stability  
considerations.  
The Typical Characteristics help the designer pick a recom-  
mended RS versus capacitive load. The resulting frequency  
response curves show a flat response for several selected  
capacitive loads and recommended RS combinations. Para-  
sitic capacitive loads greater than 2pF can begin to degrade  
the performance of the OPA847. Long PCB traces, un-  
matched cables, and connections to multiple devices can  
easily cause this value to be exceeded. Always consider this  
effect carefully and add the recommended series resistor as  
close as possible to the OPA847 output pin (see the Board  
Layout section).  
FREQUENCY RESPONSE CONTROL  
Voltage-feedback op amps exhibit decreasing closed-loop  
bandwidth as the signal gain is increased. In theory, this  
relationship is described by the Gain Bandwidth Product  
(GBP) shown in the Electrical Characteristics. Ideally, divid-  
ing GBP by the noninverting signal gain (also called the  
Noise Gain, or NG) predicts the closed-loop bandwidth. In  
OPA847  
16  
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The criterion for setting the RS resistor is a maximum band-  
width, flat frequency response at the load. For the OPA847  
operating in a gain of +20, the frequency response at the  
output pin is very flat to begin with, allowing relatively small  
values of RS to be used for low capacitive loads. As the signal  
gain is increased, the unloaded phase margin also increases.  
Driving capacitive loads at higher gains requires lower RS  
values than those shown for a gain of +20.  
If the full envelope of the two frequencies needs to be 2VPP,  
this requires each tone to be 4dBm. The 3rd-order  
intermodulation spurious tones will then be 2(34 – 4) = 60dBc  
below the test-tone power level (–56dBm). If this same 2VPP  
2-tone envelope is delivered directly into the input of an ADC  
without the matching loss or the loading of the 50Ω network,  
the intercept would increase to at least 40dBm.  
With the same signal and gain conditions, but now driving  
directly into a light load, the spurious tones will then be at  
least 2(40 – 4) = 72dBc below the 4dBm test-tone power  
levels centered on 30MHz. Tests have shown that they are  
in fact much lower due to the lighter loading presented by  
most ADCs.  
DISTORTION PERFORMANCE  
The OPA847 is capable of delivering an exceptionally low  
distortion signal at high frequencies over a wide range of  
gains. The distortion plots in the Typical Characteristics show  
the typical distortion under a wide variety of conditions. Most  
of these plots are limited to a 110dB dynamic range. The  
OPA847’s distortion driving a 200Ω load does not rise above  
–90dBc until either the signal level exceeds 2.0VPP and/or  
the fundamental frequency exceeds 5MHz. Distortion in the  
audio band is < –130dBc.  
DC ACCURACY AND OFFSET CONTROL  
The OPA847 can provide excellent DC signal accuracy due  
to its high open-loop gain, high common-mode rejection, high  
power-supply rejection, and low input offset voltage and bias  
current offset errors. To take full advantage of its low ±0.5mV  
input offset voltage, careful attention to the input bias current  
cancellation is also required. The low-noise input stage for  
the OPA847 has a relatively high input bias current (19µA  
typical into the pins), but with a very close match between the  
two input currents—typically ±100nA input offset current.  
Figures 13 and 14 show typical distributions of input offset  
voltage and current for the OPA847.  
Generally, until the fundamental signal reaches very high  
frequencies or powers, the 2nd-harmonic dominates the dis-  
tortion with a negligible 3rd-harmonic component. Focusing  
then on the 2nd-harmonic, increasing the load impedance  
improves distortion directly. Remember that the total load  
includes the feedback network—in the noninverting configura-  
tion this is the sum of RF + RG, while in the inverting  
configuration this is only RF (see Figure 2). Increasing the  
output voltage swing increases harmonic distortion directly. A  
6dB increase in output swing generally increases the 2nd-  
harmonic 12dB and the 3rd-harmonic 18dB. Increasing the  
signal gain also increases the 2nd-harmonic distortion. Finally,  
the distortion increases as the fundamental frequency in-  
creases due to the rolloff in the loop gain with frequency.  
Conversely, the distortion improves going to lower frequencies  
down to the dominant open-loop pole at approximately 80kHz.  
1200  
Mean = 48µV  
Standard Deviation = 110µV  
1000  
Total Count = 4040  
800  
600  
400  
200  
0
The OPA847 has an extremely low 3rd-order harmonic  
distortion. This also gives a high 2-tone 3rd-order  
intermodulation intercept, as shown in the Typical Character-  
istics. This intercept curve is defined at the 50Ω load when  
driven through a 50Ω matching resistor to allow direct com-  
parisons to RF devices. This matching network attenuates  
the voltage swing from the output pin to the load by 6dB. If  
the OPA847 drives directly into the input of a high-imped-  
ance device, such as an ADC, this 6dB attenuation is not  
taken. Under these conditions, the intercept as reported in  
the Typical Characteristics increases by a minimum of 6dBm.  
The intercept is used to predict the intermodulation spurious  
power levels for two closely spaced frequencies. If the two  
test frequencies, f1 and f2, are specified in terms of average  
and delta frequency, fO = (f1 + f2)/2 and ∆f = f2 – f1 /2, the  
two 3rd-order, close-in spurious tones appear at fO ± 3 • ∆f.  
The difference between the two equal test-tone power levels  
and these intermodulation spurious power levels is given by  
∆dBc = 2(IM3 – PO), where IM3 is the intercept taken from  
the Typical Characteristics and PO is the power level in dBm  
at the 50Ω load for one of the two closely spaced test  
frequencies. For instance, at 30MHz, the OPA847 at a gain  
of +20 has an intercept of 34dBm at a matched 50Ω load.  
µV  
FIGURE 13. Input Offset Voltage Distribution in µV.  
900  
Mean = 50nA  
Standard Deviation = 120nA  
Total Count = 4040  
800  
700  
600  
500  
400  
300  
200  
100  
0
nA  
FIGURE 14. Input Offset Current Distribution in nA.  
OPA847  
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The total output offset voltage can be considerably reduced  
by matching the source impedances looking out of the two  
inputs. For example, one way to add bias current cancella-  
tion to the circuit of Figure 1 is to insert a 12.1Ω series  
resistor into the noninverting input from the 50Ω terminating  
resistor. When the 50Ω source resistor is DC-coupled, this  
increases the source impedance for the noninverting input  
bias current to 37.1Ω. Since this is now equal to the imped-  
ance looking out of the inverting input (RF || RG) for Figure 1,  
the circuit cancels the gains for the bias currents to the  
output, leaving only the offset current times the feedback  
resistor as a residual DC error term at the output. Using the  
750Ω feedback resistor, this output error is now less than  
±0.85µA • 750Ω = ±640µV over the full temperature range for  
the circuit of Figure 1, with a 12.1Ω resistor added as  
described. The output DC offset is then dominated by the  
input offset voltage multiplied by the signal gain. For the  
circuit of Figure 1, this is a worst-case output DC offset of  
±0.6mV • 20 = ±12mV over the full temperature range.  
In this case, the input is brought into an inverting gain resistor  
with the DC adjustment as an additional current summed into  
the inverting node. The resistor values setting this offset  
adjustment are much larger than the signal path resistors.  
This ensures that this adjustment has minimal impact on the  
loop gain and, hence, the frequency response.  
POWER SHUTDOWN OPERATION  
The OPA847 provides an optional power shutdown feature  
that can be used to reduce system power. If the VDIS control  
pin is left unconnected, the OPA847 operates normally. This  
shutdown is intended only as a power saving feature. For-  
ward path isolation is very good for small signals. Large  
signal isolation is not ensured. Using this feature to multiplex  
two or more outputs together is not recommended. Large  
signals applied to the shutdown output stages can turn on  
parasitic devices, degrading signal linearity for the desired  
channel.  
Turn-on time is very quick from the shutdown condition,  
typically < 60ns. Turn-off time is strongly dependent on the  
external circuit configuration, but is typically 200ns for the  
circuit of Figure 1. Using the OPA847 with higher external  
resistor values, such has high-gain transimpedance circuits,  
slows the shutdown time since the time constants for the  
internal nodes to discharge are longer.  
A fine-scale output offset null, or DC operating point adjust-  
ment, is sometimes required. Numerous techniques are  
available for introducing a DC offset control into an op amp  
circuit. Most of these techniques eventually reduce to setting  
up a DC current through the feedback resistor. One key  
consideration to selecting a technique is to ensure that it has  
a minimal impact on the desired signal path frequency  
response. If the signal path is intended to be noninverting,  
the offset control is best applied as an inverting summing  
signal to avoid interaction with the signal source. If the signal  
path is intended to be inverting, applying the offset control to  
the noninverting input can be considered. For a DC-coupled  
inverting input signal, this DC offset signal sets up a DC  
current back into the source that must be considered. An  
offset adjustment placed on the inverting op amp input can  
also change the noise gain and frequency response flatness.  
Figure 15 shows one example of an offset adjustment for a  
DC-coupled signal path that has minimum impact on the  
signal frequency response.  
To shutdown, the control pin must be asserted low. This logic  
control is referenced to the positive supply, as shown in the  
simplified circuit of Figure 16.  
+VS  
8kΩ  
Q1  
+5V  
VCC  
Power-supply decoupling  
not shown.  
17kΩ  
120kΩ  
VO  
OPA847  
0.1µF  
48Ω  
IS  
VDIS  
Control  
–VS  
VEE  
–5V  
FIGURE 16. Simplified Shutdown Control Circuit.  
+5V  
RG  
50Ω  
RF  
1kΩ  
In normal operation, base current to Q1 is provided through  
the 120kΩ resistor, while the emitter current through the 8kΩ  
resistor sets up a voltage drop that is inadequate to turn on  
the two diodes in Q1’s emitter. As VDIS is pulled low,  
additional current is pulled through the 8kΩ resistor, even-  
tually turning on these two diodes (≈ 180µA). At this point,  
any further current pulled out of VDIS goes through those  
diodes holding the emitter-base voltage of Q1 at approxi-  
mately 0V. This shuts off the collector current out of Q1,  
turning the amplifier off. The supply current in the shutdown  
mode is only that required to operate the circuit of Figure 16.  
VI  
5kΩ  
5kΩ  
±200mV Output Adjustment  
20kΩ  
100Ω  
0.1µF  
V
RF  
O = –  
VI  
= –20V/V  
RG  
–5V  
FIGURE 15. DC-Coupled, Inverting Gain of –20 with Output  
Offset Adjustment.  
OPA847  
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The shutdown feature for the OPA847 is a positive-supply  
referenced, current-controlled interface. Open-collector (or drain)  
interfaces are most effective, as long as the controlling logic  
can sustain the resulting voltage (in open mode) that appears  
at the VDIS pin. The VDIS pin voltage is one diode below the  
positive supply voltage applied to the OPA847 if the logic  
voltage is open. For voltage output logic interfaces, the on/off  
voltage levels described in the Electrical Characteristics apply  
only for a +5V supply. An open-drain interface is recommended  
for a shutdown operation using a higher positive supply and/or  
logic families with inadequate high-level voltage swings.  
unintentional bandlimiting. To reduce unwanted capacitance,  
create a window around the signal I/O pins in all of the  
ground and power planes around these pins. Otherwise,  
ground and power planes should be unbroken elsewhere on  
the board.  
b) Minimize the distance (< 0.25") from the power-supply  
pins to high-frequency 0.1µF decoupling capacitors. At the  
device pins, the ground and power plane layout should not  
be in close proximity to the signal I/O pins. Avoid narrow  
power and ground traces to minimize inductance between  
the pins and the decoupling capacitors. The power-supply  
connections should always be decoupled with these capaci-  
tors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective  
at lower frequencies, should also be used on the main supply  
pins. These can be placed somewhat further from the device  
and can be shared among several devices in the same area  
of the PC board.  
THERMAL ANALYSIS  
The OPA847 does not require heatsinking or airflow in most  
applications. Maximum desired junction temperature sets the  
maximum allowed internal power dissipation, as described  
here. In no case should the maximum junction temperature  
be allowed to exceed 150°C.  
c) Careful selection and placement of external compo-  
nents preserves the high-frequency performance of the  
OPA847. Use resistors that have low reactance at high  
frequencies. Surface-mount resistors work best and allow a  
tighter overall layout. Metal film and carbon composition  
axially leaded resistors can also provide good high-fre-  
quency performance. Again, keep their leads and PCB trace  
length as short as possible. Never use wirewound-type  
resistors in a high-frequency application. Since the output pin  
and inverting input pin are the most sensitive to parasitic  
capacitance, always position the feedback and series output  
resistor, if any, as close as possible to the output pin. Other  
network components, such as noninverting input termination  
resistors, should also be placed close to the package. Where  
double-side component mounting is allowed, place the feed-  
back resistor directly under the package on the other side of  
the board between the output and inverting input pins. Even  
with a low parasitic capacitance shunting the external resis-  
tors, excessively high resistor values can create significant  
time constants that can degrade performance. Good axial  
metal film or surface-mount resistors have approximately  
0.2pF in shunt with the resistor. For resistor values > 2.0kΩ,  
this parasitic capacitance can add a pole and/or zero below  
400MHz that can effect circuit operation. Keep resistor val-  
ues as low as possible, consistent with load driving consid-  
erations. It has been suggested here that a good starting  
point for design would be to set RG to 39.2Ω. Doing this  
automatically keeps the resistor noise terms low, and mini-  
mizes the effect of their parasitic capacitance. Transimped-  
ance applications can use much higher resistor values. The  
compensation techniques described in this data sheet allow  
excellent frequency response control, even with very high  
feedback resistor values.  
Operating junction temperature (TJ) is given by TA + PD • θJA.  
The total internal power dissipation (PD) is the sum of  
quiescent power (PDQ) and additional power dissipated in the  
output stage (PDL) to deliver load power. Quiescent power is  
simply the specified no-load supply current times the total  
supply voltage across the part. PDL depends on the required  
output signal and load but would, for a grounded resistive  
load, be at a maximum when the output is fixed at a voltage  
equal to half either supply voltage (for equal bipolar sup-  
2
plies). Under this worst-case condition, PDL = VS /(4 • RL),  
where RL includes feedback network loading. This is the  
absolute highest power that can be dissipated for a given RL.  
All actual applications dissipate less power in the output  
stage.  
Note that it is the power in the output stage and not into the  
load that determines internal power dissipation.  
As a worst-case example, compute the maximum TJ using an  
OPA847IDBV (SOT23-6 package) in the circuit of Figure 1  
operating at the maximum specified ambient temperature of  
+85°C and driving a grounded 100Ω load. Maximum internal  
power is:  
PD = 10V • 18.9mA + 52/(4(100Ω || 789Ω)) = 259mW  
Maximum TJ = +85°C + (0.26W • 150°C/W) = 124°C  
All actual applications will operate at a lower junction tem-  
perature than the 124°C computed above. Compute your  
actual output stage power to get an accurate estimate of  
maximum junction temperature, or use the results shown  
here as an absolute maximum.  
BOARD LAYOUT  
d) Connections to other wideband devices on the board  
can be made with short, direct traces or through onboard  
transmission lines. For short connections, consider the trace  
and the input to the next device as a lumped capacitive load.  
Relatively wide traces (50mils to 100mils) should be used,  
preferably with ground and power planes opened up around  
them. Estimate the total capacitive load and set RS from the  
plot of Recommended RS vs Capacitive Load. Low parasitic  
Achieving optimum performance with a high-frequency am-  
plifier like the OPA847 requires careful attention to board  
layout parasitics and external component types. Recommen-  
dations that will optimize performance include:  
a) Minimize parasitic capacitance to any AC ground for all  
of the signal I/O pins. Parasitic capacitance on the output and  
inverting input pins can cause instability: on the noninverting  
input, it can react with the source impedance to cause  
OPA847  
SBOS251E  
19  
www.ti.com  
capacitive loads (< 4pF) may not need an RS, since the  
OPA847 is nominally compensated to operate with a 2pF  
parasitic load. Higher parasitic capacitive loads without an RS  
are allowed as the signal gain increases from +20V/V (in-  
creasing the unloaded phase margin). If a long trace is  
required, and the 6dB signal loss intrinsic to a doubly-  
terminated transmission line is acceptable, implement a  
matched impedance transmission line using microstrip or  
stripline techniques (consult an ECL design handbook for  
microstrip and stripline layout techniques). A 50Ω environ-  
ment is normally not necessary onboard and, in fact, a higher  
impedance environment improves distortion, as shown in the  
distortion versus load plots. With a characteristic board trace  
impedance defined based on board material and trace di-  
mensions, a matching series resistor into the trace from the  
output of the OPA847 is used, as well as a terminating shunt  
resistor at the input of the destination device. Remember  
also that the terminating impedance is the parallel combina-  
tion of the shunt resistor and the input impedance of the  
destination device; this total effective impedance should be  
set to match the trace impedance. If the 6dB attenuation of  
a doubly-terminated transmission line is unacceptable, a  
long trace can be series-terminated at the source-end only.  
Treat the trace as a capacitive load in this case and set the  
series resistor value as shown in the plot of Recommended  
RS vs Capacitive Load. This does not preserve signal integ-  
rity as well as a doubly-terminated line. If the input imped-  
ance of the destination device is low, there will be some  
signal attenuation due to the voltage divider formed by the  
series output into the terminating impedance.  
almost impossible to achieve a smooth, stable frequency  
response. Best results are obtained by soldering the OPA847  
onto the board.  
INPUT AND ESD PROTECTION  
The OPA847 is built using a very high-speed complementary  
bipolar process. The internal junction breakdown voltages are  
relatively low for these very small geometry devices. These  
breakdowns are reflected in the Absolute Maximum Ratings  
table. All device pins are protected with internal ESD protec-  
tion diodes to the power supplies, as shown in Figure 17.  
+VCC  
External  
Pin  
Internal  
Circuitry  
–VCC  
FIGURE 17. Internal ESD Protection.  
These diodes provide moderate protection to input overdrive  
voltages above the supplies as well. The protection diodes  
can typically support 30mA continuous current. Where higher  
currents are possible (for example, in systems with ±15V  
supply parts driving into the OPA847), current limiting series  
resistors should be added into the two inputs. Keep these  
resistor values as low as possible, since high values degrade  
both noise performance and frequency response.  
e) Socketing a high-speed part like the OPA847 is not  
recommended. The additional lead length and pin-to-pin  
capacitance introduced by the socket can create an ex-  
tremely troublesome parasitic network that can make it  
OPA847  
20  
SBOS251E  
www.ti.com  
Revision History  
DATE  
REVISION PAGE  
SECTION  
Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C.  
Design-In Tools Board part number changed.  
DESCRIPTION  
12/08  
E
D
2
4/06  
15  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
OPA847  
SBOS251E  
21  
www.ti.com  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
OPA847ID  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SOIC  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
D
8
6
6
6
6
8
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
OPA  
847  
OPA847IDBVR  
OPA847IDBVRG4  
OPA847IDBVT  
OPA847IDBVTG4  
OPA847IDG4  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DBV  
DBV  
DBV  
DBV  
D
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
OATI  
Green (RoHS  
& no Sb/Br)  
OATI  
OATI  
OATI  
Green (RoHS  
& no Sb/Br)  
250  
Green (RoHS  
& no Sb/Br)  
75  
Green (RoHS  
& no Sb/Br)  
OPA  
847  
OPA847IDR  
SOIC  
D
2500  
2500  
Green (RoHS  
& no Sb/Br)  
OPA  
847  
OPA847IDRG4  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
OPA  
847  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
OPA847IDBVR  
OPA847IDBVT  
OPA847IDR  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
D
6
6
8
3000  
250  
180.0  
180.0  
330.0  
8.4  
8.4  
3.2  
3.2  
6.4  
3.1  
3.1  
5.2  
1.39  
1.39  
2.1  
4.0  
4.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q1  
2500  
12.4  
12.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
OPA847IDBVR  
OPA847IDBVT  
OPA847IDR  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
D
6
6
8
3000  
250  
210.0  
210.0  
367.0  
185.0  
185.0  
367.0  
35.0  
35.0  
35.0  
2500  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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