OPA855 [TI]
具有双极性输入的 8GHz 增益带宽积、解补偿跨阻放大器;
| 型号： | OPA855 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双极性输入的 8GHz 增益带宽积、解补偿跨阻放大器 放大器 |
| 文件： | 总39页 (文件大小：2999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA855
ZHCSII6C –JULY 2018 –REVISED JANUARY 2023
OPA8558GHz 增益带宽积、7V/V 稳定增益、双极输入放大器
1 特性
3 说明
• 高增益带宽积：8GHz
• 解补偿，增益≥7V/V（稳定）
• 低输入电压噪声：0.98nV/√Hz
• 压摆率：2750V/µs
• 低输入电容：
– 共模：0.6pF
– 差分：0.2pF
• 宽输入共模范围：
– 与正电源相差0.4V
– 与负电源相差1.1V
• 3VPP 总输出摆幅
• 电源电压范围：3.3V 至5.25V
• 静态电流：17.8mA
• 封装：8 引脚WSON
OPA855 是一款具有双极输入的宽带低噪声运算放大
器，适用于宽带跨阻和电压放大器应用。将该器件配置
为跨阻放大器 (TIA) 时，8GHz 增益带宽积 (GBWP) 能
够以高达几十千欧的跨阻增益实现高闭环带宽。
下图展示了将 OPA855 配置为 TIA 时，该放大器的带
宽和噪声性能与光电二极管电容的函数关系。计算总噪
声时的带宽范围为从直流到左轴上计算得出的频率
(f )。OPA855 封装具有一个反馈引脚 (FB)，可简化输
入和输出之间的反馈网络连接。
OPA855 经过优化，可在光学飞行时间(ToF) 系统中运
行， 在该系统中， OPA855 与时数转换器（ 如
TDC7201）配合使用。可在具有差分输出放大器（如
THS4541 或 LMH5401）的高分辨率激光雷达系统中
使用OPA855 来驱动高速模数转换器(ADC)。
– 裸片（预发布）
• 温度范围：-40°C 至+125°C
封装信息
器件型号(1)
OPA855
封装尺寸（标称值）
封装
2 应用
WSON (DSG, 8)
2.00 mm × 2.00 mm
• 光时域反射计(OTDR)
• 3D 扫描仪
• 激光测距
• 固态扫描激光雷达
• 光学ToF 位置传感器
• 无人机视觉
器件信息(3)
封装
器件型号(1)
OPA855
芯片尺寸（标称值）
裸片(2)
0.751 mm × 0.705 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
(2) 预发布封装。
(3) 请参阅器件比较表。
• 工业机器人激光雷达
• 扫地机器人激光雷达
• 硅光电倍增器(SiPM) 缓冲放大器
• 光电倍增管后置放大器
CF
450
400
350
300
250
200
150
100
50
160
140
120
100
80
f-3dB, RF = 6 kW
f-3dB, RF = 12 kW
IRN, RF = 6 kW
IRN, RF = 12 kW
60
RF
VBIAS
40
Rx
Lens
5 V
TLV3501
+
20
œ
0
OPA855
+
Stop 2
Start 2
3.8 V
0
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
18
20
VREF
œ
D609
CF
RF
光电二极管电容与带宽和噪声间的关系
TDC7201
(Time-to-
Digital
VBIAS
5 V
Converter)
TLV3501
+
œ
+
OPA855
Stop 1
Start 1
3.8 V
VREF
œ
Tx
Lens
MSP430
ꢀController
Pulsed Laser
Diode
高速飞行时间接收器
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS622
OPA855
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ZHCSII6C –JULY 2018 –REVISED JANUARY 2023
Table of Contents
9.4 Device Functional Modes..........................................20
10 Application, Implementation, and Layout................. 21
10.1 Application Information........................................... 21
10.2 Typical Application.................................................. 21
10.3 Typical Application.................................................. 23
10.4 Power Supply Recommendations...........................27
10.5 Layout..................................................................... 28
11 Device and Documentation Support..........................30
11.1 Device Support........................................................30
11.2 Documentation Support.......................................... 30
11.3 Receiving Notification of Documentation Updates..30
11.4 支持资源..................................................................30
11.5 Trademarks............................................................. 30
11.6 静电放电警告...........................................................30
11.7 术语表..................................................................... 30
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Thermal Information ...................................................5
7.4 Recommended Operating Conditions ........................5
7.5 Electrical Characteristics ............................................6
7.6 Typical Characteristics................................................8
8 Parameter Measurement Information..........................15
9 Detailed Description......................................................16
9.1 Overview...................................................................16
9.2 Functional Block Diagram.........................................16
9.3 Feature Description...................................................17
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (January 2022) to Revision C (January 2023)
Page
• Added the Typical Application, Design Requirements, Detailed Design Procedure, and Application Curves
sections.............................................................................................................................................................23
Changes from Revision A (October 2018) to Revision B (January 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 在特性部分和器件信息表中添加了裸片预发布封装..........................................................................................1
• Added the bare die preview package to the Pin Configuration and Functions section.......................................4
Changes from Revision * (July 2018) to Revision A (October 2018)
Page
• 将“预告信息”更改为“量产数据（正在供货）”.............................................................................................1
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ZHCSII6C –JULY 2018 –REVISED JANUARY 2023
5 Device Comparison Table
VOLTAGE NOISE (nV/
MINIMUM STABLE
GAIN
INPUT
CAPACITANCE (pF)
GAIN BANDWIDTH
(GHz)
DEVICE
INPUT TYPE
√Hz)
OPA855
OPA856
OPA858
OPA859
LMH6629
Bipolar
Bipolar
CMOS
CMOS
Bipolar
7 V/V
1 V/V
7 V/V
1 V/V
10 V/V
0.98
0.9
0.8
1.1
0.8
0.8
5.7
8
1.1
5.5
0.9
4
2.5
3.3
0.69
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6 Pin Configuration and Functions
NC
13
PD
12
PAD
#1
FB
1
FB
NC
INœ
IN+
1
2
3
4
8
7
6
5
PD
11
10
VS+
VS+
VS+
OUT
VSœ
NC
IN-
2
3
Thermal pad
9
OUT
8
7
VS-
VS-
IN+
4
5
6
Not to scale
NC
NC
图6-2. Bare Die Package (Preview)
图6-1. DSG Package,
8-Pin WSON With Exposed Thermal Pad
(Top View)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
FB
NO.
1
I
I
I
Feedback connection to output of amplifier
Inverting input
3
IN–
IN+
4
Noninverting input
NC
2
Do not connect
—
O
I
OUT
PD
6
Amplifier output
8
Power down connection. PD = logic low = power off mode; PD = logic high = normal operation.
5
Negative voltage supply
VS–
VS+
—
—
—
7
Positive voltage supply
Thermal pad
Connect the thermal pad to VS–
表6-2. Bond Pad Functions
PAD
NAME
FB
TYPE(1)
DESCRIPTION
NO.
1
I
I
I
Feedback connection to output of amplifier
Inverting input
3
IN–
IN+
4
Noninverting input
2,5,6,
13
NC
Do not connect
—
OUT
9
12
O
I
Amplifier output
PD
Power down connection. PD = logic low = power off mode; PD = logic high = normal operation.
7,8
Negative voltage supply
Positive voltage supply
Connect to VS–
VS–
VS+
—
—
—
10,11
Backside
(1) I = input, O = output, FB = feedback, NC = no connect
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
(VS–) –0.5
(VS–) –0.5
MAX
5.5
UNIT
V
VS
Total supply voltage (VS+ –VS–
Input voltage
)
VIN+, VIN–
VID
(VS+) + 0.5
1
V
Differential input voltage
Output voltage
V
VOUT
IIN
(VS+) + 0.5
±10
V
Continuous input current
Continuous output current(2)
Junction temperature
Operating free-air temperature
Storage temperature
mA
mA
°C
°C
°C
IOUT
TJ
±100
150
TA
125
–40
–65
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JS-002, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Thermal Information
OPA856
THERMAL METRIC(1)
DSG (WSON)
8 PINS
80.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
100
45
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.8
ΨJT
45.2
ΨJB
RθJC(bot)
22.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.3
NOM
MAX
5.25
125
UNIT
V
VS
TA
5
Total supply voltage (VS+ –VS–
)
Operating free-air temperature
°C
–40
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7.5 Electrical Characteristics
at VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is
referenced to midsupply, and TA = 25℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC PERFORMANCE
SSBW
LSBW
GBWP
Small-signal bandwidth
Large-signal bandwidth
Gain-bandwidth product
Bandwdith for 0.1-dB flatness
Slew rate (10%-90%)
Rise time
VOUT = 100 mVPP
2.5
850
8
GHz
MHz
GHz
MHz
V/µs
ns
VOUT = 2 VPP
200
2750
0.17
0.17
2.3
SR
tr
VOUT = 2-V step
VOUT = 100-mV step
VOUT = 100-mV step
VOUT = 2-V step
tf
Fall time
ns
Settling time to 0.1%
Settling time to 0.001%
Overshoot or undershoot
Overdrive recovery
ns
VOUT = 2-V step
2600
5%
3
ns
VOUT = 2-V step
2x output overdrive
f = 10 MHz, VOUT = 2 VPP
f = 100 MHz, VOUT = 2 VPP
f = 10 MHz, VOUT = 2 VPP
f = 100 MHz, VOUT = 2 VPP
f = 1 MHz
ns
90
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
65
86
dBc
74
en
ei
Input-referred voltage noise
Input-referred current noise
Closed-loop output impedance
0.98
2.5
nV/√Hz
pA/√Hz
Ω
f = 1 MHz
zO
f = 1 MHz
0.15
DC PERFORMANCE
AOL
Open-loop voltage gain
70
76
±0.2
dB
VOS
Input offset voltage
Input offset voltage drift
Input bias current (1)
Input bias current drift
Input offset current
TA = 25°C
1.5
–5
1
mV
µV/°C
µA
–1.5
0.5
ΔVOS/ΔT
IB
TA = –40°C to 125°C
TA = 25°C
–18.5
–1
–12
–0.08
±0.1
µA/°C
µA
ΔIB/ΔT
IBOS
TA = –40°C to +125°C
TA = 25°C
ΔIBOS
ΔT
/
Input offset current drift
1
nA/°C
dB
TA = –40°C to +125°C
CMRR
Common-mode rejection ratio
VCM = ±0.5 V referred to midsupply
90
100
INPUT
Common-mode input resistance
Common-mode input capacitance
Differential input resistance
2.3
0.6
5
MΩ
pF
kΩ
pF
V
CCM
CDIFF
VIH
VIL
Differential input capacitance
0.2
2.9
1.1
4.6
4.3
1.1
1.3
Common-mode input range (high)
Common-mode input range (low)
Common-mode input range (high)
Common-mode input range (high)
Common-mode input range (low)
Common-mode input range (low)
CMRR > 80 dB, VS+ = 3.3 V
CMRR > 80 dB, VS+ = 3.3 V
CMRR > 80 dB
2.7
4.4
1.3
1.3
V
VIH
VIH
VIL
V
V
TA = –40°C to +125 °C, CMRR > 80 dB
CMRR > 80 dB
V
VIL
V
TA = –40°C to +125°C, CMRR > 80 dB
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7.5 Electrical Characteristics (continued)
at VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is
referenced to midsupply, and TA = 25℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUTPUT
VOH
Output voltage (high)(2)
Output voltage (high)(2)
Output voltage (low)(2)
Output voltage (low)(2)
TA = 25°C, VS+ = 3.3 V
2.35
3.95
2.4
4.1
4
V
V
TA = 25°C
VOH
VOL
VOL
TA = –40°C to +125°C
TA = 25°C, VS+ = 3.3 V
TA = 25°C
1.05
1.05
1.1
80
1.15
1.15
V
V
TA = –40°C to +125°C
RL = 10 Ω, AOL > 60 dB
TA = –40°C to +125°C, RL = 10 Ω, AOL > 60 dB
65
IO_LIN
Linear output drive (sink and source)
Output short-circuit current
mA
mA
70
ISC
POWER SUPPLY
85
16
105
17.8
16.7
19.5
86
19.5
IQ
Quiescent current
mA
dB
TA = –40°C
TA = 125°C
PSRR+
Positive power-supply rejection ratio
Negative power-supply rejection ratio
80
70
80
PSRR–
POWER DOWN
Disable voltage threshold
Amplifier OFF below this voltage
Amplifier ON below this voltage
0.65
1
1.5
70
V
V
Enable voltage threshold
Power-down quiescent current
PD bias current
1.8
140
140
μA
μA
ns
70
Turnon time delay
Time to VOUT = 90% of final value
15
Turnoff time delay
120
ns
(1) Current flowing into the input pin is considered negative
(2) Amplifier output saturated
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7.6 Typical Characteristics
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
3
6
3
0
0
-3
-3
-6
-6
Gain = +7 V/V
Gain = -7 V/V
Gain = +10 V/V
Gain = +20 V/V
G = +39.2 V/V
-9
-12
-15
-9
VS = 5 V
VS = 3.3 V
-12
1M
10M
100M
Frequency (Hz)
1G
5G
D502
1M
10M
100M
Frequency (Hz)
1G
5G
VOUT = 100 mVPP
D500
VOUT = 100 mVPP; for circuit configuration, see 节8
图7-2. Small-Signal Frequency Response vs Supply Voltage
图7-1. Small-Signal Frequency Response vs Gain
3
0
3
0
-3
-6
-3
TA = -40èC
TA = 0èC
-6
TA = +25èC
TA = +85èC
TA = +125èC
-9
-9
RL = 100 W
RL = 200 W
RL = 400 W
-12
1M
10M
Frequency (Hz)
100M
D504
1M
10M
100M
Frequency (Hz)
1G
5G
VOUT = 100 mVPP
Gain = 39.2 V/V, RF = 953 Ω
D503
VOUT = 100 mVPP
图7-4. Small-Signal Frequency Response vs Ambient
Temperature
图7-3. Small-Signal Frequency Response vs Output Load
4
3
0
2
0
-2
-4
-6
-3
-6
-8
Gain = +7 V/V
Gain = -7 V/V
Gain = +10 V/V
Gain = +20 V/V
-12
RS = 16.5 W, C L = 10 pF
RS = 8 W, C L = 47 pF
RS = 5.6 W, C L = 100 pF
RS = 1.6 W, C L = 1 nF
-9
-10
-12
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D506
D505
VOUT = 2 VPP
图7-6. Large-Signal Frequency Response vs Gain
VOUT = 100 mVPP; for circuit configuration, see 图8-3
图7-5. Small-Signal Frequency Response vs Capacitive Load
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
0.2
0.1
3
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-3
-6
-9
VS = 5 V, VOUT = 2 VPP
VS = 5 V, VOUT = 1 VPP
VS = 3.3 V, VOUT = 1 VPP
Gain = 7 V/V
10M
-12
1M
1M
100M
Frequency (Hz)
1G
10M
100M
Frequency (Hz)
1G
5G
D507
D508
VOUT = 2 VPP
图7-7. Large-Signal Response for 0.1-dB Gain Flatness
图7-8. Large-Signal Frequency Response vs Voltage Supply
90
75
60
45
30
15
0
90
100
AOL Magnitude (dB)
AOL Phase (è)
45
0
10
-45
-90
-135
-180
-225
1
Gain = 7 V/V
Gain = 20 V/V
0.1
1M
-15
100k
10M
Frequency (Hz)
100M
1M
10M 100M
Frequency (Hz)
1G
10G
D509
D510
Small-Signal Response
Small-Signal Response
图7-9. Closed-Loop Output Impedance vs Frequency
图7-10. Open-Loop Magnitude and Phase vs Frequency
10
100
10
1
1.2
Voltage Noise
Current Noise
1.15
1.1
1.05
1
1
0.95
0.9
0.85
0.1
-40
-20
0
20
40
60
80
100 120 140
1k
10k
100k 1M
Frequency (Hz)
10M
100M
Ambient Temperature (èC)
D512
D511
Frequency = 10 MHz
.
图7-12. Voltage Noise Density vs Ambient Temperature
图7-11. Voltage and Current Noise Density vs Frequency
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
-40
-50
-40
-50
HD2, VOUT = 0.5 V PP
HD2, VOUT = 1 VPP
HD2, VOUT = 2 VPP
HD2, VOUT = 2.5 V PP
HD3, VOUT = 0.5 V PP
HD3, VOUT = 1 VPP
HD3, VOUT = 2 VPP
HD3, VOUT = 2.5 V PP
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D513
D514
.
.
图7-13. Harmonic Distortion (HD2) vs Output Swing
图7-14. Harmonic Distortion (HD3) vs Output Swing
-40
-40
HD2, VOUT = 100 W
HD2, VOUT = 200 W
HD2, VOUT = 400 W
HD3, VOUT = 100 W
HD3, VOUT = 200 W
HD3, VOUT = 400 W
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D515
D516
VOUT = 2 VPP
VOUT = 2 VPP
图7-15. Harmonic Distortion (HD2) vs Output Load
图7-16. Harmonic Distortion (HD3) vs Output Load
-40
-40
HD2, Gain = +7 V/V
HD3, Gain = +7 V/V
HD2, Gain = -7 V/V
HD2, Gain = +10 V/V
HD2, Gain = +20 V/V
HD3, Gain = -7 V/V
HD3, Gain = +10 V/V
HD3, Gain = +20 V/V
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D517
D518
VOUT = 2 VPP
VOUT = 2 VPP
图7-17. Harmonic Distortion (HD2) vs Gain
图7-18. Harmonic Distortion (HD3) vs Gain
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
60
40
20
0
1.25
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-20
-40
-60
Input
Output
Input
Output
-1.25
Time (5 ns/div)
Time (5 ns/div)
D519
D520
Average Rise and Fall Time (10% –90%) = 300 ps
Average Rise and Fall Time (10% –90%) = 569 ps
图7-20. Large-Signal Transient Response
Rise and fall time limited by test equipment
图7-19. Small-Signal Transient Response
75
4
3
50
25
2
1
0
0
-1
-2
-3
-4
-25
-50
-75
RS = 16.5 W, C L = 10 pF
RS = 8 W, C L = 47 pF
RS = 5.6 W, C L = 100 pF
RS = 1.6 W, C L = 1 nF
Ideal Output
Measured Output
Time (5 ns/div)
Time (2 ns/div)
D521
D522
.
2x Output Overdrive
图7-21. Small-Signal Transient Response vs Capacitive Load
图7-22. Output Overload Response
3
3
2
Power Down ( PD)
Output
2
1
1
0
0
-1
-1
-2
-3
-2
Power Down ( PD)
Output
-3
Time (5 ns/div)
Time (5 ns/div)
D523
D524
.
.
图7-23. Turnon Transient Response
图7-24. Turnoff Transient Response
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
120
100
80
60
40
20
0
100
80
60
40
20
0
CMRR
PSRR+
PSRR-
10k
100k
1M 10M
Frequency (Hz)
100M
1G
10k
100k
1M 10M
Frequency (Hz)
100M
1G
D525
D526
Small-Signal Response
Small-Signal Response
图7-25. Common-Mode Rejection Ratio vs Frequency
图7-26. Power Supply Rejection Ratio vs Frequency
18.25
18
19.5
19
18.5
18
17.75
17.5
17.25
17
17.5
17
16.75
16.5
Unit 1
Unit 2
Unit 3
16.5
VS = 3.3 V
VS = 5 V
16.25
16
16
-40
3
3.25 3.5 3.75
4
Total Supply Voltage (V)
4.25 4.5 4.75
5
5.25
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D560
D561
3 Typical Units
.
图7-27. Quiescent Current vs Supply Voltage
图7-28. Quiescent Current vs Ambient Temperature
0.75
0.25
Unit 1
Unit 2
Unit 3
0.5
0.25
0
0.15
0.05
-0.25
-0.5
-0.75
-1
-0.05
-0.15
-0.25
3
3.25 3.5 3.75
4
Total Supply Voltage (V)
4.25 4.5 4.75
5
5.25
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D563
D564
3 Typical Units
µ = 0.4 µV/°C
28 units tested
σ= 0.7 µV/°C
图7-29. Offset Voltage vs Supply Voltage
图7-30. Offset Voltage vs Ambient Temperature
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
1.25
1
0.75
0.5
Unit 1
Unit 2
Unit 3
TA = -40èC
TA = +25èC
TA = +125èC
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1.25
0.5
1
1.5
2
Common-Mode Voltage (V)
2.5
3
3.5
4
4.5
5
0.5
1
1.5
2
Common-Mode Voltage (V)
2.5
3
3.5
4
4.5
5
D566
D567
VS+ = 5 V, VS– = 0 V
3 Typical Units
VS+ = 5 V, VS– = 0 V
图7-31. Offset Voltage vs Input Common-Mode Voltage
图7-32. Offset Voltage vs Input Common-Mode Voltage vs
Ambient Temperature
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-0.5
-1
-1
Unit 1
Unit 2
Unit 3
TA = -40èC
-1.5
-1.5
TA = +25èC
TA = +125èC
-2
-2
1
1.5
2
2.5
Output Voltage (V)
3
3.5
4
4.5
1
1.5
2
2.5
Output Voltage (V)
3
3.5
4
4.5
D569
D570
VS+ = 5 V, VS– = 0 V
3 Typical Units
VS+ = 5 V, VS– = 0 V
图7-33. Offset Voltage vs Output Swing
图7-34. Offset Voltage vs Output Swing vs Ambient
Temperature
-7
-8
0
Unit 1
Unit 2
Unit 3
TA = -40èC
TA = +25èC
TA = +125èC
-9
-5
-10
-11
-12
-13
-14
-15
-16
-17
-18
-10
-15
-20
-25
-40
-20
0
20
40
60
80
100 120 140
1
1.5
2
Common-Mode Voltage (V)
2.5
3
3.5
4
4.5
Ambient Temperature (èC)
D571
D572
3 Typical Units
VS+ = 5 V, VS– = 0 V
图7-35. Input Bias Current vs Ambient Temperature
图7-36. Input Bias Current vs Input Common-Mode Voltage vs
Ambient Temperature
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
2.2
2
4.5
4
TA = -40èC
TA = +25èC
TA = +125èC
3.5
3
1.8
1.6
1.4
1.2
1
2.5
2
1.5
1
TA = -40èC
TA = +25èC
TA = +125èC
0.5
0
0.8
-120
-100
-80
-60
Output Current (mA)
-40
-20
0
0
20
40
60
Output Current (mA)
80
100
120
D573
D574
VS+ = 5 V, VS– = 0 V
VS+ = 5 V, VS– = 0 V
图7-37. Output Swing vs Sinking Current
图7-38. Output Swing vs Sourcing Current
8000
7000
6000
5000
4000
3000
2000
1000
0
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
D541
D540
Quiescent Current (mA)
Offset Voltage (mV)
µ = 17.6 mA
13780 units tested
σ= 0.3 mA
13780 units tested
µ = –0.2 mV
σ= 0.15 mV
图7-39. Quiescent Current Distribution
图7-40. Offset Voltage Distribution
8000
7000
6000
5000
4000
3000
2000
1000
0
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
Inverting Current
Noninverting Current
Input Bias Current (mA)
D542
D543
Input Offset Current (mA)
13780 units tested
µ = –11.2 µA
σ= 0.6 µA
µ = 0.04 µA
13780 units tested
σ= 0.1 µA
图7-41. Input Bias Current Distribution
图7-42. Input Offset Current Distribution
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8 Parameter Measurement Information
The various test setup configurations for the OPA855 are shown in 图 8-1, 图 8-2, and 图 8-3. When configuring
the OPA855 in a gain of +39.2 V/V, feedback resistor RF was set to 953 Ω.
图 7-1 shows 5-dB of peaking with the amplifier in an inverting configuration of –7 V/V with the amplifier
configured as shown in 图 8-2. The 50-Ω matched termination of this circuit configuration results in the amplifier
being configured in a noise gain of 5.3 V/V, which is lower than the recommended +7 V/V.
GND
50 ꢀ
2.5 V
50 ꢀ
50-ꢀ
Source
169 ꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
RG
453 ꢀ
GND
GND
GND
RG values depend on gain configuration
图8-1. Noninverting Configuration
2.5 V
169 ꢀ
+
50-ꢀ
Measurement
System
GND
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
50 ꢀ
50-ꢀ
Source
GND
64 ꢀ
453 ꢀ
GND
220 ꢀ
GND
图8-2. Inverting Configuration (Gain = –7 V/V)
GND
50 ꢀ
2.5 V
50 ꢀ
50-ꢀ
Source
RS
1 kꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
CL
53.6 ꢀ
Þ2.5 V
75 ꢀ
453 ꢀ
GND
GND
GND
GND
图8-3. Capacitive Load Driver Configuration
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9 Detailed Description
9.1 Overview
The ultra-wide, 8-GHz gain bandwidth product (GBWP) of the OPA855, combined with the broadband voltage
noise of 0.98 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed data
acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front ends.
The OPA855 combines multiple features to optimize dynamic performance. In addition to the wide, small-signal
bandwidth, the OPA855 has 850 MHz of large-signal bandwidth (2 VPP), and a slew rate of 2750 V/µs, making
the device a viable option for high-speed pulsed applications.
9.2 Functional Block Diagram
The OPA855 is a classic voltage feedback operational amplifier (op amp) with two high-impedance inputs and a
low-impedance output. Standard application circuits are supported, like the two basic options shown in 图 9-1
and 图9-2. The resistor on the noninverting pin is used for bias current cancellation to minimize the output offset
voltage. In a noninverting configuration the additional resistors on the noninverting pin add noise to the system
so if SNR is critical, the resistor can be eliminated. In an inverting configuration the noninverting node is typically
connected to a DC voltage, so the high-frequency noise contribution from the bias cancellation resistor can be
bypassed by adding a large 1-µF capacitor in parallel to the resistor to shunt the noise. The DC operating point
for each configuration is level-shifted by the reference voltage (VREF), which is typically set to midsupply in
single-supply operation. VREF is typically connected to ground in split-supply applications.
VSIG
VS+
RF || RG
(1+RF/RG)×VSIG
VREF
VIN
+
VOUT
VREF
œ
RG
VSœ
RF
VREF
图9-1. Noninverting Amplifier
VS+
RF || RG
œ(RF/RG)×VSIG
VREF
VIN
+
VSIG
VOUT
VREF
VREF
œ
RG
VSœ
RF
图9-2. Inverting Amplifier
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9.3 Feature Description
9.3.1 Input and ESD Protection
The OPA855 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown
voltages are low for these small geometry devices, and as a result, all device pins are protected with internal
ESD protection diodes to the power supplies as 图 9-3 shows. There are two antiparallel diodes between the
inputs of the amplifier that clamp the inputs during an overrange or fault condition.
VS+
Power Supply
ESD Cell
VIN+
+
VOUT
œ
VINÞ
FB
VSÞ
图9-3. Internal ESD Structure
9.3.2 Feedback Pin
The OPA855 pin layout is optimized to minimize parasitic inductance and capacitance, which is a critical care
about in high-speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The
FB pin is separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin
must be left floating. There are two advantages to this pin layout:
1. A feedback resistor (RF) can connect between the FB and IN–pin on the same side of the package (see 图
9-4) rather than going around the package.
2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN–pins by
increasing the physical separation between the pins.
FB
NC
INœ
IN+
PD
1
2
3
4
8
7
6
5
VS+
OUT
VSœ
RF
œ
+
图9-4. RF Connection Between FB and IN–Pins
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9.3.3 Wide Gain-Bandwidth Product
图 7-10 shows the open-loop magnitude and phase response of the OPA855. Calculate the gain bandwidth
product of any op amp by determining the frequency at which the AOL is 40 dB and multiplying that frequency by
a factor of 100. The open-loop response shows the OPA855 to have approximately 62° of phase-margin in a
noise gain of 7 V/V. The second pole in the AOL response occurs before the magnitude crosses 0 dB, and the
resultant phase margin is less than 0°. This indicates instability at a gain of 0 dB (1 V/V). Amplifiers that are not
unity-gain stable are known as decompensated amplifiers. Decompensated amplifiers typically have higher gain-
bandwidth product, higher slew rate, and lower voltage noise, compared to a unity-gain stable amplifier with the
same amount of quiescent power consumption.
图 9-5 shows the open-loop magnitude (AOL) of the OPA855 as a function of temperature. The results show
approximately 5° of phase-margin variation over the entire temperature range in a noise gain of 7 V/V.
Semiconductor process variation is the naturally occurring variation in the attributes of a transistor (Early-voltage,
β, channel-length and width) and other passive elements (resistors and capacitors) when fabricated into an
integrated circuit. The process variation can occur across devices on a single wafer or across devices over
multiple wafer lots over time. Typically, the variation across a single wafer is tightly controlled. 图 9-6 shows the
AOL magnitude of the OPA855 as a function of process variation over time. The results show the AOL curve for
the nominal process corner and the variation one standard deviation from the nominal. The simulated results
show less than 2° of phase-margin difference within a standard deviation of process variation in a noise gain of 7
V/V.
One of the primary applications for the OPA855 is as a high-speed transimpedance amplifier (TIA). The low-
frequency noise gain of a TIA is 0 dB (1 V/V). At high frequencies the ratio of the total input capacitance and the
feedback capacitance set the noise gain. To maximize the TIA closed-loop bandwidth, the feedback capacitance
is typically smaller than the input capacitance, which implies that the high-frequency noise gain is greater than 0
dB. As a result, op amps configured as TIAs are not required to be unity-gain stable, which makes a
decompensated amplifier a viable option for a TIA. What You Need To Know About Transimpedance Amplifiers
– Part 1 and What You Need To Know About Transimpedance Amplifiers – Part 2 describe transimpedance
amplifier compensation in greater detail.
90
75
60
45
30
15
0
90
75
60
45
30
15
0
AOL at -40èC
AOL at 25èC
AOL at +125èC
AOL (-1 s)
AOL (Typ.)
AOL (+1 s)
-15
-15
100k
1M
10M 100M
Frequency (Hz)
1G
10G
100k
1M
10M 100M
Frequency (Hz)
1G
10G
D604
D605
图9-5. Open-Loop Gain vs Temperature
图9-6. Open-Loop Gain vs Process Variation
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9.3.4 Slew Rate and Output Stage
In addition to wide bandwidth, the OPA855 features a high slew rate of 2750 V/µs. The slew rate is a critical
parameter in high-speed pulse applications with narrow sub-10-ns pulses, such as optical time-domain
reflectometry (OTDR) and LIDAR. The high slew rate of the OPA855 implies that the device accurately
reproduces a 2-V, sub-ns pulse edge, as seen in 图 7-20. The wide bandwidth and slew rate of the OPA855
make it an excellent amplifier for high-speed signal-chain front ends.
图 9-7 shows the open-loop output impedance of the OPA855 as a function of frequency. To achieve high slew
rates and low output impedance across frequency, the output swing of the OPA855 is limited to approximately 3
V. The OPA855 is typically used in conjunction with high-speed pipeline ADCs and flash ADCs that have limited
input ranges. Therefore, the OPA855 output swing range coupled with the class-leading voltage noise
specification maximizes the overall dynamic range of the signal chain.
20
18
16
14
12
10
8
6
4
2
0
10k
100k
1M
10M 100M
Frequency (Hz)
1G
10G
D601
图9-7. Open-Loop Output Impedance (ZOL) vs Frequency
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9.4 Device Functional Modes
9.4.1 Split-Supply and Single-Supply Operation
The OPA855 can be configured with single-sided supplies or split-supplies as shown in 图 10-11. Split-supply
operation using balanced supplies with the input common-mode set to ground eases lab testing because most
signal generators, network analyzers, spectrum analyzers, and other lab equipment typically reference inputs
and outputs to ground. In split-supply operation, the thermal pad must be connected to the negative supply.
Newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply.
The OPA855 can be used with a single positive supply (negative supply at ground) with no change in
performance if the input common-mode and output swing are biased within the linear operation of the device. In
single-supply operation, level shift the DC input and output reference voltages by half the difference between the
power supply rails. This configuration maintains the input common-mode and output load reference at midsupply.
To eliminate gain errors, the source driving the reference input common-mode voltage must have low output
impedance across the frequency range of interest. In this case, the thermal pad must be connected to ground.
9.4.2 Power-Down Mode
The OPA855 features a power-down mode to reduce the quiescent current to conserve power. 图 7-23 and 图
7-24 show the transient response of the OPA855 as the PD pin toggles between the disabled and enabled
states.
The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is
configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable
threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65 V supplies, then
the threshold voltages are at –1 V and 0.15 V. If the amplifier is configured with ±2.5 V supplies, then the
threshold voltages are at –1.85 V and –0.7 V.
图 9-8 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled state to
the disabled state. Similarly, 图 9-9 shows the switching behavior of a typical amplifier as the PD pin is swept up
from the disabled state to the enabled state. The small difference in the switching thresholds between the down
sweep and the up sweep is caused by the hysteresis designed into the amplifier to increase immunity to noise
on the PD pin.
20
17.5
15
20
17.5
15
12.5
10
12.5
10
7.5
5
7.5
5
TA = -40èC
TA = +25èC
TA = +125èC
TA = -40èC
TA = +25èC
TA = +125èC
2.5
0
2.5
0
-2
-1.5
-1
-0.5
0
0.5
Power Down Voltage (V)
1
1.5
2
-2
-1.5
-1
-0.5
0
0.5
Power Down Voltage (V)
1
1.5
2
D600
D601
图9-8. Switching Threshold
图9-9. Switching Threshold ( PD Pin Swept from
(PD Pin Swept from High to Low)
Low to High)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the
amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a
parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA855 uses internal,
back-to-back protection diodes between the inverting and noninverting input pins as 图9-3 shows. In the power-
down state, if the differential voltage between the input pins of the amplifier exceeds a diode voltage drop, an
additional low-impedance path is created between the noninverting input pin and the output pin.
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10 Application, Implementation, and Layout
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The OPA855 offers very high-bandwidth, high slew-rate, low noise, and better than –60 dBc of distortion
performance at frequencies of up to 100 MHz. These features make this device an excellent low-noise amplifier
in high-speed data acquisition systems.
10.2 Typical Application
图10-1 shows the OPA855 configured as a transimpedance amplifier (U1) in a wide-bandwidth, optical front-end
system. A second amplifier, the OPA859-Q1, configured as a unity-gain buffer (U2) sets a dc offset voltage to the
THS4520. The THS4520 is used to convert the single-ended transimpedance output of the OPA855 into a
differential output signal. The THS4520 drives the input of the ADS54J64, 14-bit, 1-GSPS analog-to-digital
converter (ADC) that digitizes the analog signal.
CF
RF
VBIAS
5 V
œ
U1
499 ꢀ
499 ꢀ
3.8 V
+
OPA855
5 V
+
œ
Low-pass
filter
VOCM = 1.3 V
ADS54J64
+
œ
5 V
œ
U2
+
3.25 V
OPA859
499 ꢀ
499 ꢀ
图10-1. OPA855 as a TIA in an Optical Front-End System
10.2.1 Design Requirements
The objective is to design a low noise, wideband optical front-end system using the OPA855 as a
transimpedance amplifier. The design requirements are:
• Amplifier supply voltage: 5 V
• TIA common-mode voltage: 3.8 V
• THS4520 gain: 1 V/V
• ADC input common-mode voltage: 1.3 V
• ADC analog differential input range: 1.1 VPP
10.2.2 Detailed Design Procedure
The closed-loop bandwidth of a transimpedance amplifier is a function of the following:
1. The total input capacitance (CIN). This total includes the photodiode capacitance, the input capacitance of
the amplifier (common-mode and differential capacitance) and any stray capacitance from the PCB.
2. The op amp gain bandwidth product (GBWP).
3. The transimpedance gain (RF).
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图10-1 shows the OPA855 configured as a TIA, with the avalanche photodiode (APD) reverse biased so that the
APD cathode is tied to a large positive bias voltage. In this configuration, the APD sources current into the op
amp feedback loop so that the output swings in a negative direction relative to the input common-mode voltage.
To maximize the output swing in the negative direction, the OPA855 common-mode voltage is set close to the
positive limit; only 1.2 V from the positive supply rail. The feedback resistance (RF) and the input capacitance
(CIN) form a zero in the noise gain that results in instability if left unchecked. To counteract the effect of the zero,
a pole is inserted into the noise gain transfer function by adding the feedback capacitor (CF).
The Transimpedance Considerations for High-Speed Amplifiers Application Report discusses theories and
equations that show how to compensate a transimpedance amplifier for a particular transimpedance gain and
input capacitance. The bandwidth and compensation equations from the application report are available in an
Excel® calculator. What You Need To Know About Transimpedance Amplifiers – Part 1 provides a link to the
calculator.
The equations and calculators in the referenced application report and blog posts are used to model the
bandwidth (f–3dB) and noise (IRN) performance of the OPA855 configured as a TIA. The resultant performance is
shown in 图 10-2 and 图 10-3. The left-side Y-axis shows the closed-loop bandwidth performance, whereas the
right side of the graph shows the integrated input-referred noise. The noise bandwidth to calculate IRN for a fixed
RF and CPD is set equal to the f–3dB frequency. 图 10-2 shows the amplifier performance as a function of
photodiode capacitance (CPD) for RF = 6 kΩ and 12 kΩ. Increasing CPD decreases the closed-loop bandwidth.
To maximize bandwidth, make sure to reduce any stray parasitic capacitance from the PCB. The OPA855 is
designed with 0.8 pF of total input capacitance to minimize the effect of stray capacitance on system
performance. 图 10-3 shows the amplifier performance as a function of RF for CPD = 1.5 pF and 2.5 pF.
Increasing RF results in lower bandwidth. To maximize the signal-to-noise ratio (SNR) in an optical front-end
system, maximize the gain in the TIA stage. Increasing RF by a factor of X increases the signal level by X, but
only increases the resistor noise contribution by √X, thereby improving SNR. Since the OPA855 is a bipolar
input amplifier, increasing the feedback resistance increases the voltage offset due to the bias current and also
increases the total output noise due to increased noise contributions from the amplifiers current noise.
The OPA859-Q1 configured as a unity-gain buffer drives a DC offset voltage of 3.25 V into the lower half of the
THS4520. To maximize the dynamic range of the ADC, the OPA855-Q1 and OPA859-Q1 drive a differential
common-mode of 3.8 V and 3.25 V respectively into the THS4520. The dc offset voltage of the buffer amplifier
can be derived using 方程式1.
≈
∆
∆
∆
∆
∆
«
’
÷
÷
÷
÷
÷
◊
VADC _DIFF _IN
1
2
VBUF _DC = VTIA _ CM
-
ì
≈
∆
«
’
÷
RF
RG ◊
(1)
where
• VTIA_CM is the common-mode voltage of the TIA (3.8 V)
• VADC_DIFF_IN is the differential input voltage range of the ADC (1.1 VPP
)
• RF and RG are the feedback resistance (499 Ω) and gain resistance (499 Ω) of the THS4520 differential
amplifier
The low-pass filter between the THS4520 and the ADC54J64 minimizes high-frequency noise and maximizes
SNR. The ADC54J64 has an internal buffer that isolates the output of the THS4520 from the ADC sampling-
capacitor input, so a traditional charge bucket filter is not required.
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10.2.3 Application Curves
450
400
350
300
250
200
150
100
50
160
140
120
100
80
350
300
250
200
150
100
120
f-3dB, CF = 1.5 pF
f-3dB, CF = 2.5 pF
f-3dB, RF = 6 kW
f-3dB, RF = 12 kW
IRN, RF = 6 kW
IRN, RF = 12 kW
IRN, CF = 1.5 pF
IRN, RF = 2.5 pF
100
80
60
40
20
60
40
20
0
0
2
4
6
Photodiode capacitance (pF)
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
Feedback Resistance (kW)
D609
D610
图10-2. Bandwidth and Noise vs Photodiode Capacitance
图10-3. Bandwidth and Noise vs Feedback Resistance
10.3 Typical Application
There are two main approaches for current to voltage conversion. One uses a non-inverting voltage feedback
amplifier in combination with a shunt resistor to first convert current and then further amplify the optical signal.
The other approach configures an amplifier for transimpedance applications which combines both steps into
one. 图10-4 shows the standard configuration for both approaches.
图10-4. Transimpedance Amplifier vs. Voltage Feedback Amplifier
Both configurations provide a low output impedance stage which provides the ability to interface with various
types of loads. However, the non-inverting option comes with a few disadvantages. TIA's input impedance is
near zero, since the amplifier keeps the voltage at the inverting input node at the same potential as the non-
inverting input node. While the VFB's input impedance is equal to the shunt resistor RL. In the case of the VFB
amplifier, the signal response will be slowed due to a large time constant created by the shunt resistor and
capacitor. Also, the linearity of the photodetector can suffer, especially for higher detector currents due to the
varying voltage bias produced at the shunt resistor. And, since the voltage bias of the photodetector is no longer
constant for all detector currents, the diode’s internal capacitance will vary. Using a TIA, the voltage bias
remains constant at the voltage set by the non-inverting node, and can provide level shifting to the signal which
is especially useful for single-supply configurations.
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OPA855 offers 8 GHz of gain bandwidth, high slew-rate, and low noise which makes this device suitable for a
wide range of photodetectors. 图 10-5 shows the OPA855 configured as a transimpedance amplifier (TIA) in a
wide-bandwidth, optical front-end system. Various types of optical sensors can be used as an optical input to the
amplifier: photodiode (PD), avalanche photodiode (APD), Photomultiplier Tube (PMT), and Multi-Pixel Photon
Counter (MPPC) or known as Solid-State Photomultiplier (SiPM). Optical detection applications have commonly
used APDs, but ultra-low light source detection has been a challenge in past solutions. With technologies such
as PMTs and MPPCs, their high intrinsic gain, while maintaining a fast output, requires a low noise, high-speed
interface. The OPA855 can accommodate for these optical challenges and would work equally as well in these
applications.
图10-5. Transimpedance Amplifier with APD or SiPM/MPPC or PMT Inputs
Transimpedance applications require low voltage and current noise for optimal system performance. Due to its
high input impedance structure, the OPA855 has a great balance between low input-referred voltage noise and
current noise which is consistent over frequency. Overall, the amplifier noise should have minimal impact to the
total noise of the application. We would need to examine the total input referred noise to the optical sensor.
Noise sources in optical sensors vary especially when introducing gain and photon paralleling. Optical power,
gain, and applied reverse bias are the main characteristics that will affect signal to noise ratio. Standard
photodiodes contribute the lowest noise at the highest quantum efficiency. Internal to photodiodes, noises
sources include shot and thermal. Shot noise is a random occurrence of photodetection which arises in periods
of both light and dark. Dark current is noise that occurs in the absence of an optical source which can be
included with shot noise. And, thermal noise originates from the shunt resistance internal to the diode. At the
lower signal levels, shot noise will dominate. 图 10-6 shows an example of the noise sources present in a
transimpedance amplifier circuit. The total TIA noise is the root sum square of each component within the
system: photodiode noise, amplifier current noise, amplifier voltage noise, and feedback resistor noise.
图10-6. Photodiode and TIA Noise Model
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Interfacing with APDs is similar to interfacing with PIN PDs, but APDs have additional noise factors due to its
internal gain. APDs have increased shot noise and the addition of a multiplication excess noise factor.
Decreasing capacitance, increasing diode shunt resistance, and decreasing reverse voltage bias applied to the
APD deceases noise at the expense of response time. MPPCs' total noise is comparable to APDs, but with
differing noise sources. This optical sensor includes digital-like noise factors such as dark count rate, after
pulsing, and optical crosstalk due to its paralleling gain cells. For PMTs, dark count rate is lower. In general,
PMTs’ total noise is comparable to PDs’ with an internal gain comparable to APDs'. However, PMTs have the
lowest quantum efficiency of the optical sensor space.
10.3.1 Design Requirements
The objective is to design a low noise, wideband optical front-end system using a diverse selection of optical
sensors: PD, APD, PMT, and MPPC with the OPA855 as the TIA. The approximate design requirements for each
type of photodetector are listed in 表10-1.
表10-1. Design Parameters
Sensor
Intrinsic Gain
(A/W)
Reverse Bias (V)
Input
Target
Transimpedance
Total Optical
Gain (kV/W)
Capacitance (pF) Bandwidth (MHz)
Gain RF (kΩ)
PD (PIN)
APD
1
30
150
1250
50
3
1
15
200
100
10
100
10
1
100
100
1000
1×106
5×105
PMT
1×106
5×105
50
100
MPPC (SiPM)
1
10.3.2 Detailed Design Procedure
The OPA855 is decompensated and requires a high-frequency gain of 7V/V or greater to be stable. Using the
OPA855 in lower gains results in increased peaking and potential instability. Decompensated amplifiers are
advantageous in TIA applications due the inherent characteristics of a TIA design. The zero and pole pair
introduced by the input and feedback capacitances along with the feedback resistor increases the noise gain
until it flattens out at a high gain with a magnitude shown in 方程式2.
C
TOT
1 +
(2)
C
F
where
• CTOT is the total input capacitance of the amplifier (includes photodetector capacitance and the common-
mode and differential input capacitance of the amplifier)
• CF is the feedback capacitance of the amplifier
A decompensated amplifier allows for benefits such as increased open loop gain, increased bandwidth,
increased slew rate, and lower input referred noise for the same quiescent current relative to its unity gain stable
counterpart.
Similar to the concept described in 节 10.2.2, the rise time and the internal capacitance of the photodetector will
determine the closed-loop bandwidth. Both the closed-loop bandwidth and the transimpedance gain (RF)
determine the necessary gain bandwidth (GBWP) of the amplifier. 表 10-1 shows the standard photodiode
characteristics based on type of photodetector. Target values such as the system bandwidth and gain were
calculated using these concepts with the chosen photodiode characteristics. Detailed explanations and
equations can be found in the application reports discussed in 节10.2.2.
图10-5 shows the OPA855 configured as a TIA, with the optical sensor reverse biased so that the diode cathode
is tied to the positive bias voltage. A RC filter can be used at the reverse bias node as a low pass filter to
eliminate high frequency noise. The internal capacitance of photodetectors will vary based on sensor type and
the value of the applied reverse voltage. The setups between each sensor type will slightly differ, but the
connection to the amplifier will be consistent throughout.
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The difference between each optical design comprise choosing the optimal feedback resistor to set the
transimpedance gain and the optimal feedback capacitance to compensate for the additional input capacitance.
With an 8 GHz GBWP, the OPA855 can accommodate very fast rise times to pair with emerging optical sensors
to meet the industry’s demands for faster optical detections.
The DC voltage bias at the non-inverting input of the OPA855 shown in 图 10-5 will set the common-mode
voltage which will maximize the output swing of the system in mismatched power supply configurations. The DC
bias is critical to avoid clipping or saturating the output stage of the amplifier. For the later stages, a fully
differential amplifier (FDA) can be used to convert single-ended signal to a differential input to drive an analog-
to-digital converter (ADC) as shown in 图 10-1. Higher order filters can be added between the FDA and ADC for
system noise reduction.
图 10-7 shows the performance that results from the design parameters provided in 表 10-1, and 图 10-8 shows
the general trends. Both figures depict the closed-loop bandwidth performance of the OPA855 configured as a
TIA using different sensor types and gain configurations. 图 10-7 shows the amplifier performance based on the
chosen photodetector from the values provided in 表 10-1. PMTs and MPPCs have higher intrinsic gains, but
requires a wide bandwidth to compensate for its higher internal capacitance. Whereas, PDs and APDs require
higher gain configurations to achieve similar output voltage levels. The OPA855 is able to provide the bandwidth
to accommodate for both optical challenges. 图 10-7 shows a generic view of the amplifier performance as a
function of sensor capacitance and transimpedance gain. Increasing the feedback resistance and input
capacitance, decreases the closed-loop bandwidth. Throughout the trends, the amount of change in closed-loop
bandwidth is consistent in relationship of the changes in both terms. A photodiode capacitance of 1 pF and a
feedback resistance of 1 kΩ results in a very high closed-loop system bandwidth of 1.1 GHz.
10.3.3 Application Curves
图10-7. Optical Sensor TIA Frequency Response 图10-8. 1 Photodetector Input Characteristics TIA
Frequency Response
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图10-9. 2 Photodetector Input Characteristics TIA 图10-10. 3 Photodetector Input Characteristics TIA
Frequency Response
Frequency Response
10.4 Power Supply Recommendations
The OPA855 operates on supplies from 3.3 V to 5.25 V. The OPA855 operates on single-sided supplies, split
and balanced bipolar supplies, and unbalanced bipolar supplies. Because the OPA855 does not feature rail-to-
rail inputs or outputs, the input common-mode and output swing ranges are limited at 3.3-V supplies.
a) Single supply configuration
VS+
VS+
+
2
0.1 …F
6.8 …F
RG
75 ꢀ
RF
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
RT
49.9 ꢀ
VS+
2
VS+
2
b) Split supply configuration
VS+
+
0.1 …F
6.8 …F
RG
RF
75 ꢀ
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
+
RT
49.9 ꢀ
0.1 …F
6.8 …F
VSœ
图10-11. Split and Single Supply Circuit Configuration
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10.5 Layout
10.5.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA855 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output and inverting input pins can cause instability. To reduce unwanted capacitance, cut out the power and
ground traces under the signal input and output pins. Otherwise, ground and power planes must be unbroken
elsewhere on the board. When configuring the amplifier as a TIA, if the required feedback capacitor is less
than 0.15 pF, consider using two series resistors, each of half the value of a single resistor in the feedback
loop to minimize the parasitic capacitance from the resistor.
• Minimize the distance (less than 0.25-in) from the power-supply pins to high-frequency bypass
capacitors. Use high-quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage
ratings at least three times greater than the amplifiers maximum power supplies. This configuration makes
sure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain
bandwidth specification. At the device pins, do not allow the ground and power plane layout to be in close
proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the
pins and the decoupling capacitors. The power-supply connections must always be decoupled with these
capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency must be
used on the supply pins. Place these decoupling capacitors further from the device. Share the decoupling
capacitors among several devices in the same area of the printed circuit board (PCB).
• Careful selection and placement of external components preserves the high-frequency performance
of the OPA855. Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall
layout. Never use wirewound resistors in a high-frequency application. Because the output pin and inverting
input pin are the most sensitive to parasitic capacitance, always position the feedback and series output
resistor, if any, as close to the output pin as possible. Place other network components (such as noninverting
input termination resistors) close to the package. Even with a low parasitic capacitance shunting the external
resistors, high resistor values create significant time constants that can degrade performance. When
configuring the OPA855 as a voltage amplifier, keep resistor values as low as possible and consistent with
load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and minimizes
the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power
consumption because RF and RG become part of the output load network of the amplifier.
10.5.2 Layout Example
Representative schematic
Connect PD to VS+ to enable the
amplifier
VS+
1
2
8
7
CBYP
RS
+
NC (Pin 2) isolates the IN- and FB
pins thereby reducing capacitive
coupling
œ
Thermal
Pad
CBYP
RF
CBYP
Place gain and feedback resistors
close to pins to minimize stray
capacitance
VS-
RF
3
4
6
5
RS
RG
RG
CBYP
Connect the thermal pad to the
negative supply pin
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Place bypass capacitor
close to power pins
图10-12. Layout Recommendation
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When configuring the OPA855 as a transimpedance amplifier additional care must be taken to minimize the
inductance between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the
same side of the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB
increases the parasitic effects due to via inductance. APD packaging can be quite large which often requires the
APD to be placed further away from the amplifier than ideal. The added distance between the two device results
in increased inductance between the APD and op amp feedback network as shown in 图 10-13. The added
inductance is detrimental to a decompensated amplifiers stability since it isolates the APD capacitance from the
noise gain transfer function. The noise gain is given by 方程式 3. The added PCB trace inductance between the
feedback network increases the denominator in 方程式 3 thereby reducing the noise gain and the phase margin.
In cases where a leaded APD in a TO can is used inductance should be further minimized by cutting the leads of
the TO can as short as possible.
The layout shown in 图 10-13 can be improved by following some of the guidelines shown in 图 10-14. The two
key rules to follow are:
• Add an isolation resistor RISO as close as possible to the inverting input of the amplifier. Select the value of
R
ISO to be between 10 Ωand 20 Ω. The resistor dampens the potential resonance caused by the trace
inductance and the amplifiers internal capacitance.
• Close the loop between the feedback elements (RF and CF) and RISO as close to the APD pins as possible.
This ensures a more balanced layout and reduces the inductive isolation between the APD and the feedback
network.
≈
’
÷
ZF
Noise Gain = 1+
∆
ZIN ◊
«
(3)
where
• ZF is the total impedance of the feedback network.
• ZIN is the total impedance of the input network.
Vbias
APD
Package
FB
NC
INœ
IN+
1
2
3
4
8
7
6
5
PD
RF
VS+
CF
Thermal
Pad
OUT
Trace inductance isolates
APD capacitance from the
amplifier noise gain
VSœ
图10-13. Non-Ideal TIA Layout
Vbias
CF
APD
Package
FB
NC
INœ
IN+
1
2
3
4
8
7
6
5
PD
RF
VS+
Close the loop close
to APD pins
Thermal
Pad
OUT
RISO
VSœ
Place RISO close to INœ
图10-14. Improved TIA Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
• LIDAR Pulsed Time of Flight Reference Design
• LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
• Wide Bandwidth Optical Front-end Reference Design
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, OPA855EVM user's guide
• Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow
• Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits
• Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 1
• Texas Instruments What You Need To Know About Transimpedance Amplifiers –Part 2
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Excel® is a registered trademark of Microsoft Corporation.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA855IDSGR
OPA855IDSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
855
855
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jan-2023
OTHER QUALIFIED VERSIONS OF OPA855 :
Automotive : OPA855-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA855IDSGR
OPA855IDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA855IDSGR
OPA855IDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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