OPA856 [TI]
具有 1.1GHz 单位增益带宽、0.9nV/√Hz 噪声的双极输入放大器;
| 型号： | OPA856 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.1GHz 单位增益带宽、0.9nV/√Hz 噪声的双极输入放大器 放大器 |
| 文件： | 总33页 (文件大小：3549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA856
ZHCSM22 – OCTOBER 2020
OPA856 1.1GHz 单位带宽增益积、0.9nV /√Hz， 双极 输入放大器
1 特性
3 说明
•
•
•
•
•
单位带宽增益积：1.1GHz
OPA856 是一款具有双极输入的宽带低噪声运算放大
器，适用于宽带跨阻和电压放大器应用。将该器件配置
为跨阻放大器 (TIA) 时，1.1GHz 增益带宽积 (GBWP)
能够在低电容光电二极管应用中实现高闭环带宽。
增益带宽积：1.1GHz
压摆率：350V/µs
低输入电压噪声：0.9nV/√Hz
低输入电容：
– 共模：0.4pF
– 差动：0.7pF
电源电压范围：3.3V 至 5.25V
封装：8 引脚 WSON
温度范围：–40°C 至 +125°C
下图展示了将 OPA856 配置为 TIA 时，该放大器的
带宽和噪声性能与光电二极管电容的函数关系。计算总
噪声时的带宽范围为从直流到左轴上计算得出的频率
(f )。OPA856 封装具有一个反馈引脚 (FB)，可简化输
入和输出之间的反馈网络连接。
•
•
•
OPA856 经过优化，可在光学飞行时间 (ToF) 系统
中运行，在该系统中，OPA856 与时数转换器（如
TDC7201）配合使用。可在具有差分输出放大器（如
THS4541 或 LMH5401）的高分辨率激光雷达系统中
使用 OPA856 来驱动高速模数转换器 (ADC)。
2 应用
•
•
•
•
•
•
•
•
•
•
光时域反射计 (OTDR)
3D 扫描仪
激光测距
固态扫描激光雷达
光学 ToF 位置传感器
无人机视觉
器件信息
器件型号(1)
OPA856
封装
封装尺寸（标称值）
WSON (8)
2.00 mm × 2.00 mm
工业机器人激光雷达
扫地机器人激光雷达
硅光电倍增器 (SiPM) 缓冲放大器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
光电倍增管后置放大器
CF
450
400
350
300
250
200
150
100
50
135
120
105
90
f-3dB, RF = 1 kW
f-3dB, RF = 5 kW
IRN, RF = 1 kW
IRN, RF = 5 kW
RF
VBIAS
Rx
Lens
5 V
TLV3501
+
œ
3.8 V
+
OPA856
Stop 2
Start 2
VREF
œ
75
CF
RF
60
TDC7201
(Time-to-
Digital
VBIAS
45
5 V
Converter)
TLV3501
+
œ
30
3.8 V
+
OPA856
Stop 1
Start 1
VREF
œ
15
0
0
0
2
4
6
8
10
12
14
Photodiode Capacitance (pF)
16
18
20
Tx
Lens
MSP430
ꢀController
Pulsed Laser
Diode
光电二极管电容与带宽和噪声间的关系
高速飞行时间接收器
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS623
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ...................................................4
7.5 Electrical Characteristics ............................................5
7.6 Typical Characteristics................................................7
7.7 Typical Characteristics (continued)........................... 11
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
10 Power Supply Recommendations..............................23
11 Layout...........................................................................24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................25
12.1 Device Support....................................................... 25
12.2 Documentation Support.......................................... 25
12.3 Receiving Notification of Documentation Updates..25
12.4 支持资源..................................................................25
12.5 Trademarks.............................................................25
12.6 Electrostatic Discharge Caution..............................25
12.7 术语表..................................................................... 25
13 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
DATE
REVISION
NOTES
October 2020
*
Initial Release
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
5 Device Comparison Table
MINIMUM STABLE
GAIN
VOLTAGE NOISE
(nV/√Hz)
INPUT
CAPACITANCE (pF)
GAIN BANDWIDTH
(GHz)
DEVICE
INPUT TYPE
OPA856
OPA855
OPA858
OPA859
Bipolar
Bipolar
CMOS
CMOS
1 V/V
7 V/V
7 V/V
1 V/V
0.9
0.98
2.5
1.1
0.8
0.8
0.8
1.1
8
5.5
0.9
3.3
6 Pin Configuration and Functions
FB
NC
INœ
IN+
1
2
3
4
8
7
PD
VS+
OUT
VSœ
Thermal pad
6
5
Not to scale
图 6-1. DSG Package
8-Pin WSON with Exposed Thermal Pad
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
FB
NO.
1
I
I
Feedback connection to output of amplifier
Inverting input
IN–
3
IN+
4
I
Noninverting input
NC
2
—
O
I
Do not connect.
OUT
PD
6
Amplifier output
8
Power down connection. PD = logic low = power off mode; PD = logic high = normal operation.
VS–
5
—
—
—
Negative voltage supply
VS+
7
Positive voltage supply
Thermal pad
Connect the thermal pad to VS–.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
(VS–) – 0.5
(VS–) – 0.5
MAX
5.5
UNIT
V
VS
Total supply voltage (VS+ – VS–
Input voltage
)
VIN+, VIN–
VID
(VS+) + 0.5
1
V
Differential input voltage
Output voltage
V
VOUT
IIN
(VS+) + 0.5
±10
V
Continuous input current
Continuous output current(2)
Junction temperature
Operating free-air temperature
Storage temperature
mA
mA
°C
°C
°C
IOUT
TJ
±100
150
TA
–40
–65
125
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JS-002, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.3
NOM
MAX
5.25
125
UNIT
V
VS
TA
Total supply voltage (VS+ – VS–
Operating free-air temperature
)
5
–40
°C
7.4 Thermal Information
OPA856
THERMAL METRIC(1)
DSG (WSON)
8 PINS
80.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
100
45
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.8
ΨJB
45.2
RθJC(bot)
22.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.5 Electrical Characteristics
at VS+ = 5 V, VS– = 0 V, G = 1 V/V, RF = 0 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced
to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC PERFORMANCE
SSBW
LSBW
GBWP
Small-signal bandwidth
Large-signal bandwidth
Gain-bandwidth product
Bandwdith for 0.1-dB flatness
Slew rate (10%-90%)
Rise time
VOUT = 100 mVPP
1.1
110
1.08
175
350
0.75
0.75
7
GHz
MHz
GHz
MHz
V/µs
ns
VOUT = 2 VPP
VOUT = 100 mVPP
VOUT = 2-V step
SR
tr
VOUT = 100-mV step
VOUT = 100-mV step
VOUT = 2-V step
tf
Fall time
ns
Settling time to 0.1%
ns
f = 10 MHz, VOUT = 2 VPP
f = 50 MHz, VOUT = 2 VPP
f = 10 MHz, VOUT = 2 VPP
f = 50 MHz, VOUT = 2 VPP
f = 1 MHz
85
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
dBc
50
95
45
en
ei
Input-referred voltage noise
Input-referred current noise
Closed-loop output impedance
0.9
2.5
0.15
nV/√Hz
pA/√Hz
Ω
f = 1 MHz
zO
f = 1 MHz
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
Input offset voltage
70
76
±0.2
0.7
dB
TA = 25°C
–1.5
1.5
–5
1
mV
µV/°C
µA
ΔVOS/ΔT Input offset voltage drift
TA = –40°C to 125°C
TA = 25°C
IB
Input bias current (1)
Input bias current drift
Input offset current
–20
–1
–15
-0.1
±0.1
0.75
106
ΔIB/ΔT
IBOS
TA = –40°C to +125°C
TA = 25°C
µA/°C
µA
ΔIBOS/ΔT Input offset current drift
TA = –40°C to +125°C
VCM = ±0.5 V referred to midsupply
nA/°C
dB
CMRR
INPUT
CCM
CDIFF
VIH
Common-mode rejection ratio
90
Common-mode input capacitance
Differential input capacitance
0.4
0.7
2.9
1.1
4.6
4.3
1.1
1.3
pF
pF
V
Common-mode input range (high)
Common-mode input range (low)
Common-mode input range (high)
Common-mode input range (high)
Common-mode input range (low)
Common-mode input range (low)
CMRR > 80 dB, VS+ = 3.3 V
CMRR > 80 dB, VS+ = 3.3 V
CMRR > 80 dB
2.7
4.4
VIL
1.3
1.3
V
VIH
V
VIH
TA = –40°C to +125 °C, CMRR > 80 dB
CMRR > 80 dB
V
VIL
V
VIL
TA = –40°C to +125°C, CMRR > 80 dB
V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.5 Electrical Characteristics (continued)
at VS+ = 5 V, VS– = 0 V, G = 1 V/V, RF = 0 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced
to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUTPUT
VOH
Output voltage (high)(2)
Output voltage (high)(2)
Output voltage (low)(2)
Output voltage (low)(2)
TA = 25°C, VS+ = 3.3 V
2.35
3.95
2.4
4.1
4
V
V
TA = 25°C
VOH
VOL
VOL
TA = –40°C to +125°C
TA = 25°C, VS+ = 3.3 V
TA = 25°C
1.05
1.05
1.1
80
1.15
1.15
V
V
TA = –40°C to +125°C
RL = 10 Ω, AOL > 60 dB
TA = –40°C to +125°C, RL = 10 Ω, AOL > 60 dB
65
85
IO_LIN
Linear output drive (sink and source)
Output short-circuit current
mA
mA
65
ISC
POWER SUPPLY
105
15.4
17.2
15.5
19.5
86
19.5
IQ
Quiescent current
TA = –40°C
TA = 125°C
mA
dB
PSRR+
PSRR–
Positive power-supply rejection ratio
Negative power-supply rejection ratio
80
70
80
POWER DOWN
Disable voltage threshold
Amplifier OFF below this voltage
Amplifier ON above this voltage
0.65
1
1.5
70
V
V
Enable voltage threshold
Power-down quiescent current
PD bias current
1.8
85
85
μA
μA
ns
ns
70
Turnon time delay
Time to VOUT = 90% of final value
15
Turnoff time delay
250
(1) Current flowing into the input pin is considered negative.
(2) Amplifier output saturated.
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.6 Typical Characteristics
at VS+ = +2.5 V, VS– = –2.5 V, RF = 0 Ω, Gain = 1 V/V, input common-mode biased at midsupply, RL = 200 Ω, output load
referenced to midsupply, and TA = 25°C (unless otherwise noted)
3
3
0
0
-3
-3
-6
-6
G = 1 V/V
G = -1 V/V
G = 2 V/V
G = 5 V/V
G = 20 V/V
-9
-9
RL = 100 W
RL = 200 W
RL = 400 W
-12
-12
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
VOUT = 100 mVPP
VOUT = 100 mVPP
图 7-1. Small-Signal Response vs Gain
图 7-2. Small-Signal Response vs Output Load
3
0
3
0
-3
-6
-3
-6
G = 1 V/V
G = -1 V/V
G = 2 V/V
G = 5 V/V
G = 20 V/V
-9
-9
VCM = 0 V
VCM = 1 V
VCM = -1 V
-12
-12
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency [Hz]
100M
VOUT = 2 VPP
Gain = 20 V/V
VOUT = 100 mVPP
图 7-3. Large-Signal Response vs Gain
图 7-4. Gain Bandwidth vs Common-Mode
10
100
10
1
1.1
1.05
1
Voltage Noise
Current Noise
0.95
0.9
1
0.85
0.8
0.1
0.75
1k
10k
100k 1M
Frequency (Hz)
10M
100M
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
.
Frequency = 10 MHz
图 7-5. Voltage and Current Noise Density
图 7-6. Voltage Noise vs Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.6 Typical Characteristics (continued)
at VS+ = +2.5 V, VS– = –2.5 V, RF = 0 Ω, Gain = 1 V/V, input common-mode biased at midsupply, RL = 200 Ω, output load
referenced to midsupply, and TA = 25°C (unless otherwise noted)
90
75
60
45
30
15
0
100
50
100
10
1
AOL Magnitude
AOL Phase
0
-50
-100
-150
-200
-250
-15
0.1
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M
10M
Frequency (Hz)
100M
Small-Signal Response
Small-Signal Response
图 7-7. Open-Loop Magnitude and Phase
图 7-8. Closed Loop Output Impedance
120
120
100
80
60
40
20
0
PSRR+
PSRR-
100
80
60
40
20
0
10k
100k
1M 10M
Frequency (Hz)
100M
1G
10k
100k
1M 10M
Frequency (Hz)
100M
1G
Small-Signal Response
Small-Signal Response
图 7-9. Common-Mode Rejection Ratio
图 7-10. Power Supply Rejection Ratio
0
-20
-40
-60
-80
0
-20
HD2, VOUT = 0.5 VPP
HD2, VOUT = 1 VPP
HD2, VOUT = 2 VPP
HD2, VOUT = 2.5 VPP
HD3, VOUT = 0.5 VPP
HD3, VOUT = 1 VPP
HD3, VOUT = 2 VPP
HD3, VOUT = 2.5 VPP
-40
-60
-80
-100
-100
-120
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
.
.
图 7-11. Harmonic Distortion (HD2) vs Output Swing
图 7-12. Harmonic Distortion (HD3) vs Output Swing
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.6 Typical Characteristics (continued)
at VS+ = +2.5 V, VS– = –2.5 V, RF = 0 Ω, Gain = 1 V/V, input common-mode biased at midsupply, RL = 200 Ω, output load
referenced to midsupply, and TA = 25°C (unless otherwise noted)
0
0
HD2, RL = 100 W
HD2, RL = 200 W
HD2, RL = 400 W
HD3, RL = 100 W
HD3, RL = 200 W
HD3, RL = 400 W
-20
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
VOUT = 2 VPP
VOUT = 2 VPP
图 7-13. Harmonic Distortion (HD2) vs Load
图 7-14. Harmonic Distortion (HD3) vs Load
0
-20
0
-20
HD2, Gain = 1 V/V
HD2, Gain = -1 V/V
HD2, Gain = 2 V/V
HD2, Gain = 5 V/V
HD3, Gain = 1 V/V
HD3, Gain = -1 V/V
HD3, Gain = 2 V/V
HD3, Gain = 5 V/V
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
VOUT = 2 VPP
VOUT = 2 VPP
图 7-15. Harmonic Distortion (HD2) vs Gain
图 7-16. Harmonic Distortion (HD3) vs Gain
0.06
1.25
Input
Output
1
0.75
0.5
0.04
0.02
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.02
-0.04
-0.06
Input
Output
-1.25
Time (25 ns/div)
Time (25 ns/div)
Average Rise and Fall Time (10% - 90%) = 680 ps
Slew Rate: Rising = 365 V/µs, Falling = 346 V/µs
图 7-17. Small-Signal Transient Response
图 7-18. Large-Signal Transient Response
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.6 Typical Characteristics (continued)
at VS+ = +2.5 V, VS– = –2.5 V, RF = 0 Ω, Gain = 1 V/V, input common-mode biased at midsupply, RL = 200 Ω, output load
referenced to midsupply, and TA = 25°C (unless otherwise noted)
3
3
Power Down (PD)
Output
2
2
1
1
0
0
-1
-2
-3
-1
-2
-3
Power Down (PD)
Output
Time (5 ns/div)
Time (25 ns/div)
.
.
图 7-19. Turnon Transient Response
图 7-20. Turnoff Transient Response
4
Ideal Output
Measured Output
3
2
1
0
-1
-2
-3
-4
Time (10 ns/div)
Gain = 5 V/V, RF = 453 Ω, VIN = 1.25 VPP , 2x Output Overdrive
图 7-21. Output Overload Response
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.7 Typical Characteristics (continued)
at VS+ = +2.5 V, VS– = –2.5 V, RF = 0 Ω, Gain = 1 V/V, input common-mode biased at midsupply, RL = 200 Ω, output load
referenced to midsupply, and TA = 25°C (unless otherwise noted)
17.6
17.4
17.2
17
19
18.5
18
17.5
17
16.8
16.6
16.4
16.2
16
16.5
16
Unit 1
Unit 2
Unit 3
15.5
15
VS = 3.3 V
VS = 5 V
15.8
3
3.25 3.5 3.75
4
Total Supply Voltage (V)
4.25 4.5 4.75
5
5.25
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
3 Typical Units
图 7-22. Quiescent Current vs Supply Voltage
图 7-23. Quiescent Current vs Ambient Temperature
0.25
0.25
Unit 1
Unit 2
Unit 3
0.2
0.15
0.1
0.2
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.05
-0.1
-0.15
3
3.25 3.5 3.75
4
Total Supply Voltage (V)
4.25 4.5 4.75
5
5.25
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
3 Typical Units
σ = 0.7 µV/°C
图 7-24. Offset Voltage vs Supply Voltage
图 7-25. Offset Voltage vs Ambient Temperature
3
3
2
1
2
1
0
0
-1
-2
-3
-1
Unit 1
Unit 2
Unit 3
TA = -40èC
-2
TA = 25èC
TA = 125èC
-3
-1
-2
-1.5
-1
-0.5
Common-Mode Voltage (V)
0
0.5
1
1.5
2
2.5
-0.5
0
Common-Mode Voltage (V)
0.5
1
1.5
3 Typical Units
图 7-26. Offset Voltage vs Input Common-Mode Voltage
图 7-27. Offset Voltage vs Input Common-Mode Voltage vs
Ambient Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.7 Typical Characteristics (continued) (continued)
at VS+ = +2.5 V, VS– = –2.5 V, RF = 0 Ω, Gain = 1 V/V, input common-mode biased at midsupply, RL = 200 Ω, output load
referenced to midsupply, and TA = 25°C (unless otherwise noted)
2
1.5
1
3
2
1
0.5
0
0
-0.5
-1
-1
-2
-3
Unit 1
Unit 2
Unit 3
TA = -40èC
TA = 25èC
TA = 125èC
-1.5
-2
-2
-1.5
-1
-0.5
Output Voltage (V)
0
0.5
1
1.5
2
-2
-1.5
-1
-0.5
Output Voltage (V)
0
0.5
1
1.5
2
3 Typical Units
图 7-28. Offset Voltage vs Output Swing
图 7-29. Offset Voltage vs Output Swing vs Ambient
Temperature
-10
-12
-14
-16
-18
-20
-22
-24
-10
-12.5
-15
Unit 1
Unit 2
Unit 3
-17.5
-20
-22.5
-25
TA = -40èC
TA = 25èC
-27.5
TA = 125èC
-30
-2 -1.5 -1 -0.5
Common-Mode Voltage (V)
-40
-20
0
20
40
60
80
100 120 140
0
0.5
1
1.5
2
2.5
3
Ambient Temperature (èC)
3 Typical Units
图 7-30. Input Bias Current vs Ambient Temperature
图 7-31. Input Bias Current vs Input Common-Mode Voltage
0
2.5
TA = -40èC
TA = 25èC
TA = 125èC
-0.5
-1
2
1.5
1
-1.5
-2
0.5
0
TA = -40èC
TA = 25èC
TA = 125èC
-2.5
-125
-100
-75 -50
Output Current (mA)
-25
0
0
25
50 75
Output Current (mA)
100
125
Output slammed to the negative rail
Output slammed to the positive rail
图 7-33. Output Swing vs Sourcing Current
图 7-32. Output Swing vs Sinking Current
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
7.7 Typical Characteristics (continued) (continued)
at VS+ = +2.5 V, VS– = –2.5 V, RF = 0 Ω, Gain = 1 V/V, input common-mode biased at midsupply, RL = 200 Ω, output load
referenced to midsupply, and TA = 25°C (unless otherwise noted)
5000
4000
3000
2000
1000
0
6000
5000
4000
3000
2000
1000
0
Quiescent Current (mA)
Offset Voltage (mV)
σ = 0.2 mA
σ = 0.12 mV
图 7-34. Quiescent Current Distribution
图 7-35. Offset Voltage Distribution
6000
5000
4000
3000
2000
1000
0
6000
5000
4000
3000
2000
1000
0
Noninverting Current
Inverting Current
Input Bias Current (mA)
Input Offset Current (mA)
σ = 1 µA
σ = 0.1 µA
图 7-36. Input Bias Current Distribution
图 7-37. Input Offset Current Distribution
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
8 Detailed Description
8.1 Overview
The ultra-wide, 1.1-GHz gain bandwidth product (GBWP) of the OPA856, combined with the broadband voltage
noise of 0.9 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed data
acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front ends.
The OPA856 combines multiple features to optimize dynamic performance. In addition to the wide, small-signal
bandwidth, the OPA856 has 110 MHz of large-signal bandwidth (VOUT = 2 VPP), and a slew rate of 350 V/µs.
The OPA856 is offered in a 2-mm × 2-mm, 8-pin WSON package that features a feedback (FB) pin for a simple
feedback network connection between the amplifiers output and inverting input. Excess capacitance on an
amplifiers input pin can reduce phase margin causing instability. This problem is exacerbated in the case of very
wideband amplifiers like the OPA856. To reduce the effects of stray capacitance on the input node, the OPA856
pinout features an isolation pin (NC) between the feedback and inverting input pins that increases the physical
spacing between them thereby reducing parasitic coupling at high frequencies. The OPA856 also features a very
low capacitance input stage with only 1.1-pF of total input capacitance.
8.2 Functional Block Diagram
The OPA856 is a classic voltage feedback operational amplifier (op amp) with two high-impedance inputs and
a low-impedance output. Standard application circuits are supported, like the two basic options shown in 图 8-1
and 图 8-2. The resistor on the noninverting pin is used for bias current cancellation to minimize the output
offset voltage. In a noninverting configuration the additional resistors on the noninverting pin add noise to the
system so if SNR is critical, the resistor can be eliminated. In an inverting configuration the noninverting node is
typically connected to a DC voltage, so the high-frequency noise contribution from the bias cancellation resistor
can be bypassed by adding a large 1-µF capacitor in parallel to the resistor to shunt the noise. The DC operating
point for each configuration is level-shifted by the reference voltage (VREF), which is typically set to midsupply in
single-supply operation. VREF is typically connected to ground in split-supply applications.
VSIG
VS+
RF || RG
(1+RF/RG)×VSIG
VREF
VIN
+
VOUT
VREF
œ
RG
VSœ
RF
VREF
图 8-1. Noninverting Amplifier
VS+
RF || RG
œ(RF/RG)×VSIG
VREF
VIN
+
VSIG
VOUT
VREF
VREF
œ
RG
VSœ
RF
图 8-2. Inverting Amplifier
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
8.3 Feature Description
8.3.1 Input and ESD Protection
The OPA856 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown
voltages are low for these small geometry devices, and as a result, all device pins are protected with internal
ESD protection diodes to the power supplies as 图 8-3 shows. There are two antiparallel diodes between the
inputs of the amplifier that clamp the inputs during an overrange or fault condition.
VS+
Power Supply
ESD Cell
VIN+
+
VOUT
œ
VINÞ
FB
VSÞ
图 8-3. Internal ESD Structure
8.3.2 Feedback Pin
The OPA856 pin layout is optimized to minimize parasitic inductance and capacitance, which is a critical care
about in high-speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The
FB pin is separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin
must be left floating. There are two advantages to this pin layout:
1. A feedback resistor (RF) can connect between the FB and IN– pin on the same side of the package (see 图
8-4) rather than going around the package.
2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by
increasing the physical separation between the pins.
FB
NC
INœ
IN+
PD
1
2
3
4
8
7
6
5
VS+
OUT
VSœ
RF
œ
+
图 8-4. RF Connection Between FB and IN– Pins
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
8.3.3 Wide Gain-Bandwidth Product
图 7-7 shows the open-loop magnitude and phase response of the OPA856. Calculate the gain bandwidth
product of any op amp by determining the frequency at which the AOL is 40 dB and multiplying that frequency by
a factor of 100. The open-loop response shows the OPA856 to have approximately 57° of phase-margin when
configured as a unity-gain buffer.
图 8-5 shows the open-loop magnitude (AOL) of the OPA856 as a function of temperature. The results show
minimal variation over the entire temperature range. Semiconductor process variation is the naturally occurring
variation in the attributes of a transistor (Early-voltage, β, channel-length, and width) and other passive elements
(resistors and capacitors) when fabricated into an integrated circuit. The process variation can occur across
devices on a single wafer or across devices over multiple wafer lots over time. Typically the variation across
a single wafer is tightly controlled. 图 8-6 shows the AOL magnitude of the OPA856 as a function of process
variation over time. The results show the AOL curve for the nominal process corner and the variation one
standard deviation from the nominal. The simulated results show less than 5° of phase-margin difference within
a standard deviation of process variation when the amplifier is configured as a unity-gain bufffer.
90
75
60
45
30
15
0
90
75
60
45
30
15
0
AOL at 125èC
AOL at 25èC
AOL at -40èC
AOL (-1s)
AOL (Typ.)
AOL (+1s)
-15
-15
10k
100k
1M 10M
Frequency (Hz)
100M
1G
10k
100k
1M 10M
Frequency (Hz)
100M
1G
图 8-5. Open-Loop Gain vs Temperature
图 8-6. Open-Loop Gain vs Process Variation
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
8.3.4 Slew Rate and Output Stage
In addition to wide bandwidth, the OPA856 features a high slew rate of 2750 V/µs. The slew rate is a
critical parameter in high-speed pulse applications with narrow sub-10-ns pulses, such as optical time-domain
reflectometry (OTDR) and LIDAR. The high slew rate of the OPA856 implies that the device accurately
reproduces a 2-V, sub-ns pulse edge, as seen in 图 7-18. The wide bandwidth and slew rate of the OPA856
make it an excellent amplifier for high-speed signal-chain front ends.
图 8-7 shows the open-loop output impedance of the OPA856 as a function of frequency. To achieve high slew
rates and low output impedance across frequency, the output swing of the OPA856 is limited to approximately
3 V. The OPA856 is typically used in conjunction with high-speed pipeline ADCs and flash ADCs that have
limited input ranges. Therefore, the OPA856 output swing range coupled with the class-leading voltage noise
specification maximizes the overall dynamic range of the signal chain.
30
25
20
15
10
5
0
10k
100k
1M
10M 100M
Frequency (Hz)
1G
10G
图 8-7. Open-Loop Output Impedance (ZOL) vs Frequency
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
8.4 Device Functional Modes
8.4.1 Split-Supply and Single-Supply Operation
The OPA856 can be configured with single-sided supplies or split-supplies as shown in 图 10-1. Split-supply
operation using balanced supplies with the input common-mode set to ground eases lab testing because most
signal generators, network analyzers, spectrum analyzers, and other lab equipment typically reference inputs
and outputs to ground. In split-supply operation, the thermal pad must be connected to the negative supply.
Newer systems use a single power supply to improve efficiency and reduce the cost of the extra power
supply. The OPA856 can be used with a single positive supply (negative supply at ground) with no change in
performance if the input common-mode and output swing are biased within the linear operation of the device. In
single-supply operation, level shift the DC input and output reference voltages by half the difference between the
power supply rails. This configuration maintains the input common-mode and output load reference at midsupply.
To eliminate gain errors, the source driving the reference input common-mode voltage must have low output
impedance across the frequency range of interest. In this case, the thermal pad must be connected to ground.
8.4.2 Power-Down Mode
The OPA856 features a power-down mode to reduce the quiescent current to conserve power. 图 7-19 and
图 7-20 show the transient response of the OPA856 as the PD pin toggles between the disabled and enabled
states.
The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is
configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable
threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65 V supplies, then
the threshold voltages are at –1 V and 0.15 V. If the amplifier is configured with ±2.5 V supplies, then the
threshold voltages are at –1.85 V and –0.7 V.
图 8-8 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled state to
the disabled state. Similarly, 图 8-9 shows the switching behavior of a typical amplifier as the PD pin is swept up
from the disabled state to the enabled state. The small difference in the switching thresholds between the down
sweep and the up sweep is caused by the hysteresis designed into the amplifier to increase immunity to noise
on the PD pin.
20
17.5
15
20
17.5
15
12.5
10
12.5
10
7.5
5
7.5
5
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
2.5
0
2.5
0
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
Power-Down Voltage (V)
图 8-8. Switching Threshold
(PD Pin Swept from High to Low)
Power-Down Voltage (V)
图 8-9. Switching Threshold
(PD Pin Swept from Low to High)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When
the amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form
a parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA856 uses
internal, back-to-back protection diodes between the inverting and noninverting input pins as 图 8-3 shows. In
the power-down state, if the differential voltage between the input pins of the amplifier exceeds a diode voltage
drop, an additional low-impedance path is created between the noninverting input pin and the output pin.
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The OPA856 offers over 1 GHz of bandwidth, high slew-rate, low noise, excellent linearity, and is stable for unity
gain applications. The low noise and unity gain stability make the OPA856 a great choice for use as a front-end
buffer in high-speed data acquisition systems. Additionally the wide bandwidth allows the amplifier to perform
excellently in transimpedance applications or in a high-gain active filter configuration.
9.2 Typical Application
The high GBWP of the OPA856 makes the device an excellent choice as a transimpedance amplifier while the
unity gain stability allows for use of feedback clamping or other unity gain circuitry that would not work for a
decompensated amplifier. 图 9-1 shows the OPA856 configured as a transimpedance amplifier with an option
feedback clamping diode connection.
CF
VBIAS
RF
œ
VOUT
+
VOFFSET
图 9-1. OPA856 Transimpedance Amplifier with Optional Diode Clamping
9.2.1 Design Requirements
The objective is to design a low noise, wideband optical front-end system using the OPA856
as a transimpedance amplifier. The design requirements are:
•
•
•
•
Amplifier supply voltage: ± 2.5 V
1 kΩ transimpedance gain
Transimpedance bandwidth > 100 MHz
Total input capacitance 4 pF (1.1 pF from amplifier)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
9.2.2 Detailed Design Procedure
The OPA856 meets the growing demand for wideband, low-noise photodiode amplifiers. The closed-loop
bandwidth of a transimpedance amplifier is a function of the following:
1. The total input capacitance (CIN). This total includes the photodiode capacitance, the input capacitance of
the amplifier (common-mode and differential capacitance) and any stray capacitance from the PCB.
2. The op amp gain bandwidth product (GBWP).
3. The transimpedance gain (RF).
图 9-1 shows the OPA856 configured as a TIA, with the photodiode reverse biased so that the diode cathode
is tied to a positive bias voltage. In this configuration, the diode sources current into the op amp feedback loop
so that the output swings in a negative direction relative to the input common-mode (VOFFSET) voltage. The
feedback resistance (RF) and the input capacitance (CIN) form a zero in the noise gain that results in instability
if left unchecked. To counteract the effect of the zero, a pole is inserted into the noise gain transfer function by
adding the feedback capacitor (CF).
The Transimpedance Considerations for High-Speed Amplifiers Application Report discusses theories and
equations that show how to compensate a transimpedance amplifier for a particular transimpedance gain and
input capacitance. The bandwidth and compensation equations from the application report are available in a
Microsoft Excel ™ calculator. What You Need To Know About Transimpedance Amplifiers – Part 1 provides a
link to the calculator. Calculating the expected bandwidth with an approximate input capacitance of 4 pF and a
feedback capacitor of 1 pF yields a bandwidth of approximately 200 MHz.
The amplifier was tested in a transimpedance configuration by using a photodiode with an optical fiber input
connection. A tunable laser connected through an optical modulator was used to create the modulated optical
excitation to the photodiode. 图 9-2 shows the test setup configuration for the frequency response measurement.
The network analyzer's swept frequency output drives the optical modulators electrical input which in turn drives
the photodiode. The OPA856 output drives the network analyzer's input.
Network Analyzer
Tunable Laser
-
ON
OFF
1330 nm
-
-
1 pF
5V
1 kΩ
200-Ω load matched
to 50-Ω input
Optical
Modulator
169 ꢀ
œ
Fiber connected
photodiode
+
OPA856
71.5 ꢀ
图 9-2. OPA856 Transimpedance Frequency Response Test Setup
图 9-4 shows the frequency response measurements for a small signal and large signal (~1 Vpp) output. The
plot contains noticeable noise and variations because the test environment did not have complete capability
to accurately manage the thermal drift, perform optical connection integrity analysis, and calibrate the optical
path. A more stringently controlled optical environment could achieve more stable results, but was beyond the
scope of these measurements. The results in 图 9-4 correlate well with predicted results of approximately 200
MHz of bandwidth. It is expected that the results would not perfectly match calculated values because it is
challenging to perfectly account for all parasitic capacitances that affect the input and feedback capacitance in
the transimpedance calculations.
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
Many transimpedance applications can have unpredicted, large input currents that can cause the amplifier's
output to saturate. It is often important to understand how the amplifier will behave when its output is saturated
at various levels of overdrive. A typical linear amplifier like the OPA856 can be expected to have an output
saturation recovery time that increases as the amount of output overdrive increases. When using a pulse based
input signal, the output saturation recovery time effectively extends the duration of the pulse. 图 9-3 shows the
test setup configuration to measure a pulsed optical input to the OPA856. The optical modulator used in the test
setup had limited output amplitude capability to create a saturated signal. In order to prevent the modulator from
saturating, the OPA856 output was saturated by adjusting VOFFSET close to the the amplifier's output swing
limit on the negative rail.
Pulse Generator
Tunable Laser
1V
ON
OFF
1 pF
1330 nm
5V
1 kΩ
Oscilloscope
200-Ω load matched
to 50-Ω input
Optical
Modulator
169 ꢀ
œ
-
-
-
Fiber connected
photodiode
+
OPA856
71.5 ꢀ
+
VOFFSET
œ
图 9-3. OPA856 Transimpedance Pulse Saturation Extention Test Setup
图 9-5 shows the resulting shifted output pulses labelled by the magnitude of voltage they are overdriving the
amplifiers output saturation voltage level (VOV). These values only serve as approximations of the overdrive level
of the signal because of expected variances from the optical interface setup. 图 9-6 shows a magnified view of
the rising edge of the measured pulse responses in order to better detail the pulse extension created by the
signal overdrive. These plots have been scaled and normalized to be easier to read and compare. As expected,
图 9-6 shows that the pulse duration is extended as the overdrive level increases. The data only captured an
overdrive voltage maximum of 640 mV, but it can be expected that larger voltages would extend the pulse
further.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
9.2.3 Application Curves
备注
图 9-6 output voltages are scaled for visual comparison purposes and are not the actual measured
values. See 图 9-5 for actual measured values.
图 9-5. Transimpedance Pulse Response
图 9-4. Transimpedance Frequency Response
图 9-6. Transimpedance Pulse Response Magnified and Scaled
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
10 Power Supply Recommendations
The OPA856 operates on supplies from 3.3 V to 5.25 V. The OPA856 operates on single-sided supplies,
split and balanced bipolar supplies, and unbalanced bipolar supplies. Because the OPA856 does not feature
rail-to-rail inputs or outputs, the input common-mode and output swing ranges are limited at 3.3-V supplies.
a) Single supply configuration
VS+
VS+
+
2
0.1 …F
6.8 …F
RG
75 ꢀ
RF
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
RT
49.9 ꢀ
VS+
2
VS+
2
b) Split supply configuration
VS+
+
0.1 …F
6.8 …F
RG
RF
75 ꢀ
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
+
RT
49.9 ꢀ
0.1 …F
6.8 …F
VSœ
图 10-1. Split and Single Supply Circuit Configuration
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA856 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
•
Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output and inverting input pins can cause instability. To reduce unwanted capacitance, cut out the power and
ground traces under the signal input and output pins. Otherwise, ground and power planes must be unbroken
elsewhere on the board. When configuring the amplifier as a TIA, if the required feedback capacitor is less
than 0.15 pF, consider using two series resistors, each of half the value of a single resistor in the feedback
loop to minimize the parasitic capacitance from the resistor.
•
Minimize the distance (less than 0.25-in) from the power-supply pins to high-frequency bypass
capacitors. Use high-quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage
ratings at least three times greater than the amplifiers maximum power supplies. This configuration makes
sure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain
bandwidth specification. At the device pins, do not allow the ground and power plane layout to be in close
proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the
pins and the decoupling capacitors. The power-supply connections must always be decoupled with these
capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency must be
used on the supply pins. Place these decoupling capacitors further from the device. Share the decoupling
capacitors among several devices in the same area of the printed circuit board (PCB).
•
Careful selection and placement of external components preserves the high-frequency performance
of the OPA856. Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall
layout. Never use wirewound resistors in a high-frequency application. Because the output pin and inverting
input pin are the most sensitive to parasitic capacitance, always position the feedback and series output
resistor, if any, as close to the output pin as possible. Place other network components (such as noninverting
input termination resistors) close to the package. Even with a low parasitic capacitance shunting the
external resistors, high resistor values create significant time constants that can degrade performance. When
configuring the OPA856 as a voltage amplifier, keep resistor values as low as possible and consistent
with load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and
minimizes the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power
consumption because RF and RG become part of the output load network of the amplifier.
11.2 Layout Example
Representative schematic
Connect PD to VS+ to enable the
amplifier
VS+
1
2
8
7
CBYP
RS
+
NC (Pin 2) isolates the IN- and FB
pins thereby reducing capacitive
coupling
œ
Thermal
Pad
CBYP
RF
CBYP
Place gain and feedback resistors
close to pins to minimize stray
capacitance
VS-
RF
3
4
6
5
RS
RG
RG
CBYP
Connect the thermal pad to the
negative supply pin
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Place bypass capacitor
close to power pins
图 11-1. Layout Recommendation
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: OPA856
OPA856
ZHCSM22 – OCTOBER 2020
www.ti.com.cn
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
•
•
•
LIDAR Pulsed Time of Flight Reference Design
LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
Wide Bandwidth Optical Front-end Reference Design
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
Texas Instruments, OPA855EVM user's guide
Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow
Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits
Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model
Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
Texas Instruments, What You Need To Know About Transimpedance Amplifiers – Part 1
Texas Instruments What You Need To Know About Transimpedance Amplifiers – Part 2
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: OPA856
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA856IDSGR
ACTIVE
WSON
DSG
8
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
856
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA856IDSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DSG
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
OPA856IDSGR
8
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
OPA858-Q1_V01
OPA858-Q1 5.5-GHz Gain Bandwidth Product, Gain of 7-V/V Stable, FET Input Amplifier
TI
©2020 ICPDF网 联系我们和版权申明