OPA859Q1DSGR [TI]
OPA859-Q1 1.8-GHz Unity-Gain Bandwidth, 3.3-nV/âHz, FET Input Amplifier;
| 型号： | OPA859Q1DSGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPA859-Q1 1.8-GHz Unity-Gain Bandwidth, 3.3-nV/âHz, FET Input Amplifier |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA859-Q1
SBOSA59 – FEBRUARY 2021
OPA859-Q1 1.8-GHz Unity-Gain Bandwidth, 3.3-nV/√Hz, FET Input Amplifier
1 Features
3 Description
•
AEC-Q100 Qualified for Automotive Applications:
– Temperature grade 1: –40°C to +125°C, TA
High Unity-Gain Bandwidth: 1.8 GHz
Gain Bandwidth Product: 900 MHz
Ultra-Low Bias Current MOSFET Inputs: 10 pA
Low Input Voltage Noise: 3.3 nV/√Hz
Slew Rate: 1150 V/µs
Low Input Capacitance:
– Common-Mode: 0.6 pF
– Differential: 0.2 pF
Wide Input Common-Mode Range:
– 1.4 V from Positive Supply
The OPA859-Q1 is a wideband, low-noise operational
amplifier with CMOS inputs for wideband
transimpedance and voltage amplifier applications.
When the device is configured as a transimpedance
amplifier (TIA), the 0.9-GHz gain bandwidth product
(GBWP) enables high closed-loop bandwidths in low-
capacitance photodiode applications.
•
•
•
•
•
•
The graph below shows the bandwidth and noise
performance of the OPA859-Q1 as a function of the
photodiode capacitance when the amplifier is
configured as a TIA. The total noise is calculated
along a bandwidth range extending from DC to the
calculated frequency (f) on the left scale. The
OPA859-Q1 package has a feedback pin (FB) that
simplifies the feedback network connection between
the input and the output.
•
– Includes Negative Supply
•
•
•
•
•
2.5 VPP Output Swing in TIA Configuration
Supply Voltage Range: 3.3 V to 5.25 V
Quiescent Current: 20.5 mA
Package: 8-Pin WSON
Temperature Range: –40°C to +125°C
The OPA859-Q1 is optimized to operate in optical
time-of-flight (ToF) systems where the OPA859-Q1 is
used with time-to-digital converters, such as the
TDC7201. Use the OPA859-Q1 to drive a high-speed
analog-to-digital converter (ADC) in high-resolution
LIDAR systems with a differential output amplifier,
such as the THS4541-Q1.
2 Applications
•
•
•
•
•
•
•
•
•
•
Automotive LIDAR
Time of flight (ToF) Camera
Optical Time Domain Reflectometry (OTDR)
3D Scanner
Laser Distance Measurement
Solid-State Scanning LIDAR
Optical ToF Position Sensor
Drone Vision
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
OPA859-Q1
WSON (8)
2.00 mm × 2.00 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
Silicon Photomultiplier (SiPM) Buffer Amplifier
Photomultiplier Tube Post Amplifier
CF
225
150
135
120
105
90
f-3dB, RF = 2 kW
200
f-3dB, RF = 5 kW
RF
VBIAS
IRN, RF = 2 kW
IRN, RF = 5 kW
Rx
Lens
175
5 V
TLV3501
+
œ
150
125
100
75
3.5 V
+
OPA859
Stop 2
Start 2
VREF
œ
CF
RF
75
TDC7201
(Time-to-
Digital
VBIAS
60
5 V
Converter)
TLV3501
+
œ
50
45
3.5 V
+
OPA859
Stop 1
Start 1
VREF
œ
25
30
0
15
0
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
18
20
Tx
Lens
D409
MSP430
ꢀController
Pulsed Laser
Diode
Photodiode Capacitance vs Bandwidth and Noise
High-Speed Time-of-Flight Receiver
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA859-Q1
SBOSA59 – FEBRUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics................................................8
7 Parameter Measurement Information..........................15
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 21
10 Power Supply Recommendations..............................23
11 Layout...........................................................................24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................25
12.1 Device Support....................................................... 25
12.2 Documentation Support.......................................... 25
12.3 Receiving Notification of Documentation Updates..25
12.4 Support Resources................................................. 25
12.5 Trademarks.............................................................25
12.6 Electrostatic Discharge Caution..............................25
12.7 Glossary..................................................................25
13 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
February 2021
*
Initial Release
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Device Comparison Table
MINIMUM
STABLE GAIN
VOLTAGE
NOISE (nV/√ Hz)
INPUT
CAPACITANCE (pF)
GAIN
BANDWIDTH (GHz)
DEVICE
INPUT TYPE
OPA855-Q1
OPA858-Q1
OPA859-Q1
Bipolar
CMOS
CMOS
7 V/V
7 V/V
1 V/V
0.98
2.5
0.8
0.8
0.8
8
5.5
0.9
3.3
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5 Pin Configuration and Functions
FB
NC
INœ
IN+
1
2
3
4
8
7
6
5
PD
VS+
OUT
VSœ
Thermal pad
Not to scale
Figure 5-1. DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
FB
NO.
1
I
I
Feedback connection to output of amplifier
Inverting input
IN–
3
IN+
4
I
Noninverting input
NC
2
—
O
I
Do not connect
OUT
PD
6
Amplifier output
8
Power down connection. PD = logic low = power off mode; PD = logic high = normal operation.
VS–
VS+
5
—
—
—
Negative voltage supply
Positive voltage supply
7
Thermal pad
Connect the thermal pad to VS–
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
(VS–) – 0.5
(VS–) – 0.5
MAX
5.5
UNIT
V
VS
Total supply voltage (VS+ – VS–
Input voltage
)
VIN+, VIN–
VID
(VS+) + 0.5
1
V
Differential input voltage
Output voltage
V
VOUT
IIN
(VS+) + 0.5
±10
V
Continuous input current
Continuous output current(2)
Junction temperature
Operating free-air temperature
Storage temperature
mA
mA
°C
°C
°C
IOUT
TJ
±100
150
TA
–40
–65
125
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Long-term continuous output current for electromigration limits.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
± 1500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.3
NOM
MAX
5.25
125
UNIT
V
VS
TA
Total supply voltage (VS+ – VS–
Operating free-air temperature
)
5
–40
°C
6.4 Thermal Information
OPA859-Q1
THERMAL METRIC(1)
DSG (WSON)
8 PINS
80.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
100
45
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.8
ΨJB
45.2
RθJC(bot)
22.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VS+ = 5 V, VS- = 0 V, input common-mode biased at midsupply, unity gain configuration, RL = 200 Ω, output load is referenced
to midsupply, and TA ≈ +25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
LSBW
GBWP
Small-signal bandwidth
Large-signal bandwidth
Gain-bandwidth product
Bandwidth for 0.1dB flatness
Slew rate (10% - 90%)
Rise time
VOUT = 100 mVPP
1.8
400
900
140
1150
0.3
0.3
8
GHz
MHz
MHz
MHz
V/µs
ns
VOUT = 2 VPP
SR
tr
VOUT = 2-V step
VOUT = 100-mV step
VOUT = 100-mV step
VOUT = 2-V step
tf
Fall time
ns
Settling time to 0.1%
Settling time to 0.001%
Overshoot/undershoot
ns
VOUT = 2-V step
3000
7%
90
ns
VOUT = 2-V step
f = 10 MHz, VOUT = 2 VPP
f = 100 MHz, VOUT = 2 VPP
f = 10 MHz, VOUT = 2 VPP
f = 100 MHz, VOUT = 2 VPP
f = 1 MHz
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
60
86
dBc
dBc
64
en
Input-referred voltage noise
3.3
0.15
nV/√Hz
Ω
ZOUT
Closed-loop output impedance
f = 1 MHz
DC PERFORMANCE
AOL
Open-loop voltage gain
60
–5
65
±0.9
–2
dB
mV
µV/°C
pA
VOS
Input offset voltage
TA = 25°C
5
ΔVOS/ΔT
IBN, IBI
IBOS
Input offset voltage drift
Input bias current
TA = –40°C to +125°C
TA = 25°C
–5
–5
70
±0.5
±0.1
84
5
5
Input offset current
TA = 25°C
pA
CMRR
INPUT
Common-mode rejection ratio
VCM = ±0.5 V
dB
Common-mode input resistance
Common-mode input capacitance
Differential input resistance
1
0.62
1
GΩ
pF
GΩ
pF
V
CCM
CDIFF
VIH
Differential input capacitance
Common-mode input range (high)
Common-mode input range (low)
0.2
1.9
0
VS+ = 3.3 V, CMRR > 66 dB
VS+ = 3.3 V, CMRR > 66 dB
CMRR > 66 dB
1.7
3.4
VIL
0.4
V
3.6
3.3
0
VIH
VIL
Common-mode input range (high)
Common-mode input range (low)
V
V
TA = –40°C to +125°C, CMRR > 66 dB
CMRR > 66 dB
0.4
TA = –40°C to +125°C, CMRR > 66 dB
0.35
0.45
OUTPUT
VOH
Output voltage (high)
Output voltage (high)
Output voltage (low)
Output voltage (low)
VS+ = 3.3 V, TA = 25°C
TA = 25°C
2.3
2.4
4.1
V
V
V
V
3.95
VOH
VOL
VOL
TA = –40°C to +125°C
VS+ = 3.3 V, TA = 25°C
TA = 25°C
3.9
1.05
1.1
1.15
1.15
TA = –40°C to +125°C
1.2
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6.5 Electrical Characteristics (continued)
VS+ = 5 V, VS- = 0 V, input common-mode biased at midsupply, unity gain configuration, RL = 200 Ω, output load is referenced
to midsupply, and TA ≈ +25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
RL = 10 Ω, AOL > 52 dB
65
76
IO_LIN
Linear output drive (sink and source)
Output short-circuit current
TA = –40°C to +125°C, RL = 10 Ω,
AOL > 52 dB
64
ISC
POWER SUPPLY
85
105
mA
VS+ = 5 V
18
17.5
18
20.5
20
24
23.5
24
VS+ = 3.3 V
VS+ = 5.25 V
TA = 125°C
TA = –40°C
IQ
Quiescent current
21
mA
dB
24.5
18.5
74
PSRR+
PSRR–
Positive power-supply rejection ratio
Negative power-supply rejection ratio
66
64
72
POWER DOWN
Disable voltage threshold
Amplifier OFF below this voltage
Amplifier ON above this voltage
0.65
1
1.5
70
V
V
Enable voltage threshold
Power-down quiescent current
PD bias current
1.8
140
200
µA
µA
ns
ns
70
Turnon time delay
Time to VOUT = 90% of final value
25
Turnoff time delay
120
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6.6 Typical Characteristics
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
3
3
0
0
-3
-3
-6
-6
Gain = +1 V/V
Gain = -1 V/V
Gain = +2 V/V
Gain = +5 V/V
Gain = +20 V/V
-9
-9
VS = 3.3 V
VS = 5 V
-12
-12
1M
10M
100M
Frequency (Hz)
1G
5G
1M
10M
100M
Frequency (Hz)
1G
5G
D302
D300
VOUT = 100 mVPP
VOUT = 100 mVPP; see Section 7 for circuit configuration
Figure 6-2. Small-Signal Frequency Response vs Supply
Voltage
Figure 6-1. Small-Signal Frequency Response vs Gain
3
0
2
1
0
-1
-2
-3
-4
-3
-6
-5
TA = 125èC
TA = 85èC
-9
-6
RL = 100 W
TA = 25èC
RL = 200 W
RL = 400 W
-12
TA = 0èC
-7
TA = -40èC
-8
1M
10M
100M
Frequency (Hz)
1G
5G
1M
10M
100M
Frequency (Hz)
1G
5G
D303
D304
VOUT = 100 mVPP
VOUT = 100 mVPP
Figure 6-3. Small-Signal Frequency Response vs Output Load
Figure 6-4. Small-Signal Frequency Response vs Ambient
Temperature
3
0
4
2
0
-3
-6
-9
-2
-4
-6
-8
RS = 18 W, CL = 10 pF
VS = ê1.65 V, VOUT = 100 mVPP, VCM = 0 V
RS = 9.1 W, CL = 47 pF
-12
-10
VS = ê2.5 V, VOUT = 100 mVPP, VCM = 0.9 V
RS = 6.2 W, CL = 100 pF
RS = 2 W, CL = 1 nF
VS = ê2.5 V, VOUT = 2 VPP, VCM = 0 V
-15
-12
1M
10M
Frequency (Hz)
100M
1M
10M
100M
Frequency (Hz)
1G
D301
D305
Gain = 20 V/V
RF = 453 Ω
VOUT = 100 mVPP, See Figure 7-4 for circuit configuration
Figure 6-5. Frequency Response at Gain = 20 V/V
Figure 6-6. Small-Signal Frequency Response vs Capacitive
Load
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
3
0.2
0.1
0
0
-3
-0.1
-0.2
-0.3
-0.4
-0.5
-6
Gain = +1 V/V
Gain = -1 V/V
Gain = +2 V/V
Gain = +5 V/V
Gain = +20 V/V
-9
-12
1M
10M
100M
Frequency (Hz)
1G
1M
10M
Frequency (Hz)
100M
D306
D307
VOUT = 2 VPP
VOUT = 2 VPP
Figure 6-7. Large-Signal Frequency Response vs Gain
Figure 6-8. Large-Signal Response for 0.1-dB Gain Flatness
100
75
60
45
30
15
0
45
AOL Magnitude (dB)
AOL Phase (è)
0
10
1
-45
-90
-135
-180
-225
0.1
0.01
-15
100k
1M
10M
Frequency (Hz)
100M
10k
100k
1M 10M
Frequency (Hz)
100M
1G
D309
D310
Small-Signal Response
Small-Signal Response
Figure 6-9. Closed-Loop Output Impedance vs Frequency
Figure 6-10. Open-Loop Magnitude and Phase vs Frequency
100
4
3.8
3.6
3.4
3.2
3
10
2.8
2.6
1
1k
10k
100k 1M
Frequency (Hz)
10M
100M
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D311
D312
Frequency 10 MHz
Figure 6-11. Voltage Noise Density vs Frequency
Figure 6-12. Voltage Noise Density vs Ambient Temperature
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
-40
-50
-40
-50
HD2, VOUT = 0.5 VPP
HD2, VOUT = 1 VPP
HD2, VOUT = 2 VPP
HD2, VOUT = 2.5 VPP
HD3, VOUT = 0.5 VPP
HD3, VOUT = 1 VPP
HD3, VOUT = 2 VPP
HD3, VOUT = 2.5 VPP
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D313
D314
Figure 6-13. Harmonic Distortion (HD2) vs Output Swing
Figure 6-14. Harmonic Distortion (HD3) vs Output Swing
-40
-40
HD2, RL = 100 W
HD2, RL = 200 W
HD2, RL = 400 W
HD3, RL = 100 W
HD3, RL = 200 W
HD3, RL = 400 W
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D315
D316
VOUT = 2 VPP
VOUT = 2 VPP
Figure 6-15. Harmonic Distortion (HD2) vs Output Load
Figure 6-16. Harmonic Distortion (HD3) vs Output Load
-40
-40
HD2, Gain = 1 V/V, RF = 0 W
HD3, Gain = 1 V/V, RF = 0 W
HD2, Gain = -1 V/V, RF = 150 W
HD2, Gain = 2 V/V, RF = 150 W
HD2, Gain = 5 V/V, RF = 453 W
HD3, Gain = -1 V/V, RF = 150 W
HD3, Gain = 2 V/V, RF = 150 W
HD3, Gain = 5 V/V, RF = 453 W
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D317
D318
VOUT = 2 VPP
VOUT = 2 VPP
Figure 6-17. Harmonic Distortion (HD2) vs Gain
Figure 6-18. Harmonic Distortion (HD3) vs Gain
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
60
1.25
1
Input
Output
Input
Output
40
0.75
0.5
20
0.25
0
0
-0.25
-0.5
-0.75
-1
-20
-40
-60
-1.25
Time (5 ns/div)
Time (5 ns/div)
D319
D320
Average Rise and Fall Time (10% - 90%) = 450 ps
Slew Rate: Falling = 1160 V/µs, Rising = 1400 V/µs
Figure 6-19. Small-Signal Transient Response
Figure 6-20. Large-Signal Transient Response
0.075
4
3
2
0.05
0.025
0
1
0
-1
-2
-0.025
RS = 18 W, CL = 10 pF
RS = 9.1 W, CL = 47 pF
-0.05
RS = 6.2 W, CL = 100 pF
-3
-4
Ideal Output
Measured Output
RS = 2 W, CL = 1 nF
-0.075
Time (10 ns/div)
Time (5 ns/div)
D321
D322
See Figure 7-4 for circuit configuration
Gain = 5 V/V, RF = 453 Ω, 2x Output Overdrive
Figure 6-21. Small-Signal Transient Response vs Capacitive
Load
Figure 6-22. Output Overload Response
3
3
Power Down (PD)
Output
2
2
1
1
0
0
-1
-1
-2
-3
-2
Power Down (PD)
Output
-3
Time (5 ns/div)
Time (5 ns/div)
D323
D324
Figure 6-23. Turnon Transient Response
Figure 6-24. Turnoff Transient Response
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
100
80
60
40
20
0
80
60
40
20
0
CMRR
PSRR+
PSRR-
-20
10k
100k
1M 10M
Frequency (Hz)
100M
1G
10k
100k
1M 10M
Frequency (Hz)
100M
1G
D325
D326
Small-Signal Response
Small-Signal Response
Figure 6-25. Common-Mode Rejection Ratio vs Frequency
Figure 6-26. Power Supply Rejection Ratio vs Frequency
21.5
21.25
21
24
23
22
21
20
20.75
20.5
20.25
20
19.75
19.5
19
Unit 1
Unit 2
Unit 1
Unit 2
19.25
19
18
-40
3
3.25 3.5 3.75
4
Total Supply Voltage (V)
4.25 4.5 4.75
5
5.25
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D360
D361
2 Typical Units
VS = 5 V
2 Typical Units
Figure 6-27. Quiescent Current vs Supply Voltage
Figure 6-28. Quiescent Current vs Ambient Temperature
80
1
Unit 1
Unit 2
Unit 3
78
76
74
72
70
68
66
64
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-40
-20
0
20
40
60
80
100 120 140
3
3.25 3.5 3.75
4
Total Supply Voltage (V)
4.25 4.5 4.75
5
5.25
Ambient Temperature (èC)
D362
D363
32 Units Tested
3 Typical Units
Figure 6-29. Quiescent Current (Amplifier Disabled) vs Ambient
Temperature
Figure 6-30. Offset Voltage vs Supply Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
0.8
0.6
0.4
0.2
0
2
1.5
1
Unit 1
Unit 2
Unit 3
0.5
0
-0.2
-0.4
-0.6
-0.8
-0.5
-1
-40
-20
0
20
40
60
80
100 120 140
0
0.5
1
1.5
Common-Mode Voltage (V)
2
2.5
3
3.5
4
4.5
Ambient Temperature (èC)
D364
D366
µ = –2.1 µV/°C
σ = 2 µV/°C
32 Units Tested
VS = 5 V
3 Typical Units
Figure 6-31. Offset Voltage vs Ambient Temperature
Figure 6-32. Offset Voltage vs Input Common-Mode Voltage
1.5
5
4
TA = -40èC
TA = +25èC
TA = +125èC
3
1
0.5
0
2
1
0
-1
-2
-3
Unit 1
Unit 2
Unit 3
-4
-5
-0.5
0
0.5
1
1.5
Common-Mode Voltage
2
2.5
3
3.5
4
4.5
1
1.5
2
2.5
Output Voltage (V)
3
3.5
4
4.5
D367
D369
VS = 5 V
VS = 5 V
3 Typical Units
Figure 6-33. Offset Voltage vs Input Common-Mode Voltage vs
Ambient Temperature
Figure 6-34. Offset Voltage vs Output Swing
4
3
10n
1n
2
1
100p
10p
1p
0
-1
-2
TA = -40èC
Unit 1
Unit 2
Unit 3
-3
TA = +25èC
TA = +125èC
-4
0.1p
1
1.5
2
2.5
Output Voltage (V)
3
3.5
4
4.5
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D370
D371
VS = 5 V
3 Typical Units
Figure 6-35. Offset Voltage vs Output Swing vs Ambient
Temperature
Figure 6-36. Input Bias Current vs Ambient Temperature
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
5
0
2.4
2.2
2
TA = -40èC
TA = +25èC
TA = +125èC
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
1.8
1.6
1.4
1.2
1
0
0.5
1
1.5
Common-Mode Voltage (V)
2
2.5
3
3.5
4
-120
-100
-80
-60
Output Current (mA)
-40
-20
0
D372
D373
VS = 5 V
VS = 5 V
Figure 6-37. Input Bias Current vs Input Common-Mode Voltage
Figure 6-38. Output Swing vs Sinking Current
4.5
4
7000
6000
5000
4000
3000
2000
1000
0
3.5
3
2.5
2
1.5
1
TA = -40èC
TA = +25èC
0.5
0
TA = +125èC
0
20
40
60
Output Current (mA)
80
100
120
D374
D340
Quiescent Current (mA)
VS = 5 V
µ = 20.8 mA
σ = 0.25 mA
9150 Units Tested
Figure 6-39. Output Swing vs Sourcing Current
Figure 6-40. Quiescent Current Distribution
2000
4500
4000
3500
3000
2500
2000
1500
1000
500
1750
1500
1250
1000
750
500
250
0
0
D342
D341
Offset Voltage (mV)
Input Bias Current (pA)
µ = –0.38 mV
σ = 0.97 mV
9150 Units Tested
µ = –0.55 pA
σ = 0.23 pA
9150 Units Tested
Figure 6-41. Offset Voltage Distribution
Figure 6-42. Input Bias Current Distribution
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7 Parameter Measurement Information
The various test setup configurations for the OPA859-Q1 are shown in the figures below. When configuring the
OPA859-Q1 as a noninverting amplifier in gains less 3 V/V, set RF = 150 Ω. When configuring the OPA859-Q1
as a noninverting amplifier in gains of 4 V/V and greater, set RF = 453 Ω.
GND
50 ꢀ
2.5 V
50 ꢀ
50-ꢀ
Source
169 ꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
GND
GND
Figure 7-1. Unity-Gain Buffer Configuration
2.5 V
50 ꢀ
50-ꢀ
Source
169 ꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
GND
RG
RF
GND
GND
RG values depend on gain configuration
Figure 7-2. Noninverting Configuration
2.5 V
169 ꢀ
+
50-ꢀ
Measurement
System
GND
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
50 ꢀ
50-ꢀ
Source
GND
150 ꢀ
150 ꢀ
GND
75 ꢀ
GND
Figure 7-3. Inverting Configuration (Gain = –1 V/V)
GND
50 ꢀ
2.5 V
50 ꢀ
50-ꢀ
Source
RS
169 ꢀ
75 ꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
CL
Þ2.5 V
GND
GND
GND
Figure 7-4. Capacitive Load Driver Configuration
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8 Detailed Description
8.1 Overview
The ultra-wide, 900-MHz gain bandwidth product (GBWP) of the OPA859-Q1, combined with the broadband
voltage noise of 3.3 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed
data acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front
ends. The OPA859-Q1 combines multiple features to optimize dynamic performance. In addition to the wide
small-signal bandwidth, the OPA859-Q1 has 400 MHz of large-signal bandwidth (VOUT = 2 VPP), and a slew rate
of 1150 V/µs.
The OPA859-Q1 is offered in a 2-mm × 2-mm, 8-pin WSON package that features a feedback (FB) pin for a
simple feedback network connection between the amplifiers output and inverting input. Excess capacitance on
an amplifiers input pin can reduce phase margin causing instability. This problem is exacerbated in the case of
very wideband amplifiers like the OPA859-Q1. To reduce the effects of stray capacitance on the input node, the
OPA859-Q1 pinout features an isolation pin (NC) between the feedback and inverting input pins that increases
the physical spacing between them thereby reducing parasitic coupling at high frequencies. The OPA859-Q1
also features a very low capacitance input stage with only 0.8-pF of total input capacitance.
8.2 Functional Block Diagram
The OPA859-Q1 is a classic voltage feedback operational amplifier (op amp) with two high-impedance inputs
and a low-impedance output. Standard application circuits are supported, like the two basic options shown in
Figure 8-1 and Figure 8-2. The DC operating point for each configuration is level-shifted by the reference voltage
(VREF), which is typically set to midsupply in single-supply operation. VREF is typically connected to ground in
split-supply applications.
VSIG
VS+
(1 + RF / RG) × VSIG
VREF
VIN
+
VOUT
VREF
œ
RG
VSœ
RF
VREF
Figure 8-1. Noninverting Amplifier
VS+
œ(RF / RG) × VSIG
VREF
+
VSIG
VOUT
VREF
VREF
VIN
œ
RG
VSœ
RF
Figure 8-2. Inverting Amplifier
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8.3 Feature Description
8.3.1 Input and ESD Protection
The OPA859-Q1 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown
voltages are low for these small geometry devices, and as a result, all device pins are protected with internal
ESD protection diodes to the power supplies as Figure 8-3 shows. There are two antiparallel diodes between the
inputs of the amplifier that clamp the inputs during an overrange or fault condition.
VS+
Power Supply
ESD Cell
VIN+
+
VOUT
œ
VINÞ
FB
VSÞ
Figure 8-3. Internal ESD Structure
8.3.2 Feedback Pin
The OPA859-Q1 pin layout is optimized to minimize parasitic inductance and capacitance, which is a critical care
about in high-speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The
FB pin is separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin
must be left floating. There are two advantages to this pin layout:
1. A feedback resistor (RF) can connect between the FB and IN– pin on the same side of the package (see
Figure 8-4) rather than going around the package.
2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by
increasing the physical separation between the pins.
FB
NC
INœ
IN+
PD
1
2
3
4
8
7
6
5
VS+
OUT
VSœ
RF
œ
+
Figure 8-4. RF Connection Between FB and IN– Pins
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8.3.3 Wide Gain-Bandwidth Product
Figure 6-10 shows the open-loop magnitude and phase response of the OPA859-Q1. Calculate the gain
bandwidth product of any op amp by determining the frequency at which the AOL is 40 dB and multiplying that
frequency by a factor of 100. The open-loop response shows the OPA859-Q1 to have approximately 63° of
phase-margin when configured as a unity-gain buffer.
Figure 8-5 shows the open-loop magnitude (AOL) of the OPA859-Q1 as a function of temperature. The results
show approximately 5° of phase-margin variation over the entire temperature range. Semiconductor process
variation is the naturally occurring variation in the attributes of a transistor (Early-voltage, β, channel-length, and
width) and other passive elements (resistors and capacitors) when fabricated into an integrated circuit. The
process variation can occur across devices on a single wafer or across devices over multiple wafer lots over
time. Typically the variation across a single wafer is tightly controlled. Figure 8-6 shows the AOL magnitude of the
OPA859-Q1 as a function of process variation over time. The results show the AOL curve for the nominal process
corner and the variation one standard deviation from the nominal. The simulated results show less than 2° of
phase-margin difference within a standard deviation of process variation when the amplifier is configured as a
unity-gain bufffer.
75
60
45
30
15
0
75
60
45
30
15
0
AOL at -40èC
AOL at 25èC
AOL at +125èC
AOL (-1 s)
AOL (Typ.)
AOL (+1 s)
-15
-15
100k
1M
10M 100M
Frequency (Hz)
1G
100k
1M
10M 100M
Frequency (Hz)
1G
D405
D404
Figure 8-6. Open-Loop Gain vs Process Variation
Figure 8-5. Open-Loop Gain vs Temperature
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8.3.4 Slew Rate and Output Stage
In addition to wide bandwidth, the OPA859-Q1 features a high slew rate of 2750 V/µs. The slew rate is a critical
parameter in high-speed pulse applications with narrow sub-10-ns pulses, such as optical time-domain
reflectometry (OTDR) and LIDAR. The high slew rate of the OPA859-Q1 implies that the device accurately
reproduces a 2-V, sub-ns pulse edge, as seen in Figure 6-20. The wide bandwidth and slew rate of the OPA859-
Q1 make it an excellent amplifier for high-speed signal-chain front ends.
Figure 8-7 shows the open-loop output impedance of the OPA859-Q1 as a function of frequency. To achieve
high slew rates and low output impedance across frequency, the output swing of the OPA859-Q1 is limited to
approximately 3 V. The OPA859-Q1 is typically used in conjunction with high-speed pipeline ADCs and flash
ADCs that have limited input ranges. Therefore, the OPA859-Q1 output swing range coupled with the class-
leading voltage noise specification for a CMOS amplifier maximizes the overall dynamic range of the signal
chain.
20
18
16
14
12
10
8
6
4
2
0
10k
100k
1M
10M 100M
Frequency (Hz)
1G
10G
D601
Figure 8-7. Open-Loop Output Impedance (ZOL) vs Frequency
8.3.5 Current Noise
The input impedance of CMOS and JFET input amplifiers at low frequencies exceed several GΩs. However, at
higher frequencies, the transistors parasitic capacitance to the drain, source, and substrate reduces the
impedance. The high impedance at low frequencies eliminates any bias current and the associated shot noise.
At higher frequencies, the input current noise increases (see Figure 8-8) as a result of capacitive coupling
between the CMOS gate oxide and the underlying transistor channel. This phenomenon is a natural artifact of
the construction of the transistor and is unavoidable.
100p
10p
1p
100f
10f
1f
1k
10k
100k 1M
Frequency (Hz)
10M
100M
1G
D607
Figure 8-8. Input Current Noise (IBN and IBI) vs Frequency
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8.4 Device Functional Modes
8.4.1 Split-Supply and Single-Supply Operation
The OPA859-Q1 can be configured with single-sided supplies or split-supplies as shown in Figure 10-1. Split-
supply operation using balanced supplies with the input common-mode set to ground eases lab testing because
most signal generators, network analyzers, spectrum analyzers, and other lab equipment typically reference
inputs and outputs to ground. In split-supply operation, the thermal pad must be connected to the negative
supply.
Newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply.
The OPA859-Q1 can be used with a single positive supply (negative supply at ground) with no change in
performance if the input common-mode and output swing are biased within the linear operation of the device. In
single-supply operation, level shift the DC input and output reference voltages by half the difference between the
power supply rails. This configuration maintains the input common-mode and output load reference at midsupply.
To eliminate gain errors, the source driving the reference input common-mode voltage must have low output
impedance across the frequency range of interest. In this case, the thermal pad must be connected to ground.
8.4.2 Power-Down Mode
The OPA859-Q1 features a power-down mode to reduce the quiescent current to conserve power. Figure 6-23
and Figure 6-24 show the transient response of the OPA859-Q1 as the PD pin toggles between the disabled and
enabled states.
The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is
configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable
threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65 V supplies, then
the threshold voltages are at –1 V and 0.15 V. If the amplifier is configured with ±2.5 V supplies, then the
threshold voltages are at –1.85 V and –0.7 V.
Figure 8-9 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled
state to the disabled state. Similarly, Figure 8-10 shows the switching behavior of a typical amplifier as the PD
pin is swept up from the disabled state to the enabled state. The small difference in the switching thresholds
between the down sweep and the up sweep is caused by the hysteresis designed into the amplifier to increase
immunity to noise on the PD pin.
25
20
15
10
5
25
20
15
10
5
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
0
0
-2
-1.5
-1
-0.5
Power Down Voltage (V)
0
0.5
1
1.5
2
-2
-1.5
-1
-0.5
Power Down Voltage (V)
0
0.5
1
1.5
2
D200
D201
Figure 8-9. Switching Threshold ( PD Pin Swept
from High to Low)
Figure 8-10. Switching Threshold ( PD Pin Swept
from Low to High)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the
amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a
parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA859-Q1 uses
internal, back-to-back protection diodes between the inverting and noninverting input pins as Figure 8-3 shows.
In the power-down state, if the differential voltage between the input pins of the amplifier exceeds a diode
voltage drop, an additional low-impedance path is created between the noninverting input pin and the output pin.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPA859-Q1 offers high input impedance, very high-bandwidth, high slew-rate, low noise, and better than –
60 dBc of distortion performance at frequencies up to 100 MHz. These features make this device an excellent
front-end buffer in high-speed data acquisition systems. The wide bandwidth also makes this amplifier an
excellent choice for high-gain active filter systems.
9.2 Typical Application
Figure 9-1 shows the OPA859-Q1 configured as a transimpedance amplifier (U1) in a wide-bandwidth, optical
front-end system. A second OPA859-Q1 configured as a unity-gain buffer (U2) sets a dc offset voltage to the
THS4520. The THS4520 is used to convert the single-ended transimpedance output of the OPA859-Q1 into a
differential output signal. The THS4520 drives the input of the ADS54J64, 14-bit, 1-GSPS analog-to-digital
converter (ADC) that digitizes the analog signal.
CF
RF
VBIAS
5 V
œ
U1
499 ꢀ
499 ꢀ
3.5 V
+
OPA859
5 V
+
œ
Low-pass
filter
VOCM = 1.3 V
ADS54J64
+
œ
5 V
œ
U2
+
2.95 V
OPA859
499 ꢀ
499 ꢀ
Figure 9-1. OPA859-Q1 as Both a TIA and a Buffer in an Optical Front-End System
9.2.1 Design Requirements
The objective is to design a low noise, wideband optical front-end system using the OPA859-Q1 as a
transimpedance amplifier. The design requirements are:
•
•
•
•
•
Amplifier supply voltage: 5 V
TIA common-mode voltage: 3.5 V
THS4520 gain: 1 V/V
ADC input common-mode voltage: 1.3 V
ADC analog differential input range: 1.1 VPP
9.2.2 Detailed Design Procedure
The OPA859-Q1 meets the growing demand for wideband, low-noise photodiode amplifiers. The closed-loop
bandwidth of a transimpedance amplifier is a function of the following:
1. The total input capacitance (CIN). This total includes the photodiode capacitance, the input capacitance of the
amplifier (common-mode and differential capacitance) and any stray capacitance from the PCB.
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2. The op amp gain bandwidth product (GBWP).
3. The transimpedance gain (RF).
Figure 9-1 shows the OPA859-Q1 configured as a TIA, with the avalanche photodiode (APD) reverse biased so
that the APD cathode is tied to a large positive bias voltage. In this configuration, the APD sources current into
the op amp feedback loop so that the output swings in a negative direction relative to the input common-mode
voltage. To maximize the output swing in the negative direction, the OPA859-Q1 common-mode voltage is set
close to the positive limit; only 1.5 V from the positive supply rail. The feedback resistance (RF) and the input
capacitance (CIN) form a zero in the noise gain that results in instability if left unchecked. To counteract the effect
of the zero, a pole is inserted into the noise gain transfer function by adding the feedback capacitor (CF).
The Transimpedance Considerations for High-Speed Amplifiers Application Report discusses theories and
equations that show how to compensate a transimpedance amplifier for a particular transimpedance gain and
input capacitance. The bandwidth and compensation equations from the application report are available in an
Excel® calculator. What You Need To Know About Transimpedance Amplifiers – Part 1 provides a link to the
calculator.
The equations and calculators in the referenced application report and blog posts are used to model the
bandwidth (f–3dB) and noise (IRN) performance of the OPA859-Q1 configured as a TIA. The resultant
performance is shown in Figure 9-2 and Figure 9-3. The left-side Y-axis shows the closed-loop bandwidth
performance, whereas the right side of the graph shows the integrated input-referred noise. The noise bandwidth
to calculate IRN for a fixed RF and CPD is set equal to the f–3dB frequency. Figure 9-2 shows the amplifier
performance as a function of photodiode capacitance (CPD) for RF = 10 kΩ and 20 kΩ. Increasing CPD
decreases the closed-loop bandwidth. To maximize bandwidth, make sure to reduce any stray parasitic
capacitance from the PCB. The OPA859-Q1 is designed with 0.8 pF of total input capacitance to minimize the
effect of stray capacitance on system performance. Figure 9-3 shows the amplifier performance as a function of
RF for CPD = 1 pF and 2 pF. Increasing RF results in lower bandwidth. To maximize the signal-to-noise ratio
(SNR) in an optical front-end system, maximize the gain in the TIA stage. Increasing RF by a factor of X
increases the signal level by X, but only increases the resistor noise contribution by √X, thereby improving SNR.
The OPA859-Q1 configured as a unity-gain buffer drives a dc offset voltage of 2.95 V into the lower half of the
THS4520. To maximize the dynamic range of the ADC, the two OPA859 amplifiers drive a differential common-
mode of 3.5 V and 2.95 V into the THS4520. The dc offset voltage of the buffer amplifier can be derived using
Equation 1.
≈
∆
∆
∆
∆
∆
«
’
÷
÷
÷
÷
÷
◊
VADC _DIFF _IN
1
2
VBUF _DC = VTIA _ CM
-
ì
≈
∆
«
’
÷
RF
RG ◊
(1)
where
•
•
•
VTIA_CM is the common-mode voltage of the TIA (3.5 V)
VADC_DIFF_IN is the differential input voltage range of the ADC (1.1 VPP
RF and RG are the feedback resistance (499 Ω) and gain resistance (499 Ω) of the THS4520 differential
amplifier
)
The low-pass filter between the THS4520 and the ADC54J64 minimizes high-frequency noise and maximizes
SNR. The ADC54J64 has an internal buffer that isolates the output of the THS4520 from the ADC sampling-
capacitor input, so a traditional charge bucket filter is not required.
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9.2.3 Application Curves
225
150
135
120
105
90
350
300
250
200
150
100
50
140
f-3dB, RF = 2 kW
f-3dB, CF = 0.5 pF
f-3dB, CF = 1 pF
200
175
150
125
100
75
f-3dB, RF = 5 kW
IRN, RF = 2 kW
IRN, RF = 5 kW
120
IRN, CF = 0.5 pF
IRN, RF = 1 pF
100
80
60
40
20
75
60
50
45
25
30
0
15
0
0
0
2
4
6
8
10
12
14
Photodiode capacitance (pF)
16
18
20
1
10
Feedback Resistance (kW)
100
D409
D410
Figure 9-2. Bandwidth and Noise vs Photodiode Capacitance
Figure 9-3. Bandwidth and Noise vs Feedback Resistance
10 Power Supply Recommendations
The OPA859-Q1 operates on supplies from 3.3 V to 5.25 V. The OPA859-Q1 operates on single-sided supplies,
split and balanced bipolar supplies, and unbalanced bipolar supplies. Because the OPA859-Q1 does not feature
rail-to-rail inputs or outputs, the input common-mode and output swing ranges are limited at 3.3-V supplies.
a) Single supply configuration
VS+
VS+
+
2
0.1 …F
6.8 …F
RG
75 ꢀ
RF
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
RT
49.9 ꢀ
VS+
2
VS+
2
b) Split supply configuration
VS+
+
0.1 …F
6.8 …F
RG
RF
75 ꢀ
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
+
RT
49.9 ꢀ
0.1 …F
6.8 …F
VSœ
Figure 10-1. Split and Single Supply Circuit Configuration , Gain = 7 V/V
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11 Layout
11.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA859-Q1 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
•
Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output and inverting input pins can cause instability. To reduce unwanted capacitance, cut out the power and
ground traces under the signal input and output pins. Otherwise, ground and power planes must be unbroken
elsewhere on the board. When configuring the amplifier as a TIA, if the required feedback capacitor is less
than 0.15 pF, consider using two series resistors, each of half the value of a single resistor in the feedback
loop to minimize the parasitic capacitance from the resistor.
•
Minimize the distance (less than 0.25-in) from the power-supply pins to high-frequency bypass
capacitors. Use high-quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage
ratings at least three times greater than the amplifiers maximum power supplies. This configuration makes
sure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain
bandwidth specification. At the device pins, do not allow the ground and power plane layout to be in close
proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the
pins and the decoupling capacitors. The power-supply connections must always be decoupled with these
capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency must be
used on the supply pins. Place these decoupling capacitors further from the device. Share the decoupling
capacitors among several devices in the same area of the printed circuit board (PCB).
•
Careful selection and placement of external components preserves the high-frequency performance
of the OPA859-Q1. Use low-reactance resistors. Surface-mount resistors work best and allow a tighter
overall layout. Never use wirewound resistors in a high-frequency application. Because the output pin and
inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series
output resistor, if any, as close to the output pin as possible. Place other network components (such as
noninverting input termination resistors) close to the package. Even with a low parasitic capacitance shunting
the external resistors, high resistor values create significant time constants that can degrade performance.
When configuring the OPA859-Q1 as a voltage amplifier, keep resistor values as low as possible and
consistent with load driving considerations. Decreasing the resistor values keeps the resistor noise terms low
and minimizes the effect of the parasitic capacitance. However, lower resistor values increase the dynamic
power consumption because RF and RG become part of the output load network of the amplifier.
11.2 Layout Example
Representative schematic
Connect PD to VS+ to enable the
amplifier
VS+
1
2
8
7
CBYP
RS
+
NC (Pin 2) isolates the IN- and FB
pins thereby reducing capacitive
coupling
œ
Thermal
Pad
CBYP
RF
CBYP
Place gain and feedback resistors
close to pins to minimize stray
capacitance
VS-
RF
3
4
6
5
RS
RG
RG
CBYP
Connect the thermal pad to the
negative supply pin
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Place bypass capacitor
close to power pins
Figure 11-1. Layout Recommendation
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
•
•
•
LIDAR Pulsed Time of Flight Reference Design
LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
Wide Bandwidth Optical Front-end Reference Design
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
Texas Instruments, OPA858EVM user's guide
Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow
Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits
Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model
Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
Texas Instruments, What You Need To Know About Transimpedance Amplifiers – Part 1
Texas Instruments What You Need To Know About Transimpedance Amplifiers – Part 2
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Excel® is a registered trademark of Microsoft Corporation.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA859Q1DSGR
PREVIEW
WSON
DSG
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
859Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA859-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2021
Catalog: OPA859
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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