OPA862IDT [TI]
12.6V、低噪声、单端到差分、高输入阻抗放大器 | D | 8 | -40 to 125;
| 型号： | OPA862IDT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12.6V、低噪声、单端到差分、高输入阻抗放大器 | D | 8 | -40 to 125 放大器 光电二极管 |
| 文件： | 总39页 (文件大小：3725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA862
ZHCSK39C –AUGUST 2019 –REVISED AUGUST 2020
OPA862 高输入阻抗、单端到差分ADC 驱动器
1 特性
3 说明
• 宽电源电压范围：3V 至12.6V
• 高输入阻抗：325MΩ
• 电压噪声：
– 输入参考噪声(f ≥5kHz)：2.3nV/√Hz
– 输出参考噪声(f ≥10kHz)：8.3nV/√Hz
• 差分输出失调电压：±700µV（最大值）
• 输出温漂：±1.5µV/°C（典型值）
• A2 偏置电流消除IB：±5nA（典型值）
• 增益带宽积：400MHz
• 小信号带宽：44MHz (G = 2V/V)
• 压摆率：140V/µs
• HD2、HD3（VOD = 10VPP，50kHz）：
–122dBc、–140dBc
OPA862 是一款单端到差分模数转换器 (ADC) 驱动
器，具有高输入阻抗，可直接连接传感器。该器件在增
益设置为 2V/V 的条件下，仅需消耗 3.1mA 的静态电
流即可实现 8.3nV/√Hz 的输出参考噪声密度。具有
1kΩ 电阻且增益设置为 1V/V 的全差分放大器必须低
于 1nV/√ Hz，才可实现与 OPA862 等效的输出参考
噪声密度
8.3nV/√ Hz。用户可使用外部电阻器对 OPA862 进行
其他增益设置。该器件具有 400MHz 的高增益带宽积
和140V/µs 的压摆率。
因此，与同类的单端到差分 ADC 驱动器相比，该器件
具有出色的线性度，可提供快速趋稳的 18 位性能。该
器件包含一个用于设置输出共模电压的参考输入引脚。
• 轨至轨输出：
– 高线性输出电流：60mA（典型值）
• 静态电流：3.1mA
• 禁用模式：12µA 静态电流
• 工作温度范围：
OPA862 完全可在3V 至12.6V 的宽电源电压范围内正
常工作，并且具有轨至轨输出级。该器件使用德州仪器
(TI) 专有的高速硅锗 (SiGe) 工艺制造，在18 位系统上
实现了出色的低失真性能。在断电状态下，器件禁用模
式的静态电流仅为12µA。
–40°C 至+125°C
OPA862 可在宽达 –40°C 至 +125°C 的工业温度范围
内运行。
2 应用
器件信息(1)
• 16 位和18 位ADC 驱动器
• 内存和LCD 测试仪
• 数据采集(DAQ)
封装尺寸（标称值）
器件型号
OPA862
封装
SOIC (8)
WSON (8)
4.90mm × 3.90mm
3.00mm × 3.00mm
• 测试和测量
• 跨阻放大器(TIA)
• D 类音频放大器驱动器
• 压电式传感器接口
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 医疗仪器
+7 V
-80
HD2, VS = 10 V
HD3, VS = 10 V
HD2, VS = 5 V
HD3, VS = 5 V
-90
-100
-110
-120
-130
-140
-150
-160
OPA862
+5 V
œ
64.9 ꢀ
A1
+
RINT
700 ꢀ
470 pF
470 pF
VIN
ADS8881
RINT
700 ꢀ
RREF
0 ꢀ
œ
A2
+
64.9 ꢀ
VREF
2.5 V
œ3.3 V
单端高输入阻抗传感器接口
10k
100k
Frequency (Hz)
1M
D017
谐波失真与频率间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS919
OPA862
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ZHCSK39C –AUGUST 2019 –REVISED AUGUST 2020
Table of Contents
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................19
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Applications.................................................. 21
9 Power Supply Recommendations................................26
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Examples.................................................... 27
11 Device and Documentation Support..........................28
11.1 Documentation Support.......................................... 28
11.2 Receiving Notification of Documentation Updates..28
11.3 支持资源..................................................................28
11.4 Trademarks............................................................. 28
11.5 Electrostatic Discharge Caution..............................28
11.6 术语表..................................................................... 28
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics: VS = ±2.5 V to ±5 V ...........5
6.6 Typical Characteristics: VS = ±5 V.............................. 7
6.7 Typical Characteristics: VS = ±2.5 V......................... 10
6.8 Typical Characteristics: VS = 1.9 V, –1.4 V..............12
6.9 Typical Characteristics: VS = 1.9 V, –1.4 V to ±5
V..................................................................................13
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (Feburary 2020) to Revision C (August 2020)
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• 将OPA862 WSON 封装的状态从预发布更改为正在供货................................................................................. 1
Changes from Revision A (September 2019) to Revision B (February 2020)
Page
• 将文档状态从“预告信息”更改为“生产数据”................................................................................................ 1
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5 Pin Configuration and Functions
VFB
VREF
VS+
8
7
6
5
VIN
1
2
3
4
1
2
3
4
8
7
6
5
VIN
VFB
VREF
VS+
PD
PD
VS-
VS-
VOUT+
VOUT-
VOUT-
VOUT+
Not to scale
Not to scale
图5-1. D Package, 8-Pin SOIC (Top View)
图5-2. DTK Package, 8-Pin WSON (Top View)
表5-1. Pin Functions
PIN(1)
TYPE(2)
DESCRIPTION
NAME
PD
NO.
7
I
I
Power down (low = enable, high = disable), cannot be floated
VFB
1
Amplifier 1 inverting (feedback) input
Amplifier 1 noninverting (signal) input
Noninverting output
VIN
8
I
VOUT+
VOUT–
VREF
VS+
4
O
O
I
5
Inverting output
2
Amplifier 2 noninverting (reference) input
Positive power supply
3
P
P
6
Negative power supply
VS–
(1) Solder the exposed DTK package thermal pad to a heatspreading power or ground plane. This pad is electrically isolated from the die,
but must be connected to a power or ground plane and not floated.
(2) I = input, O = output, and P = power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
13
Supply voltage, (VS+) –(VS–
)
Supply turn-on/turn-off maximum dV/dT(2)
Input-output voltage range
Differential input voltage
Continuous input current(3)
Continuous output current(4)
Continuous power dissipation
Junction, TJ
1
(VS+) + 0.5
0.7
V/µs
Voltage
(VS–) –0.5
V
±10
Current
mA
±20
See Thermal Information
150
Temperature
Operating free-air, TA
125
150
–40
–65
°C
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Stay below this ± supply turn-on edge rate to make sure that the edge-triggered ESD absorption device across the supply pins remains
off.
(3) Continuous input current limit for both the ESD diodes to supply pins and amplifier differential input clamp diode. The differential input
clamp diode limits the voltage across it to 0.7 V with this continuous input current flowing through it.
(4) Long-term continuous current for electromigration limits.
6.2 ESD Ratings
VALUE
±2500
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specificationJESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
10
MAX
12.6
125
UNIT
VS+
TA
Single-supply positive voltage
Ambient temperature
V
25
°C
–40
6.4 Thermal Information
OPA862
THERMAL METRIC(1)
D (SOIC)
8 PINS
125.7
65.9
DTK (WSON)
8 PINS
65.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56.7
69.1
34.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18
1.6
ΨJT
68.3
34.4
ΨJB
RθJC(bot)
N/A
8.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: VS = ±2.5 V to ±5 V
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, RREF = 0 Ω, and
VS = ±5 V for VOD = 10 VPP condtions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC PERFORMANCE
VOD = 20 mVPP
44
48
VOD = 20 mVPP, G = 4 V/V, RF = 700 Ω
SSBW
Differential small-signal bandwidth
Differential large-signal bandwidth
MHz
VOD = 20 mVPP, G = –2 V/V, RF = 700
Ω
48
VOD = 1 VPP
42
14
LSBW
GBWP
VS = ±2.5 V, VOD = 5 VPP
VOD = 10 VPP
MHz
MHz
7.5
VOD = 40 mVPP, G = 200 V/V,
RF = 700 Ω
Differential gain-bandwidth product
Bandwidth for 0.1-dB flatness
400
VOD = 20 mVPP, G = 2 V/V
VOD = 5 VPP, f = 1 MHz
VOD = 10 VPP
6.5
41
MHz
dB
Output balance (ΔVOD / ΔVOCM
Slew rate(1) (20% –80%)
Overshoot, undershoot
Rise and fall time
)
SR
140
0.2%
8.5
V/µs
VOD = 10-V step
tr, tf
VOD = 200-mV step
ns
ns
To 0.0015% of final value,
VOD = 10-V step
Settling time
100
Input overdrive recovery
Output overdrive recovery
VIN = VS ± 0.5 V, VREF = midsupply
G = –4 V/V, VOD = 2x overdrive
VOD = 10 VPP, f = 15 kHz
VOD = 10 VPP, f = 50 kHz
VOD = 10 VPP, f = 350 kHz
VOD = 10 VPP, f = 15 kHz
VOD = 10 VPP, f = 50 kHz
VOD = 10 VPP, f = 350 kHz
f ≥10 kHz
100
120
ns
ns
–133
–122
–110
–148
–140
–110
8.3
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
dBc
Differential output noise
en
ei
nV/√Hz
pA/√Hz
Input voltage noise of A1 and A2
Input current noise of A1
Input current noise of A2
2.3
f ≥5 kHz
0.7
f ≥100 kHz
0.9
f ≥100 kHz
DC PERFORMANCE
Differential output offset voltage
±50
±50
±1.5
±1.5
±0.5
±0.5
1
±700
µV
VOS
Input offset voltage for A1, A2
±325
SOIC
±9
TA = 0°C to 85°C,
TA = –40°C to 125°C
Differential output offset drift
WSON
SOIC
±7
µV/°C
±3
TA = 0°C to 85°C,
TA = –40°C to 125°C
Input offset voltage drift for A1, A2
WSON
±2.5
Input bias current, A1
Input bias current, A2
Input bias current drift, A1
Input bias current drift, A2
Input offset current, A1
3.1
µA
nA
IB
VREF pin
±5
±90
13
nA/°C
pA/°C
nA
TA = –40°C to 125°C
±65
±4
VREF pin, TA = –40°C to 125°C
IOS
±110
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6.5 Electrical Characteristics: VS = ±2.5 V to ±5 V (continued)
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, RREF = 0 Ω, and
VS = ±5 V for VOD = 10 VPP condtions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential gain
2
V/V
Differnetial gain error
Differential gain error drift
Internal resistors
±0.1
±0.02
700
±0.25
%
ppm/°C
Ω
G
TA = –40°C to 125°C
RINT
INPUT
Input common-mode range, A1
VREF pin common-mode range
VS– + 0.5
VS– + 1.3
VS+ –1.1
VS+ –1.1
CMIR
V
VCM = VS+ –1.1 V and
VCM = VS– + 0.5 V
ΔVOS (2) at CMIR specification, A1
ΔVOS (2) at CMIR specification
Common-mode rejection ratio
±25
±50
µV
µV
dB
VREF = VS+ –1.1 V and
VREF = VS– + 1.3 V
CMRR = VOD / VIN, VIN = VREF
VCM = ±1 V, RREF = 0 Ω
,
CMRR
100
120
Input impedance common-mode, A1
Input impedance differential-mode, A1
Input impedance, A2
325 || 0.6
35 || 1.9
2.3 || 3.5
MΩ|| pF
kΩ|| pF
GΩ|| pF
VREF pin
OUTPUT
VOL
Output voltage range low
Output voltage range high
Each output, single-ended
Each output, single-ended
VS– + 0.15 VS– + 0.25
V
V
VS+ –
0.25
VS+ –
0.15
VOH
VS = ±5 V, VOD = ±2.65 V, ∆VOCM < ±10
mV relative to no-load condition
Linear output current
40
60
mA
POWER SUPPLY
VS
IQ
Specified operating voltage
Single-supply referred to GND
VS = ±5 V, TA = 25°C
3
10
3.1
9
12.6
3.3
V
mA
Quiescent current
2.8
Quiescent current drift
Power-supply rejection ratio
µA/°C
dB
VS = ±5 V, TA = –40°C to 125°C
VIN = VREF = 0 V, ΔVS = 2 V
PSRR
105
115
POWER DOWN
Disable voltage threshold
Disabled above specified voltage
Enabled below specified voltage
VS– + 1.5
V
V
Enable voltage threshold
Disable pin bias current
Power-down quiescent current
Turn-on time delay
VS– + 1
10
20
nA
µA
µs
µs
–10
12
1.3
2.5
Turn-off time delay
(1) Average of rising and falling slew rate.
(2) ΔVOS = VOS at specified CMIR VCM –VOS at midsupply VCM
.
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6.6 Typical Characteristics: VS = ±5 V
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
3
1
0
-1
0
-2
-3
-4
-3
-5
-6
-6
-7
-8
G = 2 V/V
G = -2 V/V
G = 4 V/V
G = 10 V/V
G = 2 V/V
G = -2 V/V
G = 4 V/V
G = 10 V/V
-9
-9
-10
-11
-12
-12
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
D003
D006
VOD = 20 mVPP
VOD = 10 VPP
图6-2. Large-Signal Frequency Response
图6-1. Small-Signal Frequency Response
180
-30
160
150
140
130
120
110
100
90
A1, Magnitude
A1, Phase
A2, Magnitude
A2, Phase
CMRR
PSRR+
PSRR-
160
140
120
100
80
-45
-60
-75
-90
-105
-120
-135
-150
-165
-180
80
60
70
40
60
50
20
40
0
30
20
-20
100
1k
10k 100k
Frequency (Hz)
1M
10M
1
10
100
1k
10k 100k 1M 10M 100M
Frequency (Hz)
D054
D058
Simulation, A1 and A2
Simulation
图6-4. CMRR and PSRR vs Frequency
图6-3. Open-Loop Gain And Phase vs Frequency
400
100
A1
A2
10
1
100
0.1
0.01
0.001
0.0001
10
4
A1
A2
10
100
1k
10k
100k
Frequency (Hz)
1M
10M 100M 1G
10k
100k
1M
Frequency (Hz)
10M
100M
D059
D053
Simulation
Simulation
图6-5. Open-Loop Output Impedance vs Frequency
图6-6. Closed-Loop Output Impedance vs Frequency
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6.6 Typical Characteristics: VS = ±5 V (continued)
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
625
500
375
250
125
0
150
125
100
75
50
25
0
-25
-50
-75
-100
-125
-150
-125
-250
-375
-500
-625
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D038
D061
99 units
99 units
图6-7. Differential Output Offset Voltage vs Temperature
图6-8. A1 Input Offset Voltage vs Temperature
27
45
VS = 10 V
VS = 5 V
VS = 3.3 V
VS = 10 V
VS = 5 V
VS = 3.3 V
24
21
18
15
12
9
40
35
30
25
20
15
10
5
6
3
0
0
Differential VOS Drift (mV/°C)
D062
D040
A1 Input VOS Drift (mV/°C)
–40°C to +125°C, over 115 units
–40°C to +125°C, over 115 units
图6-9. Differential Output Offset Voltage Drift Histogram
图6-10. A1 Input Offset Voltage Drift Histogram
3.25
3
120
105
90
75
60
45
30
15
0
2.75
2.5
2.25
2
1.75
1.5
1.25
1
-15
-30
0.75
0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D044
D063
32 units
32 units
图6-12. A1 Input Offset Current vs Temperature
图6-11. A1 Input Bias Current vs Temperature
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6.6 Typical Characteristics: VS = ±5 V (continued)
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
0.5
0.4
0.3
0.2
0.1
0
3
2.5
2
90
60
30
0
1.5
1
-0.1
-0.2
-0.3
-0.4
-0.5
-30
-60
-90
VIN IB
VFB IB
IOS
0.5
0
-5
-4
-3
-2
A1 Input Common-Mode Voltage (V)
-1
0
1
2
3
4
5
-5
-4
-3
-2
A1 Input Common-Mode Voltage (V)
-1
0
1
2
3
4
5
D037
D045
.
.
图6-13. A1 Input Offset Voltage vs Input Common-Mode Voltage 图6-14. A1 Input Bias Current and Input Offset Current vs Input
Common-Mode Voltage
30
20
80
60
40
10
20
0
0
-10
-20
-30
-40
-50
-20
-40
-60
-80
-5
-4
-3
-2
-1
0
1
2
A2 Input Common-Mode Voltage (V)
3
4
5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D047
D046
.
32 units
图6-16. A2 Input Bias Current vs Input Common-Mode Voltage
图6-15. A2 Input Bias Current vs Temperature
12
20
VIN ì 2
VOD
VIN ì -4
VOD
17.5
15
12.5
10
7.5
5
2.5
0
10
8
6
4
2
0
-2.5
-5
-2
-4
-6
-8
-10
-12
-7.5
-10
-12.5
-15
-17.5
-20
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
D026
D027
.
G = –4 V/V
图6-17. Input Overdrive Recovery
图6-18. Output Overdrive Recovery
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6.7 Typical Characteristics: VS = ±2.5 V
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
3
0
1
0
-1
-2
-3
-4
-3
-5
-6
-6
-7
-8
G = 2 V/V
G = -2 V/V
G = 4 V/V
G = 10 V/V
G = 2 V/V
G = -2 V/V
G = 4 V/V
G = 10 V/V
-9
-9
-10
-11
-12
-12
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
D002
D005
VOD = 20 mVPP
VOD = 5 VPP
图6-20. Large-Signal Frequency Response
图6-19. Small-Signal Frequency Response
1
1
0
-1
0
-1
-2
-3
-4
-5
-6
-7
-8
-2
-3
-4
-5
-6
-7
-8
-9
CL = 0 pF
CL = 5 pF
CL = 10 pF
CL = 0 pF
CL = 5 pF
CL = 10 pF
-10
-11
-12
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
D009
D010
VOD = 20 mVPP
VOD = 5 VPP
图6-21. Small-Signal Frequency Response Over CL
图6-22. Large-Signal Frequency Response Over CL
1
0
-15
-20
-25
-30
-35
-40
-45
-50
-55
-1
-2
-3
-4
-5
-6
-7
-8
VOD = 20 mVPP
VOD = 1 VPP
VOD = 2 VPP
VOD = 5 VPP
-9
-10
-11
-12
VIN = 10 mVPP
VIN = 1 VPP
-60
-65
1M
10M
Frequency (Hz)
100M
100k
1M
10M
100M
Frequency (Hz)
D011
D052
.
.
图6-23. Frequency Response Over Differential Output Voltage,
图6-24. Input-to-Output Disable Mode Isolation
VOD
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6.7 Typical Characteristics: VS = ±2.5 V (continued)
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
-65
-75
-85
15 kHz, HD2
15 kHz, HD3
100 kHz, HD2
100 kHz, HD3
1 MHz, HD2
1 MHz, HD3
HD2, G = 2 V/V
HD3, G = 2 V/V
HD2, G = -2 V/V
HD3, G = -2 V/V
HD2, G = 4 V/V
HD3, G = 4 V/V
-75
-85
-95
-95
-105
-115
-125
-135
-145
-155
-105
-115
-125
-135
-145
-155
200
1k
10k
100k
Frequency (Hz)
1M
Differential Load, RL (W)
D014
D018
VOD = 5 VPP
VOD = 5 VPP
图6-25. Harmonic Distortion vs Differential Load
图6-26. Harmonic Distortion vs Frequency and Gain
150
125
100
75
3
2.5
2
1.5
1
50
0.5
0
25
0
-0.5
-1
-25
-50
-75
-100
-125
-150
-1.5
-2
-2.5
-3
-3.5
CL = 0 pF
100 200
CL = 5 pF
300
CL = 10 pF
500
CL = 0 pF
CL = 5 pF
CL = 10 pF
-175
-4
0
400
600
700
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
Time (ns)
D020
D021
VOD = 200 mVPP
VOD = 5 VPP
图6-27. Small-Signal Step Response Over CL
图6-28. Large-Signal Step Response Over CL
6
10
VIN ì 2
VOD
VIN ì -4
VOD
5
7.5
5
4
3
2
2.5
0
1
0
-1
-2
-3
-4
-5
-6
-2.5
-5
-7.5
-10
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
D064
D028
.
G = –4 V/V
图6-29. Input Overdrive Recovery
图6-30. Output Overdrive Recovery
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6.8 Typical Characteristics: VS = 1.9 V, –1.4 V
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
3
0
2
1
0
-1
-2
-3
-3
-4
-5
-6
-6
-7
-8
G = 2 V/V
G = -2 V/V
G = 4 V/V
G = 10 V/V
G = 2 V/V
G = -2 V/V
G = 4 V/V
G = 10 V/V
-9
-9
-10
-11
-12
-12
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
D001
D006
VOD = 20 mVPP
VOD = 2 VPP
图6-31. Small-Signal Frequency Response
图6-32. Large-Signal Frequency Response
5
4
7
VIN ì 2
VOD
VIN ì -4
VOD
6
5
3
4
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
D065
D029
.
G = –4 V/V
图6-33. Input Overdrive Recovery
图6-34. Output Overdrive Recovery
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6.9 Typical Characteristics: VS = 1.9 V, –1.4 V to ±5 V
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-1
-2
-3
-4
-5
-6
-7
-8
-9
VS = 3.3 V
VS = 5 V
VS = 10 V
VS = 3.3 V
VS = 5 V
VS = 10 V
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D012
D013
VIN = 10 mVPP, VREF = 0 V, measured at VOUT+
VIN = 0 V, VREF = 20 mVPP, measured at VOUT–
图6-35. A1 Small-Signal Frequency Response
图6-36. VREF Small-Signal Frequency Response
-80
-90
HD2, VS = 10 V
HD2, VS = 10 V
HD3, VS = 10 V
HD2, VS = 5 V
HD3, VS = 5 V
HD2, VS = 3.3 V
HD3, VS = 3.3 V
-95
HD3, VS = 10 V
HD2, VS = 5 V
HD3, VS = 5 V
-90
-100
-110
-120
-130
-140
-150
-160
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
10k
100k
Frequency (Hz)
1M
10k
100k
Frequency (Hz)
1M
D017
D066
VOD = 10 VPP for 10-V supply, VOD = 5 VPP for 5-V supply
VOD = 2 VPP
图6-37. Harmonic Distortion vs Frequency
图6-38. Harmonic Distortion vs Frequency
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-155
-90
-95
VS = 10 V, HD2
VS = 10 V, HD3
VS = 5 V, HD2
VS = 5 V, HD3
VS = 3.3 V, HD2
VS = 3.3 V, HD3
VS = 10 V, HD2
VS = 10 V, HD3
VS = 5 V, HD2
VS = 5 V, HD3
VS = 3.3 V, HD2
VS = 3.3 V, HD3
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
1
10
Differential Output Voltage, VOD (VPP
1
10
Differential Output Voltage, VOD (VPP
)
)
D016
D015
Frequency = 50 kHz
Frequency = 50 kHz, G = –2 V/V
图6-39. Harmonic Distortion vs Differential Output Voltage
图6-40. Harmonic Distortion vs Differential Output Voltage
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6.9 Typical Characteristics: VS = 1.9 V, –1.4 V to ±5 V (continued)
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
125
100
75
6
5
4
3
50
2
25
1
0
0
-25
-50
-75
-100
-125
-150
-1
-2
-3
-4
-5
-6
VS = 10 V
VS = 5 V
VS = 3.3 V
VS = 10 V
VS = 5 V
VS = 3.3 V
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
0
100 200 300 400 500 600 700 800 900
Time (ns)
D022
D023
VOD = 200 mVPP
图6-42. Large-Signal Step Response
图6-41. Small-Signal Step Response
30
10
10
7
A1, A2, Input Referred
Total Output Referred
A1, each input
A2, VREF
5
4
3
2
1
0.7
0.5
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10
100
1k
Frequency (Hz)
10k
100k
D043
D041
1/f corner (A1) = 1.2 kHz, 1/f corner (A2) = 700 Hz
1/f corner (A1, A2) = 30 Hz, 1/f corner (output) = 49 Hz
图6-44. Current Noise Density vs Frequency
图6-43. Voltage Noise Density vs Frequency
65
60
55
50
45
40
35
30
25
20
15
10
7
4
VS = 10 V
VS = 5 V
VS = 3.3 V
1
-2
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
-5
100k
1M
Frequency (Hz)
10M
1M
10M
Frequency (Hz)
100M
D055
D007
图6-45. Output Balance vs Frequency
VS = 5 V, VOD = 20 mVPP
图6-46. Small-Signal Frequency Response vs Temperature
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6.9 Typical Characteristics: VS = 1.9 V, –1.4 V to ±5 V (continued)
TA ≈25°C, A1 input common-mode voltage (VCM) = midsupply, VREF = midsupply, RF (connected between
VOUT+ and VFB) = 0 Ω, RG = open, differential gain (G) = 2 V/V, RL (differential load) = 2 kΩ, and RREF = 0 Ω(unless
otherwise noted).
6
5
3.14
3.12
3.10
3.08
3.06
3.04
3.02
3.00
2.98
2.96
2.94
4
3
2
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
1
0
-1
-2
-3
-4
-5
-6
3
4
5
6
7
8
9
Voltage Supply, VS (V)
10
11
12
13
0
5
10 15 20 25 30 35 40 45 50 55 60
Output Load Current (mA)
D033
D031
图6-48. Quiescent Current vs Voltage Supply
VS = 10 V, single-ended output voltage and load current for A1
and A2
图6-47. Output Saturation Voltage vs Output Load Current
4.00
20
18
16
14
12
10
8
VS = 12.6 V
VS = 10 V
VS = 5 V
VS = 3.3 V
VS = 3 V
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
3.75
3.50
3.25
3.00
2.75
2.50
2.25
6
4
3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
4
5
6
7
8
9
Voltage Supply, VS (V)
10
11
12
13
D034
D035
图6-49. Quiescent Current vs Temperature
图6-50. Power-Down Quiescent Current vs Voltage Supply
1.5
3
1
0.8
0.6
0.4
0.2
0
VOD
PD
1
2
0.5
0
1
0
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
-1
-2
-3
-1.5
0
1
2
3
4
5
6
7
8
9
10
-5
-4
-3
-2
-1
0
1
PD Voltage (V)
2
3
4
5
Time (ms)
D050
D049
VS = 5 V
VS = 10 V
图6-52. Turnon and Turnoff Timing
图6-51. Power-Down Bias Current vs Power-Down Voltage
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7 Detailed Description
7.1 Overview
The OPA862 is a 44-MHz, single-ended-to-differential amplifier suitable for use in high-input impedance analog
front-ends. This device offers a gain-bandwidth product (GBWP) of 400 MHz with a low output-referred voltage
noise of 8.3 nV/√ Hz while consuming only 3.1 mA of quiescent current. The OPA862 includes a REF pin for
output common-mode voltage control using amplifier 2 and a shutdown pin for low-power mode operation that
consumes only 12 µA of quiescent current.
The OPA862 can be configured for a single-ended-to-differential gain of 2 V/V without using any external
resistors. The device can be configured in gains other than 2 V/V by using only two external resistors in the
feedback loop of amplifier 1 (A1) and requires fewer external gain-setting resistors compared to a fully
differential amplifier (FDA). The noninverting input of A1 offers high input impedance (325 MΩ typical) for
interfacing single-ended sensors that often have a non-zero output impedance to differential input analog-to-
digital converters (ADCs). A combination of large 140-V/µs slew rate, 400-MHz GBWP, and nonlinearity
cancellation in the output stages of the two amplifiers results in exceptional distortion and settling performance
for 18-bit systems.
The OPA862 includes an internal capacitor CFILT in the feedback circuit of amplifier 2 (A2) that limits the device
bandwidth to approximately 44 MHz. Although the individual amplifiers have a GBWP of 200 MHz, because of
the architecture of the OPA862, the input and output signal bandwidth must not exceed approximately 44 MHz to
achieve good linearity. High GBWP amplifiers generally have high linearity because they can maintain high loop
gain. The simple architecture of the OPA862 (as compared to an FDA) has an inherent delay between the
outputs VOUT+ and VOUT– that primarily limits the linearity performance versus the high GBWP of the
individual amplifiers. The benefit of the CFILT capacitor is that the CFILT filters and minimizes the noise at the
output beyond the usable frequency of the OPA862.
The VREF pin can be used to set the output common-mode to a desired value. 节 7.4 describes various
configurations that the OPA862 can be used in.
7.2 Functional Block Diagram
VS+
OPA862
œ
VFB
VIN
A1
VOUT+
+
CFILT
6 pF
RLINT
8.4 kꢀ
RINT
700 ꢀ
RINT
700 ꢀ
œ
A2
VOUTœ
+
VREF
PD
VSœ
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7.3 Feature Description
7.3.1 Input and ESD Protection
The OPA862 is built using a high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry devices. These breakdowns are reflected in 节 6.1. As
shown in 图7-1 all device pins are protected with internal ESD protection diodes to the power supplies.
These diodes provide moderate protection to input overdrive voltages beyond the supplies as well. The
protection diodes can typically support 10-mA continuous current. Where higher currents are possible (for
example, in systems with ±12-V supply parts driving into the OPA862), add current limiting series resistors in
series with the inputs to limit the current. Keep these resistor values as low as possible because high values can
degrade both noise performance and frequency response. The OPA862 has back-to-back ESD diodes between
the VIN and VFB pins. As a result, the differential input voltage between the VIN and VFB pins must be limited to
0.7 V or less to keep from forward biasing these back-to-back ESD diodes. The diodes are robust enough to
survive transient conditions such as those common during slew conditions. In the event the differential input
voltage exceeds 0.7 V, these back-to-back diodes forward bias and protect the amplifier but the current must be
limited per the specifications in 节6.1 to avoid permanent damage to these diodes or the amplifier.
VS+
OPA862
VFB
œ
A1
VOUT+
+
RINT
700 ꢀ
VIN
Power Supply
ESD Cell
RINT
700 ꢀ
œ
A2
VOUTœ
VREF
+
VSœ
PD
图7-1. Internal ESD Protection
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7.3.2 Anti-Phase Reversal Protection
When the input common-mode voltage approaches or exceeds VS–, the base-collector junction of the input
transistors forward biases. This condition creates an output path parallel to the normal gm path of the transistors
that is opposite in phase to the gm path. When this parallel path starts to dominate, phase inversion occurs. To
protect against phase inversion, the OPA862 features anti-phase reversal (APR) protection Schottky diodes on
the input transistors. The Schottky diodes turn on at a voltage lower than the forward bias voltage of the base-
collector junction, thus preventing the forward bias and the phase-inversion at the base-collector junction of the
input transistors. 图7-2 shows a diagram of APR protection within the OPA862.
VS+
VIN
VFB
Internal Circuitry
图7-2. Anti-Phase Reversal Protection
7.3.3 Precision and Low Noise
The OPA862 is laser trimmed for high DC precision. An important factor that reduces the DC precision of the
system that uses the OPA862 is the errors introduced by the bias currents of A2 flowing through the internal
feedback resistors, RINT; see 节 7.2. To minimize the error contribution from IB, the A2 amplifier of the OPA862
features a unique IB cancellation mechanism. This IB cancellation mechanism is the reason why the IB of A2 is
orders of magnitude lower than the IB of A1. The DC errors are negligible for most applications because of the
nanoamperes of IB and very low IB drift of A2. However, despite being very low, if the IB errors of A2 are
significant for an application, a 348-Ω RREF resistor can be used on the VREF input to cancel out the IB errors.
The tradeoff of using the RREF is that this resistor introduces noise that is amplified by a factor of two at VOUT–
because of the noise gain of two of A2. The CFILT capacitor (see 节 7.2) also helps filter out the flat band noise
contribution of RREF. The 700-Ω internal resistors were carefully chosen to balance low noise while keeping the
total power dissipation low by taking advantage of the low 3.1-mA quiescent current of the OPA862. As shown in
图 7-3, to get the equivalent 8.3-nV/√ Hz noise of the OPA862 with a typical FDA configuration, the FDA must
be less than 1 nV/√ Hz; such FDAs are often difficult to find or expensive. When RREF equals 0 Ω, the typical
error resulting from the IB of A2 appears as an input-referred offset of 3.5 µV at the VREF input, and when RREF
is 348 Ω, the differential output-referred noise increases from 8.3 nV/√Hz to 9.6 nV/√Hz.
Fully Differential Amplifier
<1 nV/√Hz
OPA862
1 kꢀ
1 kꢀ
1
8
œ
4
5
A1
VOUT+
+
RINT
700 ꢀ
œ
VOD
VOCM
VOD
RINT
+
700 ꢀ
œ
A2
VOUTœ
2
+
1 kꢀ
G = 1 V/V
1 kꢀ
G = 2 V/V
8.3 nV/√Hz
IB noise ignored
图7-3. Equivalent Voltage Noise FDA to OPA862
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7.4 Device Functional Modes
7.4.1 Split-Supply Operation (±1.5 V to ±6.3 V)
To facilitate testing with common lab equipment, the OPA862 can be configured to allow for split-supply
operation. This configuration eases lab testing because the mid-point between the power rails is ground, and
most signal generators, network analyzers, oscilloscopes, spectrum analyzers, and other lab equipment
reference the inputs and outputs to ground. For split-supply operation referenced to ground, the power supplies
VS+ and VS– are symmetrical around ground and generally VREF is also set equal to ground. Split-supply
operation is preferred in systems where the signals swing around ground because of the ease-of-use; however,
the system requires two supply rails.
7.4.2 Single-Supply Operation (3 V to 12.6 V)
Many newer systems use a single power supply to improve efficiency and reduce the cost of the extra power
supply. The OPA862 can be used with a single supply (negative supply set to ground), as shown in 图 7-4, with
no change in performance if the input and output are biased within the linear operation of the device. To change
the circuit from split supply to a single-supply configuration, level shift all the voltages by half the difference
between the power-supply rails. In the single-supply configuration, a voltage must be set on the VREF pin,
typically midsupply, such that VREF does not violate the common-mode input range (CMIR) specification or the
output voltage range of A2. An additional advantage of configuring an amplifier for single-supply operation is that
the effects of PSRR are minimized because the low-supply rail is grounded. See the Single-Supply Op Amp
Design Techniques application report for examples of single-supply designs.
+5 V
OPA862
VS+
œ
1 kꢀ
A1
+
RINT
700 ꢀ
+
VIN
RINT
700 ꢀ
œ
œ
A2
+
1 kꢀ
VSœ
2.5 V
图7-4. Typical Single-Supply Configuration
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Single-Ended-to-Differential Gain of 4 V/V
图 8-1 shows the configuration that can be used for a single-ended-to-differential gain of 4 V/V. Amplifier A1
follows all the conventional equations of a regular voltage-feedback amplifier for inverting and noninverting
gains. With the fixed inverting gain of –1 V/V for the configuration of A2, the primary role of A2 is to invert the
output of A1 so that a differential signal is available at the output pins, VOUT+ and VOUT–. In the configuration
shown in 图 8-1, VOUT+ is always in phase with VIN and equal to VIN times two. VOUT– has the same swing as
VOUT+ but 180° out of phase. The common-mode voltage at A1 is equal to VIN and the common-mode voltage at
A2 is equal to the voltage on the VREF pin, which in the case of 图8-1 is GND.
RG
RF
700 ꢀ
700 ꢀ
+5 V
0.1 µF
3
OPA862
1
8
œ
4
5
A1
VOUT+
+
RINT
700 ꢀ
ROP
1 kꢀ
+
VIN
VOD
RINT
œ
RON
1 kꢀ
700 ꢀ
œ
A2
VOUTœ
VREF
2
+
7
6
VOUT+ and VOUTœ voltages are
with respect to GND
0.1 µF
œ5 V
图8-1. Single-Ended To Differential Gain of 4 V/V Configuration
方程式 1 through 方程式 4 can be derived from the configuration in 图 8-1. The output common-mode voltage,
V
OCM, is the average of VOUT+ and VOUT–, and is equal to the voltage on the VREF pin as given by 方程式4.
≈
’
÷
RF
VOUT+ = V 1+
∆
IN
RG ◊
«
(1)
(2)
(3)
≈
’
÷
RF
VOUT- = -VOUT+ + 2ì VREF = -V 1+
+ 2ì V
∆
IN
REF
RG ◊
«
≈
’
RF
VOD = VOUT+ - VOUT- = 2ì V 1+
- 2ì V
∆
÷
IN
REF
RG ◊
«
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VOUT+ + VOUT-
VOCM
=
= VREF
2
(4)
8.2 Typical Applications
8.2.1 Single-Ended to Differential with 2.5-V Output Common-Mode Voltage
Most real-world signals are single ended. Often, fully differential amplifiers (FDAs) are used for single-ended-to-
differential conversions but the low-impedance input of the FDA configuration can be a challenge for digital
acquisition systems (DAQs). The high input impedance input of the OPA862, coupled with its ability to convert
single-ended inputs to differential outputs, makes the device an excellent choice for DAQs.
+7 V
0.1 µF
3
OPA862
1
œ
4
5
A1
VOUT+
8
+
RINT
700 ꢀ
ROP
1 kꢀ
VIN
VOD
RINT
RON
1 kꢀ
700 ꢀ
œ
A2
VOUTœ
2
+
VREF
2.5 V
=
7
6
VOUT+ and VOUTœ voltages are
with respect to GND
0.1 µF
œ3.3 V
图8-2. Single-Ended to Differential, G = 2 V/V With 2.5-V VOCM Configuration
8.2.1.1 Design Requirements
Use the design requirements shown in 表8-1 to design a single-ended-to-differential output circuit block.
表8-1. Design Requirements
DESIGN PARAMETER
VALUE
Input signal, VIN
1-MHz, 0-5 V, sinusoidal signal
Output common-mode voltage, VOCM
Differential gain, G
2.5 V
2 V/V
2 kΩ
Differential load
8.2.1.2 Detailed Design Procedure
For RF = 0 Ω, with the VFB pin shorted to VOUT+, use 方程式3 to determine that the OPA862 is in a differential
gain of 2 V/V configuration. 方程式 4 describes how setting VREF equal to 2.5 V results in a VOCM of 2.5 V, as
required per the design criteria. When designing a front-end stage with the OPA862, the input common-mode
voltage and the output voltage range of the input and output pins, respectively, must be considered carefully.
Choose the supplies such that none of these voltage ranges are violated and that the single-ended output
voltages at each output do not exceed the maximum allowed voltages of the subsequent stage that the OPA862
is driving. Simulate the transfer characteristics of this circuit to ensure the output voltages are within the desired
operation limits. 图 8-3 illustrates the transfer characteristics for the OPA862 configuration in 图 8-2. The output
waveforms of the circuit in 图8-2 are described in 图8-4 and meets the design requirements of 表8-1.
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8.2.1.3 Application Curves
6
4.5
3
5.5
4.5
3.5
2.5
1.5
1.5
0
0.5
-0.5
-1.5
-2.5
-3.5
-4.5
-5.5
-1.5
-3
VOUT-
VOUT+
VOD
VOUT-
VOUT+
VOD
-4.5
-6
VIN
0
0.5
1
1.5
2
2.5
3
Input voltage, VIN (V)
3.5
4
4.5
5
Time, 250 ns per division
D100
D100
图8-3. DC Transfer Characteristics
8.2.2 Transimpedance Amplifier Configuration
图8-4. Transient Output Response
With recent advancements in light-sensing technology, transimpedance (TIA) applications are becoming popular,
ranging in signal bandwidth needs from tens of kHz to hundreds of MHz. Because the current output of the
photodiode in these TIA applications is unipolar, a key challenge in interfacing with the fully differential input
analog-to-digital converters (ADCs) is maximizing the differential signal to the ADC in order to maximize the
signal-to-noise ratio (SNR).
As illustrated in the output waveform of 图 8-6, only half the differential output signal swing of the FDA is
available. On the contrary, by using the OPA862 as the TIA stage, a single-device interface to the ADC can be
designed that also allows the full differential swing to the ADC and set the desired output common-mode as
shown in 图 8-5. VREF is used to set the output common-mode voltage and VDC is used to DC shift the outputs
such that for a zero photodiode current, VOD (equal to VOUT+ – VOUT–) is at one of the peaks of the desired
differential peak-to-peak swing. Whether the VOD peak at the zero photodiode current is at a high or low peak is
determined by the direction of current through RF in the presence of the photodiode signal current.
VBIAS
CF
RF
OPA862
œ
VOUT+
A1
VOUT+
+
RINT
700 ꢀ
VDC
RINT
VREF
700 ꢀ
œ
A2
VOUTœ
VOUTœ
+
VREF
图8-5. Improved TIA Signal Chain With the OPA862
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GND
TIA VO
VBIAS
TIA Stage
RF
Fully Differential ADC Driver
RG
RF
œ
VO+
+
œ
VOCM
VOCM
+
VOœ
RF
RG
图8-6. Conventional TIA Signal Chain
8.2.2.1 Design Requirements
Use the design requirements shown in 表8-2 to design the TIA circuit block.
表8-2. Design Requirements
DESIGN PARAMETER
VALUE
0 mA to 5 mA
50 pF
Photodiode current, IIN
Photodiode Capacitance, CD
Signal bandwidth
9 MHz
Output common-mode voltage, VOCM
2.5 V
8.2.2.2 Detailed Design Procedure
In most TIA designs, selecting the right photodiode for the application is the most important decision because
the photodiode determines the IIN and CD parameters that in turn determine the bandwidth required from the
amplifier, the realizable TIA gain, and the signal bandwidth. Signal bandwidth also determines the rise time of
the pulses. Choosing the photodiode with as low a capacitance as possible maximizes the TIA signal bandwidth
for a given amplifier. Similarly, choosing a low TIA gain (RF) allows for higher signal bandwidth but having a RF
as high as possible maximizes the SNR of the signal chain.
In order to take advantage of the increased SNR by using the OPA862 as described in 图 8-5, the amplifier is
already chosen. Using the design methodology explained at What You Need To Know About Transimpedance
Amplifiers – Part 1 and the design parameters in 表 8-2, RF can be determined to be 1 kΩ and the required
feedback capacitor, CF, is 22 pF. Because the range of IIN is 0 mA to 5 mA and RF is 1 kΩ, the range of a single-
ended output voltage at VOUT+ is 0 V to 5 V (IIN × RF). In the cathode bias configuration of the photodiode
condition in 图 8-7, when the photodiode is excited the current flows towards VOUT+ through RF, resulting in a
voltage pulse that goes lower from the zero current value. Thus, setting VOUT+ = 5 V and VOUT– = 0 V (VOD = +5
V) is desirable when the current is zero so that when the maximum current pulse of 5 mA occurs, VOUT+ goes to
0 V and VOUT– reaches 5 V (VOD = –5 V). The VOCM target of 2.5 V, which is a typical mid-reference voltage for
differential input ADCs, can be set by choosing VREF = VOCM. The values of VDC and VREF can be determined by
setting the values of VOUT+ and VOUT– to appropriate values at the zero photo-current in the following equations:
• VDC = VOUT+
• VREF = (VOUT– + VDC) / 2 = VOCM
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图8-8 and 图8-9 show the small-signal bandwidth and large-signal step response TINA simulation results of the
circuit in 图8-7.
VBIAS
22 pF CF
1 kꢀ RF
+7 V
0.1 µF
3
OPA862
1
œ
4
5
A1
VOUT+
8
+
RINT
700 ꢀ
VDC
5 V
VOD
RINT
700 ꢀ
œ
A2
VOUTœ
2
+
VREF
2.5 V
7
6
VOUT+ and VOUTœ voltages are
with respect to GND
0.1 µF
œ3.3 V
图8-7. TIA Circuit With the OPA862
8.2.2.3 Application Curves
6
4
6
69
66
63
60
57
54
51
48
45
42
39
4
2
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
VOD
VOUT+
VOUT-
VOUT-
VOUT+
VOD
1.25
IIN
0
0.25
0.5
0.75
Time (ms}
1
1.5
100k
1M
10M
100M
D103
Frequency (Hz)
D102
图8-9. Large-Signal Transient Response
图8-8. Small-Signal Bandwidth
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8.2.3 DC Level-Shifting
Often, applications must level-shift a ground-referenced signal to a non-ground voltage. Configurations in 图
8-10 and 图 8-11 show two different ways of level-shifting a signal by using the OPA862 without having to use
external resistors, saving board cost and space. These configurations leverage the fixed noninverting gain-of-2
configuration of A2 and the summing configuration of A1 to level-shift the signal at VOUT–. The internal
resistors of the OPA862 are extremely well-matched to maintain the gain-of-2 accuracy of A2. Similarly matched
external resistors can add significant cost to the system and often are more expensive than the amplifier itself.
Apart from the polarity of the VDC-shift at the output, a key difference between the configurations of 图 8-10 and
图 8-11 is that in the case of 图 8-10, VDC only must be capable of driving the IB of A1 but in the case of 图 8-11,
VDC must be capable of driving higher currents, as given by I = VDC / RG when a noninverting input of A1 is
grounded.
+7 V
0.1 µF
3
OPA862
1
œ
4
5
A1
VOUT+
VDC
œ2.5 V
=
8
+
RINT
700 ꢀ
VOUTœ
5 V
IB
RINT
2 × VIN
700 ꢀ
VIN
1.25 V
œ
œVDC
A2
VOUTœ
2.5 V
0 V
2
+
7
6
VIN
0 V
-1.25 V
0.1 µF
VOUT+ and VOUTœ voltages are
with respect to GND
œ2.5 V
图8-10. Level-Shifting With a DC Source of Polarity Opposite to the Desired DC Shift
RG = RF
RF
VDC =
2.5 V
+7 V
VDC
I =
RG
0.1 µF
3
OPA862
1
8
œ
4
5
A1
VOUT+
+
RINT
700 ꢀ
VOUTœ
5 V
RINT
2 × VIN
700 ꢀ
VIN
1.25 V
œ
VDC
A2
VOUTœ
2.5 V
0 V
2
+
7
6
VIN
0 V
-1.25 V
0.1 µF
VOUT+ and VOUTœ voltages are
with respect to GND
œ2.5 V
图8-11. Level-Shifting With a DC Source of Polarity Same as the Desired DC Shift
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9 Power Supply Recommendations
The OPA862 is intended to work in a supply range of 3 V to 12.6 V. The OPA862 can be used in single-supply
operation, or in a balanced or unbalanced split-supply operation. Good power-supply bypassing is
recommended for best AC performance and distortion in particular. Minimize the distance (less than 0.1 inch)
from the power-supply pins to high-frequency, 0.1-µF decoupling capacitors. A larger capacitor (2.2 µF or 10 µF
is typical) is used with a high-frequency, 0.1-µF supply decoupling capacitor at the device supply pins. For
single-supply operation, only the positive supply has these capacitors. When a split-supply is used, use these
capacitors for each supply to ground. If necessary, place the larger capacitors further from the device and share
these capacitors among several devices in the same area of the printed circuit board (PCB). Avoid narrow power
and ground traces to minimize inductance between the pins and the decoupling capacitors. An optional 0.1-µF
supply decoupling capacitor across the two power supplies (for bipolar operation) reduces second-order
harmonic distortion.
10 Layout
10.1 Layout Guidelines
Achieving optimum AC performance with a fast amplifier such as the OPA862 requires careful attention to board
layout parasitics and external component types. The OPA862EVM can be used as a reference when designing
the circuit board. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. On the noninverting input, VIN, the device can react with the
source impedance to cause unintentional band limiting. To reduce unwanted capacitance, open a plane
cutout around the signal I/O pins in the ground and power planes below those pins. Otherwise, ground and
power planes must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.1") from the power-supply pins to high-frequency, 0.01-µF or 0.1-µF decoupling
capacitors. At the device pins, do not allow the ground and power plane layout to be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
Larger (2.2-µF to 10-µF) decoupling capacitors, effective at lower frequencies, must also be used on the
supply pins. These capacitors can be placed somewhat farther from the device and shared among several
devices in the same area of the PC board.
3. Careful selection and placement of external components preserve the AC performance of the
OPA862. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film and carbon composition axially leaded resistors can also provide good high
frequency performance. Again, keep their leads and PCB trace length as short as possible. Because the
VOUT+ pin and the VFB pin are the most sensitive to parasitic capacitance, always position the feedback
and series output resistor, if any, as close as possible to the VFB and VOUT+ pins, respectively.
4. Connections to other wideband devices on the board can be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground
and power planes opened up around them.
5. Socketing a high-speed part such as the OPA862 is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create troublesome parasitic network that can make
achieving a smooth, stable frequency response difficult. Best results are obtained by soldering the OPA862
to the board.
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10.2 Layout Examples
RG
RF
VS+
CBYP
3
OPA862
ROP
1
8
œ
4
A1
+
VIN
RINT
700 ꢀ
RINT
700 ꢀ
RON
œ
5
RREF
A2
2
+
6
7
PD
CBYP
VSœ
图10-1. Representative Schematic for Layout in
Ground and power plane exist on
inner layers.
RG
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
VIN
1
2
3
4
8
7
6
5
RF
CBYP
Place bypass capacitors
close to power pins
Vias to connect RREF and CBYP. Place
these components on the other side
of the PCB close to the vias.
ROP
RON
RREF and CBYP not shown as they
are on the other side of the PCB.
Place output resistors close to output
pins to minimize parasitic capacitance
图10-2. Layout Recommendations
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, Single-Supply Op Amp Design Techniques application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA862IDR
OPA862IDT
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
862
862
862
Samples
Samples
Samples
NIPDAU
NIPDAU
OPA862IDTKR
WSON
DTK
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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22-May-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA862IDR
OPA862IDT
SOIC
SOIC
D
D
8
8
8
2500
250
330.0
180.0
330.0
12.4
12.4
12.4
6.4
6.4
3.3
5.2
5.2
3.3
2.1
2.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q2
OPA862IDTKR
WSON
DTK
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA862IDR
OPA862IDT
SOIC
SOIC
D
D
8
8
8
2500
250
356.0
210.0
367.0
356.0
185.0
367.0
35.0
35.0
35.0
OPA862IDTKR
WSON
DTK
3000
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
DTK0008A
3.1
2.9
A
B
3.1
2.9
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
(0.1) TYP
1.5
1.4
6X 0.5
1.75
4
5
8
PKG
1.84
1.64
9
1
0.3
8X
0.2
0.1
0.05
C A B
C
0.5
0.3
PIN 1 ID
(OPTIONAL)
8X
PKG
4224357 / A 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
WSON - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
DTK0008A
(2.8)
(1.45)
8X (0.25)
6X (0.5)
(0.475)
1
8
(0.62)
9
PKG
(1.74)
(1.5)
(R0.05) TYP
4
5
(Ø0.2) VIA
(TYP)
PKG
8X(0.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224357 / A 07/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
WSON - 0.8 mm max height
DTK0008A
PLASTIC QUAD FLATPACK- NO LEAD
(2.8)
(1.34)
8X (0.25)
6X (0.5)
1
8
PKG
(1.5) (1.58)
(R0.05) TYP
5
4
9
8X(0.6)
PKG
EXPOSED METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 9: 84%
SCALE: 20X
4224357 / A 07/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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