OPA875IDR [TI]
Single 2:1 High-Speed Video Multiplexer; 单身2 ： 1高速视频多路复用器
| 型号： | OPA875IDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single 2:1 High-Speed Video Multiplexer |
| 文件： | 总18页 (文件大小：660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA875
SBOS340–DECEMBER 2006
Single 2:1 High-Speed Video Multiplexer
FEATURES
DESCRIPTION
•
700MHz SMALL-SIGNAL BANDWIDTH
(AV = +2)
The OPA875 offers a very wideband, single-channel
2:1 multiplexer in an SO-8 or a small MSOP-8
package. Using only 11mA, the OPA875 provides a
gain of +2 video amplifier channel with > 425MHz
large-signal bandwidth (4VPP). Gain accuracy and
switching glitch are improved over earlier solutions
using a new input stage switching approach. This
technique uses current steering as the input switch
while maintaining an overall closed-loop design. With
> 700MHz small-signal bandwidth at a gain of 2, the
OPA875 gives a typical 0.1dB gain flatness to
> 200MHz.
•
•
•
•
•
•
•
425MHz, 4VPP BANDWIDTH
0.1dB GAIN FLATNESS to 200MHz
4ns CHANNEL SWITCHING TIME
LOW SWITCHING GLITCH: 40mVPP
3100V/µs SLEW RATE
0.025%/0.025° DIFFERENTIAL GAIN, PHASE
HIGH GAIN ACCURACY: 2.0V/V ±0.4%
APPLICATIONS
System power may be reduced using the chip enable
feature for the OPA875. Taking the chip enable line
high powers down the OPA875 to < 300µA total
supply current. Muxing multiple OPA875 outputs
together, then using the chip enable to select which
channels are active, increases the number of
possible inputs.
•
•
•
•
•
RGB SWITCHING
LCD PROJECTOR INPUT SELECT
WORKSTATION GRAPHICS
ADC INPUT MUX
DROP-IN UPGRADE TO LT1675-1
Where three channels are required, consider using
the OPA3875 for the same level of performance.
EN
Ch 0
75W
75W
75W
OPA875
(Patented)
Out
OPA875 RELATED PRODUCTS
DESCRIPTION
Ch 1
SEL
Channel Select
OPA3875
OPA692
OPA693
Triple-Channel OPA875
225MHz Video Buffer
700MHz Video Buffer
2:1 Video Multiplexer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
OPA875
www.ti.com
SBOS340–DECEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION
SPECIFIED
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
OPA875ID
OPA875IDR
Rails, 75
OPA875
SO-8
D
–40°C to +85°C
–40°C to +85°C
OPA875
BPL
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
OPA875IDGKT
OPA875IDGKR
OPA875
MSOP-8
DGK
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range, unless otherwise noted.
OPA875
UNIT
Power Supply
±6.5
V
Internal Power Dissipation
Input Voltage Range
See Thermal Analysis
±VS
–40 to +125
+260
V
Storage Temperature Range
Lead Temperature (soldering, 10s)
Operating Junction Temperature
Continuous Operating Junction Temperature
ESD Rating:
°C
°C
°C
°C
+150
+140
Human Body Model (HBM)
Charge Device Model (CDM)
Machine Model
2000
1500
200
V
V
V
PIN CONFIGURATION
Table 1. TRUTH TABLE
OPA875
Top View
MSOP, SO
SELECT
ENABLE
VOUT
R0
OPA875
1
0
0
0
1
R1
1
2
3
4
8
7
6
5
+VS
Chip Enable (EN)
Output (VOUT
Channel Select (SEL)
Channel 0 (V0)
X
Off
GND
Channel 1 (V1)
-VS
)
402
402
2
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OPA875
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SBOS340–DECEMBER 2006
ELECTRICAL CHARACTERISTICS: VS = ±5V
At G = +2, RL = 150Ω, unless otherwise noted.
OPA875
MIN/MAX OVER
TYP
TEMPERATURE
0°C to
+70°C(3)
–40°C to
+85°C(3)
MIN/
MAX
TEST
LEVEL(1)
PARAMETER
CONDITIONS
See Figure 1
+25°C
+25°C(2)
UNITS
AC PERFORMANCE
Small-Signal Bandwidth
Large-Signal Bandwidth
Bandwidth for 0.1dB Gain Flatness
Maximum Small-Signal Gain
Minimum Small-Signal Gain
SFDR
VO = 200mVPP, RL = 150Ω
VO = 4VPP, RL = 150Ω
VO = 200mVPP
700
425
200
2.0
525
390
515
380
505
370
MHz
MHz
MHz
V/V
min
min
typ
B
B
C
B
B
B
B
B
C
C
B
C
C
VO = 200mVPP, RL = 150Ω, f = 5MHz
VO = 200mVPP, RL = 150Ω, f = 5MHz
10MHz, VO = 2VPP, RL = 150Ω
f > 100kHz
2.02
1.98
–64
7.0
2.03
1.97
–63
7.2
2.05
1.95
–62
7.4
max
min
max
max
max
typ
2.0
V/V
–66
6.7
dBc
nV/√Hz
pA/√Hz
%
Input Voltage Noise
Input Current Noise
f > 100kHz
3.8
4.2
4.6
4.9
NTSC Differential Gain
NTSC Differential Phase
Slew Rate
RL = 150Ω
0.025
0.025
3100
460
600
RL = 150Ω
°
typ
VO = ±2V
2800
2700
2600
V/µs
ps
min
typ
Rise Time and Fall Time
VO = 0.5V Step
VO = 1.4V Step
ps
typ
CHANNEL-TO-CHANNEL PERFORMANCE
Gain Match
RL = 150Ω
±0.05
±3
±0.25
±9
±0.3
±10
±0.35
±12
%
mV
dB
max
max
typ
A
A
C
Output Offset Voltage Mismatch
Crosstalk
f < 50MHz, RL = 150Ω
–65
CHANNEL AND CHIP-SELECT
PERFORMANCE
SEL (Channel Select) Switching Time
EN (Chip Select) Switching Time
RL = 150Ω
Turn On
4
9
ns
ns
typ
typ
C
C
C
C
C
C
A
A
A
A
Turn Off
60
40
30
–70
ns
typ
SEL (Channel Select) Switching Glitch
EN (Chip-Select) Switching Glitch
Off Isolation
Both Inputs to Ground, At Matched Load
Both Inputs to Ground, At Matched Load
50MHz, Chip Disabled (EN = High)
EN, A0, A1
mVPP
mVPP
dB
typ
typ
typ
Maximum Logic 0
0.8
2.0
35
0.8
2.0
45
0.8
2.0
50
V
max
min
max
max
Minimum Logic 1
EN, A0, A1
V
EN Logic Input Current
SEL Logic Input Current
DC PERFORMANCE
Output Offset Voltage
Average Output Offset Voltage Drift
Input Bias Current
0V to 4.5V
25
55
µA
0V to 4.5V
70
85
100
µA
RIN = 0Ω, G = +2V/V
±2.5
±5
±14
±18
1.4
±15.8
±50
±17
±50
mV
µV/°C
µA
max
max
max
max
max
A
B
A
B
A
±19.5
±40
±20.5
±40
Average Input Bias Current Drift
Gain Error (from 2V/V)
INPUT
nA/°C
%
VO = ±2V
0.4
1.5
1.6
Input Voltage Range
Input Resistance
±2.8
1.75
0.9
V
MΩ
pF
pF
pF
min
typ
typ
typ
typ
C
C
C
C
C
Input Capacitance
Channel Selected
Channel Deselected
Chip Disabled
0.9
0.9
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C tested specifications.
(3) Junction temperature = ambient at low temperature limit; junction temperature = ambient +14°C at high temperature limit for over
temperature specifications.
3
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OPA875
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SBOS340–DECEMBER 2006
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2, RL = 150Ω, unless otherwise noted.
OPA875
MIN/MAX OVER
TYP
TEMPERATURE
0°C to
+70°C(3)
–40°C to
+85°C(3)
MIN/
MAX
TEST
LEVEL(1)
PARAMETER
CONDITIONS
+25°C
+25°C(2)
UNITS
OUTPUT
Output Voltage Range
Output Current
Output Resistance
±3.5
±70
0.3
800
800
2
±3.4
±50
±3.35
±45
±3.3
±40
V
mA
Ω
min
min
typ
A
A
C
A
A
C
VO = 0V, Linear Operation
Chip enabled
Chip Disabled, Maximum
Chip Disabled, Minimum
Chip Disabled
912
688
915
685
918
682
Ω
max
min
typ
Ω
Output Capacitance
pF
POWER SUPPLY
Specified Operating Voltage
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Maximum Quiescent Current
Power-Supply Rejection Ratio
±5
V
V
typ
min
max
max
min
max
min
min
C
B
A
A
A
A
A
A
±3.0
±6.0
11.5
10
±3.0
±6.0
11.7
9.5
±3.0
±6.0
12
V
Chip Selected, VS = ±5V
Chip Selected, VS = ±5V
Chip Deselected
11
11
mA
mA
µA
dB
dB
9
300
56
500
50
550
48
600
47
(+PSRR)
(–PSRR)
Input-Referred
Input-Referred
55
51
49
48
THERMAL CHARACTERISTICS
Specified Operating Range D Package
–40 to +85
°C
typ
C
Thermal Resistance θJA
Junction-to-Ambient
D
SO-8
+100
+140
°C/W
°C/W
typ
typ
C
C
DGK
MSOP-8
4
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OPA875
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SBOS340–DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = ±5V
At G = +2 and RL = 150Ω, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
7
6
5
4
3
2
0.3
1
0
0.2
0.1
-1
-2
-3
-4
-5
-6
0
-0.1
-0.2
-0.3
-0.4
5VPP
4VPP
500mVPP
1VPP
2VPP
VO = 500mVPP
1
0
RL = 150W
G = +2V/V
1M
10M
100M
Frequency (Hz)
1G
0
200M
400M
600M
800M
1G
Frequency (Hz)
Figure 1.
Figure 2.
NONINVERTING PULSE RESPONSE
DISABLE FEEDTHROUGH vs FREQUENCY
0.5
0.4
2.5
0
Input-Referred
BW = +5V
RL = 150W
2.0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
G = +2V/V
Large-Signal 4VPP
Small-Signal 0.4VPP
0.3
1.5
0.2
1.0
0.1
0.5
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
-1.0
-1.5
-2.0
-2.5
100MHz Square-Wave Input
Time (1ns/div)
1M
10M
100M
Frequency (Hz)
1G
Figure 3.
Figure 4.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
80
70
60
50
40
30
20
10
0
8
7
0.1dB Peaking Targeted
CL = 10pF
6
5
4
3
CL = 47pF
2
1
RS
CL = 100pF
x2
75W
0
(1)
1kW
CL
-1
-2
-3
CL = 22pF
75W
NOTE: (1) 1kW is optional.
1
10
100
1000
1M
10M
100M
400M
Capacitive Load (pF)
Frequency (Hz)
Figure 5.
Figure 6.
5
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SBOS340–DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-60
VO = 2VPP
VO = 2VPP
RL = 150W
f = 10MHz
f = 10MHz
-65
2nd-Harmonic
-70
2nd-Harmonic
3rd-Harmonic
-75
-80
3rd-Harmonic
-85
dBc = dB Below Carrier
dBc = dB Below Carrier
-90
±2.5
±3.0
±3.5
±4.0
±4.5
±5.0
±5.5
±6.0
100
1k
Supply Voltage (±VS)
Resistance (W)
Figure 7.
Figure 8.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-55
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
VO = 2VPP
RL = 150W
RL = 150W
-60
-65
f = 10MHz
-70
2nd-Harmonic
2nd-Harmonic
-75
-80
-85
3rd-Harmonic
-90
3rd-Harmonic
-95
-100
-105
dBc = dB Below Carrier
dBc = dB Below Carrier
0.5
1.5
2.5
3.5
4.5
5.5
6.5 7.0
1M
10M
100M
Output Voltage Swing (VPP
)
Frequency (Hz)
Figure 9.
Figure 10.
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
5
4
-50
1W Internal
Power Limit
RL = 100W
Load Power at Matched 50W Load
3
-60
-70
dBc = dB Below Carrier
2
100W Load Line
25W Load Line
1
0
50MHz
-1
-2
-3
-4
-5
-80
20MHz
10MHz
50W Load Line
-90
1W Internal
Power Limit
-100
-200 -150 -100 -50
0
50
100
150
200
-6
-4
-2
0
2
4
6
8
10
IO (mA)
Single-Tone Load Power (dBm)
Figure 11.
Figure 12.
6
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SBOS340–DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
CHANNEL SWITCHING
CHANNEL-TO-CHANNEL SWITCHING TIME
1.5
1.0
1.5
1.0
0.5
0.5
Output Voltage
0
-0.5
-1.0
0
-0.5
-1.0
-1.5
Output Voltage
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-1.5
VSEL
VSEL
RL = 150W
VIN_Ch0 = +0.5VDC
VIN_RI = 400MHz, 1VPP
VIN_RO = 0VDC
VIN_Ch1 = -0.5VDC
-0.5
-0.5
Time (5ns/div)
Time (5ns/div)
Figure 13.
Figure 14.
CHANNEL SWITCHING GLITCH
DISABLE/ENABLE TIME
30
1.5
1.0
At Matched Load
Output Voltage
20
0.5
10
0
0
-0.5
-1.0
-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-10
-20
VEN
7.5
5.0
2.5
0
VSEL
VIN_Ch1 = 0V
VIN_Ch0 = 200MHz, 1VPP
-2.5
-0.5
Time (10ns/div)
Time (20ns/div)
Figure 15.
Figure 16.
DISABLE/ENABLE SWITCHING GLITCH
CHANNEL-TO-CHANNEL CROSSTALK
15
At Matched Load
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
Input-Referred
5
0
-5
-10
-15
Ch 0 Selected
Ch 1 Driven
5.0
2.5
0
VEN
Ch 1 Selected
Ch 0 Driven
-100
-110
-2.5
Time (100ns/div)
1M
10M
100M
Frequency (Hz)
1G
Figure 17.
Figure 18.
7
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SBOS340–DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At G = +2 and RL = 150Ω, unless otherwise noted.
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
INPUT IMPEDANCE vs FREQUENCY
10k
10M
1M
Disabled
1k
100
10
100k
10k
1k
1
Enabled
0.1
100
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 19.
Figure 20.
PSRR vs FREQUENCY
SUPPLY CURRENT vs TEMPERATURE
18
16
14
12
10
8
60
50
40
30
20
10
0
-PSRR
+PSRR
6
4
2
100
1k
10k
100k
1M
10M
100M
1G
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Ambient Temperature (°C)
Figure 21.
Figure 22.
TYPICAL DC DRIFT OVER TEMPERATURE
INPUT VOLTAGE AND CURRENT NOISE
100
3.0
2.5
2.0
1.5
1.0
8
6
4
2
0
VOS
IB
10
Voltage Noise (6.7nV/ÖHz)
Input Current Noise (3.8pA/ÖHz)
1
10
100
1k
10k
100k
1M
10M
100M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Ambient Temperature (°C)
Figure 23.
Figure 24.
8
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SBOS340–DECEMBER 2006
APPLICATIONS INFORMATION
1-BIT HIGH-SPEED PGA
TRANSMIT/RECEIVE SWITCH
The OPA875 can be used as a 1-bit, high-speed
programmable gain amplifier (PGA) when used in
conjunction with another amplifier. Figure 25 shows
the OPA695 used twice with one amplifier configured
in a unity-gain structure, and the other amplifier
configured in a gain of +8V/V.
The OPA875 can be used as a transmit/receive
switch in which the receive channel is disconnected,
when the OPA875 is switched from channel 0 to
channel 1, to prevent the transmit pulse from going
through the receive signal chain. This architecture is
shown in Figure 26.
When channel 0 is selected, the overall gain to the
matched load of the OPA875 is 0dB. When channel
1 is selected, this circuit delivers an 18dB gain to the
matched load.
HIGH ISOLATION RGB VIDEO MUX
Three OPA875s can be used as a triple, 2:1 video
MUX (see Figure 27). This configuration has the
advantage of having higher R to G to B isolation than
a comparable and more integrated solution does,
such as the OPA3875, especially at higher
frequencies. This comparison is shown in Figure 28.
+5V
+5V
OPA695
OPA875
50W
Channel 0
x1
-5V
IN
50W
523W
x2
50W
50W
Source
50W
Channel 1
50W
Load
+5V
x1
OPA695
-5V
-5V
402W
57.6W
Figure 25. 1-Bit, High-Speed PGA
OPA875
Receive Channel
Channel 0
x1
x1
x2
Channel 1
Figure 26. Transmit/Receive Switch
9
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SBOS340–DECEMBER 2006
4-INPUT RGB ROUTER
OPA875_A
OPA875_B
OPA875_C
Two OPA875s can be used together to form a
four-input RGB router. The router for the red
component is shown in Figure 29.
x1
x1
Ch 0
ROUT
GOUT
BOUT
x2
x2
x2
OPA875
Ch 1
R1
x1
x1
RO
69W
x2
x1
x1
Ch 0
R2
EN
Ch 1
R3
x1
x1
RO
69W
Red
Out
x2
75W
x1
x1
Ch 0
R4
EN
Chip
Select
Ch 1
Figure 29. 4-Input RGB Router
Figure 27. High Isolation RGB Video MUX
When connecting OPA875 outputs together, maintain
a gain of +1 at the load. The OPA875 operates at a
gain of +6dB; thus, matching resistance must be
selected to achieve –6dB attenuation.
0
OPA3875
All Hostile
Crosstalk
Input-Referred
OPA3875
Adjacent Channel
Crosstalk
-10
-20
-30
-40
-50
-60
-70
-80
-90
The set of equations to solve are shown in
Equation 1 and Equation 2. Here, the impedance of
interest is ZO = 75Ω.
OPA875_C
Ch. 0 Driven
Adjacent Channel Crosstalk
RO = ZO || (R + RF + RG)
RF
1 +
= 2
RG
(1)
(2)
OPA875
All Hostile
Crosstalk
OPA875_A
Ch. 1 Driven, Adjacent
Channel Crosstalk
RF + RG = 804W
RF = RG
100
1
10
1G
Frequency (MHz)
Solving for RO with n devices connected together, we
get Equation 3:
Figure 28. All-Hostile and Adjacent Channel
Crosstalk
75 ´ (n - 1) + 804
241200
[75 ´ (n - 1) + 804]2
RO
=
´
1 +
- 1
2
The configuration of the three OPA875 devices used
is shown in Figure 27. Note that for the test, the
OPA875_B was measured when both the
OPA875_A and OPA875_C were driven for all
hostile crosstalk and only the OPA875_A or
OPA875_C was driven for the adjacent channel
crosstalk.
(3)
10
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Results for n varying from 2 to 6 are given in
Table 2.
OPERATING SUGGESTIONS
DRIVING CAPACITIVE LOADS
Table 2. Series Resistance versus Number of
Parallel Outputs
One of the most demanding, yet very common load
conditions is capacitive loading. Often, the capacitive
load is the input of an ADC—including additional
external capacitance that may be recommended to
improve ADC linearity. A high-speed device such as
the OPA875 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the device open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
problem have been suggested. When the primary
considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest
and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series
isolation resistor between the amplifier output and
the capacitive load. This isolation resistor does not
eliminate the pole from the loop response, but rather
shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the
capacitive load pole, thus increasing the phase
margin and improving stability.
NUMBER OF OPA875s
RO (Ω)
69
2
3
4
5
6
63.94
59.49
55.59
52.15
The two major limitations of this circuit are the device
requirements for each OPA875 and the acceptable
return loss because of the mismatch between the
load (75Ω) and the matching resistor.
DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
A printed circuit board (PCB) is available to assist in
the initial evaluation of circuit performance using the
OPA875. The fixture is offered free of charge as an
unpopulated PCB, delivered with a user's guide. The
summary information for this fixture is shown in
Table 3.
The Typical Characteristics show the recommended
RS versus capacitive load and the resulting
frequency response at the load; see Figure 5.
Parasitic capacitive loads greater than 2pF can begin
to degrade the performance of the OPA875. Long
PCB traces, unmatched cables, and connections to
multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and
add the recommended series resistor as close as
possible to the OPA875 output pin (see the Board
Layout Guidelines section).
Table 3. OPA875 Demonstration Fixture
ORDERING
NUMBER
LITERATURE
NUMBER
PRODUCT
OPA875IDGK
OPA875ID
PACKAGE
MSOP-8
SO-8
DEM-TIV-MSOP-1A
DEM-TIV-SO-1A
SBOU044
SBOU045
The demonstration fixture can be requested at the
Texas Instruments web site at (www.ti.com) through
the OPA875 product folder.
MACROMODELS AND APPLICATIONS
SUPPORT
DC ACCURACY
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF amplifier circuits
where parasitic capacitance and inductance can
have a major effect on circuit performance. A SPICE
model for the OPA875 is available through the Texas
Instruments web site at www.ti.com. These models
do a good job of predicting small-signal AC and
The OPA875 offers excellent DC signal accuracy.
Parameters that influence the output DC offset
voltage are:
•
•
•
•
•
Output offset voltage
Input bias current
Gain error
Power-supply rejection ratio
Temperature
transient performance under
a wide variety of
operating conditions. They do not do as well in
predicting the harmonic distortion or dG/dP
characteristics. These models do not attempt to
distinguish between the package types in their
small-signal AC performance.
11
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Leaving both temperature and gain error parameters
aside, the output offset voltage envelope can be
described as shown in Equation 4:
PSRR+
are extremely low at low output power levels. The
output stage continues to hold them low even as the
fundamental power reaches very high levels. As the
Typical
Characteristics
show,
the
spurious
VOSO_envelope = VOSO + (RS·Ib) x G ± |5 - (VS+)| x 10-
20
intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not
decrease significantly. For two tones centered at
20MHz, with 4dBm/tone into a matched 50Ω load
(that is, 1VPP for each tone at the load, which
requires 4VPP for the overall 2-tone envelope at the
output pin), the Typical Characteristics show a 82dBc
difference between the test-tone power and the
3rd-order intermodulation spurious levels.
PSRR-
20
± |-5 - (VS-)| x 10-
(4)
With:
VOSO: Output offset voltage
RS: Input resistance seen by R0, R1, G0, G1,
B0, or B1.
Ib: Input bias current
G: Gain
NOISE PERFORMANCE
VS+: Positive supply voltage
VS–: Negative supply voltage
PSRR+: Positive supply PSRR
PSRR–: Negative supply PSRR
The OPA875 offers an excellent balance between
voltage and current noise terms to achieve low
output noise. As long as the AC source impedance
looking out of the noninverting node is less than
100Ω, this current noise will not contribute
significantly to the total output noise. The device
input voltage noise and the input current noise terms
combine to give low output noise under a wide
variety of operating conditions. Figure 30 shows this
device noise analysis model with all the noise terms
included. In this model, all noise terms are taken to
be noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
Evaluating the front-page schematic, using
a
worst-case, +25°C offset voltage, bias current and
PSRR specifications and operating at ±6V, gives a
worst-case output equal to Equation 5:
50
20
-
14mV + 75W x 18mA x 2 |5 - 6| x 10
51
20
-
|-5 - (-6)| x 10
= ±22.7mV
(5)
+5V
DISTORTION PERFORMANCE
en
OPA875
The OPA875 provides good distortion performance
into a 100Ω load on ±5V supplies. Relative to
alternative solutions, it provides exceptional
performance into lighter loads. Generally, until the
fundamental signal reaches very high frequency or
power levels, the 2nd-harmonic dominates the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the
load impedance improves distortion directly. Also,
providing an additional supply decoupling capacitor
(0.01µF) between the supply pins (for bipolar
operation) improves the 2nd-order distortion slightly
(3dB to 6dB).
+1
+1
RS
ib
eO
+2
eR
S
-5V
Channel
Select
EN
Figure 30. Noise Model
In most op amps, increasing the output voltage
swing increases harmonic distortion directly. The
Typical Characteristics show the 2nd-harmonic
increasing at a little less than the expected 2X rate
while the 3rd-harmonic increases at a little less than
the expected 3X rate. Where the test power doubles,
the 2nd-harmonic increases only by less than the
expected 6dB, whereas the 3rd-harmonic increases
by less than the expected 12dB. This also shows up
in the two-tone, 3rd-order intermodulation spurious
(IM3) response curves. The 3rd-order spurious levels
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 6 shows the
general form for the output noise voltage using the
terms shown in Figure 30.
en2 + (ibRS)2 + 4kTRS
eo = 2
(6)
12
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SBOS340–DECEMBER 2006
Dividing this expression by the device gain (2V/V)
gives the equivalent input-referred spot noise voltage
at the noninverting input as shown in Equation 7.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with
a
high
frequency amplifier such as the OPA875 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
en2 + (ibRS)2 + 4kTRS
en =
(7)
Evaluating these two equations for the OPA875
circuit and component values shown in Figure 30
gives a total output spot noise voltage of 13.6nV/√Hz
and a total equivalent input spot noise voltage of
6.8nV/√Hz. This total input-referred spot noise
voltage is higher than the 6.7nV/√Hz specification for
the mux voltage noise alone. This number reflects
the noise added to the output by the bias current
noise times the source resistor.
a) Minimize parasitic capacitance to any AC
ground for all of the signal I/O pins. Parasitic
capacitance on the output pin can cause instability:
on the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To
reduce unwanted capacitance, a window around the
signal I/O pins should be opened in all of the ground
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.
THERMAL ANALYSIS
Heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired
junction temperature will set the maximum allowed
internal power dissipation as discussed in this
document. In no case should the maximum junction
temperature be allowed to exceed +150°C.
b) Minimize the distance (< 0.25") from the
power-supply pins to high frequency 0.1µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The
power-supply connections (on pins 9, 11, 13, and 15)
should always be decoupled with these capacitors.
An optional supply decoupling capacitor across the
two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger
(2.2µF to 6.8µF) decoupling capacitors, effective at
lower frequency, should also be used on the main
supply pins. These may be placed somewhat farther
from the device and may be shared among several
devices in the same area of the PCB.
Operating junction temperature (TJ) is given by TA +
PD × θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load but, for a grounded resistive load, be
at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal
2
bipolar supplies). Under this condition PDL = VS /(4 ×
RL), where RL includes feedback network loading.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA875. Resistors should be a
very low reactance type. Surface-mount resistors
Note that it is the power in the output stage and not
in the load that determines internal power
dissipation.
work best and allow
a tighter overall layout.
As a worst-case example, compute the maximum TJ
using an OPA875IDGK in the circuit of Figure 30
operating at the maximum specified ambient
temperature of +85°C with its outputs driving a
grounded 100Ω load to +2.5V:
Metal-film and carbon composition, axially leaded
resistors can also provide good high-frequency
performance. Again, keep their leads and printed
circuit board (PCB) trace length as short as possible.
Never use wirewound type resistors in
a
PD = 10V x 11mA + (52 [4 x (100W || 804W) ] ) = 180mW
high-frequency application. Other network
components, such as noninverting input termination
resistors, should also be placed close to the
package.
Maximum TJ = +85°C + (0.18mW x 140°C/W) = 110°C
This worst-case condition does not exceed the
maximum junction temperature. Normally, this
extreme case is not encountered. Careful attention to
internal power dissipation is required.
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them.
13
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SBOS340–DECEMBER 2006
Estimate the total capacitive load and set RS from
the plot of Figure 5. Low parasitic capacitive loads (<
5pF) may not need an RS because the OPA875 is
nominally compensated to operate with a 2pF
parasitic load. If a long trace is required, and the 6dB
e) Socketing a high-speed part like the OPA875 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA875 onto the board.
signal loss intrinsic to
a
doubly-terminated
transmission line is acceptable, implement
a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout
techniques). A 50Ω environment is normally not
necessary on board, and in fact, a higher impedance
environment will improve distortion as shown in the
Distortion versus Load plots. With a characteristic
board trace impedance defined based on board
material and trace dimensions, a matching series
resistor into the trace from the output of the OPA875
is used as well as a terminating shunt resistor at the
input of the destination device. Remember also that
the terminating impedance will be the parallel
combination of the shunt resistor and the input
impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. The high output voltage and current
capability of the OPA875 allows multiple destination
devices to be handled as separate transmission
lines, each with their own series and shunt
INPUT AND ESD PROTECTION
The OPA875 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins have limited ESD protection using
internal diodes to the power supplies as shown in
Figure 31.
+VCC
External
Pin
Internal
Circuitry
-VCC
terminations. If the 6dB attenuation of
a
Figure 31. Internal ESD Protection
doubly-terminated transmission line is unacceptable,
a long trace can be seriesterminated at the source
end only. Treat the trace as a capacitive load in this
case and set the series resistor value as shown in
Figure 5. This will not preserve signal integrity as
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA875), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible because
high values degrade both noise performance and
frequency response.
well as
a doubly-terminated line. If the input
impedance of the destination device is low, there will
be some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
OPA875ID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA875IDG4
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
D
75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA875IDGKR
OPA875IDGKRG4
OPA875IDGKT
OPA875IDGKTG4
OPA875IDR
DGK
DGK
DGK
DGK
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA875IDRG4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 1
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OPA8785VM/883B
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