OPT4048DTST_技术文档

OPT4048

ZHCSNT7 –DECEMBER 2022

OPT4048 高速高精度三色XYZ 颜色传感器

• 自动白平衡

• 楼宇自动化与控制

1 特性

• 照明控制系统

• 平板电脑和笔记本电脑

• 通过高速I2C 接口实现高精度、高速颜色光/数转换

• 使用精密光学滤波器的四通道感应：

– XYZ 三色通道与CIE 1931 光谱密切匹配，具有

出色的红外抑制功能

– 清晰的宽带宽通道

3 说明

OPT4048 是一款单芯片高分辨率颜色传感器，能够测

量四个通道，每个通道具有特定设计的光谱响应。四个

通道中的三个通道与 CIE 三色光谱非常匹配，第四个

通道具有宽带光谱响应。通过从这些通道进行测量，可

以提取照明环境的重要特性，例如 (i) 光强度 (lux)、(ii)

CIE XY 中的颜色、LUV 坐标以及 (iii) 相关色温。

OPT4048 采用小型SOT-5X3 封装。

• CIE XY 中的高分辨率颜色测量、LUV 空间、相关

色温(CCT) 以及环境照度测量

• 半对数输出，具有7 个二进制对数满标度照度范

围，在每个范围内具有高度线性响应

• 内置自动满标度照度范围选择逻辑，可根据输入光

条件切换测量范围，范围之间具有良好的增益匹配

• 26 位有效动态范围，从2.15mlux 到144klux

• 12 个可配置转换时间，每个通道为600μs 到

800ms，适用于各种高速和高精度应用

• 针对硬件同步触发和中断的外部引脚中断

• 低工作电流：24μA，具有超低待机功耗：2μA

• 工作温度范围：–40°C 至+85°C

• 宽电源范围：1.6V 至3.6V

OPT4048 具有可选寻址方案，可在共享的 I²C 总线上

启用多达 4 个器件。这些通道的光谱响应经过专门调

节，可紧密模拟 CIE 三色光谱，从而实现超精确的颜

色检测，同时强烈抑制远离其各自峰值的波长，尤其是

NIR（850nm 和 940nm）区域。这些滤波器采用先进

的滤波技术，即使在更高的光入射角下也能提供出色的

滤波性能。该器件具有高精度颜色检测功能，支持多种

需要精确检测环境光颜色和色温的应用。

• 耐受5.5V 电压的I/O

• 可选择的I²C 地址

• 小巧的外形：

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

OPT4048

– 2.1mm x 1.9mm x 0.6mm SOT-5X3 封装

2.10mm X 1.90mm X

0.6mm

SOT-5X3 (8)

2 应用

(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。

• 显示亮度和颜色调整

• 摄像头图像校正

2

CH0 (X)

CH1 (Y)

1.8

CH2 (Z)

CH3 (W)

1.6

CIE X

CIE Y

CIE Z

1.4

1.2

1

0.8

0.6

0.4

0.2

0

Cover Glass

OPT4048

lux

CIE XYZ/U'V'

CCT in K

I²C

350

450

550

650

750

850

950

Wavelength (nm)

归一化光谱响应

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBOSA84

OPT4048

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Table of Contents

8.4 Register Maps...........................................................24

9 Application and Implementation..................................33

9.1 Application Information............................................. 33

9.2 Typical Application.................................................... 33

9.3 Do's and Don'ts.........................................................36

9.4 Power Supply Recommendations.............................37

9.5 Layout....................................................................... 37

10 Device and Documentation Support..........................39

10.1 Documentation Support.......................................... 39

10.2 接收文档更新通知................................................... 39

10.3 支持资源..................................................................39

10.4 Trademarks.............................................................39

10.5 Electrostatic Discharge Caution..............................39

10.6 术语表..................................................................... 39

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions.........................4

7.4 Thermal Information....................................................4

7.5 Electrical Characteristics.............................................5

7.6 Typical Characteristics................................................7

8 Detailed Description........................................................9

8.1 Overview.....................................................................9

8.2 Functional Block Diagram.........................................10

8.3 Feature Description...................................................10

Information.................................................................... 39

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

December 2022

*

Initial release.

2

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5 说明（续）

OPT4048 上设计的光学滤波器提供了强大的红外抑制功能，尽管传感器放置在深色玻璃下（这是最终产品工业设

计出于美学考虑的常见要求），但这一功能也有助于保持高精度。

OPT4048 专为需要照度级别检测的系统而设计，通过提供有关照明强度和照明颜色的信息来增强用户体验。

OPT4048 器件可通过每个通道12 个步骤配置为以 600μs 到800ms 的光转换时间运行，从而能够根据应用需要

提供系统灵活性。转换时间包括光采集时间和ADC 转换时间。测量分辨率由光强度和采集时间两者决定，能够有

效地测量低至2.15mlux 的光强度变化。

数字操作可灵活用于系统集成。测量可以是连续的，也可以通过寄存器写入或硬件引脚单次触发。此器件提供了

阈值检测逻辑，这允许处理器进入睡眠状态，直到传感器检测到适当的唤醒事件并通过中断引脚进行报告。

数字输出，表示通过兼容I²C 和SMBus 的双线制串行接口报告照度级别。

OPT4048 兼具低功耗和低电源电压功能，有助于延长电池供电系统的电池寿命。

6 Pin Configuration and Functions

SDA

INT

NC

1

2

3

4

8

7

6

5

VDD

ADDR

NC

GND

SCL

图6-1. DTS Package, 8-Pin SOT-5X3, Top View

表6-1. Pin Functions

TYPE

DESCRIPTION

NO.

1

NAME

VDD

ADDR

NC

Power

Digital input

No Connection

Power

Device power. Connect to a 1.6-V to 3.6-V supply.

2

Address pin. This pin sets the LSBs of the I²C address.

3

No Connection

4

GND

SCL

NC

Ground

I²C clock. Connect with a 10-kΩresistor to a 1.6-V to 5.5-V supply.

5

Digital input

No Connection

Digital I/O

6

No Connection

7

INT

Interrupt input/output open-drain. Connect with a 10-kΩresistor to a 1.6-V to 5.5-

V supply.

I²C data. Connect with a 10-kΩresistor to a 1.6-V to 5.5-V supply.

8

SDA

Digital I/O

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

6

UNIT

V

Voltage

VDD to GND

SDA and SCL to GND

6

V

Current in to any pin

10

mA

°C

T_J

Junction temperature

Storage temperature

150

150⁽²⁾

T_stg

°C

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) Long exposure to temperatures higher than 105°C can cause package discoloration, spectral distortion, and measurement inaccuracy.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.6

NOM

MAX

3.6

UNIT

V

VDD

T_J

Supply voltage

Junction temperature

85

°C

–40

7.4 Thermal Information

OPT4048

THERMAL METRIC⁽¹⁾

DTS

8 Pins

112.2

28.4

22.1

1.2

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

22

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

4

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7.5 Electrical Characteristics

All specifications at TA = 25°C, VDD = 3.3 V, 100-ms conversion-time per channel, automatic full-scale range, white LED and

normal-angle incidence of light, unless otherwise specified. Spec parameters are preliminary, subject to change.over

operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Optical

Number of Channels

4

600

550

460

500

CH0 (X)

CH1(Y)

CH2(Z)

CH3(W)

nm

bits

ms

Peak irradiance spectral responsivity

ʎ_peak

ADC resolution

9

20

Range determination

3

25

Conversion-time CT = 0x6

Conversion-time CT = 0xB

T_intg

Light Integration-time per channel ⁽⁴⁾

800

codes

per

CH0 (X) Lowest auto gain range, 800 ms

conversion time per channel

R_CH0

2770

3960

1910

μW/cm²

codes

per

μW/cm²

CH1 (Y) Lowest auto gain range, 800 ms

conversion time per channel

R_CH1

R_CH2

R_CH3

Peak Responsivity

codes

per

μW/cm²

CH2 (Z) Lowest auto gain range, 800 ms

conversion time per channel

codes

per

μW/cm²

CH3 (W) Lowest auto gain range, 800 ms

conversion time per channel

6950

17.2

Lowest auto gain range, 100 ms

conversion-time per channel

mlux

ER_lux

Equivalent Resolution

Lowest auto gain range, 800 ms

conversion-time per channel

2.15

144284

2000

mlux

lux

E_vFS

E_v

Full-scale equivalent Illuminance

Measurement output result from lux

measurement

2000 lux input⁽¹⁾

All channels

1800

2200

lux

Relative accuracy between gain ranges

0.6

0.2

%

(2)

850nm near infra-red, all channels except

for CH3 (W)

E_vIR

Infrared response⁽⁶⁾

Light source variation for lux

measurement (incandescent, halogen,

fluorescent)

Bare device, no cover glass

4

%

Input illuminance > 2254 lux , 100 ms

conversion-time per channel, all channels

2

5

%

Linearity

Input illuminance <= 2254 lux , 100 ms

conversion-time per channel, all channels

Dark Measurement

All channels

CH0 (X)

0

0.02

0.05

10 codes

%/°C

CH1 (Y)

%/°C

Drift across temperature

CH2 (Z)

%/°C

CH3 (W)

%/°C

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7.5 Electrical Characteristics (continued)

All specifications at TA = 25°C, VDD = 3.3 V, 100-ms conversion-time per channel, automatic full-scale range, white LED and

normal-angle incidence of light, unless otherwise specified. Spec parameters are preliminary, subject to change.over

operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

134

121

99

MAX

UNIT

CH0 (X)

CH1 (Y)

CH2 (Z)

CH3 (W)

°

Angular response (FWHM)

128

VDD at 3.6 V and 1.6 V, 30 different

sources, all channels

PSRR

Power-supply rejection ratio⁽³⁾

0.2

%/V

POWER SUPPLY

V_DD

V_I2C

Power supply

Power supply for I²C pull up resistor

1.6

3.6

5.5

V

I²C pullup resistor, V_DD≤_VI2C

Dark

24

29

2

µA

V

I_QACTIVEActive Current

Full-scale lux

Dark

I_Q

Quiescent current

Full-scale lux

2.6

0.8

POR

Power-on-reset threshold

DIGITAL

C_IO

I/O Pin Capacitance

3

pF

V

Low-level input voltage (SDA, SCL, and

ADDR)

0.3 X

V_DD

V_IL

V_IH

0

High-level input voltage (SDA, SCL, and

ADDR)

0.7 X

V_DD

5.5

V

Low-level input current (SDA, SCL, and

ADDR)

I_IL

0.01

0.25⁽⁵⁾

0.32

µA

V

V_OL

I_ZH

Low-level output voltage (SDA and INT)

I_OL=3mA

Output logic high, high-Z leakage current

(SDA, INT)

Measured with V_DDat pin

0.25⁽⁵⁾

µA

TEMPERATURE

Specified temperature range

85

°C

–40

(1) Tested with the white LED calibrated to 2000 lux.

(2) Characterized by measuring fixed near-full-scale light levels on the higher adjacent full-scale range setting.

(3) PSRR is the percent change of the measured lux output from the current value, divided by the change in power supply voltage, as

characterized by results from 3.6-V and 1.6-V power supplies.

(4) The conversion-time, from start of conversion until the data are ready to be read, is the integration-time plus analog-to-digital

conversion-time.

(5) The specified leakage current is dominated by the production test equipment limitations. Typical values are much smaller.

(6) Tested with a near infrared LED of 850nm wavelength.

6

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7.6 Typical Characteristics

At T_A= 25°C, V_DD= 3.3 V, 800-ms conversion time (CONVERSION_TIME = 0xB), automatic full-scale range (RANGE =

0xC), white LED, and normal-angle incidence of light, unless otherwise specified.

2

1.8

1.6

1.4

1.2

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

CH0 (X)

CH1 (Y)

CH2 (Z)

CH3 (W)

CH0 (X)

CH1 (Y)

CH2 (Z)

CH3 (W)

CIE X

CIE Y

CIE Z

0.8

0.6

0.4

0.2

0

-100 -80 -60 -40 -20

0

20

40

60

80 100

350

450

550

650

750

850

950

Illuminance Angle (°)

Wavelength (nm)

Normalized to 0°

spacer

Channels measurements scaled to match CIE curves

spacer

图7-2. Device Response vs Illuminance Angle

图7-1. Spectral Response vs Wavelength

1.5

1.45

1.4

1.14

1.12

1.1

1.35

1.3

1.08

1.06

1.04

1.02

1

1.25

1.2

1.15

1.1

0.98

0.96

0.94

1.05

1

0.001 0.01

0.1

1

10

100 1000 10000 100000

0.001 0.01

0.1

1

10

100 1000 10000 100000

Input Illuminance (Lux)

Normalized to dark condition

图7-3. Active Current vs Input Light Level

图7-4. Standby Current vs Input Light Level

1.1

1.08

1.06

1.04

1.02

1

1.05

1.04

1.03

1.02

1.01

1

0.99

0.98

0.97

0.96

0.95

0.94

0.98

0.96

0.94

0.92

0.9

1.6 1.8

2

2.2 2.4 2.6 2.8

Power Supply (V)

3

3.2 3.4 3.6

1.6 1.8

2

2.2 2.4 2.6 2.8

Power Supply (V)

3

3.2 3.4 3.6

Normalized to 3.3 V

图7-6. Standby Current vs Power Supply

Normalized to 3.3 V

图7-5. Active Current vs Power Supply

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7.6 Typical Characteristics (continued)

At T_A= 25°C, V_DD= 3.3 V, 800-ms conversion time (CONVERSION_TIME = 0xB), automatic full-scale range (RANGE =

0xC), white LED, and normal-angle incidence of light, unless otherwise specified.

1.0029

1.0026

1.0023

1.002

1.036

1.032

1.028

1.024

1.02

E=0

E=1

E=2

E=3

E=4

E=5

E=6

1.0017

1.0014

1.0011

1.0008

1.0005

1.0002

0.9999

0.9996

1.016

1.012

1.008

1.004

1

100

500 1000

10000

100000 300000

1.6 1.8

2

2.2 2.4 2.6 2.8

Supply Voltage(V)

3

3.2 3.4 3.6

Input Illuminance (Lux)

E denotes register EXPONENT_CHx

Normalized to 25 ms

Normalized to 3.3 V

图7-7. Device Response vs Power Supply

图7-8. Conversion Time at 25 ms per channel vs Input Light

Level

1.1

1.08

1.06

1.04

1.02

1

1.4

1.35

1.3

1.25

1.2

1.15

1.1

0.98

0.96

0.94

0.92

0.9

1.05

1

0.95

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature (°C)

Normalized to 25°C

spacer

图7-10. Standby Current vs Temperature

图7-9. Active Current vs Temperature

1.05

1.04

1.03

1.02

1.01

1

CH0 (X)

CH1 (Y)

CH2 (Z)

CH3 (W)

0.99

0.98

0.97

0.96

0.95

0.94

-40

-20

0

20

40

60

80

100

Temperature (°C)

Normalized to 25°C

图7-11. Device Response vs Temperature

8

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8 Detailed Description

8.1 Overview

The OPT4048 measures the color properties of the light source that illuminates the device. This device

measures four channels (X Channel, Y Channel, Z Channel, W Channel) with special spectral characteristics,

which helps extract properties of the light source (i) the CIE XY/U'V' color coordinates (ii) the lux level and (iii)

the correlated color temperature. Name of the channels correspond to the respective CIE tristimulus curves with

additional W channel being the wide channel response.

With close matching to the CIE tristimulus spectral profiles, OPT4048 measures the true color of any light source

or environment. This helps applications where, measuring the precise characteristics of the lighting environment

is critical like display brightness, color temperature adjustment, camera color temperature correction, object true

color recognition & medical applications.

Since CIE tristimulus curves are devised to mimic human color perception, matching the sensor spectral

response to those curves is vital because color sensors are used to measure and help create excellent human

lighting experiences. Strong rejection of infrared light, which a human does not see, is a crucial component of

this matching. This matching makes the OPT4048 especially good for operation underneath windows that are

visibly dark, but infrared transmissive

OPT4048 is fully self-contained to measure the properties of light and report the result in ADC codes digitally

over the I²C bus. The result can also be used to alert a system and interrupt a processor with the INT pin. The

result can also be summarized with a programmable threshold comparison with a specified channel and

communicated with the INT pin.

OPT4048 is by default configured to operate in automatic full-scale range detection mode that always selects the

best full-scale range setting for the given lighting conditions. There are 7 full-scale range settings, one of which

can be selected manually as well. Setting the device to operate in automatic full-scale range detection mode

frees the user from having to program their software for potential iterative cycles of measurement and

readjustment of the full-scale range until good for any given measurement. With device exhibiting excellent

linearity over the entire 26 bit dynamic range of measurement no additional linearity calibration is required at

system level.

The OPT4048 contains 4 channels, results of which are always available all the time as independent channel

registers which can be digitally read over the I²C bus synchronously or asynchronously.

The device measures light for 4 channels sequentially (X, Y, Z, W) with selectable conversion times from 600 μs

per channel to 800 ms per channel in 12 steps. Measurements can be read asynchronously or interrupt pin

based which can be configured to generate an interrupt every time a single channel completes conversion or

every time all 4 channels complete conversion.

The device starts up in a low-power shutdown state, such that the OPT4048 only consumes active-operation

power after being programmed into an active state.

OPT4048 optical filtering system is not excessively sensitive to small particles and micro-shadows on the optical

surface. This reduced sensitivity is a result of the relatively minor device dependency on uniform density optical

illumination of the sensor area for infrared rejection. Proper optical surface cleanliness is always recommended

for best results on all optical devices.

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8.2 Functional Block Diagram

VDD

2

OPT4048

I C

SCL

CH0 (X)

Interface

Ambient

AGC

SDA

Light

CH0 (X)

CH1 (Y)

CH2 (Z)

CH3 (W)

CH1 (Y)

ADC

ADDR

CH2 (Z)

INT

Controller

CH3 (W)

GND

8.3 Feature Description

8.3.1 Spectral Matching to CIE

The OPT4048 spectral response closely matches CIE 1931 tristimulus spectra, which is modeled to be a close

representation of how an average human perceives light. This is crucial to measure the characteristics of light

such an color, intensity as close as possible to how humans perceive.

OPT4048 also has excellent infrared light (IR) rejection. This IR rejection is especially important because many

real-world lighting sources have significant infrared content that humans do not see. If the sensor measures

infrared light that the human eye does not see, then a true human experience is not accurately represented.

If the application demands hiding OPT4048 underneath dark window (such that the end-product user cannot see

the sensor) the infrared rejection of the OPT4048 becomes significantly more important because many dark

windows attenuate visible light but transmit infrared light. This attenuation of visible light and lack of attenuation

of IR light amplifies the ratio of the infrared light to visible light that illuminates the sensor. Results can still be

well matched to the human eye under this condition because of the high infrared rejection of the OPT4048.

8.3.2 Automatic Full-Scale Range Setting

The OPT4048 has an automatic full-scale range setting feature that eliminates the need to predict and set the

best range for the device. Each channel has a auto-scaling algorithm and independently tracks light levels. In

this mode, the OPT4048 automatically selects the best full-scale range for the given lighting condition. The

OPT4048 has a high degree of result matching between the full-scale range settings. This matching eliminates

the problem of varying results or the need for range-specific, user-calibrated gain factors when different full-scale

ranges are chosen. The device has independent range detection logic making the device operate seamlessly

with a wide range of light color and levels.

8.3.3 Output Register CRC and Counter

OPT4048 device features additional bits as part of the output register which helps in improving the reliability of

light measurements for the application.

8.3.3.1 Output Sample Counter

The OPT4048 device features registers COUNTER_CHx as part of the output registers which increments for

every successful measurement. This register can be read as part of the output registers which helps the

application to keep track of measurements. The 4 bit counter starts at 0 on power-up and counts up to 15 after

which the counter resets back to 0 and continues to count up. There are independent counters for each channel

counting up every successful conversion.

• Host or the controller needs consecutive measurements. Utilizing the COUNTER_CHx registers allow the

controller to compare samples and makes sure that the samples are in expected order without missing

intermediate counter values.

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• As a safety feature where when light level are not changing, the controller can make sure that the

measurements from OPT4048 are not stuck by comparing values of registers COUNTER_CHx between

measurements. If the COUNTER_CHx values continue to change over samples, the device is updating the

output register with the most recent measurement of light levels.

8.3.3.2 Output CRC

CRC_CHx registers consists of Cyclic Redundancy Checker bits part of the output registers calculated within the

OPT4048 device and updated on every measurement. This feature helps in detecting communication related bit

errors during the output readout from the device. The calculation method for the CRC bits is shown in the 图

8-12, which can be independently verified in the controller or host firmware/software to validate if communication

between the controller and the device was successful without bit errors during transmission.

8.3.3.3 Threshold Detection

OPT4048 features a threshold detection logic which can be programmed to indicate and update register flags if

measured light levels cross thresholds set by the user. The threshold condition can be programmed to use one

of the 4 channels as trigger determined by the THRESHOLD_CH_SEL register. There are independent low and

high threshold target registers with independent flag registers to indicate the status of measured light level.

Measured light level reaching below low threshold and above the high threshold are called faults. Users can

program a fault count register, which counts consecutive number of faults before the flag registers are set.

Details on the register and setting up the threshold is available in 节8.3.4.2 and 节8.3.4.5.

8.3.4 Device Functional Modes

8.3.4.1 Modes of Operation

OPT4048 has output registers which are always available to readout to get measurements, the measurements

themselves are updated based on the device mode of operation listed below. The OPT4048 device has the

following modes of operation:

• Power-down mode: This is power-down or standby mode where the device enters a low power state. There

is no active light sensing or conversion in this mode. Device still responds to I²C transactions which can be

utilized to bring the device out of this mode.

• Continuous mode: In this mode OPT4048 measures all 4 channels in a round robin fashion continuously

and updates their corresponding output registers. The conversion time register CONVERSION_TIME

determines the time between each channel conversion and a hardware interrupt on pin INT is generated for

every successful conversion on each channel or all 4 channels depending on INT_CFG register value. TI

recommends to configure the INT pin in output mode using the INT_DIR register. The device active circuits

are continuously kept active to minimize the interval between measurements.

• One shot mode of operation: There are several ways in which OPT4048 can be used in one shot mode of

operation with one common theme which is that OPT4048 stays in standby mode and a conversion is

triggered by a register write either by a register write to configuration register or hardware interrupt on the INT

pin. Every trigger generates one measurement for 4 channels, effectively taking four times the time set by the

CONVERSION_TIME register

There are two types of one shot modes.

– Force auto-range one shot mode: Every one shot trigger forces a full reset on auto-ranging control logic

and a fresh auto-range detection in initiated ignoring the previous measurements. This is particularly

useful in situation where lighting conditions are expected to change a lot and one shot trigger frequency is

not very often. There is small penalty on conversion time due for the auto-ranging logic to recover from

reset state. The full reset cycle on the auto-ranging control logic takes around 500 μs which needs to be

accounted for between measurements when this mode is used.

– Regular auto-range one shot mode: Auto-range selection logic utilizes the information from the previous

measurements to decide on range for the current trigger. This mode is recommended only when the

device needs time synchronized measurements with frequent triggers from the controller. In other words,

this mode can be used as an alternative to continuous mode the key difference being that the interval

between measurements in determined by the one shot triggers.

One Shot can be triggered using by the following:

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– Hardware trigger: INT pin can be configured to be an input to trigger a measurement using INT_DIR

register. Since INT pin is used as input, there is no hardware interrupt to indicate completion of

measurement. The controller needs to keep time from the trigger mechanism and read out output

registers.

– Register trigger: An I²C write to the M register triggers a measurement. The register value is reset after a

successful measurement. INT pin can be configured to indicate measurement completion to read out

output registers using the INT_DIR register.

TI highly recommends to set the interval between subsequent triggers to account for all the aspects involved

in the trigger mechanism like the I²C transaction time, device wake-up time, auto-range time (if used) and 4

times the device conversion time.

Since the device enters standby after each one shot trigger, measurement interval on the one shot trigger

mechanism needs to account for additional time T_ssas specified in the specification table for the circuits to

recover from standby state. However setting the quick wake up register QWAKE eliminates the need for this

additional T_ssat the cost of not powering down the active circuit with device not entering the standby mode

between triggers.

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Continuous Mode (INT_CFG=3)

Measurement

(n+1)

Output registers

INT (output)

(n+2)

(n-1)

(n)

Interrupt_(n+1)

Interrupt_(n)

Interrupt_(n-1)

4 X Conversion Time

Active Power

Device Power

Continuous Mode (INT_CFG=1)

Measurement

(n+1)

Output registers

INT (output)

(n+2)

(n-1)

(n)

Interrupt_(n+1)

Interrupt_(n)

Interrupt_(n-1)

1 X Conversion Time

Active Power

Device Power

INT (input)

One-shot Mode (Pin Trigger)

Trigger_(n)

4 X Conversion Time

Trigger_(n+1)

4 X Conversion Time

Measurement

(n)

Measurement

Standby

Output registers

Device Power

(n-1)

(n+1)

Active Power

Standby

Active Power

Standby

_{Trigger bi}O_{ts s}n_ete_by-_Cs_onh_troo_llet_rMode (Register Trigger)

Config register

Trigger bits reset by Device

Trigger_(n+1)

Trigger bits reset by Device

Trigger_(n)

4 X Conversion Time

Measurement

(n)

Output registers

Measurement

(n-1)

(n+1)

INT (output)

Interrupt_(n)

Standby

Interrupt_(n+1)

Standby

Active Power

Standby

Device Power

图8-1. Timing Diagrams for different Operating modes

8.3.4.2 Interrupt Modes of Operation

The device has an interrupt reporting system that allows the processor connected to the I²C bus to go to sleep,

or otherwise ignore the device results, until a user-defined event occurs that requires possible action.

Alternatively, this same mechanism can also be used with any system that can take advantage of a single digital

signal that indicates whether the light is above or below levels of interest.

Channel on which this behavior can be enabled is set by the register THRESHOLD_CH_SEL.

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The INT pin has an open-drain output, which requires the use of a pull-up resistor. This open-drain output allows

multiple devices with open-drain INT pins to be connected to the same line, thus creating a logical NOR or AND

function between the devices. The polarity of the INT pin can be controlled by the INT_POL.

There are two major types of interrupt reporting mechanism modes: latched window comparison mode and

transparent hysteresis comparison mode. The configuration register LATCH controls which of these two modes

is used. 图 8-2 and 表 8-1 summarize the function of these two modes. Additionally, the INT pin can either be

used to indicate a fault in one of these modes (INT_CFG=0) or to indicate a conversion completion (INT_CFG

>0). This is shown in 表8-2.

图8-2. Interrupt Pin Status (for INT_CFG=0 setting) and Register Flag Behavior

表8-1. Interrupt Pin Status (for INT_CFG=0 setting) and Register Flag Behavior

INT Pin State (when

LATCH Setting

FLAG_H Value

FLAG_L Value

Latching Behavior

INT_CFG=0)

INT pin indicates if

measurement is above

(INT active) or below (INT

inactive) the threshold. If

measurement is between

the high and low threshold

values then the previous

INT value is maintained.

This prevents the INT pin

from repeated toggling

when the measurement

values are close to the

threshold.

0: If measurement is

below the low limit

1: If measurement is

above the high limit

If measurement is

between high and low

limits previous value is

maintained

0: If measurement is

above the high limit

1: If measurement is

below the low limit

If measurement is

between high and low

limits previous value is

maintained

Not latching: Values are

updated after each

conversion

0: Transparent hysteresis

mode

INT pin becomes active if

the measurement is

outside the window (above

high threshold or below

the low threshold). The

INT pin does not reset and

return to the inactive state

until register 0xC is read.

Latching: INT pin,

FLAG_H and FLAG_L

values do not reset until

the register 0x0C is read.

1: If measurement is

above the high limit

1: If measurement is

below the low limit

1: Latched window mode

The THRESHOLD_H, THRESHOLD_L, LATCH and FAULT_COUNT registers control the interrupt behavior. The

LATCH field setting allows a choice between the latched window mode and transparent hysteresis mode as

shown in the table. Interrupt reporting can be observed on INT pin, the FLAG_H, and the FLAG_L registers.

Results from comparing the current sensor measurements with THRESHOLD_H and THRESHOLD_L registers

are referred to as fault events. The calculations to set these registers can be found in 节 8.3.4.5. The

FAULT_COUNT register dictates the number of continuous fault events required to trigger an interrupt event and

subsequently change the state of the interrupt reporting mechanisms. For example, with a FAULT_COUNT value

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of 2 corresponding to 4 fault counts, the INT pin, FLAG_H and FLAG_L states shown in the table are not

realized unless 4 consecutive measurements are taken that satisfy the fault condition.

INT pin function listed in 表 8-1 is valid only when INT_CFG=0. The INT pin function can be changed to indicate

an end of conversion as well shown in 表 8-2. The FLAG_H and FLAG_L registers continue to behave as listed

in 表8-1 even while INT_CFG>0. The polarity of the INT pin is controlled by the INT_POL register.

表8-2. INT_CFG Setting and Resulting INT Pin Behavior

INT_CFG Setting

INT Pin Function

0

As per 表8-1

INT pin asserted with 1us pulse width after conversion of every

channel

1

3

INT pin asserted with 1us pulse width every 4 conversions to indicate

all channel measurements are complete

8.3.4.3 Light Range Selection

The OPT4048 has an automatic full-scale-range setting mode that eliminates the need for a user to predict and

set the best range for the device. This mode is entered when register RANGE is set to 0xC. The device

determines the appropriate full-scale range to take the measurement based on a combination of current lighting

conditions and the previous measurement.

If a measurement is towards the low side of full-scale, then the full-scale range is decreased by one or two

settings for the next measurement. If a measurement is towards the upper side of full-scale, the full-scale range

is increased by one setting for the next measurement.

If the measurement exceeds the full-scale range, resulting from a fast increasing optical transient event, then the

current measurement is aborted. This invalid measurement is not reported. If the scale is not at the maximum,

then the device increases the scale by one step and a new measurement is retaken with that scale. Therefore,

during a fast increasing optical transient in this mode, a measurement can possibly take longer to complete and

report than indicated by the configuration register CONVERSION_TIME.

The logic that determines the appropriate range settings for each channel is independent of each other, which

verifies a support of a wide range of colors represented with the best accuracy.

TI highly recommends to use this feature, since the device selects the best range setting based on lighting

condition. However, there is an option to manually set the range. Setting the range manually turns off the

automatic full-scale selection logic and the device operates for a particular range setting.

表8-3. Range Selection Table

RANGE register setting

Typical Full-scale Light level

0

1

2254 lux

4509 lux

2

9018 lux

3

18036 lux

4

36071 lux

72142 lux

5

6

144284 lux

12

Determined by automatic full-scale range logic

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8.3.4.4 Selecting Conversion Time

OPT4048 device offers several conversion times to select from. Conversion Time is defined as the time to take

for one measurement to complete for one channel and update the results in output register. Since OPT4048 is 4

channel device the actual time to complete a 4 channel measurement is 4 times the time specified in the

CONVERSION_TIME register. Measurement initiation is determined by the mode of operation as specified in 节

8.3.4.1.

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表8-4. Conversion Time Selection

CONVERSION_TIME Register

Typical Conversion Time Per Channel

0

1

600 μs

1 ms

2

1.8 ms

3.4 ms

6.5 ms

12.7 ms

25 ms

3

4

5

6

7

50 ms

8

100 ms

200 ms

400 ms

800 ms

9

10

11

8.3.4.5 Light and Color Measurement

The OPT4048 device measures light on 4 independent channels and updates output registers with proportional

ADC codes. Updated are based on the mode of operation as described in 节 8.3.4.1. If readout of output

registers is performed before a successful completion of a measurement, the previous measurement is what

would be read out. Output of the each channel is represented by two parts (i) 4 bits of EXPONENT_CHx and (ii)

20 bits of MANTISSA_CHx. This arrangement of binary logarithmic full-scale range with linear representation

with in a range, helps in covering a large dynamic range of measurements. MANTISSA here represents the

linear ADC codes proportional to the measured light within a given full-scale range and the EXPONENT_CHx

represents the current-full scale range selected. The selected range can be automatically determined by the

auto-range selection logic or manually selected as per 表8-3.

Lux level can be determined using the following equations:

MANTISSA_CHx=(RESULT_MSB_CHx<<8) + RESULT_LSB_CHx

(1)

or

MANTISSA_CHx=(RESULT_MSB_CHx x 2^8) + RESULT_LSB_CHx

(2)

where RESULT_MSB_CHx, RESULT_LSB_CHx and EXPONENT_CHx are registers part of the output register

for each channel

RESULT_MSB_CHx register carries the most significant 12 bits of the MANTISSA_CHx and RESULT_LSB_CHx

register carries the least significant 8 bits of the MANTISSA_CHx. MANTISSA_CHx is then computed using the

above equations to get the 20 bit number. EXPONENT_CHx is directly read from the register which is 4 bits.

Once the EXPONENT_CHx and MANTISSA_CHx portions are calculated the linearized ADC_CODES_CHx is

calculated using the following equation:

ADC_CODES_CHx = (MANTISSA_CHx<<EXPONENT_CHx)

(3)

or

ADC_CODES_CHx = (MANTISSA_CHx x 2^EXPONENT_CHx)

(4)

With maximum value for register EXPONENT_CHx being 8 ADC_CODES is effectively a 28 bit number. The

semi-logarithmic numbers have been converted to a linear ADC_CODES_CHx representation making simple to

convert to lux and CIE XY color coordinates

Conversion of the raw ADC codes to the CIE colorimetric X, Y and lux are given by the equation below

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m0x m0y m0z m0l

m1x m1y m1z m1l

m2x m2y m2z m2l

m3x m3y m3z m3l

adc_codes_cℎ0 adc_codes_cℎ1 adc_codes_cℎ2 adc_codes_cℎ3 ∙

= x y z lux

(5)

x

CIEx =

CIEy =

(6)

(7)

x + y + z

y

x + y + z

The conversion matrix can be customized based on target application and details for the same can be found in

节9.2.4.

Lux Calculations

As listed in the 方程式 5 lux values can be obtained along with the color information as part of the matrix.

However, isolating the lux calculations from the matrix can be useful. In that case, the matrix can be simplified to

remove lux calculations as shown below

m0x m0y m0z

m1x m1y m1z

adc_codes_cℎ0 adc_codes_cℎ1 adc_codes_cℎ2 adc_codes_cℎ3 ∙

= x y z

(8)

(9)

m2x m2y m2z

m3x m3y m3z

Lux can be simply calculated using the following equation

lux = adc_codes_ch1 x 2.15e-3

Threshold Detection Calculations

Threshold result registers THRESHOLD_H_RESULT and THRESHOLD_H_RESULT are 12 bit, while threshold

exponent registers THRESHOLD_H_EXPONENT and THRESHOLD_L_EXPONENT are 4 bits. Since threshold

is compared at linear ADC_CODES_CHx, the threshold registers are padded with zeros internally as shown to

compare with the ADC_CODES_CHx

ADC_CODES_TH = THRESHOLD_H_RESULT << (8 + THRESHOLD_H_EXPONENT)

ADC_CODES_TH = THRESHOLD_H_RESULT x 2^(8 + THRESHOLD_H_EXPONENT)

ADC_CODES_TL = THRESHOLD_L_RESULT << (8 + THRESHOLD_L_EXPONENT)

ADC_CODES_TL=THRESHOLD_L_RESULT x 2^(8 + THRESHOLD_L_EXPONENT)

(10)

(11)

(12)

(13)

(14)

or

and

or

Threshold are then compared as shown to detect Fault events.

If ADC_CODES_CHx < ADC_CODES_TL a Fault Low is detected

and

If ADC_CODES_CHx > ADC_CODES_TH a Fault High is detected

(15)

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Based on the FAULT_COUNT register setting, with consecutive Fault High or Fault Low events, respective

FLAG_H and FLAG_L registers are set. Clearly understanding the difference between

THRESHOLD_H_EXPONENT,

THRESHOLD_H_RESULT,

THRESHOLD_L_EXPONENT,

THRESHOLD_L_RESULT and the output registers is important to be able to set appropriate threshold based on

application needs. More details can be found in 节8.3.4.2.

8.3.4.6 Light Resolution

The OPT4048 device's effective resolution is dependent on both the conversion time setting and the full-scale

light range. Although the LSB resolution of the linear ADC_CODES doesn’t change, the effective or useful

resolution of the device is dependent on the conversion time setting and the full-scale range as per the table

below. In conversion times where the effective resolution is lower, the LSBs are padded with 0.

表8-5. Resolution Table

EXPONENT

0

1

2

3

4

5

6

MANTES

SA

effective

bits

CONVERSION_ Conversion

Full-scale

lux

2254

4509

9018

18036

36071

72142

144284

TIME register

Time

Effective Resolution in lux

0

1

600 us

1 ms

9

4.4

8.8

4.4

17.6

8.8

35.2

17.6

70.45

35.2

140.9

70.45

35.2

281.8

140.9

70.45

35.2

10

11

12

13

14

15

16

17

18

19

20

2.2

2

1.8 ms

3.4 ms

6.5 ms

12.7 ms

25 ms

1.1

2.2

4.4

8.8

17.6

3

550.4 m

275.2 m

137.6 m

68.8 m

34.4 m

17.2 m

8.6 m

1.1

2.2

4.4

8.8

17.6

4

550.4 m

275.2 m

137.6 m

68.8 m

34.4 m

17.2 m

8.6 m

4.30 m

1.1

2.2

4.4

8.8

17.6

5

550.4 m

275.2 m

137.6 m

68.8 m

34.4 m

17.2 m

8.6 m

1.1

2.2

4.4

8.8

6

550.4 m

275.2 m

137.6 m

68.8 m

34.4 m

17.2 m

1.1

2.2

4.4

7

50 ms

550.4 m

275.2 m

137.6 m

68.8 m

34.4 m

1.1

2.2

8

100 ms

200 ms

400 ms

800 ms

550.4 m

275.2 m

137.6 m

68.8 m

1.1

9

550.4 m

275.2 m

137.6 m

10

11

4.30 m

2.15 m

As shown in the table above the resolution of the device is dependent on the CONVERSION_TIME and full-

scale range. A similar scaling applies to the peak responsitivity for each channel.

8.3.4.7 Programming

The OPT4048 supports the transmission protocol for standard mode (up to 100 kHz), fast mode (up to 400 kHz),

and high-speed mode (up to 2.6 MHz). Fast and standard modes are described as the default protocol, referred

to as F/S. High-speed mode is described in the 节8.3.4.7.2.1.

8.3.4.7.1 I²C Bus Overview

The OPT4048 offers compatibility with both I²C and SMBus interfaces. The I²C and SMBus protocols are

essentially compatible with one another. The I²C interface is used throughout this document as the primary

example with the SMBus protocol specified only when a difference between the two protocols is discussed.

The device is connected to the bus with two pins: an SCL clock input pin and an SDA open-drain bidirectional

data pin. The bus must have a controller device that generates the serial clock (SCL), controls the bus access,

and generates start and stop conditions. To address a specific device, the controller initiates a start condition by

pulling the data signal line (SDA) from a high logic level to a low logic level while SCL is high. All targets on the

bus shift in the target address byte on the SCL rising edge, with the last bit indicating whether a read or write

operation is intended. During the ninth clock pulse, the target being addressed responds to the controller by

generating an acknowledge bit by pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data

transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a

start or stop condition. When all data are transferred, the controller generates a stop condition, indicated by

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pulling SDA from low to high while SCL is high. The device includes a 28-ms timeout on the I²C interface to

prevent locking up the bus. If the SCL line is held low for this duration of time, the bus state machine is reset.

8.3.4.7.1.1 Serial Bus Address

To communicate with the OPT4048, the controller must first initiate an I²C start command. Then, the controller

must address target devices via a target address byte. The target address byte consists of a seven bit address

and a direction bit that indicates whether the action is to be a read or write operation.

Four I²C addresses are possible by connecting the ADDR pin to one of four pins: GND, VDD, SDA, or SCL.

Table below summarizes the possible addresses with the corresponding ADDR pin configuration. The state of

the ADDR pin is sampled on every bus communication and must be driven or connected to the desired level

before any activity on the interface occurs.

ADDR PIN CONNECTION

DEVICE I²C ADDRESS

GND

VDD

SDA

SCL

1000100

1000101

1000110

1000101

8.3.4.7.1.2 Serial Interface

The OPT4048 operates as a target device on both the I²C bus and SMBus. Connections to the bus are made via

the SCL clock input line and the SDA open-drain I/O line. The device supports the transmission protocol for

standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up to 2.6 MHz). All data bytes

are transmitted most-significant bits first.

The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects

of input spikes and bus noise. See the 节9.2.1 for further details of the I²C bus noise immunity.

8.3.4.7.2 Writing and Reading

Accessing a specific register on the OPT4048 is accomplished by writing the appropriate register address during

the I²C transaction sequence. Refer to 节 8.4 for a complete list of registers and their corresponding register

addresses. The value for the register address (as shown in 节 8.4) is the first byte transferred after the target

address byte with the R/W bit low.

1

9

1

9

SCL

SDA

RA RA RA RA RA RA RA RA

A0

A1

1

0

1

R/W

7

6

5

4

3

2

1

0

Stop by

Controller

(optional)

Start by

Controller

ACK by

Device

ACK by

Device

Frame 1: Two-Wire Device Address Byte ⁽¹⁾

Frame 2: Register Address Byte

图8-3. Setting the I²C Register Address

Writing to a register begins with the first byte transmitted by the controller. This byte is the target address with

the R/W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the

controller is the address of the register that data are to be written to. The next two bytes are written to the

register addressed by the register address. The device acknowledges receipt of each data byte. The controller

can terminate the data transfer by generating a start or stop condition.

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When reading from the device, the last value stored in the register address by a write operation determines

which register is read during a read operation. To change the register address for a read operation, a new partial

I²C write transaction must be initiated. This partial write is accomplished by issuing a target address byte with

the R/W bit low, followed by the register address byte and a stop command. The controller then generates a start

condition and sends the target address byte with the R/W bit high to initiate the read command. The next byte is

transmitted by the target and is the most significant byte of the register indicated by the register address. This

byte is followed by an acknowledge from the controller; then the target transmits the least significant byte. The

controller acknowledges receipt of the data byte. The controller can terminate the data transfer by generating a

not-acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from

the same register are desired, continually sending the register address bytes is not necessary; the device retains

the register address until that number is changed by the next write operation.

图 8-4and 图 8-5show the write and read operation timing diagrams, respectively. Note that register bytes are

sent most significant byte first, followed by the least significant byte.

1

9

1

9

1

9

1

9

SCL

SDA

RA RA RA RA RA RA RA RA

A0

A1

1

0

1

R/W

D15 D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

7

6

5

4

3

2

1

0

Start by

Controller

ACK by

Device

ACK by

Device

ACK by

Device

Stop by

Controller

ACK by

Device

Frame 1 Two-Wire Device Address Byte ⁽¹⁾

Frame 2 Register Address Byte

Frame 3 Data MSByte

Frame 4 Data LSByte

图8-4. I²C Write Example

1

9

1

9

1

9

SCL

SDA

A1

A0

R/W

1

0

1

D15 D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

No ACK

by

Controller(2)

Stop by

Controller

Start by

Controller

ACK by

Device

From

Device

ACK by

Controller

From Device

Frame 1 Two-Wire Device Address Byte ⁽¹⁾

Frame 2 Data MSByte

Frame 3 Data LSByte

A. An ACK by the controller can also be sent.

图8-5. I²C Read Example

8.3.4.7.2.1 High-Speed I²C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors or active pullup devices.

The controller generates a start condition followed by a valid serial byte containing the high-speed (HS)

controller code 0000 1XXXb. This transmission is made in either standard mode or fast mode (up to 400 kHz).

The device does not acknowledge the HS controller code but does recognize the code and switches the internal

filters to support a 2.6-MHz operation.

The controller then generates a repeated start condition (a repeated start condition has the same timing as the

start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 2.6 MHz are allowed. Instead of using a stop condition, use repeated start conditions

to secure the bus in HS mode. A stop condition ends the HS mode and switches all internal filters of the device

to support the F/S mode.

8.3.4.7.2.2 Burst Read Mode

OPT4048 supports I²C burst read mode which helps in minimizing the number of transactions on the bus for

efficient data transfer from the device to the controller.

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Before considering the burst mode, a regular I²C read transaction involves an I²C write operation to the device

read pointer, followed by the actual I²C read operation. With the output registers in continuous locations, writing

the register pointer every 2 bytes takes up several clock cycles. With the burst mode enabled, the read pointer

address is auto incremented after every register read (2 bytes), eliminating the need write operations to set the

pointer for subsequent register reads.

Burst mode can be enabled by setting the register I2C_BURST. When a STOP command is issued the pointer

resets to the original register address before the auto-increments.

Register Write Operation

Register

Address

data[15:8]

Target Address

data[7:0]

W

Register Read Operation

Register

Address

Target Address

data[15:8]

data[7:0]

R

Target Address

W

pointer set

Register Address

Register

Address

Target Address

data[15:8]

Target Address W

Register Address+2

data[15:8]

Register Address+1

Start

data[15:8]

data[7:0]

Stop

Register Address+4

data[15:8]

data[7:0]

Register Address+3

data[15:8]

Pointer reset to

Register Address

data[7:0]

pointer auto increments by 1 every 2 bytes

图8-6. I²C Operations

8.3.4.7.2.3 General-Call Reset Command

The I²C general-call reset allows the host controller in one command to reset all devices on the bus that respond

to the general-call reset command. The general call is initiated by writing to the I²C address 0 (0000 0000b). The

reset command is initiated when the subsequent second address byte is 06h (0000 0110b). With this transaction,

the device issues an acknowledge bit and sets all registers to the power-on-reset default condition.

8.3.4.7.2.4 SMBus Alert Response

The SMBus alert response provides a quick identification for which device issued the interrupt. Without this alert

response capability, the processor does not know which device pulled the interrupt line when there are multiple

target devices connected.

OPT4048 is designed to respond to the SMBus alert response address, when in the latched window-style

comparison mode. The OPT4048 does not respond to the SMBus alert response when in transparent mode.

The response behavior of the device to the SMBus alert response is shown in 图 8-7. When the interrupt line to

the processor is pulled to active, the controller can broadcast the alert response target address. Following this

alert response, any target devices that generated an alert identify themselves by acknowledging the alert

response and sending respective I²C address on the bus. The alert response can activate several different

target devices simultaneously. If more than one target attempts to respond, bus arbitration rules apply. The

device with the lowest address wins the arbitration. If the OPT4048 loses the arbitration, the device does not

acknowledge the I²C transaction and the INT pin remains in an active state, prompting the I²C controller

processor to issue a subsequent SMBus alert response. When the OPT4048 wins the arbitration, the device

acknowledges the transaction and sets the INT pin to inactive. The controller can issue that same command

again, as many times as necessary to clear the INT pin. See 节8.3.4.2 for additional details of how the flags and

INT pin are controlled. The controller can obtain information about the source of the OPT4048 interrupt from the

address broadcast in the above process. The FLAG_H value is sent as the final LSB of the address to provide

the controller additional information about the cause of the OPT4048 interrupt. If the controller requires

additional information, the result register or the configuration register can be queried. The FLAG_Hand FLAG_L

registers are not cleared upon an SMBus alert response.

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INT

1

9

1

9

SCL

SDA

FH⁽¹⁾

0

1

0

R/ W

1

0

1

A1

A0

Start By

ACK By

Device

From

Device

NACK By

Controller

Stop By

Controller

Frame 2 Target Address Byte⁽²⁾

Frame 1 SMBus ALERT Response Address Byte

A. FH is the FLAG_H register

B. A1 and A0 are determined by the ADDR pin

图8-7. Timing Diagram for SMBus Alert Response

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8.4.1 ALL Register Map

8.4.1.1 Register 0h (offset = 0h) [reset = 0h]

图8-9. Register 0h

15

7

14

EXPONENT_CH0

R-0h

13

12

11

10

9

8

0

RESULT_MSB_CH0

R-0h

6

5

4

3

2

1

RESULT_MSB_CH0

R-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-10. Register 00 Field Descriptions

Bit

Field

Type

Reset

Description

EXPONENT output CH0. Determines the full-scale range of

the light measurement for the channel.

15-12

EXPONENT_CH0

R

0h

Result register MSB (Most significant bits) CH0. Used to

calculate the MANTISSA representing light level within a

given EXPONENT or full-scale range

RESULT_MSB_C

H0

11-0

R

0h

8.4.1.2 Register 1h (offset = 1h) [reset = 0h]

图8-11. Register 1h

15

14

13

12

11

10

2

9

1

8

0

RESULT_LSB_CH0

R-0h

7

6

5

4

3

COUNTER_CH0

R-0h

CRC_CH0

R-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-12. Register 01 Field Descriptions

Bit

Field

Type

Reset

Description

Result register LSB(Least significant bits) CH0. Used to

calculate MANTISSA representing light level within a given

EXPONENT or full-scale range

RESULT_LSB_C

H0

15-8

R

0h

Sample counter CH0. Rolling counter which increments for

every conversion

7-4

3-0

COUNTER_CH0

CRC_CH0

R

0h

CRC bits CH0.

R[19:0]=(RESULT_MSB_CH0[11:0]<<8)+RESULT_LSB_C

H0[7:0]

X[0]=XOR(EXPONENT_CH0[3:0],R[19:0],CRC_CH0[3:0])

XOR of all bits

X[1]=XOR(CRC_CH0[1],CRC_CH0[3],R[1],R[3],R[5],R[7],

R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])

X[2]=XOR(CRC_CH0[3],R[3],R[7],R[11],R[15],R[19],E[3])

X[3]=XOR(R[3],R[11],R[19])

8.4.1.3 Register 2h (offset = 2h) [reset = 0h]

图8-13. Register 2h

15

14

13

12

11

10

9

8

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图8-13. Register 2h (continued)

EXPONENT_CH1

R-0h

RESULT_MSB_CH1

R-0h

7

6

5

4

3

2

1

0

RESULT_MSB_CH1

R-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-14. Register 02 Field Descriptions

Bit

Field

Type

Reset

Description

EXPONENT output CH1. Determines the full-scale range of

the light measurement for the channel.

15-12

EXPONENT_CH1

R

0h

Result register MSB (Most significant bits) CH1. Used to

calculate the MANTISSA representing light level within a

given EXPONENT or full-scale range

RESULT_MSB_C

H1

11-0

R

0h

8.4.1.4 Register 3h (offset = 3h) [reset = 0h]

图8-15. Register 3h

15

14

13

12

11

10

2

9

1

8

0

RESULT_LSB_CH1

R-0h

7

6

5

4

3

COUNTER_CH1

R-0h

CRC_CH1

R-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-16. Register 03 Field Descriptions

Bit

Field

Type

Reset

Description

Result register LSB(Least significant bits) CH1. Used to

calculate MANTISSA representing light level within a given

EXPONENT or full-scale range

RESULT_LSB_C

H1

15-8

R

0h

Sample counter CH1. Rolling counter which increments for

every conversion

7-4

3-0

COUNTER_CH1

CRC_CH1

R

0h

CRC bits CH1.

R[19:0]=(RESULT_MSB_CH1[11:0]

<<8)+RESULT_LSB_CH1[7:0]

X[0]=XOR(EXPONENT_CH1[3:0],R[19:0],CRC_CH1[3:0])

XOR of all bits

X[1]=XOR(CRC_CH1[1],CRC_CH1[3],R[1],R[3],R[5],R[7],

R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])

X[2]=XOR(CRC_CH1[3],R[3],R[7],R[11],R[15],R[19],E[3])

X[3]=XOR(R[3],R[11],R[19])

8.4.1.5 Register 4h (offset = 4h) [reset = 0h]

图8-17. Register 4h

15

14

EXPONENT_CH2

R-0h

13

12

11

10

9

8

0

RESULT_MSB_CH2

R-0h

7

6

5

4

3

2

1

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图8-17. Register 4h (continued)

RESULT_MSB_CH2

R-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-18. Register 04 Field Descriptions

Bit

Field

Type

Reset

Description

EXPONENT output CH2. Determines the full-scale range of

the light measurement for the channel.

15-12

EXPONENT_CH2

R

0h

Result register MSB (Most significant bits) CH2. Used to

calculate the MANTISSA representing light level within a

given EXPONENT or full-scale range

RESULT_MSB_C

H2

11-0

R

0h

8.4.1.6 Register 5h (offset = 5h) [reset = 0h]

图8-19. Register 5h

15

14

13

12

11

10

2

9

1

8

0

RESULT_LSB_CH2

R-0h

7

6

5

4

3

COUNTER_CH2

R-0h

CRC_CH2

R-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-20. Register 05 Field Descriptions

Bit

Field

Type

Reset

Description

Result register LSB(Least significant bits) CH2. Used to

calculate MANTISSA representing light level within a given

EXPONENT or full-scale range

RESULT_LSB_C

H2

15-8

R

0h

Sample counter CH2. Rolling counter which increments for

every conversion

7-4

3-0

COUNTER_CH2

CRC_CH2

R

0h

CRC bits CH2.

R[19:0]=(RESULT_MSB_CH2[11:0]<<8)+RESULT_LSB_C

H2[7:0]

X[0]=XOR(EXPONENT_CH2[3:0],R[19:0],CRC_CH2[3:0])

XOR of all bits

X[1]=XOR(CRC_CH2[1],CRC_CH2[3],R[1],R[3],R[5],R[7],

R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])

X[2]=XOR(CRC_CH2[3],R[3],R[7],R[11],R[15],R[19],E[3])

X[3]=XOR(R[3],R[11],R[19])

8.4.1.7 Register 6h (offset = 6h) [reset = 0h]

图8-21. Register 6h

15

14

EXPONENT_CH3

R-0h

13

12

11

10

9

8

0

RESULT_MSB_CH3

R-0h

7

6

5

4

3

2

1

RESULT_MSB_CH3

R-0h

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LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-22. Register 06 Field Descriptions

Bit

Field

Type

Reset

Description

EXPONENT output CH3. Determines the full-scale range of

the light measurement for the channel.

15-12

EXPONENT_CH3

R

0h

Result register MSB (Most significant bits) CH3. Used to

calculate the MANTISSA representing light level within a

given EXPONENT or full-scale range

RESULT_MSB_C

H3

11-0

R

0h

8.4.1.8 Register 7h (offset = 7h) [reset = 0h]

图8-23. Register 7h

15

14

13

12

11

10

2

9

1

8

0

RESULT_LSB_CH3

R-0h

7

6

5

4

3

COUNTER_CH3

R-0h

CRC_CH3

R-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-24. Register 07 Field Descriptions

Bit

Field

Type

Reset

Description

Result register LSB(Least significant bits) CH3. Used to

calculate MANTISSA representing light level within a given

EXPONENT or full-scale range

RESULT_LSB_C

H3

15-8

R

0h

Sample counter CH3. Rolling counter which increments for

every conversion

7-4

3-0

COUNTER_CH3

CRC_CH3

R

0h

CRC bits CH3.

R[19:0]=(RESULT_MSB_CH3[11:0]<<8)+RESULT_LSB_C

H3[7:0]

X[0]=XOR(EXPONENT_CH3[3:0],R[19:0],CRC_CH3[3:0])

XOR of all bits

X[1]=XOR(CRC_CH3[1],CRC_CH3[3],R[1],R[3],R[5],R[7],

R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])

X[2]=XOR(CRC_CH3[3],R[3],R[7],R[11],R[15],R[19],E[3])

X[3]=XOR(R[3],R[11],R[19])

8.4.1.9 Register 8h (offset = 8h) [reset = 0h]

图8-25. Register 8h

15

14

13

12

11

10

9

8

0

THRESHOLD_L_EXPONENT

R/W-0h

THRESHOLD_L_RESULT

R/W-0h

7

6

5

4

3

2

1

THRESHOLD_L_RESULT

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

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图8-26. Register 08 Field Descriptions

Bit

Field

Type

Reset

Description

THRESHOLD_L_

EXPONENT

15-12

R/W

0h

Threshold low register exponent

THRESHOLD_L_

RESULT

11-0

R/W

0h

Threshold low register result

8.4.1.10 Register 9h (offset = 9h) [reset = BFFFh]

图8-27. Register 9h

15

14

13

12

11

10

9

8

0

THRESHOLD_H_EXPONENT

R/W-Bh

THRESHOLD_H_RESULT

R/W-Fh

7

6

5

4

3

2

1

THRESHOLD_H_RESULT

R/W-FFh

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-28. Register 09 Field Descriptions

Bit

Field

Type

Reset

Description

THRESHOLD_H_

EXPONENT

15-12

R/W

Bh

Threshold high register exponent

Threshold high register result

THRESHOLD_H_

RESULT

11-0

R/W

FFFh

8.4.1.11 Register Ah (offset = Ah) [reset = 3208h]

图8-29. Register Ah

15

14

13

12

11

10

9

8

QWAKE

R/W-0h

0

RANGE

R/W-Ch

CONVERSION_TIME

R/W-2h

W-0h

7

6

5

4

3

2

1

0

CONVERSION_TIME

R/W-0h

OPERATING_MODE

R/W-0h

LATCH

R/W-1h

INT_POL

R/W-0h

FAULT_COUNT

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-30. Register 0A Field Descriptions

Bit

Field

QWAKE

0

Type

R/W

W

Reset

Description

Quick Wake-up from Standby in one shot mode by not

powering down all circuits. Applicable only in One-shot

mode and helps get out of standby mode faster with penalty

in power consumption compared to full standby mode.

15-15

14-14

0h

Must read or write 0

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图8-30. Register 0A Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Controls the full-scale light level range of the device. The

format of this register is same as the EXPONENT register

for all values from 0 to 6.

0 : 2.2klux

1 : 4.5kux

13-10

RANGE

R/W

Ch

2 : 9klux

3 : 18klux

4 : 36klux

5 : 72klux

6 : 144klux

12 : Auto-Range

Controls the device conversion time per channel

0 : 600 us

1 : 1 ms

2 : 1.8 ms

3 : 3.4 ms

4 : 6.5 ms

5 : 12.7 ms

6 : 25 ms

7 : 50 ms

8 : 100 ms

9 : 200 ms

10 : 400 ms

11 : 800 ms

CONVERSION_TI

ME

9-6

R/W

8h

Controls device mode of operation

0 : Power-down

1 : Forced auto-range OneShot

2 : OneShot

OPERATING_MO

DE

5-4

R/W

0h

3 : Continuous

Controls the functionality of the interrupt reporting

mechanisms for INT pin for the threshold detection logic.

3-3

2-2

LATCH

R/W

1h

0h

Controls the polarity or active state of the INT pin.

0 : Active Low

INT_POL

1 : Active High

Fault count register instructs the device as to how many

consecutive fault events are required to trigger the

threshold mechanisms: the flag high (FLAG_H) and the flag

low (FLAG_L) registers.

1-0

FAULT_COUNT

R/W

0h

0 : One fault Count

1 : Two Fault Counts

2 : Four Fault Counts

3 : Eight Fault Counts

8.4.1.12 Register Bh (offset = Bh) [reset = 8011h]

图8-31. Register Bh

15

14

13

12

11

10

0

9

0

8

0

1

0

R/W-1h

R/W-0h

W-0h

R/W-0h

7

0

6

5

4

3

2

1

0

THRESHOLD_CH_SEL

R/W-0h

INT_DIR

R/W-1h

INT_CFG

R/W-0h

I2C_BURST

R/W-1h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-32. Register 0B Field Descriptions

Bit

Field

Type

Reset

Description

15-7

128

R/W

80h

Must read or write 128

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图8-32. Register 0B Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Channel select for threshold logic

0 : CH0 Selected

1 : CH1 Selected

THRESHOLD_CH

_SEL

6-5

R/W

0h

2 : CH2 Selected

3 : CH3 Selected

Determines the direction of the INT pin.

4-4

3-2

INT_DIR

INT_CFG

R/W

1h

0h

0 : Input

1 : Output

Controls the output interrupt mechanism after end of

conversion

0 : SMBUS Alert

1 : INT Pin data ready for next channel

3 : INT Pin data ready for all channels

1-1

0-0

0

R/W

0h

1h

Must read or write 0

When set enables I2C burst mode minimizing I2C read

cycles by auto incrementing read register point by 1 after

every register read

I2C_BURST

8.4.1.13 Register Ch (offset = Ch) [reset = 0h]

图8-33. Register Ch

15

14

13

12

11

10

0

9

0

8

0

R/W-0h

7

0

6

0

5

0

4

0

3

2

1

0

OVERLOAD_F CONVERSION

FLAG_H

FLAG_L

LAG

_READY_FLAG

R/W-0h

R-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-34. Register 0C Field Descriptions

Bit

Field

Type

Reset

Description

15-4

0

R/W

0h

Must read or write 0

Indicates when an overflow condition occurs in the data

conversion process, typically because the light illuminating

the device exceeds the full-scale range.

OVERLOAD_FLA

G

3-3

2-2

R

0h

Conversion ready flag indicates when a conversion

completes. The flag is set to 1 at the end of a conversion

and is cleared (set to 0) when register address 0xA is either

read or written with any non-zero value

CONVERSION_R

EADY_FLAG

0 : Conversion in progress

1 : Conversion is complete

Flag high register identifies that the result of a conversion is

measurement than a specified level of interest. FLAG_H is

set to 1 when the result is larger than the level in the

THRESHOLD_H_EXPONENT and

1-1

FLAG_H

R

0h

THRESHOLD_H_RESULT registers for a consecutive

number of measurements defined by the FAULT_COUNT

register.

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图8-34. Register 0C Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Flag low register identifies that the result of a measurement

is smaller than a specified level of interest. FLAG_L is set

to 1 when the result is smaller than the level in the

THRESHOLD_L_EXPONENT and

0-0

FLAG_L

R

0h

THRESHOLD_L_RESULT registers for a consecutive

number of measurements defined by the FAULT_COUNT

register.

8.4.1.14 Register 11h (offset = 11h) [reset = 820h]

图8-35. Register 11h

15

14

13

12

11

10

2

9

1

8

0

DIDL

R-0h

DIDH

R-8h

R/W-0h

7

6

5

4

3

DIDH

R-21h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

图8-36. Register 11 Field Descriptions

Bit

Field

0

Type

R/W

R

Reset

Description

15-14

13-12

11-0

0h

Must read or write 0

Device ID L

DIDL

DIDH

8h

R

21h

Device ID H

32

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

Color sensors are used in a wide variety of applications that require precise measurement of light as perceived

by human eye, since the color sensors have a specialized filter that mimic human eye. The following sections

shows crucial information about integrating OPT4048 in applications.

There are two categories of interface to the OPT4048: electrical and optical.

9.2 Typical Application

9.2.1 Electrical Interface

The electrical interface is quite simple, as illustrated in 图 9-1below. Connect the OPT4048 I²C SDA and SCL

pins to the same pins of an applications processor, micro controller, or other digital processor. If that digital

processor requires an interrupt resulting from an event of interest from theOPT4048, then connect the INT pin to

either an interrupt or general-purpose I/O pin of the processor. There are multiple uses for this INT pin, including

triggering a measurement on one-shot mode, signaling the system to wake up from low-power mode, processing

other tasks while waiting for an ambient light event of interest, or alerting the processor that a sample is ready to

be read. Connect pullup resistors between a power supply appropriate for digital communication and the SDA

and SCL pins (because the pins have open-drain output structures). If the INT pin is used, connect a pullup

resistor to the INT pin. A typical value for these pullup resistors is 10 kΩ. The resistor choice can be optimized in

conjunction to the bus capacitance to balance the system speed, power, noise immunity, and other

requirements.

Short or Open

VIO: 1.6V to 5V

0.1uF

10k

VDD:1.6V to 3.6V

VDD

Ambient

Light

VIO

OPT4048_SDA

SDA

SCL

GPIO/TimerPin

INT

ADDR

Controller

GND

Micro Controller or Processor

GND

图9-1. Typical Application Schematic

The power supply and grounding considerations are discussed in the 节9.4.

Although spike suppression is integrated in the SDA and SCL pin circuits, use proper layout practices to

minimize the amount of coupling into the communication lines. One possible introduction of noise occurs from

capacitively coupling signal edges between the two communication lines themselves. Another possible noise

introduction comes from other switching noise sources present in the system, especially for long communication

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lines. In noisy environments, shield communication lines to reduce the possibility of unintended noise coupling

into the digital I/O lines that can be incorrectly interpreted.

9.2.2 Design Requirements

9.2.2.1 Optical Interface

1

8

A

0.39

Section A

图9-2. Sensor Position

Any physical component that affects the light which illuminates the sensing area of a light sensor also affects the

performance of that light sensor. Therefore, for the best performance, make sure to understand and control the

effect of these components. Design a window width and height to permit light from a sufficient field of view to

illuminate the sensor. For best performance, use a field of view of at least ±35°, or preferably ±45° or more.

Understanding and designing the field of view is discussed further in application report OPT3001: Ambient Light

Sensor Application Guide (SBEA002)..

9.2.3 Detailed Design Procedure

9.2.3.1 Optomechanical Design

After completing the electrical design, the next task is the optomechanical design. Window sizing and placement

is discussed in more rigorous detail in OPT3001: Ambient Light Sensor Application Guide.

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9.2.4 Application Curves

Matrix values for Color determination

ADC measurements from OPT4048 channels can be used to determine the intensity (lux) and the color (CIE X,Y

coordinates) as per specified in 节 8.3.4.5. Here is an example of such measurements performed an RGB LED

source TI LP5036EVM. The intensity of the Red, Green and Blue LEDs were varied independently and the

corresponding color coordinates detected by OPT4048 (CIEx,CIEy) are plotted on the CIE XY and CIE UV color

space.

图9-3. CIE XY and CIE UV space plots of color coordinates

Value of matrix used for this calculation is as shown below

2 . 34892992e − 04 −1.89652390e − 05 1.20811684e − 05

0

4.07467441e − 05 1.98958202e − 04 − 1.58848115e − 05 2.15e − 3

(16)

9.28619404e − 05 −1.69739553e − 05 6.74021520e − 04

0

Correlated Color Temperature

The CIE XY and CIE UV color spaces shown in 图 9-3 and 图 9-4 has been annotated with the ideal black body

curve and intersecting iso-thermal lines. The ideal black body curve represents the color perceived by human

eye in CIE YX and CIE UV spaces when an ideal black body of certain Kelvins emit radiation. The intersecting

lines with various kelvin markings are iso-thermal lines which represent the same color temperature and is

commonly referred to as Correlated Color Temperature (CCT). CCT is a representation of how warm or cool a

color source is which is a common terminology used in classifying light bulbs. CCT is often valid only around the

ideal black body curve and does not make sense when there is too much deviation. Any color coordinate close

to the ideal black body curve can be represented as having a particular CCT by using the formula below:

3

2

CCT = 437n + 3601n + 6861n + 5517

(17)

where n is defined as

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CIEx − 0.3320

n =

(18)

0.1858 − CIEy

These are highly non-linear functions and the estimation of the CCT is very sensitive to the CIE X and CIE Y

coordinates. Small errors due to non-ideality in the system can cause an amplified error in CCT estimation.

Set of off the shelf lamp sources were taken and the CCT values measured by OPT4048 is shown below.

图9-4. CIE XY and CIE UV Space Plots of Color Coordinates

The CIE color space plots have been zoomed-in to see the points more clearly. The annotation in the plot specify

the color temperature of the lamps as specified by the manufacturer. While the lamp manufacturers approximate

the CCT in Kelvins to nearest 1000 s, 500 s or 100 s, OPT4048 estimates the CCT high resolution using the

equations specified above.

Color accuracy and the CCT accuracy can be further optimized based on the cavity design, cover glass and

target application. More information is available at OPT4048.

9.3 Do's and Don'ts

As with any optical product, take special care when handling the OPT4048. The device is a piece of active

silicon, without the mechanical protection of an epoxy-like package or other reinforcement. This design allows

the device to be as thin as possible. Take extra care to handle the device gently to not crack or break the device.

Use a properly-sized vacuum manipulation tool to handle the device.

The optical surface of the device must be kept clean for best performance, both when prototyping with the

device, and during mass production manufacturing procedures. Keep the optical surface clean of fingerprints,

dust, and other optical-inhibiting contaminants.

If the optical surface of the device requires cleaning, use a few gentle brushes with a soft swab of deionized

water or isopropyl alcohol. Avoid potentially abrasive cleaning and manipulating tools and excessive force that

can scratch the optical surface.

If the OPT4048 performs less than optimally, then inspect the optical surface for dirt, scratches, or other optical

artifacts.

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9.4 Power Supply Recommendations

Although the OPT4048 has low sensitivity to power-supply noise, good practices are always recommended. For

best performance, the OPT4048 VDD pin must have a stable, low-noise power supply with a 100-nF bypass

capacitor close to the device and solid grounding. There are many options for powering the OPT4048 because

of the device low current consumption levels.

9.5 Layout

9.5.1 Layout Guidelines

The PCB layout design for the OPT4048 requires a couple of considerations. Bypass the power supply with a

capacitor placed close to the device. Note that optically reflective surfaces of components also affect the

performance of the design. The three-dimensional geometry of all components and structures around the sensor

must be taken into consideration to prevent unexpected results from secondary optical reflections. Placing

capacitors and components at a distance of at least twice the height of the component is usually sufficient. The

best optical layout is to place all close components on the opposite side of the PCB from the device. However,

this approach is not practical for the constraints of every design.

An example PCB layout with the OPT4048 is shown in 图9-5.

9.5.2 Layout Example

OPT4048

To VDD Power Supply

To Processor

Bypass Capacitor

图9-5. Example PCB Layout with the OPT4048 SOT-5X3 (8) Package

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9.5.3 Soldering and Handling Recommendations

Soldering temperature profile and guidelines are published in future revisions of this document.

As with most optical devices, handle the OPT4048 with special care to ensure optical surfaces stay clean and

free from damage. See 节 9.3 for more detailed recommendations. For best optical performance, solder flux and

any other possible debris must be cleaned after soldering processes.

备注

The bottom side of the device features an angled feature to denote the PIN 1

图9-6. Identification Feature for PIN 1

图9-7. Identification Features for PIN 1 on Package

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

• OPT4048EVM User's Guide

• OPT3001: Ambient Light Sensor Application Guide

10.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

FCSOT - 0.6 mm max height

FLIPCHIP SOT

DTS0008A

1.3

1.1

B

A

PIN 1

INDEX AREA

1

8

7

6X (0.5)

2

3

2.2

2.0

6

5

4

0.27

8X

0.17

0.1

C A B

C

2.0

1.8

0.05

SEATING PLANE

0.18

0.08

C

0.6 MAX

0.45

8X

0.05

0.00

0.25

4

5

6

7

8

3

2

1

0.05 C

4226132/B 07/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not incude mold flash, protrusions or gate burrs.

Mold flash, interlead flash, protrusions or gate burrs shall not exceed 0.15 per end or side

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EXAMPLE BOARD LAYOUT

FCSOT - 0.6 mm max height

FLIPCHIP SOT

DTS0008A

(1.72)

8X (0.72)

8X (0.3)

1

8

7

6

2

3

SYMM

6X (0.5)

5

4

SYMM

(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 30X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226132/B 07/2021

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

FCSOT - 0.6 mm max height

FLIPCHIP SOT

DTS0008A

(1.72)

8X (0.72)

1

8

7

8X (0.3)

2

3

SYMM

6

5

6X (0.5)

4

SYMM

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 30X

4226132/B 07/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	OPT4048DTST
厂家：	TEXAS INSTRUMENTS
描述：	高速高精度三色 XYZ 颜色传感器 \| DTS \| 8 \| -40 to 85 传感器
文件：	总45页 (文件大小：1897K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

OPT4048DTST [TI]

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