PAM1707BZKBD3 [TI]
AM1705 ARM Microprocessor; AM1705 ARM微处理器
| 型号： | PAM1707BZKBD3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AM1705 ARM Microprocessor |
| 文件： | 总155页 (文件大小：999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AM1705
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AM1705 ARM Microprocessor
Check for Samples: AM1705
1 AM1705 ARM Microprocessor
1.1 Features
123
– 32 Independent DMA Channels
• Highlights
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• 128K-Byte RAM Memory
– 375/456-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Programmable Real-Time Unit Subsystem
• 3.3V LVCMOS IOs (except for USB interface)
• Two External Memory Interfaces:
– EMIFA
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
•
•
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
– EMIFB
16-Bit SDRAM With 256MB Address
Space
•
– Two Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– Two Multichannel Audio Serial Ports
– 10/100 Mb/s Ethernet MAC (EMAC)
– One 64-Bit General-Purpose Timer
– One 64-bit General-Purpose/Watchdog Timer
– Three Enhanced Pulse Width Modulators
– Three 32-Bit Enhanced Capture Modules
• Applications
• Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
• Two Serial Peripheral Interfaces (SPI) Each
With One Chip-Select
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Realtime
Unit (PRU) Cores
– Industrial Automation
– Home Automation
– Test and Measurement
– Portable Data Terminals
– Educational Consoles
– Power Protection Systems
•
•
•
•
32-Bit Load/Store RISC architecture
4K Byte instruction RAM per core
512 Bytes data RAM per core
PRU Subsystem (PRUSS) can be disabled
via software to save power
– Standard power management mechanism
• 375/456-MHz ARM926EJ-S™ RISC Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– Single Cycle MAC
•
•
Clock gating
Entire subsystem under a single PSC
clock gating domain
– ARM® Jazelle® Technology
– Dedicated interrupt controller
– Dedicated switched central resource
• Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
• Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Transfer Controllers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited.
ARM, Jazelle are registered trademarks of ARM Limited.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright © 2010, Texas Instruments Incorporated
AM1705
SPRS657A–FEBRUARY 2010–REVISED APRIL 2010
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– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) Rx and Tx
– 6 Single Edge, 6 Dual Edge Symmetric or 3
Dual Edge Asymmetric Outputs
• Two Multichannel Audio Serial Ports:
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– FIFO buffers for Transmit and Receive
• 10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
• One 64-Bit General-Purpose Timer
(Configurable as Two 32-Bit Timers)
• One 64-bit General-Purpose/Watchdog Timer
(Configurable as Two 32-bit General-Purpose
Timers)
• Three Enhanced Pulse Width Modulators
(eHRPWM):
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
• Three 32-Bit Enhanced Capture Modules
(eCAP):
– Configurable as 3 Capture Inputs or 3
Auxiliary Pulse Width Modulator (APWM)
outputs
– Single Shot Capture of up to Four Event
Time-Stamps
• Two 32-Bit Enhanced Quadrature Encoder
Pulse Modules (eQEP)
• 176-pin PowerPADTM Plastic Quad Flat Pack
[PTP suffix], 0.5-mm Pin Pitch
• Commercial, Industrial, or Extended
Temperature
• Community Resources
– TI E2E Community
– Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control
– TI Embedded Processors Wiki
2
AM1705 ARM Microprocessor
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1.2 Trademarks
All trademarks are the property of their respective owners.
Copyright © 2010, Texas Instruments Incorporated
AM1705 ARM Microprocessor
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1.3 Description
The device is a low-power ARM microprocessor based on an ARM926EJ-S™.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and
16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core
also has a 8KB RAM (Vector Table) and 64KB ROM.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP)
with serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as
watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS
and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced
capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width
modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external
memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower
memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is
available for PHY configuration.
TheI2C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate
with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The device has a complete set of development tools for the ARM. These include C compilers and a
Windows™ debugger interface for visibility into source code execution.
4
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1.4 Functional Block Diagram
ARM Subsystem
JTAG Interface
System Control
ARM926EJ-S CPU
With MMU
PLL/Clock
Generator
w/OSC
Input
Clock(s)
4 KB ETB
General-
Purpose
Timer
16 KB
I-Cache
16 KB
D-Cache
Power/Sleep
Controller
General-
Purpose
Timer
8 KB RAM
(Vector Table)
Pin
Multiplexing
64 KB ROM
(Watchdog)
Switched Central Resource (SCR)
Peripherals
DMA
Customizable Interface
Shared Memory
Audio Ports
Serial Interfaces
McASP
w/FIFO
(2)
2
SPI
(2)
UART
(3)
I C
(2)
EDMA3
GPIO
PRU
Subsystem
128 KB
RAM
Connectivity
External Memory Interfaces
Control Timers
(10/100)
EMAC
(RMII)
EMIFA
NAND/ Flash
(8b)
EMIFB
SDRAM Only
(16b/32b)
USB2.0
OTG Ctlr
PHY
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
MMC/SD
(8b)
MDIO
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AM1705 ARM Microprocessor
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1
AM1705 ARM Microprocessor ........................ 1
1.1 Features .............................................. 1
1.2 Trademarks .......................................... 3
1.3 Description ........................................... 4
1.4 Functional Block Diagram ............................ 5
Revision History ......................................... 7
Device Overview ........................................ 8
3.1 Device Characteristics ............................... 8
3.2 Device Compatibility ................................. 9
3.3 ARM Subsystem ..................................... 9
3.4 Memory Map Summary ............................. 12
3.5 Pin Assignments .................................... 15
3.6 Terminal Functions ................................. 16
Device Configuration ................................. 29
6.7 Clock PLLs ......................................... 43
6.8 Interrupts ............................................ 46
6.9 General-Purpose Input/Output (GPIO) ............. 50
6.10 EDMA ............................................... 53
6.11 External Memory Interface A (EMIFA) ............. 58
6.12 External Memory Interface B (EMIFB) ............. 65
6.13 Memory Protection Units ........................... 71
6.14 MMC / SD / SDIO (MMCSD) ....................... 74
6.15 Ethernet Media Access Controller (EMAC) ......... 77
6.16 Management Data Input/Output (MDIO) ........... 82
6.17 Multichannel Audio Serial Ports (McASP0,
McASP1) ............................................ 84
6.18 Serial Peripheral Interface Ports (SPI0, SPI1) ..... 93
2
3
6.19 Enhanced Capture (eCAP) Peripheral ............ 111
6.20 Enhanced Quadrature Encoder (eQEP) Peripheral
4
5
..................................................... 114
6.21 Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM) ........................................ 116
4.1 Boot Modes ......................................... 29
4.2 SYSCFG Module ................................... 29
4.3 Pullup/Pulldown Resistors .......................... 31
6.22 Timers ............................................. 120
6.23
I.n.t.e.r.-.In..te..g.r.a.t.e.d..C..ir.c.u..it..S.e..ri.a.l.P..o.r.t.s..(.I2..C.0..,.I.2.C..1.)... 122
6.24 Universal Asynchronous Receiver/Transmitter
(UART) ............................................ 127
Device Operating Conditions ....................... 32
5.1
Absolute Maximum Ratings Over Operating
Junction Temperature Range
(Unless Otherwise Noted) ................................. 32
5.2 Recommended Operating Conditions .............. 33
6.25 USB0 OTG (USB2.0 OTG) ........................ 129
6.26 Power and Sleep Controller (PSC) ................ 137
6.27 Programmable Real-Time Unit Subsystem (PRUSS)
..................................................... 140
5.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Junction
Temperature (Unless Otherwise Noted) ............ 34
Peripheral Information and Electrical
6.28 Emulation Logic ................................... 143
6.29 IEEE 1149.1 JTAG ................................ 149
Device and Documentation Support ............. 151
6
Specifications .......................................... 35
6.1 Parameter Information .............................. 35
7
8
6.2
Recommended Clock and Control Signal Transition
7.1 Device Support .................................... 151
7.2 Documentation Support ........................... 151
Behavior ............................................ 36
6.3 Power Supplies ..................................... 37
Mechanical Packaging and Orderable
6.4
Unused USB0 (USB2.0) Pin Configurations ....... 37
Information ............................................ 152
6.5 Reset ............................................... 37
8.1
Device and Development-Support Tool
Nomenclature ..................................... 152
8.2 Mechanical Drawings ............................. 152
6.6
Crystal Oscillator or External Clock Input .......... 41
6
Contents
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2 Revision History
This data manual revision history highlights the changes made to the SPRS657 device-specific data
manual to make it an SPRS657A revision.
Table 2-1. Revision History
ADDITIONS/MODIFICATIONS/DELETIONS
Removed references to USB0_VDDA12 from Section 5.1.
Updated Device and Development-Support Tool Nomenclature - Section 8.1.
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Revision History
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3 Device Overview
3.1 Device Characteristics
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provides an overview of the device . The table shows significant features of the device, including the
capacity of on-chip RAM, peripherals, and the package type with pin count.
Table 3-1. Characteristics of the device
HARDWARE FEATURES
AM1705
EMIFB
EMIFA
16-bit , upto 512Mb SDRAM
Asynchronous (8/16-bit bus width) RAM, Flash, NOR, NAND
MMC and SD cards supported.
Flash Card Interface
EDMA3
32 independent channels, 8 QDMA channels, 2 Transfer controllers
2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as
Watch Dog)
Timers
UART
SPI
I2C
3 (one with RTS and CTS flow control)
2 (Each with one hardware chip select)
2 (both Master/Slave)
Multichannel Audio
Serial Port [McASP]
2(each with transmit/receive, FIFO buffer, 16/12/4 serializers)
10/100 Ethernet MAC
with Management Data
I/O
1 (RMII Interface)
Peripherals
eHRPWM
eCAP
6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
2 32-bit QEP channels with 4 inputs/channel
Not all peripherals pins
are available at the
same time (for more
detail, see the Device
Configurations section).
eQEP
USB 2.0 (USB0)
High-Speed OTG Controller with on-chip OTG PHY
General-Purpose
Input/Output Port
8 banks of 16-bit
PRU Subsystem
(PRUSS)
2 Programmable PRU Cores
168KB RAM, 1088KB ROM
Size (Bytes)
ARM
16KB I-Cache
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM
On-Chip Memory
Organization
ADDITIONAL MEMORY
128KB RAM
0x8B7D F02F (Silicon Revision 1.1)
0x9B7D F02F (Silicon Revision 2.0)
JTAG BSDL_ID
CPU Frequency
DEVIDR0 register
MHz
ARM926 375 MHz (1.2V) or 456 MHz (1.3V)
1.2 V nominal for 375 MHz version
1.3 V nominal for 456 MHz version
Core (V)
Voltage
I/O (V)
3.3 V
Package
24 mm x 24 mm, 176-Pin, 0.5 mm pitch, TQFP (PTP)
Product Preview (PP),
Advance Information
(AI),
Product Status(1)
AI
or Production Data
(PD)
(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
8
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3.2 Device Compatibility
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
3.3 ARM Subsystem
The ARM Subsystem includes the following features:
•
•
•
•
•
•
•
•
•
•
ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit) instruction set
Little endian
System Control Co-Processor 15 (CP15)
MMU
16KB Instruction cache
16KB Data cache
Write Buffer
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
ARM Interrupt controller
3.3.1 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
•
•
•
•
•
•
•
•
ARM926EJ -S integer core
CP15 system control coprocessor
Memory Management Unit (MMU)
Separate instruction and data caches
Write buffer
Separate instruction and data (internal RAM) interfaces
Separate instruction and data AHB bus interfaces
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
3.3.2 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers
are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as
supervisor or system mode.
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3.3.3 MMU
A single set of two level page tables stored in main memory is used to control the address translation,
permission checks and memory region attributes for both data and instruction accesses. The MMU uses a
single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The
MMU features are:
•
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
Mapping sizes are:
–
–
–
–
1MB (sections)
64KB (large pages)
4KB (small pages)
1KB (tiny pages)
•
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•
•
•
•
Hardware page table walks
Invalidate entire TLB, using CP15 register 8
Invalidate TLB entry, selected by MVA, using CP15 register 8
Lockdown of TLB entries, using CP15 register 10
3.3.4 Caches and Write Buffer
The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following
features:
•
•
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
•
•
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
3.3.5 Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926EJ-S Subsystem in the device also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
10
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•
•
Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The
ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace
data.
This device uses ETM9™ version r2p2 and ETB version r0p1. Documentation on the ETM and ETB is
available from ARM Ltd. Reference the ' CoreSight™ ETM9™ Technical Reference Manual, revision r0p1'
and the 'ETM9 Technical Reference Manual, revision r2p2'.
3.3.7 ARM Memory Mapping
By default the ARM has access to most on and off chip memory areas, EMIFA, EMIFB, and the additional
128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by
default.
See for a detailed top level device memory map that includes the ARM memory space.
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3.4 Memory Map Summary
Table 3-2. AM1705 Top Level Memory Map
Start Address
End Address
Size
ARM Mem Map
EDMA Mem PRUSS Mem
Master Peripheral
Mem Map
Map
Map
0x0000 0000
0x0000 0FFF
4K
-
PRUSS Local
Address
Space
0x0000 1000
0x01BC 0000
0x01BB FFFF
0x01BC 0FFF
-
4K
ARM ETB
-
memory
0x01BC 1000
0x01BC 1800
0x01BC 17FF
0x01BC 18FF
2K
ARM ETB reg
-
-
256
ARM Ice
Crusher
0x01BC 1900
0x01C0 0000
0x01C0 8000
0x01C0 8400
0x01C0 8800
0x01C1 0000
0x01C1 1000
0x01C1 2000
0x01C1 4000
0x01C1 5000
0x01C2 0000
0x01C2 1000
0x01C2 2000
0x01C2 3000
0x01C2 4000
0x01C4 0000
0x01C4 1000
0x01C4 2000
0x01C4 3000
0x01D0 0000
0x01D0 1000
0x01D0 2000
0x01D0 3000
0x01D0 4000
0x01D0 5000
0x01D0 6000
0x01D0 7000
0x01D0 8000
0x01D0 9000
0x01D0 A000
0x01D0 B000
0x01D0 C000
0x01D0 D000
0x01D0 E000
0x01E0 0000
0x01E1 0000
0x01E1 1000
0x01BF FFFF
0x01C0 7FFF
0x01C0 83FF
0x01C0 87FF
0x01C0 FFFF
0x01C1 0FFF
0x01C1 1FFF
0x01C1 3FFF
0x01C1 4FFF
0x01C1 FFFF
0x01C2 0FFF
0x01C2 1FFF
0x01C2 2FFF
0x01C2 3FFF
0x01C3 FFFF
0x01C4 0FFF
0x01C4 1FFF
0x01C4 2FFF
0x01CF FFFF
0x01D0 0FFF
0x01D0 1FFF
0x01D0 2FFF
0x01D0 3FFF
0x01D0 4FFF
0x01D0 5FFF
0x01D0 6FFF
0x01D0 7FFF
0x01D0 8FFF
0x01D0 9FFF
0x01D0 AFFF
0x01D0 BFFF
0x01D0 CFFF
0x01D0 DFFF
0x01DF FFFF
0x01E0 FFFF
0x01E1 0FFF
0x01E1 1FFF
-
32K
1024
1024
EDMA3 CC
EDMA3 TC0
EDMA3 TC1
-
4K
4K
PSC 0
PLL Controller
-
4K
SYSCFG
-
4K
4K
4K
Timer64P 0
Timer64P 1
I2C 0
4K
4K
4K
MMC/SD 0
SPI 0
UART 0
-
4K
4K
4K
McASP 0 Control
McASP 0 AFIFO Ctrl
McASP 0 Data
-
4K
4K
4K
McASP 1 Control
McASP 1 AFIFO Ctrl
McASP 1 Data
-
-
-
-
-
4K
4K
UART 1
UART 2
64K
USB0
-
-
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Table 3-2. AM1705 Top Level Memory Map (continued)
Start Address
End Address
Size
ARM Mem Map
EDMA Mem PRUSS Mem
Map Map
Master Peripheral
Mem Map
0x01E1 2000
0x01E1 3000
0x01E1 4000
0x01E1 5000
0x01E1 6000
0x01E2 0000
0x01E2 2000
0x01E2 3000
0x01E2 4000
0x01E2 5000
0x01E2 6000
0x01E2 7000
0x01E2 8000
0x01E2 9000
0x01F0 0000
0x01F0 1000
0x01F0 2000
0x01F0 3000
0x01F0 4000
0x01F0 5000
0x01F0 6000
0x01F0 7000
0x01F0 8000
0x01F0 9000
0x01F0 A000
0x01F0 B000
0x4000 0000
0x4800 0000
0x6000 0000
0x6200 0000
0x6400 0000
0x6600 0000
0x6800 0000
0x6800 8000
0x8000 0000
0x8002 0000
0xB000 0000
0xB000 8000
0xC000 0000
0xD000 0000
0xFFFD 0000
0x01E1 2FFF
0x01E1 3FFF
0x01E1 4FFF
0x01E1 5FFF
0x01E1 FFFF
0x01E2 1FFF
0x01E2 2FFF
0x01E2 3FFF
0x01E2 4FFF
0x01E2 5FFF
0x01E2 6FFF
0x01E2 7FFF
0x01E2 8FFF
0x01EF FFFF
0x01F0 0FFF
0x01F0 1FFF
0x01F0 2FFF
0x01F0 3FFF
0x01F0 4FFF
0x01F0 5FFF
0x01F0 6FFF
0x01F0 7FFF
0x01F0 8FFF
0x01F0 9FFF
0x01F0 AFFF
0x3FFF FFFF
0x47FF FFFF
0x5FFF FFFF
0x61FF FFFF
0x63FF FFFF
0x65FF FFFF
0x67FF FFFF
0x6800 7FFF
0x7FFF FFFF
0x8001 FFFF
0xAFFF FFFF
0xB000 7FFF
0xBFFF FFFF
0xCFFF FFFF
0xFFFC FFFF
0xFFFD FFFF
4K
SPI 1
-
4K
4K
Memory Protection Unit 1 (MPU 1)
Memory Protection Unit 2 (MPU 2)
-
8K
4K
4K
4K
EMAC Control Module RAM
EMAC Control Module Registers
EMAC Control Registers
EMAC MDIO port
-
4K
4K
4K
GPIO
PSC 1
I2C 1
-
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
eHRPWM 0
HRPWM 0
eHRPWM 1
HRPWM 1
eHRPWM 2
HRPWM 2
ECAP 0
ECAP 1
ECAP 2
EQEP 0
EQEP 1
-
-
-
32M
32M
32M
32M
32K
EMIFA async data (CS2)
EMIFA async data (CS3)
EMIFA async data (CS4)
EMIFA async data (CS5)
EMIFA Control Regs
-
128K
32K
On-chip RAM
-
EMIFB Control Regs
-
256M
64K
EMIFB SDRAM Data
ARM local
-
ROM
0xFFFE 0000
0xFFFE E000
0xFFFE DFFF
0xFFFE FFFF
-
8K
8K
ARM Interrupt
Controller
-
0xFFFF 0000
0xFFFF 1FFF
ARM local
RAM
-
ARM local
RAM (PRU 0
Only)
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Table 3-2. AM1705 Top Level Memory Map (continued)
Start Address
End Address
Size
ARM Mem Map
EDMA Mem PRUSS Mem
Map Map
Master Peripheral
Mem Map
0xFFFF 2000
0xFFFF FFFF
-
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3.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
3.5.1 Pin Map (Bottom View)
RSV2
USB0_VDDA12
USB0_VDDA18
NC
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
EMB_SDCKE
DVDD
EMB_CLK
EMB_WE_DQM[1]/GP5[14]
EMB_D[8]/GP6[8]
EMB_D[9]/GP6[9]
EMB_D[10]/GP6[10]
DVDD
USB0_DP
USB0_DM
NC
USB0_VDDA33
PLL0_VDDA
EMB_D[11]/GP6[11]
EMB_D[12]/GP6[12]
EMB_D[13]/GP6[13]
CVDD
PLL0_VSSA
OSCIN
OSCVSS
OSCOUT
EMB_D[14]/GP6[14]
DVDD
RESET
CVDD
EMB_D[15]/GP6[15]
EMB_D[0]/GP6[0]
EMB_D[1]/GP6[1]
DVDD
RSV4
RSV3
TRST
DVDD
EMB_D[2]/GP6[2]
CVDD
TMS
TDI
EMB_D[3]/GP6[3]
RVDD
VSS
CVDD
(177)
Thermal Pad
TCK
EMB_D[4]/GP6[4]
DVDD
TDO
GP7[14]
EMB_D[5]/GP6[5]
EMB_D[6]/GP6[6]
EMB_D[7]/GP6[7]
CVDD
DVDD
RVDD
AHCLKX1/EPWM0B/GP3[14]
CVDD
EMB_WE_DQM[0]/GP5[15]
EMB_WE
ACLKX1/EPWM0A/GP3[15]
AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10]
DVDD
DVDD
EMB_CAS
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
CVDD
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
DVDD
CVDD
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
DVDD
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
CVDD
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
DVDD
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
AXR1[1]/GP4[1]
Figure 3-1. Pin Map (PTP)
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3.6 Terminal Functions
to identify the external signal names, the associated pin/ball numbers along with the mechanical package
designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown
resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.
3.6.1 Device Reset and JTAG
Table 3-3. Reset and JTAG Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
RESET
DESCRIPTION
PTP
RESET
146
I
Device reset input
JTAG
IPU
IPU
IPD
IPU
IPD
IPU
TMS
TDI
152
153
156
155
150
-
I
I
JTAG test mode select
JTAG test data input
JTAG test data output
JTAG test clock
TDO
TCK
TRST
O
I
I
JTAG test reset
EMU[0]/GP7[15]
I/O
Emulation Signal
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.2 High-Frequency Oscillator and PLL
Table 3-4. High-Frequency Oscillator and PLL Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
DESCRIPTION
PTP
1.2-V OSCILLATOR
OSCIN
143
145
144
I
Oscillator input
Oscillator output
OSCOUT
OSCVSS
O
GND
Oscillator ground (for filter only)
1.2-V PLL
PLL0_VDDA
PLL0_VSSA
141
142
PWR
GND
PLL analog VDD (1.2-V filtered supply)
PLL analog VSS (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.3 External Memory Interface A (ASYNC)
Table 3-5. External Memory Interface A (EMIFA) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
MMC/SD, GPIO,
BOOT
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
54
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
52
51
49
48
46
45
I/O
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
IPU
IPU
MMC/SD, GPIO EMIFA data bus
MMC/SD, GPIO,
BOOT
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
44
I/O
IPU
EMA_A[12]/GP1[12]
EMA_A[11]/ GP1[11]
EMA_A[10]/GP1[10]
EMA_A[9]/GP1[9]
42
41
27
40
39
37
36
35
34
32
31
30
29
26
25
21
23
22
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPD
IPU
IPU
IPU
IPU
IPU
EMA_A[8]/GP1[8]
GPIO
EMIFA address bus
EMA_A[7]/GP1[7]
EMA_A[6]/GP1[6]
EMA_A[5]/GP1[5]
EMA_A[4]/GP1[4]
EMA_A[3]/GP1[3]
EMA_A[2]/MMCSD_CMD/GP1[2]
EMA_A[1]/MMCSD_CLK/GP1[1]
EMA_A[0]/GP1[0]
MMCSD, GPIO
GPIO
EMIFA address bus.
EMIFA bank address
EMA_BA[1]/GP1[13]
EMA_BA[0]/GP1[14]
EMA_CS[3] /GP2[6]
EMA_CS[2]/GP2[5]/BOOT[15]
EMA_OE /AXR0[13]/GP2[7]
GPIO
GPIO
EMIFA Async Chip
Select
GPIO, BOOT
McASP0, GPIO EMIFA output enable.
EMIFA wait
GPIO
EMA_WAIT[0]/ GP2[10]
19
I
IPU
input/interrupt.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.4 External Memory Interface B (only SDRAM )
Table 3-6. External Memory Interface B (EMIFB) Terminal Functions
PIN NO
PTP
74
SIGNAL NAME
EMB_D[15]/GP6[15]
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
EMB_D[14]/GP6[14]
EMB_D[13]/GP6[13]
EMB_D[12]/GP6[12]
EMB_D[11]/GP6[11]
EMB_D[10]/GP6[10]
EMB_D[9]/GP6[9]
EMB_D[8]/GP6[8]
EMB_D[7]/GP6[7]
EMB_D[6]/GP6[6]
EMB_D[5]/GP6[5]
EMB_D[4]/GP6[4]
EMB_D[3]/GP6[3]
EMB_D[2]/GP6[2]
EMB_D[1]/GP6[1]
EMB_D[0]/GP6[0]
EMB_A[12]/GP3[13]
EMB_A[11]/GP7[13]
EMB_A[10]/GP7[12]
EMB_A[9]/GP7[11]
EMB_A[8]/GP7[10]
EMB_A[7]/GP7[9]
EMB_A[6]/GP7[8]
EMB_A[5]/GP7[7]
EMB_A[4]/GP7[6]
EMB_A[3]/GP7[5]
EMB_A[2]/GP7[4]
EMB_A[1]/GP7[3]
EMB_A[0]/GP7[2]
EMB_BA[1]/GP7[0]
EMB_BA[0]/GP7[1]
EMB_CLK
76
78
79
80
82
83
84
GPIO
EMIFB SDRAM data bus.
62
63
64
66
68
70
72
73
89
91
O
105
92
O
O
EMIFB SDRAM row/column
address bus.
GPIO
94
O
95
O
96
O
97
O
98
O
100
101
102
103
106
107
86
O
EMIFB SDRAM row/column
address.
O
O
GPIO
O
O
EMIFB SDRAM bank address.
O
O
EMIF SDRAM clock.
EMB_SDCKE
88
I/O
O
EMIFB SDRAM clock enable.
EMIFB write enable
EMB_WE
59
EMIFB SDRAM row address
strobe.
EMB_RAS
110
O
IPU
EMB_CAS
57
O
O
IPU
IPU
EMIFB column address strobe.
EMIFB SDRAM chip select 0.
EMB_CS[0]
108
EMIFB write enable/data mask
for EMB_D.
EMB_WE_DQM[1] /GP5[14]
EMB_WE_DQM[0] /GP5[15]
85
60
O
O
IPU
IPU
GPIO
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.5 Serial Peripheral Interface Modules (SPI0, SPI1)
Table 3-7. Serial Peripheral Interface (SPI) Terminal Functions
PIN NO
PTP
SIGNAL NAME
TYPE(1)
SPI0
PULL(2)
MUXED
DESCRIPTION
UART0, EQEP0B,
GPIO, BOOT
SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
I/O
IPU
SPI0 chip select.
SPI0 enable.
UART0, EQEP0A,
GPIO, BOOT
SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
12
11
I/O
I/O
IPU
IPD
eQEP1, GPIO, BOOT SPI0 clock.
SPI0 data
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
18
17
I/O
I/O
IPD
IPD
slave-in-master-
out.
eQEP0, GPIO, BOOT
SPI0 data
slave-out-master-
in.
SPI1
SPI1_SCS[0] /UART2_TXD/GP5[13]
SPI1_ENA /UART2_RXD/GP5[12]
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
8
7
I/O
I/O
I/O
IPU
IPU
IPD
SPI1 chip select.
SPI1 enable.
UART2, GPIO
16
eQEP1, GPIO, BOOT SPI1 clock.
SPI1 data
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
14
13
I/O
I/O
IPU
IPU
slave-in-master-
out.
I2C1, GPIO, BOOT
SPI1 data
slave-out-master-
in.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.6 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon
how the eCAP module is programmed.
Table 3-8. Enhanced Capture Module (eCAP) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
eCAP0
PULL(2)
MUXED
DESCRIPTION
PTP
enhanced capture 0
input or auxiliary
PWM 0 output.
ACLKX0/ECAP0/APWM0/GP2[12]
126
I/O
I/O
I/O
IPD
McASP0, GPIO
eCAP1
eCAP2
enhanced capture 1
input or auxiliary
PWM 1 output.
ACLKR0/ECAP1/APWM1/GP2[15]
ACLKR1/ECAP2/APWM2/GP4[12]
130
165
IPD
IPD
McASP0, GPIO
McASP1, GPIO
enhanced capture 2
input or auxiliary
PWM 2 output.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.7 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
Table 3-9. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
PTP
eHRPWM0
eHRPWM0 A output
(with
high-resolution).
ACLKX1/EPWM0A/GP3[15]
162
160
132
I/O
I/O
I/O
IPD
IPD
IPD
McASP1, GPIO
eHRPWM0 B
output.
AHCLKX1/EPWM0B/GP3[14]
AMUTE1/EPWMTZ/GP4[14]
McASP1,
eHRPWM1, GPIO,
eHRPWM2
eHRPWM0 trip zone
input.
Sync input to
McASP1,
eHRPWM0, GPIO
eHRPWM0 module
or sync output to
external PWM.
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
163
I/O
IPD
eHRPWM1
eHRPWM1 A (with
high-resolution).
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
168
169
I/O
I/O
IPD
IPD
McASP1, GPIO
eHRPWM1 B
output.
McASP1,
eHRPWM0, GPIO,
eHRPWM2
eHRPWM1 trip zone
input.
AMUTE1/EPWMTZ/GP4[14]
132
I/O
IPD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-9. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions (continued)
PIN NO
PTP
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
eHRPWM2
eHRPWM2 A (with
high-resolution).
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
170
171
I/O
I/O
IPD
IPD
McASP1, GPIO
eHRPWM2 B
output.
McASP1,
eHRPWM0, GPIO,
eHRPWM2
eHRPWM2 trip zone
input.
AMUTE1/EPWMTZ/GP4[14]
132
I/O
IPD
3.6.8 Enhanced Quadrature Encoder Pulse Module (eQEP)
Table 3-10. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
PTP
eQEP0
eQEP0A quadrature
input.
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
12
9
I
I
IPU
IPU
SPIO, UART0,
GPIO, BOOT
eQEP0B quadrature
input.
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
17
18
I
I
IPD
IPD
eQEP0 index.
eQEP0 strobe.
SPI0, GPIO, BOOT
McASP1, GPIO
eQEP1
eQEP1A quadrature
input.
AXR1[3]/EQEP1A/GP4[3]
AXR1[4]/EQEP1B/GP4[4]
174
173
I
I
IPD
IPD
eQEP1B quadrature
input.
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
11
16
I
I
IPD
IPD
SPI0, GPIO, BOOT eQEP1 index.
SPI1, GPIO, BOOT eQEP1 strobe.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.9 Boot
Table 3-11. Boot Terminal Functions(1)
PIN NO
SIGNAL NAME
EMA_CS[2]/GP2[5]/BOOT[15]
TYPE(2)
PULL(3)
MUXED
DESCRIPTION
PTP
23
I
I
IPU
IPU
EMIFA, GPIO
BOOT[15].
BOOT[14].
EMIFA, McASP0,
GPIO
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
55
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
54
44
I
I
IPU
IPU
BOOT[13].
BOOT[12].
EMIFA, MMC/SD,
GPIO
(1) Boot decoding will be defined in the ROM datasheet.
(2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(3) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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(1)
Table 3-11. Boot Terminal Functions
(continued)
PIN NO
PTP
SIGNAL NAME
TYPE(2)
PULL(3)
MUXED
DESCRIPTION
McASP0, EMAC,
GPIO
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
AFSX0/GP2[13]/BOOT[10]
129
127
3
I
I
I
IPD
IPD
IPU
BOOT[11].
BOOT[10].
BOOT[9].
McASP0, GPIO
UART0, I2C0, Timer0,
GPIO
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
UART0, I2C0, Timer0,
GPIO
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
I
IPU
BOOT[8].
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
16
14
13
I
I
I
IPD
IPU
IPU
SPI1, eQEP1, GPIO
BOOT[7].
BOOT[6].
BOOT[5].
SPI1, I2C1, GPIO
SPI0, UART0,
eQEP0, GPIO
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
9
I
I
IPU
IPU
BOOT[4].
BOOT[3].
SPI0, UART0,
eQEP0, GPIO
12
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
11
18
17
I
I
I
IPD
IPD
IPD
SPIO, eQEP1, GPIO BOOT[2].
BOOT[1].
SPI0, eQEP0, GPIO
BOOT[0].
3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
Table 3-12. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
UART0
I2C0, BOOT,
Timer0, GPIO,
UART0 receive
data.
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
2
3
I
IPU
IPU
I2C0, Timer0,
GPIO, BOOT
UART0 transmit
data.
O
UART0
SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3]
9
O
I
IPU
IPU
ready-to-send
output
SPIO, eQEP0,
GPIO, BOOT
UART0
clear-to-send input
12
UART1
122
UART1 receive
data.
UART1_RXD/AXR0[9]/GP3[9](3)
UART1_TXD/AXR0[10]/GP3[10](3)
I
IPD
IPD
McASP0, GPIO
SPI1, GPIO
UART1 transmit
data.
123
UART2
7
O
UART2 receive
data.
SPI1_ENA/UART2_RXD/GP5[12]
SPI1_SCS[0]/UART2_TXD/GP5[13]
I
IPU
IPU
UART2 transmit
data.
8
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if
UART1 boot mode is used.
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3.6.11 Inter-Integrated Circuit Modules(I2C0, I2C1)
Table 3-13. Inter-Integrated Circuit (I2C) Terminal Functions
PIN NO
PTP
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
I2C0
UART0, Timer0,
GPIO, BOOT
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
2
3
I/O
I/O
IPU
IPU
I2C0 serial data.
I2C0 serial clock.
UART0, Timer0,
GPIO, BOOT
I2C1
14
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
I/O
I/O
IPU
IPU
I2C1 serial Data.
I2C1 serial clock.
SPI1, GPIO,
BOOT
13
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.12 Timers
Table 3-14. Timers Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
TIMER0
Timer0 lower
input.
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
2
I
IPU
IPU
UART0, I2C0,
GPIO, BOOT
Timer0 lower
output
3
O
TIMER1 (Watchdog )
No external pins. The Timer1 peripheral pins are not pinned out as external pins.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)
Table 3-15. Multichannel Audio Serial Ports (McASPs) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
PTP
McASP0
EMA_OE/AXR0[13]/GP2[7]
22
I/O
I/O
IPU
IPU
EMIFA, GPIO
EMIFA, GPIO,
BOOT
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
AXR0[11]/ AXR2[0]/GP3[11]
55
McASP2,
GPIO
124
I/O
IPD
UART1_TXD/AXR0[10]/GP3[10]
UART1_RXD/AXR0[9]/GP3[9]
AXR0[8]/MDIO_D/GP3[8]
123
122
121
120
118
117
116
115
113
112
111
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
GPIO
GPIO
McASP0 serial
data.
MDIO, GPIO
AXR0[7]/MDIO_CLK/GP3[7]
AXR0[6]/RMII_RXER/GP3[6]
AXR0[5]/RMII_RXD[1]/GP3[5]
AXR0[4]/RMII_RXD[0]/GP3[4]
AXR0[3]/RMII_CRS_DV/GP3[3]
AXR0[2]/RMII_TXEN/GP3[2]
AXR0[1]/RMII_TXD[1]/GP3[1]
AXR0[0]/RMII_TXD[0]/GP3[0]
EMAC, GPIO
McASP0
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
ACLKX0/ECAP0/APWM0/GP2[12]
AFSX0/GP2[13]/BOOT[10]
125
126
127
I/O
I/O
I/O
IPD
IPD
IPD
USB, GPIO
transmit master
clock.
McASP0
eCAP0, GPIO transmit bit
clock.
McASP0
transmit frame
sync.
GPIO, BOOT
EMAC, GPIO, McASP0 receive
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
ACLKR0/ECAP1/APWM1/GP2[15]
AFSR0/GP3[12]
129
130
131
I/O
I/O
I/O
IPD
IPD
IPD
BOOT
master clock.
McASP0 receive
bit clock.
eCAP1, GPIO
McASP0 receive
frame sync.
GPIO
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-15. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
PIN NO
PTP
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
McASP1
AXR1[11]/GP5[11]
AXR1[10]/GP5[10]
7
4
I/O
I/O
IPU
IPU
GPIO
eHRPWM1 A,
GPIO
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
168
169
170
171
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
eHRPWM1 B,
GPIO
eHRPWM2 A,
GPIO
McASP1 serial
data.
eHRPWM2 B,
GPIO
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
173
174
175
176
1
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
eQEP, GPIO
AXR1[1]/GP4[1]
GPIO
AXR1[0]/GP4[0]
McASP1
transmit master
clock.
eHRPWM0,
GPIO
AHCLKX1/EPWM0B/GP3[14]
160
162
163
I/O
I/O
I/O
IPD
IPD
IPD
McASP1
transmit bit
clock.
eHRPWM0,
GPIO
ACLKX1/EPWM0A/GP3[15]
McASP1
transmit frame
sync.
eHRPWM0,
GPIO
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
McASP1 receive
bit clock.
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
165
166
I/O
I/O
IPD
IPD
eCAP2, GPIO
GPIO
McASP1 receive
frame sync.
eHRPWM0,
eHRPWM1,
GPIO,
McASP1 mute
output.
AMUTE1/EPWMTZ/GP4[14]
132
O
IPD
eHRPWM2
3.6.14 Universal Serial Bus Modules (USB0)
Table 3-16. Universal Serial Bus (USB) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
DESCRIPTION
PTP
USB0 2.0 OTG (USB0)
USB0_DM
138
A
A
USB0 PHY data minus
USB0_DP
137
140
135
134
125
USB0 PHY data plus
USB0_VDDA33
USB0_VDDA18
USB0_VDDA12(3)
PWR
PWR
PWR
I
USB0 PHY 3.3-V supply
USB0 PHY 1.8-V supply input
USB0 PHY 1.2-V LDO output for bypass cap
USB_REFCLKIN. Optional clock input.
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
IPD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 uF capacitor to VSS.
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3.6.15 Ethernet Media Access Controller (EMAC)
Table 3-17. Ethernet Media Access Controller (EMAC) Terminal Functions
PIN NO
PTP
SIGNAL NAME
TYPE(1)
RMII
PULL(2)
MUXED
DESCRIPTION
EMAC 50-MHz
clock input or
output.
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
AXR0[6]/RMII_RXER/GP3[6]
129
118
I/O
IPD
IPD
McASP0, GPIO, BOOT
EMAC RMII
receiver error.
I
AXR0[5]/RMII_RXD[1]/GP3[5]
AXR0[4]/RMII_RXD[0]/GP3[4]
117
116
I
I
IPD
IPD
EMAC RMII
receive data.
EMAC RMII carrier
sense data valid.
AXR0[3]/RMII_CRS_DV/GP3[3]
AXR0[2]/RMII_TXEN/GP3[2]
115
113
I
IPD
IPD
McASP0, GPIO
EMAC RMII
transmit enable.
O
AXR0[1]/RMII_TXD[1]/GP3[1]
AXR0[0]/RMII_TXD[0]/GP3[0]
112
111
O
O
IPD
IPD
EMAC RMII trasmit
data.
MDIO
I/O
AXR0[8]/MDIO_D/GP3[8]
121
120
IPU
IPD
McASP0, GPIO
MDIO data clock.
AXR0[7]/MDIO_CLK/GP3[7]
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.16 Multimedia Card/Secure Digital (MMC/SD)
Table 3-18. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
PIN
NO
SIGNAL NAME
EMA_A[1]/MMCSD_CLK/GP1[1]
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
30
31
54
52
51
49
48
46
45
44
O
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
MMCSD_CLK.
MMCSD_CMD.
EMIFA, GPIO
EMA_A[2]/MMCSD_CMD/GP1[2]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
EMIFA, GPIO, BOOT
EMIFA, GPIO
MMC/SD data.
EMIFA, GPIO, BOOT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.17 General-Purpose IO Only Terminal Functions
Table 3-19. General-Purpose IO Only Terminal Functions
PIN NO
PTP
SIGNAL NAME
TYPE
PULL
DESCRIPTION
(1)
GP7[14]
157
I/O
IPD
General-Purpose IO signal.
(1) GP7[14] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
3.6.18 Reserved and No Connect
Table 3-20. Reserved and No Connect Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
DESCRIPTION
PTP
Reserved. For proper device operation, this pin must be tied directly to
RSV2
RSV3
133
PWR
PWR
CVDD
Reserved. For proper device operation, this pin must be tied directly to
CVDD
.
149
.
RSV4
NC
148
136
139
I
-
-
Reserved. This pin may be tied high or low.
No Connect (leave unconnected)
NC
No Connect (leave unconnected)
(1) PWR = Supply voltage.
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3.6.19 Supply and Ground
Table 3-21. Supply and Ground Terminal Functions
PIN NO
PTP
SIGNAL NAME
TYPE(1)
DESCRIPTION
10, 20, 28, 38,
50, 56, 61, 69,
77, 93, 104,
114, 147, 154,
161, 167
CVDD (Core supply)
PWR
PWR
1.2-V core supply voltage pins
RVDD (Internal RAM supply)
DVDD (I/O supply)
67, 159
1.2V internal ram supply voltage pins
3.3-V I/O supply voltage pins.
Ground pins.
5, 15, 24, 33,
43, 47, 53, 58,
65, 71, 75, 81,
87, 90, 99,
109, 119, 128,
151, 158, 164,
172
PWR
GND
VSS (Ground)
177
(1) PWR = Supply voltage, GND - Ground.
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4 Device Configuration
4.1 Boot Modes
This device supports a variety of boot modes through an internal ROM bootloader. This device does not
support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input
states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system
configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by
the values of the BOOT pins
The following boot modes are supported:
•
NAND Flash boot
8-bit NAND
NOR Flash boot
–
•
–
–
–
NOR Direct boot (8-bit or 16-bit)
NOR Legacy boot (8-bit or 16-bit)
NOR AIS boot (8-bit or 16-bit)
•
•
I2C0 / I2C1 Boot
–
–
EEPROM (Master Mode)
External Host (Slave Mode)
SPI0 / SPI1 Boot
–
–
–
Serial Flash (Master Mode)
SERIAL EEPROM (Master Mode)
External Host (Slave Mode)
•
UART0 / UART1 / UART2 Boot
External Host
–
4.2 SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
•
•
•
•
•
Readable Device, Die, and Chip Revision ID
Control of Pin Multiplexing
Priority of bus accesses different bus masters in the system
Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
Special case settings for peripherals:
–
–
–
–
–
Locking of PLL controller settings
Default burst sizes for EDMA3 TC0 and TC1
Selection of the source for the eCAP module input capture (including on chip sources)
McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals
Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
–
Clock source selection for EMIFA and EMIFB
•
Selects the source of emulation suspend signal of peripherals supporting this function.
Since the SYSCFG peripheral controls global operation of the device, its registers are protected against
erroneous accesses by several mechanisms:
•
A special key sequence must be written to KICK0, KICK1 registers before any other registers are
writeable.
•
Additionally, many registers are accessible only by a host (ARM) when it is operating in its privileged
mode. (ex. from the kernel, but not from user space code).
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Table 4-1. System Configuration (SYSCFG) Module Register Access
BYTE ADDRESS
0x01C1 4000
0x01C14008
0x01C1 400C
0x01C1 4010
0x01C1 4014
0x01C1 4018
0x01C1 4020
0x01C1 4038
0x01C1 403C
0x01C1 4040
0x01C1 4044
0x01C1 40E0
0x01C1 40E4
0x01C1 40E8
0x01C1 40EC
0x01C1 40F0
0x01C1 40F4
0x01C1 40F8
0x01C1 4110
0x01C1 4114
0x01C1 4118
0x01C1 4120
0x01C1 4124
0x01C1 4128
0x01C1 412C
0x01C1 4130
0x01C1 4134
0x01C1 4138
0x01C1 413C
0x01C1 4140
0x01C1 4144
0x01C1 4148
0x01C1 414C
0x01C1 4150
0x01C1 4154
0x01C1 4158
0x01C1 415C
0x01C1 4160
0x01C1 4164
0x01C1 4168
0x01C1 416C
0x01C1 4170
0x01C1 4174
0x01C1 4178
0x01C1 417C
0x01C1 4180
0x01C1 4184
ACRONYM
REVID
REGISTER DESCRIPTION
Revision Identification Register
ACCESS
—
DIEIDR0
DIEIDR1
DIEIDR2
DIEIDR3
DEVIDR0
BOOTCFG
KICK0R
Device Identification Register 0
Device Identification Register 1
Device Identification Register 2
Device Identification Register 3
Device Identification Register 0
Boot Configuration Register
Kick 0 Register
—
—
—
—
—
Privileged mode
Privileged mode
Privileged mode
—
KICK1R
Kick 1 Register
HOST0CFG
HOST1CFG
IRAWSTAT
IENSTAT
IENSET
Host 0 Configuration Register
Host 1 Configuration Register
Interrupt Raw Status/Set Register
Interrupt Enable Status/Clear Register
Interrupt Enable Register
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
IENCLR
Interrupt Enable Clear Register
End of Interrupt Register
EOI
FLTADDRR
FLTSTAT
MSTPRI0
MSTPRI1
MSTPRI2
PINMUX0
PINMUX1
PINMUX2
PINMUX3
PINMUX4
PINMUX5
PINMUX6
PINMUX7
PINMUX8
PINMUX9
PINMUX10
PINMUX11
PINMUX12
PINMUX13
PINMUX14
PINMUX15
PINMUX16
PINMUX17
PINMUX18
PINMUX19
SUSPSRC
-
Fault Address Register
Fault Status Register
Master Priority 0 Register
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
Master Priority 1 Register
Master Priority 2 Register
Pin Multiplexing Control 0 Register
Pin Multiplexing Control 1 Register
Pin Multiplexing Control 2 Register
Pin Multiplexing Control 3 Register
Pin Multiplexing Control 4 Register
Pin Multiplexing Control 5 Register
Pin Multiplexing Control 6 Register
Pin Multiplexing Control 7 Register
Pin Multiplexing Control 8 Register
Pin Multiplexing Control 9 Register
Pin Multiplexing Control 10 Register
Pin Multiplexing Control 11 Register
Pin Multiplexing Control 12 Register
Pin Multiplexing Control 13 Register
Pin Multiplexing Control 14 Register
Pin Multiplexing Control 15 Register
Pin Multiplexing Control 16 Register
Pin Multiplexing Control 17 Register
Pin Multiplexing Control 18 Register
Pin Multiplexing Control 19 Register
Suspend Source Register
Reserved
-
Reserved
—
CFGCHIP0
CFGCHIP1
CFGCHIP2
Chip Configuration 0 Register
Chip Configuration 1 Register
Chip Configuration 2 Register
Privileged mode
Privileged mode
Privileged mode
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Table 4-1. System Configuration (SYSCFG) Module Register Access (continued)
BYTE ADDRESS
0x01C1 4188
ACRONYM
CFGCHIP3
CFGCHIP4
REGISTER DESCRIPTION
Chip Configuration 3 Register
Chip Configuration 4 Register
ACCESS
Privileged mode
Privileged mode
0x01C1 418C
4.3 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•
Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly
recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,
providing external connectivity can help ensure that valid logic levels are latched on these device boot and
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration
pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
•
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the IO supply rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
•
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
for their specific application.
•
•
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH)
for the device, see Section 5.2, Recommended Operating Conditions.
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range
(1)
(Unless Otherwise Noted)
Core
-0.5 V to 1.4 V
-0.5 V to 2 V
(2)
(CVDD, RVDD, PLL0_VDDA )
I/O, 1.8V
(USB0_VDDA18)
Supply voltage ranges
(2)
I/O, 3.3V
(DVDD, USB0_VDDA33)
-0.5 V to 3.8V
(2)
VI I/O, 1.2V
(OSCIN)
-0.3 V to CVDD + 0.3V
-0.3V to DVDD + 0.3V
VI I/O, 3.3V
(Steady State)
VI I/O, 3.3V
DVDD + 20%
up to 20% of Signal
Period
Input voltage ranges
(Transient)
VI I/O, USB 5V Tolerant Pins:
(USB0_DM, USB0_DP)
5.25V(3)
VI I/O, USB0 VBUS
VO I/O, 3.3V
5.50V(3)
-0.5 V to DVDD + 0.3V
(Steady State)
Output voltage ranges
VO I/O, 3.3V
20% of DVDD for up to
20% of the signal period
(Transient Overshoot/Undershoot)
Input or Output Voltages 0.3V above or below their respective power
±20mA
Clamp Current
rails. Limit clamp current that flows through the I/O's internal diode
protection cells.
Storage temperature range, Tstg
(default)
-55°C to 150°C
0°C to 90°C
Commercial (default)
Industrial (D version)
Extended (A version)
Operating Junction Temperature ranges,
TJ
-40°C to 90°C
-40°C to 105°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS
(3) Up to a max of 24 hours.
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5.2 Recommended Operating Conditions
MIN
1.14
1.25
1.14
NOM
1.2
MAX
1.32
1.35
1.32
UNIT
375 MHz version
456 MHz version
V
V
V
Supply voltage, Core
(CVDD, PLL0_VDDA )
CVDD
RVDD
1.3
Supply Voltage, Internal RAM
1.2
Supply voltage, I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18)
1.71
3.15
0
1.8
3.3
0
1.89
3.45
0
V
V
DVDD
VSS
Supply voltage, I/O, 3.3V
(DVDD, USB0_VDDA33)
Supply ground
V
V
(VSS, PLL0_VSSA, OSCVSS(1)
)
High-level input voltage, I/O, 3.3V
High-level input voltage, OSCIN
Low-level input voltage, I/O, 3.3V
Low-level input voltage, OSCIN
Input Hysteresis
2
(2)
VIH
0.7*CVDD
0.8
V
(2)
VIL
0.3*CVDD
VHYS
USB
160
5
mV
V
USB0_VBUS
4.75
0
5.25
Transition time, 10%-90%, All Inputs (unless otherwise specified in
the electrical data sections)
(3)
tt
0.25P
ns
375 (1.2V)
456 (1.3V)
Commercial (default)
MHz
FSYSCLK6
ARM Operating Frequency (SYSCLK6)
Industrial (D suffix)
375 (1.2V)
456(1.3V)
0
0
MHz
MHz
Extended (A suffix)
375(1.2V)
(1) When an external crystal is used, oscillator (OSC_VSS) ground must be kept separate from other grounds and connected directly to the
crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit
board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(2) These I/O specifications do not apply to USB I/Os. USB0 I/Os adhere to USB2.0 specification.
(3) P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input
signals.
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Junction Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low/full speed:
USB0_DM and USB0_DP
2.8
USB0_VDDA33
440
V
VOH
High speed:
USB_DM and USB_DP
360
mV
DVDD= 3.15V, IOH = -4 mA
2.4
V
V
High-level output voltage (3.3V I/O)
DVDD= 3.15V, IOH = 100 mA
2.95
Low/full speed:
USB_DM and USB_DP
0.0
-10
0.3
10
V
High speed:
USB_DM and USB_DP
mV
VOL
DVDD= 3.15V, IOL = 4mA
0.4
0.2
V
V
Low-level output voltage (3.3V I/O)
DVDD= 3.15V, IOL = -100 mA
VI = VSS to DVDD without opposing
internal resistor
±35
-200
300
±40
mA
mA
mA
mA
VI = VSS to DVDD with opposing
30
(2)
internal pullup resistor
(1)
II
Input current
VI = VSS to DVDD with opposing
-50
(2)
internal pulldown resistor
VI = VSS to USB1_VDDA33 -
USB1_DM and USB1_DP
IOH
IOL
High-level output current
Low-level output current
I/O Off-state output current
All peripherals
-4
4
mA
mA
mA
pF
All peripherals
(3)
IOZ
VO = VDD or VSS; Internal pull disabled
LVCMOS signals
±35
3
CI
CO
Input capacitance
Output capacitance
LVCMOS signals
3
pF
(1) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(3) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
6.1.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.
V
ref
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
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6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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6.3 Power Supplies
6.3.1 Power-on Sequence
The device should be powered-on in the following order:
•
•
2a) CVDD core logic supply
2b) Other 1.2V logic supplies (RVDD, PLL0_VDDA). Groups 2a) and 2b) may be powered up together
or 2a) first followed by 2b).
•
•
3) All 1.8V IO supplies (USB0_VDDA18).
4) All digital IO and analog 3.3V PHY supplies (DVDD, USB0_VDDA33). USB0_VDDA33 is not
required if USB0 is not used and may be left unconnected.
There is no specific required voltage ramp rate for any of the supplies.
RESET must be maintained active until all power supplies have reached their nominal values.
Note: Future devices may support higher performance at a higher core logic voltage (CVDD). If future
migration is desired, the current design should provide separate supplies for 2a) and 2b). If not, then 2a)
and 2b) may be provided by a single supply.
6.3.2 Power-off Sequence
The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered
with the other supplies unpowered.
6.4 Unused USB0 (USB2.0) Pin Configurations
Table 6-1. Unused USB0 Pin Configurations
SIGNAL NAME
Configuration
(When USB0 is not used)
USB0_DM
USB0_DP
No connect
No connect
USB0_VDDA33
USB0_VDDA18
USB0_VBUS
USB0_VDDA12
No connect
No connect
No connect
No connect
AHCLKX0/AHCLKX2/USB_REFCLKIN/
GP2[11]
No connect or use as alternate function
6.5 Reset
6.5.1 Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are 3-stated .
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
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RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
RTCK is maintained active through a POR.
A summary of the effects of Power-On Reset is given below:
•
•
•
All internal logic (including emulation logic and the PLL logic) is reset to its default state
Internal memory is not maintained through a POR
All device pins go to a high-impedance state
CAUTION: A watchdog reset triggers a POR.
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6.5.2 Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are 3-stated .
During emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available
during emulation debug and development.
RTCK is maintained active through a warm reset.
A summary of the effects of Warm Reset is given below:
•
•
•
All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
Internal memory is maintained through a warm reset
All device pins go to a high-impedance state
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6.5.3 Reset Electrical Data Timings
Table 6-2 assumes testing over the recommended operating conditions.
(1)
Table 6-2. Reset Timing Requirements (,
)
No.
1
PARAMETER
MIN
100
20
MAX
UNIT
ns
tw(RSTL)
Pulse width, RESET/TRST low
2
tsu(BPV-RSTH)
th(RSTH-BPV)
Setup time, boot pins valid before RESET/TRST high
Hold time, boot pins valid after RESET/TRST high
ns
3
20
ns
(1) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
Power
Supplies
Ramping
Power Supplies Stable
Clock Source Stable
OSCIN
1
RESET
TRST
3
2
Boot Pins
Config
Figure 6-4. Power-On Reset (RESET and TRST active) Timing
Power Supplies Stable
OSCIN
TRST
1
RESET
3
2
Config
Boot Pins
Driven or Hi-Z
Figure 6-5. Warm Reset (RESET active, TRST high) Timing
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6.6 Crystal Oscillator or External Clock Input
The device includes two choices to provide an external clock input, which is fed to the on-chip PLL to
generate high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For
input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For
input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended.
Typical C1, C2 values are 10-20 pF.
•
•
Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit.
Figure 6-7 illustrates the option that uses an external 1.2V clock input.
C2
OSCIN
Clock Input
to PLL
X1
OSCOUT
C1
OSCVSS
Figure 6-6. On-Chip 1.2V Oscillator
Table 6-3. Oscillator Timing Requirements
PARAMETER
MIN
MAX
UNIT
fosc
Oscillator frequency range (OSCIN/OSCOUT)
12
30
MHz
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Clock
Input
to PLL
OSCIN
OSCOUT
NC
OSCVSS
Figure 6-7. External 1.2V Clock Source
Table 6-4. OSCIN Timing Requirements
No.
fOSCIN
PARAMETER
OSCIN frequency range (OSCIN)
Cycle time, external clock driven on OSCIN
MIN
12
MAX
UNIT
MHz
ns
50
tc(OSCIN)
20
tw(OSCINH) Pulse width high, external clock on OSCIN
tw(OSCINL) Pulse width low, external clock on OSCIN
0.4 tc(OSCIN)
0.4 tc(OSCIN)
ns
ns
(1)
tt(OSCIN)
tj(OSCIN)
Transition time, OSCIN
Period jitter, OSCIN
0.25P
0.02P
ns
ns
(1) P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input
signals.
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6.7 Clock PLLs
The device has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
•
•
•
•
Glitch-Free Transitions (on changing clock settings)
Domain Clocks Alignment
Clock Gating
PLL power down
The various clock outputs given by the controller are as follows:
•
•
Domain Clocks: SYSCLK [1:n]
Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
•
•
Post-PLL Divider: POSTDIV
SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
•
•
PLL Multiplier Control: PLLM
Software programmable PLL Bypass: PLLEN
6.7.1 PLL Device-Specific Information
The PLL requires some external filtering components to reduce power supply noise as shown in
Figure 6-8.
1.14V - 1.32V
50R
50R
PLL0_VDDA
0.1
µF
0.01
µF
VSS
PLL0_VSSA
Ferrite Bead: Murata BLM31PG500SN1L or Equivalent
Figure 6-8. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
CLKIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 6-9 illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 6-5 before enabling the processor to run from the PLL by
setting PLLEN = 1.
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CLKMODE
PLLEN
Square
1
Wave
PLLDIV1 (/1)
PLLDIV2 (/2)
OSCIN
Pre-Div
PLL
Post-Div
1
0
SYSCLK1
Crystal
0
SYSCLK2
PLLM
PLLDIV3 (/3)
PLLDIV4 (/4)
SYSCLK3
SYSCLK4
PLLDIV5 (/3)
PLLDIV7 (/6)
SYSCLK5
SYSCLK7
AUXCLK
EMIFA
0
1
Internal
Clock
Source
DIV4.5
CFGCHIP3[EMA_CLKSRC]
EMIFB
DIV4.5
1
0
Internal
Clock
Source
CFGCHIP3[EMB_CLKSRC]
Figure 6-9. PLL Topology
Table 6-5. Allowed PLL Operating Conditions
Default
Value
No.
PARAMETER
MIN
MAX
UNIT
PLLRST: Assertion time during
initialization
1
N/A
1000
N/A
ns
2000 N
Max PLL Lock Time =
Lock time: The time that the application
has to wait for the PLL to acquire locks
before setting PLLEN, after changing
PREDIV, PLLM, or OSCIN
m
OSCIN
cycles
2
N/A
/1
N/A
where N = Pre-Divider Ratio
M = PLL Multiplier
(1)
3
4
PREDIV
/1
/32
50
ns
PLL input frequency
( PLLREF)
12
MHz
(1)
5
6
7
PLL multiplier values (PLLM)
x20
N/A
/1
x4
x32
600(2)
/32
PLL output frequency. ( PLLOUT )
POSTDIV
400
/2(2)
MHz
ns
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 400 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed 300 MHz. The Post Divider and SYSCLK divider values must be
chosen such that the CPU clocks do not exceed 300 MHz.
(2) PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL
output clock.
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6.7.2 Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
6.7.3 PLL Controller 0 Registers
Table 6-6. PLL Controller 0 Registers
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
0x01C1 1000
0x01C1 10E4
0x01C1 1100
0x01C1 1104
0x01C1 1110
0x01C1 1114
0x01C1 1118
0x01C1 111C
0x01C1 1120
0x01C1 1124
0x01C1 1128
0x01C1 1138
0x01C1 113C
0x01C1 1140
0x01C1 1144
0x01C1 1148
0x01C1 114C
0x01C1 1150
0x01C1 1160
0x01C1 1164
0x01C1 1168
0x01C1 116C
REVID
RSTYPE
PLLCTL
-
Revision Identification Register
Reset Type Status Register
PLL Control Register
Reserved
PLLM
PLL Multiplier Control Register
PLL Pre-Divider Control Register
PLL Controller Divider 1 Register
PLL Controller Divider 2 Register
PLL Controller Divider 3 Register
Reserved
PREDIV
PLLDIV1
PLLDIV2
PLLDIV3
-
POSTDIV
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
CKEN
PLL Post-Divider Control Register
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Clock Enable Control Register
Clock Status Register
CKSTAT
SYSTAT
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
SYSCLK Status Register
PLL Controller Divider 4 Register
PLL Controller Divider 5 Register
PLL Controller Divider 6 Register
PLL Controller Divider 7 Register
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6.8 Interrupts
6.8.1 ARM CPU Interrupts
The ARM9 CPU core supports 2 direct interrupts: FIQ and IRQ. The ARM Interrupt Controller extends the
number of interrupts to 100, and provides features like programmable masking, priority, hardware nesting
support, and interrupt vector generation.
6.8.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
The ARM Interrupt controller organizes interrupts into the following hierarchy:
•
Peripheral Interrupt Requests
Individual Interrupt Sources from Peripherals
100 System Interrupts
–
•
–
One or more Peripheral Interrupt Requests are combined (fixed configuration) to generate a
System Interrupt.
–
After prioritization, the AINTC will provide an interrupt vector based unique to each System Interrupt
•
32 Interrupt Channels
–
–
Each System Interrupt is mapped to one of the 32 Interrupt Channels
Channel Number determines the first level of prioritization, Channel 0 is highest priority and 31
lowest.
–
If more than one system interrupt is mapped to a channel, priority within the channel is determined
by system interrupt number (0 highest priority)
•
•
Host Interrupts (FIQ and IRQ)
–
–
Interrupt Channels 0 and 1 generate the ARM FIQ interrupt
Interrupt Channels 2 through 31 Generate the ARM IRQ interrupt
Debug Interrupts
–
–
Two Debug Interrupts are supported and can be used to trigger events in the debug subsystem
Sources can be selected from any of the System Interrupts or Host Interrupts
6.8.1.2 AINTC Hardware Vector Generation
The AINTC also generates an interrupt vector in hardware for both IRQ and FIQ host interrupts. This may
be used to accelerate interrupt dispatch. A unique vector is generated for each of the 100 system
interrupts. The vector is computed in hardware as:
VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE)
Where BASE and SIZE are programmable. The computed vector is a 32-bit address which may
dispatched to using a single instruction of type LDR PC, [PC, #-<offset_12>] at the FIQ and IRQ vector
locations (0xFFFF0018 and 0xFFFF001C respectively).
6.8.1.3 AINTC Hardware Interrupt Nesting Support
Interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the CPU to
interrupt the ISR if a higher priority event occurs. The AINTC provides hardware support to facilitate
interrupt nesting. It supports both global and per host interrupt (FIQ and IRQ in this case) automatic
nesting. If enabled, the AINTC will automatically update an internal nesting register that temporarily masks
interrupts at and below the priority of the current interrupt channel. Then if the ISR re-enables interrupts;
only higher priority channels will be able to interrupt it. The nesting level is restored by the ISR by writing
to the nesting level register on completion. Support for nesting can be enabled/disabled by software, with
the option of automatic nesting on a global or per host interrupt basis; or manual nesting.
6.8.1.4 AINTC System Interrupt Assignments on the device
System Interrupt assignments for the device are listed in Table 6-7
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Table 6-7. AINTC System Interrupt Assignments
System Interrupt
Interrupt Name
Source
0
1
COMMTX
ARM
COMMRX
ARM
2
NINT
ARM
3
PRU_EVTOUT0
PRU_EVTOUT1
PRU_EVTOUT2
PRU_EVTOUT3
PRU_EVTOUT4
PRU_EVTOUT5
PRU_EVTOUT6
PRU_EVTOUT7
PRUSS Interrupt
4
PRUSS Interrupt
5
PRUSS Interrupt
6
PRUSS Interrupt
7
PRUSS Interrupt
8
PRUSS Interrupt
9
PRUSS Interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 - 31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PRUSS Interrupt
EDMA3_CC0_CCINT
EDMA3_CC0_CCERRINT
EDMA3_TC0_TCERRINT
EMIFA_INT
EDMA CC Region 0
EDMA CC
EDMA TC0
EMIFA
IIC0_INT
I2C0
MMCSD_INT0
MMCSD_INT1
PSC0_ALLINT
-
MMCSD
MMCSD
PSC0
Reserved
SPI0_INT
SPI0
T64P0_TINT12
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
-
Reserved
PROTERR
SYSCFG Protection Shared Interrupt
Reserved
-
EDMA3_TC1_TCERRINT
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
EMIF_MEMERR
GPIO_B0INT
GPIO_B1INT
GPIO_B2INT
GPIO_B3INT
GPIO_B4INT
GPIO_B5INT
GPIO_B6INT
GPIO_B7INT
EDMA TC1
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
EMIFB
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
GPIO Bank 6 Interrupt
GPIO Bank 7 Interrupt
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Table 6-7. AINTC System Interrupt Assignments (continued)
System Interrupt
Interrupt Name
Source
50
51
52
53
54
55
56
-
Reserved
IIC1_INT
I2C1
-
Reserved
UART_INT1
MCASP_INT
PSC1_ALLINT
SPI1_INT
UART1
McASP0, 1, 2 Combined RX / TX Interrupts
PSC1
SPI1
-
Reserved
58
59
USB0_INT
USB0 Interrupt
-
Reserved
60
-
Reserved
61
UART2_INT
-
UART2
62
Reserved
63
EHRPWM0
EHRPWM0TZ
EHRPWM1
EHRPWM1TZ
EHRPWM2
EHRPWM2TZ
ECAP0
HiResTimer / PWM0 Interrupt
HiResTimer / PWM0 Trip Zone Interrupt
HiResTimer / PWM1 Interrupt
HiResTimer / PWM1 Trip Zone Interrupt
HiResTimer / PWM2 Interrupt
HiResTimer / PWM2 Trip Zone Interrupt
ECAP0
64
65
66
67
68
69
70
ECAP1
ECAP1
71
ECAP2
ECAP2
72
EQEP0
EQEP0
73
EQEP1
EQEP1
74
T64P0_CMPINT0
T64P0_CMPINT1
T64P0_CMPINT2
T64P0_CMPINT3
T64P0_CMPINT4
T64P0_CMPINT5
T64P0_CMPINT6
T64P0_CMPINT7
T64P1_CMPINT0
T64P1_CMPINT1
T64P1_CMPINT2
T64P1_CMPINT3
T64P1_CMPINT4
T64P1_CMPINT5
T64P1_CMPINT6
T64P1_CMPINT7
Timer64P0 - Compare 0
Timer64P0 - Compare 1
Timer64P0 - Compare 2
Timer64P0 - Compare 3
Timer64P0 - Compare 4
Timer64P0 - Compare 5
Timer64P0 - Compare 6
Timer64P0 - Compare 7
Timer64P1 - Compare 0
Timer64P1 - Compare 1
Timer64P1 - Compare 2
Timer64P1 - Compare 3
Timer64P1 - Compare 4
Timer64P1 - Compare 5
Timer64P1 - Compare 6
Timer64P1 - Compare 7
PSC0
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
ARMCLKSTOPREQ
-
91 - 100
Reserved
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6.8.1.5 AINTC Memory Map
Table 6-8. AINTC Memory Map
BYTE ADDRESS
0xFFFE E000
ACRONYM
REGISTER DESCRIPTION
REV
Revision Register
Control Register
Reserved
0xFFFE E004
CR
0xFFFE E008 - 0xFFFE E00F
0xFFFE E010
-
GER
Global Enable Register
Reserved
0xFFFE E014 - 0xFFFE E01B
0xFFFE E01C
-
GNLR
Global Nesting Level Register
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E020
SISR
0xFFFE E024
SICR
0xFFFE E028
EISR
0xFFFE E02C
EICR
0xFFFE E030
-
0xFFFE E034
HIEISR
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E038
HIEICR
0xFFFE E03C - 0xFFFE E04F
0xFFFE E050
-
VBR
Vector Base Register
0xFFFE E054
VSR
Vector Size Register
0xFFFE E058
VNR
Vector Null Register
0xFFFE E05C - 0xFFFE E07F
0xFFFE E080
-
Reserved
GPIR
Global Prioritized Index Register
Global Prioritized Vector Register
Reserved
0xFFFE E084
GPVR
0xFFFE E088 - 0xFFFE E1FF
0xFFFE E200 - 0xFFFE E20B
0xFFFE E20C- 0xFFFE E27F
0xFFFE E280 - 0xFFFE E28B
0xFFFE E28C - 0xFFFE E2FF
0xFFFE E300 - 0xFFFE E30B
0xFFFE E30C - 0xFFFE E37F
0xFFFE E380 - 0xFFFE E38B
0xFFFE E38C - 0xFFFE E3FF
0xFFFE E400 - 0xFFFE E458
0xFFFE E459 - 0xFFFE E7FF
0xFFFE E800 - 0xFFFE E81F
0xFFFE E820 - 0xFFFE E8FF
0xFFFE E900 - 0xFFFE E904
0xFFFE E908 - 0xFFFE EEFF
0xFFFE EF00 - 0xFFFE EF04
0xFFFE EF08 - 0xFFFE F0FF
0xFFFE F100 - 0xFFFE F104
0xFFFE F108 - 0xFFFE F4FF
0xFFFE F500
-
SRSR[1] - SRSR[3]
System Interrupt Status Raw / Set Registers
Reserved
-
SECR[1] - SECR[3]
System Interrupt Status Enabled / Clear Registers
Reserved
-
ESR[1] - ESR[3]
System Interrupt Enable Set Registers
Reserved
-
ECR[1] - ECR[3]
System Interrupt Enable Clear Registers
Reserved
-
CMR[0] - CMR[22]
Channel Map Registers (Byte Wide Registers)
Reserved
-
-
Reserved
-
Reserved
HIPIR[1] - HIPIR[2]
Host Interrupt Prioritized Index Registers
Reserved
-
-
-
Reserved
Reserved
HINLR[1] - HINLR[2] Host Interrupt Nesting Level Registers
-
Reserved
HIER[0]
-
Host Interrupt Enable Register
Reserved
0xFFFE F504 - 0xFFFE F5FF
0xFFFE F600
HIPVR[1] - HIPVR[2] Host Interrupt Prioritized Vector Registers
Reserved
0xFFFE F608 - 0xFFFE FFFF
-
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6.9 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The device GPIO peripheral supports the following:
•
External Interrupt and DMA request Capability
–
–
–
–
–
Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
which pin(s) have triggered the interrupt.
GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to ARM INTC Interrupt Requests 42, 43,
44, 45, 46, 47, 48, and 49 respectively
Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,
and 29 respectively.
•
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-9.
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6.9.1 GPIO Register Description(s)
Table 6-9. GPIO Registers
BYTE ADDRESS
0x01E2 6000
0x01E2 6004
0x01E2 6008
ACRONYM
REGISTER DESCRIPTION
REV
Peripheral Revision Register
RESERVED
BINTEN
Reserved
GPIO Interrupt Per-Bank Enable Register
GPIO BANKS 0 AND 1
0x01E2 6010
0x01E2 6014
0x01E2 6018
0x01E2 601C
0x01E2 6020
0x01E2 6024
0x01E2 6028
0x01E2 602C
0x01E2 6030
0x01E2 6034
DIR01
GPIO Banks 0 and 1 Direction Register
OUT_DATA01
SET_DATA01
CLR_DATA01
IN_DATA01
GPIO Banks 0 and 1 Output Data Register
GPIO Banks 0 and 1 Set Data Register
GPIO Banks 0 and 1 Clear Data Register
GPIO Banks 0 and 1 Input Data Register
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
GPIO Banks 0 and 1 Interrupt Status Register
GPIO BANKS 2 AND 3
SET_RIS_TRIG01
CLR_RIS_TRIG01
SET_FAL_TRIG01
CLR_FAL_TRIG01
INTSTAT01
0x01E2 6038
0x01E2 603C
0x01E2 6040
0x01E2 6044
0x01E2 6048
0x01E2 604C
0x01E2 6050
0x01E2 6054
0x01E2 6058
0x01E2 605C
DIR23
GPIO Banks 2 and 3 Direction Register
OUT_DATA23
SET_DATA23
CLR_DATA23
IN_DATA23
GPIO Banks 2 and 3 Output Data Register
GPIO Banks 2 and 3 Set Data Register
GPIO Banks 2 and 3 Clear Data Register
GPIO Banks 2 and 3 Input Data Register
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
GPIO Banks 2 and 3 Interrupt Status Register
GPIO BANKS 4 AND 5
SET_RIS_TRIG23
CLR_RIS_TRIG23
SET_FAL_TRIG23
CLR_FAL_TRIG23
INTSTAT23
0x01E2 6060
0x01E2 6064
0x01E2 6068
0x01E2 606C
0x01E2 6070
0x01E2 6074
0x01E2 6078
0x01E2 607C
0x01E2 6080
0x01E2 6084
DIR45
GPIO Banks 4 and 5 Direction Register
OUT_DATA45
SET_DATA45
CLR_DATA45
IN_DATA45
GPIO Banks 4 and 5 Output Data Register
GPIO Banks 4 and 5 Set Data Register
GPIO Banks 4 and 5 Clear Data Register
GPIO Banks 4 and 5 Input Data Register
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
GPIO Banks 4 and 5 Interrupt Status Register
GPIO BANKS 6 AND 7
SET_RIS_TRIG45
CLR_RIS_TRIG45
SET_FAL_TRIG45
CLR_FAL_TRIG45
INTSTAT45
0x01E2 6088
0x01E2 608C
0x01E2 6090
0x01E2 6094
0x01E2 6098
0x01E2 609C
0x01E2 60A0
0x01E2 60A4
DIR67
GPIO Banks 6 and 7 Direction Register
OUT_DATA67
SET_DATA67
CLR_DATA67
IN_DATA67
GPIO Banks 6 and 7 Output Data Register
GPIO Banks 6 and 7 Set Data Register
GPIO Banks 6 and 7 Clear Data Register
GPIO Banks 6 and 7 Input Data Register
GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
SET_RIS_TRIG67
CLR_RIS_TRIG67
SET_FAL_TRIG67
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Table 6-9. GPIO Registers (continued)
BYTE ADDRESS
0x01E2 60A8
ACRONYM
CLR_FAL_TRIG67
INTSTAT67
REGISTER DESCRIPTION
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
GPIO Banks 6 and 7 Interrupt Status Register
0x01E2 60AC
6.9.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-10. Timing Requirements for GPIO Inputs(1) (see Figure 6-10)
No.
1
PARAMETER
Pulse duration, GPn[m] as input high
Pulse duration, GPn[m] as input low
MIN
MAX
UNIT
ns
tw(GPIH)
tw(GPIL)
2C(1) (2)
2C(1) (2)
2
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device
enough time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
Table 6-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-10)
No.
3
PARAMETER
Pulse duration, GPn[m] as output high
Pulse duration, GPn[m] as output low
MIN
MAX
UNIT
ns
tw(GPOH)
tw(GPOL)
2C(1) (2)
2C(1) (2)
4
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C=SYSCLK4 period in ns.
2
1
GPn[m] as input
4
3
GPn[m] as output
Figure 6-10. GPIO Port Timing
6.9.3 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-12. Timing Requirements for External Interrupts(1) (see Figure 6-11)
No.
1
PARAMETER
MIN
2C(1) (2)
MAX
UNIT
ns
tw(ILOW)
tw(IHIGH)
Width of the external interrupt pulse low
Width of the external interrupt pulse high
(1) (2)
2
2C
ns
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have device recognize the
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to
access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
2
1
GPn[m] as input
Figure 6-11. GPIO External Interrupt Timing
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6.10 EDMA
Table 6-13 is the list of EDMA3 Channel Contoller Registers and Table 6-14 is the list of EDMA3 Transfer
Controller registers.
Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
0x01C0 0000
ACRONYM
PID
REGISTER DESCRIPTION
Peripheral Identification Register
0x01C0 0004
CCCFG
EDMA3CC Configuration Register
GLOBAL REGISTERS
0x01C0 0200
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0240
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0260
0x01C0 0284
0x01C0 0300
0x01C0 0308
0x01C0 0310
0x01C0 0314
0x01C0 0318
0x01C0 031C
0x01C0 0320
0x01C0 0340
0x01C0 0348
0x01C0 0350
0x01C0 0358
0x01C0 0380
0x01C0 0384
0x01C0 0388
0x01C0 038C
0x01C0 0400 - 0x01C0 043C
0x01C0 0440 - 0x01C0 047C
0x01C0 0600
0x01C0 0604
0x01C0 0620
0x01C0 0640
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
QDMAQNUM
QUEPRI
QDMA Channel 0 Mapping Register
QDMA Channel 1 Mapping Register
QDMA Channel 2 Mapping Register
QDMA Channel 3 Mapping Register
QDMA Channel 4 Mapping Register
QDMA Channel 5 Mapping Register
QDMA Channel 6 Mapping Register
QDMA Channel 7 Mapping Register
DMA Channel Queue Number Register 0
DMA Channel Queue Number Register 1
DMA Channel Queue Number Register 2
DMA Channel Queue Number Register 3
QDMA Channel Queue Number Register
Queue Priority Register(1)
EMR
Event Missed Register
EMCR
Event Missed Clear Register
QEMR
QDMA Event Missed Register
QEMCR
QDMA Event Missed Clear Register
EDMA3CC Error Register
CCERR
CCERRCLR
EEVAL
EDMA3CC Error Clear Register
Error Evaluate Register
DRAE0
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
Event Queue Entry Registers Q0E0-Q0E15
Event Queue Entry Registers Q1E0-Q1E15
Queue 0 Status Register
DRAE1
DRAE2
DRAE3
QRAE0
QRAE1
QRAE2
QRAE3
Q0E0-Q0E15
Q1E0-Q1E15
QSTAT0
QSTAT1
Queue 1 Status Register
QWMTHRA
CCSTAT
Queue Watermark Threshold A Register
EDMA3CC Status Register
GLOBAL CHANNEL REGISTERS
Event Register
0x01C0 1000
0x01C0 1008
ER
ECR
Event Clear Register
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC
memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
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Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
0x01C0 1010
0x01C0 1018
0x01C0 1020
0x01C0 1028
0x01C0 1030
0x01C0 1038
0x01C0 1040
0x01C0 1050
0x01C0 1058
0x01C0 1060
0x01C0 1068
0x01C0 1070
0x01C0 1078
0x01C0 1080
0x01C0 1084
0x01C0 1088
0x01C0 108C
0x01C0 1090
0x01C0 1094
ACRONYM
ESR
REGISTER DESCRIPTION
Event Set Register
CER
Chained Event Register
Event Enable Register
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
EER
EECR
EESR
SER
SECR
IER
Secondary Event Clear Register
Interrupt Enable Register
IECR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
IESR
IPR
ICR
Interrupt Clear Register
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
SHADOW REGION 0 CHANNEL REGISTERS
Event Register
0x01C0 2000
0x01C0 2008
0x01C0 2010
0x01C0 2018
0x01C0 2020
0x01C0 2028
0x01C0 2030
0x01C0 2038
0x01C0 2040
0x01C0 2050
0x01C0 2058
0x01C0 2060
0x01C0 2068
0x01C0 2070
0x01C0 2078
0x01C0 2080
0x01C0 2084
0x01C0 2088
0x01C0 208C
0x01C0 2090
0x01C0 2094
ER
ECR
Event Clear Register
ESR
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
SECR
IER
IECR
IESR
IPR
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
SHADOW REGION 1 CHANNEL REGISTERS
Event Register
0x01C0 2200
0x01C0 2208
0x01C0 2210
0x01C0 2218
0x01C0 2220
ER
ECR
ESR
CER
EER
Event Clear Register
Event Set Register
Chained Event Register
Event Enable Register
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Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
ACRONYM
EECR
EESR
SER
REGISTER DESCRIPTION
0x01C0 2228
0x01C0 2230
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
0x01C0 2238
0x01C0 2240
SECR
IER
Secondary Event Clear Register
Interrupt Enable Register
0x01C0 2250
0x01C0 2258
IECR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
0x01C0 2260
IESR
0x01C0 2268
IPR
0x01C0 2270
ICR
Interrupt Clear Register
0x01C0 2278
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
0x01C0 2280
0x01C0 2284
QEER
QEECR
QEESR
QSER
QSECR
—
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
0x01C0 2288
0x01C0 228C
0x01C0 2290
0x01C0 2294
QDMA Secondary Event Clear Register
Parameter RAM (PaRAM)
0x01C0 4000 - 0x01C0 4FFF
Table 6-14. EDMA3 Transfer Controller (EDMA3TC) Registers
TRANSFER
TRANSFER
CONTROLLER 0
BYTE ADDRESS
CONTROLLER 1
ACRONYM
REGISTER DESCRIPTION
Peripheral Identification Register
BYTE ADDRESS
0x01C0 8400
0x01C0 8404
0x01C0 8500
0x01C0 8520
0x01C0 8524
0x01C0 8528
0x01C0 852C
0x01C0 8530
0x01C0 8540
0x01C0 8640
0x01C0 8644
0x01C0 8648
0x01C0 864C
0x01C0 8650
0x01C0 8654
0x01C0 8658
0x01C0 865C
0x01C0 8660
0x01C0 8680
0x01C0 8684
0x01C0 8688
0x01C0 8700
0x01C0 8704
0x01C0 8708
0x01C0 870C
0x01C0 8000
0x01C0 8004
0x01C0 8100
0x01C0 8120
0x01C0 8124
0x01C0 8128
0x01C0 812C
0x01C0 8130
0x01C0 8140
0x01C0 8240
0x01C0 8244
0x01C0 8248
0x01C0 824C
0x01C0 8250
0x01C0 8254
0x01C0 8258
0x01C0 825C
0x01C0 8260
0x01C0 8280
0x01C0 8284
0x01C0 8288
0x01C0 8300
0x01C0 8304
0x01C0 8308
0x01C0 830C
PID
TCCFG
EDMA3TC Configuration Register
TCSTAT
EDMA3TC Channel Status Register
Error Status Register
ERRSTAT
ERREN
Error Enable Register
ERRCLR
ERRDET
ERRCMD
RDRATE
SAOPT
Error Clear Register
Error Details Register
Error Interrupt Command Register
Read Command Rate Register
Source Active Options Register
SASRC
Source Active Source Address Register
Source Active Count Register
SACNT
SADST
Source Active Destination Address Register
Source Active B-Index Register
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
DFCNTRLD
DFSRCBREF
DFDSTBREF
DFOPT0
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Destination FIFO Set Count Reload Register
Destination FIFO Set Source Address B-Reference Register
Destination FIFO Set Destination Address B-Reference Register
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
DFSRC0
DFCNT0
DFDST0
Destination FIFO Destination Address Register 0
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Table 6-14. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)
TRANSFER
CONTROLLER 0
BYTE ADDRESS
TRANSFER
CONTROLLER 1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01C0 8710
0x01C0 8714
0x01C0 8740
0x01C0 8744
0x01C0 8748
0x01C0 874C
0x01C0 8750
0x01C0 8754
0x01C0 8780
0x01C0 8784
0x01C0 8788
0x01C0 878C
0x01C0 8790
0x01C0 8794
0x01C0 87C0
0x01C0 87C4
0x01C0 87C8
0x01C0 87CC
0x01C0 87D0
0x01C0 87D4
0x01C0 8310
0x01C0 8314
0x01C0 8340
0x01C0 8344
0x01C0 8348
0x01C0 834C
0x01C0 8350
0x01C0 8354
0x01C0 8380
0x01C0 8384
0x01C0 8388
0x01C0 838C
0x01C0 8390
0x01C0 8394
0x01C0 83C0
0x01C0 83C4
0x01C0 83C8
0x01C0 83CC
0x01C0 83D0
0x01C0 83D4
DFBIDX0
DFMPPRXY0
DFOPT1
Destination FIFO B-Index Register 0
Destination FIFO Memory Protection Proxy Register 0
Destination FIFO Options Register 1
DFSRC1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
DFCNT1
DFDST1
Destination FIFO Destination Address Register 1
Destination FIFO B-Index Register 1
DFBIDX1
DFMPPRXY1
DFOPT2
Destination FIFO Memory Protection Proxy Register 1
Destination FIFO Options Register 2
DFSRC2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
DFCNT2
DFDST2
Destination FIFO Destination Address Register 2
Destination FIFO B-Index Register 2
DFBIDX2
DFMPPRXY2
DFOPT3
Destination FIFO Memory Protection Proxy Register 2
Destination FIFO Options Register 3
DFSRC3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
DFCNT3
DFDST3
Destination FIFO Destination Address Register 3
Destination FIFO B-Index Register 3
DFBIDX3
DFMPPRXY3
Destination FIFO Memory Protection Proxy Register 3
Table 6-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-16 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 6-15. EDMA Parameter Set RAM
BYTE ADDRESS
0x01C0 4000 - 0x01C0 401F
0x01C0 4020 - 0x01C0 403F
0x01C0 4040 - 0x01C0 405F
0x01C0 4060 - 0x01C0 407F
0x01C0 4080 - 0x01C0 409F
0x01C0 40A0 - 0x01C0 40BF
...
DESCRIPTION
Parameters Set 0 (8 32-bit words)
Parameters Set 1 (8 32-bit words)
Parameters Set 2 (8 32-bit words)
Parameters Set 3 (8 32-bit words)
Parameters Set 4 (8 32-bit words)
Parameters Set 5 (8 32-bit words)
...
0x01C0 4FC0 - 0x01C0 4FDF
0x01C0 4FE0 - 0x01C0 4FFF
Parameters Set 126 (8 32-bit words)
Parameters Set 127 (8 32-bit words)
Table 6-16. Parameter Set Entries
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
OPT
SRC
Option
Source Address
A_B_CNT
DST
A Count, B Count
Destination Address
SRC_DST_BIDX
LINK_BCNTRLD
Source B Index, Destination B Index
Link Address, B Count Reload
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Table 6-16. Parameter Set Entries (continued)
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0018
0x001C
SRC_DST_CIDX
CCNT
Source C Index, Destination C Index
C Count
Table 6-17. EDMA Events
Event
Event Name / Source
McASP0 Receive
Event
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Event Name / Source
MMCSD Receive
MMCSD Transmit
SPI1 Receive
0
1
McASP0 Transmit
McASP1 Receive
McASP1 Transmit
Reserved
2
3
SPI1 Transmit
4
PRU_EVTOUT6
PRU_EVTOUT7
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
I2C0 Receive
5
Reserved
6
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
UART0 Receive
UART0 Transmit
Timer64P0 Event Out 12
Timer64P0 Event Out 34
UART1 Receive
UART1 Transmit
SPI0 Receive
7
8
9
I2C0 Transmit
10
11
12
13
14
15
I2C1 Receive
I2C1 Transmit
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
UART2 Receive
UART2 Transmit
SPI0 Transmit
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6.11 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the device . It supports asynchronous
memory types, such as NAND and NOR flash and Asynchronous SRAM.
6.11.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
•
•
•
SRAM memories
NAND Flash memories
NOR Flash memories
The device supports up to 13 address lines and an external wait/interrupt input. Up to 2 asynchronous
chip selects are supported by EMIFA (EMA_CS[3:2]) .
Each chip select has the following individually programmable attributes:
•
•
•
•
•
•
•
Data Bus Width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Extended Wait Option With Programmable Timeout
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
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6.11.2 External Memory Interface A (EMIFA) Registers
Table 6-18 is a list of the EMIF registers.
Table 6-18. External Memory Interface (EMIFA) Registers
BYTE ADDRESS
0x6800 0000
0x6800 0004
0x6800 0008
0x6800 000C
0x6800 0010
0x6800 0014
0x6800 0018
0x6800 001C
0x6800 0020
0x6800 003C
0x6800 0040
0x6800 0044
0x6800 0048
0x6800 004C
0x6800 0060
0x6800 0064
0x6800 0070
0x6800 0074
0x6800 0078
0x6800 007C
0x6800 00BC
0x6800 00C0
0x6800 00C4
0x6800 00C8
0x6800 00CC
0x6800 00D0
0x6800 00D4
0x6800 00D8
0x6800 00DC
ACRONYM
MIDR
REGISTER DESCRIPTION
Module ID Register
AWCC
Asynchronous Wait Cycle Configuration Register
Reserved
-
-
Reserved
CE2CFG
CE3CFG
CE4CFG
CE5CFG
-
Asynchronous 1 Configuration Register
Asynchronous 2 Configuration Register
Asynchronous 3 Configuration Register
Asynchronous 4 Configuration Register
Reserved
-
Reserved
INTRAW
INTMSK
INTMSKSET
INTMSKCLR
NANDFCR
NANDFSR
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
EMIFA Interrupt Raw Register
EMIFA Interrupt Mask Register
EMIFA Interrupt Mask Set Register
EMIFA Interrupt Mask Clear Register
NAND Flash Control Register
NAND Flash Status Register
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
NAND4BITECCLOAD NAND Flash 4-Bit ECC Load Register
NAND4BITECC1
NAND4BITECC2
NAND4BITECC3
NAND4BITECC4
NANDERRADD1
NANDERRADD2
NANDERRVAL1
NANDERRVAL2
NAND Flash 4-Bit ECC Register 1
NAND Flash 4-Bit ECC Register 2
NAND Flash 4-Bit ECC Register 3
NAND Flash 4-Bit ECC Register 4
NAND Flash 4-Bit ECC Error Address Register 1
NAND Flash 4-Bit ECC Error Address Register 2
NAND Flash 4-Bit ECC Error Value Register 1
NAND Flash 4-Bit ECC Error Value Register 2
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6.11.3 EMIFA Electrical Data/Timing
The following assume testing over recommended operating conditions.
Table 6-19. EMIFA Asynchronous Memory Timing Requirements(1)
No. PARAMETER
MIN
NOM
MAX
UNIT
READS and WRITES
Cycle time, EMIFA module clock
E
2
tc(CLK)
10
2E
ns
ns
Pulse duration, EM_WAIT assertion and
deassertion
tw(EM_WAIT)
READS
Setup time, EM_D[15:0] valid before EM_OE
high
12
13
14
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
tsu (EMOEL-EMWAIT)
3
0
ns
ns
ns
Hold time, EM_D[15:0] valid after EM_OE high
Setup Time, EM_WAIT asserted before end of
Strobe Phase(2)
4E+3
WRITES
Setup Time, EM_WAIT asserted before end of
Strobe Phase(2)
28
tsu (EMWEL-EMWAIT)
4E+3
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-14 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 6-20. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3)
No.
PARAMETER
MIN
READS and WRITES
(TA)*E - 3
NOM
MAX
UNIT
1
td(TURNAROUND) Turn around time
(TA)*E
(TA)*E + 3
ns
READS
(RS+RST+RH)*E
- 3
(RS+RST+RH)*E
+ 3
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
tc(EMRCYCLE)
(RS+RST+RH+(E (RS+RST+RH+(EW (RS+RST+RH+(
EMIF read cycle time (EW = 1)
WC*16))*E - 3
C*16))*E EWC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 0)
(RS)*E-3
(RS)*E
0
(RS)*E+3
+3
tsu(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 1)
-3
(RH)*E - 3
-3
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 0)
(RH)*E
0
(RH)*E + 3
+3
th(EMOEH-EMCEH)
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
EMA_OE low
6
7
8
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
(RS)*E-3
(RH)*E-3
(RS)*E-3
(RS)*E
(RH)*E
(RS)*E
(RS)*E+3
(RH)*E+3
(RS)*E+3
Output hold time, EMA_OE high to
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
EMA_OE low
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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(1) (2) (3)
Table 6-20. EMIFA Asynchronous Memory Switching Characteristics
(continued)
PARAMETER
MIN
NOM
MAX
UNIT
ns
Output hold time, EMA_OE high to
EMA_A[13:0] invalid
9
th(EMOEH-EMAIV)
(RH)*E-3
(RH)*E
(RH)*E+3
EMA_OE active low width (EW = 0)
(RST)*E-3
(RST)*E
(RST)*E+3
ns
10
11
tw(EMOEL)
(RST+(EWC*16))*
E-3
(RST+(EWC*16)
)*E+3
EMA_OE active low width (EW = 1)
(RST+(EWC*16))*E
ns
td(EMWAITH-
EMOEH)
Delay time from EMA_WAIT deasserted to
EMA_OE high
3E-3
4E
4E+3
ns
WRITES
(WS+WST+WH)*
E-3
(WS+WST+WH)*
E+3
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
16
17
tc(EMWCYCLE)
(WS+WST+WH+(
EWC*16))*E - 3
(WS+WST+WH+(E (WS+WST+WH+
WC*16))*E (EWC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 0)
(WS)*E - 3
-3
(WS)*E
0
(WS)*E + 3
+3
tsu(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 1)
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 0)
(WH)*E-3
-3
(WH)*E
0
(WH)*E+3
+3
th(EMWEH-EMCEH)
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 1)
tsu(EMDQMV-
EMWEL)
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
18
19
20
21
22
23
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
th(EMWEH-
EMDQMIV)
tsu(EMBAV-
EMWEL)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
Output setup time, EMA_A[13:0] valid to
EMA_WE low
Output hold time, EMA_WE high to
EMA_A[13:0] invalid
(WH)*E-3
(WH)*E
(WST)*E
(WH)*E+3
ns
ns
ns
EMA_WE active low width (EW = 0)
(WST)*E-3
(WST)*E+3
24
tw(EMWEL)
(WST+(EWC*16))
*E-3
(WST+(EWC*16)
)*E+3
EMA_WE active low width (EW = 1)
(WST+(EWC*16))*E
td(EMWAITH-
EMWEH)
Delay time from EMA_WAIT deasserted to
EMA_WE high
25
26
27
3E-3
(WS)*E-3
(WH)*E-3
4E
(WS)*E
(WH)*E
4E+3
(WS)*E+3
(WH)*E+3
ns
ns
ns
Output setup time, EMA_D[15:0] valid to
EMA_WE low
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Output hold time, EMA_WE high to
EMA_D[15:0] invalid
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3
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
4
8
5
9
6
7
29
30
10
EMA_OE
13
12
EMA_D[15:0]
EMA_WE
Figure 6-12. Asynchronous Memory Read Timing for EMIFA
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15
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
16
18
17
19
21
23
32
20
22
31
24
EMA_WE
26
27
EMA_D[15:0]
EMA_OE
Figure 6-13. Asynchronous Memory Write Timing for EMIFA
SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
14
11
EMA_OE
2
2
EMA_WAIT
Asserted
Deasserted
Figure 6-14. EMA_WAIT Read Timing Requirements
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Figure 6-15. EMA_WAIT Write Timing Requirements
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6.12 External Memory Interface B (EMIFB)
The following EMIFB Functional Block Diagram illustrates a high-level view of the EMIFB and its
connections within the device. Multiple requesters have access to EMIFB through a switched central
resource (indicated as crossbar in the figure). The EMIFB implements a split transaction internal bus,
allowing concurrence between reads and writes from the various requesters.
EMIFB
Registers
CPU
EMB_CS
EMB_CAS
EDMA
Cmd/Write
FIFO
EMB_RAS
EMB_WE
Crossbar
Master
Peripherals
EMB_CLK
SDRAM
Interface
EMB_SDCKE
EMB_BA[1:0]
EMB_A[x:0]
Read
FIFO
EMB_D[x:0]
EMB_WE_DQM[x:0]
Figure 6-16. EMIFB Functional Block Diagram
EMIFB supports a 3.3V LVCMOS Interface.
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6.12.1 Interfacing to SDRAM
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
•
•
•
•
Pre-charge bit is A[10]
Supports 8, 9, 10 or 11 column address bits
Supports up to 13 row address bits
Supports 1, 2 or 4 internal banks
Table 6-21 shows the supported SDRAM configurations for EMIFB.
Table 6-21. EMIFB Supported SDRAM Configurations(1)
SDRAM
Memory
Data Bus
Width
Memory
Density
(Mbits)
Number of EMIFB Data
Total Memory
(Mbits)
Total Memory
(Mbytes)
Rows
Columns
Banks
Memories
Bus Size
(bits)
2
2
2
2
2
2
2
2
2
2
2
2
32
32
32
32
32
32
32
32
32
32
32
32
13
13
13
13
13
13
13
13
13
13
13
13
8
8
1
2
4
1
2
4
1
2
4
1
2
4
64
128
256
128
256
512
256
512
1024
512
1024
2048
8
32
64
16
8
32
128
64
9
16
9
32
128
256
128
256
512
256
512
1024
9
64
16
10
10
10
11
11
11
32
64
128
64
128
256
(1) The shaded cells indicate configurations that are possible on the EMIFB interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
Figure 6-17 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. Figure 6-18
shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to Table 6-22,
as an example that shows additional list of commonly-supported SDRAM devices and the required
connections for the address pins. Note that in Table 6-22, page size/column size (not indicated in the
table) is varied to get the required addressability range.
SDRAM
2M x 16 x 4
Bank
EMIFB
EMB_CS
CE
EMB_CAS
EMB_RAS
CAS
RAS
WE
EMB_WE
EMB_CLK
CLK
CKE
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
Figure 6-17. EMIFB to 2M × 16 × 4 bank SDRAM Interface
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SDRAM
4M x 16 x 4
Bank
EMIFB
EMB_CS
CE
EMB_CAS
EMB_RAS
CAS
RAS
WE
EMB_WE
EMB_CLK
CLK
CKE
EMB_SDCKE
EMB_BA[1:0]
EMB_A[12:0]
BA[1:0]
A[12:0]
LDQM
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
UDQM
DQ[15:0]
EMB_WE_DQM[2]
EMB_WE_DQM[3]
EMB_D[31:16]
SDRAM
4M x 16 x 4
Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
Figure 6-18. EMIFB to Dual 4M × 16 × 4 bank SDRAM Interface
Table 6-22. Example of 16-bit EMIFB Address Pin Connections
SDRAM Size
Width
Banks
Address Pins
A[11:0]
64M bits
128M bits
256M bits
512M bits
×16
4
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
EMB_A[11:0]
A[11:0]
×16
×16
×16
4
4
4
EMB_A[11:0]
A[12:0]
EMB_A[12:0]
A[12:0]
EMB_A[12:0]
Table 6-23 is a list of the EMIFB registers.
Table 6-23. EMIFB Controller Registers
BYTE ADDRESS
0xB000 0000
0xB000 0008
0xB000 000C
0xB000 0010
0xB000 0014
0xB000 001C
0xB000 0020
ACRONYM
MIDR
REGISTER DESCRIPTION
Module ID Register
SDCFG
SDRFC
SDTIM1
SDTIM2
SDCFG2
BPRIO
SDRAM Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRAM Timing Register 2
SDRAM Configuration 2 Register
Peripheral Bus Burst Priority Register
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Table 6-23. EMIFB Controller Registers (continued)
BYTE ADDRESS
0xB000 0040
0xB000 0044
0xB000 0048
0xB000 004C
0xB000 0050
0xB000 00C0
0xB000 00C4
0xB000 00C8
0xB000 00CC
ACRONYM
PC1
REGISTER DESCRIPTION
Performance Counter 1 Register
Performance Counter 2 Register
PC2
PCC
Performance Counter Configuration Register
Performance Counter Master Region Select Register
Performance Counter Time Register
Interrupt Raw Register
PCMRS
PCT
IRR
IMR
Interrupt Mask Register
IMSR
IMCR
Interrupt Mask Set Register
Interrupt Mask Clear Register
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6.12.2 EMIFB Electrical Data/Timing
Table 6-24. EMIFB SDRAM Interface Timing Requirements
No.
19
PARAMETER
MIN
0.8
MAX
MAX
UNIT
ns
tsu(DV-CLKH)
th(CLKH-DIV)
Input setup time, read data valid on EMB_D[31:0] before EMB_CLK rising
Input hold time, read data valid on EMB_D[31:0] after EMB_CLK rising
20
1.5
ns
Table 6-25. EMIFB SDRAM Interface Switching Characteristics
No.
1
PARAMETER
MIN
7.5
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(CLK)
Cycle time, EMIF clock EMB_CLK
2
tw(CLK)
Pulse width, EMIF clock EMB_CLK high or low
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
Delay time, EMB_CLK rising to EMB_CS[0] valid
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid
Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] valid
Output hold time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] invalid
Delay time, EMB_CLK rising to EMB_D[31:0] valid
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
Delay time, EMB_CLK rising to EMB_RAS valid
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
4
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
5
6
7
8
toh(CLKH-AIV)
td(CLKH-DV)
9
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
Output hold time, EMB_CLK rising to EMB_RAS invalid
Delay time, EMB_CLK rising to EMB_CAS valid
Output hold time, EMB_CLK rising to EMB_CAS invalid
Delay time, EMB_CLK rising to EMB_WE valid
Output hold time, EMB_CLK rising to EMB_WE invalid
Delay time, EMB_CLK rising to EMB_D[31:0] 3-stated
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMB_CLK
EMB_CS[0]
3
5
7
7
9
4
6
EMB_WE_DQM[3:0]
EMB_BA[1:0]
8
8
EMB_A[12:0]
10
EMB_D[31:0]
EMB_RAS
EMB_CAS
EMB_WE
11
12
13
15
16
Figure 6-19. EMIFB Basic SDRAM Write Operation
1
BASIC SDRAM
READ OPERATION
2
2
EMB_CLK
EMB_CS[0]
3
5
7
7
4
6
EMB_WE_DQM[3:0]
EMB_BA[1:0]
8
8
EMB_A[12:0]
19
20
2 EM_CLK Delay
17
18
EMB_D[31:0]
EMB_RAS
11
12
13
14
EMB_CAS
EMB_WE
Figure 6-20. EMIFB Basic SDRAM Read Operation
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6.13 Memory Protection Units
The MPU performs memory protection checking. It receives requests from a bus master in the system and
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails
the protection check) then the MPU does not pass the transfer to the output bus but rather services the
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as
well as generating an interrupt about the fault. The following features are supported by the MPU:
•
•
•
•
•
•
•
Provides memory protection for fixed and programmable address ranges.
Supports multiple programmable address region.
Supports secure and debug access privileges.
Supports read, write, and execute access privileges.
Supports privid(8) associations with ranges.
Generates an interrupt when there is a protection violation, and saves violating transfer parameters.
MMR access is also protected.
Table 6-26. MPU1 Configuration Registers
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 4000
REVID
CONFIG
Revision ID
0x01E1 4004
Configuration
0x01E1 4010
IRAWSTAT
IENSTAT
Interrupt raw status/set
0x01E1 4014
Interrupt enable status/clear
0x01E1 4018
IENSET
Interrupt enable
0x01E1 401C
IENCLR
Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF
0x01E1 4200
-
Reserved
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
-
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Reserved
0x01E1 4204
0x01E1 4208
0x01E1 420C - 0x01E1 420F
0x01E1 4210
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
-
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Reserved
0x01E1 4214
0x01E1 4218
0x01E1 421C - 0x01E1 421F
0x01E1 4220
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
-
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Reserved
0x01E1 4224
0x01E1 4228
0x01E1 422C - 0x01E1 422F
0x01E1 4230
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
-
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Reserved
0x01E1 4234
0x01E1 4238
0x01E1 423C - 0x01E1 423F
0x01E1 4240
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
-
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Reserved
0x01E1 4244
0x01E1 4248
0x01E1 424C - 0x01E1 424F
0x01E1 4250
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
-
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Reserved
0x01E1 4254
0x01E1 4258
0x01E1 425C - 0x01E1 42FF
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Table 6-26. MPU1 Configuration Registers (continued)
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E14300
0x01E1 4304
FLTADDRR
FLTSTAT
FLTCLR
-
Fault address
Fault status
Fault clear
Reserved
0x01E1 4308
0x01E1 430C - 0x01E1 4FFF
Table 6-27. MPU2 Configuration Registers
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 5000
0x01E1 5004
REVID
CONFIG
Revision ID
Configuration
0x01E1 5010
IRAWSTAT
IENSTAT
Interrupt raw status/set
0x01E1 5014
Interrupt enable status/clear
0x01E1 5018
IENSET
Interrupt enable
0x01E1 501C
IENCLR
Interrupt enable clear
0x01E1 5020 - 0x01E1 50FF
0x01E1 5100
-
Reserved
FXD_MPSAR
FXD_MPEAR
FXD_MPPA
-
Fixed range start address
0x01E1 5104
Fixed range end start address
Fixed range memory page protection attributes
Reserved
0x01E1 5108
0x01E1 510C - 0x01E1 51FF
0x01E1 5200
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
-
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Reserved
0x01E1 5204
0x01E1 5208
0x01E1 520C - 0x01E1 520F
0x01E1 5210
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
-
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Reserved
0x01E1 5214
0x01E1 5218
0x01E1 521C - 0x01E1 521F
0x01E1 5220
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
-
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Reserved
0x01E1 5224
0x01E1 5228
0x01E1 522C - 0x01E1 522F
0x01E1 5230
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
-
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Reserved
0x01E1 5234
0x01E1 5238
0x01E1 523C - 0x01E1 523F
0x01E1 5240
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
-
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Reserved
0x01E1 5244
0x01E1 5248
0x01E1 524C - 0x01E1 524F
0x01E1 5250
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
-
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Reserved
0x01E1 5254
0x01E1 5258
0x01E1 525C - 0x01E1 525F
0x01E1 5260
PROG7_MPSAR
PROG7_MPEAR
PROG7_MPPA
Programmable range 7, start address
Programmable range 7, end address
Programmable range 7, memory page protection attributes
0x01E1 5264
0x01E1 5268
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Table 6-27. MPU2 Configuration Registers (continued)
MPU1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01E1 526C - 0x01E1 526F
0x01E1 5270
-
Reserved
PROG8_MPSAR
PROG8_MPEAR
PROG8_MPPA
-
Programmable range 8, start address
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Reserved
0x01E1 5274
0x01E1 5278
0x01E1 527C - 0x01E1 527F
0x01E1 5280
PROG9_MPSAR
PROG9_MPEAR
PROG9_MPPA
-
Programmable range 9, start address
Programmable range 9, end address
Programmable range 9, memory page protection attributes
Reserved
0x01E1 5284
0x01E1 5288
0x01E1 528C - 0x01E1 528F
0x01E1 5290
PROG10_MPSAR
PROG10_MPEAR
PROG10_MPPA
-
Programmable range 10, start address
Programmable range 10, end address
Programmable range 10, memory page protection attributes
Reserved
0x01E1 5294
0x01E1 5298
0x01E1 529C - 0x01E1 529F
0x01E1 52A0
PROG11_MPSAR
PROG11_MPEAR
PROG11_MPPA
-
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Reserved
0x01E1 52A4
0x01E1 52A8
0x01E1 52AC - 0x01E1 52AF
0x01E1 52B0
PROG12_MPSAR
PROG12_MPEAR
PROG12_MPPA
-
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Reserved
0x01E1 52B4
0x01E1 52B8
0x01E1 52BC - 0x01E1 52FF
0x01E1 5300
FLTADDRR
FLTSTAT
Fault address
0x01E1 5304
Fault status
0x01E1 5308
FLTCLR
Fault clear
0x01E1 530C - 0x01E1 5FFF
-
Reserved
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6.14 MMC / SD / SDIO (MMCSD)
6.14.1 MMCSD Peripheral Description
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The device includes an MMCSD controller which is compliant with MMC V3.31, Secure Digital Part 1
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
The MMC/SD Controller has following features:
•
•
•
•
•
•
•
MultiMediaCard (MMC).
Secure Digital (SD) Memory Card.
MMC/SD protocol support.
SDIO protocol support.
Programmable clock frequency.
512 bit Read/Write FIFO to lower system overhead.
Slave EDMA transfer capability.
The device MMC/SD Controller does not support SPI mode.
6.14.2 MMCSD Peripheral Register Description(s)
Table 6-28. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
0x01C4 0000
0x01C4 0004
0x01C4 0008
0x01C4 000C
0x01C4 0010
0x01C4 0014
0x01C4 0018
0x01C4 001C
0x01C4 0020
0x01C4 0024
0x01C4 0028
0x01C4 002C
0x01C4 0030
0x01C4 0034
0x01C4 0038
0x01C4 003C
0x01C4 0040
0x01C4 0044
0x01C4 0048
0x01C4 0050
0x01C4 0064
0x01C4 0068
0x01C4 006C
0x01C4 0070
0x01C4 0074
MMCCTL
MMCCLK
MMC Control Register
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register
MMC Data Transmit Register
MMC Command Register
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR
MMCDXR
MMCCMD
MMCARGHL
MMCRSP01
MMCRSP23
MMCRSP45
MMCRSP67
MMCDRSP
MMCCIDX
SDIOCTL
MMC Argument Register
MMC Response Register 0 and 1
MMC Response Register 2 and 3
MMC Response Register 4 and 5
MMC Response Register 6 and 7
MMC Data Response Register
MMC Command Index Register
SDIO Control Register
SDIOST0
SDIO Status Register 0
SDIOIEN
SDIO Interrupt Enable Register
SDIO Interrupt Status Register
MMC FIFO Control Register
SDIOIST
MMCFIFOCTLp
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6.14.3 MMC/SD Electrical Data/Timing
Table 6-29. Timing Requirements for MMC/SD Module
(see Figure 6-22 and Figure 6-24)
No.
1
PARAMETER
MIN
3.2
1.5
3.2
1.5
MAX
UNIT
ns
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, MMCSD_CMD valid before MMCSD_CLK high
Hold time, MMCSD_CMD valid after MMCSD_CLK high
Setup time, MMCSD_DATx valid before MMCSD_CLK high
Hold time, MMCSD_DATx valid after MMCSD_CLK high
2
ns
3
ns
4
ns
Table 6-30. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 6-21 through Figure 6-24)
No.
7
PARAMETER
MIN
0
MAX
52
UNIT
MHz
KHz
ns
f(CLK)
Operating frequency, MMCSD_CLK
Identification mode frequency, MMCSD_CLK
Pulse width, MMCSD_CLK low
8
f(CLK_ID)
tW(CLKL)
tW(CLKH)
tr(CLK)
0
400
9
6.5
6.5
10
11
12
13
14
Pulse width, MMCSD_CLK high
ns
Rise time, MMCSD_CLK
3
3
ns
tf(CLK)
Fall time, MMCSD_CLK
ns
td(CLKL-CMD)
td(CLKL-DAT)
Delay time, MMCSD_CLK low to MMCSD_CMD transition
Delay time, MMCSD_CLK low to MMCSD_DATx transition
-4.5
-4.5
2.5
2
ns
ns
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10
9
7
MMCSD_CLK
13
13
13
13
START
XMIT
Valid
Valid
Valid
END
MMCSD_CMD
Figure 6-21. MMC/SD Host Command Timing
9
10
7
MMCSD_CLK
MMCSD_CMD
1
2
Valid
START
XMIT
Valid
Valid
END
Figure 6-22. MMC/SD Card Response Timing
10
9
7
MMCSD_CLK
MMCSD_DATx
14
14
14
Dx
14
START
D0
D1
END
Figure 6-23. MMC/SD Host Write Timing
9
10
7
MMCSD_CLK
MMCSD_DATx
4
4
3
3
Start
D0
D1
Dx
End
Figure 6-24. MMC/SD Host Read and Card CRC Status Timing
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6.15 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY
configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the device through a custom interface that allows
efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
6.15.1 EMAC Peripheral Register Description(s)
Table 6-31. Ethernet Media Access Controller (EMAC) Registers
BYTE ADDRESS
0x01E2 3000
0x01E2 3004
0x01E2 3008
0x01E2 3010
0x01E2 3014
0x01E2 3018
0x01E2 3080
0x01E2 3084
0x01E2 3088
0x01E2 308C
0x01E2 3090
0x01E2 3094
0x01E2 30A0
0x01E2 30A4
0x01E2 30A8
0x01E2 30AC
0x01E2 30B0
0x01E2 30B4
0x01E2 30B8
0x01E2 30BC
0x01E2 3100
0x01E2 3104
0x01E2 3108
0x01E2 310C
0x01E2 3110
0x01E2 3114
0x01E2 3120
0x01E2 3124
0x01E2 3128
0x01E2 312C
0x01E2 3130
0x01E2 3134
0x01E2 3138
0x01E2 313C
ACRONYM
TXREV
REGISTER DESCRIPTION
Transmit Revision Register
TXCONTROL
Transmit Control Register
TXTEARDOWN
Transmit Teardown Register
RXREV
Receive Revision Register
RXCONTROL
Receive Control Register
RXTEARDOWN
Receive Teardown Register
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Clear Register
MAC Input Vector Register
MACEOIVECTOR
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
MAC End Of Interrupt Vector Register
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
RXBUFFEROFFSET
RXFILTERLOWTHRESH
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
Receive Buffer Offset Register
Receive Filter Low Priority Frame Threshold Register
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
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Table 6-31. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
0x01E2 3140
0x01E2 3144
0x01E2 3148
0x01E2 314C
0x01E2 3150
0x01E2 3154
0x01E2 3158
0x01E2 315C
0x01E2 3160
0x01E2 3164
0x01E2 3168
0x01E2 316C
0x01E2 3170
0x01E2 3174
0x01E2 31D0
0x01E2 31D4
0x01E2 31D8
0x01E2 31DC
0x01E2 31E0
0x01E2 31E4
0x01E2 31E8
0x01E2 31EC
0x01E2 3200 - 0x01E2 32FC
0x01E2 3500
0x01E2 3504
0x01E2 3508
0x01E2 3600
0x01E2 3604
0x01E2 3608
0x01E2 360C
0x01E2 3610
0x01E2 3614
0x01E2 3618
0x01E2 361C
0x01E2 3620
0x01E2 3624
0x01E2 3628
0x01E2 362C
0x01E2 3630
0x01E2 3634
0x01E2 3638
0x01E2 363C
0x01E2 3640
0x01E2 3644
0x01E2 3648
0x01E2 364C
0x01E2 3650
ACRONYM
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
REGISTER DESCRIPTION
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
Emulation Control Register
FIFO Control Register
MAC Configuration Register
Soft Reset Register
MAC Source Address Low Bytes Register
MAC Source Address High Bytes Register
MAC Hash Address Register 1
MAC Hash Address Register 2
Back Off Test Register
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
TXPAUSE
Transmit Pause Timer Register
(see Table 6-32)
MACADDRLO
MACADDRHI
MACINDEX
TX0HDP
EMAC Statistics Registers
MAC Address Low Bytes Register, Used in Receive Address Matching
MAC Address High Bytes Register, Used in Receive Address Matching
MAC Index Register
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
Transmit Channel 0 Completion Pointer Register
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
TX1CP
Transmit Channel 1 Completion Pointer Register
TX2CP
Transmit Channel 2 Completion Pointer Register
TX3CP
Transmit Channel 3 Completion Pointer Register
TX4CP
Transmit Channel 4 Completion Pointer Register
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Table 6-31. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
ACRONYM
TX5CP
TX6CP
TX7CP
RX0CP
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
RX7CP
REGISTER DESCRIPTION
Transmit Channel 5 Completion Pointer Register
Transmit Channel 6 Completion Pointer Register
Transmit Channel 7 Completion Pointer Register
Receive Channel 0 Completion Pointer Register
Receive Channel 1 Completion Pointer Register
Receive Channel 2 Completion Pointer Register
Receive Channel 3 Completion Pointer Register
Receive Channel 4 Completion Pointer Register
Receive Channel 5 Completion Pointer Register
Receive Channel 6 Completion Pointer Register
Receive Channel 7 Completion Pointer Register
0x01E2 3654
0x01E2 3658
0x01E2 365C
0x01E2 3660
0x01E2 3664
0x01E2 3668
0x01E2 366C
0x01E2 3670
0x01E2 3674
0x01E2 3678
0x01E2 367C
Table 6-32. EMAC Statistics Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E2 3200
RXGOODFRAMES
Good Receive Frames Register
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
0x01E2 3204
RXBCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
0x01E2 3208
0x01E2 320C
0x01E2 3210
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Pause Receive Frames Register
Receive CRC Errors Register
(Total number of frames received with CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
0x01E2 3214
0x01E2 3218
0x01E2 321C
0x01E2 3220
RXALIGNCODEERRORS
RXOVERSIZED
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
RXJABBER
Receive Undersized Frames Register
(Total number of undersized frames received)
RXUNDERSIZED
0x01E2 3224
0x01E2 3228
0x01E2 322C
RXFRAGMENTS
RXFILTERED
Receive Frame Fragments Register
Filtered Receive Frames Register
Received QOS Filtered Frames Register
RXQOSFILTERED
Receive Octet Frames Register
(Total number of received bytes in good frames)
0x01E2 3230
0x01E2 3234
RXOCTETS
Good Transmit Frames Register
(Total number of good frames transmitted)
TXGOODFRAMES
0x01E2 3238
0x01E2 323C
0x01E2 3240
0x01E2 3244
0x01E2 3248
0x01E2 324C
0x01E2 3250
0x01E2 3254
0x01E2 3258
0x01E2 325C
0x01E2 3260
0x01E2 3264
0x01E2 3268
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
TXCOLLISION
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
FRAME64
Transmit and Receive 64 Octet Frames Register
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Table 6-32. EMAC Statistics Registers (continued)
BYTE ADDRESS
0x01E2 326C
0x01E2 3270
0x01E2 3274
0x01E2 3278
0x01E2 327C
0x01E2 3280
0x01E2 3284
0x01E2 3288
0x01E2 328C
ACRONYM
FRAME65T127
REGISTER DESCRIPTION
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns Register
Table 6-33. EMAC Control Module Registers
BYTE ADDRESS
0x01E2 2000
0x01E2 2004
0x01E2 200C
0x01E2 2010
0x01E2 2014
0x01E2 2018
0x01E2 201C
0x01E2 2020
0x01E2 2024
0x01E2 2028
0x01E2 202C
0x01E2 2030
0x01E2 2034
0x01E2 2038
0x01E2 203C
0x01E2 2040
0x01E2 2044
0x01E2 2048
0x01E2 204C
0x01E2 2050
0x01E2 2054
0x01E2 2058
0x01E2 205C
0x01E2 2060
0x01E2 2064
0x01E2 2068
0x01E2 206C
0x01E2 2070
0x01E2 2074
0x01E2 2078
0x01E2 207C
0x01E2 2080
0x01E2 2084
ACRONYM
REV
REGISTER DESCRIPTION
EMAC Control Module Revision Register
SOFTRESET
INTCONTROL
C0RXTHRESHEN
C0RXEN
EMAC Control Module Software Reset Register
EMAC Control Module Interrupt Control Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
C0TXEN
C0MISCEN
C1RXTHRESHEN
C1RXEN
C1TXEN
C1MISCEN
C2RXTHRESHEN
C2RXEN
C2TXEN
C2MISCEN
C0RXTHRESHSTAT EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
C0RXSTAT
C0TXSTAT
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
C0MISCSTAT
C1RXTHRESHSTAT EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
C1RXSTAT
C1TXSTAT
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
C1MISCSTAT
C2RXTHRESHSTAT EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
C2RXSTAT
C2TXSTAT
C2MISCSTAT
C0RXIMAX
C0TXIMAX
C1RXIMAX
C1TXIMAX
C2RXIMAX
C2TXIMAX
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register
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Table 6-34. EMAC Control Module RAM
HEX ADDRESS RANGE
0x01E2 0000 - 0x01E2 1FFF
EMAC Local Buffer Descriptor Memory
Table 6-35. RMII Timing Requirements
No.
1
PARAMETER
MIN
TYP
MAX
UNIT
ns
tc(REFCLK)
Cycle Time, REF_CLK
Pulse Width, REF_CLK High
20
2
tw(REFCLKH)
tw(REFCLKL)
7
7
4
2
4
2
4
2
13
13
ns
3
Pulse Width, REF_CLK Low
ns
6
tsu(RXD-REFCLK)
th(REFCLK-RXD)
Input Setup Time, RXD Valid before REF_CLK High
Input Hold Time, RXD Valid after REF_CLK High
ns
7
ns
8
tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before REF_CLK High
th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after REF_CLK High
ns
9
ns
10
11
tsu(RXER-REFCLK)
Input Setup Time, RXER Valid before REF_CLK High
ns
th(REFCLKR-RXER) Input Hold Time, RXER Valid after REF_CLK High
ns
Table 6-36. RMII Timing Requirements
No.
4
PARAMETER
MIN
2.5
TYP
MAX
13
UNIT
ns
td(REFCLK-TXD)
td(REFCLK-TXEN)
Output Delay Time, REF_CLK High to TXD Valid
Output Delay Time, REF_CLK High to TXEN Valid
5
2.5
13
ns
1
2
3
RMII_MHz_50_CLK
5
5
RMII_TXEN
4
RMII_TXD[1:0]
6
7
RMII_RXD[1:0]
RMII_CRS_DV
8
9
10
11
RMII_RXER
Figure 6-25. RMII Timing Diagram
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6.16 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
6.16.1 MDIO Registers
For a list of supported MDIO registers see Table 6-37 [MDIO Registers].
Table 6-37. MDIO Register Memory Map
BYTE ADDRESS
0x01E2 4000
ACRONYM
REV
REGISTER DESCRIPTION
Revision Identification Register
0x01E2 4004
CONTROL
ALIVE
MDIO Control Register
0x01E2 4008
MDIO PHY Alive Status Register
0x01E2 400C
LINK
MDIO PHY Link Status Register
0x01E2 4010
LINKINTRAW
LINKINTMASKED
–
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
0x01E2 4014
0x01E2 4018
0x01E2 4020
USERINTRAW
USERINTMASKED
USERINTMASKSET
MDIO User Command Complete Interrupt (Unmasked) Register
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
0x01E2 4024
0x01E2 4028
0x01E2 402C
USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register
0x01E2 4030 - 0x01E2 407C
0x01E2 4080
–
Reserved
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
–
MDIO User Access Register 0
MDIO User PHY Select Register 0
MDIO User Access Register 1
MDIO User PHY Select Register 1
Reserved
0x01E2 4084
0x01E2 4088
0x01E2 408C
0x01E2 4090 - 0x01E2 47FF
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6.16.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-38. Timing Requirements for MDIO Input (see Figure 6-26 and Figure 6-27)
No.
1
PARAMETER
Cycle time, MDIO_CLK
MIN
400
180
MAX
UNIT
ns
tc(MDIO_CLK)
tw(MDIO_CLK)
tt(MDIO_CLK)
2
Pulse duration, MDIO_CLK high/low
Transition time, MDIO_CLK
ns
3
5
ns
4
tsu(MDIO-MDIO_CLKH) Setup time, MDIO_D data input valid before MDIO_CLK high
th(MDIO_CLKH-MDIO) Hold time, MDIO_D data input valid after MDIO_CLK high
10
10
ns
5
ns
1
3
3
MDIO_CLK
4
5
MDIO_D
(input)
Figure 6-26. MDIO Input Timing
Table 6-39. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-27)
No.
PARAMETER
MIN
MAX
UNIT
7
td(MDIO_CLKL-MDIO)
Delay time, MDIO_CLK low to MDIO_D data output valid
0
100
ns
1
MDIO_CLK
7
MDIO_D
(output)
Figure 6-27. MDIO Output Timing
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6.17 Multichannel Audio Serial Ports (McASP0, McASP1)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
•
•
•
Flexible clock and frame sync generation logic and on-chip dividers
Up to sixteen transmit or receive data pins and serializers
Large number of serial data format options, including:
–
–
–
–
–
TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
Time slots of 8,12,16, 20, 24, 28, and 32 bits
First bit delay 0, 1, or 2 clocks
MSB or LSB first bit order
Left- or right-aligned data words within time slots
•
•
•
•
DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers
Extensive error checking and mute generation logic
All unused pins GPIO-capable
Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample
rate by making it more tolerant to DMA latency.
•
Dynamic Adjustment of Clock Dividers
–
Clock Divider Value may be changed without resetting the McASP
The three McASPs on the device are configured with the following options:
Table 6-40. McASP Configurations(1)
Module Serializers
AFIFO
DIT
Pins
64 Word RX
64 Word TX
McASP0
McASP1
16
12
N
AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0, AFSX0, AMUTE0
64 Word RX
64 Word TX
AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1, ACLKX1, AFSX1,
AMUTE1
N
(1) Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.
Pins Function
AHCLKRx Receive Master Clock
Receive Logic
Clock/Frame Generator
State Machine
Peripheral
Configuration
Bus
GIO
Control
ACLKRx
AFSRx
Receive Bit Clock
Receive Left/Right Clock or Frame Sync
The McASPs DO NOT have
dedicated AMUTEINx pins.
AMUTEINx
AMUTEx
Clock Check and
Error Detection
DIT RAM
384 C
384 U
AFSXx
ACLKXx
AHCLKXx
Transmit Left/Right Clock or Frame Sync
Transmit Bit Clock
Transmit Master Clock
Transmit Logic
Clock/Frame Generator
State Machine
Optional
Transmit
Formatter
Serializer 0
Serializer 1
AXRx[0]
AXRx[1]
Transmit/Receive Serial Data Pin
Transmit/Receive Serial Data Pin
McASP
DMA Bus
(Dedicated)
Receive
Formatter
Serializer y
AXRx[y]
Transmit/Receive Serial Data Pin
McASPx (x = 0, 1, 2)
Figure 6-28. McASP Block Diagram
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6.17.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 6-41. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 6-42
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-43. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 6-41. McASP Registers Accessed Through Peripheral Configuration Port
McASP0
BYTE
McASP1
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
0x01D0 0000 0x01D0 4000
0x01D0 0010 0x01D0 4010
0x01D0 0014 0x01D0 4014
0x01D0 0018 0x01D0 4018
0x01D0 001C 0x01D0 401C
0x01D0 001C 0x01D0 401C
0x01D0 0020 0x01D0 4020
0x01D0 0044 0x01D0 4044
0x01D0 0048 0x01D0 4048
0x01D0 004C 0x01D0 404C
0x01D0 0050 0x01D0 4050
0x01D0 0060 0x01D0 4060
REV
PFUNC
PDIR
Revision identification register
Pin function register
Pin direction register
PDOUT
PDIN
Pin data output register
Read returns: Pin data input register
Writes affect: Pin data set register (alternate write address: PDOUT)
Pin data clear register (alternate write address: PDOUT)
Global control register
PDSET
PDCLR
GBLCTL
AMUTE
DLBCTL
DITCTL
RGBLCTL
Audio mute control register
Digital loopback control register
DIT mode control register
Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows
receiver to be reset independently from transmitter
0x01D0 0064 0x01D0 4064
0x01D0 0068 0x01D0 4068
0x01D0 006C 0x01D0 406C
0x01D0 0070 0x01D0 4070
RMASK
RFMT
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
AFSRCTL
ACLKRCTL Receive clock control register
0x01D0 0074 0x01D0 4074 AHCLKRCTL Receive high-frequency clock control register
0x01D0 0078 0x01D0 4078
0x01D0 007C 0x01D0 407C
0x01D0 0080 0x01D0 4080
0x01D0 0084 0x01D0 4084
0x01D0 0088 0x01D0 4088
0x01D0 008C 0x01D0 408C
0x01D0 00A0 0x01D0 40A0
RTDM
RINTCTL
RSTAT
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
RSLOT
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
RCLKCHK
REVTCTL
XGBLCTL
Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows
transmitter to be reset independently from receiver
0x01D0 00A4 0x01D0 40A4
0x01D0 00A8 0x01D0 40A8
0x01D0 00AC 0x01D0 40AC
0x01D0 00B0 0x01D0 40B0
XMASK
XFMT
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
AFSXCTL
ACLKXCTL Transmit clock control register
0x01D0 00B4 0x01D0 40B4 AHCLKXCTL Transmit high-frequency clock control register
0x01D0 00B8 0x01D0 40B8
0x01D0 00BC 0x01D0 40BC
0x01D0 00C0 0x01D0 40C0
0x01D0 00C4 0x01D0 40C4
0x01D0 00C8 0x01D0 40C8
0x01D0 00CC 0x01D0 40CC
0x01D0 0100 0x01D0 4100
XTDM
XINTCTL
XSTAT
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
Transmitter status register
XSLOT
Current transmit TDM time slot register
Transmit clock check control register
Transmitter DMA event control register
XCLKCHK
XEVTCTL
DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0
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Table 6-41. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
BYTE
McASP1
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
0x01D0 0104 0x01D0 4104
0x01D0 0108 0x01D0 4108
0x01D0 010C 0x01D0 410C
0x01D0 0110 0x01D0 4110
0x01D0 0114 0x01D0 4114
0x01D0 0118 0x01D0 4118
0x01D0 011C 0x01D0 411C
0x01D0 0120 0x01D0 4120
0x01D0 0124 0x01D0 4124
0x01D0 0128 0x01D0 4128
0x01D0 012C 0x01D0 412C
0x01D0 0130 0x01D0 4130
0x01D0 0134 0x01D0 4134
0x01D0 0138 0x01D0 4138
0x01D0 013C 0x01D0 413C
0x01D0 0140 0x01D0 4140
0x01D0 0144 0x01D0 4144
0x01D0 0148 0x01D0 4148
0x01D0 014C 0x01D0 414C
0x01D0 0150 0x01D0 4150
0x01D0 0154 0x01D0 4154
0x01D0 0158 0x01D0 4158
0x01D0 015C 0x01D0 415C
0x01D0 0180 0x01D0 4180
0x01D0 0184 0x01D0 4184
0x01D0 0188 0x01D0 4188
0x01D0 018C 0x01D0 418C
0x01D0 0190 0x01D0 4190
0x01D0 0194 0x01D0 4194
0x01D0 0198 0x01D0 4198
0x01D0 019C 0x01D0 419C
0x01D0 01A0 0x01D0 41A0
0x01D0 01A4 0x01D0 41A4
0x01D0 01A8 0x01D0 41A8
0x01D0 01AC 0x01D0 41AC
0x01D0 01B0 0x01D0 41B0
0x01D0 01B4 0x01D0 41B4
0x01D0 01B8 0x01D0 41B8
0x01D0 01BC 0x01D0 41BC
0x01D0 0200 0x01D0 4200
0x01D0 0204 0x01D0 4204
0x01D0 0208 0x01D0 4208
0x01D0 020C 0x01D0 420C
0x01D0 0210 0x01D0 4210
0x01D0 0214 0x01D0 4214
DITCSRA1 Left (even TDM time slot) channel status register (DIT mode) 1
DITCSRA2 Left (even TDM time slot) channel status register (DIT mode) 2
DITCSRA3 Left (even TDM time slot) channel status register (DIT mode) 3
DITCSRA4 Left (even TDM time slot) channel status register (DIT mode) 4
DITCSRA5 Left (even TDM time slot) channel status register (DIT mode) 5
DITCSRB0 Right (odd TDM time slot) channel status register (DIT mode) 0
DITCSRB1 Right (odd TDM time slot) channel status register (DIT mode) 1
DITCSRB2 Right (odd TDM time slot) channel status register (DIT mode) 2
DITCSRB3 Right (odd TDM time slot) channel status register (DIT mode) 3
DITCSRB4 Right (odd TDM time slot) channel status register (DIT mode) 4
DITCSRB5 Right (odd TDM time slot) channel status register (DIT mode) 5
DITUDRA0 Left (even TDM time slot) channel user data register (DIT mode) 0
DITUDRA1 Left (even TDM time slot) channel user data register (DIT mode) 1
DITUDRA2 Left (even TDM time slot) channel user data register (DIT mode) 2
DITUDRA3 Left (even TDM time slot) channel user data register (DIT mode) 3
DITUDRA4 Left (even TDM time slot) channel user data register (DIT mode) 4
DITUDRA5 Left (even TDM time slot) channel user data register (DIT mode) 5
DITUDRB0 Right (odd TDM time slot) channel user data register (DIT mode) 0
DITUDRB1 Right (odd TDM time slot) channel user data register (DIT mode) 1
DITUDRB2 Right (odd TDM time slot) channel user data register (DIT mode) 2
DITUDRB3 Right (odd TDM time slot) channel user data register (DIT mode) 3
DITUDRB4 Right (odd TDM time slot) channel user data register (DIT mode) 4
DITUDRB5 Right (odd TDM time slot) channel user data register (DIT mode) 5
SRCTL0
SRCTL1
SRCTL2
SRCTL3
SRCTL4
SRCTL5
SRCTL6
SRCTL7
SRCTL8
SRCTL9
SRCTL10
SRCTL11
SRCTL12
SRCTL13
SRCTL14
SRCTL15
XBUF0(1)
XBUF1(1)
XBUF2(1)
XBUF3(1)
XBUF4(1)
XBUF5(1)
Serializer control register 0
Serializer control register 1
Serializer control register 2
Serializer control register 3
Serializer control register 4
Serializer control register 5
Serializer control register 6
Serializer control register 7
Serializer control register 8
Serializer control register 9
Serializer control register 10
Serializer control register 11
Serializer control register 12
Serializer control register 13
Serializer control register 14
Serializer control register 15
Transmit buffer register for serializer 0
Transmit buffer register for serializer 1
Transmit buffer register for serializer 2
Transmit buffer register for serializer 3
Transmit buffer register for serializer 4
Transmit buffer register for serializer 5
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
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Table 6-41. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
BYTE
McASP1
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
0x01D0 0218 0x01D0 4218
0x01D0 021C 0x01D0 421C
0x01D0 0220 0x01D0 4220
0x01D0 0224 0x01D0 4224
0x01D0 0228 0x01D0 4228
0x01D0 022C 0x01D0 422C
0x01D0 0230 0x01D0 4230
0x01D0 0234 0x01D0 4234
0x01D0 0238 0x01D0 4238
0x01D0 023C 0x01D0 423C
0x01D0 0280 0x01D0 4280
0x01D0 0284 0x01D0 4284
0x01D0 0288 0x01D0 4288
0x01D0 028C 0x01D0 428C
0x01D0 0290 0x01D0 4290
0x01D0 0294 0x01D0 4294
0x01D0 0298 0x01D0 4298
0x01D0 029C 0x01D0 429C
0x01D0 02A0 0x01D0 42A0
0x01D0 02A4 0x01D0 42A4
0x01D0 02A8 0x01D0 42A8
0x01D0 02AC 0x01D0 42AC
0x01D0 02B0 0x01D0 42B0
0x01D0 02B4 0x01D0 42B4
0x01D0 02B8 0x01D0 42B8
0x01D0 02BC 0x01D0 42BC
XBUF6(1)
XBUF7
XBUF8(1)
Transmit buffer register for serializer 6
Transmit buffer register for serializer 7
Transmit buffer register for serializer 8
Transmit buffer register for serializer 9
Transmit buffer register for serializer 10
Transmit buffer register for serializer 11
Transmit buffer register for serializer 12
Transmit buffer register for serializer 13
Transmit buffer register for serializer 14
Transmit buffer register for serializer 15
Receive buffer register for serializer 0
Receive buffer register for serializer 1
Receive buffer register for serializer 2
Receive buffer register for serializer 3
Receive buffer register for serializer 4
Receive buffer register for serializer 5
Receive buffer register for serializer 6
Receive buffer register for serializer 7
Receive buffer register for serializer 8
Receive buffer register for serializer 9
Receive buffer register for serializer 10
Receive buffer register for serializer 11
Receive buffer register for serializer 12
Receive buffer register for serializer 13
Receive buffer register for serializer 14
Receive buffer register for serializer 15
XBUF9
XBUF10(1)
XBUF11(1)
XBUF12
XBUF13(1)
XBUF14(1)
XBUF15
RBUF0(2)
RBUF1(2)
RBUF2(2)
RBUF3(2)
RBUF4(3)
RBUF5(3)
RBUF6(3)
RBUF7(3)
RBUF8(3)
RBUF9(3)
RBUF10(3)
RBUF11(3)
RBUF12(3)
RBUF13(3)
RBUF14(3)
RBUF15(3)
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
(3) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
Table 6-42. McASP Registers Accessed Through DMA Port
McASP0
BYTE
McASP1
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
Receive buffer DMA port address. Cycles through receive serializers,
skipping over transmit serializers and inactive serializers. Starts at the
lowest serializer at the beginning of each time slot. Reads from DMA port
only if XBUSEL = 0 in XFMT.
Read
Accesses
01D0 2000
01D0 2000
01D0 6000
01D0 6000
RBUF
Transmit buffer DMA port address. Cycles through transmit serializers,
skipping over receive and inactive serializers. Starts at the lowest serializer
at the beginning of each time slot. Writes to DMA port only if RBUSEL = 0
in RFMT.
Write
Accesses
XBUF
Table 6-43. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
McASP0
McASP1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01D0 1000
0x01D0 1010
0x01D0 1014
BYTE ADDRESS
0x01D0 5000
0x01D0 5010
0x01D0 5014
AFIFOREV
WFIFOCTL
WFIFOSTS
AFIFO revision identification register
Write FIFO control register
Write FIFO status register
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Table 6-43. McASP AFIFO Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
McASP1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
BYTE ADDRESS
0x01D0 1018
0x01D0 101C
0x01D0 5018
0x01D0 501C
RFIFOCTL
RFIFOSTS
Read FIFO control register
Read FIFO status register
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6.17.2 McASP Electrical Data/Timing
6.17.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-44 and Table 6-45 assume testing over recommended operating conditions (see and ).
Table 6-44. McASP0 Timing Requirements(1) (2)
No.
PARAMETER
MIN
MAX
UNIT
Cycle time, AHCLKR0 external, AHCLKR0 input
Cycle time, AHCLKX0 external, AHCLKX0 input
Pulse duration, AHCLKR0 external, AHCLKR0 input
Pulse duration, AHCLKX0 external, AHCLKX0 input
Cycle time, ACLKR0 external, ACLKR0 input
20
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
20
10
2
3
4
ns
ns
ns
10
greater of 2P or 20
Cycle time, ACLKX0 external, ACLKX0 input
greater of 2P or 20
Pulse duration, ACLKR0 external, ACLKR0 input
Pulse duration, ACLKX0 external, ACLKX0 input
Setup time, AFSR0 input to ACLKR0 internal(3)
Setup time, AFSX0 input to ACLKX0 internal
Setup time, AFSR0 input to ACLKR0 external input(3)
Setup time, AFSX0 input to ACLKX0 external input
Setup time, AFSR0 input to ACLKR0 external output(3)
Setup time, AFSX0 input to ACLKX0 external output
Hold time, AFSR0 input after ACLKR0 internal(3)
Hold time, AFSX0 input after ACLKX0 internal
Hold time, AFSR0 input after ACLKR0 external input(3)
Hold time, AFSX0 input after ACLKX0 external input
Hold time, AFSR0 input after ACLKR0 external output(3)
Hold time, AFSX0 input after ACLKX0 external output
Setup time, AXR0[n] input to ACLKR0 internal(3)
Setup time, AXR0[n] input to ACLKX0 internal(4)
Setup time, AXR0[n] input to ACLKR0 external input(3)
Setup time, AXR0[n] input to ACLKX0 external input(4)
Setup time, AXR0[n] input to ACLKR0 external output(3)
Setup time, AXR0[n] input to ACLKX0 external output(4)
Hold time, AXR0[n] input after ACLKR0 internal(3)
Hold time, AXR0[n] input after ACLKX0 internal(4)
Hold time, AXR0[n] input after ACLKR0 external input(3)
Hold time, AXR0[n] input after ACLKX0 external input(4)
Hold time, AXR0[n] input after ACLKR0 external output(3)
Hold time, AXR0[n] input after ACLKX0 external output(4)
10
10
9.4
9.4
3
5
6
7
8
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
ns
ns
ns
ns
3
3
3
-1.9
-1.9
0.5
0.8
0.5
0.5
9.4
9.4
3
3
3
3
-1.7
-1.7
0.6
0.6
0.6
0.6
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Table 6-45. McASP0 Switching Characteristics(1)
No.
PARAMETER
MIN
MAX
UNIT
Cycle time, AHCLKR0 internal, AHCLKR0 output
Cycle time, AHCLKR0 external, AHCLKR0 output
Cycle time, AHCLKX0 internal, AHCLKX0 output
Cycle time, AHCLKX0 external, AHCLKX0 output
Pulse duration, AHCLKR0 internal, AHCLKR0 output
Pulse duration, AHCLKR0 external, AHCLKR0 output
Pulse duration, AHCLKX0 internal, AHCLKX0 output
Pulse duration, AHCLKX0 external, AHCLKX0 output
Cycle time, ACLKR0 internal, ACLKR0 output
Cycle time, ACLKR0 external, ACLKR0 output
Cycle time, ACLKX0 internal, ACLKX0 output
Cycle time, ACLKX0 external, ACLKX0 output
Pulse duration, ACLKR0 internal, ACLKR0 output
Pulse duration, ACLKR0 external, ACLKR0 output
Pulse duration, ACLKX0 internal, ACLKX0 output
Pulse duration, ACLKX0 external, ACLKX0 output
Delay time, ACLKR0 internal, AFSR output(7)
Delay time, ACLKX0 internal, AFSX output
20
20
9
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
20
20
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
10
11
12
ns
ns
ns
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
0
0
6
6
Delay time, ACLKR0 external input, AFSR output(7)
Delay time, ACLKX0 external input, AFSX output
Delay time, ACLKR0 external output, AFSR output(7)
Delay time, ACLKX0 external output, AFSX output
Delay time, ACLKX0 internal, AXR0[n] output
Delay time, ACLKX0 external input, AXR0[n] output
Delay time, ACLKX0 external output, AXR0[n] output
Disable time, ACLKX0 internal, AXR0[n] output
Disable time, ACLKX0 external input, AXR0[n] output
Disable time, ACLKX0 external output, AXR0[n] output
3
11.7
11.7
11.7
11.7
6
13
td(ACLKRX-AFSRX)
ns
3
3
3
0
14
15
td(ACLKX-AXRV)
2.75
3
11.7
11.7
6
ns
ns
0
tdis(ACLKX-AXRHZ)
3
11.7
11.7
3
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR0.
(3) AHX - Cycle time, AHCLKX0.
(4) P = SYSCLK2 period
(5) AR - ACLKR0 period.
(6) AX - ACLKX0 period.
(7) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
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6.17.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 6-46 and Table 6-47 assume testing over recommended operating conditions (see and ).
Table 6-46. McASP1 Timing Requirements(1) (2)
No.
PARAMETER
MIN
MAX
UNIT
Cycle time, AHCLKR1 external, AHCLKR1 input
Cycle time, AHCLKX1 external, AHCLKX1 input
Pulse duration, AHCLKR1 external, AHCLKR1 input
Pulse duration, AHCLKX1 external, AHCLKX1 input
Cycle time, ACLKR1 external, ACLKR1 input
20
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
20
10
2
3
4
ns
ns
ns
10
greater of 2P or 20
Cycle time, ACLKX1 external, ACLKX1 input
greater of 2P or 20
Pulse duration, ACLKR1 external, ACLKR1 input
Pulse duration, ACLKX1 external, ACLKX1 input
Setup time, AFSR1 input to ACLKR1 internal(3)
Setup time, AFSX1 input to ACLKX1 internal
Setup time, AFSR1 input to ACLKR1 external input(3)
Setup time, AFSX1 input to ACLKX1 external input
Setup time, AFSR1 input to ACLKR1 external output(3)
Setup time, AFSX1 input to ACLKX1 external output
Hold time, AFSR1 input after ACLKR1 internal(3)
Hold time, AFSX1 input after ACLKX1 internal
Hold time, AFSR1 input after ACLKR1 external input(3)
Hold time, AFSX1 input after ACLKX1 external input
Hold time, AFSR1 input after ACLKR1 external output(3)
Hold time, AFSX1 input after ACLKX1 external output
Setup time, AXR1[n] input to ACLKR1 internal(3)
Setup time, AXR1[n] input to ACLKX1 internal(4)
Setup time, AXR1[n] input to ACLKR1 external input(3)
Setup time, AXR1[n] input to ACLKX1 external input(4)
Setup time, AXR1[n] input to ACLKR1 external output(3)
Setup time, AXR1[n] input to ACLKX1 external output(4)
Hold time, AXR1[n] input after ACLKR1 internal(3)
Hold time, AXR1[n] input after ACLKX1 internal(4)
Hold time, AXR1[n] input after ACLKR1 external input(3)
Hold time, AXR1[n] input after ACLKX1 external input(4)
Hold time, AXR1[n] input after ACLKR1 external output(3)
Hold time, AXR1[n] input after ACLKX1 external output(4)
10
10
10.4
10.4
2.6
5
6
7
8
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
ns
ns
ns
ns
2.6
2.6
2.6
-2.4
-2.4
0.85
0.8
0.3
0.3
10.4
10.4
2.6
2.6
2.6
2.6
-2.4
-2.4
0.65
0.4
0.4
0.4
(1) ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(4) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
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Table 6-47. McASP1 Switching Characteristics(1)
No.
PARAMETER
MIN
MAX
UNIT
Cycle time, AHCLKR1 internal, AHCLKR1 output
Cycle time, AHCLKR1 external, AHCLKR1 output
Cycle time, AHCLKX1 internal, AHCLKX1 output
Cycle time, AHCLKX1 external, AHCLKX1 output
Pulse duration, AHCLKR1 internal, AHCLKR1 output
Pulse duration, AHCLKR1 external, AHCLKR1 output
Pulse duration, AHCLKX1 internal, AHCLKX1 output
Pulse duration, AHCLKX1 external, AHCLKX1 output
Cycle time, ACLKR1 internal, ACLKR1 output
Cycle time, ACLKR1 external, ACLKR1 output
Cycle time, ACLKX1 internal, ACLKX1 output
Cycle time, ACLKX1 external, ACLKX1 output
Pulse duration, ACLKR1 internal, ACLKR1 output
Pulse duration, ACLKR1 external, ACLKR1 output
Pulse duration, ACLKX1 internal, ACLKX1 output
Pulse duration, ACLKX1 external, ACLKX1 output
Delay time, ACLKR1 internal, AFSR output(7)
Delay time, ACLKX1 internal, AFSX output
Delay time, ACLKR1 external input, AFSR output(7)
Delay time, ACLKX1 external input, AFSX output
Delay time, ACLKR1 external output, AFSR output(7)
Delay time, ACLKX1 external output, AFSX output
Delay time, ACLKX1 internal, AXR1[n] output
Delay time, ACLKX1 external input, AXR1[n] output
Delay time, ACLKX1 external output, AXR1[n] output
Disable time, ACLKX1 internal, AXR1[n] output
Disable time, ACLKX1 external input, AXR1[n] output
Disable time, ACLKX1 external output, AXR1[n] output
20
20
9
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
20
20
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
10
11
12
ns
ns
ns
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
0.5
0.5
3.9
3.9
3.9
3.9
0.5
3.8
3.9
0.5
3.9
3.9
6.7
6.7
13.8
13.8
13.8
13.8
6.7
13
td(ACLKRX-AFSRX)
ns
14
15
td(ACLKX-AXRV)
13.8
13.8
6.7
ns
ns
tdis(ACLKX-AXRHZ)
13.8
13.8
(1) McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR1.
(3) AHX - Cycle time, AHCLKX1.
(4) P = SYSCLK2 period
(5) AR - ACLKR1 period.
(6) AX - ACLKX1 period.
(7) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
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6.18 Serial Peripheral Interface Ports (SPI0, SPI1)
Figure 6-29 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
SPIx_SIMO
SPIx_SOMI
Peripheral
Configuration Bus
16-Bit Shift Register
16-Bit Buffer
SPIx_ENA
SPIx_SCS
SPIx_CLK
State
Machine
GPIO
Control
(all pins)
Interrupt and
DMA Requests
Clock
Control
Figure 6-29. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin
when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain
manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In
four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating
that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified
by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the
same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
Although the SPI module supports two interrupt outputs, SPIx_INT1 is the only interrupt connected on this
device.
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Optional − Slave Chip Select
Optional Enable (Ready)
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
MASTER SPI
SLAVE SPI
Figure 6-30. Illustration of SPI Master-to-SPI Slave Connection
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6.18.1 SPI Peripheral Registers Description(s)
Table 6-48 is a list of the SPI registers.
Table 6-48. SPIx Configuration Registers
SPI0
BYTE ADDRESS
SPI1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
Global Control Register 0
0x01C4 1000
0x01C4 1004
0x01C4 1008
0x01C4 100C
0x01C4 1010
0x01C4 1014
0x01C4 1018
0x01C4 101C
0x01C4 1020
0x01C4 1024
0x01C4 1028
0x01C4 102C
0x01C4 1030
0x01C4 1034
0x01C4 1038
0x01C4 103C
0x01C4 1040
0x01C4 1044
0x01C4 1048
0x01C4 104C
0x01C4 1050
0x01C4 1054
0x01C4 1058
0x01C4 105C
0x01C4 1060
0x01C4 1064
0x01E1 2000
0x01E1 2004
0x01E1 2008
0x01E1 200C
0x01E1 2010
0x01E1 2014
0x01E1 2018
0x01E1 201C
0x01E1 2020
0x01E1 2024
0x01E1 2028
0x01E1 202C
0x01E1 2030
0x01E1 2034
0x01E1 2038
0x01E1 203C
0x01E1 2040
0x01E1 2044
0x01E1 2048
0x01E1 204C
0x01E1 2050
0x01E1 2054
0x01E1 2058
0x01E1 205C
0x01E1 2060
0x01E1 2064
SPIGCR0
SPIGCR1
SPIINT0
SPILVL
Global Control Register 1
Interrupt Register
Interrupt Level Register
SPIFLG
Flag Register
SPIPC0
Pin Control Register 0 (Pin Function)
Pin Control Register 1 (Pin Direction)
Pin Control Register 2 (Pin Data In)
Pin Control Register 3 (Pin Data Out)
Pin Control Register 4 (Pin Data Set)
Pin Control Register 5 (Pin Data Clear)
Reserved - Do not write to this register
Reserved - Do not write to this register
Reserved - Do not write to this register
Shift Register 0 (without format select)
Shift Register 1 (with format select)
Buffer Register
SPIPC1
SPIPC2
SPIPC3
SPIPC4
SPIPC5
Reserved
Reserved
Reserved
SPIDAT0
SPIDAT1
SPIBUF
SPIEMU
SPIDELAY
SPIDEF
Emulation Register
Delay Register
Default Chip Select Register
Format Register 0
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
Reserved
INTVEC1
Format Register 1
Format Register 2
Format Register 3
Reserved - Do not write to this register
Interrupt Vector for SPI INT1
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6.18.2 SPI Electrical Data/Timing
6.18.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-49 through Table 6-64 assume testing over recommended operating conditions (see Figure 6-31
through Figure 6-34).
Table 6-49. General Timing Requirements for SPI0 Master Modes(1)
No.
PARAMETER
MIN
MAX
UNIT
greater of 2P or
20 ns
1
tc(SPC)M
Cycle Time, SPI0_CLK, All Master Modes
256P
ns
2
3
tw(SPCH)M
tw(SPCL)M
Pulse Width High, SPI0_CLK, All Master Modes
Pulse Width Low, SPI0_CLK, All Master Modes
0.5tc(SPC)M - 1
0.5tc(SPC)M - 1
ns
ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
- 0.5tc(SPC)M + 5
Delay, initial data bit valid on SPI0_SIMO
after initial edge on SPI0_CLK(2)
4
5
6
7
8
td(SIMO_SPC)M
ns
ns
ns
ns
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
- 0.5tc(SPC)M + 5
Polarity = 0, Phase = 0,
from SPI0_CLK rising
5
5
5
5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay, subsequent bits valid on
td(SPC_SIMO)M SPI0_SIMO after transmit edge of
SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M -3
Output hold time, SPI0_SIMO valid
toh(SPC_SIMO)M
afterreceive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Input Setup Time, SPI0_SOMI valid
tsu(SOMI_SPC)M
beforereceive edge of SPI0_CLK
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time, SPI0_SOMI valid after
tih(SPC_SOMI)M
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
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Table 6-50. General Timing Requirements for SPI0 Slave Modes(1)
No.
PARAMETER
MIN
MAX
UNIT
greater of 2P or
20 ns
9
tc(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
256P
ns
10
11
tw(SPCH)S
tw(SPCL)S
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
18
18
ns
ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Setup time, transmit data written to SPI
12
13
14
15
16
tsu(SOMI_SPC)S before initial clock edge from master.(2)
ns
ns
ns
ns
ns
(3)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
18.5
18.5
18.5
18.5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay, subsequent bits valid on
td(SPC_SOMI)S
toh(SPC_SOMI)S
tsu(SIMO_SPC)S
tih(SPC_SIMO)S
SPI0_SOMI after transmit edge of
SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)S -3
Output hold time, SPI0_SOMI valid afte
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Input Setup Time, SPI0_SIMO valid
before receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time, SPI0_SIMO valid after
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
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Table 6-51. Additional(1) SPI0 Master Timings, 4-Pin Enable Option(2) (3)
No.
PARAMETER
MIN
MAX
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 3P + 3
3P + 3
Delay from slave assertion of
SPI0_ENA active to first SPI0_CLK
from master.(4)
17
td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 3
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK edge
to ensure master does not begin the
next transfer.(5)
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
P + 5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-49 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 6-52. Additional(1) SPI0 Master Timings, 4-Pin Chip Select Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P - 5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 2P - 5
2P - 5
Delay from SPI0_SCS active to first
SPI0_CLK(4) (5)
19
td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P - 5
0.5tc(SPC)M + P - 3
P - 3
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS
20
td(SPC_SCS)M
ns
(6) (7)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P - 3
P - 3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-49 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 6-53. Additional(1) SPI0 Master Timings, 5-Pin Option(2) (3)
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
Max delay for slave to
deassert SPI0_ENA after
final SPI0_CLK edge to
ensure master does not
begin the next transfer.(4)
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P + 5
0.5tc(SPC)M + P + 5
P + 5
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P - 3
P - 3
0.5tc(SPC)M + P -3
P - 3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final
SPI0_CLK edge to
master deasserting
SPI0_SCS
20
21
22
td(SPC_SCS)M
ns
ns
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
(5) (6)
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid
td(SCSL_ENAL)M after master asserts SPI0_SCS to delay the
master from beginning the next transfer,
C2TDELAY + P
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P -5
0.5tc(SPC)M + 2P -5
2P -5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Delay from SPI0_SCS
active to first
td(SCS_SPC)M
SPI0_CLK(7) (8) (9)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P -5
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 3
0.5tc(SPC)M + 3P + 3
3P + 3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Delay from assertion of
SPI0_ENA low to first
SPI0_CLK edge.(10)
23
td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 3
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-50 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
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UNIT
Table 6-54. Additional(1) SPI0 Slave Timings, 4-Pin Enable Option(2) (3)
No.
PARAMETER
MIN
MAX
Polarity = 0, Phase = 0,
from SPI0_CLK falling
1.5 P -3
2.5 P + 18.5
Delay from final
SPI0_CLK edge
td(SPC_ENAH)S to slave
Polarity = 0, Phase = 1,
from SPI0_CLK falling
– 0.5tc(SPC)M + 1.5 P -3
1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 18.5
2.5 P + 18.5
24
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
deasserting
SPI0_ENA.
Polarity = 1, Phase = 1,
from SPI0_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 18.5
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-50 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-55. Additional(1) SPI0 Slave Timings, 4-Pin Chip Select Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P+5
P+5
Polarity = 0, Phase = 1,
Required delay from final
from SPI0_CLK falling
26
td(SPC_SCSH)S
SPI0_CLK edge before SPI0_SCS
ns
Polarity = 1, Phase = 0,
is deasserted.
0.5tc(SPC)M + P+5
P+5
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 18.5
P + 18.5
ns
ns
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-50 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 6-56. Additional(1) SPI0 Slave Timings, 5-Pin Option(2) (3)
PARAMETER
MIN
MAX
UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 1,
Required delay from final
from SPI0_CLK falling
26
td(SPC_SCSH)S
SPI0_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI0_SCS is deasserted.
0.5tc(SPC)M + P + 5
P + 5
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 18.5
P + 18.5
18.5
ns
ns
ns
Delay from master deasserting SPI0_SCS to slave
3-stating SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5 P + 18.5
2.5 P + 18.5
2.5 P + 18.5
2.5 P + 18.5
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Delay from final clock receive
edge on SPI0_CLK to slave
3-stating or driving high
SPI0_ENA.(4)
30
tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-50 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
Table 6-57. General Timing Requirements for SPI1 Master Modes(1)
No.
1
PARAMETER
MIN
MAX
UNIT
ns
tc(SPC)M
Cycle Time, SPI1_CLK, All Master Modes
Pulse Width High, SPI1_CLK, All Master Modes
Pulse Width Low, SPI1_CLK, All Master Modes
greater of 2P or 20 ns
0.5tc(SPC)M - 1
256P
5
2
tw(SPCH)M
tw(SPCL)M
ns
3
0.5tc(SPC)M - 1
ns
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
- 0.5tc(SPC)M + 5
Delay, initial data bit valid on
SPI1_SIMO to initial edge on
SPI1_CLK(2)
4
td(SIMO_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
- 0.5tc(SPC)M + 5
Polarity = 0, Phase = 0,
from SPI1_CLK rising
5
5
5
5
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay, subsequent bits valid
on SPI1_SIMO after transmit
edge of SPI1_CLK
5
td(SPC_SIMO)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
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UNIT
(1)
Table 6-57. General Timing Requirements for SPI1 Master Modes
(continued)
No.
PARAMETER
MIN
MAX
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)M -3
Output hold time, SPI1_SIMO
valid after
receive edge of SPI1_CLK
6
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
ns
ns
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Input Setup Time,
SPI1_SOMI valid before
receive edge of SPI1_CLK
7
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Input Hold Time, SPI1_SOMI
valid after receive edge of
SPI1_CLK
8
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Table 6-58. General Timing Requirements for SPI1 Slave Modes(1)
No.
9
PARAMETER
MIN
MAX
UNIT
ns
tc(SPC)S
Cycle Time, SPI1_CLK, All Slave Modes
Pulse Width High, SPI1_CLK, All Slave Modes
Pulse Width Low, SPI1_CLK, All Slave Modes
greater of 2P or 20 ns
256P
10
11
tw(SPCH)S
tw(SPCL)S
18
18
ns
ns
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Setup time, transmit data
written to SPI before initial
clock edge from
12
tsu(SOMI_SPC)S
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
master.(2) (3)
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
19
19
19
19
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay, subsequent bits valid
on SPI1_SOMI after transmit
edge of SPI1_CLK
13
td(SPC_SOMI)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
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(1)
Table 6-58. General Timing Requirements for SPI1 Slave Modes
(continued)
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)S -3
Output hold time, SPI1_SOMI
valid after receive edge of
SPI1_CLK
14
15
16
toh(SPC_SOMI)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Input Setup Time,
SPI1_SIMO valid before
receive edge of SPI1_CLK
tsu(SIMO_SPC)S
ns
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Input Hold Time, SPI1_SIMO
valid after receive edge of
SPI1_CLK
tih(SPC_SIMO)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Table 6-59. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 3
3P + 3
Delay from slave assertion of SPI1_ENA
active to first SPI1_CLK from master.(4)
17
td(EN A_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 3
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Max delay for slave to deassert
SPI1_ENA after final SPI1_CLK edge to
ensure master does not begin the next
transfer.(5)
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + P + 5
P + 5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-57 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
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Table 6-60. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase =
0,
2P -5
to SPI1_CLK rising
Polarity = 0, Phase =
1,
0.5tc(SPC)M + 2P -5
to SPI1_CLK rising
Delay from SPI1_SCS active to first
SPI1_CLK(4) (5)
19
td(SCS_SPC)M
ns
Polarity = 1, Phase =
0,
2P -5
to SPI1_CLK falling
Polarity = 1, Phase =
1,
0.5tc(SPC)M + 2P -5
to SPI1_CLK falling
Polarity = 0, Phase =
0,
0.5tc(SPC)M + P - 3
from SPI1_CLK
falling
Polarity = 0, Phase =
1,
P - 3
from SPI1_CLK
falling
Delay from final SPI1_CLK edge to master
deasserting SPI1_SCS
20
td(SPC_SCS)M
ns
(6) (7)
Polarity = 1, Phase =
0,
0.5tc(SPC)M + P -3
from SPI1_CLK rising
Polarity = 1, Phase =
1,
P - 3
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-57 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Table 6-61. Additional(1) SPI1 Master Timings, 5-Pin Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M+P+5
Max delay for slave to
deassert SPI1_ENA
after final SPI1_CLK
edge to ensure
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+5
0.5tc(SPC)M+P+5
P+5
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
master does not
begin the next
transfer.(4)
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P -3
P - 3
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay from final
SPI1_CLK edge to
master deasserting
SPI1_SCS
20
td(SPC_SCS)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
(5) (6)
0.5tc(SPC)M+ P -3
P - 3
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-58 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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(2) (3)
Table 6-61. Additional (1) SPI1 Master Timings, 5-Pin Option
(continued)
PARAMETER
MIN
MAX
UNIT
Max delay for slave SPI to drive SPI1_ENA
valid after master asserts SPI1_SCS to delay
the master from beginning the next transfer.
21
td(SCSL_ENAL)M
C2TDELAY + P
ns
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Delay from
0.5tc(SPC)M + 2P -5
2P -5
SPI1_SCS active to
22
td(SCS_SPC)M
ns
first SPI1_CLK(7) (8)
Polarity = 1, Phase = 0,
to SPI1_CLK falling
(9)
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -5
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 3
0.5tc(SPC)M + 3P + 3
3P + 3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Delay from assertion
of SPI1_ENA low to
first SPI1_CLK
edge.(10)
23
td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 3
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
Table 6-62. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
1.5 P -3
2.5 P + 19
Delay from
final
SPI1_CLK
edge to slave
deasserting
SPI1_ENA.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
– 0.5tc(SPC)M + 1.5 P -3
1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 19
2.5 P + 19
24
td(SPC_ENAH)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 19
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-58 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-63. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
25
td(SCSL_SPC)S
td(SPC_SCSH)S
tena(SCSL_SOMI)S
P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 1,
Required delay from final
from SPI1_CLK falling
26
27
SPI1_CLK edge before
ns
ns
Polarity = 1, Phase = 0,
SPI1_SCS is deasserted.
0.5tc(SPC)M + P + 5
P + 5
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
P + 19
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-58 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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UNIT
Table 6-63. Additional (1) SPI1 Slave Timings, 4-Pin Chip Select Option
(continued)
(2) (3)
No.
PARAMETER
MIN
MAX
Delay from master deasserting SPI1_SCS to slave
3-stating SPI1_SOMI
28
tdis(SCSH_SOMI)S
P + 19
ns
Table 6-64. Additional(1) SPI1 Slave Timings, 5-Pin Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Required delay from SPI1_SCS asserted at slave to
first SPI1_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 1,
Required delay from final
from SPI1_CLK falling
26
td(SPC_SCSH)S
SPI1_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI1_SCS is deasserted.
0.5tc(SPC)M + P + 5
P + 5
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave
driving SPI1_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 19
ns
ns
ns
Delay from master deasserting SPI1_SCS to slave
3-stating SPI1_SOMI
P + 19
19
Delay from master deasserting SPI1_SCS to slave
driving SPI1_ENA valid
Polarity = 0, Phase = 0,
from SPI1_CLK falling
2.5 P + 19
2.5 P + 19
2.5 P + 19
2.5 P + 19
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Delay from final clock
receive edge on SPI1_CLK
to slave 3-stating or driving
high SPI1_ENA.(4)
30
tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-58 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
6
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 6-31. SPI Timings—Master Mode
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9
SLAVE MODE
POLARITY = 0 PHASE = 0
12
10
15
11
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
16
SI(0)
SI(1)
13
SI(n−1)
SI(n)
14
SO(0)
SO(1)
SO(n−1)
SO(n)
12
SLAVE MODE
POLARITY = 0 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
SI(0)
16
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 0
12
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(n−1)
SO(0)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 1
12
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
Figure 6-32. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH ENABLE
17
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_ENA
MO(0)
MI(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_SCS
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MI(0)
MASTER MODE 5 PIN
23
22
20
MO(1)
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0)
MO(n−1)
MO(n)
MI(0)
MI(1)
MI(n−1)
MI(n)
21
(A)
(A)
SPIx_ENA
SPIx_SCS
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-33. SPI Timings—Master Mode (4-Pin and 5-Pin)
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SLAVE MODE 4 PIN WITH ENABLE
24
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_ENA
SO(0)
SI(0)
SO(1)
SO(n−1) SO(n)
SI(n−1) SI(n)
SI(1)
SLAVE MODE 4 PIN WITH CHIP SELECT
25
26
SPIx_CLK
27
28
SO(n−1)
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SO(0)
SO(1)
SO(n)
SI(0)
SI(1)
SI(n−1)
SI(n)
SLAVE MODE 5 PIN
25
26
30
SPIx_CLK
27
29
28
SO(1)
SPIx_SOMI
SPIx_SIMO
SO(0)
SI(0)
SO(n−1)
SO(n)
SI(1)
SI(n−1) SI(n)
SPIx_ENA
(A)
(A)
DESEL
DESEL
SPIx_SCS
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-34. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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6.19 Enhanced Capture (eCAP) Peripheral
The device contains up to three enhanced capture (eCAP) modules. Figure 6-35 shows a functional block
diagram of a module.
Uses for ECAP include:
•
•
•
•
Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor triggers
Period and duty cycle measurements of Pulse train signals
Decoding current or voltage amplitude derived from cuty cycle encoded current/voltage sensors
The ECAP module described in this specification includes the following features:
•
•
•
•
•
•
•
•
•
32 bit time base
4 event time-stamp registers (each 32 bits)
Edge polarity selection for up to 4 sequenced time-stamp capture events
Interrupt on either of the 4 events
Single shot capture of up to 4 event time-stamps
Continuous mode capture of time-stamps in a 4 deep circular buffer
Absolute time-stamp capture
Difference mode time-stamp capture
All the above resources are dedicated to a single input pin
The eCAP modules are clocked at the SYSCLK2 rate.
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CTRPHS
(phase register−32 bit)
SYNCIn
APWM mode
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Continuous /
Oneshot
Capture Control
to Interrupt
Controller
CTR_OVF
CTR=PRD
CTR=CMP
control
Figure 6-35. eCAP Functional Block Diagram
Table 6-65 is the list of the ECAP registers.
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Table 6-65. ECAPx Configuration Registers
ECAP0
ECAP1
BYTE ADDRESS
ECAP2
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
Time-Stamp Counter
BYTE ADDRESS
0x01F0 6000
0x01F0 6004
0x01F0 6008
0x01F0 600C
0x01F0 6010
0x01F0 6014
0x01F0 6028
0x01F0 602A
0x01F0 602C
0x01F0 602E
0x01F0 6030
0x01F0 6032
0x01F0 605C
0x01F0 7000
0x01F0 7004
0x01F0 7008
0x01F0 700C
0x01F0 7010
0x01F0 7014
0x01F0 7028
0x01F0 702A
0x01F0 702C
0x01F0 702E
0x01F0 7030
0x01F0 7032
0x01F0 705C
0x01F0 8000
0x01F0 8004
0x01F0 8008
0x01F0 800C
0x01F0 8010
0x01F0 8014
0x01F0 8028
0x01F0 802A
0x01F0 802C
0x01F0 802E
0x01F0 8030
0x01F0 8032
0x01F0 805C
TSCTR
CTRPHS
CAP1
Counter Phase Offset Value Register
Capture 1 Register
CAP2
Capture 2 Register
CAP3
Capture 3 Register
CAP4
Capture 4 Register
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
REVID
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Revision ID
Table 6-66 shows the eCAP timing requirement and Table 6-67 shows the eCAP switching characteristics.
Table 6-66. Enhanced Capture (eCAP) Timing Requirement
PARAMETER
TEST CONDITIONS
Asynchronous
MIN
MAX
MAX
UNIT
cycles
cycles
tw(CAP)
Capture input pulse width
2tc(SCO)
2tc(SCO)
Synchronous
Table 6-67. eCAP Switching Characteristics
PARAMETER
MIN
20
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
ns
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6.20 Enhanced Quadrature Encoder (eQEP) Peripheral
The device contains up to two enhanced quadrature encoder (eQEP) modules.
System
control registers
To CPU
EQEPxENCLK
SYSCLK2
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxINT
16
QCLK
QDIR
QI
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
Position counter/
control unit
(PCCU)
Quadrature
decoder
(QDU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 6-36. eQEP Functional Block Diagram
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Table 6-68 is the list of the EQEP registers.
Table 6-69 shows the eQEP timing requirement and Table 6-70 shows the eQEP switching
characteristics.
Table 6-68. EQEP Registers
EQEP0
EQEP1
BYTE ADDRESS
BYTE ADDRESS
ACRONYM
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
REGISTER DESCRIPTION
eQEP Position Counter
0x01F0 9000
0x01F0 9004
0x01F0 9008
0x01F0 900C
0x01F0 9010
0x01F0 9014
0x01F0 9018
0x01F0 901C
0x01F0 9020
0x01F0 9024
0x01F0 9026
0x01F0 9028
0x01F0 902A
0x01F0 902C
0x01F0 902E
0x01F0 9030
0x01F0 9032
0x01F0 9034
0x01F0 9036
0x01F0 9038
0x01F0 903A
0x01F0 903C
0x01F0 903E
0x01F0 9040
0x01F0 905C
0x01F0 A000
0x01F0 A004
0x01F0 A008
0x01F0 A00C
0x01F0 A010
0x01F0 A014
0x01F0 A018
0x01F0 A01C
0x01F0 A020
0x01F0 A024
0x01F0 A026
0x01F0 A028
0x01F0 A02A
0x01F0 A02C
0x01F0 A02E
0x01F0 A030
0x01F0 A032
0x01F0 A034
0x01F0 A036
0x01F0 A038
0x01F0 A03A
0x01F0 A03C
0x01F0 A03E
0x01F0 A040
0x01F0 A05C
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
eQEP Revision ID
QCTMRLAT
QCPRDLAT
REVID
Table 6-69. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
PARAMETER
TEST CONDITIONS
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
tw(QEPP)
QEP input period
2tc(SCO)
2tc(SCO)
2tc(SCO)
2tc(SCO)
2tc(SCO)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Table 6-70. eQEP Switching Characteristics
PARAMETER
MIN
MAX
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
Delay time, QEP input edge to position compare sync output
4tc(SCO)
6tc(SCO)
td(PCS-OUT)QEP
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6.21 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
The device contains up to three enhanced PWM Modules (eHRPWM). Figure 6-37 shows a block diagram
of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the eHRPWM.
EPWMSYNCI
EPWM0SYNCI
EPWM0INT
EPWM0A
EPWM0B
eHRPWM0 module
EPWMTZ
EPWM0SYNCO
EPWM1SYNCI
Interrupt
Controllers
EPWM1INT
EPWM1A
EPWM1B
EPWMTZ
GPIO
MUX
eHRPWM1 module
EPWM1SYNCO
EPWM2SYNCI
EPWM2INT
EPWM2A
EPWM2B
eHRPWM2 module
EPWMTZ
EPWM2SYNCO
To eCAP0
module
(sync in)
EPWMSYNCO
Peripheral Bus
Figure 6-37. Multiple PWM Modules in the System
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Time−base (TB)
Sync
CTR=ZERO
CTR=CMPB
Disabled
in/out
select
Mux
TBPRD shadow (16)
TBPRD active (16)
EPWMSYNCO
EPWMSYNCI
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
Event
trigger
and
interrupt
(ET)
TBPHS active (24)
control
EPWMxINT
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMB
EPWMxA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxB
EPWMxTZINT
TZ
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 6-38. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections
Table 6-71. eHRPWM Module Control and Status Registers Grouped by Submodule
eHRPWM0
eHRPWM1
eHRPWM2
SIZE
(×16)
ACRONYM
SHADOW
REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS
TIME-BASE SUBMODULE REGISTERS
0x01F0 0000
0x01F0 0002
0x01F0 0004
0x01F0 0006
0x01F0 0008
0x01F0 000A
0x01F0 2000
0x01F0 2002
0x01F0 2004
0x01F0 2006
0x01F0 2008
0x01F0 200A
0x01F0 4000
0x01F0 4002
0x01F0 4004
0x01F0 4006
0x01F0 4008
0x01F0 400A
TBCTL
TBSTS
1
1
1
1
1
1
No
No
No
No
No
Yes
Time-Base Control Register
Time-Base Status Register
Extension for HRPWM Phase Register
Time-Base Phase Register
Time-Base Counter Register
Time-Base Period Register
(1)
TBPHSHR
TBPHS
TBCNT
TBPRD
COUNTER-COMPARE SUBMODULE REGISTER
0x01F0 000E
0x01F0 0010
0x01F0 200E
0x01F0 2010
0x01F0 400E
CMPCTL
CMPAHR
1
1
No
No
Counter-Compare Control Register
Extension for HRPWM Counter-Compare
0x01F0 4010
(1)
A Register
0x01F0 0012
0x01F0 0014
0x01F0 2012
0x01F0 2014
0x01F0 4012
0x01F0 4014
CMPA
CMPB
1
1
Yes
Yes
Counter-Compare A Register
Counter-Compare B Register
ACTION-QUALIFIER SUBMODULE REGISTER
(1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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Table 6-71. eHRPWM Module Control and Status Registers Grouped by Submodule (continued)
eHRPWM0
eHRPWM1
eHRPWM2
SIZE
(×16)
ACRONYM
SHADOW
REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS
AQCTLA
1
No
Action-Qualifier Control Register for
Output A (eHRPWMxA)
0x01F0 0016
0x01F0 2016
0x01F0 4016
AQCTLB
1
No
Action-Qualifier Control Register for
Output B (eHRPWMxB)
0x01F0 0018
0x01F0 001A
0x01F0 001C
0x01F0 2018
0x01F0 201A
0x01F0 201C
0x01F0 4018
0x01F0 401A
0x01F0 401C
AQSFRC
1
1
No
Action-Qualifier Software Force Register
AQCSFRC
Yes
Action-Qualifier Continuous S/W Force
Register Set
DEAD-BAND GENERATOR SUBMODULE REGISTER
0x01F0 001E
0x01F0 0020
0x01F0 201E
0x01F0 2020
0x01F0 401E
DBCTL
DBRED
1
1
No
No
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay
Count Register
0x01F0 4020
DBFED
1
No
Dead-Band Generator Falling Edge Delay
Count Register
0x01F0 0022
0x01F0 003C
0x01F0 2022
0x01F0 203C
0x01F0 4022
PWM-CHOPPER SUBMODULE REGISTER
0x01F0 403C PCCTL No
TRIP-ZONE SUBMODULE REGISTER
1
PWM-Chopper Control Register
0x01F0 0024
0x01F0 0028
0x01F0 002A
0x01F0 002C
0x01F0 002E
0x01F0 0030
0x01F0 2024
0x01F0 2028
0x01F0 202A
0x01F0 202C
0x01F0 202E
0x01F0 2030
0x01F0 4024
0x01F0 4028
0x01F0 402A
0x01F0 402C
0x01F0 402E
0x01F0 4030
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
1
1
1
1
1
1
No
No
No
No
No
No
Trip-Zone Select Register
Trip-Zone Control Register
Trip-Zone Enable Interrupt Register
Trip-Zone Flag Register
Trip-Zone Clear Register
Trip-Zone Force Register
EVENT-TRIGGER SUBMODULE REGISTER
0x01F0 0032
0x01F0 0034
0x01F0 0036
0x01F0 0038
0x01F0 003A
0x01F0 2032
0x01F0 2034
0x01F0 2036
0x01F0 2038
0x01F0 203A
0x01F0 4032
0x01F0 4034
0x01F0 4036
0x01F0 4038
0x01F0 403A
ETSEL
ETPS
1
1
1
1
1
No
No
No
No
No
Event-Trigger Selection Register
Event-Trigger Pre-Scale Register
Event-Trigger Flag Register
Event-Trigger Clear Register
Event-Trigger Force Register
ETFLG
ETCLR
ETFRC
HIGH-RESOLUTION PWM (HRPWM) SUBMODULE
0x01F0 5020 HRCNFG No
(2)
0x01F0 1020
0x01F0 3020
1
HRPWM Configuration Register
(2) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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6.21.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 6-72 shows the PWM timing requirements and
Table 6-73, switching characteristics.
Table 6-72. eHRPWM Timing Requirements
PARAMETER
TEST CONDITIONS
Asynchronous
Synchronous
MIN
MAX
UNIT
cycles
cycles
tw(SYNCIN)
Sync input pulse width
2tc(SCO)
2tc(SCO)
Table 6-73. eHRPWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)TZA
8tc(SCO)
cycles
ns
Delay time, trip input active to PWM forced high no pin load; no additional
Delay time, trip input active to PWM forced low programmable delay
25
20
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
no additional programmable
delay
ns
6.21.2 Trip-Zone Input Timing
t
w(TZ)
TZ
t
d(TZ-PWM)HZ
(A)
PWM
A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-39. PWM Hi-Z Characteristics
Table 6-74. Trip-Zone input Timing Requirements
PARAMETER
MIN
MAX
UNIT
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
cycle
s
1tc(SCO)
cycle
s
2tc(SCO)
Table 6-75 shows the high-resolution PWM switching characteristics.
Table 6-75. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
PARAMETER
MIN
TYP
MAX
UNIT
Micro Edge Positioning (MEP) step size(1)
200
ps
(1) MEP step size will increase with low voltage and high temperature and decrease with high voltage and cold temperature.
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6.22 Timers
The timers support the following features:
•
•
•
•
•
•
Configurable as single 64-bit timer or two 32-bit timers
Period timeouts generate interrupts, DMA events or external pin events
8 32-bit compare registers
Compare matches generate interrupt events
Capture capability
64-bit Watchdog capability (Timer64P1 only)
Table 6-76 lists the timer registers.
Table 6-76. Timer Registers
Timer64P 0
0x01C2 0000
0x01C2 0004
0x01C2 0008
0x01C2 000C
0x01C2 0010
0x01C2 0014
0x01C2 0018
0x01C2 001C
0x01C2 0020
0x01C2 0024
0x01C2 0028
0x01C2 0034
0x01C2 0038
0x01C2 003C
0x01C2 0040
0x01C2 0044
0x01C2 0060
0x01C2 0064
0x01C2 0068
0x01C2 006C
0x01C2 0070
0x01C2 0074
0x01C2 0078
0x01C2 007C
Timer64P 1
0x01C2 1000
0x01C2 1004
0x01C2 1008
0x01C2 100C
0x01C2 1010
0x01C2 1014
0x01C2 1018
0x01C2 101C
0x01C2 1020
0x01C2 1024
0x01C2 1028
0x01C2 1034
0x01C2 1038
0x01C2 103C
0x01C2 1040
0x01C2 1044
0x01C2 1060
0x01C2 1064
0x01C2 1068
0x01C2 106C
0x01C2 1070
0x01C2 1074
0x01C2 1078
0x01C2 107C
ACRONYM
REGISTER DESCRIPTION
REV
EMUMGT
GPINTGPEN
GPDATGPDIR
TIM12
Revision Register
Emulation Management Register
GPIO Interrupt and GPIO Enable Register
GPIO Data and GPIO Direction Register
Timer Counter Register 12
Timer Counter Register 34
Timer Period Register 12
Timer Period Register 34
Timer Control Register
TIM34
PRD12
PRD34
TCR
TGCR
Timer Global Control Register
Watchdog Timer Control Register
Timer Reload Register 12
Timer Reload Register 34
Timer Capture Register 12
Timer Capture Register 34
Timer Interrupt Control and Status Register
Compare Register 0
WDTCR
REL12
REL34
CAP12
CAP34
INTCTLSTAT
CMP0
CMP1
Compare Register 1
CMP2
Compare Register 2
CMP3
Compare Register 3
CMP4
Compare Register 4
CMP5
Compare Register 5
CMP6
Compare Register 6
CMP7
Compare Register 7
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6.22.1 Timer Electrical Data/Timing
Table 6-77. Timing Requirements for Timer Input(1) (2) (see Figure 6-40)
No.
1
PARAMETER
Cycle time, TM64Px_IN12
MIN
4P
MAX
UNIT
ns
tc(TM64Px_IN12)
tw(TINPH)
2
Pulse duration, TM64Px_IN12 high
Pulse duration, TM64Px_IN12 low
Transition time, TM64Px_IN12
0.45C
0.45C
0.55C
0.55C
0.05C
ns
3
tw(TINPL)
ns
4
tt(TM64Px_IN12)
ns
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
(2) C = TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is 27 MHz, use C = 37.037 ns
1
2
3
4
4
TM64P0_IN12
Figure 6-40. Timer Timing
Table 6-78. Switching Characteristics Over Recommended Operating Conditions for Timer Output
(1)
No.
5
PARAMETER
Pulse duration, TM64P0_OUT12 high
Pulse duration, TM64P0_OUT12 low
MIN
4P
MAX
UNIT
ns
tw(TOUTH)
tw(TOUTL)
6
4P
ns
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
5
6
TM64P0_OUT12
Figure 6-41. Timer Timing
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6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
6.23.1 I2C Device-Specific Information
Having two I2C modules on the device simplifies system architecture. Figure 6-42 is block diagram of the
I2C Module.
Each I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
General-Purpose I/O Capability if not used as I2C
Clock Prescaler
I2CPSCx
Control
I2CCOARx
Prescaler
Register
Own Address
Register
Slave Address
Register
I2CSARx
Bit Clock Generator
I2CCLKHx
Noise
Filter
I2Cx_SCL
Clock Divide
High Register
I2CCMDRx
I2CEMDRx
I2CCNTx
I2CPID1
Mode Register
Extended Mode
Register
Clock Divide
Low Register
I2CCLKLx
Data Count
Register
Peripheral
Configuration
Bus
Transmit
I2CXSRx
Peripheral ID
Register 1
Transmit Shift
Register
Peripheral ID
Register 2
I2CPID2
I2CDXRx
Transmit Buffer
Noise
Filter
I2Cx_SDA
Interrupt/DMA
Interrupt Enable
Register
Receive
I2CIERx
Interrupt DMA
Requests
Receive Buffer
I2CDRRx
Interrupt Status
Register
I2CSTRx
I2CSRCx
Receive Shift
Register
Interrupt Source
Register
I2CRSRx
Control
Pin Function
Register
Pin Data Out
Register
I2CPDOUT
I2CPFUNC
Pin Direction
Register
Pin Data In
Register
Pin Data Set
Register
Pin Data Clear
Register
I2CPDIR
I2CPDIN
I2CPDSET
I2CPDCLR
Figure 6-42. I2C Module Block Diagram
6.23.2 I2C Peripheral Registers Description(s)
Table 6-79 is the list of the I2C registers.
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Table 6-79. Inter-Integrated Circuit (I2C) Registers
I2C0
I2C1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01C2 2000
0x01C2 2004
0x01C2 2008
0x01C2 200C
0x01C2 2010
0x01C2 2014
0x01C2 2018
0x01C2 201C
0x01C2 2020
0x01C2 2024
0x01C2 2028
0x01C2 202C
0x01C2 2030
0x01C2 2034
0x01C2 2038
0x01C2 2048
0x01C2 204C
0x01C2 2050
0x01C2 2054
0x01C2 2058
0x01C2 205C
BYTE ADDRESS
0x01E2 8000
0x01E2 8004
0x01E2 8008
0x01E2 800C
0x01E2 8010
0x01E2 8014
0x01E2 8018
0x01E2 801C
0x01E2 8020
0x01E2 8024
0x01E2 8028
0x01E2 802C
0x01E2 8030
0x01E2 8034
0x01E2 8038
0x01E2 8048
0x01E2 804C
0x01E2 8050
0x01E2 8054
0x01E2 8058
0x01E2 805C
ICOAR
ICIMR
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
ICSAR
ICDXR
ICMDR
ICIVR
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
REVID1
REVID2
ICPFUNC
ICPDIR
ICPDIN
ICPDOUT
ICPDSET
ICPDCLR
I2C Revision Identification Register 1
I2C Revision Identification Register 2
I2C Pin Function Register
I2C Pin Direction Register
I2C Pin Data In Register
I2C Pin Data Out Register
I2C Pin Data Set Register
I2C Pin Data Clear Register
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6.23.3 I2C Electrical Data/Timing
6.23.3.1 Inter-Integrated Circuit (I2C) Timing
Table 6-80 and Table 6-81 assume testing over recommended operating conditions (see Figure 6-43 and
Figure 6-44).
Table 6-80. I2C Input Timing Requirements
No.
PARAMETER
MIN
10
MAX
UNIT
Standard Mode
Fast Mode
1
tc(SCL)
Cycle time, I2Cx_SCL
ms
2.5
4.7
0.6
4
Standard Mode
Fast Mode
2
3
tsu(SCLH-SDAL)
th(SCLL-SDAL)
tw(SCLL)
Setup time, I2Cx_SCL high before I2Cx_SDA low
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
ms
ms
ms
ms
ns
ms
ms
ns
ns
ns
ns
ms
ns
pF
Standard Mode
Fast Mode
0.6
4.7
1.3
4
Standard Mode
Fast Mode
4
Standard Mode
Fast Mode
5
tw(SCLH)
tsu(SDA-SCLH)
th(SDA-SCLL)
tw(SDAH)
tr(SDA)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
6
Setup time, I2Cx_SDA before I2Cx_SCL high
Hold time, I2Cx_SDA after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
Standard Mode
Fast Mode
7
0
0.9
Standard Mode
Fast Mode
4.7
1.3
8
Standard Mode
Fast Mode
1000
300
1000
300
300
300
300
300
9
Rise time, I2Cx_SDA
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
Standard Mode
Fast Mode
10
11
12
13
14
15
tr(SCL)
Rise time, I2Cx_SCL
Standard Mode
Fast Mode
tf(SDA)
Fall time, I2Cx_SDA
Standard Mode
Fast Mode
tf(SCL)
Fall time, I2Cx_SCL
20 + 0.1Cb
Standard Mode
Fast Mode
4
0.6
N/A
0
tsu(SCLH-SDAH)
Setup time, I2Cx_SCL high before I2Cx_SDA high
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
Standard Mode
Fast Mode
tw(SP)
50
Standard Mode
Fast Mode
400
400
Cb
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Table 6-81. I2C Switching Characteristics(1)
PARAMETER
MIN
10
2.5
4.7
0.6
4
MAX
UNIT
Standard Mode
Fast Mode
16
17
18
19
20
21
22
23
28
tc(SCL)
Cycle time, I2Cx_SCL
ms
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
low
tsu(SCLH-SDAL)
th(SDAL-SCLL)
tw(SCLL)
ms
ms
ms
ms
ns
ms
ms
ms
Standard Mode
Fast Mode
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
Setup time, I2Cx_SDA valid before I2Cx_SCL
high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
tw(SDAH)
Standard Mode
Fast Mode
Hold time, I2Cx_SDA valid after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
0
0.9
Standard Mode
Fast Mode
4.7
1.3
4
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
high
tsu(SCLH-SDAH)
0.6
(1) I2C must be configured correctly to meet the timings in Table 6-81 .
11
9
I2Cx_SDA
6
8
14
4
13
5
10
I2Cx_SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-43. I2C Receive Timings
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26
24
I2Cx_SDA
21
23
19
28
20
25
I2Cx_SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-44. I2C Transmit Timings
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6.24 Universal Asynchronous Receiver/Transmitter (UART)
The device has 3 UART peripherals. Each UART has the following features:
•
•
•
•
•
•
•
•
•
16-byte storage space for both the transmitter and receiver FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Programmable Baud Rate up to 3MBaud
Programmable Oversampling Options of x13 and x16
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
•
•
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
•
Modem control functions (CTS, RTS) on UART0 only.
The UART registers are listed in Section 6.24.1
6.24.1 UART Peripheral Registers Description(s)
Table 6-82 is the list of UART registers.
Table 6-82. UART Registers
UART0
UART1
UART2
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS
0x01C4 2000
0x01C4 2000
0x01C4 2004
0x01C4 2008
0x01C4 2008
0x01C4 200C
0x01C4 2010
0x01C4 2014
0x01C4 2018
0x01C4 201C
0x01C4 2020
0x01C4 2024
0x01C4 2028
0x01C4 2030
0x01C4 2034
0x01D0 C000
0x01D0 C000
0x01D0 C004
0x01D0 C008
0x01D0 C008
0x01D0 C00C
0x01D0 C010
0x01D0 C014
0x01D0 C018
0x01D0 C01C
0x01D0 C020
0x01D0 C024
0x01D0 C028
0x01D0 C030
0x01D0 C034
0x01D0 D000
0x01D0 D000
0x01D0 D004
0x01D0 D008
0x01D0 D008
0x01D0 D00C
0x01D0 D010
0x01D0 D014
0x01D0 D018
0x01D0 D01C
0x01D0 D020
0x01D0 D024
0x01D0 D028
0x01D0 D030
0x01D0 D034
RBR
THR
IER
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
IIR
FCR
LCR
MCR
LSR
Modem Control Register
Line Status Register
MSR
SCR
DLL
Modem Status Register
Scratchpad Register
Divisor LSB Latch
DLH
REVID1
Divisor MSB Latch
Revision Identification Register 1
PWREMU_MGMT Power and Emulation Management Register
MDR
Mode Definition Register
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6.24.2 UART Electrical Data/Timing
Table 6-83. Timing Requirements for UARTx Receive(1) (see Figure 6-45)
No.
4
PARAMETER
Pulse duration, receive data bit (RXDn)
Pulse duration, receive start bit
MIN
MAX
1.05U
1.05U
UNIT
ns
tw(URXDB)
tw(URXSB)
0.96U
0.96U
5
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-84. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 6-45)
No.
1
PARAMETER
Maximum programmable baud rate
Pulse duration, transmit data bit (TXDn)
Pulse duration, transmit start bit
MIN
MAX
UNIT
MBaud(4)
ns
(2) (3)
f(baud)
D/E
2
tw(UTXDB)
tw(UTXSB)
U - 2
U - 2
U + 2
U + 2
3
ns
(1) U = UART baud time = 1/programmed baud rate.
(2) D = UART input clock in MHz. The UART(s) input clock source is PLL0_SYSCLK2.
(3) E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART
sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).
(4) Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF loading, system
frequency, etc.
3
2
Start
UART_TXDn
Bit
Data Bits
5
4
Start
Bit
UART_RXDn
Data Bits
Figure 6-45. UART Transmit/Receive Timing
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6.25 USB0 OTG (USB2.0 OTG)
The device USB2.0 peripheral supports the following features:
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s ) and full speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous)
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable size
•
•
•
Integrated USB 2.0 High Speed PHY
Connects to a standard Charge Pump for VBUS 5 V generation
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
Important Notice: On the original device pinout (marked "A" in the lower right corner of the package),
pins USB0_VSSA33 (H4) and USB0_VSSA (F3) were connected to ground outside the package. For
more robust ESD performance, the USB0 ground references are now connected inside the package on
packages marked "B" and the package pins are unconnected. This change will require that any external
filter circuits previously referenced to ground at these pins will need to reference the board ground instead.
Table 6-85 is the list of USB OTG registers.
Table 6-85. Universal Serial Bus OTG (USB0) Registers
BYTE ADDRESS
0x01E0 0000
0x01E0 0004
0x01E0 0008
0x01E0 000C
0x01E0 0010
0x01E0 0014
0x01E0 0018
0x01E0 001C
0x01E0 0020
0x01E0 0024
0x01E0 0028
0x01E0 002C
0x01E0 0030
0x01E0 0034
0x01E0 0038
0x01E0 003C
0x01E0 0040
0x01E0 0050
0x01E0 0054
0x01E0 0058
0x01E0 005C
0x01E0 0400
0x01E0 0401
0x01E0 0402
0x01E0 0404
0x01E0 0406
0x01E0 0408
ACRONYM
REVID
REGISTER DESCRIPTION
Revision Register
CTRLR
Control Register
STATR
Status Register
EMUR
Emulation Register
MODE
Mode Register
AUTOREQ
SRPFIXTIME
TEARDOWN
INTSRCR
INTSETR
Autorequest Register
SRP Fix Time Register
Teardown Register
USB Interrupt Source Register
USB Interrupt Source Set Register
INTCLRR
USB Interrupt Source Clear Register
USB Interrupt Mask Register
INTMSKR
INTMSKSETR
INTMSKCLRR
INTMASKEDR
EOIR
USB Interrupt Mask Set Register
USB Interrupt Mask Clear Register
USB Interrupt Source Masked Register
USB End of Interrupt Register
INTVECTR
GENRNDISSZ1
GENRNDISSZ2
GENRNDISSZ3
GENRNDISSZ4
FADDR
USB Interrupt Vector Register
Generic RNDIS Size EP1
Generic RNDIS Size EP2
Generic RNDIS Size EP3
Generic RNDIS Size EP4
Function Address Register
POWER
Power Management Register
INTRTX
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
Interrupt Register for Receive Endpoints 1 to 4
Interrupt enable register for INTRTX
Interrupt Enable Register for INTRRX
INTRRX
INTRTXE
INTRRXE
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 040A
0x01E0 040B
0x01E0 040C
0x01E0 040E
0x01E0 040F
ACRONYM
INTRUSB
INTRUSBE
FRAME
REGISTER DESCRIPTION
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
INDEX
Index Register for Selecting the Endpoint Status and Control Registers
Register to Enable the USB 2.0 Test Modes
INDEXED REGISTERS
TESTMODE
These registers operate on the endpoint selected by the INDEX register
0x01E0 0410
0x01E0 0412
TXMAXP
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint (Index register set to select
Endpoints 1-4 only)
Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to select Endpoint
0)
Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints
1-4)
Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0414
0x01E0 0416
Maximum Packet Size for Peripheral/Host Receive Endpoint (Index register set to select
Endpoints 1-4 only)
PERI_RXCSR
HOST_RXCSR
COUNT0
Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints
1-4)
Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0418
Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
RXCOUNT
Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
0x01E0 041A
0x01E0 041B
HOST_TYPE0
Defines the speed of Endpoint 0
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint. (Index register set to select Endpoints 1-4 only)
HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041C
0x01E0 041D
0x01E0 041F
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint. (Index register set to select Endpoints 1-4 only)
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint. (Index register set to select Endpoints 1-4 only)
CONFIGDATA
Returns details of core configuration. (Index register set to select Endpoint 0)
FIFO
0x01E0 0420
0x01E0 0424
0x01E0 0428
0x01E0 042C
0x01E0 0430
FIFO0
FIFO1
FIFO2
FIFO3
FIFO4
Transmit and Receive FIFO Register for Endpoint 0
Transmit and Receive FIFO Register for Endpoint 1
Transmit and Receive FIFO Register for Endpoint 2
Transmit and Receive FIFO Register for Endpoint 3
Transmit and Receive FIFO Register for Endpoint 4
OTG DEVICE CONTROL
0x01E0 0460
DEVCTL
Device Control Register
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
DYNAMIC FIFO CONTROL
Transmit Endpoint FIFO Size
0x01E0 0462
0x01E0 0463
0x01E0 0464
0x01E0 0466
0x01E0 046C
TXFIFOSZ
RXFIFOSZ
(Index register set to select Endpoints 1-4 only)
Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
TXFIFOADDR
RXFIFOADDR
HWVERS
Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
Hardware Version Register
TARGET ENDPOINT 0 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0480
0x01E0 0482
0x01E0 0483
0x01E0 0484
0x01E0 0486
0x01E0 0487
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
TXHUBADDR
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 1 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0488
0x01E0 048A
0x01E0 048B
0x01E0 048C
0x01E0 048E
0x01E0 048F
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
TXHUBADDR
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 2 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0490
0x01E0 0492
0x01E0 0493
0x01E0 0494
0x01E0 0496
0x01E0 0497
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
TXHUBADDR
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 3 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0498
0x01E0 049A
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 049B
TXHUBPORT
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049C
0x01E0 049E
0x01E0 049F
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 4 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 04A0
0x01E0 04A2
0x01E0 04A3
0x01E0 04A4
0x01E0 04A6
0x01E0 04A7
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
TXHUBADDR
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
CONTROL AND STATUS REGISTER FOR ENDPOINT 0
Control Status Register for Endpoint 0 in Peripheral Mode
Control Status Register for Endpoint 0 in Host Mode
Number of Received Bytes in Endpoint 0 FIFO
Defines the Speed of Endpoint 0
0x01E0 0502
PERI_CSR0
HOST_CSR0
COUNT0
0x01E0 0508
0x01E0 050A
0x01E0 050B
0x01E0 050F
HOST_TYPE0
HOST_NAKLIMIT0 Sets the NAK Response Timeout on Endpoint 0
CONFIGDATA
Returns details of core configuration.
CONTROL AND STATUS REGISTER FOR ENDPOINT 1
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Control Status Register for Host Transmit Endpoint (host mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Control Status Register for Host Receive Endpoint (host mode)
Number of Bytes in Host Receive endpoint FIFO
0x01E0 0510
0x01E0 0512
TXMAXP
PERI_TXCSR
HOST_TXCSR
RXMAXP
0x01E0 0514
0x01E0 0516
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01E0 0518
0x01E0 051A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 051B
0x01E0 051C
0x01E0 051D
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 2
0x01E0 0520
0x01E0 0522
TXMAXP
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Control Status Register for Host Transmit Endpoint (host mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Control Status Register for Host Receive Endpoint (host mode)
Number of Bytes in Host Receive endpoint FIFO
0x01E0 0524
0x01E0 0526
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01E0 0528
0x01E0 052A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 052B
0x01E0 052C
0x01E0 052D
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 3
0x01E0 0530
0x01E0 0532
TXMAXP
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Control Status Register for Host Transmit Endpoint (host mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Control Status Register for Host Receive Endpoint (host mode)
Number of Bytes in Host Receive endpoint FIFO
0x01E0 0534
0x01E0 0536
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01E0 0538
0x01E0 053A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 053B
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
0x01E0 053C
0x01E0 053D
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 4
0x01E0 0540
0x01E0 0542
TXMAXP
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Control Status Register for Host Transmit Endpoint (host mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Control Status Register for Host Receive Endpoint (host mode)
Number of Bytes in Host Receive endpoint FIFO
0x01E0 0544
0x01E0 0546
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01E0 0548
0x01E0 054A
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 054B
0x01E0 054C
0x01E0 054D
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
DMA REGISTERS
0x01E0 1000
0x01E0 1004
0x01E0 1008
0x01E0 1800
0x01E0 1808
0x01E0 180C
0x01E0 1810
0x01E0 1820
0x01E0 1828
0x01E0 182C
0x01E0 1830
0x01E0 1840
0x01E0 1848
0x01E0 184C
0x01E0 1850
0x01E0 1860
0x01E0 1868
0x01E0 186C
0x01E0 1870
0x01E0 2C00
0x01E0 2D00
0x01E0 2D04
. . .
DMAREVID
TDFDQ
DMA Revision Register
DMA Teardown Free Descriptor Queue Control Register
DMA Emulation Control Register
DMAEMU
TXGCR[0]
Transmit Channel 0 Global Configuration Register
Receive Channel 0 Global Configuration Register
Receive Channel 0 Host Packet Configuration Register A
Receive Channel 0 Host Packet Configuration Register B
Transmit Channel 1 Global Configuration Register
Receive Channel 1 Global Configuration Register
Receive Channel 1 Host Packet Configuration Register A
Receive Channel 1 Host Packet Configuration Register B
Transmit Channel 2 Global Configuration Register
Receive Channel 2 Global Configuration Register
Receive Channel 2 Host Packet Configuration Register A
Receive Channel 2 Host Packet Configuration Register B
Transmit Channel 3 Global Configuration Register
Receive Channel 3 Global Configuration Register
Receive Channel 3 Host Packet Configuration Register A
Receive Channel 3 Host Packet Configuration Register B
RXGCR[0]
RXHPCRA[0]
RXHPCRB[0]
TXGCR[1]
RXGCR[1]
RXHPCRA[1]
RXHPCRB[1]
TXGCR[2]
RXGCR[2]
RXHPCRA[2]
RXHPCRB[2]
TXGCR[3]
RXGCR[3]
RXHPCRA[3]
RXHPCRB[3]
DMA_SCHED_CTRL DMA Scheduler Control Register
ENTRY[0]
ENTRY[1]
. . .
DMA Scheduler Table Word 0
DMA Scheduler Table Word 1
. . .
0x01E0 2DFC
ENTRY[63]
DMA Scheduler Table Word 63
QUEUE MANAGER REGISTERS
Queue Manager Revision Register
0x01E0 4000
QMGRREVID
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 4008
0x01E0 4020
0x01E0 4024
0x01E0 4028
0x01E0 402C
0x01E0 4080
0x01E0 4084
0x01E0 4088
0x01E0 4090
0x01E0 4094
0x01E0 5000
0x01E0 5004
0x01E0 5010
0x01E0 5014
. . .
ACRONYM
DIVERSION
FDBSC0
REGISTER DESCRIPTION
Queue Diversion Register
Free Descriptor/Buffer Starvation Count Register 0
Free Descriptor/Buffer Starvation Count Register 1
Free Descriptor/Buffer Starvation Count Register 2
Free Descriptor/Buffer Starvation Count Register 3
Linking RAM Region 0 Base Address Register
Linking RAM Region 0 Size Register
Linking RAM Region 1 Base Address Register
Queue Pending Register 0
FDBSC1
FDBSC2
FDBSC3
LRAM0BASE
LRAM0SIZE
LRAM1BASE
PEND0
PEND1
Queue Pending Register 1
QMEMRBASE[0]
QMEMRCTRL[0]
QMEMRBASE[1]
QMEMRCTRL[1]
. . .
Memory Region 0 Base Address Register
Memory Region 0 Control Register
Memory Region 1 Base Address Register
Memory Region 1 Control Register
. . .
0x01E0 5070
0x01E0 5074
0x01E0 600C
0x01E0 601C
. . .
QMEMRBASE[7]
QMEMRCTRL[7]
CTRLD[0]
Memory Region 7 Base Address Register
Memory Region 7 Control Register
Queue Manager Queue 0 Control Register D
Queue Manager Queue 1 Control Register D
. . .
CTRLD[1]
. . .
0x01E0 63FC
0x01E0 6800
0x01E0 6804
0x01E0 6808
0x01E0 6810
0x01E0 6814
0x01E0 6818
. . .
CTRLD[63]
QSTATA[0]
QSTATB[0]
QSTATC[0]
QSTATA[1]
QSTATB[1]
QSTATC[1]
. . .
Queue Manager Queue 63 Status Register D
Queue Manager Queue 0 Status Register A
Queue Manager Queue 0 Status Register B
Queue Manager Queue 0 Status Register C
Queue Manager Queue 1 Status Register A
Queue Manager Queue 1 Status Register B
Queue Manager Queue 1 Status Register C
. . .
0x01E0 6BF0
0x01E0 6BF4
0x01E0 6BF8
QSTATA[63]
QSTATB[63]
QSTATC[63]
Queue Manager Queue 63 Status Register A
Queue Manager Queue 63 Status Register B
Queue Manager Queue 63 Status Register C
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6.25.1 USB2.0 (USB0) Electrical Data/Timing
Table 6-86. Switching Characteristics Over Recommended Operating Conditions for USB2.0 [USB0] (see
Figure 6-46)
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
No.
PARAMETER
UNIT
MIN
75
MAX
300
300
120
2
MIN
4
MAX
20
20
111
2
MIN
0.5
0.5
–
MAX
1
2
3
4
5
tr(D)
Rise time, USB0_DP and USB0_DM signals(1)
Fall time, USB0_DP and USB0_DM signals(1)
Rise/Fall time, matching(2)
ns
ns
tf(D)
75
4
trfM
80
90
1.3
–
–
%
VCRS
Output signal cross-over voltage(1)
1.3
–
V
(3)ns
tjr(source)NT
tjr(FUNC)NT
tjr(source)PT
tjr(FUNC)PT
tw(EOPT)
tw(EOPR)
t(DRATE)
Source (Host) Driver jitter, next transition
Function Driver jitter, next transition
Source (Host) Driver jitter, paired transition(4)
Function Driver jitter, paired transition
2
2
(3)
(3)
(3)
25
2
ns
6
1
1
ns
10
1
ns
(5)
7
8
9
Pulse duration, EOP transmitter
1250
670
1500
160
82
175
–
–
–
ns
(5)
Pulse duration, EOP receiver
ns
Data Rate
1.5
–
12
480
49.5
-
Mb/s
Ω
10 ZDRV
11 ZINP
Driver Output Resistance
Receiver Input Impedance
–
40.5
49.5
40.5
-
100k
100k
Ω
(1) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) tjr = tpx(1) - tpx(0)
(5) Must accept as valid EOP
t
- t
per jr
USB0_DM
V
90% V
OH
CRS
10% V
OL
USB0_DP
t
f
t
r
Figure 6-46. USB0 Integrated Transceiver Interface Timing
6.25.2 USB0 Unused Signal Configuration
If USB0 is unused, then the USB0 signals should be configured as shown below in Table 6-1.
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6.26 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
The PSC includes the following features:
•
Provides a software interface to:
–
–
–
Control module clock enable/disable
Control module reset
Control CPU local reset
•
Supports ICEpick TAP Router power, clock and reset features. For details on ICEpick features see
http://tiexpressdsp.com/wiki/index.php?title=ICEPICK.
Table 6-87. Power and Sleep Controller (PSC) Registers
PSC0
PSC1
ACRONYM
DESCRIPTION
BYTE ADDRESS
0x01C1 0000
0x01C1 0018
0x01C1 0040
BYTE ADDRESS
0x01E2 7000
0x01E2 7018
0x01E2 7040
REVID
INTEVAL
MERRPR0
Peripheral Revision and Class Information Register
Interrupt Evaluation Register
Module Error Pending Register 0 (module 0-15)
(PSC0)
Module Error Pending Register 0 (module 0-31)
(PSC1)
0x01C1 0050
0x01E2 7050
MERRCR0
Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
Power Error Pending Register
0x01C1 0060
0x01C1 0068
0x01C1 0120
0x01C1 0128
0x01C1 0200
0x01C1 0204
0x01C1 0300
0x01C1 0304
0x01C1 0400
0x01C1 0404
0x01E2 7060
0x01E2 7068
0x01E2 7120
0x01E2 7128
0x01E2 7200
0x01E2 7204
0x01E2 7300
0x01E2 7304
0x01E2 7400
0x01E2 7404
PERRPR
PERRCR
PTCMD
Power Error Clear Register
Power Domain Transition Command Register
Power Domain Transition Status Register
Power Domain 0 Status Register
PTSTAT
PDSTAT0
PDSTAT1
PDCTL0
PDCTL1
PDCFG0
PDCFG1
Power Domain 1 Status Register
Power Domain 0 Control Register
Power Domain 1 Control Register
Power Domain 0 Configuration Register
Power Domain 1 Configuration Register
0x01C1 0800-
0x01C1 083C
0x01E2 7800-
0x01E2 787C
MDSTAT0-MDSTAT15 Module Status n Register (modules 0-15) (PSC0)
MDSTAT0-MDSTAT31 Module Status n Register (modules 0-31) (PSC1)
0x01C1 0A00-
0x01C1 0A3C
0x01E2 7A00-
0x01E2 7A7C
MDCTL0-MDCTL15
MDCTL0-MDCTL31
Module Control n Register (modules 0-15) (PSC0)
Module Control n Register (modules 0-31) (PSC1)
6.26.1 Power Domain and Module Topology
The device includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 6-88 and Table 6-89 lists the set of peripherals/modules that are controlled by the
PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 6.26.1.1.
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Table 6-88. PSC0 Default Module Configuration
LPSC Number
Module Name
EDMA3 Channel Controller
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
EMIFA (BR7)
Power Domain
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
-
Default Module State
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
Enable
Auto Sleep/Wake Only
0
—
1
—
2
—
3
—
4
SPI 0
—
5
MMC/SD 0
—
6
ARM Interrupt Controller
ARM RAM/ROM
-
—
7
Yes
-
8
-
9
UART 0
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
-
SwRstDisable
Enable
—
10
11
12
13
14
15
SCR0 (Br 0, Br 1, Br 2, Br 8)
SCR1 (Br 4)
Yes
Yes
Yes
—
Enable
SCR2 (Br 3, Br 5, Br 6)
PRUSS
Enable
SwRstDisable
SwRstDisable
-
ARM
—
-
—
Table 6-89. PSC1 Default Module Configuration
LPSC Number
Module Name
Not Used
Power Domain
—
Default Module State
Auto Sleep/Wake Only
0
—
—
1
USB0 (USB2.0)
Not Used
AlwaysON (PD0)
—
SwRstDisable
—
—
2
—
3
GPIO
AlwaysON (PD0)
—
SwRstDisable
—
—
4
Not Used
—
5
EMAC
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
—
6
EMIFB (Br 20)
McASP0 ( + McASP0 FIFO)
McASP1 ( + McASP1 FIFO)
Not Used
—
7
—
8
—
9
—
10
11
12
13
14-15
16
17
18-19
20
21
22-23
24
25
26
27-30
31
SPI 1
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
—
I2C 1
—
UART 1
—
UART 2
—
Not Used
—
Not Used
—
—
—
eHRPWM0/1/2
Not Used
AlwaysON (PD0)
—
SwRstDisable
—
—
—
ECAP0/1/2
EQEP0/1
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
—
—
—
Not Used
—
SCR8 (Br 15)
SCR7 (Br 12)
SCR12 (Br 18)
Not Used
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
Enable
Yes
Yes
Yes
—
Enable
Enable
—
On-chip RAM (Br 13)
PD_SHRAM
Enable
Yes
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6.26.1.1 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 6-90.
Table 6-90. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. The device is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
SyncReset
Asserted
Asserted
On
Off
A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
SwRstDisable
A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
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6.27 Programmable Real-Time Unit Subsystem (PRUSS)
The Programmable Real-Time Unit Subsystem (PRUSS) consists of
•
•
Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
•
A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the device.
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 6-91 and in Table 6-92. Note that these two memory maps are implemented inside
the PRUSS and are local to the components of the PRUSS.
Table 6-91. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map
BYTE ADDRESS
PRU0
PRU1
0x0000 0000 - 0x0000 0FFF
PRU0 Instruction RAM
PRU1 Instruction RAM
Table 6-92. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map
BYTE ADDRESS
PRU0
Data RAM 0
Reserved
PRU1
Data RAM 1
Reserved
(1)
(1)
(1)
(1)
0x0000 0000 - 0x0000 01FF
0x0000 0200 - 0x0000 1FFF
0x0000 2000 - 0x0000 21FF
0x0000 2200 - 0x0000 3FFF
0x0000 4000 - 0x0000 6FFF
0x0000 7000 - 0x0000 73FF
0x0000 7400 - 0x0000 77FF
0x0000 7800 - 0x0000 7BFF
0x0000 7C00 - 0xFFFF FFFF
Data RAM 1
Reserved
Data RAM 0
Reserved
INTC Registers
PRU0 Control Registers
Reserved
INTC Registers
PRU0 Control Registers
Reserved
PRU1 Control Registers
Reserved
PRU1 Control Registers
Reserved
(1) Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.
The global view of the PRUSS internal memories and control ports is documented in Table 6-93. The
offset addresses of each region are implemented inside the PRUSS but the global device memory
mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and
PRU1 can use either the local or global addresses to access their internal memories, but using the local
addresses will provide access time several cycles faster than using the global addresses. This is because
when accessing via the global address the access needs to be routed through the switch fabric outside
PRUSS and back in through the PRUSS slave port.
Table 6-93. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map
BYTE ADDRESS
REGION
0x01C3 0000 - 0x01C3 01FF
Data RAM 0
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Table 6-93. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map (continued)
BYTE ADDRESS
REGION
Reserved
0x01C3 0200 - 0x01C3 1FFF
0x01C3 2000 - 0x01C3 21FF
0x01C3 2200 - 0x01C3 3FFF
0x01C3 4000 - 0x01C3 6FFF
0x01C3 7000 - 0x01C3 73FF
0x01C3 7400 - 0x01C3 77FF
0x01C3 7800 - 0x01C3 7BFF
0x01C3 7C00 - 0x01C3 7FFF
0x01C3 8000 - 0x01C3 8FFF
0x01C3 9000 - 0x01C3 BFFF
0x01C3 C000 - 0x01C3 CFFF
0x01C3 D000 - 0x01C3 FFFF
Data RAM 1
Reserved
INTC Registers
PRU0 Control Registers
PRU0 Debug Registers
PRU1 Control Registers
PRU1 Debug Registers
PRU0 Instruction RAM
Reserved
PRU1 Instruction RAM
Reserved
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and
configuration registers) using the global memory space addresses
6.27.1 PRUSS Register Descriptions
Table 6-94. Programmable Real-Time Unit Subsystem (PRUSS) Control / Status Registers
PRU0 BYTE ADDRESS
0x01C3 7000
PRU1 BYTE ADDRESS
0x01C3 7800
ACRONYM
CONTROL
STATUS
REGISTER DESCRIPTION
PRU Control Register
PRU Status Register
0x01C3 7004
0x01C3 7804
0x01C3 7008
0x01C3 7808
WAKEUP
CYCLCNT
STALLCNT
PRU Wakeup Enable Register
PRU Cycle Count
0x01C3 700C
0x01C3 780C
0x01C3 7010
0x01C3 7810
PRU Stall Count
PRU Constant Table Block Index
Register 0
0x01C3 7020
0x01C3 7028
0x01C3 7820
0x01C3 7828
CONTABBLKIDX0
CONTABPROPTR0
PRU Constant Table Programmable
Pointer Register 0
PRU Constant Table Programmable
Pointer Register 1
0x01C3 702C
0x01C3 782C
CONTABPROPTR1
PRU Internal General Purpose
Registers (for Debug)
0x01C37400 - 0x01C3747C
0x01C37480 - 0x01C374FC
0x01C3 7C00 - 0x01C3 7C7C
0x01C3 7C80 - 0x01C3 7CFC
INTGPR0 – INTGPR31
INTCTER0 – INTCTER31
PRU Internal Constants Table
Registers (for Debug)
Table 6-95. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers
BYTE ADDRESS
0x01C3 4000
0x01C3 4004
0x01C3 4010
0x01C3 401C
0x01C3 4020
0x01C3 4024
0x01C3 4028
0x01C3 402C
0x01C3 4034
0x01C3 4038
0x01C3 4080
ACRONYM
REVID
REGISTER DESCRIPTION
Revision ID Register
CONTROL
Control Register
GLBLEN
Global Enable Register
GLBLNSTLVL
STATIDXSET
STATIDXCLR
ENIDXSET
Global Nesting Level Register
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
Global Prioritized Index Register
ENIDXCLR
HSTINTENIDXSET
HSTINTENIDXCLR
GLBLPRIIDX
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Table 6-95. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC)
Registers (continued)
BYTE ADDRESS
0x01C3 4200
ACRONYM
STATSETINT0
REGISTER DESCRIPTION
System Interrupt Status Raw/Set Register 0
System Interrupt Status Raw/Set Register 1
System Interrupt Status Enabled/Clear Register 0
System Interrupt Status Enabled/Clear Register 1
System Interrupt Enable Set Register 0
System Interrupt Enable Set Register 1
System Interrupt Enable Clear Register 0
System Interrupt Enable Clear Register 1
Channel Map Registers 0-15
0x01C3 4204
STATSETINT1
0x01C3 4280
STATCLRINT0
0x01C3 4284
STATCLRINT1
0x01C3 4300
ENABLESET0
0x01C3 4304
ENABLESET1
0x01C3 4380
ENABLECLR0
0x01C3 4384
ENABLECLR1
0x01C3 4400 - 0x01C3 4440
0x01C3 4800 - 0x01C3 4808
CHANMAP0 - CHANMAP15
HOSTMAP0 - HOSTMAP2
Host Map Register 0-2
HOSTINTPRIIDX0 -
HOSTINTPRIIDX9
0x01C3 4900 - 0x01C3 4928
Host Interrupt Prioritized Index Registers 0-9
0x01C3 4D00
0x01C3 4D04
0x01C3 4D80
0x01C3 4D84
POLARITY0
POLARITY1
TYPE0
System Interrupt Polarity Register 0
System Interrupt Polarity Register 1
System Interrupt Type Register 0
System Interrupt Type Register 1
TYPE1
HOSTINTNSTLVL0-
HOSTINTNSTLVL9
0x01C3 5100 - 0x01C3 5128
0x01C3 5500
Host Interrupt Nesting Level Registers 0-9
Host Interrupt Enable Register
HOSTINTEN
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6.28 Emulation Logic
This section describes the steps to use a third party debugger. The debug capabilities and features for
ARM are as shown below.
For TI’s latest debug and emulation information see :
http://tiexpressdsp.com/wiki/index.php?title=Category:Emulation
ARM:
•
•
•
Basic Debug
–
–
Execution Control
System Visibility
Advanced Debug
–
–
Global Start
Global Stop
Advanced System Control
–
–
–
Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
•
Program Trace
–
–
–
–
Program flow corruption
Code coverage
Path coverage
Thread/interrupt synchronization problems
•
•
•
Data Trace
–
Memory corruption
Timing Trace
–
Profiling
Analysis Actions
–
–
–
–
–
–
–
Stop program execution
Control trace streams
Generate debug interrupt
Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
•
•
Analysis Events
–
–
–
–
–
Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
Analysis Configuration
–
–
Application access
Debugger access
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Table 6-96. ARM Debug Features
Category
Hardware Feature
Availability
Unlimited
Software breakpoint
Up to 14 HWBPs, including:
2 precise(1) HWBP inside ARM core which are shared
with watch points.
8 imprecise(1) HWBPs from ETM’s address comparators,
which are shared with trace function, and can be used
as watch point too.
Basic Debug
Hardware breakpoint
4 imprecise(1) HWBPs from ICECrusher.
Up to 6 watch points, including:
2 from ARM core which is shared with HWBPs and can
be associated with a data.
Watch point
8 from ETM’s address comparators, which are shared
with trace function, and HWBPs.
2 from ARM core which is shared with HWBPs.
Analysis
Watch point with Data
8 watch points from ETM can be associated with a data
comparator, and ETM has total 4 data comparators.
Counters/timers
3x32-bit (1 cycle ; 2 event)
External Event Trigger In
External Event Trigger Out
Address range for trace
1
1
4
Data qualification for trace
System events for trace control
Counters/Timers for trace control
State Machines/Sequencers
Context/Thread ID Comparator
Independent trigger control units
Capture depth PC
2
20
Trace Control
2x16-bit
1x3-State State Machine
1
12
4k bytes ETB
4k bytes ETB
Y
On-chip Trace
Capture
Capture depth PC + Timing
Application accessible
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
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6.28.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and EMU0 .
TRST holds the debug and boundary scan logic in reset when pulled low (its default state). Since TRST
has an internal pull-down resistor, this ensures that at power up the device functions in its normal
(non-test) operation mode if TRST is not connected. Otherwise, TRST should be driven inactive by the
emulator or boundary scan controller. Boundary scan test cannot be performed while the TRST pin is
pulled low.
Table 6-97. JTAG Port Description
PIN
TYPE
NAME
DESCRIPTION
When asserted (active low) causes all test and debug logic in the device to be reset along
with the IEEE 1149.1 interface
TRST
I
Test Logic Reset
This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.
Depending on the emulator attached to , this is a free running clock or a gated clock
depending on RTCK monitoring.
TCK
I
Test Clock
Synchronized TCK. Depending on the emulator attached to, the JTAG signals are clocked
from RTCK or RTCK is monitored by the emulator to gate TCK.
RTCK
O
Returned Test Clock
TMS
TDI
I
I
Test Mode Select
Test Data Input
Test Data Output
Emulation 0
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
TDO
EMU0
O
I/O
Scan data output of the device
Channel 0 trigger + HSRTDX
6.28.2 Scan Chain Configuration Parameters
Table 6-98 shows the TAP configuration details required to configure the router/emulator for this device.
Table 6-98. JTAG Port Description
Router Port ID
Default TAP
TAP Name
Reserved
ARM926
ETB
Tap IR Length
17
18
19
No
No
No
38
4
4
The router is ICEpick revision C and has a 6-bit IR length.
6.28.3 Initial Scan Chain Configuration
The first level of debug interface that sees the scan controller is the TAP router module. The debugger
can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of
the TAP controllers without disrupting the IR state of the other TAPs.
6.28.3.1 Adding TAPS to the Scan Chain
The TAP router must be programmed to add additional TAPs to the scan chain. The following JTAG scans
must be completed to add the ARM926EJ-S to the scan chain.
A Power-On Reset (POR) or the JTAG Test-Logic Reset state configures the TAP router to contain only
the router’s TAP.
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TDO
TDI
Router
CLK
TMS
Steps
Router
ARM926EJ-S/ETM
Figure 6-47. Adding ARM926EJ-S to the scan chain
Pre-amble: The device whose data reaches the emulator first is listed first in the board configuration file.
This device is a pre-amble for all the other devices. This device has the lowest device ID.
Post-amble: The device whose data reaches the emulator last is listed last in the board configuration file.
This device is a post-amble for all the other devices. This device has the highest device ID.
•
•
•
•
•
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '0'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '0'.
Parameter : The IR main count is '6'.
Parameter : The DR main count is '1'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000007'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '8'.
Parameter : The send data value is '0x00000089'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000002'.
Parameter : The actual receive data is 'discarded'.
Function : Embed the port address in next command.
–
–
Parameter : The port address field is '0x0f000000'.
Parameter : The port address value is '3'.
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•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '32'.
Parameter : The send data value is '0xa2002108'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only all-ones JTAG IR/DR scan.
–
–
–
–
–
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'run-test/idle'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is 'all-ones'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '6'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '1'.
Parameter : The IR main count is '4'.
Parameter : The DR main count is '1'.
The initial scan chain contains only the TAP router module. The following steps must be completed in
order to add ETB TAP to the scan chain.
ARM926EJ-S/ETM
TDI
Router
TDO
CLK
TMS
Steps
ETB
ARM926EJ-S/ETM
Router
Figure 6-48. Adding ETB to the scan chain
Function : Do a send-only JTAG IR/DR scan.
•
•
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000007'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
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–
–
–
Parameter : The bit length of the command is '8'.
Parameter : The send data value is '0x00000089'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000002'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Embed the port address in next command.
–
–
Parameter : The port address field is '0x0f000000'.
Parameter : The port address value is '3'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '32'.
Parameter : The send data value is '0xa3302108'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only all-ones JTAG IR/DR scan.
–
–
–
–
–
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'run-test/idle'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is 'all-ones'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '6 + 4'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '1 + 1'.
Parameter : The IR main count is '4'.
Parameter : The DR main count is '1'.
6.28.4 JTAG 1149.1 Boundary Scan Considerations
To use boundary scan, the following sequence should be followed:
•
•
•
Execute a valid reset sequence and exit reset
Wait at least 6000 OSCIN clock cycles
Enter boundary scan mode using the JTAG pins
No specific value is required on the EMU0 pin for boundary scan testing. If TRST is not driven by the
boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.
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6.29 IEEE 1149.1 JTAG
The JTAG(1) interface is used for BSDL testing and emulation of the device.
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required
for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
6.29.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
Table 6-99. DEVIDR0 Register
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
COMMENTS
0x01C1 4018
DEVIDR0
JTAG Identification Register
Read-only. Provides 32-bit JTAG ID of the device.
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
device, the JTAG ID register resides at address location 0x01C1 4018. The register hex value for each
silicon revision is:
•
•
0x8B7D F02F for silicon revision 1.1
0x9B7D F02F for silicon revision 2.0
For the actual register bit names and their associated bit field descriptions, see Figure 6-49 and
Table 6-100.
31-28
VARIANT (4-Bit)
R-xxxx
27-12
11-1
0
PART NUMBER (16-Bit)
R-1011 0111 1101 1111
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-49. JTAG ID (DEVIDR0) Register Description - Register Value
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Table 6-100. JTAG ID Register Selection Bit Descriptions
BIT
31:28
27:12
11-1
0
NAME
VARIANT
DESCRIPTION
Variant (4-Bit) value
PART NUMBER
Part Number (16-Bit) value
MANUFACTURER Manufacturer (11-Bit) value
LSB LSB. This bit is read as a "1".
6.29.2 JTAG Test-Port Electrical Data/Timing
Table 6-101. Timing Requirements for JTAG Test Port (see Figure 6-50)
No.
1
PARAMETER
MIN
MAX
UNIT
ns
tc(TCK)
Cycle time, TCK
40
16
16
40
16
16
4
2
tw(TCKH)
Pulse duration, TCK high
Pulse duration, TCK low
Cycle time, RTCK
ns
3
tw(TCKL)
ns
4
tc(RTCK)
ns
5
tw(RTCKH)
tw(RTCKL)
tsu(TDIV-RTCKH)
th(RTCKH-TDIV)
Pulse duration, RTCK high
ns
6
Pulse duration, RTCK low
ns
7
Setup time, TDI/TMS/TRST valid before RTCK high
Hold time, TDI/TMS/TRST valid after RTCK high
ns
8
4
ns
Table 6-102. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-50)
No.
PARAMETER
Delay time, RTCK low to TDO valid
MIN
MAX
UNIT
9
td(RTCKL-TDOV)
15
ns
1
2
3
TCK
RTCK
TDO
4
5
6
9
8
7
TDI/TMS/TRST
Figure 6-50. JTAG Test-Port Timing
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7 Device and Documentation Support
7.1 Device Support
TI offers an extensive line of development tools for the device platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and
debug software and hardware modules. The tool's support documentation is electronically available within
the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the device applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the device, visit the Texas Instruments web site
on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing
and availability, contact the nearest TI field sales office or authorized distributor.
7.2 Documentation Support
The following documents describe the device. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
Reference Guides
SPRUGU3 AM1705 ARM Microprocessor System Reference Guide
SPRUFU0
AM17x/AM18x ARM Microprocessor Peripherals Overview Reference Guide
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8 Mechanical Packaging and Orderable Information
This section describes the device orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
8.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
AM1xxx processors and support tools. Each commercial AM1xxx platform member has one of three
prefixes: X, P, or null (no prefix). Texas Instruments recommends two of three possible prefix designators
for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications.
P
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
NULL
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
NULL devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
Figure 8-1 provides a legend for reading the device.
( )
( )
AM1705
X
PTP
3
DEVICE SPEED RANGE
PREFIX
3 = 375 MHz
4 = 456 MHz
TEMPERATURE RANGE (JUNCTION)
X = Experimental Device
P = Prototype Device
Blank = Production Device
Blank
D
A
=
=
=
0°C to 90°C (Commercial Grade)
-40°C to 90°C (Industrial Grade)
-40°C to 105°C( Extended Grade)
DEVICE
PACKAGE TYPE
PTP = 176-Pin PowerPADTM Plastic Quad Flat Pack
[ PTP Suffix], 0.5mm Pin Pitch
SILICON REVISION
B
= Silicon Revision 2.0
Figure 8-1. Device Nomenclature
8.2 Mechanical Drawings
This section contains mechanical drawings for the device.
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PACKAGE OPTION ADDENDUM
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14-May-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
AM1705BPTP3
AM1705BPTP4
XAM1705BPTP3
ACTIVE
ACTIVE
ACTIVE
HLQFP
HLQFP
HLQFP
PTP
176
176
176
40
40
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
PTP
PTP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
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www.ti.com/computers
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interface.ti.com
logic.ti.com
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www.ti.com/consumer-apps
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www.ti.com/industrial
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power.ti.com
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www.ti-rfid.com
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www.ti.com/space-avionics-defense
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www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
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