PC87366-ICK/VLA [TI]
IC,PERIPHERAL (MULTIFUNCTION) CONTROLLER,CMOS,QFP,128PIN;
| 型号： | PC87366-ICK/VLA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,PERIPHERAL (MULTIFUNCTION) CONTROLLER,CMOS,QFP,128PIN |
| 文件： | 总239页 (文件大小：2944K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Revision 2.01
November 23, 2000
PC87366
128-Pin LPC SuperI/O with System Hardware Monitoring
and MIDI and Game Ports
General Description
Outstanding Features
●
The PC87366, a member of National Semiconductor’s 128-pin
LPC SuperI/O family, combines National’s System Hardware
Monitoring capability with a Musical Instrument Digital Interface
(MIDI) Port and game port inputs for up to two joysticks. The
PC87366 is PC99 and ACPI compliant and offers a single-chip
solution to the most commonly used PC I/O peripherals.
System Hardware Monitoring including:
— Diode-based or thermistor-based Temperature Sen-
sor (TMS)
— Voltage Level Monitor (VLM) with VID inputs
●
MIDI Interface compatible with MPU-401 UART mode
●
Game port inputs for up to two joysticks
System Hardware Monitoring provides minimum power con-
sumption and maximum operating efficiency within the system
environment. It integrates National’s diode-based or thermistor-
based Temperature Sensor (TMS) with National’s Voltage Lev-
el Monitor (VLM) for full PC system thermal control. The
PC87366 monitors system voltages using 8-bit Analog to Dig-
ital (A/D) conversion with seven analog input channels and four
internal measuring points.
●
Extended Wake-Up support, including legacy/ACPI
power button support, direct power supply control in
response to wake-up events, power-fail recovery
●
Protection features, including chassis intrusion detection,
GPIO lock and pin configuration lock
●
Fan Speed Control and Monitor for three fans
●
Serial IRQ support (15 options)
●
Bus interface, based on Intel’s LPC Interface Specifi-
cation Revision 1.0, September 29th, 1997
ACCESS.bus Interface, SMBus® physical layer compati-
ble
The PC87366 also incorporates: Fan Speed Control and
Monitor (FSCM) for three fans, extended wake-up support
for a wide range of wake-up events, system design protection
features, a Floppy Disk Controller (FDC), a Keyboard and
Mouse Controller (KBC), ACCESS.bus® Interface (ACB),
System Wake-Up Control (SWC), General-Purpose In-
put/Output (GPIO) support for 40 ports, an enhanced
WATCHDOG Timer (WDT), a full IEEE 1284 Parallel Port
and two enhanced Serial Ports (UARTs), one with Infrared
(IR) support.
●
●
40 GPIO Ports (29 standard, including 15 with Assert
IRQ/SMI/PWUREQs interrupts; 11 VSB powered)
●
Blinking LEDs
●
128-pin PQFP Package
Block Diagram
Floppy Drive
Interface
LPC Serial
Serial
Interface
Serial Infrared
Interface Interface
Parallel Port
Interface
Analog
Inputs
I/O
Ports
Diode
REF Interface
V
IRQ
Interface
SMI
System
Bus
Interface
IEEE 1284
Parallel Port
Floppy Disk
Controller
Serial Port 2
with IR
Serial Port 1
GPIO Ports
Hardware
Monitoring
AVDD
VDD
VBdAT
VSB
ACCESS.bus
Interface
WATCHDOG
Fan Speed
Keyboard &
System Wake-Up
Control
MIDI &
Game Ports
Timer
Control & Monitor Mouse Controller
Game
MIDI
Ports
3 Control 3 Monitor Keyboard &
WDO
Power Wake-Up
SCL SDA
PWUREQ
Inputs
Interface
Mouse I/F
Outputs
Inputs
Events
Control
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
© 2000 National Semiconductor Corporation
www.national.com
❏ Alarm for fan slower than programmable thresh-
Features
old speed
• Voltage Level Monitor (VLM)
❏ Alarm for fan stop
— Seven analog inputs that can support both positive
— Three speed control lines with Pulse Width Modula-
and negative voltages
tion (PWM)
— Four internal measuring points
❏ Output signal in the range of 6 Hz to 93.75 KHz
❏ Duty cycle resolution of 1/256
— Three thermistor-based temperature monitoring
channels
• LPC System Interface
— Internal or external VREF
— VID inputs
— Synchronous cycles, up to 33 MHz bus clock
— 8-bit I/O cycles
— Meets ACPI and DMI requirements for system volt-
age monitoring
— Up to four DMA channels
— 8-bit DMA cycles
• Temperature Sensor (TMS)
— Basic read, write and DMA bus cycles are 13 clock
— Up to two remote diode inputs
cycles long
— Environment temperature sensing via an internal di-
ode
• PC99 and ACPI Compliant
— A/D analog channels provide thermal inputs to di-
— PnP Configuration Register structure
— Flexible resource allocation for all logical devices
❏ Relocatable base address
rectly sense die temperature of remote diodes
— Meets ACPI and DMI requirements for thermal man-
agement
❏ 15 IRQ routing options
— Standby mode to minimize power consumption
❏ Four optional 8-bit DMA channels (where applica-
• Extended Wake-Up
ble)
— Legacy and ACPI power button support
• Floppy Disk Controller (FDC)
— Direct power supply control in response to wake-up
— Programmable write protect
events
— FM and MFM mode support
— Power-fail recovery
— Enhanced mode command for three-mode Floppy
• Musical Instrument Digital Interface (MIDI) Port
Disk Drive (FDD) support
— Compatible with MPU-401 UART mode
— 16-byte Receive and Transmit FIFOs
— Loopback mode support
— Perpendicular recording drive support for 2.88 MB
— Burst and non-burst modes
— Full support for IBM Tape Drive register (TDR) im-
●
plementation of AT and PS/2 drive types
Game Port
— 16-byte FIFO
— Full digital implementation
— Software compatible with the PC8477, which con-
tains a superset of the FDC functions in the
microDP8473, the NEC microPD765A and the
N82077
— Supports up to two analog joysticks
• Protection
— Chassis intrusion detection (CHASI, CHASO)
— High-performance, digital separator
— Standard 5.25” and 3.5” FDD support
— GPIO lock
— Pin configuration lock
• Parallel Port
• 40 General-Purpose I/O (GPIO) Ports
— Software or hardware control
— 29 standard, with Assert IRQ/SMI/PWUREQ for 15
ports
— Enhanced Parallel Port (EPP) compatible with new
version EPP 1.9 and IEEE 1284 compliant
— 11 VSB powered
— EPP support for version EPP 1.7 of the Xircom spec-
— Programmable drive type for each output pin (open-
ification
drain, push-pull or output disable)
— EPP support as mode 4 of the Extended Capabilities
— Programmable option for internal pull-up resistor on
Port (ECP)
each input pin
— IEEE 1284-compliant ECP, including level 2
— Output lock option
— Selection of internal pull-up or pull-down resistor for
— Input debounce mechanism
Paper End (PE) pin
• Fan Speed Control and Fan Speed Monitor (FSCM)
— PCI bus utilization reduction by supporting a de-
mand DMA mode mechanism and a DMA fairness
mechanism
— Supports different fan types
— Speed monitoring for three fans
❏ Digital filtering of the tachometer input signal
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2
Features (Continued)
— Protection circuit that prevents damage to the paral-
lel port when a printer connected to it powers up or
is operated at high voltages, even if the device is in
power-down
• System Wake-Up Control (SWC)
— Power-up request upon detection of Keyboard,
Mouse, RI1, RI2, RING activity and General-Pur-
pose Input Events, as follows:
— Output buffers that can sink and source 14 mA
❏ Preprogrammed Keyboard or Mouse sequence
❏ External modem ring on serial port
• Serial Port 1 (UART1)
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
❏ Ring pulse or pulse train on the RING input signal
❏ Preprogrammed CEIR address in a preselected
standard (NEC, RCA or RC-5)
❏ General-Purpose Input Events
❏ IRQs of internal logical devices
• Serial Port 2 with Infrared (UART2)
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
— HP-SIR
— Optional routing of power-up request on IRQ, SMI
and/or PWBTOUT
— Battery-backed event configuration
— Programmable VSB-powered output for blinking
LEDs (LED1, LED2) control
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
• Clock Sources
— Consumer Remote Control supports RC-5, RC-6,
— 48 MHz clock input
NEC, RCA and RECS 80
— LPC clock, up to 33 MHz
— On-chip low-frequency clock generator for wake-up
— Non-standard DMA support − one or two channels
— PnP dongle support
• Power Supplies
• Keyboard and Mouse Controller (KBC)
— 3.3V supply operation
— 8-bit microcontroller
— Main (VDD and AVDD
— Standby (VSB
— Battery backup (VBAT
)
— Software compatible with the 8042AH and PC87911
)
microcontrollers
)
— 2 KB custom-designed program ROM
— 256 bytes RAM for data
— All pins are 5V tolerant and back-drive protected, ex-
cept LPC bus pins
— Five programmable dedicated open-drain I/O lines
• Strap Configuration
— Asynchronous access to two data registers and one
— Base Address (BADDR) strap to determine the base
status register during normal operation
address of the Index-Data register pair
— Support for both interrupt and polling
— 93 instructions
— Test strap to force the device into test mode (re-
served for National Semiconductor use)
— 8-bit timer/counter
— Power Supply and LED Configuration (PSLDC0,1)
straps to determine the power supply control func-
tions and the VSB power-up defaults of LED2
— Support for binary and BCD arithmetic
— Operation at 8 MHz,12 MHz or 16 MHz (programma-
ble option)
— Power Supply On Polarity (PSONPOL) strap to set
— Can be customized by using the PC87323, which in-
cludes a RAM-based KBC as a development plat-
form for KBC code
PSON active state and output type
• ACCESS.bus Interface (ACB)
— Serial interface compatible with SMBus physical layer
— Compatible with Philips’ I2C®
— ACB master and slave
— Supports polling and interrupt controlled operation
— Optional internal pull-up on SDA and SCL pins
• WATCHDOG Timer (WDT)
— Times out the system based on user-programmable
time-out period
— System power-down capability for power saving
— User-defined trigger events to restart WATCHDOG
— Optional routing of WATCHDOG output on IRQ
and/or SMI lines
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3
Datasheet Revision Record
Revision Date
Status
Draft 0.3
Comments
November 1998
Specification subject to change without notice; MIDI and
Game Port information is incomplete
January 1999
Preliminary 1.0
Specification subject to change without notice; Power
Supply Control and LED sections in Chapter 2 are
incomplete
July 2000
2.0
Datasheet with B2 errata included
TMS/VLM characteristics updated
November 2000
2.01
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Table of Contents
Datasheet Revision Record
............................................................................................................4
1.0 Signal/Pin Connection and Description
1.1
1.2
1.3
1.4
CONNECTION DIAGRAM .........................................................................................................15
BUFFER TYPES AND SIGNAL/PIN DIRECTORY ....................................................................16
PIN MULTIPLEXING .................................................................................................................21
DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................23
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
ACCESS.bus Interface (ACB) ....................................................................................23
Bus Interface ...............................................................................................................23
Clock ............................................................................................................................23
Fan Speed Control and Monitor (FSCM) .....................................................................23
Floppy Disk Controller (FDC) ......................................................................................23
Game Port ..................................................................................................................25
General-Purpose Input/Output (GPIO) Ports ...............................................................25
Infrared (IR) .................................................................................................................25
Keyboard and Mouse Controller (KBC) .....................................................................26
1.4.10 Musical Instrument Digital Interface (MIDI) Port ..........................................................26
1.4.11 Parallel Port ...............................................................................................................27
1.4.12 Power and Ground .....................................................................................................27
1.4.13 Protection ....................................................................................................................28
1.4.14 Serial Port 1 and Serial Port 2 .....................................................................................28
1.4.15 Strap Configuration ......................................................................................................29
1.4.16 System Hardware Monitoring ......................................................................................29
1.4.17 System Wake-Up Control ............................................................................................30
1.4.18 WATCHDOG Timer (WDT) .........................................................................................30
1.5
INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................31
2.0 Device Architecture and Configuration
2.1
2.2
OVERVIEW ...............................................................................................................................33
CONFIGURATION STRUCTURE AND ACCESS .....................................................................33
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
The Index-Data Register Pair ......................................................................................33
Banked Logical Device Registers Structure ................................................................35
Standard Logical Device Configuration Register Definitions .......................................36
Standard Configuration Registers ...............................................................................38
Default Configuration Setup ........................................................................................39
Power States ...............................................................................................................40
Address Decoding .......................................................................................................40
2.3
PROTECTION ...........................................................................................................................40
2.3.1
2.3.2
2.3.3
Chassis Intrusion Detection .........................................................................................40
Pin Configuration Lock ................................................................................................41
GPIO Pin Function Lock ..............................................................................................41
2.4
2.5
2.6
POWER SUPPLY CONTROL (PSC) .........................................................................................41
LED OPERATION AND STATES ..............................................................................................43
POWER SUPPLY CONTROL AND LED CONFIGURATION ....................................................43
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Table of Contents (Continued)
2.7
2.8
REGISTER TYPE ABBREVIATIONS ........................................................................................44
SUPERI/O CONFIGURATION REGISTERS .............................................................................44
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.8.9
SuperI/O ID Register (SID) ..........................................................................................45
SuperI/O Configuration 1 Register (SIOCF1) ..............................................................45
SuperI/O Configuration 2 Register (SIOCF2) ..............................................................46
SuperI/O Configuration 3 Register (SIOCF3) ..............................................................47
SuperI/O Configuration 4 Register (SIOCF4) ..............................................................48
SuperI/O Configuration 5 Register (SIOCF5) ..............................................................49
SuperI/O Revision ID Register (SRID) ........................................................................49
SuperI/O Configuration 8 Register (SIOCF8) ..............................................................50
SuperI/O Configuration A Register (SIOCFA) .............................................................51
2.8.10 SuperI/O Configuration B Register (SIOCFB) .............................................................52
2.8.11 SuperI/O Configuration C Register (SIOCFC) .............................................................53
2.8.12 SuperI/O Configuration D Register (SIOCFD) .............................................................54
2.9
FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................55
2.9.1
2.9.2
2.9.3
2.9.4
General Description .....................................................................................................55
Logical Device 0 (FDC) Configuration .........................................................................55
FDC Configuration Register ........................................................................................56
Drive ID Register .........................................................................................................57
2.10 PARALLEL PORT CONFIGURATION ......................................................................................58
2.10.1 General Description .....................................................................................................58
2.10.2 Logical Device 1 (PP) Configuration ............................................................................59
2.10.3 Parallel Port Configuration Register ............................................................................60
2.11 SERIAL PORT 2 CONFIGURATION .........................................................................................61
2.11.1 General Description .....................................................................................................61
2.11.2 Logical Device 2 (SP2) Configuration ..........................................................................61
2.11.3 Serial Port 2 Configuration Register ............................................................................61
2.12 SERIAL PORT 1 CONFIGURATION .........................................................................................62
2.12.1 Logical Device 3 (SP1) Configuration ..........................................................................62
2.12.2 Serial Port 1 Configuration Register ............................................................................62
2.13 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION .....................................................63
2.13.1 Logical Device 4 (SWC) Configuration ........................................................................63
2.14 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION .....................................64
2.14.1 General Description .....................................................................................................64
2.14.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration ..................................65
2.14.3 KBC Configuration Register ........................................................................................66
2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION ..........................67
2.15.1 General Description .....................................................................................................67
2.15.2 Implementation ............................................................................................................67
2.15.3 Logical Device 7 (GPIO) Configuration .......................................................................68
2.15.4 GPIO Pin Select Register ............................................................................................69
2.15.5 GPIO Pin Configuration Register .................................................................................70
2.15.6 GPIO Event Routing Register ......................................................................................71
2.16 ACCESS.BUS INTERFACE (ACB) CONFIGURATION ............................................................72
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Table of Contents (Continued)
2.16.1 General Description .....................................................................................................72
2.16.2 Logical Device 8 (ACB) Configuration .........................................................................72
2.16.3 ACB Configuration Register ........................................................................................73
2.17 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION .....................................74
2.17.1 General Description .....................................................................................................74
2.17.2 Logical Device 9 (FSCM) Configuration ......................................................................74
2.17.3 Fan Speed Control and Monitor Configuration 1 Register ...........................................75
2.17.4 Fan Speed Control and Monitor Configuration 2 Register ...........................................76
2.17.5 Fan Speed Control OTS Configuration Register (FCOCR) .........................................76
2.18 WATCHDOG TIMER (WDT) CONFIGURATION ......................................................................77
2.18.1 Logical Device 10 (WDT) Configuration ......................................................................77
2.18.2 WATCHDOG Timer Configuration Register ................................................................77
2.19 GAME PORT (GMP) CONFIGURATION ..................................................................................78
2.19.1 Logical Device 11 (GMP) Configuration ......................................................................78
2.19.2 Game Port Configuration Register ..............................................................................78
2.20 MIDI PORT (MIDI) CONFIGURATION ......................................................................................79
2.20.1 Logical Device 12 (MIDI) Configuration .......................................................................79
2.20.2 MIDI Port Configuration Register .................................................................................79
2.21 VOLTAGE LEVEL MONITOR (VLM) CONFIGURATION ..........................................................80
2.21.1 Logical Device 13 (VLM) Configuration .......................................................................80
2.22 TEMPERATURE SENSOR (TMS) CONFIGURATION .............................................................80
2.22.1 Logical Device 14 (TMS) Configuration .......................................................................80
3.0 System Wake-Up Control (SWC)
3.1
3.2
3.3
OVERVIEW ...............................................................................................................................81
FUNCTIONAL DESCRIPTION ..................................................................................................82
EVENT DETECTION .................................................................................................................83
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
Modem Ring ................................................................................................................83
Telephone Ring ...........................................................................................................83
Keyboard and Mouse Activity ......................................................................................84
CEIR Address ..............................................................................................................84
Standby General-Purpose Input Events ......................................................................84
GPIO-Triggered Events ...............................................................................................84
Software Event ............................................................................................................84
Module IRQ Wake-Up Event .......................................................................................84
3.4
SWC REGISTERS .....................................................................................................................85
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
SWC Register Map ......................................................................................................86
Wake-Up Events Status Register 0 (WK_STS0) .........................................................88
Wake-Up Events Status Register (WK_STS1) ............................................................89
Wake-Up Events Enable Register (WK_EN0) .............................................................90
Wake-Up Events Enable Register 1 (WK_EN1) ..........................................................91
Wake-Up Configuration Register (WK_CFG) ..............................................................92
Wake-Up Events Routing to SMI Enable Register 0 (WK_SMIEN0) ...........................93
Wake-Up Events Routing to SMI Enable Register 1 (WK_SMIEN1) ...........................94
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Table of Contents (Continued)
3.4.9
Wake-Up Events Routing to IRQ Enable Register 0 (WK_IRQEN0) ...........................95
3.4.10 Wake-Up Events Routing to IRQ Enable Register 1 (WK_IRQEN1) ...........................96
3.4.11 Wake-Up Extension 1 Enable Register 0 (WK_X1EN0) ..............................................97
3.4.12 Wake-Up Extension 1 Enable Register 1 (WK_X1EN1) ..............................................98
3.4.13 Wake-Up Extension 2 Enable Register 0 (WK_X2EN0) ..............................................99
3.4.14 Wake-Up Extension 2 Enable Register 1 (WK_X2EN1) ............................................100
3.4.15 Wake-Up Extension 3 Enable Register 0 (WK_X3EN0) ............................................101
3.4.16 Wake-Up Extension 3 Enable Register 1 (WK_X3EN1) ............................................102
3.4.17 PS/2 Keyboard and Mouse Wake-Up Events ............................................................103
3.4.18 PS/2 Protocol Control Register (PS2CTL) .................................................................104
3.4.19 Keyboard Data Shift Register (KDSR) .......................................................................104
3.4.20 Mouse Data Shift Register (MDSR) ...........................................................................105
3.4.21 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) ....................................105
3.4.22 CEIR Wake-Up Control Register (IRWCR) ...............................................................106
3.4.23 CEIR Wake-Up Address Register (IRWAD) ..............................................................107
3.4.24 CEIR Wake-Up Address Mask Register (IRWAM) ....................................................107
3.4.25 CEIR Address Shift Register (ADSR) ........................................................................108
3.4.26 CEIR Wake-Up Range 0 Registers ...........................................................................108
3.4.27 CEIR Wake-Up Range 1 Registers ...........................................................................109
3.4.28 CEIR Wake-Up Range 2 Registers ...........................................................................109
3.4.29 CEIR Wake-Up Range 3 Registers ...........................................................................110
3.4.30 Standby General-Purpose I/O (SBGPIO) Register Overview ....................................111
3.4.31 Standby GPIO Pin Select Register (SBGPSEL) ........................................................114
3.4.32 Standby GPIO Pin Configuration Register (SBGPCFG) ...........................................115
3.4.33 Standby GPIOE/GPIE Data Out Register 0 (SB_GPDO0) ........................................117
3.4.34 Standby GPIOE/GPIE Data In Register 0 (SB_GPDI0) ............................................117
3.4.35 Standby GPOS Data Out Register 1 (SB_GPDO1) ..................................................118
3.4.36 Standby GPIS Data In Register 1 (SB_GPDI1) .........................................................118
3.5
SWC REGISTER BITMAP .......................................................................................................119
4.0 Fan Speed Control
4.1
4.2
4.3
OVERVIEW .............................................................................................................................122
FUNCTIONAL DESCRIPTION ................................................................................................122
FAN SPEED CONTROL REGISTERS ....................................................................................123
4.3.1
4.3.2
4.3.3
Fan Speed Control Register Map ..............................................................................123
Fan Speed Control Pre-Scale Register (FCPSR) ......................................................123
Fan Speed Control Duty Cycle Register (FCDCR) ....................................................124
4.4
FAN SPEED CONTROL BITMAP ...........................................................................................124
5.0 Fan Speed Monitor
5.1
5.2
5.3
OVERVIEW .............................................................................................................................125
FUNCTIONAL DESCRIPTION ................................................................................................125
FAN SPEED MONITOR REGISTERS .....................................................................................126
5.3.1
5.3.2
Fan Speed Monitor Register Map ..............................................................................126
Fan Monitor Threshold Register (FMTHR) ................................................................127
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Table of Contents (Continued)
5.3.3
5.3.4
Fan Monitor Speed Register (FMSPR) ......................................................................127
Fan Monitor Control and Status Register (FMCSR) ..................................................127
5.4
FAN SPEED MONITOR BITMAP ............................................................................................128
6.0 General-Purpose Input/Output (GPIO) Port
6.1
6.2
OVERVIEW .............................................................................................................................129
BASIC FUNCTIONALITY ........................................................................................................130
6.2.1
6.2.2
Configuration Options ................................................................................................130
Operation ...................................................................................................................130
6.3
6.4
EVENT HANDLING AND SYSTEM NOTIFICATION ..............................................................131
6.3.1
6.3.2
Event Configuration ...................................................................................................131
System Notification ....................................................................................................131
GPIO PORT REGISTERS .......................................................................................................132
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
GPIO Pin Configuration (GPCFG) Register ..............................................................133
GPIO Pin Event Routing (GPEVR) Register .............................................................134
GPIO Port Runtime Register Map .............................................................................134
GPIO Data Out Register (GPDO) ..............................................................................135
GPIO Data In Register (GPDI) ..................................................................................135
GPIO Event Enable Register (GPEVEN) ..................................................................136
GPIO Event Status Register (GPEVST) ....................................................................136
7.0 WATCHDOG Timer (WDT)
7.1
7.2
7.3
OVERVIEW .............................................................................................................................137
FUNCTIONAL DESCRIPTION ................................................................................................137
WATCHDOG TIMER REGISTERS .........................................................................................138
7.3.1
7.3.2
7.3.3
7.3.4
WATCHDOG Timer Register Map .............................................................................138
WATCHDOG Timeout Register (WDTO) ..................................................................138
WATCHDOG Mask Register (WDMSK) ....................................................................139
WATCHDOG Status Register (WDST) ......................................................................140
7.4
7.5
COUNTING DOWN IN SECONDS ..........................................................................................140
WATCHDOG TIMER REGISTER BITMAP .............................................................................140
8.0 ACCESS.bus Interface (ACB)
8.1
8.2
OVERVIEW .............................................................................................................................141
FUNCTIONAL DESCRIPTION ................................................................................................141
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Data Transactions .....................................................................................................141
Start and Stop Conditions ..........................................................................................141
Acknowledge (ACK) Cycle ........................................................................................142
Acknowledge after Every Byte Rule ..........................................................................143
Addressing Transfer Formats ....................................................................................143
Arbitration on the Bus ................................................................................................143
Master Mode ..............................................................................................................144
Slave Mode ................................................................................................................146
Configuration .............................................................................................................146
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Table of Contents (Continued)
8.3 ACB REGISTERS ....................................................................................................................147
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
ACB Register Map .....................................................................................................147
ACB Serial Data Register (ACBSDA) ........................................................................147
ACB Status Register (ACBST) ..................................................................................148
ACB Control Status Register (ACBCST) ...................................................................149
ACB Control Register 1 (ACBCTL1) ..........................................................................150
ACB Own Address Register (ACBADDR) .................................................................151
ACB Control Register 2 (ACBCTL2) ..........................................................................151
8.4
ACB REGISTER BITMAP ........................................................................................................152
9.0 Game Port (GMP)
9.1
9.2
OVERVIEW .............................................................................................................................153
FUNCTIONAL DESCRIPTION ................................................................................................153
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Game Device Axis Position Indication .......................................................................153
Capturing the Position ...............................................................................................154
Button Status Indication .............................................................................................154
Operation Modes .......................................................................................................155
Operation Control ......................................................................................................156
9.3
GAME PORT REGISTERS .....................................................................................................157
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
Game Port Register Map ...........................................................................................157
Game Port Control Register (GMPCTL) ....................................................................158
Game Port Legacy Status Register (GMPLST) .........................................................159
Game Port Extended Status Register (GMPXST) .....................................................160
Game Port Interrupt Enable Register (GMPIEN) .......................................................161
Game Device A X-Axis Position Low Byte (GMPAXL) ..............................................162
Game Device A X-Axis Position High Byte (GMPAXH) .............................................162
Game Device A Y-Axis Position Low Byte (GMPAYL) ..............................................162
Game Device A Y-Axis Position High Byte (GMPAYH) .............................................162
9.3.10 Game Device B X-Axis Position Low Byte (GMPBXL) ..............................................163
9.3.11 Game Device B X-Axis Position High Byte (GMPBXH) .............................................163
9.3.12 Game Device B Y-Axis Position Low Byte (GMPBYL) ..............................................163
9.3.13 Game Device B Y-Axis Position High Byte (GMPBYH) .............................................163
9.3.14 Game Port Event Polarity Register (GMPEPOL) ......................................................164
9.4
GAME PORT BITMAP .............................................................................................................165
10.0 Musical Instrument Digital Interface (MIDI) Port
10.1 OVERVIEW .............................................................................................................................166
10.2 FUNCTIONAL DESCRIPTION ................................................................................................166
10.2.1 Internal Bus Interface Unit .........................................................................................167
10.2.2 Port Control and Status Registers .............................................................................167
10.2.3 Data Buffers and FIFOs .............................................................................................167
10.2.4 MIDI Communication Engine .....................................................................................167
10.2.5 MIDI Signals Routing Control Logic ...........................................................................168
10.2.6 Operation Modes .......................................................................................................168
10.2.7 MIDI Port Status Flags ..............................................................................................169
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Table of Contents (Continued)
10.2.8 MIDI Port Interrupts ...................................................................................................170
10.2.9 Enhanced MIDI Port Features ...................................................................................171
10.3 MIDI PORT REGISTERS ........................................................................................................172
10.3.1 MIDI Port Register Map .............................................................................................172
10.3.2 MIDI Data In Register (MDI) ......................................................................................172
10.3.3 MIDI Data Out Register (MDO) .................................................................................172
10.3.4 MIDI Status Register (MSTAT) ..................................................................................173
10.3.5 MIDI Command Register (MCOM) ............................................................................173
10.3.6 MIDI Control Register (MCNTL) ................................................................................174
10.4 MIDI PORT BITMAP ................................................................................................................175
11.0 Voltage Level Monitor (VLM)
11.1 OVERVIEW .............................................................................................................................176
11.2 FUNCTIONAL DESCRIPTION ................................................................................................176
11.2.1 Voltage Measurement, Channels 0 through 10 .........................................................177
11.2.2 Thermistor-Based Temperature Measurement, Channels 11 to 13 ..........................178
11.2.3
V
, V
and V
Limits, OTS and ALERT Output, IRQ and SMI ......................178
LOW
OS
HIGH
11.2.4 Power-On Reset Default States ................................................................................179
11.2.5 Standby Mode ...........................................................................................................179
11.3 ANALOG SUPPLY CONNECTION .........................................................................................179
11.3.1 Recommendations .....................................................................................................179
11.3.2 Reference Voltage .....................................................................................................180
11.4 REGISTER BANK OVERVIEW ...............................................................................................180
11.5 VLM REGISTERS ....................................................................................................................181
11.5.1 VLM Register Map .....................................................................................................181
11.5.2 Voltage Event Status Register 0 (VEVSTS0) ............................................................182
11.5.3 Voltage Event Status Register 1 (VEVSTS1) ............................................................182
11.5.4 Voltage Event to SMI Register 0 (VEVSMI0) ............................................................183
11.5.5 Voltage Event to SMI Register 1 (VEVSMI1) ............................................................184
11.5.6 Voltage Event to IRQ Register 0 (VEVIRQ0) ............................................................185
11.5.7 Voltage Event to IRQ Register 1 (VEVIRQ1) ............................................................185
11.5.8 Voltage ID Register (VID) ..........................................................................................186
11.5.9 Voltage Conversion Rate Register (VCNVR) ............................................................187
11.5.10 VLM Configuration Register (VLMCFG) ....................................................................188
11.5.11 VLM Bank Select Register (VLMBS) .........................................................................188
11.5.12 Voltage Channel Configuration and Status Register (VCHCFST) .............................189
11.5.13 Read Channel Voltage Register (RDCHV) ................................................................190
11.5.14 Channel Voltage High Limit Register (CHVH) ...........................................................190
11.5.15 Channel Voltage Low Limit Register (CHVL) ............................................................190
11.5.16 Overtemperature Shutdown Limit Register (OTSL) ...................................................190
11.6 VLM REGISTER BITMAP ........................................................................................................191
11.6.1 VLM Control and Status Registers ............................................................................191
11.6.2 VLM Channel Registers ............................................................................................191
11.7 USAGE HINTS ........................................................................................................................192
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Table of Contents (Continued)
11.7.1 Calculating the Channel Delay ..................................................................................192
11.7.2 Measuring Out of Range Positive and Negative Voltages .........................................193
11.7.3 Obtaining the Specified VLM/TMS Accuracy .............................................................193
12.0 Temperature Sensor (TMS)
12.1 OVERVIEW .............................................................................................................................194
12.2 FUNCTIONAL DESCRIPTION ................................................................................................194
12.2.1 Register Bank Overview ............................................................................................195
12.2.2
T
, T
and T
Limits, OTS and ALERT Output, IRQ and SMI ......................195
LOW
OS HIGH
12.2.3 ALERT Response Read Sequence ...........................................................................196
12.2.4 Power-On Reset Default States ................................................................................196
12.2.5 Temperature Data Format .........................................................................................197
12.2.6 Standby Mode ...........................................................................................................197
12.2.7 Diode Fault Detection ................................................................................................197
12.3 TMS REGISTERS ...................................................................................................................198
12.3.1 TMS Register Map .....................................................................................................198
12.3.2 Temperature Event Status Register (TEVSTS) .........................................................199
12.3.3 Temperature Event to SMI Register (TEVSMI) .........................................................200
12.3.4 Temperature Event to IRQ Register (TEVIRQ) .........................................................201
12.3.5 TMS Configuration Register (TMSCFG) ....................................................................202
12.3.6 TMS Bank Select Register (TMSBS) .........................................................................202
12.3.7 Temperature Channel Configuration and Status Register (TCHCFST) ....................203
12.3.8 Read Channel Temperature Register (RDCHT) ........................................................204
12.3.9 Channel Temperature High Limit Register (CHTH) ...................................................204
12.3.10 Channel Temperature Low Limit Register (CHTL) ....................................................204
12.3.11 Channel Overtemperature Limit Register (CHOTL) ..................................................204
12.4 TMS REGISTER BITMAP .......................................................................................................205
12.4.1 TMS Control and Status Registers ..........................................................................205
12.4.2 TMS Channel Registers ...........................................................................................205
12.5 USAGE HINTS ........................................................................................................................206
12.5.1 Remote Diode Selection ............................................................................................206
12.5.2 ADC Noise Filtering ...................................................................................................206
12.5.3 PC Board Layout .......................................................................................................206
12.5.4 Twisted Pair and Shielded Cables .............................................................................208
12.5.5 Obtaining the Specified VLM/TMS Accuracy .............................................................208
13.0 Legacy Functional Blocks
13.1 KEYBOARD AND MOUSE CONTROLLER (KBC) ..................................................................209
13.1.1 General Description ...................................................................................................209
13.1.2 KBC Register Map .....................................................................................................209
13.1.3 KBC Bitmap Summary ...............................................................................................209
13.2 FLOPPY DISK CONTROLLER (FDC) .....................................................................................210
13.2.1 General Description ...................................................................................................210
13.2.2 FDC Register Map .....................................................................................................210
13.2.3 FDC Bitmap Summary ...............................................................................................211
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Table of Contents (Continued)
13.3 PARALLEL PORT ....................................................................................................................212
13.3.1 General Description ...................................................................................................212
13.3.2 Parallel Port Register Map .........................................................................................212
13.3.3 Parallel Port Bitmap Summary ..................................................................................213
13.4 UART FUNCTIONALITY (SP1 AND SP2) ...............................................................................215
13.4.1 General Description ...................................................................................................215
13.4.2 UART Mode Register Bank Overview .......................................................................215
13.4.3 SP1 and SP2 Register Maps for UART Functionality ................................................216
13.4.4 SP1 and SP2 Bitmap Summary for UART Functionality ...........................................218
13.5 IR FUNCTIONALITY (SP2) .....................................................................................................220
13.5.1 General Description ...................................................................................................220
13.5.2 IR Mode Register Bank Overview .............................................................................220
13.5.3 SP2 Register Map for IR Functionality ......................................................................221
13.5.4 SP2 Bitmap Summary for IR Functionality ................................................................222
14.0 Device Characteristics
14.1 GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................224
14.1.1 Recommended Operating Conditions .......................................................................224
14.1.2 Absolute Maximum Ratings .......................................................................................224
14.1.3 Capacitance ..............................................................................................................224
14.1.4 Power Consumption under Recommended Operating Conditions ............................225
14.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ................................................225
14.2.1 Input, CMOS Compatible ...........................................................................................225
14.2.2 Input, PCI 3.3V ..........................................................................................................225
14.2.3 Input, SMBus Compatible ..........................................................................................225
14.2.4 Input, Strap Pin ..........................................................................................................226
14.2.5 Input, TTL Compatible ...............................................................................................226
14.2.6 Input, TTL Compatible with Schmitt Trigger ..............................................................226
14.2.7 Output, PCI 3.3V .......................................................................................................227
14.2.8 Output, Totem-Pole Buffer .........................................................................................227
14.2.9 Output, Open-Drain Buffer .........................................................................................227
14.2.10 Input, Analog .............................................................................................................227
14.2.11 Input, Analog .............................................................................................................227
14.2.12 Input, Analog .............................................................................................................228
14.2.13 Output, Analog ...........................................................................................................228
14.2.14 Output, Analog ...........................................................................................................228
14.2.15 Exceptions .................................................................................................................228
14.3 INTERNAL RESISTORS .........................................................................................................229
14.3.1 Pull-Up Resistor .........................................................................................................229
14.3.2 Pull-Down Resistor ....................................................................................................229
14.4 ANALOG CHARACTERISTICS ...............................................................................................229
14.4.1 VLM ...........................................................................................................................229
14.4.2 TMS ...........................................................................................................................230
14.5 AC ELECTRICAL CHARACTERISTICS ..................................................................................231
14.5.1 AC Test Conditions ....................................................................................................231
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Table of Contents (Continued)
14.5.2 Clock Timing ..............................................................................................................231
14.5.3 LCLK and LRESET ....................................................................................................232
14.5.4 LPC and SERIRQ Signals .........................................................................................233
14.5.5 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing ...........................234
14.5.6 Modem Control Timing ..............................................................................................235
14.5.7 FDC Write Data Timing .............................................................................................235
14.5.8 FDC Drive Control Timing .........................................................................................236
14.5.9 FDC Read Data Timing .............................................................................................236
14.5.10 Standard Parallel Port Timing ....................................................................................237
14.5.11 Enhanced Parallel Port Timing ..................................................................................237
14.5.12 Extended Capabilities Port (ECP) Timing ..................................................................238
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PC87366 - Rev 2.01
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM
WGATE
AVI1
65
66
67
38
37
36
35
WDATA
SLPS5/AVI0
SLPS3
STEP
DIR
PWBTIN/GPIS2
PSON/GPOS1
PWBTOUT/GPOS0
68
69
70
GPIO16/MTR1/IRSL2
DR0
34
33
32
GPIO17/DR1/IRSL3
MTR0
71
PWUREQ
VSB
72
73
31
30
INDEX
VBAT
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
DRATE0
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
CHASI
DENSEL
SLCT
GPIOE5/CHASO
GPIOE4/RING/ALARM
GPIOE3/LED2
GPIOE2/OTS2/LED1
PE
BUSY_WAIT
ACK
GPIOE1/OTS1
GPIOE0
PD7
PD6
PD5
VDD
VSS
CLKIN
GPIO10/SMI
VDD
PC87366-xxx/VLA
VSS
PD4
LAD3
PD3
SLIN_ASTRB
PD2
LAD2
LAD1
LAD0
LFRAME
INIT
PD1
ERR
PD0
LDRQ
SERIRQ
LCLK
LRESET
AFD_DSTRB
STB_WRITE
DCD1
GA20/GPIO07
KBRST/GPIO06
GPIO05/P17
GPIO04/P12
GPIO03/FANOUT0
GPIO02/FANIN0
GPIO01/FANOUT1
GPIO00/FANIN1
GPIO34/FANOUT2
8
DSR1
SIN1
7
6
5
RTS1/TEST
SOUT1/PSLDC0
CTS1
4
100
101
3
2
DTR1_BOUT1/BADDR
RI1
102
1
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC87366-xxx/VLA
See NS Package Number VLA128A
xxx = Three-character identifier for National data and keyboard ROM and/or customer identification code.
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1.0 Signal/Pin Connection and Description (Continued)
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY
Table 2 is an alphabetical list of all signals, cross-referenced to additional information for detailed functional descriptions,
electrical DC characteristics and pin multiplexing. The signal DC characteristics are denoted by a buffer type symbol, de-
scribed briefly below and in further detail in Section 14.2. The pin multiplexing information refers to two different types of
multiplexing:
●
MUX - Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two
different functions. Each function is associated with different board connectivity. Normally, the function selection is de-
termined by the board design and cannot be changed dynamically. The multiplexing options must be configured by
the BIOS upon power-up in order to comply with the board implementation.
●
MM - Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or
more modes of operation within the same function. These modes are associated with the same external (board) con-
nectivity. Mode selection may be controlled by the device driver through the registers of the functional block and do
not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O
configuration perspective. The mode selection method (registers and bits), as well as the signal specification in each
mode, are described within the functional description of the relevant functional block.
Table 1. Buffer Types
Symbol
Description
INAN#
INC
Input, analog type number
Input, CMOS compatible
INPCI
INSM
INSTRP
INT
Input, PCI 3.3V
Input, SMBus compatible
Input, Strap pin with weak pull-down during strap time
Input, TTL compatible
INTS
INULR
OAN#
OPCI
Op/n
Input, TTL compatible with Schmitt Trigger
Input, with serial UL Resistor
Output, analog type number
Output, PCI 3.3V
Output, push-pull buffer that is capable of sourcing p mA and sinking n mA
Output, open-drain output buffer that is capable of sinking n mA
Power pin
ODn
PWR
GND
Ground pin
Table 2. SIgnal/Pin Directory
Functional Group
DC Characteristics
Buffer Type Section
Signal
Pin(s)
MUX
Name
Parallel Port
Parallel Port
Section
INT
ACK
79
93
27
1.4.11
1.4.11
14.2.5
OD14, O14/14
OD6
AFD_DSTRB
ALARM
ASTRB
AVI0
14.2.9, 14.2.8
14.2.9
MM
Hardware Monitoring 1.4.16
MUX
See SLIN_ASTRB
INAN1
INAN1
37
Hardware Monitoring 1.4.16
14.2.10
14.2.10
N/A
MUX
MUX
AVI1-6
AVDD
38-43
44
Hardware Monitoring 1.4.16
Power and Ground 1.4.12
Power and Ground 1.4.12
Strap Configuration 1.4.15
PWR
AVSS
45
AGND
INSTRP
N/A
BADDR
BOUT1
101
14.2.4
See DTR1_BOUT1
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1.0 Signal/Pin Connection and Description (Continued)
Functional Group
DC Characteristics
Buffer Type Section
Signal
BOUT2
Pin(s)
MUX
Name
Section
See DTR2_BOUT2
INT
BUSY_WAIT
CHASI
CHASO
CLKIN
CTS1
78
Parallel Port
Protection
Protection
Clock
1.4.11
1.4.13
1.4.13
1.4.3
14.2.5
MM
INC
29
14.2.1
OD6
28
14.2.9
MUX
INT
22
14.2.5
INTS
INTS
INTS
INTS
O2/12
OD12, O2/12
100
108
95
Serial Port 1
Serial Port 2
Serial Port 1
Serial Port 2
FDC
1.4.14
1.4.14
1.4.14
1.4.14
1.4.5
14.2.6
CTS2
14.2.6
DCD1
14.2.6
DCD2
103
75
14.2.6
DENSEL
DIR
14.2.8
68
FDC
1.4.5
14.2.9, 14.2.8
D1N
D2N
47
49
INAN3
INAN2
Hardware Monitoring 1.4.16
Hardware Monitoring 1.4.16
14.2.12
14.2.11
D1P
D2P
48
50
OD12, O2/12
OD12, O2/12
O3/6
DR0
70
71
74
60
96
104
FDC
1.4.5
1.4.5
1.4.5
1.4.5
1.4.14
1.4.14
14.2.9, 14.2.8
14.2.9, 14.2.8
14.2.8
DR1
FDC
MUX
DRATE0
DSKCHG
DSR1
FDC
INT
FDC
14.2.5
INTS
Serial Port 1
Serial Port 2
14.2.6
INTS
DSR2
14.2.6
DSTRB
See AFD_DSTRB
O3/6
DTR1_BOUT1 101
DTR2_BOUT2 109
Serial Port 1
Serial Port 2
Parallel Port
Fan Speed
Fan Speed
Fan Speed
Fan Speed
Fan Speed
Fan Speed
KBC
1.4.14
1.4.14
1.4.11
1.4.4
1.4.4
1.4.4
1.4.4
1.4.4
1.4.4
1.4.9
1.4.17
1.4.7
14.2.8
MUX, MM
MUX, MM
O3/6
14.2.8
INT
ERR
91
4
14.2.5
INTS
FANIN0
14.2.6
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
INTS
FANIN1
2
14.2.6
INTS
FANIN2
128
5
14.2.6
O2/14
FANOUT0
FANOUT1
FANOUT2
GA20 (P21)
GPIE6-7
GPIO00-07
14.2.8
O2/14
3
14.2.8
O2/14
1
14.2.8
INT, OD2
INTS
9
14.2.5, 14.2.9
14.2.6
58-59
2-9
System Wake-Up
GPIO Port
INTS, OD6, O3/6
14.2.6, 14.2.9, 14.2.8
GPIO10
GPIO11-14
GPO15
21
53-56
57
INTS, OD6, O3/6
GPIO Port
1.4.7
14.2.6, 14.2.9, 14.2.8
MUX
GPIO16-17
69, 71
INTS, OD6, O3/6
INTS, OD6, O3/6
INTS, OD6, O3/6
GPIO20-27
117-124
GPIO Port
1.4.7
1.4.7
1.4.17
14.2.6, 14.2.9, 14.2.8
14.2.6, 14.2.9, 14.2.8
14.2.6, 14.2.9, 14.2.8
MUX
MUX
GPIO30-33
GPIO34
125-128
1
GPIO Port
GPIOE0-1
23-24
System Wake-Up
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17
1.0 Signal/Pin Connection and Description (Continued)
Functional Group
DC Characteristics
Signal
GPIOE2-5
Pin(s)
25-28
MUX
Name
System Wake-Up
System Wake-Up
System Wake-Up
FDC
Section
1.4.17
1.4.17
1.4.17
1.4.5
1.4.5
1.4.11
1.4.8
1.4.8
1.4.8
1.4.8
1.4.8
1.4.8
1.4.6
1.4.6
1.4.6
1.4.6
1.4.6
1.4.6
1.4.6
1.4.6
1.4.9
1.4.9
1.4.9
1.4.2
1.4.17
1.4.2
1.4.2
1.4.2
1.4.2
1.4.9
1.4.9
1.4.10
1.4.10
1.4.5
1.4.5
Buffer Type
Section
14.2.6, 14.2.9, 14.2.8
14.2.6
INTS, OD6, O3/6
INTS
MUX
MUX
MUX
GPIS2
35
OD6, O3/6
OD12, O2/12
INT
GPOS0-1
HDSEL
INDEX
33-34
61
14.2.9, 14.2.8
14.2.9, 14.2.8
14.2.5
73
FDC
OD14, O14/14
INTS
INIT
89
Parallel Port
Infrared
14.2.9, 14.2.8
14.2.6
MUX
IRRX1
59
INTS, O3/6
INT, O3/6
INT, O3/6
INT
MUX, MM
IRRX2_IRSL0
IRSL1
58
Infrared
14.2.6, 14.2.8
14.2.5, 14.2.8
14.2.5, 14.2.8
14.2.5
127
69
Infrared
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
IRSL2
Infrared
IRSL3
71
Infrared
O6/12
IRTX
57
Infrared
14.2.8
INTS
JOYABTN0
JOYABTN1
JOYAX
119
120
117
118
123
124
121
122
111
112
8
Game Port
Game Port
Game Port
Game Port
Game Port
Game Port
Game Port
Game Port
KBC
14.2.6
INTS
14.2.6
INTS, OD12
INTS, OD12
INTS
14.2.6, 14.2.9
14.2.6, 14.2.9
14.2.6
JOYAY
JOYBBTN0
JOYBBTN1
JOYBX
JOYBY
KBCLK
KBDAT
INTS
14.2.6
INTS, OD12
INTS, OD12
INTS, OD14
INTS, OD14
INTS, OD2
INPCI, OPCI
O12/12
14.2.6, 14.2.9
14.2.6, 14.2.9
14.2.6, 14.2.9
14.2.6, 14.2.9
14.2.6, 14.2.9
14.2.2, 14.2.7
14.2.8
KBC
MUX
MUX
KBRST (P20)
LAD0-3
LED1, LED2
LCLK
KBC
15-18
25, 26
11
Bus Interface
System Wake-Up
Bus Interface
Bus Interface
Bus Interface
Bus Interface
KBC
INPCI
14.2.2
OPCI
LDRQ
13
14.2.7
INPCI
LFRAME
LRESET
MCLK
14
14.2.2
INPCI
10
14.2.2
INTS, OD14
INTS, OD14
INTS
113
114
126
125
72
14.2.6, 14.2.9
14.2.6, 14.2.9
14.2.6
MDAT
KBC
MUX
MUX
MDRX
MIDI Port
MIDI Port
FDC
O3/6
MDTX
14.2.8
OD12, O2/12
OD12, O2/12
MTR0
14.2.9, 14.2.8
14.2.9, 14.2.8
MUX
MTR1
69
FDC
OTS1
OTS2
24
25
OD6
Hardware Monitoring 1.4.16
14.2.9
MUX
MUX
INT, OD2
P12, P16, P17 6,127, 7
KBC
1.4.9
14.2.5, 14.2.9
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18
1.0 Signal/Pin Connection and Description (Continued)
Functional Group
DC Characteristics
Buffer Type Section
Signal
PD7-5
PD4-3,
PD2, PD1
PD0
Pin(s)
80-82
85-86
88, 90
92
MUX
Name
Parallel Port
Parallel Port
Section
INT, O14/14
1.4.11
14.2.5, 14.2.9, 14.2.8
INT
PE
77
1.4.11
14.2.5
INSTRP
INSTRP
OD12, O4/4
INSTRP
INTS
PSLDC0
PSLDC1
PSON
PSONPOL
PWBTIN
PWBTOUT
PWUREQ
RDATA
RI1
99
Strap Configuration 1.4.15
Strap Configuration 1.4.15
14.2.4
MUX
MUX
MUX
107
34
14.2.4
System Wake-Up
1.4.17
14.2.9, 14.2.8
14.2.4
109
35
Strap Configuration 1.4.15
MUX
MUX
MUX
System Wake-Up
System Wake-Up
System Wake-Up
FDC
1.4.17
1.4.17
1.4.17
1.4.5
14.2.6
OD12
33
14.2.9
OD6
32
14.2.9
INT
62
14.2.5
INTS
102
110
27
Serial Port 1
Serial Port 2
System Wake-Up
Serial Port 1
Serial Port 2
ACB
1.4.14
1.4.14
1.4.17
1.4.14
1.4.14
1.4.1
14.2.6
INTS
RI2
14.2.6
INTS
MUX
MUX
RING
14.2.6
O3/6
RTS1
98
14.2.8
O3/6
RTS2
106
54
14.2.8
INT, OD6, O3/6
INT, OD6, O3/6
INPCI, OPCI
INTS
MUX
MUX
SCL
14.2.5, 14.2.9, 14.2.8
14.2.5, 14.2.9, 14.2.8
14.2.2, 14.2.7
14.2.6
SDA
55
ACB
1.4.1
SERIRQ
SIN1
12
Bus Interface
Serial Port 1
Serial Port 2
Parallel Port
Parallel Port
1.4.2
97
1.4.14
1.4.14
1.4.11
1.4.11
INTS
SIN2
105
76
14.2.6
INT
SLCT
14.2.5
OD14, O14/14
MM
SLIN_ASTRB
87
14.2.9, 14.2.8
MUX
(SLPS3)
INTS
SLPS3,5
36,37
System Wake-Up
1.4.17
14.2.6
OD12
MUX
MUX
MUX
SMI
21
Bus Interface
Serial Port 1
Serial Port 2
FDC
1.4.2
14.2.9
O3/6
SOUT1
SOUT2
STEP
STB_WRITE
TEST
TRK0
TS1-3
VBAT
99
1.4.14
1.4.14
1.4.5
14.2.8
O3/6
107
67
14.2.8
OD12, O2/12
OD14, O14/14
INSTRP
INT
14.2.9, 14.2.8
14.2.9, 14.2.8
14.2.4
MM
94
Parallel Port
1.4.11
MUX
98
Strap Configuration 1.4.15
64
FDC
VLM
1.4.5
14.2.5
INAN1
MUX
47-49
30
1.4.16
14.2.10
N/A
INULR
Power and Ground 1.4.12
VDD
20, 52, 83, 115 Power and Ground 1.4.12
PWR
N/A
VREF
INAN2, OAN1
46
31
Hardware Monitoring 1.4.16
Power and Ground 1.4.12
14.2.11, 14.2.13
N/A
VSB
PWR
GND
VSS
19, 51, 84, 116 Power and Ground 1.4.12
See BUSY_WAIT
N/A
WAIT
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19
1.0 Signal/Pin Connection and Description (Continued)
Functional Group
DC Characteristics
Buffer Type Section
OD12, O2/12
Signal
WDATA
Pin(s)
MUX
Name
Section
1.4.5
66
56
65
63
FDC
14.2.9, 14.2.8
14.2.9, 14.2.8
14.2.9, 14.2.8
14.2.5
OD6, O3/6
OD12, O2/12
INT
MUX
WDO
WATCHDOG
FDC
1.4.18
1.4.5
1.4.5
WGATE
WP
FDC
WRITE
See STB_WRITE
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20
1.0 Signal/Pin Connection and Description (Continued)
1.3 PIN MULTIPLEXING
The multiplexing options and the associated setup configuration for all pins are described in Table 3. A multiplexing option
can be chosen on one pin only per group.
Table 3. Pin Multiplexing Configuration
Default
Configuration
Alternate
Configuration
Pin(s)
Signal
GPIO34
I/O
Signal
I/O
1
2
3
4
5
6
7
8
9
I/O SIOCF2, Bits 1-0 = 00
I/O SIOCF2, Bit 2 = 0
I/O SIOCF2, Bit 3 = 0
I/O SIOCF2, Bit 4 = 0
I/O SIOCF2, Bit 5 = 0
I/O SIOCF2, Bit 6 = 0
I/O SIOCF2, Bit 7 = 0
SIOCF3, Bit 0 = 1
FANOUT2
FANIN1
FANOUT1
FANIN0
FANOUT0
P12
O
I
SIOCF2, Bits 1-0 = 01
SIOCF2, Bit 2 = 1
SIOCF2, Bit 3 = 1
SIOCF2, Bit 4 = 1
SIOCF2, Bit 5 = 1
GPIO00
GPIO01
O
I
GPIO02
GPIO03
O
GPIO04
I/O SIOCF2, Bit 6 = 1
I/O SIOCF2, Bit 7 = 1
I/O SIOCF3, Bit 0 = 0
I/O SIOCF3, Bit 1 = 0
GPIO05
P17
KBRST (P20)
GA20 (P21)
GPIO10
GPIO06
GPIO07
SMI
SIOCF3, Bit 1 = 1
21
24
I/O SIOCF3, Bit 2 = 0
I/O SIOCFA, Bit 0 = 0
O
O
O
O
O
SIOCF3, Bit 2 = 1
GPIOE1
OTS1
SIOCFA, Bit 0 = 1
LED1
SIOCFA, Bits 2-1 = 01
SIOCFA, Bits 2-1 = 10
SIOCFA, Bit 3 =1
SIOCFA, Bits 2-1 = 001
I/O
25
26
27
28
GPIOE2
GPIOE3
GPIOE4
OTS2
SIOCFA, Bit 3 = 01
I/O
LED2
RING
I
SIOCFA, Bits 5-4 = 01
SIOCFA, Bits 5-4 = 10
SIOCFA, Bit 6 =1
I/O SIOCFA, Bits 5-4 = 00
ALARM
CHASO
O
O
GPIOE5
I/O SIOCFA, Bit 6 = 0
PWBTOUT
33-35, PSON
O
O
GPOS0
GPOS1
GPIS2
AVI0
0
0
I
SIOCFA, Bit 7 = 01
I
SIOCFA, Bit 7 = 11
37
PWBTIN
SLPS5
I
I
47
48
49
54
55
56
57
58
59
D1N
I
O
I
SIOCFB, Bit 6 = 0
SIOCFB, Bit 6 = 0
SIOCFB, Bit 6 = 0
TS1
I
I
I
SIOCFB, Bit 6 = 1
SIOCFB, Bit 6 = 1
SIOCFB, Bit 6 = 1
D1P
TS2
D2N
TS3
GPIO12
GPIO13
GPIO14
GPO15
GPIE6
GPIE7
I/O SIOCF3, Bit 5 = 0
I/O SIOCF3, Bit 5 = 0
I/O SIOCF3, Bit 6 = 0
SCL
SDA
WDO
IRTX
I/O SIOCF3, Bit 5 = 1
I/O SIOCF3, Bit 5 = 1
O
O
SIOCF3, Bit 6 = 1
SIOCF3, Bit 7 = 1
O
I
SIOCF3, Bit 7 = 0
SIOCFB, Bit 0 = 0
SIOCFB, Bit 1 = 0
IRRX2_IRSL0 I/O SIOCFB, Bit 0 = 1
I
IRRX1
I
SIOCFB, Bit 1 = 1
MTR1
O
SIOCF4, Bits 1-0 = 01
69
71
GPIO16
GPIO17
I/O SIOCF4, Bits 1-0 = 00
I/O SIOCF4, Bits 3-2 = 00
IRSL2
I/O SIOCF4, Bits 1-0 = 10
DR1
O
I
SIOCF4, Bits 3-2 = 01
SIOCF4, Bits 3-2 = 10
IRSL3
117
118
119
120
GPIO20
GPIO21
GPIO22
GPIO23
I/O SIOCF4, Bit 4 = 0
I/O SIOCF4, Bit 4 = 0
I/O SIOCF4, Bit 4 = 0
I/O SIOCF4, Bit 4 = 0
JOYAX
JOYAY
JOYABTN0
JOYABTN1
I/O SIOCF4, Bit 4 = 1
I/O SIOCF4, Bit 4 = 1
I
I
SIOCF4, Bit 4 = 1
SIOCF4, Bit 4 = 1
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21
1.0 Signal/Pin Connection and Description (Continued)
Default
Configuration
Alternate
I/O Configuration
Pin(s)
Signal
GPIO24
I/O
Signal
JOYBX
121
122
123
124
125
126
I/O SIOCF4, Bit 4 = 0
I/O SIOCF4, Bit 4 = 0
I/O SIOCF4, Bit 4 = 0
I/O SIOCF4, Bit 4 = 0
I/O SIOCF4, Bit 5 = 0
I/O SIOCF4, Bit 5 = 0
I/O SIOCF4, Bit 4 = 1
I/O SIOCF4, Bit 4 = 1
GPIO25
GPIO26
GPIO27
GPIO30
GPIO31
JOYBY
JOYBBTN0
JOYBBTN1
MDTX
I
I
SIOCF4, Bit 4 = 1
SIOCF4, Bit 4 = 1
SIOCF4, Bit 5 = 1
SIOCF4, Bit 5 = 1
O
I
MDRX
P16
I/O SIOCF4, Bits 7,6 = 01
I/O SIOCF4, Bits 7,6 = 10
127
128
GPIO32
I/O SIOCF4, Bits 7,6 = 00
IRSL1
GPIO33
I/O SIOCF5, Bits 1-0=0
FANIN2
I
SIOCF5, Bits 1-0 = 10
1. The signal selected on each pin is determined during VSB power-up by the PSLDC0,1 straps.
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22
1.0 Signal/Pin Connection and Description (Continued)
1.4 DETAILED SIGNAL/PIN DESCRIPTIONS
This section describes all signals. Signals are organized in functional groups.
1.4.1
ACCESS.bus Interface (ACB)
Pin(s) I/O Buffer Type Power Well
Signal
Description
ACCESS.bus Clock Signal. An internal pull-up is optional,
depending upon the ACCESS.bus configuration register.
INSM/OD6
INSM/OD6
VDD
VDD
SCL
SDA
54
55
I/O
I/O
ACCESS.bus Data Signal. An internal pull-up is optional,
depending upon the ACCESS.bus configuration register.
1.4.2
Bus Interface
Signal
Pin(s) I/O Buffer Type Power Well
Description
LPC Address-Data. Multiplexed command, address bi-
directional data and cycle status.
INPCI/OPCI
VDD
LAD0-3
15-18
I/O
INPCI
OPCI
VDD
VDD
LCLK
11
13
I
LPC Clock. Practically, the PCI clock (up to 33 MHz).
LPC DMA Request. Encoded DMA request for LPC I/F.
LDRQ
O
LPC Frame. Low pulse indicates the beginning of new LPC
cycle or termination of a broken cycle.
INPCI
INPCI
VDD
VDD
LFRAME
LRESET
14
10
I
I
LPC Reset. Practically, the PCI system reset.
Serial IRQ. The interrupt requests are serialized over a single
pin, where each internal IRQ signal is delivered during a
designated time slot.
INPCI/OPCI
OD12
VDD
VDD
SERIRQ
SMI
12
21
I/O
OD
System Management Interrupt.
1.4.3
Clock
Signal
Pin(s) I/O Buffer Type Power Well
INT VDD
Description
CLKIN
22
I
Clock In. 48 MHz clock input.
1.4.4
Fan Speed Control and Monitor (FSCM)
Pin(s) I/O Buffer Type Power Well
Signal
Description
FANIN0
FANIN1
FANIN2
4
2
128
Fan Inputs. Used to feed the fan’s tachometer pulse to the Fan
Speed Monitor. The rising edge indicates the completion of a half
(or full) revolution of the fan.
INTS
VDD
I
FANOUT0
FANOUT1
FANOUT2
5
3
1
Fan Outputs. Pulse Width Modulation (PWM) signals, used to
control the speed of cooling fans by controlling the voltage
supplied to the fan’s motor.
O2/14
VDD
O
1.4.5
Floppy Disk Controller (FDC)
Pin(s) I/O Buffer Type Power Well
Signal
Description
Density Select. Indicates that a high FDC density data rate (500
Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is
selected.
O2/12
VDD
DENSEL
DIR
75
68
O
O
DENSEL polarity is controlled by bit 5 of the FDC Configuration
Register.
Direction. Determines the direction of the Floppy Disk Drive
(FDD) head movement (active = step in, inactive = step out)
during a seek operation. During reads or writes, DIR is inactive.
OD12, O2/12
VDD
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1.0 Signal/Pin Connection and Description (Continued)
Signal
DR0
Pin(s) I/O Buffer Type Power Well
Description
Drive Select 0. Decoded drive select output signal. DR0 is
controlled by bit 0 of the Digital Output Register (DOR).
OD12, O2/12
OD12, O2/12
VDD
VDD
70
71
O
O
Drive Select 1. Decoded drive select output signal. DR0 is
controlled by bit 1 of the Digital Output Register (DOR).
DR1
Data Rate 0. Reflects the value of bit 0 of the Configuration Control
Register (CCR) or the Data Rate Select Register (DSR), whichever
was written to last. Output from the pin is push-pull buffered.
O3/6
VDD
DRATE0
74
60
O
I
Disk Change. Indicates if the drive door has been opened. The
state of this pin is stored in the Digital Input Register (DIR). This pin
can also be configured as the RGATE data separator diagnostic input
signal via the MODE command.
INT
VDD
DSKCHG
Head Select. Determines which side of the FDD is accessed.
Active low selects side 1, inactive selects side 0.
OD12, O2/12
INT
VDD
VDD
VDD
HDSEL
INDEX
MTR0
61
73
72
O
I
Index. Indicates the beginning of an FDD track.
Motor Select 0. Active low, motor enable line for drives 0, controlled
by bits D7-4 of the Digital Output Register (DOR).
OD12, O2/12
O
Motor Select 1. Active low, motor enable lines for drives 1,
controlled by bits D7-4 of the Digital Output Register (DOR).
OD12, O2/12
INT
VDD
VDD
VDD
MTR1
RDATA
STEP
69
62
67
O
I
Read Data. Raw serial input data stream read from the FDD.
Step. Issues pulses to the disk drive at a software programmable
rate to move the head during a seek operation.
OD12, O2/12
O
Track 0. Indicates to the controller that the head of the selected
floppy disk drive is at track 0.
INT
VDD
TRK0
64
66
I
Write Data. Carries out the pre-compensated serial data that is
written to the floppy disk drive. Pre-compensation is software
selectable.
OD12, O2/12
VDD
WDATA
O
Write Gate. Enables the write circuitry of the selected disk drive.
WGATE is designed to prevent glitches during power up and
power down. This prevents writing to the disk when power is
cycled.
OD12, O2/12
VDD
WGATE
WP
65
63
O
I
Write Protected. Indicates that the disk in the selected drive is
write protected. A software programmable configuration bit (FDC
configuration at Index F0h, Logical Device 0) can force an active
write-protect indication to the FDC, regardless of the status of this
pin.
INT
VDD
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1.0 Signal/Pin Connection and Description (Continued)
1.4.6
Game Port
Signal
Pin(s) I/O Buffer Type Power Well
Description
INTS/OD12
INTS/OD12
INTS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
JOYAX
JOYAY
117
118
I/O
Joystick A X-Axis. Indicates X-axis position of joystick A.
Joystick A Y-Axis. Indicates Y-axis position of joystick A.
Joystick A Button 0. Indicates button 0 status of joystick A.
Joystick A Button 1. Indicates button 1 status of joystick A.
Joystick B X-Axis. Indicates X-axis position of joystick B.
Joystick BY-Axis. Indicates Y-axis position of joystick B.
Joystick B Button 0. Indicates button 0 status of joystick B.
Joystick B Button 1. Indicates button 1 status of joystick B.
I/O
JOYABTN0 119
JOYABTN1 120
I
INTS
I
I/O
I/O
I
INTS/OD12
INTS/OD12
INTS
JOYBX
JOYBY
121
122
JOYBBTN0 123
JOYBBTN1 124
INTS
I
1.4.7
General-Purpose Input/Output (GPIO) Ports
Pin/s I/O Buffer Type Power Well
Signal
Description
General-Purpose I/O Port 0, bits 0-7. Each pin is configured in-
dependently as input or I/O, with or without static pull-up and with
either open-drain or push-pull output type. The port support inter-
rupt assertion and each pin can be enabled or masked as an inter-
rupt source.
INTS
OD6, O3/6
/
VDD
GPIO00-07 2-9
I/O
I/O
GPIO10
GPIO11-14 53-56
GPO15 57
GPIO16-17 69, 71
21
INTS
/
General-Purpose I/O Port 1, bits 0-7. Same as Port 0. Bit 5 is
output only with low output as default.
VDD
OD6, O3/6
INTS
OD6, O3/6
/
General-Purpose I/O Port 2, bits 0-7. Similar to port 0 but
without the interrupt assertion capability.
VDD
GPIO20-27 117-124 I/O
GPIO30-33 125-128
General-Purpose I/O Port 3, bits 0-4. Similar to port 0 but
without the interrupt assertion capability.Bits 5, 6 and 7 are not
implemented.
INTS
/
VDD
GPIO34
1
I/O
OD6, O3/6
1.4.8
Signal
IRRX1
IRRX2_IRSL0 58
Infrared (IR)
Pin/s I/O Buffer Type Power Well
Description
IR Receive 1. Primary input to receive serial data from the IR
transceiver. Monitored during power-off for wake-up event
detection.
INTS
VDD, VSB
59
I
INTS/O3/6
INT/O3/6
INT/O3/6
VDD, VSB IRRX2 - IR Receive 2. Auxiliary IR receiver input to support a
I/O
I/O
I/O
second transceiver. Monitored during power-off for wake-up event
VDD
IRSL1
IRSL2
127
detection.
VDD
VDD
VDD
69
71
57
IRSL3-0 IR Select. Output are used to control the IR transceivers.
Input for PnP identification of plug-in IR transceiver (dongle).
After reset, the dual-function IRSLX pins wake up in input mode.
After the ID is read by the IR driver, they may be put into output
mode. The output mode is controlled by Serial Port 2.
INT
IRSL3
IRTX
I
O6/12
O
IR Transmit. IR serial output data.
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25
1.0 Signal/Pin Connection and Description (Continued)
1.4.9
Keyboard and Mouse Controller (KBC)
Pin/s I/O Buffer Type Power Well
Signal
Description
INT/OD2
VDD
GA20
9
I/O
Gate A20. KBC gate A20 (P21) output.
Keyboard Clock. Transfers the keyboard clock between the
SuperI/O chip and the external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P26 signal and is
connected internally to the T0 signal of the KBC. External pull-up
resistor to 5V is required (for PS/2 compliance). The pin is
monitored for wake-up event detection. To enable the activity
during power off, it must be pulled up to Keyboard and Mouse
standby voltage.
INTS/OD14 VDD, VSB
KBCLK
111
I/O
Keyboard Data. Transfers the keyboard data between the SuperI/O
chip and the external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P27 signal and is
connected internally to KBC P10. External pull-up resistor to 5V is
required (for PS/2 compliance). The pin is monitored for wake-up
event detection. To enable the activity during power off, it must be
pulled up to Keyboard and Mouse standby voltage.
INTS/OD14 VDD, VSB
KBDAT
KBRST
MCLK
112
8
I/O
I/O
I/O
INT/OD2
VDD
KBD Reset. Keyboard Reset (P20) output.
Mouse Clock. Transfers the mouse clock between the SuperI/O
chip and the external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P23 signal and is
connected internally to KBC T1. External pull-up resistor to 5V is
required (for PS/2 compliance). The pin is monitored for wake-up
event detection. To enable the activity during power off, it must be
pulled up to Keyboard and Mouse standby voltage.
INTS/OD14 VDD, VSB
113
Mouse Data. Transfers the mouse data between the SuperI/O
chip and the external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P22 signal and is
connected internally to KBC P11. External pull-up resistor to 5V is
required (for PS/2 compliance). The pin is monitored for wake-up
event detection. To enable the activity during power off, it must be
pulled up to Keyboard and Mouse standby voltage.
INTS/OD14 VDD, VSB
MDAT
114
I/O
I/O
P12, P16, 6,127,
P17
I/O Port. KBC open-drain signal for general-purpose input and
output, controlled by KBC firmware.
INT/OD2
VDD
7
1.4.10 Musical Instrument Digital Interface (MIDI) Port
Signal
MDTX
Pin(s) I/O Buffer Type Power Well
Description
MIDI Transmit. MIDI serial data output.
MIDI Receive. MIDI serial data input.
O3/6
INTS
VDD
VDD
125
126
O
I
MDRX
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26
1.0 Signal/Pin Connection and Description (Continued)
1.4.11 Parallel Port
Signal
ACK
Pin/s
79
I/O Buffer Type Power Well
Description
Acknowledge. Pulsed low by the printer to indicate that it has
received data from the Parallel Port.
INT
VDD
I
AFD - Automatic Feed. When low, instructs the printer to
automatically feed a line after printing each line. This pin is in
TRI-STATE after a 0 is loaded into the corresponding control
register bit. An external 4.7 KΩ pull-up resistor should be
attached to this pin.
OD14, O14/14
VDD
AFD_DSTRB 93
O
DSTRB - Data Strobe (EPP). Active low, used in EPP mode
to denote a data cycle. When the cycle is aborted, DSTRB
becomes inactive (high).
Busy. Set high by the printer when it cannot accept another
character.
INT
VDD
BUSY_WAIT 78
I
Wait. In EPP mode, the Parallel Port device uses this active
low signal to extend its access cycle.
INT
VDD
VDD
ERR
INIT
91
89
I
Error. Set active low by the printer when it detects an error.
Initialize. When low, initializes the printer. This signal is in
TRI-STATE after a 1 is loaded into the corresponding control
register bit. Use an external 4.7 KΩ pull-up resistor.
OD14, O14/14
O
PD7-5
PD4-3,
PD2, PD1
PD0
80-82
85-86
88, 90
92
Parallel Port Data. Transfer data to and from the peripheral
data bus and the appropriate Parallel Port data register. These
signals have a high current drive capability.
INT, O14/14
VDD
I/O
Paper End. Set high by the printer when it is out of paper. This
pin has an internal weak pull-up or pull-down resistor.
INT
INT
VDD
VDD
PE
77
76
I
I
Select. Set active high by the printer when the printer is
selected.
SLCT
SLIN - Select Input. When low, selects the printer. This signal
is in TRI-STATE after a 0 is loaded into the corresponding
control register bit. Uses an external 4.7 KΩ pull-up resistor.
OD14, O14/14
VDD
SLIN_ASTRB 87
STB_WRITE 94
O
O
ASTRB - Address Strobe (EPP). Active low, used in EPP
mode to denote an address or data cycle. When the cycle is
aborted, ASTRB becomes inactive (high).
STB - Data Strobe. When low, Indicates to the printer that
valid data is available at the printer port. This signal is in TRI-
STATE after a 0 is loaded into the corresponding control
register bit. An external 4.7 KΩ pull-up resistor should be
employed.
OD14, O14/14
VDD
WRITE - Write Strobe. Active low, used in EPP mode to
denote an address or data cycle. When the cycle is aborted,
WRITE becomes inactive (high).
1.4.12 Power and Ground
Signal
AVSS
Pin/s I/O Buffer Type Power Well
Description
45
44
I
I
AGND
PWR
-
-
Analog Ground.
Analog 3.3V Power Supply Provides power to the analog
AVDD
circuits.
Battery Power Supply. Provides battery back-up to the System
Wake-Up Control registers when VSB is lost (power-fail). The
pin is connected to the internal logic through a series resistor
for UL protection.
VBAT
INULR
30
I
-
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1.0 Signal/Pin Connection and Description (Continued)
Signal
VDD
Pin/s I/O Buffer Type Power Well
Description
Main 3.3V Power Supply.
20, 52,
I
I
I
PWR
PWR
GND
-
-
-
83, 115
Standby 3.3V Power Supply. Provides power to the Wake-Up
Control circuitry while the main power supply is turned off.
VSB
VSS
31
19, 51,
84, 116
Ground.
1.4.13 Protection
Signal Pin(s) I/O Buffer Type Power Well
CHASI
Description
Chassis Intrusion Input. Any change of this pin sets the
intrusion detection. For correct operation, this pin must be tied to
VSS when it is not used.
INC
VPP
29
I
Chassis Intrusion Output. When low, indicates that an intrusion
indication is set.
OD6
VSB
CHASO
28
O
1.4.14 Serial Port 1 and Serial Port 2
Signal
CTS1
Pin/s I/O Buffer Type Power Well
Description
100
108
Clear to Send. When low, indicates that the modem or other data
transfer device is ready to exchange data.
INTS
INTS
INTS
VDD
VDD
VDD
I
I
I
CTS2
DCD1
DCD2
95
103
Data Carrier Detected. When low, indicates that the modem or
other data transfer device has detected the data carrier.
DSR1
DSR2
96
104
Data Set Ready. When low, indicates that the data transfer device,
e.g., modem, is ready to establish a communications link.
Data Terminal Ready. When low, indicates to the modem or other
data transfer device that the UART is ready to establish a
communications link. After a system reset, these pins provide the
DTR function and set these signals to inactive high. Loopback
operation holds them inactive.
DTR1_
BOUT1
101
109
O3/6
VDD
O
Baud Output. Provides the associated serial channel baud rate
generator output signal if test mode is selected, i.e., bit 7 of the
EXCR1 Register is set.
DTR2_
BOUT2
DTR1_BOUT1 is used also as BADDR.
Ring Indicator. When low, indicates that a telephone ring signal
has been received by the modem. They are monitored during
power-off for wake-up event detection.
RI1
RI2
102
110
INTS
VDD, VSB
I
Request to Send. When low, indicates to the modem or other
data transfer device that the corresponding UART is ready to
exchange data. A system reset sets these signals to inactive high,
and loopback operation holds them inactive.
RTS1
RTS2
98
106
O3/6
VDD
O
RTS1 is used also as TEST.
Serial Input. Receive composite serial data from the
communications link (peripheral device, modem or other data
transfer device).
SIN1
SIN2
97
105
INTS
VDD
I
Serial Output. Send composite serial data to the communications
link (peripheral device, modem or other data transfer device).
These signals are set active high after a system reset.
SOUT1
SOUT2
99
107
O3/6
VDD
O
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1.0 Signal/Pin Connection and Description (Continued)
1.4.15 Strap Configuration
Signal
Pin/s I/O Buffer Type Power Well
Description
Base Address. Sampled by the trailing edge of the system reset
to determine the base address of the configuration Index-Data
register pair. During reset, it is pulled down by internal 30 KΩ
resistor.
INSTRP
VDD
BADDR
101
I
If no pull-up resistor is connected, it is sampled low, setting the
Index-Data pair at 2Eh-2Fh.
Connecting a 10 KΩ external pull-up resistor to VDD would make
it sample high, setting the Index-Data pair at 4Eh-4Fh.
Power Supply and LED Configuration. If no pull-up resistor is
connected to these pins, pins 33-35 and 37 function as
PWBTOUT, PSON, PWBTIN and SLPS5,respectively. Connecting
a 10K external pull-up resistor to VSB causes these pins to
PSLDC0
PSLDC1
99
107
1
INSTRP
I
I
VSB
function as GPOS0, GPOS1 and GPIS2 and AVI0, respectively.
Power Supply On Polarity. If no pull-up resistor is connected to
this pin, PSON is set active low with open-drain output.
Connecting a 10K external pull-up resistor to VSB causes PSON
1
INSTRP
PSONPOL 109
VSB
to be set to active high with push-pull output.
Test. If sampled high on the trailing edge of system reset, this
signal forces the device into test mode. This pin is for National
Semiconductor use only and should be left unconnected.
INSTRP
VDD
TEST
98
I
To put the chip in Test mode, connect an external pull-up to this
pin. Otherwise, leave it unconnected or connected to the UART
transceiver.
1. Make sure that the Serial Port driver is back-drive protected.
1.4.16 System Hardware Monitoring
Signal
ALARM
Pin(s) I/O Buffer Type Power Well
Description
OD6
VSB
27
O
I
Alarm. Alerts on voltage input mismatch.
INAN1
AVDD
AVI0-6
37-43
Analog Voltage Inputs. Analog inputs of the A/D converter.
D1N
D2N
47
49
Diode Cathode. Diodes 1 and 2 return current sink. Must be
grounded when not used.
INAN3
OAN2
AVDD
AVDD
I
D1P
D2P
48
50
Diode Anode. Diodes 1 and 2 current source. Connected to
remote discrete diodes.
O
Overtemperature Shutdown. Indicates that an overtemperature
was detected. See Section 2.8.9, the SuperI/O Configuration A
register, bit 0, for further details on which pin/s is/are active for
remote and local temperature sensing.
OTS1
OTS2
24
25
OD6
VSB
O
INAN1
AVDD
AVDD
TS1-3
VREF
47-49
46
I
Thermistor Sensors. Analog inputs.
Reference Voltage. Provides reference voltage for the on-chip
A/D circuits. An external reference voltage should be connected to
this input.
INAN2, OAN1
I/O
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1.0 Signal/Pin Connection and Description (Continued)
1.4.17 System Wake-Up Control
Signal
Pin/s I/O Buffer Type Power Well
Description
LED. VSB-powered pins with programmable outputs, each of
which can be used to produce a 0, 0.25, 0.5, 1, 4 Hz waveform for
LED control.
LED1
LED2
25
26
O12/12
VSB
O
INTS
INTS
VSB
VSB
GPIE6-7
58-59
I
General-Purpose Input Event.
/
General-Purpose I/O Event. VSB-powered pins.
GPIOE0-5 23-28
I/O
OD6, O3/6
INTS
VSB
VSB
General-Purpose Input Standby. VSB-powered pin.
General-Purpose Output Standby. VSB-powered pins.
GPIS2
35
I
OD6, O3/6
GPOS0-1
33-34
O
Power Supply On. Active level (low or high via PSONPOL strap)
instructs the main power supply to turn the power on. PSON
output signal is open-drain when active low and push-pull when
active high.
O4, OD12
VSB
PSON
34
35
O
Power Button In. Active (low) level indicates a user request to
turn the power on or off. This pin has an internal Schmitt-trigger
input buffer and debounce protection of at least 16 ms.
INTS
VSB
PWBTIN
I
Power Button Out. Active (low) level serves as output to the
chipset power button input.
OD12
VSB
PWBTOUT 33
PWUREQ 32
O
Power-Up Request. Active (low) level indicates that wake-up
event has occurred and causes the chipset to turn the power
supply on or to exit its current sleep state. The open-drain output
must be pulled up to VSB in order to function during power-off.
OD6
INTS
VSB
O
I
Telephone Line Ring. Detection of a pulse train on the RING pin
is a wake-up event that can activate the power-up request
(PWUREQ). The pin has a Schmitt-trigger input buffer, powered
VSB
RING
27
by VSB
.
Sleep State 3, 4 or 5. Input from this pin is assumed to be driven
by the system’s ACPI controller to indicate the system’s power
state.
INTS
INTS
VSB
SLPS3
SLPS5
36
37
I
I
Sleep State 4 or 5. Input from this pin is assumed to be driven by
the system’s ACPI controller to indicate the system’s power state.
VSB
1.4.18 WATCHDOG Timer (WDT)
Signal Pin/s I/O Buffer Type Power Well
WDO
Description
WATCHDOG Out. Low level indicates that the WATCHDOG Timer
has reached its time-out period without being retriggered.
OD6, O3/6
VDD
56
O
The output type and an optional pull-up are configurable.
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1.0 Signal/Pin Connection and Description (Continued)
1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS
The signals listed in Table 4 can optionally support internal pull-up (PU) and/or pull-down (PD) resistors. See Section 14.3
for the values of each resistor type.
Table 4. Internal Pull-Up and Pull-Down Resistors
Signal
Pin/s
Type
Comments
ACCESS.bus (ACB)
PU28
PU28
SCL
SDA
54
55
Programmable
Programmable
Game Port (GMP)
PU28
PU28
PU28
PU28
JOYABTN0
JOYABTN1
JOYBBTN0
JOYBBTN1
119
120
123
124
Programmable
Programmable
Programmable
Programmable
General-Purpose Input/Output (GPIO) Ports
PU28
PU28
GPIO00-07
2-9
Programmable
GPIO10
GPIO11-14
GPO15
21
53-56
57
Programmable
GPIO16-17
69, 71
PU28
PU28
GPIO20-27
117-124
Programmable
Programmable
GPIO30-33
GPIO34
125-128
1
Keyboard and Mouse Controller (KBC)
PU28
P12, P16, P17
6,127,7
Musical Instrument Digital Interface (MIDI) Port
PU25
MDRX
126
Programmable
Strap Configuration
PD60
PD60
PD60
PD60
PD60
BADDR
PSLDC0
PSLDC1
PSONPOL
TEST
101
99
Strap
Strap
Strap
Strap
Strap
107
109
98
Parallel Port
PU220
ACK
79
93
78
91
89
PU400
AFD_DSTRB
BUSY_WAIT
ERR
PD120
PU220
PU400
INIT
PU220
/
PE
77
Programmable
PD120
PD120
PU400
SLCT
76
87
SLIN_ASTRB
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1.0 Signal/Pin Connection and Description (Continued)
Signal
Pin/s
Type
Comments
PU400
STB_WRITE
94
System Wake-Up Control (SWC)
PU28
PU220
PU28
PU220
PU28
PU28
GPIOE0-5
GPIS2
23-28
35
Programmable
PSON/GPOS1
PWBTIN
PWBTOUT
RING
34
35
33
27
WATCHDOG Timer (WDT)
PU28
Programmable
WDO
56
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2.0 Device Architecture and Configuration
The PC87366 SuperI/O device comprises a collection of generic and proprietary functional blocks. Each functional block is
described in a separate chapter in this document. However, some parameters in the implementation of each functional block
may vary per SuperI/O device. This chapter describes the PC87366 structure and provides all logical device specific infor-
mation, including special implementation of generic blocks, system interface and device configuration.
2.1 OVERVIEW
The PC87366 consists of 15 logical devices, the host interface and a central set of configuration registers, all built around a
central internal bus. The internal bus is similar to an 8-bit ISA bus protocol. See Figure 1, which illustrates the blocks and
related logic.
The system interface serves as a bridge between the external LPC Interface and the internal bus. It supports 8-bit I/O Read,
8-bit I/O Write and 8-bit DMA transactions, as defined in Intel’s LPC Interface Specification, Revision 1.0.
The central configuration register set supports ACPI-compliant PnP configuration. The configuration registers are structured as
a subset of the Plug and Play Standard registers, defined in Appendix A of the Plug and Play ISA Specification, Revision 1.0a
by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA channels and IRQ lines)
are configured in, and managed by, the central configuration register set. In addition, some function-specific parameters are
configurable through the configuration registers and distributed to the functional blocks through special control signals.
2.2 CONFIGURATION STRUCTURE AND ACCESS
The configuration structure is comprised of a set of banked registers that are accessed via a pair of specialized registers.
2.2.1
The Index-Data Register Pair
Access to the SuperI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations.
The base address of this register pair is determined during reset, according to the state of the hardware strapping option on
the BADDR pin. Table 5 shows the selected base addresses as a function of BADDR.
Table 5. BADDR Strapping Options
I/O Address
BADDR
Index Register Data Register
0
1
2Eh
4Eh
2Fh
4Fh
The Index register is an 8-bit R/W register located at the selected base address (Base+0). It is used as a pointer to the con-
figuration register file and holds the index of the configuration register that is currently accessible via the Data register. Read-
ing the Index register returns the last value written to it (or the default of 00h after reset).
The Data register is an 8-bit virtual register, used as a data path to any configuration register. Accessing the Data register
actually accesses the configuration register that is currently pointed to by the Index register.
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2.0 Device Architecture and Configuration (Continued)
SIN1
GPIO30-34
GPIO
SOUT1
RTS1
GPIO20-27
Ports
DTR1/BOUT1
CTS1
DSR1
DCD1
GPIO10-14,16,17
Serial
Port 1
GPO15
GPIO00-07
RI1
WDO
WATCHDOG
Timer
SIN2
SOUT2
RTS2
DTR2/BOUT2
CTS2
DSR2
DCD2
RI2
Fan Speed
Control &
Monitor
FANIN0-2
Serial
Port 2
with IR
FANOUT0-2
SLCT
PE
BUSY_WAIT
ACK
SLIN_ASTRB
INIT
PD0-7
ERR
AFD_DSTRB
STB_WRITE
IRRX1,IRRX2
IRTX
IRSL0-2
IRSL3
Parallel
Port
P12,P16,P17
GA20
KBCLK
Keyboard
&
Mouse
KBDAT
KBRST
Controller
RDATA
WDATA
WGATE
HDSEL
MDAT
MCLK
DIR
SCL
SDA
ACCESS.
bus
STEP
TRK0
INDEX
FDC
DSKCHG
CLKIN
LRESET
LCLK
WP
MTR1,0
DR1,0
DENSEL
DRATE0
SERIRQ
Bus
Interface
LDRQ
LFRAME
LAD3-0
LED1,2
GPIE6,7
GPIOE0-5
GPIS2
GPOS0,1
PSON
PWBTIN
SMI
System
Wake-Up
Control
CHASI
CHASO
Protection
PWBTOUT
PWUREQ
RING
SLPS5
SLPS3
ALARM
AVI0-6
D1N,D2N
D1P,D2P
TS1-3
OTS1,2
System
Hardware
Monitoring
BADDR
PSLDC0,1
TEST
Strap
Config
PSONPOL
VREF
JOYAX
JOYAY
JOYABTN0
JOYABTN1
JOYBX
MDTX
MDRX
MIDI
Interface
Game
JOYBY
JOYBBTN0
JOYBBTN1
Config
& Control
Registers
Figure 1. PC87366 Detailed Block Diagram
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2.0 Device Architecture and Configuration (Continued)
2.2.2
Banked Logical Device Registers Structure
Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks,
where each bank holds the standard configuration registers of the corresponding logical device. Table 6 shows the LDN
values of the PC87366 functional blocks.
Figure 2 shows the structure of the standard configuration register file. The SuperI/O control and configuration registers are
not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and
device configuration registers are duplicated over 15 banks for 15 logical devices. Therefore, accessing a specific register
in a specific bank is performed by two dimensional indexing, where the LDN register selects the bank (or logical device) and
the Index register selects the register within the bank. Accessing the Data register while the Index register holds a value of
30h or higher results in a physical access to the Logical Device Configuration registers currently pointed to by the Index
register, within the logical device currently selected by the LDN register.
07h
Logical Device Number Register
SuperI/O Configuration Registers
20h
2Fh
Logical Device Control Register
30h
60h
63h
70h
71h
74h
75h
Standard Logical Device
Configuration Registers
Bank Select
Special (Vendor-defined)
Logical Device
F0h
FEh
Configuration Registers
Banks
(One per Logical Device)
Figure 2. Structure of the Standard Configuration Register File
Table 6. Logical Device Number (LDN) Assignments
LDN
Functional Block
Floppy Disk Controller (FDC)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Parallel Port (PP)
Serial Port 2 with IR (SP2)
Serial Port 1 (SP1)
System Wake-Up Control (SWC)
Keyboard and Mouse Controller (KBC) - Mouse interface
Keyboard and Mouse Controller (KBC) - Keyboard interface
General-Purpose I/O (GPIO) Ports
ACCESS.bus Interface (ACB)
Fan Speed Control and Monitor (FSCM)
WATCHDOG Timer (WDT)
Game Port (GMP)
Musical Instrument Digital Interface (MIDI) Port
Voltage Level Monitor (VLM)
Temperature Sensor (TMS)
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2.0 Device Architecture and Configuration (Continued)
Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non-existing
register) are ignored and read returns 00h on all addresses except for 74h and 75h (DMA configuration registers), which
returns 04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.
2.2.3 Standard Logical Device Configuration Register Definitions
Unless otherwise noted in Tables 7 through 12:
●
All registers are read/write.
●
All reserved bits return 0 on reads, except where noted otherwise. They must not be modified as it may cause un-
predictable results. Use read-modify-write to prevent the values of reserved bits from being changed during write.
●
Write only registers should not use read-modify-write during updates.
Table 7. Standard Control Registers
Index
Register Name
Description
07h
Logical Device This register selects the current logical device. See Table 6 for valid numbers. All
Number
other values are reserved.
20h - 2Fh
SuperI/O
Configuration
SuperI/O configuration registers and ID registers
Table 8. Logical Device Activate Register
Description
Index
Register Name
30h
Activate
Bit 0 - Logical device activation control
0: Disabled
1: Enabled
Bits 7-1 - Reserved
Table 9. I/O Space Configuration Registers
Description
Index
Register Name
60h
I/O Port Base
Address Bits (15-8) Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0.
Descriptor 0
61h
62h
63h
I/O Port Base
Address Bits (7-0) Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0.
Descriptor 0
I/O Port Base
Address Bits (15-8) Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 1.
Descriptor 1
I/O Port Base
Address Bits (7-0) Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 1.
Descriptor 1
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2.0 Device Architecture and Configuration (Continued)
Table 10. Interrupt Configuration Registers
Index
Register Name
Description
70h
Interrupt Number Sets IRQ, indicates the selected interrupt number and enables wake-up on IRQ.
and Wake-Up on
Bit 4 - Enables wake-up on the IRQ of the logical device. When enabled, IRQ
IRQ Enable
assertion triggers a wake-up event.
0: Disabled (default)
1: Enabled
Bits 3-0 select the interrupt number. A value of 1 selects IRQL1. A value of 15
selects IRQL15. IRQL0 is not a valid interrupt selection and represent no interrupt
selection.
Note: If the BIOS routine that sets IRQ does not use a Read-Modify-Write
sequence, it might reset bit 4. To ensure that the system wakes up, the BIOS must
set bit 4 before the system goes to sleep.
71h
Interrupt Request Indicates the type and level of the interrupt request level selected in the previous
Type Select
register.
If a logical device supports only one type of interrupt, this register may be read
only.
Bits 7-2 - Reserved.
Bit 1 - Level of the interrupt request selected in the previous register
0: Low polarity
1: High polarity
Bit 0 - Type of interrupt request selected in the previous register
0: Edge
1: Level
Table 11. DMA Configuration Registers
Description
Index
Register Name
74h
DMA Channel
Select 0
Indicates selected DMA channel for DMA 0 of the logical device (0 - The first DMA
channel in case of using more than one DMA channel).
Bits 2-0 select the DMA channel for DMA 0. The valid choices are 0-3, where a
value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
The values 5-7 are reserved.
75h
DMA Channel
Select 1
Indicates selected DMA channel for DMA 1 of the logical device (1 - The second
DMA channel in case of using more than one DMA channel).
Bits 2-0 select the DMA channel for DMA 1. The valid choices are 0-3, where a
value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
The values 5-7 are reserved.
Table 12. Special Logical Device Configuration Registers
Index
Register Name
Description
F0h-FEh
Logical Device
Configuration
Special (vendor-defined) configuration options.
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2.0 Device Architecture and Configuration (Continued)
2.2.4
Standard Configuration Registers
Index
Register Name
Logical Device Number
07h
20h
21h
22h
23h
24h
25h
26h
27h
28h
2Ah
2Bh
2Ch
2Dh
2Eh
30h
60h
61h
62h
63h
70h
SuperI/O ID
SuperI/O Configuration 1
SuperI/O Configuration 2
SuperI/O Configuration 3
SuperI/O Configuration 4
SuperI/O Configuration 5
SuperI/O Control and
Configuration Registers
SuperI/O Configuration 6
SuperI/O Revision ID
SuperI/O Configuration 8
SuperI/O Configuration A
SuperI/O Configuration B
SuperI/O Configuration C
SuperI/O Configuration D
Reserved exclusively for National use
Logical Device Control (Activate)
I/O Base Address Descriptor 0 Bits 15-8
I/O Base Address Descriptor 0 Bits 7-0
I/O Base Address Descriptor 1 Bits 15-8
I/O Base Address Descriptor 1 Bits 7-0
Logical Device Control and
Configuration Registers -
one per Logical Device
(some are optional)
Interrupt Number and Wake-Up on IRQ Enable
(see note, p. 37)
71h
74h
75h
F0h
F1h
F2h
IRQ Type Select
DMA Channel Select 0
DMA Channel Select 1
Device Specific Logical Device Configuration 1
Device Specific Logical Device Configuration 2
Device Specific Logical Device Configuration 3
Figure 3. Configuration Register Map
SuperI/O Control and Configuration Registers
The SuperI/O Configuration registers at indexes 20h and 27h are mainly used for part identification, global power manage-
ment and the selection of pin multiplexing options. For details, see Section 2.8.
Logical Device Control and Configuration Registers
A subset of these registers is implemented for each logical device. See functional block description in the following sections.
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2.0 Device Architecture and Configuration (Continued)
Control
The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate reg-
ister controls the activation of the associated function block. Activation of the block enables access to the block’s registers
and attaches its system resources, which are unused as long as the block is not activated. Other effects may apply on a
function-specific basis (such as clock enable and active pinout signaling).
Standard Configuration
The standard configuration registers are used to manage the PnP resource allocation to the functional blocks. The I/O port
base address descriptor 0 is a pair of registers at Index 60-61h, holding the (first or only) 16-bit base address for the register
set of the functional block. An optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices
with more than one continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select
(index 71h) allocate an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel
to the block, where applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable.
Special Configuration
The vendor-defined registers, starting at index F0h, are used to control function-specific parameters such as operation
modes, power saving modes, pin TRI-STATE, clock rate selection and non-standard extensions to generic functions.
2.2.5
Default Configuration Setup
The default configuration setup of the PC87366 can include four reset types, described below. See specific register descrip-
tions for the bits affected by each reset type.
• Software Reset
This reset is enabled by bit 1 of the SIOCF1 register, which resets all logical devices. A software reset also resets most
bits in the SuperI/O control and configuration registers (see Section 2.8 for the bits not affected). This reset does not
affect register bits that are locked for write access.
• Hardware Reset
This reset is activated by the assertion of the LRESET input. It resets all logical devices, with the exception of the System
Wake-Up Control (SWC). It also resets all SuperI/O control and configuration registers, except for those that are battery-
backed.
• VPP Power-Up Reset
This reset is activated when either VSB or VBAT is powered up after both have been off. VPP is an internal voltage which
is a combination of VSB and VBAT. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the
Device Characteristics chapter; otherwise, VBAT is used as the VPP source. This reset resets all registers whose values
are retained by VPP
.
• VSB Power-Up Reset
This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by
VPP. This reset is activated after VSB is powered up.
In the event of a hardware reset, the PC87366 wakes up with the following default configuration setup:
— The configuration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 5.
— The Keyboard Controller (KBC) is active and all other logical devices are disabled, with the exception of the SWC,
which remains functional but whose registers cannot be accessed.
— All multiplexed GPIO pins, except for pins whose function is controlled by battery-backed registers and pins 8 and 9
(which are controlled by bits 1 and 0 of the SIOCF3 register) are configured as GPIO pins, with an internal static pull-
up (default direction is input).
In the event of either a hardware or a software reset, the PC87366 wakes up with the following default configuration setup:
— The legacy devices are assigned with their legacy system resource allocation.
— The National proprietary functions are not assigned with any default resources and the default values of their base
addresses are all 00h.
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2.0 Device Architecture and Configuration (Continued)
2.2.6
Power States
The following terminology is used in this document to describe the various possible power states:
• Power On
Both VSB and VDD are active.
• Power Off
VSB is active and VDD is inactive.
• Power Fail
Both VSB and VDD are inactive.
Note: The following state is illegal: VDD active and VSB inactive.
2.2.7
Address Decoding
A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional
blocks. However, the number of configurable bits in the base address registers varies for each logical device.
The lower 1, 2, 3, 4 or 5 address bits are decoded within the functional block to determine the offset of the accessed register
within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base
address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base address
register are forced to 0 (read only) and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size
of the I/O range.
The base address of the FDC, Serial Port 1, Serial Port 2 with IR and KBC are limited to the I/O address range of 00h to
7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h.
The addresses of the non-legacy logical devices, including the GMP and the MIDI, are configurable within the full 16-bit ad-
dress range (up to FFFXh).
In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel
Port). The KBC has two I/O descriptors with some implied dependency between them. For more details, see the description
of the base address register for each logical device.
2.3 PROTECTION
The PC87366 provides features to protect the PC at mechanical and software levels.
At the mechanical level, the device can detect intrusion to the chassis of the PC.
At the software level, the device can be locked to protect configuration bits or alteration of the hardware configuration of the
device, as well as internal GPIO settings and several types of configuration settings.
All protection mechanisms can optionally be used.
2.3.1
Chassis Intrusion Detection
The Chassis Intrusion Detection mechanism is based on the state of pin 29, CHASI. This pin reflects the status of an external
switch that indicates the PC chassis state.
Bits 4,5 of the SIOCFB register monitor this pin and provide two types of information. Bit 4 reports a previously detected
chassis intrusion, defined as any kind of transition on the CHASI pin. Bit 5 reflects the momentary value of the CHASI pin.
For further details on the SIOCFB register, see Section 2.8.10.
To prevent the CHASI pin from detecting a false chassis intrusion, it is implemented with an internal noise filter.
A chassis intrusion event can be reported to the host system by either software or hardware. When using software, the sys-
tem must read the SIOCFB register to check if an intrusion event has occurred. When using hardware, the device provides
the following means for indicating chassis intrusion:
●
Dedicated output (CHASO).
●
SMI assertion.
To use the CHASO function, it must first be selected by setting bit 6 of the SIOCFA register to 1. Thereafter, whenever a
chassis intrusion is detected, the CHASO pin reflects the value of bit 4 of the SIOCFB register. When bit 4 of this register is
set to 1, the CHASO pin is asserted (driven low). It is de-asserted when this bit is cleared.
To use the SMI assertion, it must either be selected on its pin or routed to interrupt request channel 2. To select SMI on its
pin, set bit 2 of the SIOCF3 register to 1 (for further details, see Section 2.8.4). To route the SMI signal to interrupt request
channel 2, set bit 4 of the SIOCF5 register to 1 (for further details, see Section 2.8.6). In addition, the chassis intrusion event
must be routed to the SMI signal by setting bit 5 of the SIOCF8 register to 1 (for further details, see Section 2.8.8). Thereafter,
whenever a chassis intrusion is detected, the SMI signal reflects bit 4 of the SIOCFB register. When bit 4 of this register is
set to 1, the SMI signal and the selected target indication are asserted (driven low). The SMI signal is de-asserted when this
bit 4 is cleared.
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2.0 Device Architecture and Configuration (Continued)
2.3.2
Pin Configuration Lock
To lock the pin configuration of the PC87366 in order to prevent unwanted changes to hardware configuration, set bit 7 of
the SIOCF1 register to 1. Setting this bit causes all function select configuration bits, including those that are battery backed,
to become read only bits. This bit can only be cleared by a hardware reset.
2.3.3
GPIO Pin Function Lock
The PC87366 is capable of locking the attributes of each GPIO or Standby GPIO pin. The following attributes can be locked:
●
Output enable.
●
Output type.
●
Static pull-up.
●
Driven data.
GPIO pins are locked per pin by setting the Lock bit in the appropriate GPIO Pin Configuration register. When the Lock bit
is set, the configuration of the associated GPIO pin can only be released by a hardware reset.
Standby GPIO pins are locked in the same manner by setting the Lock bit in the appropriate Standby GPIO Pin Configuration
registers. However, once a Standby GPIO pin is locked, its locked attributes can only be released with a VSB power-up reset.
2.4 POWER SUPPLY CONTROL (PSC)
The PC87366 includes hardware that can be used to ease the system’s control over the computer’s power supply. This hard-
ware is implemented as a state machine that determines the required state of the power supply based on several input sig-
nals. It also connects to the system’s ACPI controller to share information about the system’s power state via specific
interface signals.
The PSC uses the pin functions SLPS3, SLPS5, PWBTIN, PWBTOUT and PSON. These functions are optional on their
respective pins and must be selected to enable the PSC by setting the values of the PSLDC0,1 strap pins (see Table 14).
Once enabled, the PSC can be operated in one of two modes, according to the value of bit 0 (Power Button Mode) of the
SIOCFD register:
●
ACPI mode.
●
Legacy mode.
ACPI Mode
When the PSC is operated in ACPI mode (bit 0 of the SIOCFD register is set to 1), the ACPI controller of the system controls
the system’s power supply by means of the SLPS3 state. When SLPS3 is set to 0, the power supply turns off; when it is set
to 1, the power supply turns on. The state of the PSON output signal (either ON or OFF) is identical to the state of the SLPS3
input signal. The polarity of PSON is set by the PSONPOL strap.
The only case in which the PSC affects the value of the PSON output is when a Crowbar condition occurs. A Crowbar con-
dition is defined as the state in which PSON has been active for a certain period of time but the system’s power supply re-
mains inactive. In this case, PSON is forced inactive, and the PWBTOUT output is pulsed to indicate to the ACPI controller
that SLPS3 must be driven low, thus indirectly inactivating PSON and preventing a deadlock. For a detailed description of
the Crowbar mechanism, see Crowbar Condition on the following page(s).
In ACPI mode, during regular operation, the PWBTOUT output is pulsed when either of the following events occurs:
●
PWBTIN is pulsed.
●
A wake-up event that is routed to PWBTOUT.
A wake-up event that is routed to the power button output can cause PWBTOUT to be pulsed in ACPI mode if one of the
following conditions is met:
●
SLPS5 is active.
●
Enable Power Button Pulse on S3 (bit 3) of the SWC WK_CFG register is set to 1.
However, when in ACPI mode, PWBTIN and PWBTOUT activity has no effect on the PSON output. The power button mech-
anism can have an indirect effect on PSON only if PWBTOUT is connected to the power button input of the ACPI controller,
thus affecting the SLPS3 signal.
Legacy Mode
When the PSC is operated in Legacy mode (bit 0 of the SIOCFD register is set to 0), the PC87366 controls the system’s
power supply. In this mode, the PSON output signal is set by the PC87366 according to the following factors: the state of
input signals, the state of the power supply lines, power button activity and certain configuration bits. Although the ACPI con-
troller does not control the system’s power supply, it tracks the system’s power state. For this purpose, the PC87366 ma-
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2.0 Device Architecture and Configuration (Continued)
nipulates the PWBTOUT so that the ACPI controller is always synchronized with the actual state of the PSON output. This
synchronization mechanism assumes that PWBTOUT is connected to the power button input of the ACPI controller. See a
schematic state diagram of the Legacy PSC mechanism in Figure 4.
VSB
Power
Fail
Power-Up
Reset
VSB Present AND Straps Sampled
Resume AND Last State is ON
Check
Resume
Mode
Resume AND Last State Is OFF
OR
No Resume AND ACPI Is ON
Synchronization Done
No Resume AND ACPI Is OFF
Synchronize
ACPI
PWBTOUT Falling Edge
ON
OFF
PWBTOUT Falling Edge
OR
Software Power Supply Off Command
Figure 4. Legacy Power Supply Control State Diagram
When VSB is first applied, the PSC state machine is initialized to Power Fail state. In this state, the mechanism waits for the
PC87366 to be initialized according to strap options. Then the PSC enters Check Resume Mode state. In this state, the PSC
checks if Resume to Last PSON state is enabled.
If Resume to Last PSON is enabled, PSON immediately resumes the state it was in when VSB was lost. To enable this mech-
anism, set bit 2 of the SIOCFD register to 1 and program the ACPI controller to resume OFF state (SLPS3 = 0) after power
fail recovery to allow the PSC to operate properly. If the last state of PSON was OFF, assuming that the ACPI controller also
resumed OFF state, PSON is set to inactive and the PSC enters OFF state. If the last state was ON, under the same as-
sumption, the ACPI controller must be notified to change its state to ON. This is done by pulsing the PWBTOUT output. This
synchronization pulse is generated when the PSC is in Synchronize ACPI state.
If Resume Last PSON State is disabled, the PSC enters either ON or OFF state according to the value of the SLPS3 input,
as follows:
●
If SLPS3 is low (active, state OFF), the PSC enters OFF state.
●
If SLPS3 is high (inactive, state ON), the PSC enters ON state.
Since SLPS3 reflects the state of the ACPI controller, the PSC actually resumes the current state of the ACPI controller.
After entering either ON or OFF states, PSC moves between these two states on the following conditions:
●
A falling edge on PWBTOUT (generated internally) changes the state from ON to OFF or vice versa.
●
A Software Power Supply Off command, writing 1 to Power Supply Off (bit 1) of the SIOCFD register, changes the
state from ON to OFF.
Since many wake-up events can activate the PWBTOUT signal, these events can actually cause the PSC to change its state
from OFF to ON, thus activating the PSON output.
As in ACPI mode, the Crowbar protection mechanism is also active in Legacy mode. However, in this mode, when a Crowbar
condition is detected, the PSC returns to OFF state, thus inactivating the PSON output. Also, to synchronize the APCI con-
troller, the PWBTOUT is pulsed to bring it to the correct state.
Table 13 summarizes the bit states that affect PSON VSB power-up default state.
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2.0 Device Architecture and Configuration (Continued)
Table 13. PSON VSB Power-Up Default State
Resume Last
PSON State
(SIOCFD, Bit 2)
PSON VSB Power-Up
Last PSON
State
Default
1
1
0
0
1
X
0
1
Same as SLPS3 state
Crowbar Condition
A Crowbar condition is a situation in which the signal that directly controls the system’s power supply is active for a certain
duration of time without a power supply response. To prevent this deadlock and enable reactivation of the power supply, a
special crowbar mechanism is included in the PSC logic.
Once the PSON is activated, assuming the power supply is off, a timer in the PSC logic starts counting. If this timer reaches
its terminal count before the power supply becomes active, the PSC detects a Crowbar condition. In this case, PSON is
deactivated and the PSC makes sure that the ACPI state of the system is changed to OFF.
The time that causes a Crowbar condition is defined as the Crowbar Timeout. The Crowbar Timeout of the PSC can be pro-
grammed to values between 0.5-2.25 seconds. This Timeout value is set by writing the appropriate value to bits 4-3 of the
SIOCFD register. For further details, refer to the description of this register in Section 2.8.12.
2.5 LED OPERATION AND STATES
The device supports up to two LEDs, depending on Pin 25 and Pin 26 Function Select (bits 1-2 and bit 3) of the SIOCFA
register. The polarity of both LEDs is determined by LED Polarity Control (bit 7) of the SIOCFD register.
The device provides modes for software LED control when in power-on state. The device also provides modes for hardware
LED control. This enables the LEDs to support features such as power and error indication.
The LEDs may be operated in Software, Hardware1 or Hardware 2 modes. These modes are set by LED Mode Control (bits
2 and 3) of the SIOCFB register. Each LED can be set to On or Off or to blink at different rates by means of bits 0-2 (LED1)
and bits 3-5 (LED2) of the SIOCFC register.
When in power-on state (both VDD and VSB exist), the LEDs are software controlled. When in power-fail state (no VSB and
no VDD), the LEDs are off. Note, however, that these rules are overridden when using the Hardware modes. Table 14 shows
the effect of Hardware modes 1 and 2 on LED operation.
Table 14. Effect of Hardware Modes 1 and 2 on LED Operation
Mode
Hardware1
System State
VSB power-up reset
Power off (VSB, no VDD
LED1
LED2
Off
1 Hz blink, 50% duty cycle
1 Hz blink, 50% duty cycle
(SIOCFB, bits 3-2=01)
)
Software controlled
Software controlled
ACPI mode and
Sleep State 3
Software controlled
ACPI mode, Sleep State 5,
bit 6 = 1 in SIOCFC register
and Power Supply Control
enabled
Software controlled
Software controlled
Hardware 2
(SIOCFB, bits 3-2=10)
ACPI mode, any other
configuration
Off
Off
Off
Off
Legacy mode and power off
(no VDD
)
2.6 POWER SUPPLY CONTROL AND LED CONFIGURATION
A combination of two strap pins (Power Supply and LED Configuration 0 and 1, PSLDC0,1, pins 99 and 107, respectively)
determines the configuration of the power supply control pins and LEDs. Both pins 99 and 107 have weak pull-downs and
are sampled on VSB power-up reset. Table 15 describes how they affect the chip configuration.
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2.0 Device Architecture and Configuration (Continued)
Table 15. PSLDC0,1 Configuration Options
PSLDC0
(Pin 99)
PSLDC1
(Pin 107)
Power Supply Control
LED2
0
0
1
1
0
1
0
1
Enabled (default)
Disabled
Not selected (default)
Selected
Disabled
Not selected
Selected
Enabled
2.7 REGISTER TYPE ABBREVIATIONS
The following abbreviations are used to indicate the Register Type:
●
R/W = Read/Write.
●
R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
●
●
●
W = Write.
RO = Read Only.
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
2.8 SUPERI/O CONFIGURATION REGISTERS
This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of 20h
- 2Eh). See Table 16 for a summary and directory of these registers.
Table 16. SuperI/O Configuration Registers
Index Mnemonic
20h SID
Register Name
SuperI/O ID
Power Well
VDD
Type
RO
Section
2.8.1
21h SIOCF1
22h SIOCF2
23h SIOCF3
24h SIOCF4
25h SIOCF5
27h SRID
VDD
R/W
R/W
R/W
R/W
R/W
RO
2.8.2
SuperI/O Configuration 1
SuperI/O Configuration 2
SuperI/O Configuration 3
SuperI/O Configuration 4
SuperI/O Configuration 5
SuperI/O Revision ID
VDD
2.8.3
VDD
2.8.4
VDD
2.8.5
VDD
2.8.6
VDD
2.8.7
28h SIOCF8
2Ah SIOCFA
2Bh SIOCFB
2Ch SIOCFC
2Dh SIOCFD
SuperI/O Configuration 8
SuperI/O Configuration A
SuperI/O Configuration B
SuperI/O Configuration C
SuperI/O Configuration D
VDD
R/W
R/W
R/W
R/W
R/W
2.8.8
VPP
2.8.9
VPP
2.8.10
2.8.11
2.8.12
VPP
VPP
2Eh Reserved exclusively for National use
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2.0 Device Architecture and Configuration (Continued)
2.8.1
SuperI/O ID Register (SID)
This register contains the identity number of the chip. The PC87366 is identified by the value E9h.
Location:
Type:
Index 20h
RO
Bit
7
6
1
5
1
4
0
3
1
2
0
1
0
0
1
Name
Reset
Chip ID
1
2.8.2
SuperI/O Configuration 1 Register (SIOCF1)
Location:
Type:
Index 21h
Varies per bit
Bit
7
6
5
4
3
2
1
SW Reset
0
0
Pins
Pin
Function
Select Lock
Global
Device
Enable
117-127
Function
Select
Number of DMA Wait
States
Number of I/O Wait
States
Name
Reset
0
0
0
1
0
0
1
Bit
Description
7
Pin Function Select Lock. This bit determines if the bits (located in the SIOCF1, 2, 3, 4, 5, A and B registers)
that select pin functions are read only or read/write. When set to 1, this bit can only be cleared by a hardware
reset.
0: Bits are R/W
1: Bits are RO
6
Pins 117-127 Function Select. This is a RO bit.
0: Pins 117-127 function set by SIOCF4 (default)
1: Reserved
5-4 Number of DMA Wait States. This is a R/W bit.
Bits
5 4
Number
0 0
0 1
1 0
1 1
Reserved
Two (default)
Six
Twelve
3-2 Number of I/O Wait States. This is a R/W bit.
Bits
3 2
Number
0 0
0 1
1 0
1 1
Zero (default)
Two
Six
Twelve
1
0
SW Reset. Read always returns 0. This is a R/W bit.
0: Ignored (default)
1: Resets all the logical devices that are reset by hardware reset (with the exception of the lock bits) and resets
the registers of the SWC, VLM and TMS
Global Device Enable. This bit controls the function enable of all the PC87366 logical devices, except System
Wake-Up Control (SWC). With the exception of SWC, it allows all logical devices to be disabled simultaneously
by writing to a single bit. This is a R/W bit.
0: All logical devices in the PC87366 are disabled, except SWC, VLM and TMS
1: Each logical device is enabled according to its Activate register (Index 30h) (default)
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2.0 Device Architecture and Configuration (Continued)
2.8.3
SuperI/O Configuration 2 Register (SIOCF2)
Location:
Type:
Index 22h
R/W
Bit
7
6
5
4
3
2
1
0
0
0
Pin 7
Function
Select
Pin 6
Function
Select
Pin 5
Function
Select
Pin 4
Function
Select
Pin 3
Function
Select
Pin 2
Function
Select
Pin 1
Function
Select
Name
Reset
0
0
0
0
0
0
Bit
Description
7
Pin 7 Function Select.
0: GPIO05 (default)
1: P17
6
5
4
3
2
Pin 6 Function Select.
0: GPIO04 (default)
1: P12
Pin 5 Function Select.
0: GPIO03 (default)
1: FANOUT0
Pin 4 Function Select.
0: GPIO02 (default)
1: FANIN0
Pin 3 Function Select.
0: GPIO01 (default)
1: FANOUT1
Pin 2 Function Select.
0: GPIO00 (default)
1: FANIN1
1-0 Pin 1 Function Select.
Bits
1 0
Function
0 0
0 1
1 x
GPIO34 (default)
FANOUT2
Reserved
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2.0 Device Architecture and Configuration (Continued)
2.8.4
SuperI/O Configuration 3 Register (SIOCF3)
Location:
Type:
Index 23h
Varies per bit
Bit
7
6
5
4
3
Reserved
0
2
1
0
Pin 57
Function
Select
Pin 56
Function
Select
Pins 54, 55
Function
Select
Pin 53
Function
Select
Pin 21
Function
Select
Pin 9
Function
Select
Pin 8
Function
Select
Name
Reset
0
0
0
0
0
1
1
Bit
Description
7
Pin 57 Function Select. This is a R/W bit.
0: GPO15 (default)
1: IRTX
6
5
4
Pin 56 Function Select. This is a R/W bit.
0: GPIO14 (default)
1: WDO
Pins 54, 55 Function Select. This is a R/W bit.
0: GPIO12/GPIO13 (default)
1: SCL/SDA
Pin 53 Function Select. This is a RO bit.
0: GPIO11 (default)
1: Reserved
3
2
Reserved.
Pin 21 Function Select. This is a R/W bit.
0: GPIO10 (default)
1: SMI
1
0
Pin 9 Function Select. This is a R/W bit.
0: GPIO07
1: GA20 (P21) (default)
Pin 8 Function Select. This is a R/W bit.
0: GPIO06
1: KBRST (P20) (default)
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2.0 Device Architecture and Configuration (Continued)
2.8.5
SuperI/O Configuration 4 Register (SIOCF4)
Location:
Type:
Index 24h
R/W
Bit
7
6
0
5
4
3
0
2
0
1
0
0
0
Pin 127
Function
Select
Pins 125,126 Pins 117-124
Function
Select
Pin 71
Function
Select
Pin 69
Function
Select
Name
Reset
Function
Select
0
0
0
Bit
Description
7-6 Pin 127 Function Select.
Bits
7 6
Function
0 0
0 1
1 0
1 1
GPIO32 (default)
P16
IRSL1
Reserved
5
4
Pins 125,126 Function Select.
0: GPIO30,31 (default)
1: MDTX, MDRX
Pins 117-124 Function Select.
0: GPIO20-27 (default)
1: JOYAX, JOYAY, JOYABTN0, JOYABTN1, JOYBX, JOYBY, JOYBBTN0, JOYBBTN1
3-2 Pin 71 Function Select.
Bits
3 2
Function
0 0
0 1
1 0
1 1
GPIO17 (default)
DR1
IRSL3
Reserved
1-0 Pin 69 Function Select.
Bits
1 0
Function
0 0
0 1
1 0
1 1
GPIO16 (default)
MTR1
IRSL2
Reserved
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2.0 Device Architecture and Configuration (Continued)
2.8.6
SuperI/O Configuration 5 Register (SIOCF5)
Location:
Type:
Index 25h
Varies per bit
Bit
7
6
5
0
4
3
0
2
0
1
0
0
0
VID0 and VID1
Route
Pin 128
Function
Select
SMI to IRQ2
Enable
Name
Reset
Reserved
Select
0
0
0
Bit
Description
7-5 VID0 and VID1 Route Select. Defines the routing of GPIO inputs to the VLM VID register. This is a R/W
bit.
Bits
7 6 5
Route Select
0 0 0
0 0 1
0 1 0
0 1 1
VID0 and VID1 are not routed.
VID4-VID0 are routed from GPIO11-13, GPIO16, GPIO17. Only CPU0 is supported.
VID4-VID0 are routed from GPIO05, GPIO12-14, GPIO32. Only CPU0 is supported.
When CPU0 is selected: VID4-VID0 are routed from GPIO20-24;
when CPU1 is selected: VID4-VID0 are routed from GPIO25-27, GPIO30, GPIO31
VID4-VID0 are routed from GPIO11-13, GPIO16, GPIO17; processor select control is routed to
GPIO14, which is configured as output.
1 0 0
Other Reserved
4
SMI to IRQ2 Enable. This is a R/W bit.
0: Disabled (default)
1: Enabled
3-2 Reserved.
1-0 Pin 128 Function Select. This is a R/W bit.
Bits
1 0
Function
0 0
0 1
1 x
GPIO33 (default)
FANIN2
Reserved
2.8.7
SuperI/O Revision ID Register (SRID)
This register contains the identity number of the chip revision. SRID is incremented on each revision.
Location:
Type:
Index 27h
RO
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2.0 Device Architecture and Configuration (Continued)
2.8.8
SuperI/O Configuration 8 Register (SIOCF8)
Location:
Type:
Index 28h
R/W
Bit
7
6
5
4
3
2
1
0
Mouse IRQ
to SMI
Enable
VLM to SMI TMS to SMI CHASO to
KBD IRQ to KBD P12 to GPI to SMI WDO to SMI
Name
Reset
Enable
Enable
SMI Enable
SMI Enable SMI Enable
Enable
Enable
0
0
0
0
0
0
0
0
Bit
Description
7
VLM to SMI Enable.
0: Disabled (default)
1: Enabled
6
5
4
3
2
1
0
TMS to SMI Enable.
0: Disabled (default)
1: Enabled
CHASO to SMI Enable.
0: Disabled (default)
1: Enabled:
Mouse IRQ to SMI Enable.
0: Disabled (default)
1: Enabled
KBD IRQ to SMI Enable.
0: Disabled (default)
1: Enabled
KBD P12 to SMI Enable.
0: Disabled (default)
1: Enabled
GPI to SMI Enable.
0: Disabled (default)
1: Enabled
WDO to SMI Enable.
0: Disabled (default)
1: Enabled
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2.0 Device Architecture and Configuration (Continued)
2.8.9
SuperI/O Configuration A Register (SIOCFA)
This is a battery-backed register.
Location:
Type:
Index 2Ah
Varies per bit
Bit
7
6
5
0
4
0
3
2
0
1
0
0
Pins 33-37
Function
Select
Pin 28
Function
Select
Pin 27
Function
Select
Pin 26
Function
Select
Pin 25
Function
Select
Pin 24
Function
Select
Name
Reset
Strap
0
0
0
Bit
Description
7
Pins 33-37 Function Select. This is a RO bit. The function of the pin selected is determined during VSB power-
up by the PSLDC0,1 straps.
0: PWBTOUT, PSON, PWBTIN, SLPS3, SLPS5
1: GPOS0, GPOS1, GPIS2, SLPS3, AVI0
6
Pin 28 Function Select. This is a R/W bit.
0: GPIOE5 (default at VPP power-up reset)
1: CHASO
5-4 Pin 27 Function Select. This is a R/W bit.
Bits
5 4
Function
0 0
0 1
1 0
GPIOE4 (default at VPP power-up reset)
RING
ALARM
Other Reserved
3
Pin 26 Function Select. This is a R/W bit.
0: GPIOE3 (default at VPP power-up reset)
1: LED2
2-1 Pin 25 Function Select. This is a R/W bit.
Bits
2 1
Function
0 0
0 1
1 0
GPIOE2 (default at VPP power-up reset)
LED1
OTS2 (can be enabled only if OTS1 is enabled)
Other Reserved
0
Pin 24 Function Select.
0: GPIOE1 (default at VPP power-up reset)
1: OTS1. OTS1 functionality changes when OTS2 is enabled. The following table summarizes which OTS output
is affected when an overtemperature is detected by any of the sources. A ‘Y’ indicates that the pin is active
for this condition; an ‘N’ indicates that it is inactive.
1 OTS Pin
OTS1
2 OTS Pins
Source
OTS1
OTS2
Remote 1
Remote 2
Local
Y
Y
Y
Y
Y
N
Y
Y
N
Y
N
N
VLM
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2.0 Device Architecture and Configuration (Continued)
2.8.10 SuperI/O Configuration B Register (SIOCFB)
This is a battery-backed register.
Location:
Type:
Index 2Bh
Varies per bit
Bit
7
Reserved
0
6
5
4
3
2
1
0
Pins 47-49
Function
Select
Pin 59
Function
Select
Pin 58
Function
Select
Intrusion
Level
Intrusion
Status
Name
Reset
LED Mode Control
0
X
1
0
0
0
0
Bit
Description
7
6
Reserved.
Pins 47-49 Function Select.
0: Pins 47-49 enabled as D1N, D1P and D2N by the TMS (default)
1 Pins 47-49 enabled as TS1, TS2 and TS3 by the VLM. For further details, see the TMS Configuration register
setting.
5
4
Intrusion Level. This is a RO bit that reflects the value of pin 29 (CHASI)—either 0 or 1.
Intrusion Status. Write 0 to this bit to clear it.
0: No intrusion
1: Intrusion detected (default at VPP power-up reset)
3-2 LED Mode Control. This is a R/W bit.
Bits
3 2
Function
0 0
0 1
1 0
1 1
Software mode (default at VPP power-up reset)
Hardware mode 1 (default when power supply control is disabled by PSLDC0,1 straps)
Hardware mode 2
Reserved
1
0
Pin 59 Function Select. This is a R/W bit.
0: GPIE7 (default at VPP power-up reset)
1: IRRX1
Pin 58 Function Select. This is a R/W bit.
0: GPIE6 (default at VPP power-up reset)
1: IRRX2_IRSL0
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2.0 Device Architecture and Configuration (Continued)
2.8.11 SuperI/O Configuration C Register (SIOCFC)
This is a battery-backed register.
Location:
Type:
Index 2Ch
R/W
Bit
7
6
5
0
4
3
0
2
0
1
0
0
LED
Power LED
Name
Reset
Configura- Status in
LED2 Blink Rate
LED1 Blink Rate
tion
S4 or S5
0
0
0
0
Bit
Description
7
LED Configuration.
0: One dual-colored LED (default at VPP power-up reset)
1: Two LEDs
6
Power LED Status in S4 or S5. This bit is active only when Hardware mode 2 is selected (bits 2-3 in the SIOCFB regis-
ter).
0: Turn off (default at VDD power off)
1: Unchanged
5-3 LED2 Blink Rate.
Bits
5 4 3 Rate (Hz) Duty Cycle
0 0 0 Off
0 0 1 0.25
0 1 0 0.5
Always low
12.5%
25%
0 1 1
1 0 0
1 0 1
1 1 0
1
2
3
4
50%1
50%
50%
50%
1 1 1 On
2-0 LED1 Blink Rate.
Bits
Always high (default at VPP power-up reset)
2 1 0 Rate (Hz) Duty Cycle
0 0 0 Off
0 0 1 0.25
0 1 0 0.5
Always low (default at VPP power-up reset)
12.5%
25%
50%
50%
50%
50%
0 1 1
1 0 0
1 0 1
1 1 0
1
2
3
4
1 1 1 On
Always high
1. When Hardware mode 1 is selected, this rate is set when VSB is powered up or when VDD becomes inactive
while VSB is active.
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2.0 Device Architecture and Configuration (Continued)
2.8.12 SuperI/O Configuration D Register (SIOCFD)
This is a battery-backed register.
Location:
Type:
Index 2Dh
Varies per bit
Bit
7
6
5
4
3
2
1
0
Resume
Last PSON
State
Power
Button
Mode
LEDPolarity Last PSON
PSON
Polarity
Power
Supply Off
Name
Reset
Crowbar Timeout
Control
State
0
0
Strap
1
1
0
0
0
Bit
Description
7
LED Polarity Control. This is a R/W bit. It determines if the LED outputs are active high or active low when
they are lit.
0: Active high (default at VSB power-up reset)
1: Active low
6
Last Power Supply On State. This is a RO bit. When operating in Legacy mode (bit 0 of this register is set to
0), this bit reflects the state of the PSON pin sampled during the last power failure (no VSB), regardless of the
polarity of PSON.
0: Off
1: On
5
Power Supply On Polarity. This is a RO bit. The polarity of PSON is determined during VSB power-up by the
PSONPOL strap.
4-3 Crowbar Timeout. This is a R/W bit.
Bits
5 4
Value (Seconds)
0 0
0 1
1 0
1 1
0.4 to 0.9 (typical 0.6)
0.9 to 1.4 (typical 1.1)
1.4 to 1.9 (typical 1.6)
1.9 to 2.5 (typical 2.1) (default at VPP power-up reset)
Note that for any specific condition, there is a minimum gap of 0.25 seconds between the actual high limit of a time-
out setting and the low limit of the next time-out setting.
2
Resume Last Power Supply On State. This is a R/W bit. When it is set to 1, PSON resumes its last state, sampled
during the last power failure, after power returns. When this bit is set to 0, the PSON state is determined by the
SLPS3 state.
0: SLPS3 (default at VPP power-up reset)
1: Last PSON state. For correct operation, the system’s ACPI controller must be configured to resume to OFF.
This enables the power supply control logic to know the state of the chipset ACPI state machine after power
failure (no VDD and VSB).
1
0
Power Supply Off. This is a R/W bit. It always returns 0 when read. When using Legacy mode (bit 0 is set to
0) and setting this bit to 1, this bit inactivates the PSON output, thereby shutting off the power supply.
0: No action (default at VPP power-up reset)
1: Inactivate PSON in Legacy mode
Power Button Mode. This is a R/W bit.
0: Legacy (default at VSB power-up reset)
1: ACPI
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2.0 Device Architecture and Configuration (Continued)
2.9 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION
2.9.1
General Description
The generic FDC is a standard FDC with a digital data separator and is DP8473 and N82077 software compatible. The
PC87366 FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter,
including:
●
FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/read-
ing from a diskette, where:
0 = FM mode
1 = MFM mode
●
A logic 1 is returned for all floating (TRI-STATE) FDC register bits upon LPC I/O read cycles.
Exceptions to standard FDC support include:
●
Automatic media sense is not supported (MSEN0-1 pins are not implemented)
●
DRATE1 is not supported.
Table 17 lists the FDC functional block registers.
Table 17. FDC Registers
Offset1
Mnemonic
Register Name
Status A
Type
00h
01h
02h
03h
04h
SRA
SRB
DOR
TDR
MSR
DSR
FIFO
RO
RO
R/W
R/W
R
Status B
Digital Output
Tape Drive
Main Status
Data Rate Select
Data (FIFO)
N/A
W
05h
06h
07h
R/W
X
DIR
Digital Input
Configuration Control
R
CCR
W
1. This is the 8-byte aligned FDC base address.
2.9.2
Logical Device 0 (FDC) Configuration
Table 18 lists the Configuration registers that affect the FDC. Only the last two registers (F0h and F1h) are described here.
See Sections 2.2.3 and 2.2.4 for descriptions of the others.
Table 18. FDC Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1 register and bit 0 of the SIOCF6 register. R/W
00h
03h
F2h
06h
03h
02h
04h
24h
00h
60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.
61h Base Address LSB register bits 2 and 0 (for A2 and A0) are read only, 00b.
70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 37).
71h Interrupt Type. Bit 1 is read/write; other bits are read only.
74h DMA Channel Select.
R/W
R/W
R/W
R/W
R/W
RO
75h Report no second DMA assignment.
F0h FDC Configuration register.
R/W
R/W
F1h Drive ID register.
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2.0 Device Architecture and Configuration (Continued)
2.9.3
FDC Configuration Register
This register is reset by hardware to 24h.
Location:
Type:
Index F0h
R/W
Bit
7
6
5
4
3
2
1
0
TDR
Register
Mode
DENSEL
Polarity
Control
PC-AT or
PS/2 Drive Reserved
Mode Select
Write
Protect
TRI-STATE
Control
Name
Reserved
Reserved
Reset
0
0
0
1
0
0
0
1
0
0
Required
Bit
Description
7
6
Reserved. Must be 0.
TDR Register Mode.
0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are 111111b (default)
1: Enhanced drive mode
5
DENSEL Polarity Control.
0: Active low for 500 Kbps or 1 Mbps data rates
1: Active high for 500 Kbps or 1 Mbps data rates (default)
4
3
Reserved. Must be 0.
Write Protect. This bit allows software to force write protect functionality. When set, writes to the floppy disk
drive are disabled. This effect is identical to WP when it is active.
0: Write protected according to WP signal (default)
1: Write protected regardless of value of WP signal
2
PC-AT or PS/2 Drive Mode Select.
0: PS/2 drive mode
1: PC-AT drive mode (default)
1
0
Reserved.
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
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2.0 Device Architecture and Configuration (Continued)
2.9.4
Drive ID Register
This read/write register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in Enhanced mode.
Location:
Type:
Index F1h
R/W
Bit
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Name
Reset
Reserved
Drive 1 ID
Drive 0 ID
0
Bit
Description
7-4 Reserved.
3-2 Drive 1 ID. When drive 1 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively.
1-0 Drive 0 ID. When drive 0 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively.
Usage Hints: Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register
in Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support auto-
matic media sense, bits 1 and/or 3 of the Drive ID register should be set to 1 (to indicate non-valid media sense). When the
corresponding drive (0 or 1) is selected, the Drive ID bit is reflected in bit 5 of the TDR register in Enhanced mode.
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2.0 Device Architecture and Configuration (Continued)
2.10 PARALLEL PORT CONFIGURATION
2.10.1 General Description
The PC87366 Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard
or SPP), Bi-directional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP
mode).
The Parallel Port includes two groups of runtime registers, as follows:
• A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h)
are used only in the Extended ECP mode.
• A group of four registers, used only in the Extended ECP mode, accessed by a second level offset.
The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-
isters are used and which address bits are used for the base address. See Tables 19 and 20 for a listing of all registers, their
offset addresses and the associated modes.
Table 19. Parallel Port Registers at First Level Offset
Offset
Mnemonic
Mode(s)
Type
Register Name
00h
DATAR
AFIFO
DTR
0,1
R/W
W
Data
3
ECP FIFO (Address)
Data (for EPP)
Status
4
R/W
RO
01h
02h
DSR
0,1,2,3
STR
4
RO
Status (for EPP)
Control
DCR
0,1,2,3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CTR
4
4
4
4
4
4
Control (for EPP)
EPP Address
03h
04h
05h
06h
07h
400h
ADDR
DATA0
DATA1
DATA2
DATA3
EPP Data Port 0
EPP Data Port 1
EPP Data Port 2
EPP Data Port 3
CFIFO
DFIFO
TFIFO
CNFGA
2
3
6
7
W
PP Data FIFO
ECP Data FIFO
Test FIFO
R/W
R/W
RO
Configuration A
401h
402h
403h
CNFGB
ECR
7
RO
R/W
R/W
Configuration B
Extended Control
Extended Index
0,1,2,3
0,1,2,3
EIR1
EDR1
EAR1
404h
405h
0,1,2,3
0,1,2,3
R/W
R/W
Extended Data
Extended Auxiliary Status
1. These registers are extended to the standard IEEE1284 registers. They are accessi-
ble only when enabled by bit 4 of the Parallel Port Configuration register (see Section
2.10.3).
Table 20. Parallel Port Registers at Second Level Offset
Offset
Mnemonic
Type
Register Name
Extended Control 0
00h
02h
04h
05h
Control0
Control2
R/W
R/W
R/W
R/W
Extended Control 1
Extended Control 4
Configuration 0
Control4
PP Confg0
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2.0 Device Architecture and Configuration (Continued)
2.10.2 Logical Device 1 (PP) Configuration
Table 21 lists the configuration registers that affect the Parallel Port. Only the last register (F0h) is described here. See Sec-
tions 2.2.3 and 2.2.4 for descriptions of the others.
Table 21. Parallel Port Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1 register.
R/W
R/W
00h
02h
60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for
A10) should be 0b.
61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP
Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.
R/W
78h
70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 37).
R/W
R/W
07h
02h
71h Interrupt Type
Bits 7-2 are read only.
Bit 1 is a read/write bit.
Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation
mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge
interrupt) in all other modes.
74h DMA Channel Select.
R/W
RO
04h
04h
F2h
75h Report no second DMA assignment.
F0h Parallel Port Configuration register.
R/W
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2.0 Device Architecture and Configuration (Continued)
2.10.3 Parallel Port Configuration Register
This register is reset by hardware to F2h.
Location:
Type:
Index F0h
R/W
Bit
7
6
5
4
3
0
2
0
1
0
Extended
Register
Access
Power
Mode
Control
TRI-STATE
Control
Name
Reset
Parallel Port Mode Select
Reserved
1
1
1
1
1
0
Bit
Description
7-5 Parallel Port Mode Select.
Bits
7 6 5 Function
0 0 0 SPP-Compatible mode
PD7-0 are always output signals
0 0 1 SPP Extended mode
PD7-0 direction is controlled by software
0 1 0 EPP 1.7 mode
0 1 1 EPP 1.9 mode
1 0 0 ECP mode (IEEE1284 register set), with no support for EPP mode
1 0 1 Reserved
1 1 0 Reserved
1 1 1 ECP mode (IEEE1284 register set), with EPP mode selectable as Mode 4
Selection of EPP 1.7 or 1.9 in ECP Mode 4 is controlled by bit 4 of the Control2 configuration register of
the parallel port at offset 02h.
Note: Before setting bits 7-5, enable the parallel port and set CTR/DCR (at base address + 2) to C4h.
4
Extended Register Access.
0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored).
1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-
time configuration within the Parallel Port address space.
3-2 Reserved.
1
Power Mode Control. When the logical device is active:
0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is
active. Registers are maintained.
1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default).
0
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
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2.0 Device Architecture and Configuration (Continued)
2.11 SERIAL PORT 2 CONFIGURATION
2.11.1 General Description
Serial Port 2 includes IR functionality as described in the Serial Port 2 with IR chapter.
2.11.2 Logical Device 2 (SP2) Configuration
Table 22 lists the configuration registers that affect the Serial Port 2. Only the last register (F0h) is described here. See Sec-
tions 2.2.3 and 2.2.4 for descriptions of the others.
Table 22. Serial Port 2 Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1 register and bit 2 of the SIOCF6 register. R/W
00h
02h
F8h
03h
03h
04h
04h
02h
60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.
61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b.
70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 37).
71h Interrupt Type. Bit 1 is R/W; other bits are read only.
74h DMA Channel Select 0 (RX_DMA).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
75h DMA Channel Select 1 (TX_DMA).
F0h Serial Port 2 Configuration register.
2.11.3 Serial Port 2 Configuration Register
This register is reset by hardware to 02h.
Location:
Type:
Index F0h
R/W
Bit
7
6
0
5
0
4
3
0
2
1
0
Bank
Select
Enable
Power
Mode
Control
Busy
Indicator
TRI-STATE
Control
Name
Reset
Reserved
0
0
0
1
0
Bit
Description
7
Bank Select Enable. Enables bank switching for Serial Port 2.
0: All attempts to access the extended registers in Serial Port 2 are ignored (default).
1: Enables bank switching for Serial Port 2.
6-3 Reserved.
2
Busy Indicator. This read only bit can be used by power management software to decide when to power-down
the Serial Port 2 logical device.
0: No transfer in progress (default).
1: Transfer in progress.
1
Power Mode Control. When the logical device is active in:
0: Low power mode
Serial Port 2 Clock disabled. The output signals are set to their default states. The RI input signal can be
programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also
prevents access to Serial Port 2 registers.)
1: Normal power mode
Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default).
0
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
One exception is the IRTX pin, which is driven to 0 when Serial Port 2 is inactive and is not affected by this bit.
0: Disabled (default)
1: Enabled
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2.0 Device Architecture and Configuration (Continued)
2.12 SERIAL PORT 1 CONFIGURATION
2.12.1 Logical Device 3 (SP1) Configuration
Table 23 lists the configuration registers that affect the Serial Port 2. Only the last register (F0h) is described here. See Sec-
tions 2.2.3 and 2.2.4 for descriptions of the others.
Table 23. Serial Port 1 Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1 register and bit 3 of the SIOCF6 register. R/W
00h
03h
F8h
04h
03h
04h
04h
02h
60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.
61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b.
70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 37).
71h Interrupt Type. Bit 1 is R/W; other bits are read only.
74h Report no DMA Assignment.
R/W
R/W
R/W
R/W
RO
75h Report no DMA Assignment.
RO
F0h Serial Port 1 Configuration register.
R/W
2.12.2 Serial Port 1 Configuration Register
This register is reset by hardware to 02h.
Location:
Type:
Index F0h
R/W
Bit
7
6
0
5
0
4
3
0
2
1
0
Bank
Select
Enable
Power
Mode
Control
Busy
Indicator
TRI-STATE
Control
Name
Reset
Reserved
0
0
0
1
0
Bit
Description
7
Bank Select Enable. Enables bank switching for Serial Port 1.
0: Disabled (default).
1: Enabled
6-3 Reserved.
2
Busy Indicator. This read only bit can be used by power management software to decide when to power-down
the Serial Port 1 logical device.
0: No transfer in progress (default).
1: Transfer in progress.
1
Power Mode Control. When the logical device is active in:
0: Low power mode
Serial Port 1 Clock disabled. The output signals are set to their default states. The RI input signal can be
programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also
prevents access to Serial Port 1 registers.)
1: Normal power mode
Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default).
0
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
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2.0 Device Architecture and Configuration (Continued)
2.13 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION
2.13.1 Logical Device 4 (SWC) Configuration
Table 24 lists the configuration registers that affect the SWC. See Sections 2.2.3 and 2.2.4 for a detailed description of these
registers.
Table 24. System Wake-Up Control (SWC) Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.1
R/W
00h
60h Base Address MSB register.
R/W
R/W
R/W
R/W
RO
00h
00h
00h
03h
04h
04h
61h Base Address LSB register. Bits 4-0 (for A4-0) are read only, 00000b.
70h Interrupt Number (see note, p. 37).
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment.
75h Report no DMA assignment.
RO
1. The logical device registers are maintained and all wake-up detection mechanisms are functional.
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2.0 Device Architecture and Configuration (Continued)
2.14 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION
2.14.1 General Description
The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse con-
troller (Logical Device 5) and a Keyboard controller (Logical Device 6).
The hardware KBC module is integrated to provide the following pin functions: P12, P16, P17, KBRST (P20), GA20 (P21),
KBDAT, KBCLK, MDAT and MCLK. KBRST and GA20 are implemented as bi-directional, open-drain pins. The Keyboard
and Mouse interfaces are implemented as bi-directional, open-drain pins. Their internal connections are shown in Figure 5.
P10, P11, P13-P15, P22-P27 of the KBC core are not available on dedicated pins; neither are T0 and T1. P10, P11, P22,
P23, P26, P27, T0 and T1 are used to implement the Keyboard and Mouse interface.
Internal pull-ups are implemented only on P12, P16 and P17.
The KBC executes a program fetched from an on-chip 2Kbyte ROM. The code programmed in this ROM is user-customiz-
able. The KBC has two interrupt request signals: one for the Keyboard and one for the Mouse. The interrupt requests are
implemented using ports P24 and P25 of the KBC core. The interrupt requests are controlled exclusively by the KBC firm-
ware, except for the type and number, which are affected by configuration registers (see Section 2.14.2 25).
The interrupt requests are implemented as bi-directional signals. When an I/O port is read, all unused bits return the value
latched in the output registers of the ports.
For KBC firmware that implements interrupt-on-OBF schemes, it is recommended to implement it as follows:
1. Put the data in DBBOUT.
2. Set the appropriate port bit to issue an interrupt request.
P12
P16
P17
P20
P21
P12
KBC
P16
P17
STATUS
KBRST
DBBIN
GA20
DBBOUT
P26
T0
KBCLK
KBDAT
P27
P10
P23
T1
MCLK
MDAT
KBD IRQ
P24
P25
Matrix
P22
P11
Mouse IRQ
Figure 5. Keyboard and Mouse Interfaces
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2.0 Device Architecture and Configuration (Continued)
2.14.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration
Tables 25 and 26 list the configuration registers that affect the Mouse and the Keyboard, respectively. Only the last register
(F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others.
Table 25. Mouse Configuration Registers
Index
Mouse Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1. When the Mouse of the KBC is inactive, the R/W
IRQ selected by the Mouse Interrupt Number and Wake-Up on IRQ Enable register
(index 70h) is not asserted. This register has no effect on host KBC commands
handling the PS/2 Mouse.
00h
70h Mouse Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 37). R/W
0Ch
02h
04h
04h
71h Mouse Interrupt Type. Bits 1,0 are read/write; other bits are read only.
74h Report no DMA assignment
R/W
RO
75h Report no DMA assignment
RO
Table 26. Keyboard Configuration Registers
Index
Keyboard Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1.
R/W
R/W
R/W
R/W
01h
00h
60h
00h
60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.
61h Base Address LSB register. Bits 2-0 are read only 000b.
62h Command Base Address MSB register. Bits 7-3 (for A15-11) are read only,
00000b.
63h Command Base Address LSB. Bits 2-0 are read only 100b.
R/W
64h
01h
02h
04h
04h
40h
70h KBD Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 37). R/W
71h KBD Interrupt Type. Bits 1,0 are read/write; others are read only.
74h Report no DMA assignment.
R/W
RO
75h Report no DMA assignment.
RO
F0h KBC Configuration register.
R/W
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2.0 Device Architecture and Configuration (Continued)
2.14.3 KBC Configuration Register
This register is reset by hardware to 40h.
Location:
Type:
Index F0h
R/W
Bit
7
6
5
0
4
0
3
Reserved
0
2
1
0
0
TRI-STATE
Control
Name
KBC Clock Source
Reset
0
1
0
0
0
Required
Bit
Description
7-6 KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled).
Bits
7 6
Source
0 0
0 1
1 0
1 1
8 MHz
12 MHz (default)
16 MHz
Reserved
5-1 Reserved.
0
TRI-STATE Control. If KBD is inactive (disabled) when this bit is set, the KBD pins (KBCLK and KBDAT) are in TRI-
STATE. If Mouse is inactive (disabled) when this bit is set, the Mouse pins (MCLK and MDAT) are in TRI-STATE.
0: Disabled (default)
1: Enabled
Usage Hints:
To change the clock frequency of the KBC:
1. Disable the KBC logical devices.
2. Change the frequency setting.
3. Enable the KBC logical devices.
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2.0 Device Architecture and Configuration (Continued)
2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION
2.15.1 General Description
The GPIO functional block includes 29 pins, arranged in three 8-bit ports (ports 0, 1 and 2) and one 5-bit port (port 3). All
pins in port 0 are I/O and have full event detection capability, enabling them to trigger the assertion of IRQ, SMI and
PWUREQ signals. With the exception of bit 5, which is output only, port 1 pins are also I/O with full event detection capability.
Pins in ports 2 and 3 are I/O but none of them has event detection capability. The 16 runtime registers associated with the
five ports are arranged in the GPIO address space as shown in Table 27. The GPIO base address is 16-byte aligned. Ad-
dress bits 3-0 are used to indicate the register offset.
Table 27. Runtime Registers in GPIO Address Space
Offset
Mnemonic
GPDO0 GPIO Data Out 0
GPDI0 GPIO Data In 0
Register Name
Port Type
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0
1
R/W
RO
GPEVEN0 GPIO Event Enable 0
GPEVST0 GPIO Event Status 0
GPDO1 GPIO Data Out 1
R/W
R/W1C
R/W
RO
GPDI1
GPIO Data In 1
GPEVEN1 GPIO Event Enable 1
GPEVST1 GPIO Event Status 1
GPDO2 Data Out 2
R/W
R/W1C
R/W
RO
2
3
GPDI2
GPDO3 Data Out 3
GPDI3 Data In 3
Data In 2
R/W
RO
2.15.2 Implementation
The standard GPIO port with event detection capability (such as ports 0, 1 and 4) has four runtime registers. Each pin is
associated with a GPIO Pin Configuration register that includes seven configuration bits. Ports 2 and 3 are non-standard
ports that do not support event detection and therefore differ from the generic model as follows:
●
They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers
GPEVEN2/3 and GPEVST2/3 are not available.
●
Only bits 3-0 are implemented in the GPIO Pin Configuration registers of ports 2 and 3. Bits 6-4, associated with the
event detection functionality, are reserved.
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2.0 Device Architecture and Configuration (Continued)
2.15.3 Logical Device 7 (GPIO) Configuration
Table 28 lists the configuration registers that affect the GPIO. Only the last three registers (F0h - F2h) are described here.
See Sections 2.2.3 and 2.2.4 for a detailed description of the others.
Table 28. GPIO Configuration Register
Index
Configuration Register or Action
Type
Reset
30h Activate. See also bit 7 of the SIOCF1 register.
60h Base Address MSB register.
R/W
R/W
R/W
R/W
R/W
RO
00h
00h
00h
00h
03h
04h
04h
00h
00h
00h
61h Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b.
70h Interrupt Number (see note, p. 37).
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment.
75h Report no DMA assignment.
RO
F0h GPIO Pin Select register.
R/W
R/W
R/W
F1h GPIO Pin Configuration register.
F2h GPIO Pin Event Routing register.
Figure 6 shows the organization of these registers.
GPIO Pin Select Register
(Index F0h)
Port Select
Pin Select
Port 3, Pin 0
Port 2, Pin 0
Port 1, Pin 0
Port 0, Pin 0
Pin 0
Port 0
GPIO Pin
Configuration Register
(Index F1h)
Configuration Registers
Port 0, Pin 7
Port 3
Pin 7
Pin 0
Port 1, Pin 0
Port 0, Pin 0
Port 0
Port 1
GPIO Pin Event
Routing Register
(Index F2h)
Event Routing
Registers
Port 0, Pin 7
Pin 7
Figure 6. Organization of GPIO Pin Registers
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2.0 Device Architecture and Configuration (Continued)
2.15.4 GPIO Pin Select Register
This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the
GPIO Pin Configuration register). It is reset by hardware to 00h.
Location:
Type:
Index F0h
R/W
Bit
7
Reserved
0
6
0
5
4
0
3
Reserved
0
2
0
1
Pin Select
0
0
0
Name
Reset
Port Select
0
Bit
Description
7
Reserved.
6-4 Port Select. These bits select the GPIO port to be configured:
000: Port 0 (default)
001, 010, 011: Binary value of port numbers 1-3, respectively. All other values are reserved.
3
Reserved.
2-0 Pin Select. These bits select the GPIO pin to be configured in the selected port:
000, 001, ... 111: Binary value of the pin number, 0, 1, ... 7 respectively (default=0)
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2.0 Device Architecture and Configuration (Continued)
2.15.5 GPIO Pin Configuration Register
This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO
Pin registers that are accessed via this register have a common bit structure, as shown below. This register is reset by hard-
ware to 44h, except for ports 2 and 3, which are reset to 04h.
Location:
Type:
Index F1h
R/W
Ports: 0 and 1 (with event detection capability)
Bit
7
6
5
4
3
Lock
0
2
1
0
Event
Event
Polarity
Pull-Up
Control
Output
Type
Output
Enable
Name
Reset
Reserved Debounce
Enable
Event Type
0
1
0
0
1
0
0
Ports 2 and 3 (without event detection capability)
Bit
7
0
6
0
5
0
4
0
3
Lock
0
2
1
0
Pull-Up
Control
Output
Type
Output
Enable
Name
Reset
Reserved
1
0
0
Bit
Description
7
6
Reserved.
Event Debounce Enable. (Ports 0 and 1 with event detection capability). Enables transferring the signal only
after a predetermined debouncing period of time.
0: Disabled
1: Enabled (default)
Reserved. (Ports 2 and 3.) Always 0.
5
4
Event Polarity. (Ports 0 and 1 with event detection capability). This bit defines the polarity of the signal that
issues an interrupt from the corresponding GPIO pin (falling/low or rising/high).
0: Falling edge or low-level input (default)
1: Rising edge or high-level input
Reserved. (Ports 2 and 3.) Always 0.
Event Type. (Ports 0 and 1 with event detection capability). This bit defines the type of the signal that issues
an interrupt from the corresponding GPIO pin (edge or level).
0: Edge input (default)
1: Level input
Reserved. (Ports 2 and 3.) Always 0.
3
2
Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to
0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O
Configuration 3 register, SIOCF3).
0: No effect (default)
1: Direction, output type, pull-up and output value locked
Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.
It supports internal pull-ups for the open-drain output buffer type.
0: Disabled
1: Enabled (default)
1
0
Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.
0: Open-drain (default)
1: Push-pull
Output Enable. This bit indicates the GPIO pin output state. It has no effect on the input path.
0: TRI-STATE (default)
1: Output enabled
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2.0 Device Architecture and Configuration (Continued)
2.15.6 GPIO Event Routing Register
This register enables the routing of the GPIO event to IRQ, SMI and/or PWUREQ signals. It is implemented only for ports
0,1 and 4, which have event detection capability. This register is reset by hardware to 00h.
Location:
Type:
Index F2h
R/W
Bit
7
0
6
0
5
Reserved
0
4
3
0
2
1
0
Enable
PWUREQ
Routing
Enable SMI Enable IRQ
Routing
Name
Reset
Routing
0
0
0
1
Bit
Description
7-3 Reserved.
2
1
0
Enable PWUREQ Routing.
0: Disabled (default)
1: Enabled
Enable SMI Routing.
0: Disabled (default)
1: Enabled
Enable IRQ Routing.
0: Disabled
1: Enabled (default)
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2.0 Device Architecture and Configuration (Continued)
2.16 ACCESS.BUS INTERFACE (ACB) CONFIGURATION
2.16.1 General Description
The ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. The ACB uses a 24
MHz internal clock.
The six runtime registers are shown below.
Table 29. ACB Runtime Registers
Offset Mnemonic
00h ACBSDA ACB Serial Data
01h ACBST ACB Status
Register Name
Type
R/W
Varies per bit
Varies per bit
R/W
02h ACBCST ACB Control Status
03h ACBCTL1 ACB Control 1
04h ACBADDR ACB Own Address
05h ACBCTL2 ACB Control 2
R/W
R/W
2.16.2 Logical Device 8 (ACB) Configuration
Table 30 lists the configuration registers that affect the ACB. Only the last register (F0h) is described here. See Sections
2.2.3 and 2.2.4 for a detailed description of the others.
Table 30. ACB Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1 register.
60h Base Address MSB register.
R/W
R/W
R/W
00h
00h
00h
00h
03h
04h
04h
00h
61h Base Address LSB register. Bits 2-0 (for A2-0) are read only, 000b.
70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 37). R/W
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment.
R/W
RO
75h Report no DMA assignment.
RO
F0h ACB Configuration register.
R/W
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2.0 Device Architecture and Configuration (Continued)
2.16.3 ACB Configuration Register
This register is reset by hardware to 00h.
Location:
Type:
Index F0h
R/W
Bit
7
0
6
0
5
Reserved
0
4
3
0
2
1
0
0
0
Internal
Pull-Up
Enable
Name
Reset
Reserved
0
0
Bit
Description
7-3 Reserved.
Internal Pull-Up Enable.
2
0: No internal pull-up resistors on SCL and SDA (default)
1: Internal pull-up resistors on SCL and SDA
1-0 Reserved.
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2.0 Device Architecture and Configuration (Continued)
2.17 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION
2.17.1 General Description
This module includes three Fan Speed Control units and three Fan Speed Monitor units. The 15 runtime registers of the six
functional blocks are arranged in the address space shown in Table 31. The base address is 16-byte aligned. Address bits
0-3 are used to indicate the register offset.
Table 31. Runtime Registers in FSCM Address Space
Offset Mnemonic
Register Name
Function
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
FCPSR0 Fan Control 0 Pre-Scale
Fan Speed Control 0
FCDCR0 Fan Control 0 Duty Cycle
FCPSR1 Fan Control 1 Pre-Scale
FCDCR1 Fan Control 1 Duty Cycle
FCPSR2 Fan Control 2 Pre-Scale
FCDCR2 Fan Control 2 Duty Cycle
FMTHR0 Fan Monitor 0 Threshold
FMSPR0 Fan Monitor 0 Speed
Fan Speed Control 1
Fan Speed Control 2
Fan Speed Monitor 0
FMCSR0 Fan Monitor 0 Control & Status
FMTHR1 Fan Monitor 1 Threshold
FMSPR1 Fan Monitor 1 Speed
Fan Speed Monitor 1
Fan Speed Monitor 2
FMCSR1 Fan Monitor 1 Control & Status
FMTHR2 Fan Monitor 2 Threshold
FMSPR2 Fan Monitor 2 Speed
FMCSR2 Fan Monitor 2 Control & Status
0Fh Reserved
2.17.2 Logical Device 9 (FSCM) Configuration
Table 32 lists the configuration registers that affect the Fan Speed Controls and the Fan Speed Monitors. Only the last one
(F0h) is described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others.
Table 32. FSCM Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1 register.
60h Base Address MSB register.
R/W
R/W
R/W
R/W
R/W
RO
00h
00h
00h
00h
03h
04h
04h
00h
00h
00h
61h Base Address LSB register. Bit 3-0 (for A3-0) are read only, 0000b.
70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 37).
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment.
75h Report no DMA assignment.
RO
F0h Fan Speed Control and Monitor Configuration 1 register.
F1h Fan Speed Control and Monitor Configuration 2 register
F2h Fan Speed Control OTS Configuration register
R/W
R/W
R/W
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2.0 Device Architecture and Configuration (Continued)
2.17.3 Fan Speed Control and Monitor Configuration 1 Register
This register is reset by hardware to 00h.
Location:
Type:
Index F0h
R/W
Bit
7
6
5
4
3
2
1
0
Fan Speed Fan Speed Fan Speed Fan Speed Fan Speed Fan Speed
TRI-STATE
Control
Name
Reset
Invert 1
Enable
Control 1 Monitor 1
Invert 0
Enable
Control 0 Monitor 0 Reserved
Enable
Enable
Enable
Enable
0
0
0
0
0
0
0
0
Bit
Description
7
Fan Speed Invert 1 Enable.
0: Disabled (default)
1: Enabled
6
5
4
3
2
Fan Speed Control 1 Enable.
0: Disabled (default)
1: Enabled
Fan Speed Monitor 1 Enable.
0: Disabled (default)
1: Enabled
Fan Speed Invert 0 Enable.
0: Disabled (default)
1: Enabled
Fan Speed Control 0 Enable.
0: Disabled (default)
1: Enabled
Fan Speed Monitor 0 Enable.
0: Disabled (default)
1: Enabled
1
0
Reserved.
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
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2.0 Device Architecture and Configuration (Continued)
2.17.4 Fan Speed Control and Monitor Configuration 2 Register
This register is reset by hardware to 00h.
Location:
Type:
Index F1h
R/W
Bit
7
0
6
0
5
Reserved
0
4
3
0
2
1
0
Fan Speed Fan Speed Fan Speed
Invert 2
Enable
Name
Reset
Control 2 Monitor 2
Enable
Enable
0
0
0
0
Bit
Description
7-3 Reserved.
2
1
0
Fan Speed Invert 2 Enable.
0: Disabled (default)
1: Enabled
Fan Speed Control 2 Enable.
0: Disabled (default)
1: Enabled
Fan Speed Monitor 2 Enable.
0: Disabled (default)
1: Enabled
2.17.5 Fan Speed Control OTS Configuration Register (FCOCR)
Location:
Type:
Index F2h
R/W
Bit
7
0
6
0
5
Reserved
0
4
3
0
2
1
0
Name
Fan 2
Fan 1
Fan 0
Enable on Enable on Enable on
OTS
OTS
OTS
Reset
0
0
0
0
Bit
Description
7-3 Reserved.
2
1
0
Fan 2 Enable on OTS. Enables fan 2 at 100% duty cycle when an OTS event becomes active.
0: Fan 2 operates as defined by the PWM mechanism
1: Fan 2 is forced to 100% duty cycle when the OTS output form any of the temperature measurement channels
(TMS or VLM) becomes active.
Fan 1 Enable on OTS. Enables fan 1 at 100% duty cycle when an OTS event becomes active.
0: Fan 1 operates as defined by the PWM mechanism
1: Fan 1 is forced to 100% duty cycle when the OTS output form any of the temperature measurement channels
(TMS or VLM) becomes active.
Fan 0 Enable on OTS. Enables fan 0 at 100% duty cycle when an OTS event becomes active.
0: Fan 0 operates as defined by the PWM mechanism
1: Fan 0 is forced to 100% duty cycle when the OTS output form any of the temperature measurement channels
(TMS or VLM) becomes active.
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2.0 Device Architecture and Configuration (Continued)
2.18 WATCHDOG TIMER (WDT) CONFIGURATION
2.18.1 Logical Device 10 (WDT) Configuration
Table 33 lists the configuration registers that affect the WATCHDOG Timer. Only the last register (F0h) is described here.
See Sections 2.2.3 and 2.2.4 for a detailed description of the others.
Table 33. WDT Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
R/W
00h
60h Base Address MSB register.
R/W
00h
00h
00h
61h Base Address LSB register. Bits 1 and 0 (for A1 and A0) are read only, 00b. R/W
70h Interrupt Number (for routing the WDO signal) and Wake-Up on IRQ Enable R/W
register (see note, p. 37).
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment.
R/W
RO
03h
04h
04h
02h
75h Report no DMA assignment.
RO
F0h WATCHDOG Timer Configuration register.
R/W
2.18.2 WATCHDOG Timer Configuration Register
This register is reset by hardware to 02h.
Location:
Type:
Index F0h
R/W
Bit
7
0
6
0
5
0
4
0
3
2
1
0
Internal
Pull-Up
Enable
Power
Mode
Control
Output
Type
TRI-STATE
Control
Name
Reset
Reserved
0
0
1
0
Bit
Description
7-4 Reserved.
3
2
1
Output Type. This bit controls the buffer type (open-drain or push-pull) of the WDO pin.
0: Open-drain (default)
1: Push-pull
Internal Pull-Up Enable. This bit controls the internal pull-up resistor on the WDO pin.
0: Disabled (default)
1: Enabled
Power Mode Control.
0: Low power mode:
WATCHDOG Timer clock disabled. WDO output signal is set to 1. Registers are accessible and maintained
(unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers).
1: Normal power mode:
WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default).
0
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
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2.0 Device Architecture and Configuration (Continued)
2.19 GAME PORT (GMP) CONFIGURATION
2.19.1 Logical Device 11 (GMP) Configuration
Table 34 lists the configuration registers that affect the Game Port. Only the last register (F0h) is described here. See Sec-
tions 2.2.3 and 2.2.4 for a detailed description of the others.
Table 34. GMP Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
R/W
00h
60h Base Address MSB register
R/W
R/W
R/W
R/W
RO
02h
00h
00h
03h
04h
04h
00h
61h Base Address LSB register. Bits 3-0 (for A3-A0) are read only, 0000b.
70h Interrupt Number and Wake-Up on IRQ Enable register.
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment
75h Report no DMA assignment
RO
F0h Game Port Configuration register
R/W
2.19.2 Game Port Configuration Register
This register is reset by hardware to 00h.
Location:
Type:
Index F0h
R/W
Bit
7
0
6
0
5
Reserved
0
4
3
0
2
1
0
0
Internal
Pull-Up
Enable
Name
Reset
Reserved
0
0
0
Bit
Description
7-3 Reserved.
2
Internal Pull-Up Enable. When the GMP functions are selected, this bit controls the internal pull-up resistor on
pins 119 (GPIO22/JOYABTN0), 120 (GPIO23/JOYABTN1), 123 (GPIO26/JOYBBTN0) and 124
(GPIO27/JOYBBTN1).
0: Disabled (default)
1: Enabled
1-0 Reserved.
Usage Hint:
To operate GMP enhanced features, make sure to locate its base address within the LPC Wide Generic address range.
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2.0 Device Architecture and Configuration (Continued)
2.20 MIDI PORT (MIDI) CONFIGURATION
2.20.1 Logical Device 12 (MIDI) Configuration
Table 34 lists the configuration registers that affect the MIDI Port. Only the last register (F0h) is described here. See Sections
2.2.3 and 2.2.4 for a detailed description of the others.
Table 35. MIDI Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
R/W
00h
60h Base Address MSB register
R/W
R/W
R/W
R/W
RO
03h
30h
00h
03h
04h
04h
00h
61h Base Address LSB register bits 1-0 (for A1-A0) are read only, 00b.
70h Interrupt Number and wake-up on IRQ enable.
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment
75h Report no DMA assignment
RO
F0h MIDI Port Configuration register
R/W
2.20.2 MIDI Port Configuration Register
This register is reset by hardware to 00h.
Location:
Type:
Index F0h
R/W
Bit
7
0
6
0
5
Reserved
0
4
3
0
2
1
0
Internal
Pull-Up
Enable
TRI-STATE
Control
Name
Reset
Reserved
0
0
0
0
Bit
Description
7-3 Reserved.
2
Internal Pull-Up Enable. This bit controls the internal pull-up resistor on pin 126 (GPIO31/MDRX).
0: Disabled (default)
1: Enabled
1
0
Reserved.
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
Usage Hint:
To operate MIDI enhanced features, make sure to locate its base address within the LPC Wide Generic address range.
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2.0 Device Architecture and Configuration (Continued)
2.21 VOLTAGE LEVEL MONITOR (VLM) CONFIGURATION
2.21.1 Logical Device 13 (VLM) Configuration
Table 36 lists the configuration registers that affect the VLM. See Sections 2.2.3 and 2.2.4 for a detailed description of these
registers.
Table 36. VLM Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
R/W
00h
60h Base Address MSB register
R/W
R/W
R/W
R/W
RO
00h
00h
00h
03h
04h
04h
61h Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b.
70h Interrupt Number
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment
75h Report no DMA assignment
RO
2.22 TEMPERATURE SENSOR (TMS) CONFIGURATION
2.22.1 Logical Device 14 (TMS) Configuration
Table 37 lists the configuration registers that affect the TMS. See Sections 2.2.3 and 2.2.4 for a detailed description of these
registers.The OTS, ALERT, IRQ and SMI signals are routed through the configuration module. OTS is routed to a pin, IRQ
and SMI are routed to a designated interrupt signal and ALERT is not connected. When measuring temperature using ther-
mistors that are connected to the VLM module, the OTS, ALERT, SMI and IRQ signals are routed through the TMS config-
uration. Therefore, ensure that you set the TMS configuration registers (described in Table 37) and enable the TMS module
whenever temperature measurement is in use. In the TMS or VLM module, enable the required source of IRQ, SMI and OTS
signals via the configuration registers inside the module.
Table 37. TMS Configuration Registers
Index
Configuration Register or Action
Type
Reset
30h Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
R/W
00h
60h Base Address MSB register
R/W
R/W
R/W
R/W
RO
00h
00h
00h
03h
04h
04h
61h Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b.
70h Interrupt Number
71h Interrupt Type. Bit 1 is read/write. Other bits are read only.
74h Report no DMA assignment
75h Report no DMA assignment
RO
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3.0 System Wake-Up Control (SWC)
3.1 OVERVIEW
The SWC recognizes the following maskable system events:
●
Modem ring (RI1 and RI2 pins).
●
Telephone ring (RING input pin).
●
Keyboard activity or specific programmable key sequence.
●
Mouse activity or specific programmable sequence of clicks and movements.
●
Programmable Consumer Electronics IR (CEIR) address.
●
Wake-up on module IRQs for FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB, Fan Speed Control and
Monitor (FSCM) and WATCHDOG Timer (WDT), Game Port and MIDI Port.
●
Eight VSB-powered, general-purpose input events (via GPIOE0-5 and GPIE6-7).
●
15 VDD-powered, GPIO-triggered events (via GPIO00-07, GPIO10-14, GPIO16-17).
●
Software event.
The SWC notifies the device when any of these events occur by asserting one or more of the following output pins:
●
Power-Up Request (PWUREQ).
●
System Management Interrupt (SMI).
●
Interrupt Request (via SERIRQ).
●
Power Button (PWBTOUT).
Figure 7 shows the block diagram of the SWC.
Wake-Up
Configuration
and Control
Registers
IRQ
Filters and
Polarity
Selection
Logic
Wake-Up
Mode Control
(Extension)
Logic
Wake-Up Event
Detection
and Routing
Logic
Wake-Up
Event
Sources
16
16
16
SMI
PWUREQ
Wake-Up
Extension
Enable
ACPI
Enable, Status
and Routing
14
Registers
Control Registers
Power-Supplies
100 msec
Pulse
Generator
(VDD, VSB) Status
System ACPI
State
PWBTOUT
Internal Crowbar
Indication
16 msec
Debouncer
PWBTIN
Figure 7. SWC Block Diagram
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3.0 System Wake-Up Control (SWC) (Continued)
In addition to the event detection and system notification capabilities, the SWC operates several general-purpose I/O pins
powered by VSB. These pins can be used to perform various tasks while VSB is present and VDD is not.
3.2 FUNCTIONAL DESCRIPTION
The SWC monitors 16 system events or activities. Upon entering the SWC, the events pass through a filter (where applica-
ble) and polarity adjustment logic. After filtering and polarity adjustment, each event enters the Wake-Up Mode Control (Ex-
tension) Logic, which determines its effect during the various system power states. The Wake-Up Mode Control (Extension)
Logic also controls the effect of each wake-up event on the power button output (PWBTOUT). See Figure 7 for an illustration
of this mechanism.
After the wake-up mode is determined for all events, each one of them is fed into a dedicated detector that determines when
this event is active, according to predetermined (either fixed or programmable) criteria. A set of dedicated registers is used
to determine the wake-up criteria, including the CEIR address and the keyboard sequence.
Two Wake-Up Events Status registers (WK_STSn) hold a Status bit for each of the 16 events.
Six Wake-Up Events Routing Control registers (WK_ENn WK_SMIENn and WK_IRQENn) hold three Routing Enable bits
for each of the 16 events to allow selective routing of these events to PWUREQ, SMI and/or the assigned SWC interrupt
request (IRQ) channel.
Upon detection of any active event, the corresponding Status bit is set to 1 regardless of any Routing Enable bit. If both the
Status bit and a Routing Enable bit corresponding to a specific event are set to 1 (no matter in what order), the output pin
corresponding to that Routing Enable bit is asserted. The Status bit is de-asserted by writing 1 to it. Writing 0 to a Routing
Enable bit of an event prevents it from issuing the corresponding system notification but does not affect the Status bit. Figure
8 show the routing scheme of detected wake-up events to the various means of system notification.
Wake-Up Event i
Event i
From Wake-Up
WK_STSn.i
Detection
Extension Logic
PWUREQ
SMI
WK_ENn.i
Event
Routing
Logic
WK_SMIENn.i
WK_IRQENn.i
IRQ
Figure 8. Wake-Up Events Routing Scheme
To enable the assertion of SMI by detected wake-up events, it is necessary to either select the SMI function on a device pin
or route it to an interrupt request channel via the device’s configuration registers.
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3.0 System Wake-Up Control (SWC) (Continued)
Six Wake-Up Extension Enable registers (WK_X1EN0,1 WK_X2EN0,1 and WK_X3EN0,1) hold three configuration bits for
each of the 16 events to allow selective routing of detected events to the Power Button (PWBTOUT) pulse generator and to
control the wake-up mode for each one of them. Figure 9 illustrates the Wake-Up Mode Control (Extension) mechanism.
Wake-Up Raw Event i
V
Present
To Event i
Detection
Logic
DD
Post V Power-On Silence
Post V Power-On Silence
DD
SB
Enable Power Button Pulse
To Power
Button
Pulse
Generator
WK_X1ENn.i
WK_X2ENn.i
WK_X3ENn.i
Figure 9. Wake-Up Mode Control (Extension) Mechanism
To operate the power button pulse generator, the PSLDC0,1 straps must be set to enable the Power Supply Control function
(see Section 2.6). In addition, one of the following conditions must be satisfied:
●
SLPS5 is active (the system is in Sleep State 5), or
●
Legacy Power Button is enabled, or
●
Power Button operation in Sleep State 3 is enabled.
The two latter conditions are determined by device configuration registers. (Refer to the Device Architecture and Configura-
tion chapter.)
In addition to monitoring various system events, the SWC operates several general-purpose I/O (GPIO) pins powered by
VSB. Four runtime data registers (SB_GPDOn and SB_GPDIn) hold a Data Out bit and a Data In bit for each VSB-powered
GPIO pin. In addition, each GPIO pin has a dedicated configuration register that controls its characteristics. These configu-
ration registers are accessed via a set of Standby GPIO Pin Select and Pin Configuration registers (SBGPSEL and SBG-
PCFG). For a detailed description of the VSB powered GPIO pins, see Section 3.4.30.
The SWC logic is powered by VSB. The SWC control and configuration registers are battery backed, powered by VPP. The
setup of the wake-up events, including programmable sequences, is retained throughout power failures (no VSB) as long as
the battery is connected. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the Device Char-
acteristics chapter; otherwise, VBAT is used as the VPP source.
Hardware reset does not affect these registers. They are reset only by software reset or power-up of VPP
.
3.3 EVENT DETECTION
3.3.1
Modem Ring
High-to-low transitions on RI1 or RI2 indicate the detection of a ring in an external modem connected to Serial Port 1 or Serial
Port 2, respectively, and can be used as wake-up events.
3.3.2
Telephone Ring
A telephone ring is detected by the SWC by processing the raw signal coming directly from the telephone line into the RING
input pin. Detection of a pulse-train with a frequency higher than 16 Hz lasting at least 0.19 sec is used as a wake-up event.
The RING pulse-train detection is achieved by monitoring the falling edges on RING in time slots of 62.5 msec (a 16 Hz
cycle). A positive detection occurs if falling edges of RING are detected in three consecutive time slots, following a time slot
in which no RING falling edge is detected. This detection method guarantees the detection of a RING pulse-train with fre-
quencies higher than 16 Hz. It filters out (does not detect) pulses of less than 10 Hz and may detect pulses between 10 Hz
to 16 Hz.
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3.0 System Wake-Up Control (SWC) (Continued)
3.3.3
Keyboard and Mouse Activity
The detection of either any activity or a specific predetermined keyboard or mouse activity can be used as a wake-up event.
The keyboard wake-up detection can be programmed to detect:
●
Any keystroke.
●
A specific programmable sequence of up to eight alphanumeric keystrokes.
●
Any programmable sequence of up to 8 bytes of data received from the keyboard.
The mouse wake-up detection can be programmed to detect either a mouse click or movement, a specific programmable
click (left or right) or double-clicks.
The keyboard or mouse event detection operates independently of the KBC (which is powered down with the rest of the system).
3.3.4
CEIR Address
A CEIR transmission received on an IRRX pin in a pre-selected standard (NEC, RCA or RC-5) is matched against a pro-
grammable CEIR address. Detection of a match can be used as a wake-up event.
Whenever an IR signal is detected, the receiver immediately enters the active state. When this happens, the receiver keeps
sampling the IR input signal and generates a bit string where a logic 1 indicates an idle condition and a logic 0 indicates the
presence of IR energy. The received bit string is de-serialized and assembled into 8-bit characters.
The expected CEIR protocol of the received signal should be configured through bits 5,4 at the CEIR Wake-Up Control reg-
ister (see Section 3.4.22).
The CEIR Wake-Up Address register (IRWAD) holds the unique address to be compared with the address contained in the
incoming CEIR message. If CEIR is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then the CEIR
Event Status bit of the WK_STS0 register is set to 1 (see Section 3.4.2).
The CEIR Address Shift register holds the received address, which is compared with the address contained in the IRWAD.
The comparison is affected also by the CEIR Wake-Up Address Mask register (IRWAM) in which each bit determines wheth-
er to ignore the corresponding bit in the IRWAD.
If CEIR routing to interrupt request is enabled, the assigned SWC interrupt request may be used to indicate that a complete
address has been received. To get this interrupt when the address is completely received, the IRWAM should be written with
FFh. Once the interrupt is received, the value of the address can be read from the ADSR register.
Another parameter used to determine whether a CEIR signal is to be considered valid is the bit cell time width. There are
four time ranges for the different protocols and carrier frequencies. Four pairs of registers define the low and high limits of
each time range. (See Sections 3.4.29 through for more details regarding the recommended values for each protocol.)
The CEIR address detection operates independently of the serial port with the IR (which is powered down with the rest of
the system).
3.3.5
Standby General-Purpose Input Events
A general-purpose event is defined as the detection of falling edge or rising edge on a specific signal. Each signal’s event
is configurable via software. GPIOE0-5 and GPIE6-7 may trigger a system notification by any of the means mentioned in
Section 3.1.
A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software.
3.3.6
GPIO-Triggered Events
A GPIO-triggered event is defined as the detection of falling edge or rising edge on a specific GPIO signal whose status bit
is routed to PWUREQ. Each signal’s event is configurable via software in the GPIO logical device configuration registers.
GPIO00-07, GPIO10-14, GPIO16-17 may trigger a system notification only by PWUREQ. Other means of system notification
triggered by GPIOs are available via the GPIO logical device configuration registers.
A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software.
All GPIO pins are powered by VDD and therefore can cause an assertion of PWUREQ only when VDD is present.
3.3.7
Software Event
A software event is defined as writing 1 to the Software Event Status bit of the WK_STS0 register. Once this bit is set to 1,
it has the same effect as any other Event Status bit.
Since WK_STS0 is accessible only when VDD is present, the Software Event can be activated only when VDD is present.
3.3.8
Module IRQ Wake-Up Event
A module IRQ wake-up event is defined as the leading edge of the IRQ assertion of any of the following logical devices:
FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB, Fan Speed Control and Monitor (FSCM), Game Port and MIDI
Port.
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3.0 System Wake-Up Control (SWC) (Continued)
To enable the IRQ of a specific logical device to trigger a wake-up event, the associated Enable bit must be set to 1. This is
bit 4 of the Interrupt Number and Wake-Up on IRQ Enable register, located at index 70h in the configuration space of the
logical device (see Table 10 in Device Architecture and Configuration chapter). When this bit is set, any IRQ assertion of the
corresponding logical device activates the module IRQ wake-up event. Therefore, the module IRQ wake-up event is a com-
bination of all IRQ signals of the logical devices for which wake-up on IRQ is enabled.
Note that index 70h has two functions: it is used to set IRQ and to enable wake-up on IRQ. If the BIOS routine that sets IRQ
does not use a Read-Modify-Write sequence, it might reset bit 4, which is the Wake-Up on IRQ bit. To ensure that the system
wakes up, the BIOS must set bit 4 before the system goes to sleep.
When the event is detected as active, its associated Status bit (bit 7 of the WK0_STS register) is set to 1. If the associated
Enable bit (bit 7 of the WK_EN0 register) is also set to 1, the PWUREQ output is asserted. It remains asserted until the Status
bit is cleared.
Since all the logical devices listed above are powered by VDD, a module IRQ event can be activated only when VDD is
present.
3.4 SWC REGISTERS
The SWC registers are organized in four banks, all of which are battery-backed. The offsets are related to a base address
that is determined by the SWC Base Address register in the device configuration registers. The lower 19 offsets are common
to the four banks, while the upper offsets (13-1fh) are divided as follows:
●
Bank 0 holds the Keyboard/Mouse Control registers.
●
Bank 1 holds the CEIR Control registers.
●
Bank 2 holds the Event Routing Configuration and Wake-Up Extension Control registers.
●
Bank 3 holds the Standby General-Purpose I/O (GPIO) Pins Configuration registers.
The active bank is selected through the Configuration Bank Select field (bits 1-0) in the Wake-Up Configuration register
(WK_CFG). See Section 3.4.6.
As a programming aid, the registers are described in this chapter according to the following functional groupings:
●
General status, enable, configuration and routing registers.
●
Extension enable registers.
●
PS/2 event configuration registers.
●
CEIR event configuration registers.
●
Standby GPIO configuration and control registers.
The following abbreviations are used to indicate the Register Type:
●
R/W = Read/Write.
●
R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
●
W = Write.
●
RO = Read Only.
●
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.1
SWC Register Map
The following tables list the SWC registers. For the SWC register bitmap, see Section 3.5.
Table 38. Banks 0, 1, 2 and 3 - The Common Control and Status Register Map
Offset
Mnemonic
WK_STS0
Register Name
Wake-Up Events Status 0
Type
Section
00h
01h
02h
03h
04h
R/W1C
R/W1C
R/W
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
WK_STS1
WK_EN0
WK_EN1
WK_CFG
Wake-Up Events Status 1
Wake-Up Enable 0
Wake-Up Enable 1
R/W
Wake-Up Configuration
R/W
05h-07h Reserved
08h
09h
0Ah
0Bh
SB_GPDO0
SB_GPDI0
SB_GPDO1
SB_GPDI1
Standby GPIOE/GPIE Data Out 0
Standby GPIOE/GPIE Data In 0
Standby GPOS Data Out 1
Standby GPIS Data In 1
R/W
RO
3.4.33
3.4.34
3.4.35
3.4.36
R/W
RO
0Ch-12h Reserved
Table 39. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Configuration and Control Register Map
Offset
Mnemonic
PS2CTL
Register Name
PS/2 Protocol Control
Type
Section
13h
R/W
3.4.18
14h-15h Reserved
16h
17h
KDSR
MDSR
Keyboard Data Shift
Mouse Data Shift
RO
RO
3.4.19
3.4.20
3.4.21
18h-1Fh PS2KEY0-PS2KEY7 PS/2 Keyboard Key Data
R/W
Table 40. Bank 1 - CEIR Wake-Up Configuration and Control Register Map
Offset
Mnemonic
IRWCR
Register Name
CEIR Wake-Up Control
Type
Section
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
R/W
3.4.22
Reserved
IRWAD
CEIR Wake-Up Address
R/W
R/W
R/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3.4.23
3.4.24
3.4.25
3.4.26
3.4.26
3.4.27
3.4.27
3.4.28
3.4.28
3.4.29
3.4.29
IRWAM
CEIR Wake-Up Address Mask
CEIR Address Shift
ADSR
IRWTR0L
IRWTR0H
IRWTR1L
IRWTR1H
IRWTR2L
IRWTR2H
IRWTR3L
IRWTR3H
CEIR Wake-Up, Range 0, Low Limit
CEIR Wake-Up, Range 0, High Limit
CEIR Wake-Up, Range 1, Low Limit
CEIR Wake-Up, Range 1, High Limit
CEIR Wake-Up, Range 2, Low Limit
CEIR Wake-Up, Range 2, High Limit
CEIR Wake-Up, Range 3, Low Limit
CEIR Wake-Up, Range 3, High Limit
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3.0 System Wake-Up Control (SWC) (Continued)
Table 41. Bank 2 - Event Routing Configuration Register Map
Offset
Mnemonic
WK_SMIEN0
Register Name
Wake-Up SMI Enable 0
Type
Section
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3.4.7
3.4.8
WK_SMIEN1
WK_IRQEN0
WK_IRQEN1
WK_X1EN0
WK_X1EN1
WK_X2EN0
WK_X2EN1
WK_X3EN0
WK_X3EN1
Wake-Up SMI Enable 1
Wake-Up Interrupt Request Enable 0
Wake-Up Interrupt Request Enable 1
Wake-Up Extension 1 Enable 0
Wake-Up Extension 1 Enable 1
Wake-Up Extension 2 Enable 0
Wake-Up Extension 2 Enable 1
Wake-Up Extension 3 Enable 0
Wake-Up Extension 3 Enable 1
3.4.9
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.4.15
3.4.16
1Dh-1Fh Reserved
Table 42. Bank 3 - Standby GPIO Pin Configuration Register Map
Offset
Mnemonic
SBGPSEL
SBGPCFG
Register Name
Standby GPIO Pin Select
Standby GPIO Pin Configuration
Type
Section
13h
14h
R/W
R/W
3.4.31
3.4.32
15h-1Fh Reserved
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.2
Wake-Up Events Status Register 0 (WK_STS0)
This register is set to 00h on power-up of VPP, VSB or software reset. It indicates which of the corresponding eight wake-up
events have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bit 6 of this register has a special type, as
described in the table below.
Location:
Type:
Offset 00h
R/W1C
Bit
7
6
5
4
3
2
1
0
Module IRQ Software
CEIR
Event
Status
Mouse
Event
Status
KBD
Event
Status
RI2
Event
Status
RI1
Event
Status
GPIO Event
Status
Name
Reset
Event
Event
Status
Status
0
0
0
0
0
0
0
0
Bit
Description
7
Module IRQ Event Status. This sticky bit shows the status of the module IRQ event detection.
0: Event not active (default)
1: Event active
6
5
Software Event Status. Writing 1 to this bit inverts its value.
0: Event not active (default)
1: Event active
GPIO Event Status. This sticky bit shows the status of the VDD GPIO event detection.
0: Event not detected (default)
1: Event detected
4
3
2
1
0
CEIR Event Status.
0: Event not detected (default)
1: Event detected
Mouse Event Status.
0: Event not detected (default)
1: Event detected
KBD Event Status.
0: Event not detected (default)
1: Event detected
RI2 Event Status.
0: Event not detected (default)
1: Event detected
RI1 Event Status.
0: Event not detected (default)
1: Event detected
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.3
Wake-Up Events Status Register (WK_STS1)
This register is set to 00h on power-up of VPP, VSB or software reset. It indicates which of the corresponding eight wake-up
events have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
Location:
Type:
Offset 01h
R/W1C
Bit
7
6
5
4
3
2
1
0
GPIE4/
RING
Event
Status
GPIE7
Event
Status
GPIE6
Event
Status
GPIE5
Event
Status
GPIE3
Event
Status
GPIE2
Event
Status
GPIE1
Event
Status
GPIE0
Event
Status
Name
Reset
0
0
0
0
0
0
0
0
Bit
Description
7
GPIE7 Event Status.
0: Event not detected (default)
1: Event detected
6
5
4
GPIE6 Event Status.
0: Event not detected (default)
1: Event detected
GPIE5 Event Status.
0: Event not detected (default)
1: Event detected
GPIE4/RING Event Status. This sticky bit shows the status of either GPIE4 or RING event detection, according
to the function currently selected on pin 27.
0: Event not detected (default)
1: Event detected
3
2
1
0
GPIE3 Event Status.
0: Event not detected (default)
1: Event detected
GPIE2 Event Status.
0: Event not detected (default)
1: Event detected
GPIE1 Event Status.
0: Event not detected (default)
1: Event detected
GPIE0 Event Status.
0: Event not detected (default)
1: Event detected
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.4
Wake-Up Events Enable Register (WK_EN0)
This register is set to 00h on power-up of VPP or software reset. Detected wake-up events that are enabled activate the
PWUREQ signal.
Location:
Type:
Offset 02h
R/W
Bit
7
6
5
4
3
2
1
0
Module IRQ Software
CEIR
Event
Enable
Mouse
Event
Enable
KBD
Event
Enable
RI2
Event
Enable
RI1
Event
Enable
GPIO Event
Enable
Name
Reset
Event
Event
Enable
Enable
0
0
0
0
0
0
0
0
Bit
Description
7
6
5
4
3
2
1
0
Module IRQ Event Enable.
0: Disabled (default)
1: Enabled
Software Event Enable.
0: Disabled (default)
1: Enabled
GPIO Event Enable.
0: Disabled (default)
1: Enabled
CEIR Event Enable.
0: Disabled (default)
1: Enabled
Mouse Event Enable.
0: Disabled (default)
1: Enabled
KBD Event Enable.
0: Disabled (default)
1: Enabled
RI2 Event Enable.
0: Disabled (default)
1: Enabled
RI1 Event Enable.
0: Disabled (default)
1: Enabled
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.5
Wake-Up Events Enable Register 1 (WK_EN1)
This register is set to 00h on power-up of VPP or software reset. Detected wake-up events that are enabled activate the
PWUREQ signal.
Location:
Type:
Offset 03h
R/W
Bit
7
6
5
4
3
2
1
0
GPIE4/
RING
Event
Enable
GPIE7
Event
Enable
GPIE6
Event
Enable
GPIE5
Event
Enable
GPIE3
Event
Enable
GPIE2
Event
Enable
GPIE1
Event
Enable
GPIE0
Event
Enable
Name
Reset
0
0
0
0
0
0
0
0
Bit
Description
7
6
5
4
3
2
1
0
GPIE7 Event Enable.
0: Disabled (default)
1: Enabled
GPIE6 Event Enable.
0: Disabled (default)
1: Enabled
GPIE5 Event Enable.
0: Disabled (default)
1: Enabled
GPIE4/RING Event Enable.
0: Disabled (default)
1: Enabled
GPIE3 Event Enable.
0: Disabled (default)
1: Enabled.
GPIE2 Event Enable.
0: Disabled (default)
1: Enabled
GPIE1 Event Enable.
0: Disabled (default)
1: Enabled
GPIE0 Event Enable.
0: Disabled (default)
1: Enabled
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.6
Wake-Up Configuration Register (WK_CFG)
This register is set to 00h on power-up of VPP or software reset. It enables access to CEIR registers, keyboard/mouse reg-
isters, Event Routing Control registers or Standby GPIO registers.
Location:
Type:
Offset 04h
R/W
Bit
7
6
5
0
4
0
3
2
1
0
Enable
Power
Button
Swap KBC
Inputs
Configuration Bank
Select
Name
Reserved
Pulse on S3
Reset
0
0
0
0
0
0
0
0
Required
Bit
Description
7-4 Reserved.
3
Enable Power Button Pulse on S3.
0: Disabled (default)
1: Enabled
2
Swap KBC Inputs.
0: No swapping (default)
1: KBD (KBCLK, KBDAT) and Mouse (MCLK, MDAT) inputs swapped
1-0 Configuration Bank Select.
Bits
1 0
Bank
Register
0 0
0 1
1 0
1 1
0
1
2
3
Keyboard/Mouse
CEIR
Event Routing, Wake-Up Extension
Standby GPIO
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.7
Wake-Up Events Routing to SMI Enable Register 0 (WK_SMIEN0)
This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the
SMI signal. Detected wake-up events that are enabled activate the SMI signal regardless of the value of the WK_EN0 reg-
ister.
Location:
Type:
Bank 2, Offset 13h
R/W
Bit
7
6
5
Reserved
0
4
3
2
1
0
Software
Event to
SMI Enable
CEIR
Event to
Mouse
Event to
KBD
Event to
RI2
Event to
RI1
Event to
Name
Reset
Reserved
SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable
0
0
0
0
0
0
0
Bit
Description
7
6
Reserved.
Software Event to SMI Enable.
0: Disabled (default)
1: Enabled
5
4
Reserved.
CEIR Event to SMI Enable.
0: Disabled (default)
1: Enabled
3
2
1
0
Mouse Event to SMI Enable.
0: Disabled (default)
1: Enabled
KBD Event to SMI Enable.
0: Disabled (default)
1: Enabled
RI2 Event to SMI Enable.
0: Disabled (default)
1: Enabled
RI1 Event to SMI Enable.
0: Disabled (default)
1: Enabled
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.8
Wake-Up Events Routing to SMI Enable Register 1 (WK_SMIEN1)
This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the
SMI signal. Detected wake-up events that are enabled activate the SMI signal regardless of the value of the WK_EN1 reg-
ister.
Location:
Type:
Bank 2, Offset 14h
R/W
Bit
7
6
5
4
3
2
1
0
GPIE4/
RING
Event to
SMI Enable
GPIE7
Event to
GPIE6
Event to
GPIE5
Event to
GPIE3
Event to
GPIE2
Event to
GPIE1
Event to
GPIE0
Event to
Name
Reset
SMI Enable SMI Enable SMI Enable
SMI Enable SMI Enable SMI Enable SMI Enable
0
0
0
0
0
0
0
0
Bit
Description
7
6
5
4
3
2
1
0
GPIE7 Event to SMI Enable.
0: Disabled (default)
1: Enabled
GPIE6 Event to SMI Enable.
0: Disabled (default)
1: Enabled
GPIE5 Event to SMI Enable.
0: Disabled (default)
1: Enabled
GPIE4/RING Event to SMI Enable.
0: Disabled (default)
1: Enabled
GPIE3 Event to SMI Enable.
0: Disabled (default)
1: Enabled.
GPIE2 Event to SMI Enable.
0: Disabled (default)
1: Enabled
GPIE1 Event to SMI Enable.
0: Disabled (default)
1: Enabled
GPIE0 Event to SMI Enable.
0: Disabled (default)
1: Enabled
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.9
Wake-Up Events Routing to IRQ Enable Register 0 (WK_IRQEN0)
This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the
assigned SWC interrupt request (IRQ) channel. Detected wake-up events that are enabled activate the assigned IRQ chan-
nel regardless of the value of the WK_EN0 register.
Location:
Type:
Bank 2, Offset 15h
R/W
Bit
7
6
5
Reserved
0
4
3
2
1
0
Software
Event to
IRQ Enable
CEIR
Event to
Mouse
Event to
KBD
Event to
RI2
Event to
RI1
Event to
Name
Reset
Reserved
IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable
0
0
0
0
0
0
0
Bit
Description
7
6
Reserved.
Software Event to IRQ Enable.
0: Disabled (default)
1: Enabled
5
4
Reserved.
CEIR Event to IRQ Enable.
0: Disabled (default)
1: Enabled
3
2
1
0
Mouse Event to IRQ Enable.
0: Disabled (default)
1: Enabled
KBD Event to IRQ Enable.
0: Disabled (default)
1: Enabled.
RI2 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
RI1 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.10 Wake-Up Events Routing to IRQ Enable Register 1 (WK_IRQEN1)
This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the
assigned SWC IRQ channel. Detected wake-up events that are enabled activate the IRQ signal regardless of the value of
the WK_EN1 register.
Location:
Type:
Bank 2, Offset 16h
R/W
Bit
7
6
5
4
3
2
1
0
GPIE4/
RING
Event to
IRQ Enable
GPIE7
Event to
GPIE6
Event to
GPIE5
Event to
GPIE3
Event to
GPIE2
Event to
GPIE1
Event to
GPIE0
Event to
Name
Reset
IRQ Enable IRQ Enable IRQ Enable
IRQ Enable IRQ Enable IRQ Enable IRQ Enable
0
0
0
0
0
0
0
0
Bit
Description
7
6
5
4
3
2
1
0
GPIE7 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
GPIE6 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
GPIOE5 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
GPIE4/RING Event to IRQ Enable.
0: Disabled (default)
1: Enabled
GPIE3 Event to IRQ Enable.
0: Disabled (default)
1: Enabled.
GPIE2 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
GPIE1 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
GPIE0 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.11 Wake-Up Extension 1 Enable Register 0 (WK_X1EN0)
This register is set to 1Fh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event de-
tectors while VDD is present. Wake-up events that are enabled are routed to their event detectors while VDD is present.
Location:
Type:
Bank 2, Offset 17h
R/W
Bit
7
6
5
0
4
3
2
1
0
CEIR
Mouse
KBD
RI2
RI1
Name
Reset
Reserved
Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex.1
Enable
Enable
Enable
Enable
Enable
0
0
1
1
1
1
1
Bit
Description
7-5 Reserved.
4
3
2
1
0
CEIR Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
Mouse Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
KBD Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
RI2 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
RI1 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.12 Wake-Up Extension 1 Enable Register 1 (WK_X1EN1)
This register is set to FFh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event de-
tectors while VDD is present. Wake-up events that are enabled are routed to their event detectors while VDD is present.
Location:
Type:
Bank 2, Offset 18h
R/W
Bit
7
6
5
4
3
2
1
0
GPIE4/
RING
Event Ex. 1
Enable
GPIE7
GPIE6
GPIE5
GPIE3
GPIE2
GPIE1
GPIE0
Name
Reset
Event Ex. 1 Event Ex. 1 Event Ex. 1
Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit
Description
7
6
5
4
3
2
1
0
GPIE7 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
GPIE6 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
GPIE5 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
GPIE4/RING Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
GPIE3 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
GPIE2 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
GPIE1 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
GPIE0 Event Extension 1 Enable.
0: Disabled
1: Enabled (default)
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.13 Wake-Up Extension 2 Enable Register 0 (WK_X2EN0)
This register is set to 1Fh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event de-
tectors while VDD is not present. Wake-up events that are enabled are routed to their event detectors while VDD is not
present.
Location:
Type:
Bank 2, Offset 19h
R/W
Bit
7
6
5
0
4
3
2
1
0
CEIR
Mouse
KBD
RI2
RI1
Name
Reset
Reserved
Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2
Enable
Enable
Enable
Enable
Enable
0
0
1
1
1
1
1
Bit
Description
7-5 Reserved.
4
3
2
1
0
CEIR Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
Mouse Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
KBD Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
RI2 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
RI1 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.14 Wake-Up Extension 2 Enable Register 1 (WK_X2EN1)
This register is set to FFh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event de-
tectors while VDD is not present. Wake-up events that are enabled are routed to their event detectors while VDD is not
present.
Location:
Type:
Bank 2, Offset 1Ah
R/W
Bit
7
6
5
4
3
2
1
0
GPIE4/
RING
Event Ex. 2
Enable
GPIE7
GPIE6
GPIE5
GPIE3
GPIE2
GPIE1
GPIE0
Name
Reset
Event Ex. 2 Event Ex. 2 Event Ex. 2
Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit
Description
7
6
5
4
3
2
1
0
GPIE7 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
GPIE6 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
GPIE5 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
GPIE4/RING Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
GPIE3 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
GPIE2 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
GPIE1 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
GPIE0 Event Extension 2 Enable.
0: Disabled
1: Enabled (default)
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.15 Wake-Up Extension 3 Enable Register 0 (WK_X3EN0)
This register is set to 00h on power-up of VPP or software reset. It controls the routing of raw wake-up events to the Power
Button pulse generator. Wake-up events that are enabled are routed to the Power Button pulse generator.
Location:
Type:
Bank 2, Offset 1Bh
R/W
Bit
7
6
5
0
4
3
2
1
0
CEIR
Mouse
KBD
RI2
RI1
Name
Reset
Reserved
Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3
Enable
Enable
Enable
Enable
Enable
0
0
0
0
0
0
0
Bit
Description
7-5 Reserved.
4
3
2
1
0
CEIR Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
Mouse Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
KBD Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
RI2 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
RI1 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.16 Wake-Up Extension 3 Enable Register 1 (WK_X3EN1)
This register is set to 00h on power-up of VPP or software reset. It controls the routing of raw wake-up events to the Power
Button pulse generator. Wake-up events that are enabled are routed to the Power Button pulse generator.
Location:
Type:
Bank 2, Offset 1Ch
R/W
Bit
7
6
5
4
3
2
1
0
GPIE3/
RING
Event Ex. 3
Enable
GPIE7
GPIE6
GPIE5
GPIE3
GPIE2
GPIE1
GPIE0
Name
Reset
Event Ex. 3 Event Ex. 3 Event Ex. 3
Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3
Enable
Enable
Enable
Enable
Enable
Enable
Enable
0
0
0
0
0
0
0
0
Bit
Description
7
6
5
4
3
2
1
0
GPIE7 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
GPIE6 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
GPIE5 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
GPIE4/RING Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
GPIE3 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
GPIE2 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
GPIE1 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
GPIE0 Event Extension 3 Enable.
0: Disabled (default)
1: Enabled
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.17 PS/2 Keyboard and Mouse Wake-Up Events
The SWC can be configured to detect any predetermined PS/2 keyboard or mouse activity.
The detection mechanisms for keyboard and mouse events are independent. Therefore, they can be operated simulta-
neously with no interference. Since both mechanisms are implemented by hardware, which is independent of the device’s
keyboard controller, the keyboard controller itself need not be activated to detect either keyboard or mouse events.
Keyboard Wake-Up Events
The keyboard wake-up detection mechanism can be programmed to detect:
●
Any keystroke.
●
A specific programmable sequence of up to eight alphanumeric keystrokes (Password mode).
●
Any programmable sequence of up to 8 bytes of data received from the keyboard (Special Key Sequence mode).
To program the keyboard wake-up detection mechanism to wake-up on any keystroke, perform the following sequence:
1. Put the wake-up mechanism in Special Key Sequence mode by setting bits 3-0 of the PS2CTL register to 0001b.
2. Set the PS2KEY0 and PS2KEY1 registers to 00h. This forces the wake-up detection mechanism to ignore the values of
incoming data, thus causing it to wake-up on any keystroke.
In Password mode, the Make and Break bytes transmitted by the keyboard are discarded, and only the scan codes are com-
pared against those programmed in the PS2KEYn registers. To simplify the detection mechanism, only keys with a scan
code of 1 byte can be included in the sequence to be detected. To program the keyboard wake-up detection mechanism to
operate in Password mode, proceed as follows:
1. Set bits 3-0 of the PS2CTL register with a value that indicates the desired number of keystrokes in the sequence. The
programmed value should be the number of keystrokes + 7. For example, to wake-up on a sequence of two keys, set
bits 3-0 to 9h.
2. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers, in sequential order, with the scan codes of the
keys in the sequence. For example, if there are three keys in the sequence and the scan codes of these keys are 05h
(first), 50h (second) and 44h (third), program PS2KEY0 to 05h, PS2KEY1 to 50h and PS2KEY2 to 44h (the scan codes
are only examples).
In Special Key Sequence mode, all the bytes transmitted by the keyboard are compared against the ones programmed in
the PS2KEYn registers. These include the Make and Break bytes. This mode enables the detection of any sequence of key-
strokes, including keys such as Shift and Alt. To program the keyboard wake-up detection mechanism to operate in Special
Key Sequence mode, proceed as follows:
1. Set bits 3-0 of the PS2CTL register to a value that indicates the desired number of keystrokes in the sequence. The pro-
grammed value should be the number of keystrokes + 1. For example, to wake-up on a sequence of three received bytes,
set bits 3-0 of PS2CTL to 2h.
2. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers in sequential order with the values of the data bytes
that comprise the sequence. For example, if the number of bytes in the sequence is four and the values of these bytes
are E0h (first), 5Bh (second), E0h (third) and DBh (fourth), program PS2KEY0 to E0h, PS2KEY1 to 5Bh, PS2KEY2 to
E0h and PS2KEY3 to DBh (the byte values are only examples).
Mouse Wake-Up Events
The mouse wake-up detection mechanism can be programmed to detect either a mouse click or movement, a specific pro-
grammable click (left or right) or double-click.
To program this mechanism to wake-up on a specific event, set bits 6-4 of the PS2CTL register to the required value, ac-
cording to the description of these bits in Section 3.4.18.
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.18 PS/2 Protocol Control Register (PS2CTL)
This register is set to 00h on power-up of VPP or software reset. It configures the PS/2 keyboard and mouse wake-up fea-
tures. Before changing bits 6-4 or 3-0, clear them to 0 and then write the new value.
Location:
Type:
Bank 0, Offset 13h
R/W
Bit
7
6
5
4
3
0
2
1
0
0
Disable
Parity
Check
Name
Reset
Mouse Wake-Up Configuration
Keyboard Wake-Up Configuration
0
0
0
0
0
0
Bit
Description
7
Disable Parity Check.
0: Enabled (default)
1: Disabled
6-4 Mouse Wake-Up Configuration.
Bits
6 5 4 Configuration
0 0 0 Disable mouse wake-up detection
0 0 1 Wake-up on any mouse movement or button click
0 1 0 Wake-up on left button click
0 1 1 Wake-up on left button double-click
1 0 0 Wake-up on right button click
1 0 1 Wake-up on right button double-click
1 1 0 Wake-up on any button single-click (left, right or middle)
1 1 1 Wake-up on any button double-click (left, right or middle)
3-0 Keyboard Wake-Up Configuration.
Bits
3 2 1 0
Configuration
0 0 0 0
Disable keyboard wake-up detection
0 0 0 1
to
0 1 1 1
Special key sequence 2-8 PS/2 scan codes, “Make” and “Break” (including Shift and Alt keys)
}
}
1 0 0 0
to
1 1 1 1
Password enabled with 1-8 keys “Make” code (excluding Shift and Alt keys)
3.4.19 Keyboard Data Shift Register (KDSR)
This register is set to 00h on power-up of VPP or software reset. It stores the keyboard data shifted in from the keyboard
during transmission only when keyboard wake-up detection is enabled.
Location:
Type:
Bank 0, Offset 16h
RO
Bit
7
6
0
5
0
4
3
2
0
1
0
0
0
Name
Reset
Keyboard Data
0
0
0
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.20 Mouse Data Shift Register (MDSR)
This register is set to 00h on power-up of VSB or software reset. It stores the mouse data shifted in from the mouse during
transmission only when mouse wake-up detection is enabled.
Location:
Type:
Bank 0, Offset 17h
RO
Bit
7
6
0
5
Reserved
0
4
0
3
0
2
0
1
0
0
Name
Reset
Mouse Data
0
0
3.4.21 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7)
Eight registers (PS2KEY0-PS2KEY7) store the scan codes for the password or key sequence of the keyboard wake-up fea-
ture, as follows:
●
PS2KEY0 register stores the scan code for the first key in the password/key sequence.
●
PS2KEY1 register stores the scan code for the second key in the password/key sequence.
●
PS2KEY2 - PS2KEY7 registers store the scan codes for the third to eighth keys in the password/key sequence.
When one of these registers is set to 00h, it indicates that the value of the corresponding scan code byte is ignored (not
compared). These registers are set to 00h on power-up of VPP or software reset.
Location:
Type:
Bank 0, Offset 18h-1Fh
R/W
Bit
7
6
5
0
4
3
2
0
1
0
0
0
Name
Reset
Scan Code of Keys 0-7
0
0
0
0
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.22 CEIR Wake-Up Control Register (IRWCR)
This register is set to 00h on power-up of VPP or software reset.
Location:
Type:
Bank 1, Offset 13h
R/W
Bit
7
6
0
5
4
3
2
1
Reserved
0
0
Select
IRRX2 Input IRRXn Input
Invert
CEIR
Enable
Name
Reset
Reserved
CEIR Protocol Select
0
0
0
0
0
0
Bit
Description
7-6 Reserved.
5-4 CEIR Protocol Select.
Bits
5 4
0 0
0 1
1 X
Protocol
RC5 (default)
NEC/RCA
Reserved
3
2
Select IRRX2 Input. Selects the IRRX input.
0: IRRX1 (default)
1: IRRX2
Invert IRRXn Input.
0: Not inverted (default)
1: Inverted
1
0
Reserved.
CEIR Enable.
0: CEIR is disabled (default). Registers are maintained but CEIR Event Status bit (of WK0_STS) does not
reflect CEIR events. (Unlike the CEIR Event Enable bit of WK0_EN that does not affect the CEIR Event
Status bit.)
1: CEIR is enabled
.
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.23 CEIR Wake-Up Address Register (IRWAD)
This register holds the unique address to be compared with the address contained in the incoming CEIR message. If CEIR
is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WK0_STS register is set to 1
(see Section 3.4.2).
This register is set to 00h on power-up of VPP or software reset.
Location:
Type:
Bank 1, Offset 15h
R/W
Bit
7
6
0
5
0
4
3
2
0
1
0
0
0
Name
Reset
CEIR Wake-Up Address
0
0
0
3.4.24 CEIR Wake-Up Address Mask Register (IRWAM)
Each bit in this register determines whether the corresponding bit in the IRWAD register is enabled in the address compar-
ison. Bits 5, 6 and 7 must be set to 1 if the RC-5 protocol is selected.
This register is set to E0h on power-up of VPP or software reset.
Location:
Type:
Bank 1, Offset 16h
R/W
Bit
7
6
1
5
1
4
3
2
0
1
0
0
0
Name
Reset
CEIR Wake-Up Address Mask
1
0
0
Bit
Description
7-0 CEIR Wake-Up Address Mask. If the corresponding bit is 0, the address bit is not masked (enabled for
compare). If the corresponding bit is 1, the address bit is masked (ignored during compare).
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.25 CEIR Address Shift Register (ADSR)
This register holds the received address to be compared with the address contained in the IRWAD register.
This register is set to 00h on power-up of VPP or software reset.
Location:
Type:
Bank 1, Offset 17h
RO
Bit
7
6
0
5
0
4
3
2
0
1
0
0
0
Name
Reset
CEIR Address
0
0
0
3.4.26 CEIR Wake-Up Range 0 Registers
These registers define the low and high limits of time range 0. The values are represented in units of 0.1 msec.
For the RC-5 protocol, the bit cell width must fall within this range for the cell to be considered valid. The nominal cell width
is 1.778 msec for a 36 KHz carrier. IRWTR0L and IRWTR0H should be set to 10h and 14h respectively (default).
For the NEC protocol, the time distance between two consecutive CEIR pulses that encodes a bit value of 0 must fall within
this range. The nominal distance for a 0 is 1.125 msec for a 38 KHz carrier. IRWTR0L and IRWTR0H should be set to 09h
and 0Dh respectively.
IRWTR0L Register
This register is set to 10h on power-up of VPP or software reset.
Location:
Type:
Bank 1, Offset 18h
R/W
Bit
7
6
5
0
4
1
3
2
1
0
0
Name
Reset
Reserved
CEIR Pulse Change, Range 0, Low Limit
0 0 0
0
0
IRWTR0H Register
This register is set to 14h on power-up of VPP or software reset.
Location:
Type:
Bank 1, Offset 19h
R/W
Bit
7
6
5
0
4
1
3
2
1
0
0
Name
Reset
Reserved
CEIR Pulse Change, Range 0, High Limit
0
0
0
1
0
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.27 CEIR Wake-Up Range 1 Registers
These registers define the low and high limits of time range 1. The values are represented in units of 0.1 msec.
For the RC-5 protocol, the pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid.
The nominal pulse width is 0.889 for a 38 KHz carrier. IRWTR1L and IRWTR1H should be set to 07h and 0Bh, respectively (de-
fault).
For the NEC protocol, the time between two consecutive CEIR pulses that encodes a bit value of 1 must fall within this range.
The nominal time for a 1 is 2.25 msec for a 36 KHz carrier. IRWTR1L and IRWTR1H should be set to 14h and 19h respectively.
IRWTR1L Register
This register is set to 07h on power-up of VPP or software reset.
Location:
Type:
Bank 1, Offset 1Ah
R/W
Bit
7
6
5
0
4
0
3
2
1
0
1
Name
Reset
Reserved
CEIR Pulse Change, Range 1, Low Limit
0 1 1
0
0
IRWTR1H Register
This register is set to 0Bh on power-up of VPP or software reset.
Location:
Type:
Bank 1, Offset 1Bh
R/W
Bit
7
6
5
0
4
0
3
2
1
0
1
Name
Reset
Reserved
CEIR Pulse Change, Range 1, High Limit
0
0
1
0
1
3.4.28 CEIR Wake-Up Range 2 Registers
These registers define the low and high limits of time range 2. The values are represented in units of 0.1 msec. These reg-
isters are not used when the RC-5 protocol is selected.
For the NEC protocol, the header pulse width must fall within this range in order for the header to be considered valid. The
nominal value is 9 msec for a 38 KHz carrier. IRWTR2L and IRWTR2H should be set to 50h and 64h respectively (default).
IRWTR2L Register
This register is set to 50h on power-up of Vpp or software reset.
Location:
Type:
Bank 1, Offset 1Ch
R/W
Bit
7
6
1
5
4
3
2
1
0
0
0
Name
Reset
CEIR Pulse Change, Range 2, Low Limit
0
0
1
0
0
IRWTR2H Register
This register is set to 64h on power-up of Vpp or software reset.
Location:
Type:
Bank 1, Offset 1Dh
R/W
Bit
7
6
1
5
4
3
2
1
0
0
0
Name
Reset
CEIR Pulse Change, Range 2, High Limit
0
1
0
0
1
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.29 CEIR Wake-Up Range 3 Registers
These registers define the low and high limits of time range 3. The values are represented in units of 0.1 msec. These reg-
isters are not used when the RC-5 protocol is selected.
For the NEC protocol, the post header gap width must fall within this range in order for the gap to be considered valid. The
nominal value is 4.5 msec for a 36 KHz carrier. IRWTR3L and IRWTR3H should be set to 28h and 32h respectively (default).
IRWTR3L Register
This register is set to 28h on power-up of Vpp or software reset.
Location:
Type:
Bank1, Offset 1Eh
R/WS
Bit
7
6
0
5
4
3
2
1
0
0
0
Name
Reset
CEIR Pulse Change, Range 3, Low Limit
1 0
0
1
0
IRWTR3H Register
This register is set to 32h on power-up of Vpp or software reset.
Location:
Type:
Bank 1, Offset 1Fh
R/W
Bit
7
6
0
5
4
3
2
1
1
0
0
Name
Reset
CEIR Pulse Change, Range 3, High Limit
0
1
1
0
0
CEIR Recommended Values
Table 43 lists the recommended time ranges limits for the different protocols and their four applicable ranges. The values
are represented in hexadecimal code where the units are of 0.1 msec.
Table 43. Time Range Limits for CEIR Protocols
RC-5
NEC
RCA
Range
Low Limit High Limit Low Limit High Limit Low Limit High Limit
0
1
2
3
10h
07h
−
14h
0Bh
−
09h
14h
50h
28h
0Dh
19h
64h
32h
0Ch
16h
B4h
23h
12h
1Ch
DCh
2Dh
−
−
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.30 Standby General-Purpose I/O (SBGPIO) Register Overview
The SWC can be used to operate up to 12 VSB-powered general-purpose input/output (GPIO), input (GPI) or output (GPO)
pins, eight of which support event detection. These are as follows:
●
GPIOE0-5 are GPIO pins.
●
GPIE6,7 and GPIS2,3 are GPI pins.
●
GPOS0,1 are GPO pins.
For programming convenience, these pins are associated with two SBGPIO ports. Specifically, GPIE0-5 and GPIE6,7 are
associated with bits 0 to 7 of SBGPIO port 0, respectively, and GPOS0,1 and GPIS2,3 are associated with bits 0 to 3 of
SBGPIO port 1, respectively.
Table 44 provides a summary of the SBGPIO pin-to-port assignment and pin types.
Table 44. SBGPIO Pin Types and Associated Port
Event
Detection
Pin(s)
Port
Type
GPIOE0-5
GPIE6,7
GPOS0,1
GPIS2,3
0
0
1
1
I/O
Yes
Yes
No
I
O
I
No
An SBGPIO port is structured as an 8-bit port, based on eight pins. It features:
• Software capability to manipulate and read pin levels.
• Controllable system notification by several means based on the pin level’s transition.
• Ability to capture and manipulate events and their associated status.
• Back-drive protected pins.
SBGPIO port operation is associated with two sets of registers:
• Pin configuration registers, mapped in the SWC register bank 3. These registers are used to statically set up the log-
ical behavior of each pin. There is one 8-bit register for each SBGPIO pin.
• Two 8-bit runtime registers: SBGPIO Data Out (SBGPDO) and SBGPIO Data In (SBGPDI). These registers are
mapped in the SWC device I/O space (determined by the base address registers in the SWC Device Configuration).
They are used to manipulate and/or read the pin values. Each runtime register corresponds to the 8-pin port de-
scribed above (see Table 44).
Each SBGPIO pin is associated with up to six configuration bits and the corresponding bit slice of the two runtime registers,
as shown in Figure 10.
The SBGPIO port has basic as well as enhanced functionality. Basic functionality includes the manipulation and reading of
the SBGPIO pins, as described in Section 6.2 on page 130. Enhanced functionality includes event detection, as described
in Event Detection on page 113.
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3.0 System Wake-Up Control (SWC) (Continued)
Bit n
SBGPDOX
SBGPDIX
SBGPIOX Base Address
Runtime
Registers
8 SBGPIO Pin Configuration
Registers
X = port number
n = pin number, 0 to 7
SBGPIO Pin
Configuration Register
SBGPIO Port X
Pin n
SBGPIOXn CNFG
SBGPIOXn
Pin Logic
x8
Port and Pin
SBGPIO Pin
Select Register
Select
x8
Event
Pending
Indicator
To Wake-Up
Logic
x8
Figure 10. SBGPIO Port Architecture
Basic Functionality
The basic functionality of each SBGPIO pin is based on four configuration bits and a bit slice of runtime registers SBGPDO
and SBGPDI. The configuration and operation of a single pin (pin n in port X) is shown in Figure 11.
Read Only
Data In
Static
Push-Pull=1
Pull-Up
Pin
Read/Write
Data Out
Internal
Bus
Pull-Up
Enable
Output
Enable
Output
Type
Pull-Up
Control
Lock
Bit 3
Bit 2
Bit 1
Bit 0
SBGPIO Pin Configuration Register
Figure 11. SBGPIO Basic Functionality
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3.0 System Wake-Up Control (SWC) (Continued)
Configuration Options
The SBGPIO Pin Configuration register controls the following basic configuration options:
• Pin Direction - Controlled by Output Enable (bit 0).
• Output Type - Push-pull vs. open-drain. It is controlled by Output Type (bit 1) by enabling/disabling the pull-up portion of
the output buffer.
• Weak Static Pull-up - May be added to any type of port (input, open-drain or totem pole). It is controlled by Pull-Up Control
(bit 2).
• Pin Lock - A GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The
lock is controlled by Lock (bit 3). It disables writes to the SBGPDO register bits and to bits 0-3 of the Standby GPIO Pin
Configuration register (Including the Lock bit itself). Once locked, it can be released by hardware reset only.
Operation
The value that is written to the SBGPDO register is driven to the pin, if the output is enabled. Reading from the SBGPDO
register returns its contents, regardless of the pin value or the port configuration. The SBGPDI register is a read-only register.
Reading from the SBGPDI register returns the pin value, regardless of what is driving it (the port itself, configured as an
output port, or the external device when the port is configured as an input port). Writing to this register is ignored.
Activation of the SBGPIO port is controlled by the same external, device-specific configuration bit (or a combination of bits)
that control the activation of the SWC. When the SWC logical device is inactive, access to both the SBGPDI and SBGPDO
registers is disabled. However, there is no change in the port configuration and in the SBGPDO value and hence there is no
effect on the outputs of the pins.
Event Detection
The enhanced SBGPIO port supports input event detection. This functionality is based on three configuration bits. The con-
figuration and operation of the event detection capability is shown in Figure 12. An SWC status register reflects the status
of each input event. SWC configuration registers determine the effect of each input event on the various means of system
notification available in the SWC.
Event
Pending
Indicator
R/W
Event
Enable
0
1
Rising
Edge
Detector
R/W 1 to Clear
Input
Status
Debouncer
Detected
Pin
Enabled Events
from other
SBGPIO Pins
Rising Edge =1
Internal
Bus
Event
Debounce
Event Polarity
Bit 5
Enable
Bit 6
SBGPIO Pin Configuration Register
Figure 12. Event Detection
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3.0 System Wake-Up Control (SWC) (Continued)
Event Configuration
Each pin in the SBGPIO port is a potential input event source. The event detection can trigger a system notification upon predeter-
mined behavior of the source pin. The SBGPIO Pin Configuration register determines the event detection trigger type for the system
notification.
• Event Type and Polarity - One trigger type of event detection is supported: edge (Event Type, bit 4 = 0). An edge event
may be detected upon a source pin transition either from high to low or low to high. The direction of the transition (i.e.,
edge) is determined by Event Polarity (bit 5).
• Event Debounce Enable - The input signal can be debounced for about 15 msec before entering the detector. The signal
state is transferred to the detector only after a debouncing period during which the signal has no transitions, to ensure
that the signal is stable. The debouncer adds 15 msec delay to both assertion and de-assertion of the event pending
indicator. Therefore, when working with a level event and system notification by either SMI or IRQ, it is recommended
to disable the debounce if the delay in the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event
Debounce Enable (bit 6 of the SBGPIO Pin Configuration register).
3.4.31 Standby GPIO Pin Select Register (SBGPSEL)
This register selects the GPIOE/GPIE pin (port number and pin number) to be configured (the register accessed by the
Standby GPIO Pin Configuration register). This register is reset to 00h on VPP power-up or software reset.
When port 0 is selected, bits 2-0 select between pins GPIE7,6 and GPIOE5-0. When port 1 is selected, bits 2-0 select be-
tween pins GPOS0 and GPOS1. Pins GPIS2 and GPIS3 are input only and require no configuration.
Location:
Type:
Bank 3, Offset 13h
R/W
Bit
7
6
5
0
4
3
2
0
1
Pin Select
0
0
0
Name
Reset
Reserved
Port Select Reserved
0
0
0
0
Bit
Description
7-5 Reserved.
4
Port Select. This bit selects the GPIO port to be configured.
0: Port 0 (default)
1: Port 1
3
Reserved.
2-0 Pin Select. These bits select the GPIO pin to be configured in the selected port.
000, 001, ... 111:The binary value of the pin number, 0, 1, ... 7 respectively (default=0)
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.32 Standby GPIO Pin Configuration Register (SBGPCFG)
This is a group of 12 configuration registers. Eight are identical for GPIOE and GPIE, two are identical for GPOS and two
are identical for GPIS. Each GPIOE/GPIE register is associated with one GPIOE/GPIE pin, and each GPOS and GPIS reg-
ister is associated with one GPOS or GPIS pin. The entire set is mapped to the same address. The mapping scheme is
based on the Standby GPIO Pin Select (SBGPSEL) register that functions as an index register and the specific Standby
GPIO Pin Configuration register that reflects the configuration of the currently selected pin.
Bits 0-3 are applicable only for pins GPIOE0-5 and GPOS0,1. Bits 4-6 are applicable for all GPIOE/GPIE pins.
Location:
Type:
Bank 3, Offset 14h
R/W (bit 3 is set only)
For GPIOE and GPIE:
Bit
7
6
5
4
3
Lock
0
2
1
0
Event
Event
Polarity
Pull-Up
Control
Output
Type
Output
Enable
Name
Reset
Reserved Debounce
Enable
Event Type
0
1
0
0
1
0
0
For GPOS:
Bit
7
0
6
0
5
4
0
3
Lock
0
2
1
0
Pull-Up
Control
Output
Type
Output
Enable
Name
Reset
Reserved
0
1
0
1
For GPIS:
Bit
7
0
6
0
5
0
4
3
0
2
0
1
0
0
0
Name
Reset
Reserved
0
Bit
Description
7
6
Reserved. (For GPOS and GPIS, bits 7-4 and 7-0 are reserved, respectively).
Event Debounce Enable.
0: Disabled
1: Enabled (default)
5
4
3
Event Polarity. This bit defines the polarity of the signal that causes a detection of an event from the
corresponding GPIO pin.
0: Falling edge input (default)
1: Rising edge input
Event Type. This bit defines the signal type that causes a detection of an event from the corresponding GPIO
pin.
0: Edge input (default)
1: Reserved
Lock. This bit locks bits 2-0 of this register. These bits are associated with the GPIO pin currently selected by
the SBGPSEL register. Once this bit is set to 1 by software, it can only be cleared to 0 by VSB power-up reset.
0: No effect (default at VSB power-up reset)
1: Direction, output type, pull-up and output value locked
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3.0 System Wake-Up Control (SWC) (Continued)
Bit
Description
2
Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.
It supports open-drain output signals with internal pull-ups and TTL input signals.
0: Disabled
1: Enabled (default)
1
0
Output Type. This bit controls the output buffer type (open-drain or totem pole) of the corresponding GPIO pin.
0: Open-drain (default)
1: Push-pull
Output Enable. For GPOS, this is a R/O bit. It indicates the GPOS pin output state and is always 1. For GPIOE
and GPIE, this bit indicates the GPIO pin output state. It has no effect on input.
0: TRI-STATE (default for GPIOE/GPIE)
1: Output enabled (default for GPOS)
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.33 Standby GPIOE/GPIE Data Out Register 0 (SB_GPDO0)
This register is set to 3Fh on VPP power-up or software reset only when the Lock bit of the SBGPCFG register is set to 0. It
determines the value to be driven on the GPIOE pins when configured as outputs.
Location:
Type:
Offset 08h
R/W
Bit
7
6
0
5
1
4
1
3
1
2
1
1
1
0
1
Name
Reset
Reserved
Data Out
0
Bit
Description
7-6 Reserved.
5
4
3
2
1
0
Data Out. Bits 5-0 correspond to pins GPIOE5-0 respectively. The value of each bit determines the value driven
on the corresponding GPIOE pin when its output buffer is enabled. Writing to the bit latches the written data
unless the bit is locked by the corresponding GPIOE Configuration Lock bit. Reading the bit returns its value,
regardless of the pin value and configuration.
0: Corresponding pin level low when output enabled
1: Corresponding pin level high (according to buffer type and static pull-up selection) when output enabled
3.4.34 Standby GPIOE/GPIE Data In Register 0 (SB_GPDI0)
This register reflects the values of the GPIE7-6 and GPIOE5-0 pins. Write to this register is ignored.
Location:
Type:
Offset 09h
RO
Bit
7
6
5
4
3
2
1
0
Name
Reset
Data In
X
X
X
X
X
X
X
X
Bit
Description
7
6
5
4
3
2
1
0
Data In. Bits 7-0 correspond to pins GPIE7-6 and GPIOE5-0 respectively. Reading each bit returns the value of
the corresponding GPIE/GPIOE pin regardless of the pin configuration and the SB0_GPDO register value.
0: Corresponding pin level low
1: Corresponding pin level high
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3.0 System Wake-Up Control (SWC) (Continued)
3.4.35 Standby GPOS Data Out Register 1 (SB_GPDO1)
This register is set to 03h on VPP power-up or software reset only when the Lock bit of the SBGPCFG register is set to 0. It
determines the value to be driven on the GPSO0,1 pins.
Location:
Type:
Offset 0Ah
R/W
Bit
7
6
0
5
0
4
0
3
0
2
0
1
1
0
1
Name
Reset
Reserved
Data Out
0
Bit
Description
7-2 Reserved.
1-0 Data Out. Bits 1-0 correspond to pins GPOS1-0 respectively. The value of each bit determines the value driven
on the corresponding GPOS pin when its output buffer is enabled. Writing to the bit latches the written data
unless the bit is locked by the corresponding GPOS Configuration Lock bit. Reading the bit returns its value,
regardless of the pin value and configuration.
0: Corresponding pin level low
1: Corresponding pin level high (according to buffer type and static pull-up selection)
3.4.36 Standby GPIS Data In Register 1 (SB_GPDI1)
This register reflects the values of the GPOS0,1 and GPIS2,3 pins. Write to this register is ignored.
Location:
Type:
Offset 0Bh
RO
Bit
7
6
5
4
3
2
1
0
Name
Reset
Reserved
Data In
X
X
X
X
X
X
X
X
Bit
Description
7-4 Reserved.
3-0 Data In. Reading each bit returns the value of the corresponding GPOS/GPIS pin.
0: Corresponding pin level low
1: Corresponding pin level high
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3.0 System Wake-Up Control (SWC) (Continued)
3.5 SWC REGISTER BITMAP
Table 45. Banks 0 and 1 - The Common Register Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
Module
WK_STS0 IRQ Event
Status
Software
Event
Status
GPIO
Event
Status
CEIR
Event
Status
Mouse
Event
Status
KBD
Event
Status
RI2
Event
Status
RI1
Event
Status
00h
01h
02h
03h
GPIE4/
RING
Event
Status
GPIE7
Event
Status
GPIE6
Event
Status
GPIE5
Event
Status
GPIE3
Event
Status
GPIE2
Event
Status
GPIE1
Event
Status
GPIE0
Event
Status
WK_STS1
Module
WK_EN0 IRQ Event
Enable
Software
Event
Enable
GPIO
Event
Enable
CEIR
Event
Enable
Mouse
Event
Enable
KBD
Event
Enable
RI2
Event
Enable
RI1
Event
Enable
GPIE4/
RING
Event
GPIE7
Event
Enable
GPIE6
Event
Enable
GPIE5
Event
Enable
GPIE3
Event
Enable
GPIE2
Event
Enable
GPIE1
Event
Enable
GPIE0
Event
Enable
WK_EN1
WK_CFG
Enable
Enable
Power But- SwapKBC
ton Pulse
on S3
Configuration Bank
Select
04h
Reserved
Inputs
05h-07h
Reserved
08h SB_GPDO0
09h SB_GPDI0
Reserved
Data Out
Data In
0Ah SB_GPDO1
0Bh SB_GPDI1
0Ch-12h
Reserved
Data Out
Reserved
Data In
Reserved
Table 46. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Configuration and Control Registers Bitmap
Register
Offset Mnemonic
Bits
7
6
5
4
3
2
1
0
Disable
Parity
13h
PS2CTL
Mouse Wake-Up Configuration
Keyboard Data
Keyboard Wake-Up Configuration
16h
17h
KDSR
MDSR
Reserved
Mouse Data
PS2KEY0-
PS2KEY7
18h-1Fh
Scan Code of Keys 0-7
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3.0 System Wake-Up Control (SWC) (Continued)
Table 47. Bank 1 - CEIR Wake-Up Configuration and Control Registers Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
Select
IRRX2
Input
Invert
IRRXn
Input
CEIR
Enable
13h
IRWCR
Reserved
CEIR Protocol Select
Reserved
Reserved
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
IRWAD
IRWAM
CEIR Wake-Up Address
CEIR Wake-Up Address Mask
CEIR Address
ADSR
IRWTR0L
IRWTR0H
IRWTR1L
IRWTR1H
IRWTR2L
IRWTR2H
IRWTR3L
IRWTR3H
Reserved
Reserved
Reserved
Reserved
CEIR Pulse Change, Range 0, Low Limit
CEIR Pulse Change, Range 0, High Limit
CEIR Pulse Change, Range 1, Low Limit
CEIR Pulse Change, Range 1, High Limit
CEIR Pulse Change, Range 2, Low Limit
CEIR Pulse Change, Range 2, High Limit
CEIR Pulse Change, Range 3, Low Limit
CEIR Pulse Change, Range 3, High Limit
Table 48. Bank 2 - Event Routing Control Registers Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
Software
Event to
SMI Enable
CEIR
Event to
Mouse
Event to
KBD
Event to
RI2
Event to
RI1
Event to
13h WK_SMIEN0 Reserved
Reserved
SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable
GPIE4/
RING
Event to
SMI Enable
GPIE7
GPIE6
Event to
GPIE5
Event to
GPIE3
Event to
GPIE2
Event to
GPIE1
Event to
GPIE0
Event to
14h WK_SMIEN1 Event to
SMI Enable SMI Enable SMI Enable
SMI Enable SMI Enable SMI Enable SMI Enable
Software
Event to
CEIR
Event to
Mouse
Event to
KBD
Event to
RI2
Event to
RI1
Event to
15h WK_IRQEN0 Reserved
Reserved
IRQ Enable
IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable
GPIE4/
RING
Event to
IRQ Enable
GPIE7
GPIE6
Event to
GPIE5
Event to
GPIE3
Event to
GPIE2
Event to
GPIE1
Event to
GPIE0
Event to
16h WK_IRQEN1 Event to
IRQ Enable IRQ Enable IRQ Enable
IRQ Enable IRQ Enable IRQ Enable IRQ Enable
CEIR
Mouse
KBD
RI2
RI1
17h
18h
19h
WK_X1EN0
Reserved Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1
Enable
Enable
Enable
Enable
Enable
GPIE4/
RING
Event Ex. 1
Enable
GPIE7
GPIE6
GPIE5
GPIE3
GPIE2
GPIE1
GPIE0
WK_X1EN1 Event Ex. 1 Event Ex. 1 Event Ex. 1
Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
CEIR
Mouse
KBD
RI2
RI1
WK_X2EN0
Reserved
Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2
Enable Enable Enable Enable Enable
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3.0 System Wake-Up Control (SWC) (Continued)
GPIE4/
RING
Event Ex. 2
Enable
GPIE7
GPIE6
GPIE5
GPIE3
GPIE2
GPIE1
GPIE0
1Ah WK_X2EN1 Event Ex. 2 Event Ex. 2 Event Ex. 2
Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2
Enable
Enable
Reserved
GPIE6
Enable
Enable
Mouse
Enable
Enable
Enable
CEIR
KBD
RI2
RI1
1Bh WK_X3EN0
Event Ex. Event Ex. Event Ex. 3 Event Ex. 3 Event Ex. 3
3 Enable
3 Enable
Enable
Enable
Enable
GPIE4/
RING
Event Ex. 3
Enable
GPIE7
GPIE5
GPIE3
GPIE2
GPIE1
GPIE0
1Ch WK_X3EN1 Event Ex. 3 Event Ex. 3 Event Ex. 3
Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1Dh-
1Fh
Reserved
Table 49. Bank 3 - Standby General-Purpose I/O Configuration Registers Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
Port
Select
13h
14h
SBGPSEL
Reserved
Event
Reserved
Pin Select
Event
Polarity
Event
Type
Pull-Up
Control
Output
Type
Output
Enable
SBGPCFG Reserved Debounce
Enable
Lock
15h-
1Fh
Reserved
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4.0 Fan Speed Control
4.1 OVERVIEW
This chapter describes a generic Fan Speed Control module. For the implementation used in this device, see the Device
Architecture and Configuration chapter.
The Fan Speed Control is a programmable Pulse Width Modulation (PWM) generator. The PWM generator output is used
to control the fan’s power voltage, which is correlated to the fan’s speed. Converting a 0 to 100% duty cycle PWM signal to
an analog voltage range is achieved by an external circuit, as shown in Figure 13. Some newer fans accept direct PWM
input without any external circuitry. When an overtemperature condition is detected, the Fan speed Control forces the fan to
turn on at 100% duty cycle.
Control
FANOUT
Fan Speed
Control
External
Circuitry
Fan
Figure 13. Fan Speed Control - System Configuration
4.2 FUNCTIONAL DESCRIPTION
The PWM generator operation is based on a PWM counter and two registers: the Fan Speed Control Pre-Scale register
(FCPSR), used to determine the overall cycle time (or the frequency) of the FANOUT output, and the Fan Speed Control
Duty Cycle register (FCDCR), used to determine the duty cycle of the FANOUT between 0 to 100%.
The PWM counter is an 8-bit, free-running counter that runs continuously in a cyclic manner, i.e., its cycle equals 256 clock
periods. The PWM output is high, as long as the count is lower than the FCDCR value and it flips to low as the counter ex-
ceeds that value. The duty cycle (expressed as a percentage) is therefore (FCDCR/256)*100. In particular, the PWM output
is continuously low when FCDCR=0 and continuously high when FCDCR=FFh. The FANOUT output may be inverted by an
external configuration bit, in which case the FANOUT duty cycle is ([256-FCDCR]/256)*100.
The PWM counter clock is generated by dividing the input clock (either 24 MHz or 200 KHz), using a clock divider. The di-
vision factor, which must be between 1 and 124, is defined as Pre-Scale Value+1, where Pre-Scale is the binary value stored
in bits 6 to 0 of the FCPSR register. The resulting PWM output frequency is therefore:
(24 MHz or 200 kHz/([Pre-Scale Value+1]*256).
The default selection of 24 MHz input clock allows a programmable FANOUT frequency in the range of 756 Hz to 93.75 KHz.
For lower frequencies, selecting the 200 KHz input clock allows a frequency range of 6 Hz to 781 Hz (see Figure 14).
The FANOUT frequency must be pre-selected according to the fan type’s specific requirements prior to enabling the Fan
Speed Control. The only run-time change that is required to dynamically control the fan speed is the value of the FCDCR
register.
Warning! The contents of the FCPSR register must not be changed when the Fan Speed Control is enabled.
Enable Fans on OTS Detection When the respective Fan i Enable on OTS (bits 2-0) of the Fan Speed Control OTS Con-
figuration register is set (see Section 2.17.5 on page 76), the fan is forced to 100% duty cycle when any of the temperature
measurement channels flags an overtemperature condition. This occurs regardless of the setting of the FCDCR register in
order to help protect the system from overheating.
24 MHz
0
1
Clock
PWM
Counter
Divider
Invert
FANOUT
(1-124)
200 KHz
PWM Output -
FCDCR > Counter
Comparator
0
1
FANOUT
Bits 6-0
Bit 7
O
FCPSR Register
FCDCR Register
Figure 14. PWM Generator (FANOUT)
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4.0 Fan Speed Control (Continued)
4.3 FAN SPEED CONTROL REGISTERS
The following abbreviations are used to indicate the Register Type:
• R/W = Read/Write.
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write.
• RO = Read Only.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
4.3.1
Fan Speed Control Register Map
Offset
Mnemonic
Register Name
Type
R/W
R/W
Section
4.3.2
Device specific1
Device specific1
FCPSR Fan Speed Control Pre-Scale
FCDCR Fan Speed Control Duty Cycle
4.3.3
1. The location of this register is defined in the Device Architecture and Configuration chapter.
4.3.2
Fan Speed Control Pre-Scale Register (FCPSR)
Location:
Type:
Device specific
R/W
Bit
7
6
0
5
0
4
0
3
2
0
1
0
0
0
Clock
Select
Name
Reset
Pre-Scale Value
0
0
Bit
Description
7
Clock Select. This bit selects the input clock for the clock divider.
0: 24 MHz
1: 200 KHz
6-0 Pre-Scale Value. The clock divider for the input clock (24 MHz or 200 KHz) is Pre-Scale Value + 1. Writing
0000000b to these bits transfers the input clock directly to the counter. The maximum clock divider is 124 (7Bh
+1). These bits must not be programmed with the values 7Ch, 7Dh, 7Eh and 7Fh as this may produce
unpredictable results.
The contents of this register should not be changed when the corresponding Fan Speed Control Enable bit of
the Fan Speed Control Configuration register is 1 (see Device Architecture and Configuration chapter) as this
may produce unpredictable results.
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4.0 Fan Speed Control (Continued)
4.3.3
Fan Speed Control Duty Cycle Register (FCDCR)
Location:
Type:
Device specific
R/W
Bit
7
6
1
5
1
4
3
2
1
1
1
0
1
Name
Duty Cycle Value
Reset
1
1
1
Bit
Description
7-0 Duty Cycle. The binary value of this 8-bit field determines the number of clock cycles out of a 256-cycle period,
during which the PWM output is high (while FANOUT is either equal to or the inverse of the PWM output,
depending on the Inverse FANOUT configuration bit).
00h: PWM output is continuously low
01h - FEh: PWM output is high for [Duty Cycle Value] clock cycles and low for [256-Duty Cycle Value] clock
cycles
FFh: PWM output is continuously high
4.4 FAN SPEED CONTROL BITMAP
Register
Bits
Offset
Mnemonic
FCPSR
7
6
5
4
3
2
1
0
Device
specific1
Clock
Select
Pre-Scale Value
Device
FCDCR
Duty Cycle Value
1
specific
1. The location of this register is defined in the Device Architecture and Configuration chapter.
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5.0 Fan Speed Monitor
5.1 OVERVIEW
This chapter describes a generic Fan Speed Monitor module. For the implementation used in this device, see the Device
Architecture and Configuration chapter.
The Fan Speed Monitor determines the fan’s speed by measuring the time between consecutive tachometer pulses emitted
by the fan once or twice per revolution (depending on the fan type). It may provide the system with a current speed reading
and/or alert the system, by interrupt, whenever the speed drops below a programmable threshold. The Fan Speed Monitor
indicates whether the speed is just below the threshold or inefficiently low to consider the fan stopped.
Figure 15 shows the basic system configuration of the Fan Speed Monitor.
Fan
Filtering
Circuitry
(optional)
FANIN
Tachometer Pulse
Fan Speed
Monitor
Figure 15. Fan Speed Monitor - System Configuration
5.2 FUNCTIONAL DESCRIPTION
The fan emits a tachometer pulse every half or full revolution (depending on the fan type). These pulses are fed into the Fan
Speed Monitor through the FANIN input pin. Measuring the time between these pulses is the basis for speed monitoring.
NCBTP is defined as the Number of Clock-cycles Between consecutive Tachometer Pulses. For a known clock rate (f Hz)
and number of pulses per revolution (n=1,2), the Fan Speed is calculated according to the following relationship:
f
------------------------------
Fan Speed (in RPM) = 60 •
NCBTP • n
The Fan Speed Monitor consists of an 8-bit counter to measure the NCBTP and three 8-bit registers: Fan Monitor Speed
register (FMSPR), Fan Monitor Threshold register (FMTHR) and Fan Monitor Control and Status register (FMCSR). Figure
16 is a general block diagram of the Fan Speed Monitor.
The Up Counter and the FMSPR register are cleared to 0 while the Fan Speed Monitor is disabled (and in particular upon
system reset).
When the Fan Speed Monitor is enabled and there is no counter overflow, the counter runs (up-counts), clocked by the se-
lected clock rate. Starting from the second FANIN pulse (after activation) and upon every rising edge of FANIN when the
Over Threshold bit is 0, the FMSPR register is loaded with the contents of the counter, the counter is cleared to 0 and the
Speed Ready bit is set to 1.
Upon reading FMSPR, the Speed Ready bit of the FMCSR is cleared to 0.
The above operation continually repeats itself, providing the host with the current speed reading, as long as the FMSPR
register value is lower than the threshold.
Once the loaded FMSPR register value exceeds the threshold, the Over Threshold bit is set to 1. Interrupt is asserted if
enabled. The FMSPR register is not loaded with any new values when the Over Threshold bit is set. A new value is loaded
only after clearing the Over Threshold bit (by writing 1) and reading the FMSPR register. This guarantees that the same
NCBTP value that generated the interrupt remains available for the interrupt handler.
If the counter passes FFh, the Overflow bit is set to 1, the FMSPR register is cleared and the interrupt is asserted, if enabled.
The Overflow bit is cleared to 0 when it is written with 1, after which speed measurement resumes.
The input buffer of the FANIN signal is a hysteresis buffer (Schmitt trigger). This signal passes through a digital filter when
the Filter Disable bit (bit 4 of the FMCSR register) is 0. The digital filter uses a 32 KHz clock to filter out any pulses shorter
than 750 µsec. This filter can be by-passed when setting bit 4 of the FMCSR register to 1.
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5.0 Fan Speed Monitor (Continued)
.
Speed Ready
(FMCSR, Bit 0)
Set
16 Khz
8 Khz
4 Khz
2 Khz
Clock
Clear
Up Counter
Overflow
(FMCSR, Bit 2)
FMSPR Register
Comparator
Clock Select
(FMCSR, Bits 6-5)
Load
Over
Interrupt
Threshold
(FMCSR, Bit 1)
Filter
Pos. Edge
Detector
Interrupt Enable
(FMCSR, Bit 3)
FANIN
FMTHR Register
Filter Disable
(FMCSR, Bit 4)
Figure 16. Fan Speed Monitor
5.3 FAN SPEED MONITOR REGISTERS
The FMSPR register is used to hold the current speed reading (which is represented by the latest NCBTP and refreshed
upon every FANIN pulse).
The FMTHR register holds the maximum allowed NCBTP value (representing the slowest speed at which the fan is allowed
to operate) without causing system alert.
Additional control and status bits are available through the FMCSR register. These include:
• Over Threshold. A status bit that indicates that the NCBTP has exceeded the threshold (the speed has dropped below
the allowed minimum).
• Overflow. A status bit that indicates that the NCBTP is higher than FFh. With a proper input clock selection, this means
that the speed is inefficiently low and is considered stopped.
• Speed Ready. A status bit that indicates that new, valid data has been loaded into the FMSPR register.
• Clock Select. A 2-bit control field that selects the counter clock rate as either 2 KHz, 4 KHz, 8 KHz or 16 KHz.
The following abbreviations are used to indicate the Register Type:
• R/W = Read/Write.
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write.
• RO = Read Only.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
5.3.1
Fan Speed Monitor Register Map
Offset
Mnemonic
Register Name
Type
R/W
Section
5.3.2
Device specific1
Device specific1
Device specific1
FMTHR Fan Monitor Threshold
FMSPR Fan Monitor Speed
RO
5.3.3
FMCSR Fan Monitor Control and Status
Varies per bit
5.3.4
1. The location of this register is defined in the Device Architecture and Configuration chapter.
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5.0 Fan Speed Monitor (Continued)
5.3.2
Fan Monitor Threshold Register (FMTHR)
This 8-bit register contains the programmable threshold for the fan. This threshold is the maximum number of clock cycles
between consecutive tachometer pulses (frequencies of 16, 8, 4 or 2 KHz). It represents the minimum fan speed permitted
in the system. If the period between consecutive tachometer pulses is greater than the threshold, an interrupt (if enabled) is
issued. After reset, the value of FMTHR is FFh.
This register should not be changed when the corresponding Fan Monitor Enable bit is set to 1 (enabled), since this may
cause unpredictable results.
Location:
Type:
Device specific
R/W
Bit
7
6
1
5
1
4
3
2
1
1
1
0
1
Name
Reset
Threshold Value
1
1
1
5.3.3
Fan Monitor Speed Register (FMSPR)
This read-only 8-bit register holds the speed reading, represented by number of clock cycles between consecutive tachom-
eter pulses. For details, refer to Section 5.2. When the Speed Ready bit of the FMCSR register is 1, FMSPR holds valid data
that has not yet been read.
It is cleared to 00h upon any of the following conditions:
●
System reset.
●
Fan Monitor Enable bit is set to 0.
●
Overflow bit is set to 1.
Location:
Type:
Device specific
RO
Bit
7
6
0
5
0
4
3
2
0
1
0
0
0
Name
Reset
Fan Speed Reading
0
0
0
5.3.4
Fan Monitor Control and Status Register (FMCSR)
Location:
Type:
Device specific
Varies per bit
Bit
7
Reserved
0
6
5
1
4
3
2
Overflow
0
1
0
Filter
Disable
Interrupt
Enable
Over
Threshold
Speed
Ready
Name
Reset
Clock Select
0
0
0
0
0
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5.0 Fan Speed Monitor (Continued)
Bit
Type
Description
7
Reserved
6-5
R/W Clock Select. Selects the clock source provided to the counter.
These bits must not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled).
00: 16 KHz
01: 8 KHz (default)
10: 4 KHz
11: 2 KHz
4
R/W Filter Disable. When this bit is set to 1, the digital filter is disabled. When it is cleared, the filter is
enabled. This bit should not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled)
to avoid unpredictable results.
0: Digital filter enabled (default)
1: Digital filter disabled
3
2
R/W Interrupt Enable. This bit controls the assertion of overflow interrupt and Over Threshold interrupt.
0: Interrupt disabled (default)
1: Interrupt enabled. Interrupt is asserted when an Over Threshold bit, Overflow bit or both are set to 1.
R/W1C Overflow. Indicates that the counter has passed FFh and the fan speed is inefficiently slow; i.e., slower
than 60 f/(256 n). Writing 1 to this bit clears it to 0.
0: No overflow occurred since the last time this bit was cleared (by reset or by writing 1)
1: Counter passed FFh
1
0
R/W1C Over Threshold. Indicates that the value loaded into the FMSPR register upon detection of the rising
edge of the FANIN pulse exceeded the threshold value.
0: FMSPR register value did not exceed the threshold since the last time this bit was cleared (by reset
or by writing 1)
1: FMSPR register value exceeded the threshold
RO Speed Ready. This bit indicates that the speed register holds new (not yet read) and valid data. It is set
to 1 on each rising edge of the FANIN input (starting from the second one) if the Over Threshold bit is
0. It is cleared to 0 whenever the speed register is read or when the Overflow bit is set.
0: No new valid data in the FMSPR register (data is either invalid or has already been read)
1: FMSPR register loaded with new and valid data
5.4 FAN SPEED MONITOR BITMAP
Register
Bits
Offset
Mnemonic
FMTHR
7
6
5
4
3
2
1
0
Device
specific1
Threshold Value
Device
FMSPR
FMCSR
Fan Speed Reading
specific1
Device
specific1
Filter
Interrupt
Enable
Over
Threshold
Speed
Ready
Reserved
Clock Select
Overflow
Disable
1. The location of this register is defined in the Device Architecture and Configuration chapter.
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6.0 General-Purpose Input/Output (GPIO) Port
This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations.
For the device specific implementation, see the Device Architecture and Configuration chapter.
6.1 OVERVIEW
The GPIO port is an 8-bit port, which is based on eight pins. It features:
●
Software capability to manipulate and read pin levels.
●
Controllable system notification by several means based on the pin level or level transition.
●
Ability to capture and manipulate events and their associated status.
●
Back-drive protected pins.
GPIO port operation is associated with two sets of registers:
●
Pin Configuration registers, mapped in the Device Configuration space. These registers are used to statically set up
the logical behavior of each pin. There are two 8-bit register for each GPIO pin.
●
Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and
GPIO Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by
the base address registers in the GPIO Device Configuration). They are used to manipulate and/or read the pin val-
ues and to control and handle system notification. Each runtime register corresponds to the 8-pin port, such that bit
‘n’ in each one of the four registers is associated with GPIOXn pin, where ‘X’ is the port number.
Each GPIO pin is associated with ten configuration bits and the corresponding bit slice of the four runtime registers, as
shown in Figure 17.
The functionality of the GPIO port is divided into basic functionality (which includes the manipulation and reading of the GPIO
pins) and enhanced functionality (which includes event detection and system notification). Basic functionality is described in
Section 6.2. Enhanced functionality is described in Section 6.3.
Bit n
GPDOX
GPIOX Base Address
GPDIX
Runtime
8 GPCFG
Registers
GPEVENX
GPEVSTX
Registers
X = port number
n = pin number, 0 to 7
GPIO Pin
Configuration (GPCFG)
Register
GPIOXn
Pin
GPIOXn CNFG
GPIOXn
Port Logic
x8
Port and Pin
Select
GPIO Pin
Select (GPSEL)
Register
x8
8 GPEVR
Registers
Event
Pending
Indicator
Interrupt
Request
Event
Routing
Control
SMI
x8
PWUREQ
GPIO Pin Event
Routing (GPEVR)
Register
GPIOXn ROUTE
Figure 17. GPIO Port Architecture
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6.0 General-Purpose Input/Output (GPIO) Port (Continued)
6.2 BASIC FUNCTIONALITY
The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and
GPDI. The configuration and operation of a single pin GPIOXn (pin n in port X) is shown in Figure 18.
GPIO Device
Enable
Read Only
Data In
Static
Pull-Up
Push-Pull =1
Pin
Read/Write
Data Out
Internal
Bus
Pull-Up
Enable
Output
Enable
Output
Type
Pull-Up
Control
Lock
Bit 3
Bit 2
Bit 1
Bit 0
GPIO Pin Configuration (GPCFG) Register
Figure 18. GPIO Basic Functionality
6.2.1
Configuration Options
The GPCFG register controls the following basic configuration options:
• Port Direction - Controlled by the Output Enable bit (bit 0).
• Output Type - Push-pull vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the pull-up
portion of the output buffer.
• Weak Static Pull-up - May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control
(bit 2).
• Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The
lock is controlled by Lock (bit 3). It disables writes to the GPDO register bits and to bits 0-3 of the GPCFG register (In-
cluding the Lock bit itself). Once locked, it can be released by hardware reset only.
6.2.2
Operation
The value that is written to the GPDO register is driven to the pin if the output is enabled. Reading from the GPDO register
returns its contents regardless of the pin value or the port configuration. The GPDI register is a read-only register. Reading
from the GPDI register returns the pin value regardless of what is driving it (the port itself, configured as an output port, or
the external device when the port is configured as an input port). Writing to this register is ignored.
Activation of the GPIO port is controlled by external device specific configuration bit (or a combination of bits). When the port
is inactive, access to GPDI and GPDO registers is disabled and the inputs are blocked. However, there is no change in the
port configuration and in the GPDO value and hence there is no effect on the outputs of the pins.
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6.0 General-Purpose Input/Output (GPIO) Port (Continued)
6.3 EVENT HANDLING AND SYSTEM NOTIFICATION
The enhanced GPIO port supports system notification based on event detection. This functionality is based on six configu-
ration bits and a bit slice of runtime registers GPEVEN and GPEVST. The configuration and operation of the event detection
capability is shown in Figure 19. The operation of system notification is illustrated in Figure 20.
1
Event
Pending
Indicator
0
R/W
Event
Enable
0
1
Rising
Edge
Detector
R/W 1 to Clear
Input
Status
Debouncer
Detected
Pin
Enabled Events
from other
GPIO Pins
Rising Edge or
High Level =1
Level =1
Internal
Bus
Event
Event Type
Debounce
Event Polarity
Bit 5
Enable
Bit 6
Bit 4
GPIO Pin Configuration Register
Figure 19. Event Detection
6.3.1
Event Configuration
Each pin in the GPIO port is a potential input event source. The event detection can trigger a system notification upon pre-
determined behavior of the source pin. The GPCFG register determines the event detection trigger type for the system no-
tification.
Event Type and Polarity
Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin tran-
sition either from high to low or low to high. A level event may be detected when the source pin is in active level. The trigger
type is determined by Event Type (bit 4 of the GPCFG register). The direction of the transition (for edge) or the polarity of
the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG register).
Event Debounce Enable
The input signal can be debounced for about 15 msec before entering the detector. To ensure that the signal is stable, the
signal state is transferred to the detector only after a debouncing period, during which the signal has no transitions. The
debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. Therefore, when working
with a level event and system notification by either SMI or IRQ, it is recommended to disable the debounce if the delay in
the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG
register).
6.3.2
System Notification
System notification on GPIO-triggered events is by means of assertion of one or more of the following output pins:
●
Interrupt Request (via the device’s Bus Interface).
●
System Management Interrupt (SMI, via the device’s Bus Interface).
●
Power-Up Request (PWUREQ, via the System Wake-Up Control).
The system notification for each GPIO pin is controlled by the corresponding bits in the GPEVEN and GPEVR registers.
System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1. The corresponding
bits in the GPEVR register select which means of system notification the detected event is routed to. The event routing
mechanism is described in Figure 20.
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6.0 General-Purpose Input/Output (GPIO) Port (Continued)
Event Pending Indicator
PWUREQ
SMI
Event
Routing
Logic
IRQ
Enable
SMI
Routing
Enable
IRQ
Routing
Enable
PWUREQ
Routed Events
from other GPIO Pins
Routing
Bit 2
Bit 1
Bit 0
GPIO Pin Event Routing Register
Figure 20. GPIO Event Routing Mechanism
The GPEVST register is a general-purpose edge detector that may be used to reflect the event source pending status for
edge-triggered events.
The term active edge refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for
falling edge). Active level refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level).
The corresponding bit of the GPEVST register is set by hardware whenever an active edge is detected regardless of any
other bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.
A GPIO pin is in event pending state if the corresponding bit of the GPEVEN register is set and either:
●
The Event Type is level and the pin is in active level, or
●
The Event Type is edge and the corresponding bit of the GPEVST register is set.
The target means of system notification is asserted if at least one GPIO pin is in event pending state.
The selection of the target means of system notification is determined by the GPEVR register. If IRQ is selected as one of the
means for the system notification, the specific IRQ line is determined by the IRQ selection procedure of the device configura-
tion. The assertion of any means of system notification is blocked when the GPIO functional block is deactivated.
If the output of a GPIO pin is enabled, it may be put in event pending state by the software when writing to the GPDO register.
A pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source may not
be released by software (except for disabling the source) as long as the pin is in active level. When level event is used, it is
recommended to disable the input debouncer.
Upon deactivation of the GPIO port, the GPEVST register is cleared and access to both the GPEVST and GPEVEN registers
is disabled. All system notification means including the target IRQ line are detached from the GPIO and de-asserted.
Before enabling any system notification, it is recommended to set the desired event configuration and then verify that the
status registers are cleared.
6.4 GPIO PORT REGISTERS
The register maps in this chapter use the following abbreviations for Type:
●
R/W = Read/Write.
●
R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
●
W = Write.
●
RO = Read Only.
●
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
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6.0 General-Purpose Input/Output (GPIO) Port (Continued)
6.4.1
GPIO Pin Configuration (GPCFG) Register
This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is
mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register, which functions as an index
register and the specific GPCFG register, which reflects the configuration of the currently selected pin. For details on the
GPSEL register, refer to the Device Architecture and Configuration chapter.
Bits 4-6 are applicable only for the enhanced GPIO port with event detection support. In the basic port, these bits are re-
served, return 0 on read and have no effect on port functionality.
Location:
Type:
Device specific
R/W (bit 3 is set only)
Bit
7
6
5
4
3
Lock
0
2
1
0
Event De-
Event Po-
larity
Pull-Up
Control
Output
Type
Output En-
able
Name
Reset
Reserved bounce En-
able
Event Type
0
1
0
0
1
0
0
Bit
Description
7
6
Reserved.
Event Debounce Enable.
0: Disabled
1: Enabled (default)
5
4
3
Event Polarity. This bit defines the polarity of the signal that causes a detection of an event from the
corresponding GPIO pin (falling/low or rising/high).
0: Falling edge or low-level input (default)
1: Rising edge or high-level input
Event Type. This bit defines the signal type that causes a detection of an event from the corresponding GPIO
pin.
0: Edge input (default)
1: Level input
Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to
0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1. (Refer to the
Device Architecture and Configuration chapter.)
0: No effect (default)
1: Direction, output type, pull-up and output value locked
2
Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.
It supports open-drain output signals with internal pull-ups and TTL input signals.
0: Disabled
1: Enabled (default)
1
0
Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.
0: Open-drain (default)
1: Push-pull
Output Enable. This bit indicates the GPIO pin output state. It has no effect on input.
0: TRI-STATE (default)
1: Output enabled
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6.0 General-Purpose Input/Output (GPIO) Port (Continued)
6.4.2
GPIO Pin Event Routing (GPEVR) Register
This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is
mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register, which functions as an index
register and the specific GPER register, which reflects the routing configuration of the currently selected pin. For details on
the GPSEL register, refer to the Device Architecture and Configuration chapter.
This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port, this register
set is reserved, returns 0 on read and has no effect on port functionality.
Location:
Type:
Device specific
R/W
Bit
7
0
6
0
5
Reserved
0
4
3
0
2
1
0
GPIO Event GPIO Event GPIO Event
toPWUREQ to SMI En- to IRQ En-
Name
Reset
Enable
able
able
0
0
0
1
Bit
Description
7-3 Reserved.
2
1
0
GPIO Event to PWUREQ Enable. This bit is used to enable/disable the routing of the corresponding GPIO
detected event to PWUREQ.
0: Disabled (default)
1: Enabled
GPIO Event to SMI Enable. This bit is used to enable/disable the routing of the corresponding GIO detected
event to SMI.
0: Disabled (default)
1: Enabled
GPIO Event to IRQ Enable. This bit is used to enable/disable the routing of the corresponding GPIO detected
event to IRQ.
0: Disabled
1: Enabled (default)
6.4.3
GPIO Port Runtime Register Map
Offset
Mnemonic
GPDO
Register Name
GPIO Data Out
Type
R/W
Section
6.4.4
Device specific1
Device specific1
Device specific1
Device specific1
GPDI
GPIO Data In
RO
6.4.5
GPEVEN
GPEVST
GPIO Event Enable
GPIO Event Status
R/W
6.4.6
R/W1C
6.4.7
1. The location of this register is defined in the Device Architecture and Configuration
chapter in Section 2.15.1.
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6.0 General-Purpose Input/Output (GPIO) Port (Continued)
6.4.4
GPIO Data Out Register (GPDO)
Location:
Type:
Device specific
R/W
Bit
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Name
Reset
Data Out
1
Bit
Description
7
6
Data Out. Bits 7-0 correspond to pins 7-0, respectively. The value of each bit determines the value driven on
the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless
the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value regardless of the pin value
and configuration.
5
4
3
2
1
0
0: Corresponding pin driven to low when output enabled
1: Corresponding pin driven or released to high (according to buffer type and static pull-up selection) when
output enabled
6.4.5
GPIO Data In Register (GPDI)
Location:
Type:
Device specific
RO
Bit
7
6
5
4
3
2
1
0
Name
Reset
Data In
X
X
X
X
X
X
X
X
Bit
Description
7
6
5
Data In. Bits 7-0 correspond to pins 7-0, respectively. Reading each bit returns the value of the corresponding
GPIO pin regardless of the pin configuration and the GPDO register value. Write is ignored.
4
3
2
1
0
0: Corresponding pin level low
1: Corresponding pin level high
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6.0 General-Purpose Input/Output (GPIO) Port (Continued)
6.4.6
GPIO Event Enable Register (GPEVEN)
Location:
Type:
Device specific
R/W
Bit
7
6
0
5
0
4
3
2
0
1
0
0
0
Name
Reset
Event Enable
0
0
0
Bit
Description
7
6
5
Event Enable. Bits 7-0 correspond to pins 7-0, respectively. Each bit enables system notification triggering by
the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPEVST register.
4
3
2
1
0
0: IRQ generation by corresponding GPIO pin masked
1: IRQ generation by corresponding GPIO pin enabled
6.4.7
GPIO Event Status Register (GPEVST)
Location:
Type:
Device specific
R/W1C
Bit
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Name
Reset
Status
0
Bit
Description
7
6
Status. Bits 7-0 correspond to pins 7-0, respectively. Each bit is an edge detector that is set to 1 by the
hardware upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding
GPIO pin. This edge detection is independent of the Event Type or the Event Enable bit in the GPEVEN register.
However, the bit may reflect the event status for enabled, edge-trigger event sources. Writing 1 to the Status bit
clears it to 0.
5
4
3
2
1
0
0: No active edge detected since last cleared
1: Active edge detected
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7.0 WATCHDOG Timer (WDT)
7.1 OVERVIEW
The WATCHDOG Timer prompts the system via SMI or interrupt when no system activity is detected on a predefined selec-
tion of system events for a predefined period of time of between 1 and 255 minutes or seconds. The numeric value (1-255)
is configured in the WDTO register (WDTO); the time unit used for counting down (minutes or seconds) is configured in the
Status register (WDST).
The WATCHDOG Timer monitors four maskable system events: the interrupt request lines of the Keyboard, Mouse and the
two serial ports (UART1 and UART2). The system prompt is performed by asserting a special-purpose output pin (WDO),
which can be attached to external SMI. Alternatively, this indication can be routed to any arbitrary IRQ line and is also avail-
able on a status bit that can be read by the host.
This chapter describes the generic WATCHDOG Timer functional block. A device may include a different implementation.
For device specific implementation, see the Device Architecture and Configuration chapter.
7.2 FUNCTIONAL DESCRIPTION
This section describes how the WATCHDOG Timer works. By default, the WATCHDOG Timer counts down in minutes. To
change the time unit from minutes to seconds, reconfigure the WDST register as defined in Section 7.4 on page 140.
The WATCHDOG Timer consists of an 8-bit counter and three registers: Timeout register (WDTO), Mask register (WDMSK)
and Status register (WDST). The counter is an 8-bit down counter that is clocked every minute or second and is used for
the timeout period countdown. The WDTO register holds the programmable timeout, which is the period of inactivity after
which the WATCHDOG Timer prompts the system (1 to 255 minutes or seconds). The WDMSK register determines which
system events are enabled as WATCHDOG Timer trigger events to restart the countdown. The WDST register holds the
WATCHDOG Timer status bit that reflects the value of the WDO pin and indicates that the timeout period has expired. In
addition, it sets the time unit (minutes or seconds). Figure 21 shows the functionality of the WATCHDOG Timer.
Enable Bits
1 Minute/Second Clock
Data Bus
Write
Register
3 2 1 0
WDMSK
WDTO Register
Keyboard IRQ
Load
Reload
Mouse IRQ
Timer
Serial Port 1 IRQ
Zero Detector
Interrupt
WDO
Serial Port 2 IRQ
Status Bit
Figure 21. WATCHDOG Timer Functional Diagram
Upon reset, the Timeout register (WDTO) is initialized to zero, the timer is deactivated, the WDO is inactive (high) and all
trigger events are masked.
Upon writing to the WDTO register, the timer is activated while the counter is loaded with the timeout value and starts count-
ing down every minute or second. If a trigger event (unmasked system event) occurs before the counter has expired
(reached zero), the counter is reloaded with the timeout period (from WDTO register) and restarts the countdown. If no trig-
ger event occurs before the timeout period expires, the counter reaches zero and stops counting. Consequently, the WDO
pin is asserted (pulled low) and the WDO Status bit is cleared to 0.
Writing to the WDTO register de-asserts the WDO output (released high) and sets the WDO Status bit to 1. If a non-zero
value is written, a new countdown starts as described above. If 00h is written, the timer is deactivated.
To summarize, the WDO output is de-asserted (high) and the Status bit is set to 1 (inactive) upon:
●
Reset, or
●
Activating the WATCHDOG Timer or
●
Writing to the WDTO register.
The WDO output is asserted (low) and the WDO status is set to zero (active) when the counter reaches zero.
When an IRQ is assigned to the WATCHDOG Timer (through the WATCHDOG Timer device configuration), the selected
IRQ level is active as long as the WDO status bit is low (active).
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7.0 WATCHDOG Timer (WDT) (Continued)
7.3 WATCHDOG TIMER REGISTERS
The WATCHDOG Timer registers, at offsets 00h-02h relative to the WATCHDOG base address, are shown in the following
register map. The base address is defined by designated registers in the WATCHDOG Timer device configuration register
set.
The following abbreviations are used to indicate the Register Type:
• R/W = Read/Write.
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write.
• RO = Read Only,
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
7.3.1
WATCHDOG Timer Register Map
Offset Mnemonic
Register Name
Type
Section
00h
01h
02h
03h
WDTO
WDMSK
WDST
WATCHDOG Timeout
WATCHDOG Mask
WATCHDOG Status
Reserved
R/W
R/W
RO
7.3.2
7.3.3
7.3.4
7.3.2
WATCHDOG Timeout Register (WDTO)
This register holds the programmable timeout period, which is between 1 and 255 minutes or seconds. Writing to this register
de-asserts the WDO output and sets the WDO status bit to 1 (inactive). Additionally, writing to this register is interpreted as
a command for starting or stopping the WATCHDOG Timer, according to the data written. If a non-zero value is written, the
timer is activated (countdown starts). If a non-zero value is written when the counter is running, the timer is immediately
reloaded with the new value and starts counting down from the new value. If 00h is written, the timer and its outputs are de-
activated.
Location:
Type:
Offset 00h
R/W
Bit
7
6
0
5
0
4
3
2
0
1
0
0
0
Name
Reset
Programmed Timeout Period
0
0
0
Bit
Description
7-0 Programmed Timeout Period. These bits hold the binary value of the timeout period in minutes or seconds (1
to 255). A value of 00h halts the counter and forces the outputs to inactive levels. A device reset clears the
register to 00h.
00h: Timer and WDO outputs inactive
01h-FFh: Programmed timeout period (in minutes or seconds)
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7.0 WATCHDOG Timer (WDT) (Continued)
7.3.3
WATCHDOG Mask Register (WDMSK)
This register is used to determine which system events (IRQ) are enabled as WATCHDOG Timer trigger events. An enabled
IRQ event becomes a trigger event that causes the timer to reload the WDTO and restart the countdown.
This register enables or masks the trigger events that restart the WATCHDOG Timer.
Location:
Type:
Offset 01h
R/W
Bit
7
0
6
0
5
0
4
0
3
2
1
0
Serial Port 2 Serial Port 1 Mouse IRQ KBD IRQ
IRQ Trigger IRQ Trigger
Name
Reset
Reserved
Trigger
Enable
Trigger
Enable
Enable
Enable
0
0
0
0
Bit
Description
7-4 Reserved.
3
2
1
0
Serial Port 2 IRQ Trigger Enable. This bit enables the IRQ assigned to Serial Port 2 to trigger WATCHDOG
Timer reloading.
0: Serial Port 2 IRQ not a trigger event
1: An active Serial Port 2 IRQ enabled as a trigger event
Serial Port 1 IRQ Trigger Enable. This bit enables the IRQ assigned to Serial Port 1 to trigger WATCHDOG
Timer reloading.
0: Serial Port 1 IRQ not a trigger event
1: An active Serial Port 1 IRQ enabled as a trigger event
Mouse IRQ Trigger Enable. This bit enables the IRQ assigned to the Mouse to trigger WATCHDOG Timer
reloading.
0: Mouse IRQ not a trigger event
1: An active Mouse IRQ enabled as a trigger event
KBD IRQ Trigger Enable. This bit enables the IRQ assigned to the Keyboard to trigger reloading of the
WATCHDOG Timer.
0: Keyboard IRQ not a trigger event
1: An active Keyboard IRQ enabled as a trigger event
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7.0 WATCHDOG Timer (WDT) (Continued)
7.3.4
WATCHDOG Status Register (WDST)
This register holds the WATCHDOG Timer status, which reflects the value of the WDO pin and indicates that the timeout
period has expired.
On reset or on WATCHDOG Timer activation, this register is initialized to 01h.
Location:
Type:
Offset 02h
RO
Bit
7
Time Unit
0
6
0
5
0
4
0
3
0
2
1
0
Name
Reset
Reserved
Time Unit Reserved WDO Value
0
0
1
Bit
Description
7
Time Unit.
0: Minutes (default)
1: Seconds (see Section 7.4)
6-3 Reserved.
2
Time Unit.
0: Minutes (default)
1: Seconds (see Section 7.4)
1
0
Reserved.
WDO Value. This bit reflects the value of the WDO signal (even if WDO is not configured for output).
0: WDO active
1: WDO inactive (default)
7.4 COUNTING DOWN IN SECONDS
To select seconds (instead of minutes) as the time unit used by the WATCHDOG Timer to countdown:
1. In the WDST register (see Section 7.3.4), write 80h to set bit 7 to ‘1’.
2. In the WDST register, write 84h to set bit 2 to ‘1’.
3. In the WDTO register (see Section Section 7.3.2), set the number of seconds to countdown (in Hexadecimal notation,
for example, ‘0A’ is 10 seconds, ‘FF’ is 255 seconds).
7.5 WATCHDOG TIMER REGISTER BITMAP
Register
Bits
Offset Mnemonic
7
6
5
4
3
2
1
0
00h
WDTO
Programmed Timeout Period
Serial Port 2 Serial Port 1
Mouse IRQ KBD IRQ
IRQ
Trigger
Enable
IRQ
Trigger
Enable
01h
WDMSK
Reserved
Trigger
Enable
Trigger
Enable
WDO
Value
02h
WDST
Time Unit
Reserved
Time Unit Reserved
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8.0 ACCESS.bus Interface (ACB)
The ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. The ACB is also com-
patible with Intel's SMBus and Philips’ I2C. The ACB can be configured as a bus master or slave and can maintain bi-direc-
tional communication with both multiple master and slave devices. As a slave device, the ACB may issue a request to
become the bus master.
The ACB allows easy interfacing to a wide range of low-cost memories and I/O devices, including EEPROMs, SRAMs, tim-
ers, ADC, DAC, clock chips and peripheral drivers.
This chapter describes the general ACB functional block. A device may include a different implementation. For device spe-
cific implementation, see the Device Architecture and Configuration chapter.
8.1 OVERVIEW
The ACCESS.bus protocol uses a two-wire interface for bi-directional communication between the devices connected to the
bus. The two interface lines are the Serial Data Line (SDL) and the Serial Clock Line (SCL). These lines should be connected
to a positive supply via an internal or external pull-up resistor and should remain high even when the bus is idle.
Each IC has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers).
During data transactions, the master device initiates the transaction, generates the clock signal and terminates the transac-
tion. For example, when the ACB initiates a data transaction with an attached ACCESS.bus compliant peripheral, the ACB
becomes the master. When the peripheral responds and transmits data to the ACB, their master/slave (data transaction ini-
tiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed.
8.2 FUNCTIONAL DESCRIPTION
8.2.1
Data Transactions
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Conse-
quently, throughout the clock’s high period, the data should remain stable (see Figure 22). Any changes on the SDA line
during the high state of the SCL and in the middle of a transaction aborts the current transaction. New data should be sent
during the low SCL state. This protocol permits a single data line to transfer both command/control information and data,
using the synchronous serial clock.
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condi-
tion to terminate the transaction. Each byte is transferred with the most significant bit first. After each byte (8 bits), an Ac-
knowledge signal must follow. The following sections provide further details of this process.
During each clock cycle, the slave can stall the master while it handles the received data or prepares new data. This can be
done for each bit transferred, or on a byte boundary, by the slave holding SCL low to extend the clock-low period. Typically,
slaves extend the first clock cycle of a transfer if a byte read has not yet been stored or if the next byte to be transmitted is
not yet ready. Some microcontrollers with limited hardware support for ACCESS.bus extend the access after each bit, thus
allowing the software to handle this bit.
SDA
SCL
Data Line Change
Stable:
of Data
Data Valid Allowed
Figure 22. Bit Transfer
8.2.2
Start and Stop Conditions
The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated, the bus
is considered busy and retains this status for a certain time after a Stop Condition is generated. A high-to-low transition of
the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while
the SCL is high indicates a Stop Condition (Figure 23). After a Stop Condition is issued, the data in the received buffer is not
valid.
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows
another device to be accessed or a change in the direction of data transfer.
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8.0 ACCESS.bus Interface (ACB) (Continued)
SDA
SCL
S
P
Start
Stop
Condition
Condition
Figure 23. Start and Stop Conditions
8.2.3
Acknowledge (ACK) Cycle
The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred and the ACK
signal sent by the receiving device (see Figure 24).
The master generates the ACK clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA
line (permits it to go high) to allow the receiver to send the ACK signal. The receiver must pull down the SDA line during the
ACK clock pulse, signalling that it has correctly received the last data byte and is ready to receive the next byte. Figure 25
illustrates the ACK cycle.
Acknowledge
Signal From Receiver
SDA
MSB
SCL
3 - 6
9
ACK
8
1
2
7
9
ACK
1
2
3 - 8
P
S
Start
Condition
Stop
Condition
Clock Line Held
Low by Receiver
While Interrupt
is Serviced
Byte Complete
Interrupt Within
Receiver
Figure 24. ACCESS.bus Data Transaction
Data Output
by Transmitter
Transmitter Stays Off Bus
During Acknowledge Clock
Data Output
by Receiver
Acknowledge
Signal From Receiver
SCL
3 - 6
8
1
2
7
9
S
Start
Condition
Figure 25. ACCESS.bus Acknowledge Cycle
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.2.4
Acknowledge after Every Byte Rule
According to this rule, the master generates an acknowledge clock pulse after each byte transfer and the receiver sends an
acknowledge signal after every byte received. There are two exceptions to this rule:
• When the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (negative ac-
knowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse
(generated by the master), but the SDA line is not pulled down.
• When the receiver is full or otherwise occupied or if a problem has occurred, the receiver sends a negative acknowledge
to indicate that it cannot accept additional data bytes.
8.2.5
Addressing Transfer Formats
Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave
being addressed. The slave device should send an acknowledge signal on the SDA line once it recognizes its address.
The address consists of the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the
bit sent after the address, the eighth bit. A low-to-high transition during a SCL high period indicates the Stop Condition and
ends the transaction of SDA (see Figure 26).
When the address is sent, each device in the system compares this address with its own. If there is a match, the device
considers itself addressed and sends an acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the
device acts either as a transmitter or a receiver.
The I2C bus protocol allows a general call address to be sent to all slaves connected to the bus. The first byte sent specifies
the general call address (00h). The second byte specifies the meaning of the general call (for example, write slave address
by software only). Those slaves that require data acknowledge the call and become slave receivers; other slaves ignore the
call.
SDA
SCL
9
9
9
8
8
8
1 - 7
1 - 7
Data
1 - 7
Data
P
S
Start
Condition
Stop
Condition
Address
ACK
R/W
ACK
ACK
Figure 26. A Complete ACCESS.bus Data Transaction
8.2.6
Arbitration on the Bus
Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is
initially determined according to address bits and clock cycle. If the masters are trying to address the same slave, data com-
parisons determine the outcome of this arbitration. In Master mode, the device immediately aborts a transaction if the value
sampled on the SDA line differs from the value driven by the device. (An exception to this rule is SDA while receiving data.
The lines may be driven low by the slave without causing an abort.)
The SCL signal is monitored for clock synchronization and to allow the slave to stall the bus. The actual clock period is set
by the master with the longest clock period or by the slave stall period. The clock high period is determined by the master
with the shortest clock high period.
When an abort occurs during the address transmission, a master that identifies the conflict should give up the bus, switch
to Slave mode and continue to sample SDA to check if it is being addressed by the winning master on the bus.
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.2.7
Master Mode
Requesting Bus Mastership
An ACCESS.bus transaction starts with a master device requesting bus mastership. It asserts a Start Condition followed by
the address of the device it wants to access. If this transaction is successfully completed, the software may assume that the
device has become the bus master.
For the device to become the bus master, the software should perform the following steps:
1. Configure the INTEN bit of the ACBCTL1 register to the desired operation mode (Polling or Interrupt) and set the START
bit of this register. This causes the ACB to issue a Start Condition on the ACCESS.bus when the ACCESS.bus becomes
free (BB bit of the ACBCST register is cleared or other conditions that can delay start). It then stalls the bus by holding
SCL low.
2. If a bus conflict is detected (i.e., another device pulls down the SCL signal), the BER bit of the ACBST register is set.
3. If there is no bus conflict, the MASTER bit of the ACBST register and the SCAST of the ACBST register are set.
4. If the INTEN bit of the ACBCTL1 register is set and either the BER or SDAST bit of the ACBST register is set, an interrupt
is issued.
Sending the Address Byte
When the device is the active master of the ACCESS.bus (the MASTER bit of the ACBST register is set), it can send the
address on the bus.
The address sent should not be the device’s own address, as defined by the ADDR bit of the ACBADDR register if the SAEN
bit of this register is set, nor should it be the global call address if the GCMTCH bit of the ACBCST register is set.
To send the address byte, use the following sequence:
1. For a receive transaction where the software wants only one byte of data, set the ACB bit of the ACBCTL1 register. If
only an address needs to be sent or if the device requires stall for some other reason, set the STASTRE bit of the
ACBCTL1 register.
2. Write the address byte (7-bit target device address) and the direction bit to the ACBSDA register. This causes the ACB
to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to the NEGACK bit of
the ACBST register. During the transaction, the SDA and SCL lines are continuously checked for conflict with other de-
vices. If a conflict is detected, the transaction is aborted, the BER bit of the ACBST register is set and the MASTER bit
of this register is cleared.
3. If the STASTRE bit of the ACBCTL1 register is set and the transaction was successfully completed (i.e., both the BER
and NEGACK bits of the ACBST register are cleared), the STASTR bit is set. In this case, the ACB stalls any further
ACCESS.bus operations (i.e., holds SCL low). If the INTEN bit of the ACBCTL1 register is set, it also sends an interrupt
request to the host.
4. If the requested direction is transmit and the start transaction was completed successfully (i.e., neither the NEGACK nor
the BER bit of the ACBST register is set and no other master has accessed the device), the SDAST bit of the ACBST
register is set to indicate that the ACB awaits attention.
5. If the requested direction is receive, the start transaction was completed successfully and the STASTRE bit of the
ACBCTL1 register is cleared, the ACB starts receiving the first byte automatically.
6. Check that both the BER and NEGACK bits of the ACBST register are cleared. If the INTEN bit of the ACBCTL1 register
is set, an interrupt is generated when either the BER or NEGACK bit of the ACBST register is set.
Master Transmit
After becoming the bus master, the device can start transmitting data on the ACCESS.bus.
To transmit a byte in an interrupt or polling controlled operation, the software should:
1. Check that both the BER and NEGACK bits of the ACBST register are cleared and that the SDAST bit of the ACBST
register is set. If the STASTRE bit of the ACBCTL1 register is set, also check that the STASTR bit of the ACBST register
is cleared (and clear it if required).
2. Write the data byte to be transmitted to the ACBSDA register.
When either the NEGACK or BER bit of the ACBST register is set, an interrupt is generated. When the slave responds with
a negative acknowledge, the NEGACK bit of the ACBST register is set and the SDAST bit of the ACBST register remains
cleared. In this case, if the INTEN bit of the ACBCTL1 register is set, an interrupt is issued.
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8.0 ACCESS.bus Interface (ACB) (Continued)
Master Receive
After becoming the bus master, the device can start receiving data on the ACCESS.bus.
To receive a byte in an interrupt or polling operation, the software should:
1. Check that the SDAST bit of the ACBST register is set and that the BER bit is cleared. If the STASTRE bit of the
ACBCTL1 register is set, also check that the STASTRE bit of the ACBST register is cleared (and clear it if required).
2. Set the ACK bit of the ACBCTL1 register to 1, if the next byte is the last byte that should be read. This causes a negative
acknowledge to be sent.
3. Read the data byte from the ACBSDA register.
Before receiving the last byte of data, set the ACK bit of the ACBCTL1 register.
Master Stop
To end a transaction, set the STOP bit of the ACBCTL1 register before clearing the current stall flag (i.e., the SDAST,
NEGACK or STASTR bit of the ACBST register). This causes the ACB to send a Stop Condition immediately and to clear
the STOP bit of the ACBCTL1 register. A Stop Condition may be issued only when the device is the active bus master (the
MASTER bit of the ACBST register is set).
Master Bus Stall
The ACB can stall the ACCESS.bus between transfers while waiting for the host response. The ACCESS.bus is stalled by
holding the SCL signal low after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus
operation. The user must make sure that the next operation is prepared before the flag that causes the bus stall is cleared.
The flags that can cause a bus stall in Master mode are:
●
Negative acknowledge after sending a byte (NEGACK bit of the ACBST register = 1).
●
SDAST bit of the ACBST register = 1.
●
STASTRE bit of the ACBCTL1 register = 1 after a successful start (STASTR bit of the ACBST register =1).
Repeated Start
A repeated start is performed when the device is already the bus master (MASTER bit of the ACBST register is set). In this
case, the ACCESS.bus is stalled and the ACB awaits host handling due to the following states in the ACBST register: neg-
ative acknowledge (NEGACK bit = 1), empty buffer (SDAST bit = 1) and/or a stall after start (STASTR bit = 1).
For a repeated start:
1. Set the START bit of the ACBCTL1 register = 1.
2. In Master Receive mode, read the last data item from ACBSDA.
3. Follow the address send sequence, as described in Sending the Address Byte.
4. If the ACB was awaiting handling (STASTR bit of the ACBST register = 1), clear it only after writing the requested address
and direction to ACBSDA.
Master Error Detection
The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer or the acknowledge
cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal condition is detected, BER is set and Master mode is
exited (MASTER bit of the ACBST. register is cleared).
Bus Idle Error Recovery
When a request to become the active bus master or a restart operation fails, the BER bit of the ACBST register is set to
indicate the error. In some cases, both the device and the other device may identify the failure and leave the bus idle. In this
case, the start sequence may be incomplete and the ACCESS.bus may remain deadlocked.
To recover from deadlock, use the following sequence:
1. Clear the BER and BB bits of the ACBCST register.
2. Wait for a timeout period to check that there is no other active master on the bus (the BB bit remains cleared).
3. Disable and re-enable the ACB to put it in the non-addressed Slave mode. This completely resets the functional block.
At this point, some of the slaves may not identify the bus error. To recover, the ACB becomes the bus master: it asserts a
Start Condition, sends an address byte and then asserts a Stop Condition that synchronizes all the slaves.
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.2.8
Slave Mode
A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the ACB is enabled and is not acting
as a master (the MASTER bit of the ACBST register is cleared), it acts as a slave device.
Once a Start Condition on the bus is detected, the device checks whether the address sent by the current master matches
either:
●
The ADDR bit value of the ACBADDR register, if the SAEN bit = 1, or
●
The general call address if the GCMEN bit of the ACBCTL1 register = 1.
This match is checked even when the MASTER bit is set. If a bus conflict (on SDA or SCL) is detected, the BER bit of the
ACBST register is set, the MASTER bit is cleared and the device continues to search the received message for a match.
If an address match or a global match is detected:
1. The device asserts its SDA pin during the acknowledge cycle.
2. The MATCH bit of the ACBCST register and the NMATCH bit of the ACBST register are set. If the XMIT bit of the ACBST
register is set (Slave Transmit mode), the SDAST bit of the ACBST register is set to indicate that the buffer is empty.
3. If the INTEN bit of the ACBCTL1 register is set, an interrupt is generated the NMINTE bit is also set.
4. The software then reads the XMIT bit of the ACBST register to identify the direction requested by the master device. It
clears the NMATCH bit of the ACBST register so future byte transfers are identified as data bytes.
Slave Receive and Transmit
Slave receive and transmit are performed after a match is detected and the data transfer direction is identified. After a byte
transfer, the ACB extends the acknowledge clock until the software reads or writes the ACBSDA register. The receive and
transmit sequences are identical to those used in the master routine.
Slave Bus Stall
When operating as a slave, the device stalls the ACCESS.bus by extending the first clock cycle of a transaction in the fol-
lowing cases:
●
SDAST bit of the ACBST register is set.
●
NMATCH bit of the ACBST register and NMINTE bit of the ACBCTL1 register are set.
Slave Error Detection
The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition within the data transfer
or the acknowledge cycle). When this occurs, the BER bit is set and MATCH and GMATCH are cleared, setting the ACB as
an unaddressed slave.
8.2.9
Configuration
SDA and SCL Signals
The SDA and SCL are open-drain signals. The device permits the user to define whether to enable or disable the internal
pull-up of each of these signals.
ACB Clock Frequency
The ACB permits the user to set the clock frequency for the ACCESS.bus clock. The clock is set by the SCLFRQ field of the
ACBCTL2 register, which determines the SCL clock period used by the device. This clock low period may be extended by
stall periods initiated by the ACB or by another ACCESS.bus device. In case of a conflict with another bus master, a shorter
clock high period may be forced by the other bus master until the conflict is resolved.
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.3 ACB REGISTERS
The following abbreviations are used to indicate the Register Type:
• R/W = Read/Write.
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write.
• RO = Read Only.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
8.3.1
ACB Register Map
Offset Mnemonic
00h ACBSDA ACB Serial Data
01h ACBST ACB Status
Register Name
Type
Section
R/W
Varies per bit
Varies per bit
R/W
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
02h ACBCST ACB Control Status
03h ACBCTL1 ACB Control 1
04h ACBADDR ACB Own Address
05h ACBCTL2 ACB Control 2
R/W
R/W
8.3.2
ACB Serial Data Register (ACBSDA)
This shift register is used to transmit and receive data. The most significant bit is transmitted (received) first and the least
significant bit is transmitted (received) last. Reading or writing to the ACBSDA register is allowed only when the SDAST bit
of the ACBST register is set or for repeated starts after setting the START bit. An attempt to access this register under other
conditions may produce unpredictable results.
Location:
Type:
Offset 00h
R/W
Bit
7
6
5
4
3
2
1
0
Name
Reset
ACB Serial Data
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.3.3
ACB Status Register (ACBST)
This register maintains the current ACB status. On reset, and when the ACB is disabled, ACBST is cleared (00h).
Location:
Type:
Offset 01h
Varies per bit
Bit
7
SLVSTP
0
6
SDAST
0
5
BER
0
4
NEGACK
0
3
STASTR
0
2
NMATCH
0
1
MASTER
0
0
XMIT
0
Name
Reset
Bit
Type
Description
7
R/W1C SLVSTP (Slave Stop). Writing 0 to SLVSTP is ignored.
0: Writing 1 or ACB disabled
1: Stop Condition detected after a slave transfer in which MATCH or GCMATCH was set
6
5
RO SDAST (SDA Status).
0: Reading from the ACBSDA register during a receive or when writing to it during a transmit. When
ACBCTL1.START is set, reading the ACBSDA register does not clear SDAST. This enables ACB to
send a repeated start in Master Receive mode.
1: SDA Data register awaiting data (transmit - master or slave) or holds data that should be read
(receive - master or slave).
R/W1C BER (Bus Error). Writing 0 to BER is ignored.
0: Writing 1 or ACB disabled
1: Start or Stop Condition detected during data transfer (i.e., Start or Stop Condition during the transfer
of bits 2 through 8 and acknowledge cycle) or when an arbitration problem is detected.
4
3
R/W1C NEGACK (Negative Acknowledge). Writing 0 to NEGACK is ignored.
0: Writing 1 or ACB disabled
1: Transmission not acknowledged on the ninth clock (In this case, SDAST is not set)
R/W1C STASTR (Stall After Start). Writing 0 to STASTR is ignored.
0: Writing 1 or ACB disabled
1: Address sent successfully (i.e., a Start Condition sent without a bus error or Negative Acknowledge),
if ACBCTL1.STASTRE is set. This bit is ignored in Slave mode. When STASTR is set, it stalls the
ACCESS.bus by pulling down the SCL line and suspends any further action on the bus (e.g., receive
of first byte in Master Receive mode). In addition, if ACBCTL1.INTEN is set, it also causes the ACB
to send an interrupt.
2
R/W1C NMATCH (New Match). Writing 0 to NMATCH is ignored. If ACBCTL1.INTEN is set, an interrupt is sent
when this bit is set.
0: Software writes 1 to this bit
1: Address byte follows a Start Condition or a repeated start, causing a match or a global-call match.
1
0
RO Master.
0: Arbitration loss (BER is set) or recognition of a Stop Condition
1: Bus master request succeeded and Master mode active
RO XMIT (Transmit). Direction bit.
0: Master/Slave Transmit mode not active
1: Master/Slave Transmit mode active
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.3.4
ACB Control Status Register (ACBCST)
This register configures and controls the ACB functional block. It maintains the current ACB status and controls several ACB
functions. On reset and when the ACB is disabled, the non-reserved bits of ACBCST are cleared.
Location:
Type:
Offset 02h
Varies per bit
Bit
7
6
0
5
TGSCL
0
4
TSDA
X
3
GCMTCH
0
2
MATCH
0
1
BB
0
0
BUSY
0
Name
Reset
Reserved
0
Bit Type
Description
7-6
Reserved.
5
R/W
TGSCL (Toggle SCL Line). Enables toggling the SCL line during error recovery.
0: Clock toggle completed
1: When the SDA line is low, writing 1 to this bit toggles the SCL line for one cycle. Writing 1 to TGSCL
while SDA is high is ignored
4
3
RO
RO
TSDA (Test SDA Line). This bit reads the current value of the SDA line. It can be used while recovering
from an error condition in which the SDA line is constantly pulled low by an out-of-sync slave. Data written
to this bit is ignored.
GCMTCH (Global Call Match).
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition)
1: In Slave mode, ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a Start
Condition) is 00h
2
RO
MATCH (Address Match).
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition)
1: ACBADDR.SAEN is set and the first seven bits of the address byte (the first byte transferred after a
Start Condition) match the 7-bit address in the ACBADDR register
1
0
R/W1C BB (Bus Busy).
0: Writing 1, ACB disabled or Stop Condition detected
1: Bus active (a low level on either SDA or SCL) or Start Condition
RO
Busy. This bit should always be written 0. This bit indicates the period between detecting a Start Condition
and completing receipt of the address byte. After this, the ACB is either free or enters Slave mode.
0: Completion of any state below or ACB disabled
1: ACB is in one of the following states:
—
—
—
Generating a Start Condition
Master mode (ACBST.MASTER is set)
Slave mode (ACBCST.MATCH or ACBCST.GCMTCH set)
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.3.5
ACB Control Register 1 (ACBCTL1)
Location:
Type:
Offset 03h
R/W
Bit
7
STASTRE
0
6
NMINTE
0
5
GCMEN
0
4
ACK
0
3
Reserved
0
2
INTEN
0
1
STOP
0
0
START
0
Name
Reset
Bit
Description
7
STASTRE (Stall After Start Enable).
0: When cleared, ACBST.STASTR can not be set. However, if ACBST.STASTR is set, clearing STASTRE will not
clear ACBST.STASTR.
1: Stall after start mechanism enabled; ACB stalls the bus after the address byte
6
5
4
NMINTE (New Match Interrupt Enable).
0: No interrupt issued on a new match
1: Interrupt issued on a new match only if ACBCTL1.INTEN set
GCMEN (Global Call Match Enable).
0: ACB not responding to global call
1: Global call match enabled
Receive Acknowledge. This bit is ignored in Transmit mode. When the device acts as a receiver (slave or
master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle.
0: Cleared after acknowledge cycle
1: Negative acknowledge issued on next received byte
3
2
Reserved.
Interrupt Enable.
0: ACB interrupt disabled
1: ACB interrupt enabled. An interrupt is generated in response to one of the following events:
—
—
—
—
—
—
Detection of an address match (ACBST.NMATCH=1) and NMINTE=1
Receipt of Bus Error (ACBST.BER=1)
Receipt of Negative Acknowledge after sending a byte (ACBST.NEGACK=1)
Acknowledge of each transaction (same as the hardware set of the ACBST.SDAST bit)
In Master mode if ACBCTL1.STASTRE=1, after a successful start (ACBST.STASTR=1)
Detection of a Stop Condition while in Slave mode (ACBST.SLVSTP=1)
1
0
Stop.
0: Automatically cleared after STOP issued
1: Setting this bit in Master mode generates a Stop Condition to complete or abort current message transfer
Start. Set this bit only when in Master mode or when requesting Master mode.
0: Cleared after Start Condition sent or Bus Error (ACBST.BER=1) detected
1: Single or repeated Start Condition generated on the ACCESS.bus. If the device is not the active master of
the bus (ACBST.MASTER=0), setting START generates a Start Condition when the ACCESS.bus becomes
free (ACBCST.BB=0). An address transmission sequence should then be performed.
If the device is the active master of the bus (ACBST.MASTER=1), setting START and then writing to the
ACBSDA register generates a Start Condition. If a transmission is already in progress, a repeated Start
Condition is generated. This condition can be used to switch the direction of the data flow between the master
and the slave or to choose another slave device without separating them with a Stop Condition.
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.3.6
ACB Own Address Register (ACBADDR)
This is a byte-wide register that holds the ACB ACCESS.bus address. The reset value of this register is undefined.
Location:
Type:
Offset 04h
R/W
Bit
7
6
5
4
3
2
1
0
Name
Reset
SAEN
ADDR
Bit
Description
7
SAEN (Slave Address Enable).
0: ACB does not check for an address match with ADDR field
1: ADDR field holds a valid address and enables the match of ADDR to an incoming address byte
6-0 ADDR (Own Address). These bits hold the 7-bit device address. When in Slave mode, the first seven bits
received after a Start Condition are compared with this field (the first bit received is compared with bit 6 and the
last bit with bit 0). If the address field matches the received data and SAEN (bit 7) is 1, a match is declared.
8.3.7
ACB Control Register 2 (ACBCTL2)
This register enables/disables the functional block and determines the ACB clock rate.
Location:
Type:
Offset 05h
R/W
Bit
7
6
0
5
0
4
SCLFRQ
0
3
0
2
0
1
0
0
ENABLE
0
Name
Reset
0
Bit
Description
7-1 SCLFRQ (SCL Frequency). This field defines the SCL period (low and high time) when the device serves as a
bus master. The clock low and high times are defined as follows:
tSCLl = tSCLh = 2*SCLFRQ*tCLK
where tCLK is the module input clock cycle, as defined in the Device Architecture and Configuration chapter.
SCLFRQ can be programmed to values in the range of 00010002 (810) through 11111112 (12710). Using any
other value has unpredictable results.
0
Enable.
0: ACB disabled, ACBCTL1, ACBST and ACBCST cleared and clocks halted
1: ACB enabled
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8.0 ACCESS.bus Interface (ACB) (Continued)
8.4 ACB REGISTER BITMAP
Register
Bits
Offset Mnemonic
7
6
5
4
3
2
1
0
00h
01h
02h
03h
ACBSDA
ACBST
ACB Serial Data
NEGACK STASTR
SLVSTP
SDAST
BER
NMATCH MASTER
XMIT
BUSY
START
ACBCST
Reserved
TGSCL
GCMEN
TSDA
ACK
GCMTCH
Reserved
ADDR
MATCH
INTEN
BB
ACBCTL1 STASTRE NMINTE
SAEN
STOP
04h ACBADDR
05h ACBCTL2
SCLFRQ
ENABLE
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9.0 Game Port (GMP)
9.1 OVERVIEW
This chapter describes a generic Game Port. For the implementation used in this device, see the Device Architecture and
Configuration chapter.
The Game Port monitors the interface of up to two game devices and provides data that can be used to determine the exact
momentary status of these game devices.
A game device is an instrument used for giving commands to a PC, usually to control a game executed on that PC. A Joystick
is a commonly used game device. These commands are given by the game device in a passive manner by indicating several
status parameters that can be captured by the system via the Game Port.
The status of a game device includes the following parameters:
●
Button status (pressed/released) of up to two buttons per game device.
●
Horizontal (X-axis) position indicated by the game device.
●
Vertical (Y-axis) position indicated by the game device.
Figure 27 shows the basic system configuration of the Game Port.
X-Axis
X-Axis
Y-Axis
Y-Axis
Game Device
Game
Port
Game
Interface
Button 1
Button 0
Button 1
Button 0
Device A
Circuitry
Figure 27. Game Port System Configuration
9.2 FUNCTIONAL DESCRIPTION
9.2.1
Game Device Axis Position Indication
A typical game device has the following interface pins:
●
an X-axis position indicator.
●
a Y-axis position indicator.
●
one or two button status indicator(s).
The X and Y axis indicators are fed into the Game Port via pins JOYnX and JOYnY, respectively, where ‘n’ indicates the
game device number. The status indicators of buttons 0 and 1 are fed into the Game Port via JOYnBTN0,1, respectively.
The X and Y axis position indication mechanism of each game device includes external components, as seen in Figure 28.
Such a mechanism is implemented per game device axis line.
X/Y-Axis
Indicators
Input
Path
RVX
RCX
Game
Port
JOYnX
JOYnY
Pins
CX
X/Y-Axis
Circuit
Discharge
Control
Game Device
X/Y-Axis Varying
Resistor
Waveform Shaping Circuit
Figure 28. Game Device Axis Position Indication Mechanism
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9.0 Game Port (GMP) (Continued)
The varying resistors RVX and RVY are usually implemented in the game device. Their resistance values are determined
directly by the horizontal and vertical positions, respectively, indicated by the game device. The waveform shaping circuits
are usually implemented outside the game device using constant resistors (RCX/Y) and constant capacitors (CX/Y). Together
with RVX/Y, these components implement two R-C structures whose varying parameters are used to determine the exact
momentary position indicated by the game device.
When the Game Port is enabled and not in the midst of a game device position reading process, it drives the JOYnX,Y pins
low. In this state, the capacitors CX/Y are completely discharged.
9.2.2
Capturing the Position
The process of capturing the position indicated by the game device is initiated by a command given to the Game Port to
release the JOYnX,Y lines, thus allowing the capacitors CX/Y to be charged. This command is given by performing a write
access to offset 1 from the Game Port base address, which is the offset of the Game Port Legacy Status Register (GMPLST,
see Section 9.3.3). Once JOYnX,Y pins are released, RCX/Y and RVX/Y start charging CX/Y, and the voltage level of the
JOYnX,Y pins increases until it reaches VIH. This process is described in Figure 29.
V
CX/Y [V]
Charge
Discharge
Idle
Idle
VDD
VIH
0
Drive
Low
Drive
Low
Release
Time
Time measured as
position indication
Figure 29. Position Reading Process Waveform (not drawn to scale)
The vertical and horizontal positions indicated by the game device are determined by measuring the time it takes for the
voltage level on the JOYnX,Y pins to reach the level of logic 1. Since the charging time is determined by the resistance val-
ues of RVX/Y, measuring this time actually indicates the resistance values of RVX/Y and therefore also reflects the position
indicated by the game device.
Once an axis pin is sensed as logic 1, the axis circuit discharge control is activated in order to discharge CX/Y. This causes
the corresponding axis pin to be driven low for approximately 1.5 µsec. After that, this axis line is held low until another po-
sition reading process is initiated.
During the charge time and the 1.5 µsec discharge time that follows, the corresponding axis line does not respond to any
reading process initiation. This prevents software from disturbing the position reading process and makes the position read-
ing processes of all axis lines independent of each other.
9.2.3
Button Status Indication
The button status indication mechanism is described in Figure 30. Although this figure shows an active-low button
(RBU0>>RBD0), the polarity of the button can be either high or low, assuming that the Game Port software is aware of the
button’s polarity.
Buttons 0,1
Status
RBU0
Indicators
Input Path
Game
Port
JOYnBTN0
JOYnBTN1
Pins
RBD0
Game Device Button Status Circuit
Figure 30. Game Device Button Status Indication Mechanism
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9.0 Game Port (GMP) (Continued)
A simple push-button mechanism is usually used to implement the game device buttons. The status of each button is sensed
by the Game Port via the JOYnBTN0,1 pins as either high or low and is reflected by the GMPLST register. It is the respon-
sibility of the software to determine the actual status of the buttons according to their polarity, which depends on the specific
implementation of the system and the game device.
9.2.4
Operation Modes
The Game Port can be used to monitor the position and button status indicators in one of the following operation modes:
●
Legacy mode.
●
Enhanced mode.
Legacy Mode
Legacy mode is enabled when bit 0 of the GMPCTL register is set to 0, which is its default state.
In this mode, the game device indicators are monitored by polling their momentary status via the Game Port Legacy Status
register (GMPLST, see Section 9.3.3).
The process of reading the position status of the game device(s) is initiated by performing a write access to offset 1 in the
Game Port address space. This write access causes the Game Port to release the JOYnX,Y pins. When a JOYnX,Y pin is
released, the corresponding bit in the GMPLST register is set to 1. To capture the position indicated by the game device,
the software must poll the GMPLST register and measure the time it takes for JOYnX,Y to go high. This measurement should
be performed by measuring the time during which an axis bit is 1.
Reading the status of the buttons of the game device is done by polling the GMPLST register and looking for changes in the
bits reflecting the status of the JOYnBTN0,1 pins.
No debounce of the input signals is performed by the Game Port in Legacy mode. It is the responsibility of the software to
implement such debounce, if necessary.
Enhanced Mode
Enhanced mode is enabled when bit 0 of the GMPCTL register is set to 1.
In Enhanced mode, the Game Port hardware monitors the status indicators of the game device(s) and provides processed
data that can be easily used by software to determine the complete status of the game device.
The process of reading the position status of the game device(s) is initiated the same way it is done in Legacy mode. How-
ever, in Enhanced mode, the Game Port hardware measures the CX/Y charging time using four 16-bit up-counters. Each
one of the four axis status lines (two lines per game device) has a dedicated counter.
Once the Game Port releases the JOYnX,Y to go high, each one of the counters starts counting until its associated axis
status line reaches the voltage level of logic 1.
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9.0 Game Port (GMP) (Continued)
When a position counter of a game device stops counting, its associated Position Counter Ready bit in the GMPXST register
is set. All the software has to do in this case is wait until the counters associated with the game device are ready and then
read their values. The least significant byte of a position counter should be read first. The full 16-bit count value should be
calculated as follows:
X/Y Position Count = GMPnX/YL + (GMPnX/YH * 256)
where:
GMPnX/YL indicates the low byte of the position counter of device n (either X or Y axis) and
GMPnY/HL indicates the high byte of the position counter of device n (either X or Y axis).
It is the responsibility of the software to calibrate itself according to the actual count values acquired when the game device
was set to indicate its extreme horizontal and vertical positions.
If a position counter has reached the full count of FFFFh, it means that this counter has overflowed. Overflow means that
the counter has reached its full count before the corresponding axis indicator has reached the level of logic 1. In such a case,
the software must decide what to do.
The Game Port supports the following clock frequencies for operating the position counters:
●
1 MHz clock (default).
●
500 KHz clock.
The clock frequency for the position counter of each game device is configured via the GMPCTL register and should be set
by the software to match the physical components of the external game device interface circuitry. Setting the desired position
counter frequency should be done before initiating a position status reading process.
Reading the status of the buttons of the game device(s) is done the same way it is done in Legacy mode. In addition, an
optional debouncer of 16 msec is implemented on each button status input. The debouncers are disabled by default and
may be enabled by software via the GMPCTL register.
9.2.5
Operation Control
When the Game Port is operated in Legacy mode, it can only be operated by polling (see Section 9.2.4, Legacy Mode).
When the Game Port is operated in Enhanced mode, both kinds of status reading operations (position and button) can be
performed using polling or interrupt controlled operation.
If polling controlled operation is preferred, the software should poll either the GMPLST register for the direct status of the
buttons as in Legacy mode or the GMPXST register, which provides indications regarding button events detected by hard-
ware. The GMPXST register should also be polled for the status of the position counters. When the status is ready, the
counter values can be read. These values reflect the positions indicated by the game device.
If interrupt controlled operation is preferred, the software should first define the events on which an interrupt request is to be
issued. This is done by writing the required values to the GMPEPOL (see Section 9.3.14) and GMPIEN (see Section 9.3.5)
registers. The GMPEPOL register defines the events on which the buttons cause an interrupt request to be issued. These
events are all edge-triggered. The GMPIEN register determines which events are physically routed to the interrupt request
assigned to the Game Port. An independent interrupt enable bit is implemented in the GMPIEN register for each one of the
four buttons and two position counters of the two supported game devices.
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9.0 Game Port (GMP) (Continued)
9.3 GAME PORT REGISTERS
The following abbreviations are used to indicate the Register Type:
●
R/W = Read/Write.
●
R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
●
W = Write.
●
RO = Read Only.
●
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
9.3.1
Game Port Register Map
The following table lists the Game Port registers. For the Game Port register bitmap, see Section 9.4.
Offset
Mnemonic
Register Name
Type
Section
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
GMPCTL Game Port Control
R/W
RO
9.3.2
9.3.3
GMPLST Game Port Legacy Status
GMPXST Game Port Extended Status
R/W1C
R/W
RO
9.3.4
GMPIEN Game Port Interrupt Enable
9.3.5
GMPAXL Game Device A X Position Low Byte
GMPAXH Game Device A X Position High Byte
GMPAYL Game Device A Y Position Low Byte
GMPAYH Game Device A Y Position High Byte
GMPBXL Game Device B X Position Low Byte
GMPBXH Game Device B X Position High Byte
GMPBYL Game Device B Y Position Low Byte
GMPBYH Game Device B Y Position High Byte
GMPEPOL Game Port Event Polarity
9.3.6
RO
9.3.7
RO
9.3.8
RO
9.3.9
RO
9.3.10
9.3.11
9.3.12
9.3.13
9.3.14
RO
RO
RO
R/W
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9.0 Game Port (GMP) (Continued)
9.3.2
Game Port Control Register (GMPCTL)
This register affects the functionality of the Game Port only when operated in Enhanced mode (bit 0 of this register is set
to 1). Bits 1,2 and 4-7 affect Game Port functionality, as described in the table below.
Location:
Type:
Offset 00h
R/W
Bit
7
6
5
4
3
2
1
0
Device B
Button 1
Device B
Button 0
Device A
Button 1
Device A
Button 0
GMP
Enhanced
Mode
Device B
Reserved Pre-Scale Pre-Scale
Device A
Name
Debounce Debounce Debounce Debounce
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Reset
0
0
0
0
0
0
0
0
0
Required
Bit
Description
7
Device B Button 1 Debounce Enable. When set to 1, enables a 16 ms input debouncer on Device B Button 1
status input.
0: Disabled (default)
1: Enabled
6
5
4
Device B Button 0 Debounce Enable. Same as bit 7 but for Device B Button 0.
0: Disabled (default)
1: Enabled
Device A Button 1 Debounce Enable. Same as bit 7 but for Device A Button 1.
0: Disabled (default)
1: Enabled
Device A Button 0 Debounce Enable. Same as bit 7 but for Device A Button 0.
0: Disabled (default)
1: Enabled
3
2
Reserved.
Device B Pre-Scale Enable. This bit determines the clock frequency used by Device B position counters.
0: 1 MHz (default)
1: 500 KHz
1
0
Device A Pre-Scale Enable. This bit determines the clock frequency used by Device A position counters.
0: 1 MHz (default)
1: 500 KHz
GMP Enhanced Mode Enable.
0: Disabled (default)
1: Enabled
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9.0 Game Port (GMP) (Continued)
9.3.3
Game Port Legacy Status Register (GMPLST)
This register is functional in all Game Port operation modes. Reading this register returns the status and the state of Device
A and B button and Axis pins, as defined in the table below. Writing to the offset of this register initiates a game device po-
sition reading process by forcing a low pulse to be driven on the axis pins in Legacy and Enhanced modes and by initializing
all position counters in Enhanced mode.
Location:
Type:
Offset 01h
RO
Bit
7
6
5
4
3
2
1
0
Device B
Button 1
Device B
Button 0
Device A
Button 1
Device A
Device B
Device B
Device A
Device A
Name
Reset
Button 0 Y-Axis Pin X-Axis Pin Y-Axis Pin X-Axis Pin
Pin Status Pin Status Pin Status Pin Status
Status
Status
Status
Status
X
X
X
X
X
X
X
X
Bit
Description
7
6
5
4
3
2
1
0
Device B Button 1 Pin Status. This bit directly reflects the status of Device B Button 1 input pin.
0: Low
1: High
Device B Button 0 Pin Status. This bit directly reflects the status of Device B Button 0 input pin.
0: Low
1: High
Device A Button 1 Pin Status. This bit directly reflects the status of Device A Button 1 input pin.
0: Low
1: High
Device A Button 0 Pin Status. This bit directly reflects the status of Device A Button 0 input pin.
0: Low
1: High
Device B Y-Axis Pin Status. This bit reflects the state of Device B Y-axis input pin.
0: JOYBY pin is released for charging
1: JOYBY pin is driven low
Device B X-Axis Pin Status. This bit reflects the state of Device B X-axis input pin.
0: JOYBX pin is released for charging
1: JOYBX pin is driven low
Device A Y-Axis Pin Status. This bit reflects the state of Device A Y-axis input pin.
0: JOYAY pin is released for charging
1: JOYAY pin is driven low
Device A X-Axis Pin Status. This bit reflects the status of Device A X-axis input pin.
0: JOYAX pin is released for charging
1: JOYAX pin is driven low
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9.0 Game Port (GMP) (Continued)
9.3.4
Game Port Extended Status Register (GMPXST)
This register indicates which of the corresponding game device interface events have occurred. Writing 1 to a bit clears it.
Reading a position counter clears the corresponding Counter Ready bit. Writing 0 to a bit has no effect.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 02h
R/W1C
Bit
7
6
5
4
3
2
1
0
Device B
Button 1
Event
Device B
Button 0
Event
Device A
Button 1
Event
Device A
Device B
Device B
Device A
Device A
Button 0 Y-Position X-Position Y-Position X-Position
Event
Status
Name
Reset
Counter
Ready
Counter
Ready
Counter
Ready
Counter
Ready
Status
Status
Status
0
0
0
0
0
0
0
0
Bit
Description
7
6
5
4
3
2
1
0
Device B Button 1 Event Status. When set to 1, indicates that a Device B Button 1 event has occurred. The
event itself is defined by the GMPEPOL register, see Section 9.3.14.
0: Event not active (default)
1: Event active
Device B Button 0 Event Status. When set to 1, indicates that a Device B Button 0 event has occurred. The
event itself is defined by the GMPEPOL register, see Section 9.3.14.
0: Event not active (default)
1: Event active
Device A Button 1 Event Status. When set to 1, indicates that a Device A Button 1 event has occurred. The
event itself is defined by the GMPEPOL register, see Section 9.3.14.
0: Event not active (default)
1: Event active
Device A Button 0 Event Status. When set to 1, indicates that a Device A Button 0 event has occurred. The
event itself is defined by the GMPEPOL register, see Section 9.3.14.
0: Event not active (default)
1: Event active
Device B Y-Position Counter Ready. When set to 1, indicates that the value of the Y-position counter of Device
B can now be read.
0: Event not active (default)
1: Event active
Device B X-Position Counter Ready. When set to 1, indicates that value of the X-position counter of Device B
can now be read.
0: Event not active (default)
1: Event active
Device A X-Position Counter Ready. When set to 1, indicates that the value of the Y-position counter of Device
A can now be read.
0: Event not active (default)
1: Event active
Device A X-Position Counter Ready. When set to 1, indicates that the value of the X-position counter of Device
A can now be read.
0: Event not active (default)
1: Event active
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9.0 Game Port (GMP) (Continued)
9.3.5
Game Port Interrupt Enable Register (GMPIEN)
This register defines the conditions on which the Game Port asserts its interrupt request signal.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 03h
R/W
Bit
7
6
5
4
3
2
1
0
Device B
Button 1
Device B
Button 0
Device A
Button 1
Device A
Button 0
Position
Reserved IRQ Event
Device B
Position
Device A
Position
Name
Reset
IRQ Enable IRQ Enable IRQ Enable IRQ Enable
Definition IRQ Enable IRQ Enable
0
0
0
0
0
0
0
0
Bit
Description
7
Device B Button 1 IRQ Enable. When set to 1, the Game Port issues an interrupt request in response to an
event triggered by Button 1 of Device B. When set to 0, Button 1 of Device B cannot cause interrupt requests to
be issued.
0: Disabled (default)
1: Enabled
6
5
4
Device B Button 0 IRQ Enable. Same as bit 7 of this register but for Device B Button 0.
0: Disabled (default)
1: Enabled
Device A Button 1 IRQ Enable. Same as bit 7 of this register but for Device A Button 1.
0: Disabled (default)
1: Enabled
Device A Button 0 IRQ Enable. Same as bit 7 of this register but for Device A Button 0.
0: Disabled (default)
1: Enabled
3
2
Reserved.
Position IRQ Event Definition Defines the event on which the position IRQ is asserted for both game devices.
0: Both X-Position Counter and Y-Position Counter are ready
1: Either X-Position Counter or Y-Position Counter is ready
1
0
Device B Position IRQ Enable. When set to 1, the Game Port issues an interrupt request when the position
reading of Device B is completed and the position counters can be read. When set to 0, no interrupt request is
issued in response to any change in the status of Device B position counters.
0: Disabled (default)
1: Enabled
Device A Position IRQ Enable. Same as bit 2 of this register but for Device A.
0: Disabled (default)
1: Enabled
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9.0 Game Port (GMP) (Continued)
9.3.6
Game Device A X-Axis Position Low Byte (GMPAXL)
Reading this register returns the value of the low byte of the X-axis position counter of game Device A. Before reading this
register verify that bit 0 of GMPXST (Device A Position Counter Ready) is set to 1. Writing to the offset of this register is
ignored.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 04h
RO
Bit
7
6
0
5
4
3
2
1
0
0
0
Name
Reset
Device A X-Axis Position Counter Low Byte
0
0
0
0
0
9.3.7
Game Device A X-Axis Position High Byte (GMPAXH)
Reading this register returns the value of the high byte of the X-axis position counter of game Device A. Read this register
after reading the GMPAXL register and verifying that bit 0 of GMPXST (Device A Position Counter Ready) is set to 1. Writing
to the offset of this register is ignored.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 05h
RO
Bit
7
6
0
5
4
3
2
1
0
0
0
Name
Reset
Device A X-Axis Position Counter High Byte
0
0
0
0
0
9.3.8
Game Device A Y-Axis Position Low Byte (GMPAYL)
Reading this register returns the value of the low byte of the Y-axis position counter of game Device A. Before reading this
register, verify that bit 1 of GMPXST (Device A Position Counter Ready) is set to 1. Writing to the offset of this register is
ignored.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 06h
RO
Bit
7
6
0
5
4
3
2
1
0
0
0
Name
Reset
Device A Y-Axis Position Counter Low Byte
0
0
0
0
0
9.3.9
Game Device A Y-Axis Position High Byte (GMPAYH)
Reading this register returns the value of the high byte of the Y-axis position counter of game Device A. Read this register
after reading the GMPAYL register and verifying that bit 1 of GMPXST (Device A Position Counter Ready) is set to 1. Writing
to the offset of this register is ignored.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 07h
RO
Bit
7
6
0
5
4
3
2
1
0
0
0
Name
Device A Y-Axis Position Counter High Byte
Reset
0
0
0
0
0
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9.0 Game Port (GMP) (Continued)
9.3.10 Game Device B X-Axis Position Low Byte (GMPBXL)
Reading this register returns the value of the low byte of the X-axis position counter of game Device B. Before reading this
register, verify that bit 2 of GMPXST (Device B Position Counter Ready) is set to 1. Writing to the offset of this register is
ignored.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 08h
RO
Bit
7
6
0
5
4
3
2
1
0
0
0
Name
Reset
Device B X-Axis Position Counter Low Byte
0
0
0
0
0
9.3.11 Game Device B X-Axis Position High Byte (GMPBXH)
Reading this register returns the value of the high byte of the X-axis position counter of game Device B. Before reading this
register, verify that bit 2 of GMPXST (Device B Position Counter Ready) is set to 1. Writing to the offset of this register is
ignored.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 09h
RO
Bit
7
6
0
5
4
3
2
1
0
0
0
Name
Reset
Device B X-Axis Position Counter High Byte
0
0
0
0
0
9.3.12 Game Device B Y-Axis Position Low Byte (GMPBYL)
Reading this register returns the value of the low byte of the Y-axis position counter of game Device B. Before reading this
register, verify that bit 3 of GMPXST (Device B Position Counter Ready) is set to 1. Writing to the offset of this register is
ignored.
This register is functional only in Enhanced mode.
Location:Offset 0Ah
Type:
RO
Bit
7
0
6
0
5
4
3
2
1
0
0
0
Name
Reset
Device B Y-Axis Position Counter Low Byte
0
0
0
0
9.3.13 Game Device B Y-Axis Position High Byte (GMPBYH)
Reading this register returns the value of the high byte of the Y-axis position counter of game Device B. Before reading this
register, verify that bit 3 of GMPXST (Device B Position Counter Ready) is set to 1. Writing to the offset of this register is
ignored.
This register is functional only in Enhanced mode.
Location:Offset 0Bh
Type:
RO
Bit
7
0
6
0
5
4
3
2
1
0
0
0
Name
Device B Y-Axis Position Counter High Byte
Reset
0
0
0
0
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9.0 Game Port (GMP) (Continued)
9.3.14 Game Port Event Polarity Register (GMPEPOL)
This register defines the polarity of button events on which the Game Port issues an interrupt request.
This register is functional only in Enhanced mode.
Location:
Type:
Offset 0Ch
R/W
Bit
7
6
5
4
3
2
1
0
Device B Button 1 Event Device B Button 0 Event Device A Button 1 Event Device A Button 0 Event
Polarity Polarity Polarity Polarity
Name
Reset
0
0
0
0
0
0
0
0
Bit
Description
7-6 Device B Button 1 Event Polarity. This bit defines the event polarity on which Device B Button 1 issues an
interrupt request.
Bits
7 6
Number
0 0
0 1
1 0
1 1
None (default)
Rising edge
Falling edge
Rising and falling edge
5-4 Device B Button 0 Event Polarity. Same as bits 7-6 of this register but for Device B Button 0.
Bits
5 4
Number
0 0
0 1
1 0
1 1
None (default)
Rising edge
Falling edge
Rising and falling edge
3-2 Device A Button 1 Event Polarity. Same as bits 7-6 of this register but for Device A Button 1.
Bits
3 2
Number
0 0
0 1
1 0
1 1
None (default)
Rising edge
Falling edge
Rising and falling edge
1-0 Device A Button 0 Event Polarity. Same as bits 7-6 of this register but for Device A Button 0.
Bits
1 0
Number
0 0
0 1
1 0
1 1
None (default)
Rising edge
Falling edge
Rising and falling edge
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9.0 Game Port (GMP) (Continued)
9.4 GAME PORT BITMAP
Register
Bits
Offset
Mnemonic
7
6
5
4
3
2
1
0
Device B Device B Device A Device A
Button 1 Button 0 Button 1 Button 0
Debounce Debounce Debounce Debounce
GMP
Enhanced
Mode
Device B Device A
Reserved Pre-Scale Pre-Scale
00h
GMPCTL
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Device B Device B Device A Device A
Button 1 Button 0 Button 1 Button 0
Device B
X-Axis
Pin
Device A
X-Axis
Pin
Device B
Y-AxisPin
Status
Device A
Y-Axis Pin
Status
01h
02h
03h
GMPLST
GMPXST
GMPIEN
Pin
Status
Pin
Status
Pin
Status
Pin
Status
Status
Status
Device B Device B Device A Device A Device B Device B Device A Device A
Button 1 Button 0 Button 1 Button 0 Y-Position X-Position Y-Position X-Position
Event
Status
Event
Status
Event
Status
Event
Status
Counter
Ready
Counter
Ready
Counter
Ready
Counter
Ready
Device B Device B Device A Device A
Button 1 Button 0 Button 1 Button 0
Position Device B Device A
IRQ
Event
Position
IRQ
Position
IRQ
Reserved
IRQ
IRQ
IRQ
IRQ
Enable
Enable
Enable
Enable
Definition
Enable
Enable
04h
05h
06h
07h
08h
09h
0Ah
0Bh
GMPAXL
GMPAXH
GMPAYL
GMPAYH
GMPBXL
GMPBXH
GMPBYL
GMPBYH
Device A X-Axis Position Counter Low Byte
Device A X-Axis Position Counter High Byte
Device A Y-Axis Position Counter Low Byte
Device A Y-Axis Position Counter High Byte
Device B X-Axis Position Counter Low Byte
Device B X-Axis Position Counter High Byte
Device B Y-Axis Position Counter Low Byte
Device B Y-Axis Position Counter High Byte
Device B Button 1
Event Polarity
Device B Button 0
Event Polarity
Device A Button 1
Event Polarity
Device A Button 0
Event Polarity
0Ch
GMPEPOL
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10.0 Musical Instrument Digital Interface (MIDI) Port
10.1 OVERVIEW
This chapter describes a generic MIDI Port. For the implementation used in this device, see the Device Architecture and
Configuration chapter.
The MIDI Port is an asynchronous receiver/transmitter that uses a two-wire, bi-directional, relatively slow communication
channel to transmit and receive data bytes to or from MIDI-compliant devices, according to a predefined communication pro-
tocol. The MIDI Port is compatible with MPU-401 UART mode.
The MIDI Port was originally defined to establish a standard interface between computers and digital musical instruments
such as synthesizers and has become the de facto standard for this purpose. However, the MIDI is also commonly used for
other purposes such as communicating with advanced game devices.
The MIDI Port serves as a communication pipe between software and a MIDI device. The software and the MIDI device must
interpret the data they exchange and act accordingly.
The MIDI Port supports the following two feature types:
●
Legacy (MPU-401).
●
Enhanced.
Legacy. These include all features supported by MPU-401 UART mode. They can all be operated via the Legacy I/O ad-
dress space of two bytes, traditionally allocated for the MIDI Port.
Enhanced. These features extend the capabilities of the MIDI Port. They can only be operated if the MIDI is allocated with
an address space of at least three bytes.
The basic system configuration of the MIDI Port consists of the port itself, a single pull-up resistor for the MDRX pin and a
MIDI-compliant device. This system configuration is shown in Figure 31. The purpose of the pull-up resistor is to make sure
that the MIDI Port senses an inactive (high) MIDI receive signal in the absence of a MIDI device.
R
MDRX Pin
MIDI Receive
MIDI Transmit
MIDI Transmit
MIDI Receive
MIDI
Port
MIDI
Device
MDTX Pin
Figure 31. MIDI System Configuration
10.2 FUNCTIONAL DESCRIPTION
The MIDI Port consists of five major functional blocks:
●
Internal Bus Interface Unit.
●
Port Control and Status Registers.
●
Data Buffers and FIFOs.
●
MIDI Communication Engine.
●
MIDI Signals Routing Control Logic.
See Figure 32 for a block diagram of the MIDI Port.
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
Asynchronous
Interface
Synchronous
Interface
SuperI/O
Internal
Bus
Tx Data
8
Tx Data
8
MIDI
Transmit
Signal
MIDI
Communication
Engine
Data
Buffers
and
MIDI
MDTX Pin
MDRX Pin
Internal
Rx Data
8
Rx Data
8
Signals
Routing
Control
Bus
Interface
Unit
MIDI
Receive
Signal
(Data Serializer)
FIFOs
Control
Control
Data Buffer
Status and Control
Communication
Status and Control
Read/Write
Routing
Control
Interface
MIDI Port
Control and Status
Registers
Figure 32. MIDI Port Block Diagram
10.2.1 Internal Bus Interface Unit
The Internal Bus Interface Unit handles all read and write transactions between the host and the registers of the MIDI Port.
It also controls the MIDI Port interrupt request logic (see Section 10.2.8).
10.2.2 Port Control and Status Registers
A Control register (MCNTL, see Section 10.3.6) and a Status register (MSTAT, see Section 10.3.4) allow the user to control
the operation of the MIDI and provide status information regarding its various functional units. A Command register (MCOM,
see Section 10.3.5) allows the user to control the operation mode of the MIDI Port by serving as a port via which the host
can issue commands to the MIDI. A MIDI Port command is defined as a write access to the MIDI Command register. The
meaning of each command is determined by the data byte written during this write access.
10.2.3 Data Buffers and FIFOs
The Data Buffers and FIFOs function as a mechanism for synchronizing between the Internal Bus Interface Unit and the
MIDI Communication Engine. This synchronization allows each of these units to handle its own tasks without having to
pause to send/receive data to/from the other unit. Synchronization also bridges the gap in the data transfer rate between
these two units. Data transfer rate matching is done when the FIFOs of the MIDI Port are enabled. It allows the MIDI Port to
interface a bus at a relatively high data transfer rate while maintaining communication with a MIDI device over a communi-
cation channel that supports a relatively low data transfer rate.
10.2.4 MIDI Communication Engine
The MIDI Communication Engine handles the serializing of outgoing data and the de-serializing of incoming data transferred
between the MIDI Port and the MIDI device. During transmit (serial data transfer from the MIDI Port to the MIDI device), the
Communication Engine receives data bytes from the output data buffer or FIFO, serializes them into a stream of data bits
and transmits them as a sequence of high and low pulses over the MDTX pin according to the MIDI communication protocol.
During receive (serial data transfer from the MIDI device to the MIDI Port), the Communication Engine receives a sequence
of high and low pulses via the MDRX pin, converts them into a stream of data bits and de-serializes them into data bytes
that it sends to the input data buffer or FIFO.
Both transmit and receive are performed at a fixed serial data rate of 31.25 Kbits per second. The serial data format is also
fixed and consists of one Start bit, eight Data bits and one Stop bit. See the waveform illustrating a MIDI byte transfer in
Figure 33.
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
LSB
MSB
0
MIDI Signal
Start
Stop
Bit
1
0
1
0
1
0
1
Data Bits
Bit
32µsec
Figure 33. MIDI Byte Transfer Waveform
10.2.5 MIDI Signals Routing Control Logic
The MIDI Signals Routing Control Logic controls the various routing options available for the MIDI transmit and receive sig-
nals. It is controlled by the MIDI Control register (MCNTL, see Section 10.3.6). These routing options are not part of the
Legacy definition of the MIDI Port.
10.2.6 Operation Modes
The MIDI Port can be operated in one of the following modes:
●
Pass-Thru (Non-UART) Mode (default).
●
UART Mode.
Pass-Thru (Non-UART) Mode
After a hardware reset, the MIDI Port is in Pass-Thru mode.
In this mode, transmission is disabled by default, and all writes to the MIDI Data Out register (MDO, see Section 10.3.3) are
ignored. Transmission in this mode may be enabled by setting bit 4 of the MIDI Control register (MCNTL, see Section
10.3.6).
Receive in Pass-Thru mode is enabled and a 16-byte Receive FIFO is available. Reading the MIDI Data In register (MDI,
see Section 10.3.2) in this mode returns the oldest data stored in the Receive FIFO. If serial data is received while the Re-
ceive FIFO is full with data that has not yet been read, the last received data is lost, thus maintaining the data that was pre-
viously stored in the Receive Buffer.
When in Pass-Thru mode, the MIDI Port responds to commands issued by the host, as follows:
●
3Fh puts the MIDI Port in UART mode. Also, in response to this command, the MIDI Port puts an acknowledge byte
of FEh in the Receive Buffer.
●
A0h-A7h or ABh causes the MIDI Port to put an acknowledge byte of FEh, followed by a data byte of 00h, in the Re-
ceive Buffer.
●
ACh causes the MIDI Port to put an acknowledge byte of FEh, followed by a data byte of 15h, in the Receive Buffer.
●
ADh causes the MIDI Port to put an acknowledge byte of FEh, followed by a data byte of 01h, in the Receive Buffer.
●
AFh causes the MIDI Port to put an acknowledge byte of FEh, followed by a data byte of 64h, in the Receive Buffer.
●
FFh resets the MIDI Port to its initial state, including all the bits of the MSTAT register. In response, the MIDI Port
puts an acknowledge of FEh in the Receive Buffer. This command is usually referred to as the MIDI Reset Command.
●
The MIDI Port responds to all other commands by putting an acknowledge byte of FEh in the Receive Buffer.
Putting the acknowledge byte of FEh is equivalent to receiving a data byte. Therefore, once an acknowledge byte is put in
the Receive Buffer, it causes the Receive Buffer Empty status flag (see Section 10.2.7) to be cleared, which may also cause
a MIDI Port interrupt request to be issued.
When the Receive FIFO is disabled, switching from Pass-Thru mode to UART mode causes data stored in the Receive Buff-
er to be lost. After switching to UART mode, the MIDI Port is blocked for receive until the acknowledge byte is read from the
Receive Buffer.
If a command is issued to the MIDI Port while the MIDI Communication Engine is in the middle of a byte transfer (the Start
bit has been transmitted or received), the execution of the command and the response are postponed until the ongoing byte
transfer is completed.
After each MIDI Port operation in Pass-Thru mode, the MIDI Status register (MSTAT, see Section 10.3.4) is updated accord-
ingly.
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
UART Mode
Entering UART mode is done by software giving the MIDI Port command of 3Fh. Once in UART mode, both transmit and
receive are enabled. In addition, the two 16-byte Receive and Transmit FIFOs are automatically enabled.
In UART mode, data written to the MDO register is placed in the Transmit FIFO, from which it is taken by the MIDI Commu-
nication Engine and transmitted via the MDTX pin to the MIDI device. Likewise, whenever the Transmit FIFO is not empty,
the next byte is taken out by the Communication Engine and transmitted via the MDTX pin to the MIDI device.
Whenever serial data is received by the Communication Engine via the MDRX pin, it is de-serialized and put in the Receive
FIFO. Reading the MDI register returns the next byte in the Receive FIFO. The MDI register should not be read while the
Receive FIFO is empty. If serial data is received while the Receive FIFO is full, this data is lost and not stored in the Receive
FIFO, thus keeping the data that was previously stored in the Receive FIFO.
When in UART mode, the MIDI Port responds to commands given by the host as follows:
●
A command of FFh returns the MIDI Port to Pass-Thru mode and resets it to its initial state.
●
All other commands issued while the MIDI Port is in UART mode are ignored.
When switching from UART mode to Pass-Thru mode, any data previously stored in the Receive FIFO is lost unless the
FIFO is enabled for Pass-Thru mode.
As in Pass-Thru mode, if a command is issued to the MIDI Port while the MIDI Communication Engine is in the middle of a
byte transfer, the execution of the command and the response are postponed until the ongoing byte transfer is completed.
The MIDI commands supported by the MIDI Port and their respective responses are listed in Table 50.
After each MIDI Port operation in UART mode, the MSTAT register is updated accordingly.
Table 50. MIDI Commands Supported by the MIDI Port
MIDI Port Response
Command
Pass-Thru Mode
UART Mode
Enter UART mode
FEh (Acknowledge)
3Fh
A0h-A7h, ABh
ACh
Ignored
FEh (Acknowledge)
00h
Ignored
Ignored
Ignored
Ignored
FEh (Acknowledge)
15h
FEh (Acknowledge)
01h
ADh
FEh (Acknowledge)
64h
AFh
MIDI Port Reset
FEh (Acknowledge)
Enter Pass-Thru Mode
MIDI Port Reset
FFh
Others
FEh (Acknowledge)
Ignored
10.2.7 MIDI Port Status Flags
The status of the various functional units of the MIDI Port is reflected by the MSTAT register. This register is functional in
both Pass-Thru and UART modes. Some of the status indications provided by the MSTAT register are not included in the
Legacy definition of the MIDI Port. These indications can be ignored if not required by the software.
The following status flags are included in the Legacy definition of the MIDI Port:
●
Receive Buffer Empty.
●
Transmit Buffer Full.
The Receive Buffer Empty flag is reflected by bit 7 of the MSTAT register. The Transmit Buffer Full flag is reflected by bit 6
of the MSTAT register. When operating in UART mode, these bits reflect the status of the Receive and Transmit FIFOs.
The Receive Buffer Empty status flag is also cleared to 0 when an acknowledge byte is put by the MIDI Port itself following
a MIDI command.
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
The values of these bits are set by the MIDI Port hardware and are not affected by reading the MSTAT register.
The following status indications are provided by the MIDI Port, although they are not included in the Legacy definition of the
MIDI Port:
●
Receive FIFO Full.
●
Transmit FIFO Empty.
●
Receive Overrun Error.
●
MIDI Port Operation Mode.
The Receive FIFO Full and Transmit FIFO Empty status flags are reflected by MSTAT register bits 5 and 2, respectively.
These bits are updated only when the MIDI Port operates in UART mode or when in Pass-Thru mode with the Receive FIFO
enabled. Otherwise, these bits are constantly cleared. The values of these bits are set by the MIDI Port hardware and are
not affected by reading the MSTAT register.
The Receive Overrun Error flag indicates that serial data was received by the MIDI Communication Engine while the Receive
Buffer of FIFO was full. This flag is reflected by bit 3 of the MSTAT register. It is updated in both Pass-Thru and UART modes.
When a Receive Overrun Event occurs, the data in the Receive Buffer/FIFO is kept and all incoming data is lost. Incoming
data will keep getting lost until there is room in the Receive Buffer/FIFO to accept it. The Receive Overrun Error status flag
is cleared when the MSTAT register is read.
The MIDI Port Operation Mode flag indicates whether the MIDI Port currently operates in Pass-Thru or UART mode. This
status flag is reflected by bit 4 of the MSTAT register. It can be used by software to keep track of the currently selected MIDI
Port operation mode.
10.2.8 MIDI Port Interrupts
The MIDI Port supports interrupt assertion in both Pass-Thru and UART modes in response to one or both of the following
events:
●
Receive Data Ready.
●
Transmit Buffer Empty.
The Receive Data Ready event refers to the case in which there is data to be read in the Receive Buffer/FIFO. An interrupt
request is asserted by the MIDI Port to indicate a Receive Data Ready event in one of the following cases:
• The MIDI Port is in Pass-Thru mode, and the Receive Buffer contains a data or acknowledge byte that has not been read
yet. In this case, the interrupt request is de-asserted once the Receive Buffer is read.
• The MIDI Port is in UART mode and the Receive FIFO contains eight or more data bytes that have not been read yet,
or it is in Pass-Thru mode with the Receive FIFO enabled. In this case, the interrupt request is de-asserted once the
Receive FIFO level drops below eight bytes.
• Either:
— The MIDI Port is in UART mode, the Receive FIFO contains less than eight data bytes that have not been read yet,
and no data was received by the Communication Engine, or
— The MIDI Port is in Pass-Thru mode with the Receive FIFO enabled, or
— A read occurs from the Receive FIFO during a timeout period of approximately 1.28 msec (the time it takes to transfer
4 bytes over the MIDI communication channel).
In this case, the interrupt request is de-asserted when either new data is received by the Communication Engine or data
is read from the Receive FIFO.
The Transmit Buffer Empty event refers to the case in which the Transmit Buffer/FIFO of the MIDI Port can still accept data
to transmit. An interrupt request is asserted by the MIDI Port to indicate a Transmit Buffer Empty event in one of the following
cases:
• The MIDI Port is in Pass-Thru mode and the Transmit Buffer is empty. In this case, the interrupt request is de-asserted
once a byte is written to the Transmit Buffer.
• The MIDI Port is in UART mode and the Transmit FIFO is empty. In this case, the interrupt request is de-asserted once
the Transmit FIFO is filled with at least three bytes.
After hardware reset, interrupts are asserted by the MIDI Port only in response to a Receive Data Ready event. Interrupt
assertion in response to Transmit Buffer Empty events can be enabled by setting writing 1 to bit 1 of the MCNTL register.
Interrupt assertion in response to Receive Data Ready events can be disabled by writing 0 to bit 3 of the MCNTL register.
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
10.2.9 Enhanced MIDI Port Features
The MIDI Port supports the following modes/operations, which are not part of the Legacy definition of the MIDI Port:
●
Transmit in Pass-Thru.
●
Loopback mode.
●
MIDI Thru.
●
MDTX pin masking.
Transmit in Pass-Thru. When the MIDI Port is operated in Pass-Thru mode, transmit is disabled by default. To enable it,
write 1 to bit 4 of the MCNTL register.
Loopback Mode. The MIDI serial data transmit signal is routed internally to the MIDI serial data receive signal. This causes
all the data transmitted by the MIDI Port to also be received. Loopback mode can be used as a mode for testing the MIDI
Port or its software. To enable it, write 1 to bit 7 of the MCNTL register.
MIDI Thru. The MIDI serial data receive signal is routed internally to the MIDI serial data transmit signal. This causes any
incoming stream of pulses received via the MDRX pin to be driven immediately on the MDTX pin. This feature allows the
MIDI Port to be connected as a link in a chain of several MIDI devices. In parallel to routing the MIDI receive signal to the
MIDI transmit signals, the incoming serial data is also received by the MIDI Port itself. To enable it, write 1 to bit 6 of the
MCNTL register.
MDTX Pin Masking. MDTX pin masking forces this pin to remain at a high level. This causes all transmit processes to occur
without physically driving the serial data via the MDTX pin. Writing 1 to bit 2 of the MCNTL register enables MDTX pin mask-
ing.
The above three features are handled by the MIDI Signals Routing Control Logic, which is illustrated in Figure 34.
Loopback
Mode
Enable
MIDI Thru
Enable
MDTX Pin
Masking
Enable
MIDI
Transmit
Signal
0
1
MDTX Pin
MDRX Pin
MIDI
Receive
Signal
1
0
Figure 34. MIDI Signals Routing Control Logic
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
10.3 MIDI PORT REGISTERS
The following abbreviations are used to indicate the Register Type:
●
R/W = Read/Write.
●
R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
●
W = Write.
●
RO = Read Only.
●
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
10.3.1 MIDI Port Register Map
The following table lists the MIDI Port registers. For the MIDI Port register bitmap, see Section 10.4.
Offset
Mnemonic
Register Name
Type
Section
00h
00h
01h
01h
02h
MDI
MIDI Data In
MIDI Data Out
R
W
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
MDO
MSTAT MIDI Status
MCOM MIDI Command
MCNTL MIDI Control
R
W
W/R
10.3.2 MIDI Data In Register (MDI)
This read register is used for reading data received by the MIDI Port and status information returned by the MIDI Port in
response to a previously issued command. When the FIFOs of the MIDI Port are enabled, reading from this offset returns
the next byte taken out of the Receive FIFO.
Location:
Type:
Offset 00h
R
Bit
7
6
5
4
3
2
1
0
Name
Reset
Data In
X
X
X
X
X
X
X
X
10.3.3 MIDI Data Out Register (MDO)
This write register is used for writing data to be transmitted by the MIDI Port. When the FIFOs of the MIDI Port are enabled,
writing to this offset puts the data byte into the Transmit FIFO.
Location:
Type:
Offset 00h
W
Bit
7
6
5
4
3
2
1
0
Name
Data Out
Reset
X
X
X
X
X
X
X
X
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
10.3.4 MIDI Status Register (MSTAT)
This read register provides status information regarding the functional blocks of the MIDI Port.
Location:
Type:
Offset 01h
R
Bit
7
6
5
4
3
2
1
0
0
0
Name
MIDI Port
Operation
Mode
Rx Buffer Tx Buffer
Empty
Rx FIFO
Full
Rx Overrun Tx FIFO Not
Reserved
Full
Error
Empty
Reset
1
0
0
0
0
0
Bit
Description
7
Rx Buffer Empty. When set to 1, it indicates that the Receive Buffer in Pass-Thru mode, or the FIFO in UART
mode, is empty. When set to 0, it indicates that the Receive Buffer or FIFO contain data that can be read via the
MDI register.
0: Not empty
1: Empty (default)
6
5
Tx Buffer Full. When set to 1, it indicates that the Transmit Buffer or FIFO cannot accept any more data. When
set to 0, it indicates that the Transmit Buffer or FIFO can accept more data written to the MDO register.
0: Not full (default)
1: Full
Rx FIFO Full. When set to 1, it indicates that the Receive FIFO cannot accept any more received data bytes.
When set to 0, it indicates that the Receive FIFO can accept more received data bytes. This bit is forced to 0
when the FIFOs are disabled.
0: Not full or disabled (default)
1: Full
4
3
MIDI Port Operation Mode. When set to 1, it indicates that the MIDI Port is currently operating in UART mode.
When set to 0, it indicates that the MIDI Port is currently operating in Pass-Thru (non-UART) mode.
0: Pass-Thru mode (default)
1: UART mode
Rx Overrun Error. This bit is cleared to 0 when the MSTAT register is read. An overrun error is defined as the
state in which one or more data bytes have been received by the MIDI Port while the Receive Buffer, or FIFO,
was full.
0: No overrun error (default)
1: Overrun error
2
Tx FIFO Not Empty. This bit is forced to 0 when the FIFOs are disabled.
0: Empty or disabled (default)
1: Not empty
1-0 Reserved.
10.3.5 MIDI Command Register (MCOM)
This write register is a port via which commands are issued by the host to the MIDI Port.
Location:
Type:
Offset 01h
W
Bit
7
6
5
4
3
2
1
0
Name
Command Byte
Reset
X
X
X
X
X
X
X
X
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
10.3.6 MIDI Control Register (MCNTL)
This register controls enhanced MIDI functions.
Location:
Type:
Offset 02h
R/W
Bit
7
6
5
4
3
2
1
0
Name
Rx Data
Ready
Interrupt
Enable
Tx Buffer
Empty
Interrupt
Enable
Rx FIFO
Enable for
Pass-Thru
Mode
Loopback
Mode
Enable
Pass-Thru
Transmit
Enable
MDTX Pin
Masking
Enable
MIDI Thru
Enable
Reserved
Reset
0
0
0
0
0
1
0
0
1
Required
Bit
Description
7
Loopback Mode Enable. When enabled, the MIDI receive signal is internally connected to the MIDI transmit
signal.
0: Disabled (default)
1: Enabled
6
MIDI Thru Enable. When enabled, the MDRX pin is internally connected to the MDTX pin, which then reflects
the MIDI receive signal. When disabled, the MDTX pin is driven with data coming from the MIDI Port transmit
engine.
0: Disabled (default)
1: Enabled
5
4
Reserved.
Pass-Thru Transmit Enable. When enabled, data is transmitted in Pass-Thru (non-UART) mode.
0: Disabled (default)
1: Enabled
3
2
1
0
Rx Data Ready Interrupt Enable. When enabled, an interrupt request is asserted in response to a Receive
Data Ready event.
0: Disabled
1: Enabled (default)
MDTX Pin Masking Enable. When enabled, the MDTX pin is constantly driven high by the MIDI Port. When
disabled, MDTX serves as the MIDI Port transmit line.
0: Disabled (default)
1: Enabled
Tx Buffer Empty Interrupt Enable. When enabled, an interrupt request is asserted in response to a Transmit
Buffer Empty event.
0: Disabled (default)
1: Enabled
Rx FIFO Enable for Pass-Thru Mode. When this bit is set to 1, the Receive FIFO is enabled in Pass-Thru
mode. This bit is ignored in UART mode.
0: Disabled
1: Enabled (default)
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10.0 Musical Instrument Digital Interface (MIDI) Port (Continued)
10.4 MIDI PORT BITMAP
Register
Bits
Offset
Mnemonic
MDI
7
6
5
4
3
2
1
0
00h
00h
Data In
MDO
Data Out
MIDI Port
Operation Overrun
Mode Error
Rx
Rx Buffer Tx Buffer Rx Buffer
Tx FIFO
Empty
01h
01h
MSTAT
MCOM
Reserved
Empty
Full
Full
Command Byte
Rx FIFO
Enablefor
Pass-
Thru
Mode
Pass-
Thru
Rx Data
Ready
MDTX
Pin
Tx Buffer
Empty
Loopback
Mode
Enable
MIDIThru
Enable
02h
MCNTL
Reserved
Transmit Interrupt Masking Interrupt
Enable Enable Enable Enable
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11.0 Voltage Level Monitor (VLM)
11.1 OVERVIEW
The Voltage Level Monitor (VLM) is an A/D converter that monitors various voltages in the system, reports their values to
system monitoring software and can set an alarm when any of these voltages is outside a specified range. The VLM con-
forms to LDCM and DMI requirements for system monitoring.
The VLM can sense up to 14 voltage values. Seven sources are external and can be applied per system requirements. Four
values are internal and used for VSB, VDD, VBAT and AVDD. VSB, VDD and AVDD are internally divided by 2 to allow detection
of voltage both over and under the specified range. TS1, TS2 and TS3 inputs are used for temperature measurement using
a thermistor.
The host can query the various voltage readout values and configure the VLM to generate an ALARM signal when the volt-
age is outside a specified range (below ViLOW or above ViHIGH, where i is the channel number). The ALARM can generate
an interrupt internally and/or output to a pin of the device.
11.2 FUNCTIONAL DESCRIPTION
The VLM incorporates an 8-bit A/D converter and a set of control, configuration and status registers and digital circuitry that
controls its operation. Figure illustrates the structure of the VLM module.
The VLM measures the various input voltages periodically, as defined by the conversion rate setting (see Section 11.5.9).
At the beginning of each period, a measurement trigger is issued, which starts a burst of conversion operations. The burst
includes scanning all enabled channels starting from channel 0.
To guarantee the stability of the signal at the input of the A/D converter, a delay is added between the end of each conversion
and the beginning of the next. The delay between samples should be adjusted according to the resistance and capacitance
of the input source. See Section 11.7.1 for information on how to calculate the sampling delay; see Section 11.5.9 for the
associated programing model.
The voltage readout is an unsigned integer between 0 and 255. Section 11.2.1 describes how the readout is converted to a
voltage value.
The VLM is designed to preserve indication of failures by disabling the conversion whenever the SLPS3 input becomes ac-
tive (i.e., VDD is expected to drop) and whenever an error is detected. The conversion and register updates resume only
after power is restored and normal system operation resumes. To prevent loss of error condition flagging, the conversions
for voltage measurement channels (0 through 10 only) that are out of range are stopped until the ALARM status is cleared.
Whenever SLPS3 is not available in the system, the SLPS3 input should be tied to 1 and the software should disable the
measurements before the power fails or ignore and clear any pending error flags after power is restored.
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11.0 Voltage Level Monitor (VLM) (Continued)
AVI0
AVI6
AD0
AD1
AD2
VLM
VIN0
VSB
Power
AD3
AD4
14:1
Analog
MUX
SIB
AD5
AD6
AD7
AD8
AD9
VSB
VDD
VBAT
A/D
Converter
VIN6
A/D Converter
Control Logic
AD10
AD11
AD12
AD13
AVDD
TS1
TS2
TS3
Status,
Data & Config
Registers
Start
Delay
VREF
Clock
Clock
Divider
*(2.45
±0.05)
REF
Internal
VREF
AVDD
AVss
Analog
Power
3.3V
ALARM
IRQ
+
+
To
Low
VLM
Config
}
SMI
High
ALERT
OTS
To
TMS
Config
+
IRQ
Overtemp
}
SMI
Figure 35. VLM Functional Diagram
11.2.1 Voltage Measurement, Channels 0 through 10
Voltage is measured relative to (2.45±0.05)*VREF (where VREF is the voltage of the VREF input or the internal reference volt-
age). The results are output to the Read Channel Voltage (RDCHV) register associated with the channel. The voltage mea-
sured is:
Vi = (2.45±0.05)*VREF *RDCHVi / 256
VSB, VDD and AVDD are internally divided by two. Therefore, the readouts are half their actual values. When external dividers
are used to scale input voltage to within the dynamic range of the A/D Converter, appropriate scale factors should be taken
into account.
VHIGH and VLOW Limits, ALARM Output, IRQ and SMI
The voltage reading is compared to two limits: VHIGH and VLOW. If the voltage reading is outside any of these limits, the
respective status bit (Channel High Limit Exceeded or Channel Low Limit Exceeded) in the VCHCFST register is set. The
status bit stays active until it is cleared by the software. An ALARM status bit in the VEVSTS0 or VEVSTS1 register is set
when the Channel High Limit Exceeded or the Channel Low Limit Exceeded bit for the respective channel is set.
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11.0 Voltage Level Monitor (VLM) (Continued)
The ALARM output is used to indicate to the system that a voltage outside the high/low limits was detected. The ALARM
output Enable bit in the VCHCFST register enables the ALARM output to be active when the Channel High Limit Exceeded
or the Channel Low Limit Exceeded status bit in the VCHCFST register is set.
The SMI output generates an interrupt if any enabled SMI event occurs. Each bit in the VEVSTS0/1 register has a corre-
sponding SMI Enable bit in the VEVSMI0/1 register. When any status bit and its corresponding SMI Enable bit are set, the
SMI output is active.
The IRQ output generates an interrupt if any enabled IRQ event occurs. Each bit in the VEVSTS0/1 register has a corre-
sponding IRQ Enable bit in the VEVIRQ0/1 register. When any status bit and its corresponding IRQ Enable bit are set, the
IRQ output is active.
Alarm Response Read Sequence
When the VLM activates the ALARM output, the host should respond by reading the VEVSTS0 and VEVSTS1 registers. It
should then access the register of each of the channels whose bit is set in the VEVSTS0 and VEVSTS1 registers and clear
these bits by writing 1 to each of them.
11.2.2 Thermistor-Based Temperature Measurement, Channels 11 to 13
The VLM module can measure environmental temperature by using thermistors. This feature is supported over channels 11
to 13. The temperature measurement under this scheme is based on a voltage divider between AVDD and AVSS where one
of the two resistors is a thermistor. See Figure 36.
AVDD
AVDD
R
PTS
TSi
TSi
NTS
AVSS
R
AVSS
Figure 36. Measuring Temperature Using Thermistors
The translation of voltage to temperature is determined by the parameters of the thermistor in use. The values in the registers
with the results and limits are defined by the result of the voltage measurement. For the channels that support temperature
measurement, standard temperature monitoring functions are provided: low- and high-temperature ALERT and overtemper-
ature shutdown.
11.2.3
VOS, VHIGH and VLOW Limits, OTS and ALERT Output, IRQ and SMI
The voltage reading is compared to three limits: VOS, VHIGH and VLOW. If the voltage reading is outside any of these limits,
the respective status bit (Channel Overtemperature Limit Exceeded, Channel High Limit Exceeded or the Channel Low Limit
Exceeded) in the VCHCFST register is set. The status bit will stay active until it is cleared by the software. An ALERT status
bit in the VEVSTS0/1 register is set when the Channel High Limit Exceeded, the Channel Low Limit Exceeded or the Over-
temperature Event bit for the respective channel is set.
The OTS output is used to indicate to the system that the overtemperature limit has been exceeded. The OTS Output Enable
bit in the VCHCFST register enables the OTS output to be active when the OTS status of the channel is active.
The ALERT output is used to indicate to the system that the current temperature is outside the high/low limits. The ALERT
output Enable bit in the VTCHCFST register enables the ALERT output to be active when the Channel High Limit Exceeded
or the Channel Low Limit Exceeded status bit in the VCHCFST register is set. [The ALERT signal is not connected in the
365 and 366.]
The SMI output generates an interrupt if any enabled SMI event occurs. Each bit in the VEVSTS1 register has a correspond-
ing SMI Enable bit in the VEVSMI1 register. When any status bit and its corresponding SMI Enable bit are set, the SMI output
is active.
The IRQ output generates an interrupt if any enabled IRQ event occurs. Each bit in the VEVSTS1 register has a correspond-
ing IRQ Enable bit in the VEVIRQ1 register. When any status bit and its corresponding IRQ Enable bit are set, the IRQ output
is active.
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11.0 Voltage Level Monitor (VLM) (Continued)
ALERT Response Read Sequence
When the VLM activates its ALERT output, the host should respond by reading the VEVSTS0 and VEVSTS1 registers. It
should then access the register of each of the channels that has its respective bit set and clear the HIGHV and LOWV status
bits by writing 1 to each of them.
11.2.4 Power-On Reset Default States
VLM power-on default conditions are:
• All registers are loaded with their default values.
• The ALARM output, IRQ and SMI are disabled.
11.2.5 Standby Mode
Standby mode is enabled by setting the Standby Mode Enable bit in the VLMCFG register. Standby mode reduces power
supply current by disabling new measurements, but register values are retained and the registers can be accessed by soft-
ware (as usual).
11.3 ANALOG SUPPLY CONNECTION
11.3.1 Recommendations
Power is supplied to the analog parts of the A/D Converter through two dedicated analog power pins: AVDD and AVSS. This
ensures effective isolation of the analog parts from noise caused by the digital parts. The digital parts of the VLM are supplied
via VSB. To obtain the best performance, bear in mind the following recommendations (see also details in Figure 37).
Ground Connection. The analog ground pin, AVSS, should be connected at only one point to the digital ground pins. At this
point, the following ground connections should also be made:
• The decoupling capacitors of the analog supply AVDD pin.
• The reference voltage VREF pin.
• The four digital supply VSB pins.
• The ground reference of the input signals to the A/D Converter.
Low-impedance ground layers also improve noise isolation.
Power Connection. The analog supply pin, AVDD, should be connected to a low-noise power supply, 3.3V. It is recom-
mended to supply the AVDD pin through an external LC or RC filter. An example of an RC filter [R1 and (C2+C3)] is shown
in Figure 37.
Decoupling Capacitors. The following decoupling capacitors should be used:
• Digital VSB: Place one capacitor of 0.1 µF on each VSB pin as close as possible to the pin (4 x C4). Also, place one 10-
47 µF tantalum capacitor (C5) on the common net as close as possible to the chip.
• Analog AVDD: Place a 0.1 µF capacitor and a 10-47 µF tantalum capacitor on the AVDD pins (C3 and C2) as close as
possible to the pin.
• VREF: Place a low-leakage, non-polarized, 0.47 µF capacitor (C1) as close as possible to the VREF pin.
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11.0 Voltage Level Monitor (VLM) (Continued)
Analog
Power
Power
Supply
R1 10 Ω
3.3 V
AD0
AD6
AD0
AD6
VIN
V
REF
V
REF
VREF
C1
0.47
µF
AV
AV
V
DD
SB
+
C5
+
22
µF
GND
SS
C4
0.1
µF
0.1
µF
C3
22
µF
C2
Analog Ground Layer
Digital Ground Layer
Figure 37. Analog Power Supply
11.3.2 Reference Voltage
Analog input voltage is measured relative to (2.45±0.05)*VREF. VREF may be either internal or external. When an internal
REF is used, a capacitor should be connected between the VREF pin and AVSS. The VREF default setting is for external.
This default prevents contention between the internal and external VREF
V
.
Note that the VREF setting is common to both the VLM and the TMS modules. If either of these modules is configured to use
internal reference voltage, the internal reference voltage is used by both modules.
11.4 REGISTER BANK OVERVIEW
The VLM uses register banks to enable host access to its registers. The VLM has 10 common registers in addition to five
registers that are located in each of the 13 banks. The common registers include configuration and status information com-
mon to all the channels. Each of the banks is associated with one channel and holds its readout, configuration and status
information. All registers use the same 16-byte address space to indicate offsets 00h through 0Fh. The active bank must be
selected by the software.
The VLM Bank Selection (VLMBS) register, which is common to all banks, selects the active banks (see Figure 38). The
default bank selection after system reset is 0.
Common
Registers
for
All Banks
Offset 00h
.
}
.
.
Offset 08h
VLMBS (09h)
Offset 0Ah
Offset 0Bh
BANK 13
Offset 0Eh
Offset 0Fh
BANK 1
BANK 0
Figure 38. Register Bank Architecture
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11.0 Voltage Level Monitor (VLM) (Continued)
11.5 VLM REGISTERS
The register maps in this chapter use the following abbreviations for Type:
• R/W = Read/Write.
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write.
• RO = Read Only.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
11.5.1 VLM Register Map
Table 51. VLM Control and Status Register Map
Offset Mnemonic
Register Name
Voltage Event Status 0
Type
Section
00h VEVSTS0
01h VEVSTS1
02h VEVSMI0
03h VEVSMI1
04h VEVIRQ0
05h VEVIRQ1
06h VID
RO
RO
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.8
11.5.9
11.5.10
11.5.11
Voltage Event Status 1
Voltage Event to SMI 0
Voltage Event to SMI 1
Voltage Event to IRQ 0
Voltage Event to IRQ 1
Voltage ID
R/W
R/W
R/W
R/W
Varies per bit
R/W
07h VCNVR
08h VLMCFG
09h VLMBS
Voltage Conversion Rate
VLM Configuration
R/W
VLM Bank Select
R/W
Table 52. VLM Channel Register Map (One per Channel)
Offset Mnemonic
Register Name
Type
Section
0Ah VCHCFST
0Bh RDCHV
0Ch CHVH
Voltage Channel Configuration and Status
Read Channel Voltage
Varies per bit
RO
11.5.12
11.5.13
11.5.14
11.5.15
11.5.16
Channel Voltage High Limit
R/W
0Dh CHVL
Channel Voltage Low Limit
R/W
0Eh OTSL
Overtemperature Shutdown Limit
R/W
0Fh Reserved
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11.0 Voltage Level Monitor (VLM) (Continued)
11.5.2 Voltage Event Status Register 0 (VEVSTS0)
This register indicates which of the corresponding eight VLM events has occurred.
Location:
Type:
Offset 00h
RO
Bit
7
6
5
4
3
2
1
0
VSB
ALARM
Event
AVI6
ALARM
Event
AVI5
ALARM
Event
AVI4
ALARM
Event
AVI3
ALARM
Event
AVI2
ALARM
Event
AVI1
ALARM
Event
AVI0
ALARM
Event
Name
Reset
Status
Status
Status
Status
Status
Status
Status
Status
0
0
0
0
0
0
0
0
Bit
Description
7
VSB ALARM Event Status. This channel measures the internal VSB power, using VSB/2.
0: Voltage level within limits (default)
1: High or low limit exceeded
6-0 Analog Voltage Inputs 6-0 ALARM Event Status.
0: Voltage level within limits (default)
1: High or low limit exceeded
11.5.3 Voltage Event Status Register 1 (VEVSTS1)
This register indicates which of the corresponding VLM events has occurred.
Location:
Type:
Offset 01h
RO
Bit
7
6
0
5
4
3
2
1
0
AVDD
TMS3
TMS2
TMS1
VBAT
ALARM
Event
VDD
ALARM
Event
ALERT or ALERT or ALERT or
OTS Event OTS Event OTS Event
Status
ALARM
Event
Status
Name
Reset
Reserved
Status
Status
Status
Status
0
0
0
0
0
0
0
Bit
Description
7-6 Reserved.
5
4
3
TMS3 ALERT or OTS Event Status.
0: Voltage level within limits (default)
1: OTS, high or low limit exceeded
TMS2 ALERT or OTS Event Status.
0: Voltage level within limits (default)
1: OTS, High or low limit exceeded
TMS1 ALERT or OTS Event Status.
0: Voltage level within limits (default)
1: OTS, High or low limit exceeded
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11.0 Voltage Level Monitor (VLM) (Continued)
Bit
Description
2
AVDD ALARM Event Status. This channel measures the internal AVDD power, using AVDD/2.
0: Voltage level within limits (default)
1: High or low limit exceeded
1
0
VBAT ALARM Event Status. This channel measures the VBAT power input.
0: Voltage level within limits (default)
1: High or low limit exceeded
VDD ALARM Event Status. This channel measures the internal VDD power, using VDD/2.
0: Voltage level within limits (default)
1: High or low limit exceeded
11.5.4 Voltage Event to SMI Register 0 (VEVSMI0)
This register is one of two registers that controls event routing to SMI.
Location:
Type:
Offset 02h
R/W
Bit
7
6
5
4
3
2
1
0
VSB Event AVI6 Event AVI5 Event AVI4 Event AVI3 Event AVI2 Event AVI1 Event AVI0 Event
Name
Reset
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
0
0
0
0
0
0
0
0
Bit
Description
7
VSB Event to SMI Enable.
0: Disabled (default)
1: Enabled
6-0 AVI6-0 Event to SMI Enable.
0: Disabled (default)
1: Enabled
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11.0 Voltage Level Monitor (VLM) (Continued)
11.5.5 Voltage Event to SMI Register 1 (VEVSMI1)
This register is one of two registers that controls event routing to SMI.
Location:
Type:
Offset 03h
R/W
Bit
7
6
0
5
4
3
2
1
0
AVDD Event
VBAT Event VDD Event
to SMI
Enable
TMS3
Event to
TMS2
Event to
TMS1
Event to
Name
Reset
Reserved
to SMI
Enable
to SMI
Enable
SMI Enable SMI Enable SMI Enable
0
0
0
0
0
0
0
Bit
Description
7-6 Reserved.
5
4
3
2
TMS3 Event to SMI Enable.
0: Disabled (default)
1: Enabled
TMS2 Event to SMI Enable.
0: Disabled (default)
1: Enabled
TMS1 Event to SMI Enable.
0: Disabled (default)
1: Enabled
AVDD Event to SMI Enable.
0: Disabled (default)
1: Enabled
1
0
VBAT Event to SMI Enable.
0: Disabled (default)
1: Enabled
VDD Event to SMI Enable.
0: Disabled (default)
1: Enabled
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11.0 Voltage Level Monitor (VLM) (Continued)
11.5.6 Voltage Event to IRQ Register 0 (VEVIRQ0)
This register is one of two registers that controls event routing to IRQ.
Location:
Type:
Offset 04h
R/W
Bit
7
6
5
4
3
2
1
0
VSB Event AVI6 Event AVI5 Event AVI4 Event AVI3 Event AVI2 Event AVI1 Event AVI0 Event
Name
Reset
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
0
0
0
0
0
0
0
0
Bit
Description
7
VSB Event to IRQ Enable.
0: Disabled (default)
1: Enabled
6-0 AVI6-0 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
11.5.7 Voltage Event to IRQ Register 1 (VEVIRQ1)
This register is one of two registers that controls routing to IRQ.
Location:
Type:
Offset 05h
R/W
Bit
7
6
0
5
4
3
2
1
0
AVDD Event
TMS3
Event to
TMS2
Event to
TMS1
Event to
VBAT Event VDD Event
Name
Reset
Reserved
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
IRQ Enable IRQ Enable IRQ Enable
0
0
0
0
0
0
0
Bit
Description
7-6 Reserved.
5
4
3
TMS3 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
TMS2 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
TMS1 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
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11.0 Voltage Level Monitor (VLM) (Continued)
Bit
Description
2
AVDD Event to IRQ Enable.
0: Disabled (default)
1: Enabled
1
0
VBAT Event to IRQ Enable.
0: Disabled (default)
1: Enabled
VDD Event to IRQ Enable.
0: Disabled (default)
1: Enabled
11.5.8 Voltage ID Register (VID)
This register indicates the configuration of the power supply regulator for the CPU(s).
Location:
Type:
Offset 06h
Varies per bit
Bit
7
6
5
Reserved
0
4
3
2
VID Value
X
1
0
Name
Reset
CPU VID Select
0
0
X
X
X
X
Bit Type
Description
7-6 R/W CPU Voltage ID Select. This field selects which of the CPUs’ VID pins is read in the Voltage ID Value
field.
Bits
7 6 Voltage ID
0 0
0 1
CPU0 (default)
CPU1
Other Reserved
5
Reserved.
4-0 RO Voltage ID Value. Returns the current value of the VID inputs selected by the CPU VID Select field. The
pins used for the VID field are defined by VID0 and VID1 Route Select bits of the SuperI/O Configuration
5 register (See Section 2.8.6).
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11.0 Voltage Level Monitor (VLM) (Continued)
11.5.9 Voltage Conversion Rate Register (VCNVR)
This register indicates time related specification for the VLM.
Location:
Type:
Offset 07h
R/W
Bit
7
6
0
5
0
4
3
0
2
0
1
0
0
Name
Reset
Reserved
Channel Delay
Conversion Period
0
0
0
Bit
Description
7-6 Reserved.
5-3 Channel Delay. These bits define the sampling delay. The sampling delay helps guarantee the accuracy
of the sampled value when switching from one channel to another.
Bits
5 4 3 Delay (µsec)
0 0 0 40 (default)
0 0 1 80
0 1 0 160
Others Reserved
2-0 Conversion Period. These bits define the period of time between reconversions of all enabled channels.
VBAT (channel 9) is converted at the first of every 1024 conversion periods.
Bits
2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
Others
Conversion Period
2 seconds (default)
1 second
0.5 seconds
0.1 seconds
0.05 seconds
0.02 seconds
Reserved
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11.0 Voltage Level Monitor (VLM) (Continued)
11.5.10 VLM Configuration Register (VLMCFG)
This register selects the channels and sets global configuration (not channel specific) values.
Location:
Type:
Offset 08h
R/W
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Standby
Mode
Enable
External
VREF
Name
Reset
Reserved
1
1
Bit
Description
7-2 Reserved.
1
External VREF.
This bit selects either the internal or external reference voltage as a reference for the A/D Converter. Note
that if either the VLM or TMS specify the use of an internal VREF, the internal VREF will be used by both
these modules.
0: Internal VREF in use
1: External VREF in use (default)
0
Standby Mode Enable.
0: Monitoring operation enabled
1 Standby mode enabled (default)
11.5.11 VLM Bank Select Register (VLMBS)
This register selects a bank and its associated channels.
Location:
Type:
Offset 09h
R/W
Bit
7
6
Reserved
0
5
0
4
0
3
0
2
1
0
0
0
Name
Reset
Bank Select Value
0
0
Bit
Description
7-5 Reserved.
4-0 Bank Select Value. These bits contain the binary value that selects a bank and its associated channels
for configuration and viewing.
4 3 2 1 0 Bank Function
0 0 0 0 0
0 0 0 0 1
......
0
1
Channel 0 (default)
Channel 1
0 1 0 1 0 10
0 1 0 1 1 11
......
Channel 10
Channel 11 - Temperature
0 1 1 0 1 13
Other
Channel 13 - Temperature
Reserved
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11.0 Voltage Level Monitor (VLM) (Continued)
11.5.12 Voltage Channel Configuration and Status Register (VCHCFST)
This register indicates the current channel status.
Location:
Type:
Offset 0Ah - Banks 0 through 10
Varies per bit
Bit
7
6
5
0
4
3
2
1
0
ALARM
Output
Enable
Channel
Channel
End of
Conversion
Channel
Enable
Name
Reset
Reserved
Reserved High Limit Low Limit
Exceeded Exceeded
0
0
0
0
0
0
0
Location:
Type:
Offset 0Ah - Bank 11 through 13
Varies per bit
Bit
7
6
5
0
4
3
2
1
0
Channel
Overtemp
Limit
ALARM
Output
Enable
Channel
High Limit Low Limit
Exceeded Exceeded
Channel
End of
Conversion
Channel
Enable
Name
Reset
Reserved
Exceeded
0
0
0
0
0
0
0
Bit
Type
Description
7
RW1C End of Conversion. This bit indicates that the RDCHV register (see next page) holds new data. It is set
when new data is written into RDCHV as a result of completing a conversion for this channel. It is
cleared by writing 1 to this bit.
0: No new data (default)
1: New data not yet read
6-5
4
Reserved.
R/W ALARM Output Enable.
0: Disabled (default)
1: Enabled
3
2
1
0
RW1C Channel Overtemperature Limit Exceeded. Banks 11 through 13.
0: Voltage read, indicating overtemperature limit exceeded (default)
1: OTS signal set, indicating overtemperature limit exceeded
RW1C Channel High Limit Exceeded.
0: Voltage lower than limit (default)
1: Voltage higher than limit
RW1C Channel Low Limit Exceeded.
0: Voltage higher than limit (default)
1: Voltage lower than limit
R/W Channel Enable.
0: Disabled (default)
1: Enabled
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11.0 Voltage Level Monitor (VLM) (Continued)
11.5.13 Read Channel Voltage Register (RDCHV)
This register holds the last voltage readout for each channel. The value is an 8-bit unsigned integer of the voltage measured
by the channel.
Location:
Type:
Offset 0Bh - Banks 0 to 13
RO
Bit
7
6
5
0
4
3
2
0
1
0
0
0
Name
Reset
Channel Voltage Value
0
0
0
0
11.5.14 Channel Voltage High Limit Register (CHVH)
This register holds the voltage high limit value that is compared with the voltage reading.
Location:
Type:
Offset 0Ch - Banks 0 through 13
R/W
Bit
7
6
5
1
4
3
2
1
1
1
0
1
Name
Reset
Channel Voltage High Limit Value
1
1
1
1
11.5.15 Channel Voltage Low Limit Register (CHVL)
This register holds the voltage low limit value that is compared with the voltage reading.
Location:
Type:
Offset 0Dh - Banks 0 through 13
R/W
Bit
7
6
5
0
4
3
2
0
1
0
0
0
Name
Reset
Channel Voltage Low Limit Value
0
0
0
0
11.5.16 Overtemperature Shutdown Limit Register (OTSL)
This register defines the overtemperature shutdown limit for banks 11 to 13. Its power-up default is the maximum voltage
readout.
Location:
Type:
Offset 0Eh Banks 11 to 13
R/W
Bit
7
6
5
4
3
2
1
1
0
1
Name
Reset
Overtemperature Shutdown Limit Value
1
1
1
1
1
1
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11.0 Voltage Level Monitor (VLM) (Continued)
11.6 VLM REGISTER BITMAP
11.6.1 VLM Control and Status Registers
Register
Bits
Offset Mnemonic
7
6
5
4
3
2
1
0
VSB
ALARM
Event
AVI6
ALARM
Event
AVI5
ALARM
Event
AVI4
ALARM
Event
AVI3
ALARM
Event
AVI2
ALARM
Event
AVI1
ALARM
Event
AVI0
ALARM
Event
00h
VEVSTS0
Status
Status
Status
Status
Status
Status
Status
Status
AVDD
TMS3
TMS2
TMS1
VBAT
ALARM
Event
VDD
ALARM
Event
ALERT or ALERT or ALERT or
OTS Event OTS Event OTS Event
ALARM
Event
01h
02h
03h
04h
05h
VEVSTS1
VEVSMI0
VEVSMI1
VEVIRQ0
VEVIRQ1
Reserved
Status
Status
Status
Status
Status
Status
VSB Event AVI6 Event AVI5 Event AVI4 Event AVI3 Event AVI2 Event AVI1 Event AVI0 Event
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
to SMI
Enable
AVDD
TMS3
Event to
SMI
TMS2
Event to
SMI
TMS1
Event to
SMI
VBAT
Event to
SMI
VDD Event
to SMI
Enable
Event to
SMI
Enable
Reserved
Enable
Enable
Enable
Enable
VSB Event AVI6 Event AVI5 Event AVI4 Event AVI3 Event AVI2 Event AVI1 Event AVI0 Event
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
to IRQ
Enable
AVDD
TMS3
Event to
IRQ
TMS2
Event to
IRQ
TMS1
Event to
IRQ
VBAT
Event to
IRQ
VDD Event
to IRQ
Enable
Event to
IRQ
Enable
Reserved
Enable
Enable
Enable
Enable
06h
07h
VID
CPU VID Select
Reserved
Reserved
VID Value
VCNVR
Channel Delay
Conversion Period
Standby
Mode En-
able
External
VREF
08h
09h
VLMCFG
VLMBS
Reserved
Reserved
Bank Select Value
11.6.2 VLM Channel Registers
Register
Bits
Offset Mnemonic
7
6
5
4
3
2
1
0
ALARM
Output
Enable
Channel
Channel
0Ah
End of
Conversion
Channel
Enable
(Bank VCHCFST
0-10)
Reserved
Reserved High Limit Low Limit
Exceeded Exceeded
Channel
Overtemp
Limit
ALARM
Output
Enable
Channel
High Limit Low Limit
Exceeded Exceeded
Channel
0Ah
End of
Conversion
Channel
Enable
(Bank VCHCFST
11-13)
Reserved
Exceeded
0Bh
(Bank
0-13)
RDCHV
Channel Voltage Value
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11.0 Voltage Level Monitor (VLM) (Continued)
Register
Bits
0Ch
(Bank
0-13)
CHVH
CHVL
OTSL
Channel Voltage High Limit Value
Channel Voltage Low Limit Value
0Dh
(Bank
0-13)
0Eh
(Bank
11-13)
Overtemperature Shutdown Limit Value
Reserved
0Fh
11.7 USAGE HINTS
11.7.1 Calculating the Channel Delay
The channel delay is the interval between the time a new channel is selected and the time the channel voltage can be mea-
sured. The reason for this delay is to allow the voltage to charge all internal capacitors to guarantee accuracy of the mea-
surement. This delay period depends on characteristics of the input (resistance and capacitance) and of the external circuit.
Figure 39 shows the schematic of the input and its equivalent R-C circuit. The sampling time should be long enough to guar-
antee that the voltage settles on the capacitor CS. The voltage on CS should be stable before the measurement starts. The
R
AIN and CAIN values represent the input path serial resistance and parallel capacitance. RAIN is the serial resistance of the
multiplexer, Sample & Hold switch and other parasitic resistors. CAIN is the parallel capacitance of the input pin, pad, lead-
frame, CS, etc. The required sampling time is determined by RAIN and CAIN together with the input source resistance
R
SOURCE and parasitic capacitance CP. Table 53 can be used as a reference for calculating the sample time. Channel Delay
of the VCNVR register should be programmed accordingly.
RSOURCE
CP is the parasitic capacitor including the external
elements (PCB capacitance etc.).
AD0
AD1
AD2
AD3
AD4
AD5
AD6
VIN
R
AIN is the equivalent serial resistance of all serial
elements inside the chip (pin, bonding, MUX, Sample &
Hold switch, layout).
Analog
MUX
Input
Signal
CS is the sampling capacitor.
Cs
CAIN is the equivalent parallel capacitance of the chip
parasitic capacitances and the CS capacitor.
RSOURCE
RAIN
CAIN
VIN
CP
Figure 39. Analog Input Schematic Diagram and Equivalent R-C Circuit
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11.0 Voltage Level Monitor (VLM) (Continued)
Table 53. Delay Setting Example
External
Elements
Delay Time
(ns)
R
C
P
SOURCE
[KΩ]
[pF]
5
0.1
1
15
110
10
30
0.1
1
900
3200
25
27.5
210
10
30
0.1
1
2220
7900
45
50
430
10
30
3350
11400
11.7.2 Measuring Out of Range Positive and Negative Voltages
Only voltages within the range of 0V to (2.45±0.05)*VREF can be measured by the module. To measure voltages out of this
range, any of the external measurement pins can be used with the addition of external resistors that should be used as volt-
age dividers. (See Figure 40.)
VIN (12V)
AVDD
R1
R1
AVI
AVI
R2
R2
AVSS
VIN (-12V)
AVSS
Figure 40. Measurement Out of Positive and Negative Voltages
11.7.3 Obtaining the Specified VLM/TMS Accuracy
To obtain the specified VLM/TMS accuracy, see Section 12.5.5 on page 208:
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12.0 Temperature Sensor (TMS)
12.1 OVERVIEW
The Temperature Sensor (TMS) is a diode input temperature sensor that consists of a Delta-Sigma Analog to Digital (A/D)
converter and a digital overtemperature detector. Both of these elements conform to Advance Configuration and Power In-
terface (ACPI) requirements for thermal management.
The TMS senses its own temperature and the temperature of two target ICs by measuring the voltage drop of diode(s)
placed on the target IC’s die. A host can query the TMS at any time to read the temperature of the remote diode(s) in addition
to the local temperature. An ALERT interrupt output becomes active when the temperature goes above THIGH or below
T
LOW. The host may program the two thresholds for each sensing channel to define an operation window. Overtemperature
Shutdown (OTS) output becomes active when the temperature exceeds the programmable limit TOS
.
12.2 FUNCTIONAL DESCRIPTION
The TMS incorporates a band-gap temperature sensor using a local and remote diode(s) and an 8-bit Delta-Sigma Analog-
to-Digital Converter (A/D converter). Once enabled and put in active (non-standby mode), the TMS continuously measures
temperature of up to one internal diode and two remote diodes. TMS readings are available at all times via the host interface.
When SLPS3 input becomes inactive, the conversion is stopped and no new results are generated until both SLPS3 be-
comes active and the internal wake up sequence is completed. TMS registers are maintained by VSB during this period.
A digital comparator is also incorporated to compare temperature readings to user-programmable limits. OTS output indi-
cates that the result of the comparison exceeds the limit preset in the Channel Overtemperature Limit register. ALERT output
indicates that the result of the comparison is not within limits preset in the Channel Temperature High or Low Limit (CHTH
and CHTL) registers.
Figure 41 shows a simplified block diagram of the TMS. It represents only the local diode and one remote diode (even though
there are actually two remote diodes in addition to the local diode and one or three OTS signals, one for each diode sensor
or combined).
TMS Module
VSB
VDD
VSS
8-Bit
Temperature
Sensor
Overtemp
High
∆−Σ
ALERT
A/D Converter
Circuitry
Enable
and
Config
Logic
OTS
IRQ
To
TMS
Config
DPi
DNi
}
Low
Diode
SMI
Selector
High and
Low Limit
Setpoints
Enable
Bits
Overtemp.
Shutdown
Setpoint
Control
Logic
Conversion Temperature
Rate Readout
Figure 41. TMS Simplified Block Diagram
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12.0 Temperature Sensor (TMS) (Continued)
12.2.1 Register Bank Overview
Three register banks control TMS operation. The first part of each bank is a set of registers common to all banks. The second
part of each bank contains registers which are specific to that bank. All registers use the same 16-byte address space to
indicate offsets 00h through 0Fh. The software selects the currently active bank using the Bank Select register (TMSBS) —
see Figure 42. Bank 0 is selected after reset.
Common
Registers
for
All Banks
Offset 00h
.
.
}
.
Offset 08h
TMSBS (09h)
Offset 0Ah
.
.
.
BANK 2
Offset 0Eh
BANK 1
BANK 0
Figure 42. Register Bank Architecture
12.2.2 TOS, THIGH and TLOW Limits, OTS and ALERT Output, IRQ and SMI
The temperature reading is compared to three limits: TOS, THIGH and TLOW. If the temperature reading is outside any of
these limits, the respective status bit (Channel Overtemperature Limit Exceeded, Channel Temp High Limit Exceeded or
Channel Temp Low Limit Exceeded) in the TCHCFST register is set. The status bit stays active until it is cleared by the soft-
ware. An ALERT status bit in the TEVSTS register is set when the Channel Temp High Limit Exceeded or Channel Temp
Low Limit Exceeded bit for the respective channel is set. The channel’s Overtemperature Event status in the TEVSTS reg-
ister is set when the Channel Overtemperature Limit Exceeded bit is set.
The OTS output is used to indicate to the system that the overtemperature limit has been exceeded. The OTS Output Enable
bit in the TCHCFST register enables the OTS output to be active when the OTS status of the channel is active.
The ALERT output is used to indicate to the system that the current temperature is outside the high/low limits. The ALERT
output Enable bit in the TCHCFST register enables the ALERT output to be active when the Channel Temp High Limit Ex-
ceeded or the Channel Temp Low Limit Exceeded status bit in TCHCFST register is set.
The SMI output generates an interrupt if any enabled SMI event occurs. Each bit in the TEVSTS register has a correspond-
ing SMI Enable bit in the TEVSMI register. When any status bit and its corresponding SMI Enable bit are set, the SMI output
is active.
The IRQ output generates an interrupt if any enabled IRQ event occurs. Each bit in the TEVSTS register has a correspond-
ing IRQ Enable bit in the TEVIRQ register. When any status bit and its corresponding IRQ Enable bit are set, the IRQ output
is active.
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12.0 Temperature Sensor (TMS) (Continued)
THIGH
TOS1
TLOW
TOS2
ALERT
OTS
Indicates when temperature is sampled by the A/D Converter.
Indicates when temperature is sampled by the A/D Converter.
b: OTS Signal
a: ALERT Signal
TOS1
THIGH1
TLOW1
TOS2
THIGH2
TLOW2
ALERT
OTS
Indicates when temperature is sampled by the A/D Converter.
c: Combined ALERT and OTS Signals
Figure 43. OTS and ALERT Temperature Response Diagrams
12.2.3 ALERT Response Read Sequence
The Read Channel Temperature register (RDCHT) holds the temperature value most recently read from the channel. The
Temperature Event Status register (TEVSTS) indicates any ALERT detected as long as VSB is maintained. ALERTs are
cleared by software.
When an IRQ or SMI is received, check the TEVSTS register to see which of the sensors detected an out-of-limit readout,
access the channel readouts, read the current value and status information and clear any pending status bits.
12.2.4 Power-On Reset Default States
TMS always powers up in a known state. TMS power-up default conditions are:
1. Local temperature set to 0°C.
2. Remote temperature set to 0°C until the TMS senses a diode present on D+ and D- input pins.
3. Status register set to 00h.
4. Command register set to 00h; ALERT and OTS enabled and Standby mode deactivated.
5. Local and Remote TOS set to 127°C.
6. Local and Remote THIGH set to 127°C.
7. Local and Remote TLOW set to -55°C.
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12.0 Temperature Sensor (TMS) (Continued)
12.2.5 Temperature Data Format
Temperature data is stored in the RDCHT, CHTH, CHTL and CHOTL registers as an 8-bit, 2’s complement word with a Least
Significant Bit (LSB) equal to 1° C.
Table 54. Temperature Formats
Digital Output
Temperature
(°C)
Binary
Hex
+125
+25
+1
0111 1101
0001 1001
0000 0001
0000 0000
1111 1111
1110 0111
7Dh
19h
01h
00h
FFh
E7h
0
-1
-25
0111,1101
+25°C
+1°C
0001,1001
0000,0001
Temperature
0000,0000
0°C
1111,1111
+125°C
-55°C
1110,0111
1100,1001
-1°C
-25°C
Figure 44. Temperature-to-Digital Transfer Function (Non-linear scale for clarity)
12.2.6 Standby Mode
Standby mode is enabled by setting the Standby Mode bit in the TMSCFG register to 1 (default). Standby mode disables
the conversion process to reduce power supply current. During standby mode, all registers retain their values and can be
accessed by software (as usual).
12.2.7 Diode Fault Detection
At the beginning of each conversion, the TMS goes through a diode fault detection sequence. If the DxP input is shorted to VDD
or floating, the temperature reading will be +127° C and the Open bit of the TCHCFST register is set, which activates the
ALERT and OTS outputs on completion of a conversion. If DxP is shorted to GND or DxN, the temperature reading is O° C
and the Temperature Low Limit bit of the TCHCFST register is not set.
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12.0 Temperature Sensor (TMS) (Continued)
12.3 TMS REGISTERS
The TMS registers are divided into two groups: TMS Control and Status registers and TMS channel registers. The TMS
channel registers are duplicated for each channel.
The register maps in this chapter use the following abbreviations for Type:
• R/W = Read/Write.
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write.
• RO = Read Only.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
12.3.1 TMS Register Map
Table 55. TMS Control and Status Register Map
Offset Mnemonic
Register Name
Temperature Event Status
Type
Section
00h TEVSTS
01h Reserved
02h TEVSMI
03h Reserved
04h TEVIRQ
RO
12.3.2
Temperature Event to SMI
Temperature Event to IRQ
R/W
R/W
12.3.3
12.3.4
05h-
Reserved
07h
08h TMSCFG
09h TMSBS
TMS Configuration
TMS Bank Select
R/W
R/W
12.3.5
12.3.6
Table 56. TMS Channel Register Map (One per Channel)
Offset Mnemonic
Register Name
Type
Section
0Ah TCHCFST
0Bh RDCHT
0Ch CHTH
Temperature Channel Configuration and Status Varies per bit
12.3.7
12.3.8
Read Channel Temperature
RO
Channel Temperature High Limit
Channel Temperature Low Limit
Channel Overtemperature Limit
R/W
R/W
R/W
12.3.9
0Dh CHTL
12.3.10
12.3.11
0Eh CHOTL
0Fh Reserved
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12.0 Temperature Sensor (TMS) (Continued)
12.3.2 Temperature Event Status Register (TEVSTS)
This register is set to 00h on power-up of AVDD. It indicates which of the corresponding three TMS events has occurred.
Location:
Type:
Offset 00h
RO
Bit
7
6
0
5
4
3
2
1
0
Local
Overtemp
Event
Local
ALERT
Event
Remote 2 Remote 2 Remote 1 Remote 1
Overtemp
Event
ALERT
Event
Status
Overtemp
Event
Status
ALERT
Event
Status
Name
Reset
Reserved
Status
Status
Status
0
0
0
0
0
0
0
Bit
Description
7-6 Reserved.
5
4
3
2
1
0
Local Overtemperature Event Status.
0: Event not detected (default)
1: Event detected
Local ALERT Event Status.
0: Event not detected (default)
1: Event detected
Remote 2 Overtemperature Event Status.
0: Event not detected (default)
1: Event detected
Remote 2 ALERT Event Status.
0: Event not detected (default)
1: Event detected
Remote 1 Overtemperature Event Status.
0: Event not detected (default)
1: Event detected
Remote 1 ALERT Event Status.
0: Event not detected (default)
1: Event detected
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12.0 Temperature Sensor (TMS) (Continued)
12.3.3 Temperature Event to SMI Register (TEVSMI)
This register controls temperature event routing to the SMI.
Location:
Type:
Offset 02h
R/W
Bit
7
6
0
5
4
3
2
1
0
Local
Overtemp
Event to
Local
ALERT
Event to
Remote 2 Remote 2 Remote 1 Remote 1
Overtemp
Event to
ALERT
Event to
Overtemp
Event to
ALERT
Event to
Name
Reset
Reserved
SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable
0
0
0
0
0
0
0
Bit
Description
7-6
Reserved.
5
4
3
2
1
0
Local Overtemperature Event to SMI Enable.
0: Disabled (default)
1: Enabled
Local ALERT Event to SMI Enable.
0: Disabled (default)
1: Enabled
Remote 2 Overtemperature Event to SMI Enable.
0: Disabled (default)
1: Enabled
Remote 2 ALERT Event to SMI Enable.
0: Disabled (default)
1: Enabled
Remote 1 Overtemperature Event to SMI Enable.
0: Disabled (default)
1: Enabled
Remote 1 ALERT Event to SMI Enable.
0: Disabled (default)
1: Enabled
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12.0 Temperature Sensor (TMS) (Continued)
12.3.4 Temperature Event to IRQ Register (TEVIRQ)
This register controls temperature event routing to the IRQ.
Location:
Type:
Offset 04h
R/W
Bit
7
6
0
5
4
3
2
1
0
Local
Overtemp
Event to
Local
ALERT
Event to
Remote 2 Remote 2 Remote 1 Remote 1
Overtemp
Event to
ALERT
Event to
Overtemp
Event to
ALERT
Event to
Name
Reset
Reserved
IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable
0
0
0
0
0
0
0
Bit
Description
7-6
Reserved.
5
4
3
2
1
0
Local Overtemperature Event to IRQ Enable.
0: Disabled (default)
1: Enabled
Local ALERT Event to IRQ Enable.
0: Disabled (default)
1: Enabled
Remote 2 Overtemperature Event to IRQ Enable.
0: Disabled (default)
1: Enabled
Remote 2 ALERT Event to IRQ Enable.
0: Disabled (default)
1: Enabled
Remote 1 Overtemperature Event to IRQ Enable.
0: Disabled (default)
1: Enabled
Remote 1 ALERT Event to IRQ Enable.
0: Disabled (default)
1: Enabled
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12.0 Temperature Sensor (TMS) (Continued)
12.3.5 TMS Configuration Register (TMSCFG)
This register selects channels and sets global configuration (not channel-specific) values.
Location:
Type:
Offset 08h
R/W
Bit
7
6
0
5
0
4
0
3
0
2
0
1
0
External
VREF
Standby
Mode
Name
Reset
Reserved
0
1
1
Bit
Description
7-2 Reserved.
1
External VREF.
This bit selects either internal or external reference voltage for conversion. Note that if either the VLM or TMS
are configured to use the internal VREF, the internal VREF will be used by both.
0: Internal VREF in use
1: External VREF in use (default)
0
Standby Mode.
0: Monitoring operation enabled
1: Standby mode (default)
12.3.6 TMS Bank Select Register (TMSBS)
This register selects banks and sets global configuration (not bank specific) values.
Location:
Type:
Offset 09h
R/W
Bit
7
6
0
5
0
4
0
3
0
2
1
0
0
0
Name
Reset
Reserved
Bank Select
0
0
Bit
Description
7-4 Reserved.
3-0 Bank Select. These bits select the bank for configuration and viewing.
Bits
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
Other
Bank
Function
0
1
2
Remote diode 1
Remote diode 2
Local diode
Reserved
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12.0 Temperature Sensor (TMS) (Continued)
12.3.7 Temperature Channel Configuration and Status Register (TCHCFST)
This register is set to 00h on power-up of AVDD. Bits 3-1 indicate which of three temperature limits has been exceeded. Write
1 to clear any of these bits. Writing 0 has no effect.
Location:
Type:
Offset 0Ah
Varies per bit
Bit
7
6
Open
0
5
4
3
2
1
0
Channel
Channel
Channel
ALERT
Output
Enable
End of
Conversion
OTS Output
Enable
Overtemp Temp High Temp Low
Limit Limit Limit
Exceeded Exceeded Exceeded
Channel
Enable
Name
Reset
0
0
0
0
0
0
0
Bit
Type
Description
7
R/W1C End of Conversion. This bit reflects the data in the RDCHT register (see next page). It is cleared by
writing 1 to this bit. It is set when new data is written to the RDCHT register.
0: No new data (default)
1: New data not yet read
6
5
4
3
2
1
R/W1C Open.
0: No fault (default)
1: Remote diode continuity (open circuit) fault
R/W OTS Output Enable.
0: Disabled (default)
1: Enabled
R/W ALERT Output Enable.
0: Disabled (default)
1: Enabled
R/W1C Channel Overtemperature Limit Exceeded.
0: Overtemperature lower than limit (default)
1: Overtemperature higher than limit
R/W1C Channel Temperature High Limit Exceeded.
0: Temperature lower than limit (default)
1: Temperature higher than limit
R/W1C Channel Temperature Low Limit Exceeded. This bit is set whenever a value lower than the value
specified in CHTL is written into RDCHT. It is cleared by writing 1 to it.
0: Temperature higher than limit (default)
1: Temperature lower than limit
0
R/W Channel Enable.
0: Disabled (default)
1: Enabled
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12.0 Temperature Sensor (TMS) (Continued)
12.3.8 Read Channel Temperature Register (RDCHT)
This register holds the last temperature readout for each channel. The value is an 8-bit, 2’s complement word with a Least
Significant Bit (LSB) equal to 1° C of the temperature measured by the channel.
Location:
Type:
Offset 0Bh
RO
Bit
7
6
0
5
0
4
3
2
0
1
0
0
0
Name
Reset
Channel Temperature Value
0
0
0
12.3.9 Channel Temperature High Limit Register (CHTH)
This register holds the temperature high limit value that is compared with the temperature reading.
Location:
Type:
Offset 0Ch
R/W
Bit
7
6
1
5
4
3
2
1
1
0
1
Name
Reset
Channel Temperature High Limit Value
0
1
1
1
1
12.3.10 Channel Temperature Low Limit Register (CHTL)
This register holds the temperature low limit value that is compared with the temperature reading.
Location:
Type:
Offset 0Dh
R/W
Bit
7
6
1
5
4
3
2
1
0
0
1
Name
Reset
Channel Temperature Low Limit Value
1
0
0
1
0
12.3.11 Channel Overtemperature Limit Register (CHOTL)
This register holds the overtemperature limit value that is compared with the temperature reading.
Location:
Type:
Offset 0Eh
R/W
Bit
7
6
1
5
4
3
2
1
1
0
1
Name
Reset
Channel Overtemperature Limit Value
0
1
1
1
1
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12.0 Temperature Sensor (TMS) (Continued)
12.4 TMS REGISTER BITMAP
12.4.1 TMS Control and Status Registers
Register
Bits
Offset Mnemonic
00h TEVSTS
01h
7
6
5
4
3
2
1
0
Local
Overtemp
Event
Local
ALERT
Event
Remote 2 Remote 2 Remote 1 Remote 1
Overtemp
Event
ALERT
Event
Status
Overtemp
Event
Status
ALERT
Event
Status
Reserved
Reserved
Status
Status
Status
Reserved
Local
Overtemp
Event to
SMI
Local
ALERT
Event to
SMI
Remote 2 Remote 2 Remote 1 Remote 1
Overtemp
Event to
SMI
ALERT
Event to
SMI
Overtemp
Event to
SMI
ALERT
Event to
SMI
02h TEVSMI
03h
Enable
Enable
Enable
Enable
Enable
Enable
Reserved
Local
Overtemp
Event to
IRQ
Local
ALERT
Event to
IRQ
Remote 2 Remote 2 Remote 1 Remote 1
Overtemp
Event to
IRQ
ALERT
Event to
IRQ
Overtemp
Event to
IRQ
ALERT
Event to
IRQ
04h TEVIRQ
Reserved
Enable
Enable
Enable
Enable
Enable
Enable
05h-
07h
Reserved
External
VREF
Standby
Mode
08h
09h
TMSCFG
TMSBS
Reserved
Reserved
Bank Select
12.4.2 TMS Channel Registers
Register
Bits
Offset Mnemonic
0Ah TCHCFST
7
6
5
4
3
2
1
0
Channel
Channel
Channel
OTS
Output
Enable
ALERT
Output
Enable
End of
Conversion
Overtemp Temp High Temp Low Channel
Open
Limit
Limit
Limit
Enable
Exceeded Exceeded Exceeded
0Bh RDCHT
0Ch CHTH
0Dh CHTL
0Eh CHOTL
0Fh
Channel Temperature Value
Channel Temperature High Limit Value
Channel Temperature Low Limit Value
Channel Overtemperature Limit Value
Reserved
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12.0 Temperature Sensor (TMS) (Continued)
12.5 USAGE HINTS
12.5.1 Remote Diode Selection
Temperature accuracy depends on a good quality transistor, used as a diode-connected small-signal transistor. Accuracy
has been experimentally verified for the Motorola and other devices listed in Table 57. A temperature sensor can directly
measure the die temperature of CPUs with on-board temperature-sensing diodes.
The transistor must be a small-signal type with a relatively high forward voltage; otherwise, the A/D input voltage range may
be violated. The forward voltage must be greater than 0.25V at 10µA at the highest expected temperature. The forward volt-
age must be less than 0.95V at 100µA at the lowest expected temperature. Power transistors do not work. In addition, the
base resistance must be less than 100Ω. Tight specifications for forward-current gain (+50 to +150, for example) indicate
devices with consistent VBE characteristics.
Thermal mass can seriously degrade the temperature sensor’s effective accuracy. The use of smaller packages for remote
sensors, such as SOT23s, improves the situation.
The delay effect should be expected when measuring temperature using the internal diode.
Table 57. Remote Sensor Transistor Manufacturers
Manufacturer
Model
Central Semiconductor (USA)
Motorola (USA)
CMPT3904
MMBT3904
National Semiconductor (USA)
Rohm Semiconductor (Japan)
Samsung (Korea)
MMBT3904
SST3904
KST3904-TF
SMBT3904
Siemens (Germany)
Zetex (England)
FMMT3904CT-ND
12.5.2 ADC Noise Filtering
The ADC is an integrating type with inherently good noise rejection, especially of low-frequency signals such as power sup-
ply hum. Micropower operation places constraints on high-frequency noise rejection; therefore, careful PC board layout and
proper external noise filtering are required for high-accuracy remote measurements in electrically noisy environments.
High-frequency EMI is best filtered at DXP and DXN with an external 2200 pF capacitor. This value can be increased to
about 3300pF (max), including cable capacitance. Capacitance higher than 3300 pF introduces errors due to the rise time
of the switched current source.
Nearly all noise sources tested cause the ADC measurements to be higher than the actual temperature, depending on the
frequency and amplitude.
12.5.3 PC Board Layout
1. Place the temperature sensor as close as practical to the remote diode. In a noisy environment, such as a computer
motherboard, this distance can be 4 in. to 8 in. (typical) or more as long as the worst noise sources (such as CRTs, clock
generators, memory buses and ISA/PCI buses) are avoided.
2. Do not route the DXP DXN lines next to high-inductance signals. Also, do not route the traces across a fast memory bus,
which can easily introduce +30˚C error, even with good filtering. Otherwise, most noise sources are fairly benign.
3. Route the DXP and DXN traces in parallel and in close proximity to each other and away from any high-voltage traces
such as +12VDC. Beware of leakage currents from PC board contamination; e.g., a 20M leakage path from DXP to
ground causes about +1˚C error.
4. Connect guard traces to GND on either side of the DXP DXN traces (Figure 45). With guard traces in place, routing near
high-voltage traces is not a problem.
5. Route through as few vias and crossunders as possible to minimize copper/solder thermocouple effects.
6. When introducing a thermocouple, make sure that both the DXP and the DXN paths have matching thermocouples. In
general, PC board-induced thermocouples are not a serious problem. A copper-solder thermocouple exhibits 3V/˚C, and
it takes about 200V of voltage error at DXP DXN to cause a +1˚C measurement error. So, most parasitic thermocouple
errors are swamped out.
7. Use wide traces. Narrow ones are more inductive and tend to pick up radiated noise. The 10 mil widths and spacings
recommended in Figure 45 are not absolutely necessary (as they offer only a minor improvement in leakage and noise),
but try to use them where practical.
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12.0 Temperature Sensor (TMS) (Continued)
• Keep in mind that copper cannot be used as an EMI shield, and only ferrous materials such as steel work well. Placing
a copper ground plane between the DXP-DXN traces and traces carrying high-frequency noise signals does not help
reduce EMI.
GND
10 mil
10 mil
10 mil
DXP
Minimum
10 mil
DXN
GND
Figure 45. DXP/DXN PC Traces
DXP
DXN
2N3904
2200 pF
Figure 46. Typical Operating Circuit
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12.0 Temperature Sensor (TMS) (Continued)
12.5.4 Twisted Pair and Shielded Cables
For remote sensor distances longer than 8 in. or in particularly noisy environments, a twisted pair is recommended. Its prac-
tical length is 6 feet to 12 feet (typical) before noise becomes a problem, as tested in a noisy electronics laboratory. For
longer distances, the best solution is a shielded twisted pair like that used for audio microphones. Connect the twisted pair
to DXP and DXN and the shield to GND and leave the shield’s remote end unterminated.
Excess capacitance at DX_ limits practical remote sensor distances. For very long cable runs, the cable’s parasitic capaci-
tance often provides noise filtering, so the 2200 pF capacitor can often be removed or reduced in value.
Cable resistance also affects remote sensor accuracy: 1Ω series resistance introduces about +1/2˚C error.
12.5.5 Obtaining the Specified VLM/TMS Accuracy
To obtain the specified VLM/TMS accuracy, use the following sequence on VSB power-up:
1. Set the TMS Logical Device base address.
2. Enable the TMS Logical Device.
3. Write 00h to index 08h of the TMS Logical Device.
4. Write 0Fh to index 09h of the TMS Logical Device.
5. Write 08h to index 0Ah of the TMS Logical Device.
6. Write 04h to index 0Bh of the TMS Logical Device.
7. Write 35h to index 0Ch of the TMS Logical Device.
8. Write 05h to index 0Dh of the TMS Logical Device.
9. Write 05h to index 0Eh of the TMS Logical Device.
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13.0 Legacy Functional Blocks
This chapter briefly describes the following blocks that provide legacy device functions:
●
Keyboard and Mouse Controller (KBC).
●
Floppy Disk Controller (FDC).
●
Parallel Port.
●
Serial Port 1 (SP1), UART Functionality for both Serial Port 1 and Serial Port 2.
●
Serial Port 2 (SP2), Infrared Functionality.
The description of each Legacy block includes the sections listed below. For more information about legacy blocks, contact
your National representative.
●
General Description.
●
Register Map table(s).
●
Bitmap table(s).
The register maps in this chapter use the following abbreviations for Type:
●
R/W = Read/Write.
●
R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
●
W = Write.
●
RO = Read Only.
●
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
13.1 KEYBOARD AND MOUSE CONTROLLER (KBC)
13.1.1 General Description
The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse con-
troller and a Keyboard controller.
The KBC is functionally equivalent to the industry standard 8042A Keyboard controller, which may serve as a detailed tech-
nical reference for the KBC.
13.1.2 KBC Register Map
Offset
Mnemonic
Register Name
Type
DBBOUT Read KBC Data
DBBIN Write KBC Data
STATUS Read Status
R
W
R
00h
04h
DBBIN Write KBC Command
W
13.1.3 KBC Bitmap Summary
Register
Bits
Offset Mnemonic
DBBOUT
7
6
5
4
3
2
1
0
KBC Data Bits (For Read cycles)
KBC Data Bits (For Write cycles)
00h
DBBIN
STATUS
General Purpose Flags
F1
F0
IBF
OBF
04h
DBBIN
KBC Command Bits (For Write cycles)
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13.0 Legacy Functional Blocks (Continued)
13.2 FLOPPY DISK CONTROLLER (FDC)
13.2.1 General Description
The generic FDC is a standard FDC with a digital data separator and is DP8473 and N82077 software compatible.
The FDC is implemented in this device as follows:
●
FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/read-
ing from a diskette, where:
0 = FM mode
1 = MFM mode
●
Automatic media sense is not supported (MSEN0-1 pins are not implemented).
●
DRATE1 is not supported.
●
A logic 1 is returned for all floating (TRI-STATE) FDC register bits upon LPC I/O read cycles.
13.2.2 FDC Register Map
Offset
Mnemonic
Register Name
Status A
Type
00h
01h
02h
03h
SRA
SRB
DOR
TDR
MSR
DSR
FIFO
RO
RO
R/W
R/W
R
Status B
Digital Output
Tape Drive
Main Status
Data Rate Select
Data (FIFO)
Reserved
04h
W
05h
06h
R/W
DIR
Digital Input
Configuration Control
R
07h
CCR
W
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13.0 Legacy Functional Blocks (Continued)
13.2.3 FDC Bitmap Summary
The FDC supports two system operation modes: PC-AT mode and PS/2 mode (MicroChannel systems). Unless specifically
indicated otherwise, all fields in all registers are valid in both drive modes.
Register
Bits
Offset Mnemonic
7
6
5
4
3
2
1
0
IRQ
Pending
Head Se-
lect
Head
Direction
SRA1
00h
Reserved
Step
TRK0
INDEX
WP
Drive
Select 0
Status
SRB1
01h
Reserved
WDATA
RDATA
WGATE
MTR1
MTR0
Motor
Enable 3
Motor
Enable 2
Motor
Enable 1
Motor
Enable 0
Reset
Controller
02h
03h
DOR
TDR
DMAEN
Drive Select
Reserved
Tape Drive Select 1,0
Tape Drive Select 1,0
Logical Drive
Exchange
TDR2
Reserved
Drive ID Information
Command
Data I/O
Direction Execution
Non-DMA
in
Drive 3
Busy
Drive 2
Busy
Drive 1
Busy
Drive 0
Busy
MSR
DSR
RQM
Progress
04h
Data Transfer Rate
Select
Software
Reset
Low Power Reserved
Precompensation Delay Select
05h
07h
07h
FIFO
DIR3
Data Bits
Reserved
DSKCHG
DSKCHG
High
Density
DIR1
CCR
Reserved
Reserved
DRATE 1,0 Status
DRATE1,0
1. Applicable only in PS/2 Mode.
2. Applicable only in Enhanced TDR Mode.
3. Applicable only in PC-AT Compatible Mode.
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13.0 Legacy Functional Blocks (Continued)
13.3 PARALLEL PORT
13.3.1 General Description
The Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP),
Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).
13.3.2 Parallel Port Register Map
The Parallel Port functional block register maps are grouped according to first and second level offsets. EPP and second
level offset registers are available only when base address is 8-byte aligned.
Table 58. Parallel Port Register Map for First Level Offset
First Level
Offset
Modes (ECR Bits)
7 6 5
Mnemonic
Register Name
Type
0 0 0
0 0 1
000h
DATAR PP Data
R/W
000h
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
400h
401h
402h
403h
404h
405h
AFIFO ECP Address FIFO
0 1 1
All Modes
All Modes
1 0 0
W
DSR
DCR
Status
RO
Control
R/W
R/W
R/W
R/W
R/W
R/W
W
ADDR EPP Address
DATA0 EPP Data Port 0
DATA1 EPP Data Port 1
DATA2 EPP Data Port 2
DATA3 EPP Data Port 3
CFIFO PP Data FIFO
DFIFO ECP Data FIFO
TFIFO Test FIFO
1 0 0
1 0 0
1 0 0
1 0 0
0 1 0
0 1 1
R/W
R/W
RO
1 1 0
CNFGA Configuration A
CNFGB Configuration B
1 1 1
1 1 1
RO
ECR
EIR
Extended Control
Extended Index
All Modes
All Modes
All Modes
All Modes
R/W
R/W
R/W
R/W
EDR
EAR
Extended Data
Extended Auxiliary Status
Table 59. Parallel Port Register Map for Second Level Offset
Second Level
Register Name Type
Offset
00h
02h
04h
05h
Control0
Control2
R/W
R/W
R/W
R/W
Control4
PP Confg0
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13.0 Legacy Functional Blocks (Continued)
13.3.3 Parallel Port Bitmap Summary
The Parallel Port functional block bitmaps are grouped according to first and second level offsets.
Table 60. Parallel Port Bitmap Summary for First Level Offset
Register
Bits
Offset Mnemonic
7
6
5
4
3
2
1
0
DATAR
000h
Data Bits
AFIFO
Address Bits
Printer
Status
ACK
Status
SLCT
Status
ERR
Status
EPP Time-
out Status
001h
002h
DSR
DCR
PE Status
Reserved
Printer
Automatic
Data
Strobe
Control
Direction
Control
Interrupt
Enable
PP Input
Control
Reserved
Initialization Line Feed
Control
Control
003h
004h
005h
006h
007h
400h
400h
400h
ADDR
DATA0
DATA1
DATA2
DATA3
CFIFO
DFIFO
TFIFO
EPP Device or Register Selection Address Bits
EPP Device or R/W Data
EPP Device or R/W Data
EPP Device or R/W Data
EPP Device or R/W Data
Data Bits
Data Bits
Data Bits
Bit 7 of PP
Confg0
400h
401h
CNFGA
CNFGB
Reserved
Reserved
Interrupt
Request
Value
Reserved
Interrupt Select
Reserved
DMA Channel Select
ECP
Interrupt
Mask
ECP
Interrupt
Service
ECP DMA
Enable
FIFO
FIFO Full
402h
ECR
ECP Mode Control
Empty
403h
404h
405h
EIR
EDR
EAR
Reserved
Second Level Offset
Data Bits
Reserved
FIFO Tag
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13.0 Legacy Functional Blocks (Continued)
Table 61. Parallel Port Bitmap Summary for Second Level Offset
Bits
Register
Second
Level Mnemonic
Offset
7
6
5
4
3
2
1
0
EPP Time-
out
Interrupt
Mask
DCR
00h
Control0
Control2
Reserved
Register Freeze Bit
Live
Reserved
Channel
Address
Enable
Revision
Reserved 1.7 or 1.9
Select
SPP Com-
patibility
02h
04h
Reserved
Control4 Reserved
PP DMA Request Inactive Time
Reserved
PP DMA Request Active Time
PE
Demand
DMA
Enable
PP
Confg0
Bit 3 of
CNFGA
Internal
Pull-up or
Pull-down
ECP DMA Channel
Number
05h
ECP IRQ Channel Number
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13.0 Legacy Functional Blocks (Continued)
13.4 UART FUNCTIONALITY (SP1 AND SP2)
13.4.1 General Description
Both SP1 and SP2 provide UART functionality. The generic SP1 and SP2 support serial data communication with remote
peripheral device or modem using a wired interface. The functional blocks can function as a standard 16450 or 16550 or as
an Extended UART.
13.4.2 UART Mode Register Bank Overview
Four register banks, each containing eight registers, control UART operation. All registers use the same 8-byte address
space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common to all banks. See Figure
47.
BANK 3
BANK 2
BANK 1
Common
Register
Throughout
All Banks
BANK 0
Offset 07h
Offset 06h
Offset 05h
Offset 04h
LCR/BSR
Offset 02h
Offset 01h
Offset 00h
16550 Banks
Figure 47. UART Mode Register Bank Architecture
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13.0 Legacy Functional Blocks (Continued)
13.4.3 SP1 and SP2 Register Maps for UART Functionality
Table 62. Bank 0 Register Map
Offset
Mnemonic
Register Name
Receiver Data Port
Type
00h
00h
01h
RXD
TXD
IER
RO
W
Transmitter Data Port
Interrupt Enable
R/W
RO
W
EIR
Event Identification (Read Cycles)
FIFO Control (Write Cycles)
Line Control
02h
03h
FCR
LCR1
R/W
BSR1
MCR
LSR
Bank Select
04h
05h
06h
07h
Modem/Mode Control
Link Status
R/W
RO
MSR
Modem Status
RO
SPR/ASCR Scratchpad/Auxiliary Status and Control
R/W
1. When bit 7 of this Register is set to 1, bits 6-0 of BSR select the bank, as
shown in Table 63.
Table 63. Bank Selection Encoding
BSR Bits
Bank
Functionality
Selected
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
1
1
x
0
1
1
1
1
1
1
1
1
x
x
x
x
1
1
1
1
1
1
x
x
x
x
0
0
0
0
1
1
x
x
x
x
0
0
1
1
0
0
x
x
x
x
0
1
0
1
0
1
x
x
1
x
0
0
0
0
0
0
x
x
x
1
0
0
0
0
0
0
0
1
1
1
2
3
4
5
6
7
UART + IR
(SP1 + SP2)
IR Only
(SP2)
Table 64. Bank 1 Register Map
Register Name
Offset
Mnemonic
Type
00h
01h
LBGD(L) Legacy Baud Generator Divisor Port (Low Byte)
LBGD(H) Legacy Baud Generator Divisor Port (High Byte)
Reserved
R/W
R/W
02h
03h
LCR/BSR Line Control/Bank Select
Reserved
R/W
04h - 07h
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13.0 Legacy Functional Blocks (Continued)
Table 65. Bank 2 Register Map
Register Name
Offset
Mnemonic
Type
00h
01h
02h
03h
04h
05h
06h
07h
BGD(L) Baud Generator Divisor Port (Low Byte)
BGD(H) Baud Generator Divisor Port (High Byte)
R/W
R/W
R/W
R/W
R/W
EXCR1
Extended Control1
LCR/BSR Line Control/Bank Select
EXCR2
Extended Control 2
Reserved
TXFLV
RXFLV
TX_FIFO Level
RX_FIFO Level
R/W
R/W
Table 66. Bank 3 Register Map
Offset
Mnemonic
Register Name
Type
00h
01h
MRID
Module Revision ID
RO
RO
SH_LCR Shadow of LCR (Read Only)
SH_FCR Shadow of FIFO Control (Read Only)
LCR/BSR Line Control/Bank Select
Reserved
02h
RO
03h
R/W
04h-07h
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13.0 Legacy Functional Blocks (Continued)
13.4.4 SP1 and SP2 Bitmap Summary for UART Functionality
Table 67. Bank 0 Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
RXD
Receiver Data Bits
Transmitter Data Bits
MS_IE
00h
TXD
IER1
Reserved
LS_IE
LS_IE
IPR1
TXLDL_IE RXHDL_IE
TXLDL_IE RXHDL_IE
01h
Reserved3/
MS_IE
IER2
Reserved
TXEMP_IE
DMA_IE4
EIR1
FEN1
FEN0
Reserved
RXFT
IPR0
IPF
Reserved3/
DMA_EV4
LS_EV or
TXHLT_EV
EIR2
02h
Reserved
TXEMP_EV
MS_EV
TXLDL_EV RXHDL_EV
FCR
RXFTH1
BKSE
RXFTH0
SBRK
TXFTH1
STKP
TXFTH0
EPS
Reserved
PEN
TXSR
STB
RXSR
WLS1
FIFO_EN
WLS0
LCR5
03h
BSR5
BKSE
Bank Select
ISEN or
DCDLP
MCR1
04h
Reserved
LOOP
RILP
RTS
DTR
MCR2
Reserved
TX_DFR
FE
Reserved
PE
RTS
OE
DTR
RXDA
DCTS
05h
06h
LSR
ER_INF
DCD
TXEMP
RI
TXRDY
DSR
BRK
CTS
MSR
DDCD
TERI
DDSR
SPR1
Scratch Data
07h
4
ASCR2
TXUR4
RXACT
RXWDG4
S_OET4
Reserved
Reserved
Reserved RXF_TOUT
1. Non-Extended Mode.
2. Extended Mode.
3. In SP1 only.
4. In SP2 only.
5. When bit 7 of this register is set to 1, bits 6-0 of BSR select the bank, as shown in Table 63.
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13.0 Legacy Functional Blocks (Continued)
Table 68. Bank 1 Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
00h
01h
02h
03h
LBGD(L)
LBGD(H)
Legacy Baud Generator Divisor (Least Significant Bits)
Legacy Baud Generator Divisor (Most Significant Bits)
Reserved
LCR/BSR
Same as Bank 0
04h-
07h
Reserved
Table 69. Bank 2 Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
00h
01h
02h
03h
04h
BGD(L)
BGD(H)
EXCR1
Baud Generator Divisor Low (Least Significant Bits)
Baud Generator Divisor High (Most Significant Bits)
BTEST
LOCK
Reserved
Reserved
ETDLBK
LOOP
Reserved
EXT_SL
LCR/BSR
EXCR2
Same as Bank 0
PRESL0
PRESL1
Reserved
05h Reserved
06h
07h
TXFLV
RXFLV
Reserved
Reserved
TFL4
RFL4
TFL3
RFL3
TFL2
RFL2
TFL1
RFL1
TFL0
RFL0
Table 70. Bank 3 Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
00h
01h
02h
03h
MRID
Module ID (MID 7-4)
Revision ID(RID 3-0)
SH_LCR
SH_FCR
LCR/BSR
BKSE
SBRK
STKP
EPS
PEN
STB
WLS1
RXSR
WLS0
RXFTH1
RXFTH0
TXFHT1
TXFTH0
Reserved
TXSR
FIFO_EN
Same as Bank 0
Reserved
04h-
07h
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13.0 Legacy Functional Blocks (Continued)
13.5 IR FUNCTIONALITY (SP2)
13.5.1 General Description
This section describes the IR support registers of Serial Port 2 (SP2). The UART support registers for both SP1 and SP2
are described in Section 13.4.
The IR functional block provides advanced, versatile serial communications features with IR capabilities.
SP2 supports also two DMA channels; the functional block can use either one or both of them. One channel is required for
IR-based applications because IR communication works in half duplex fashion. Two channels would normally be needed to
handle high-speed full-duplex UART based applications.
13.5.2 IR Mode Register Bank Overview
Eight register banks, each containing eight registers, control SP2 operation. Banks 0-3 are used to control both UART and
IR modes of operation; banks 4-7 are used to control and configure the IR modes of operation only. All registers use the
same 8-byte address space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common
to all banks. See Figure 48.
BANK 7
BANK 6
Common
Register
Throughout
BANK 5
BANK 4
BANK 3
BANK 2
BANK 1
BANK 0
All Banks
Offset 07h
Offset 06h
Offset 05h
Offset 04h
LCR/BSR
IR Special Banks
(Banks 4-7)
Offset 02h
Offset 01h
Offset 00h
Figure 48. SP2 Register Bank Architecture
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13.0 Legacy Functional Blocks (Continued)
13.5.3 SP2 Register Map for IR Functionality
.
Table 71. Bank 4 Register Map
Offset
Mnemonic
Register Name
Type
00h-01h
02h
Reserved
IRCR1
IR Control 1
R/W
R/W
03h
LCR/BSR Line Control/Bank Select
Reserved
04h - 07h
Table 72. Bank 5 Register Map
Offset
Mnemonic
Register Name
Type
00h-02h
03h
Reserved
LCR/BSR Line Control/Bank Select
R/W
R/W
04h
IRCR2
IR Control 2
05h - 07h Reserved
Table 73. Bank 6 Register Map
Register Name
Offset
Mnemonic
Type
00h
01h
IRCR3
IR Control 3
Reserved
R/W
02h
SIR_PW SIR Pulse Width Control (≤ 115 Kbps)
LCR/BSR Line Control/Bank Select
Reserved
R/W
R/W
03h
04h-07h
Table 74. Bank 7 Register Map
Offset
Mnemonic
Register Name
Type
00h
01h
02h
03h
04h
05h
06h
07h
IRRXDC IR Receiver Demodulator Control
IRTXMC IR Transmitter Modulator Control
RCCFG CEIR Configuration
RO
RO
RO
LCR/BSR Line Control/Bank Select
IRCFG1 IR Interface Configuration 1
Reserved
R/W
R/W
IRCFG3 IR Interface Configuration 3
IRCFG4 IR Interface Configuration 4
R/W
R/W
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13.0 Legacy Functional Blocks (Continued)
13.5.4 SP2 Bitmap Summary for IR Functionality
Table 75. Bank 4 Bitmap
Bits
Register
Offset Mnemonic
7
7
7
6
5
4
3
2
1
0
00h-
01h
Reserved
02h
03h
EIR
Reserved
IR_SL1
IR_SL0
Reserved
LCR/BSR
Same as Bank 0
Reserved
04h-
07h
Table 76. Bank 5 Bitmap
Bits
Register
Offset Mnemonic
6
5
4
3
2
1
0
00h-
02h
Reserved
03h
04h
LCR/BSR
IRCR2
Same as Bank 0
AUX_IRRX Reserved
Reserved
Reserved
IRMSSL IR_FDPLX
05h-
07h
Table 77. Bank 6 Bitmap
Bits
Register
Offset Mnemonic
6
5
4
3
2
1
0
00h
01h
02h
03h
IRCR3
SHDM_DS SHMD_DS
Reserved
Reserved
SIR_PW
Reserved
SPW (3-0)
LCR/BSR
Same as Bank 0
Reserved
04h-
07h
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13.0 Legacy Functional Blocks (Continued)
Table 78. Bank 7 Bitmap
Bits
Register
Offset Mnemonic
7
6
5
4
3
2
1
0
IRRXDC
00h
01h
02h
03h
04h
05h
06h
07h
DBW (2-0)
MCPW (2-0)
T_OV
DFR (4-0)
MCFR (4-0)
IRTXMC
RCCFG
RCDM_DS
RC_MMD0
R_LEN
RXHSC
SIRC (2-0)
RCH (2-0)
Reserved
TXHSC RC_MND1
LCR/BSR
Same as Bank 0
IRCFG1 STRV_MS
IRID3
IRIC (2-0)
Reserved
RXINV
IRCFG3
IRCFG4
Reserved
AMCFG
Reserved
IRSL21_DS
RCLC (2-0)
Reserved
Reserved IRSL0_DS
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14.0 Device Characteristics
14.1 GENERAL DC ELECTRICAL CHARACTERISTICS
14.1.1 Recommended Operating Conditions
Symbol
AVDD
VDD
Parameter
Analog Supply Voltage (only one)
Supply Voltage
Min
3.0
3.0
3.0
2.4
0
Typ
3.3
3.3
3.3
3.0
Max Unit
3.6
3.6
3.6
3.6
+70
V
V
VSB
V
Standby Voltage
VBAT
TA
V
Battery Backup Supply Voltage
Operating Temperature
°C
14.1.2 Absolute Maximum Ratings
Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all volt-
ages are relative to ground.
Symbol
Parameter
Conditions
Min
-0.5
−0.5
−0.5
−0.5
−65
Max
TBD
Unit
AVDD Analog Supply Voltage
VDD
VI
+6.5
V
V
Supply Voltage
VDD + 0.5
VDD + 0.5
+165
Input Voltage
VO
V
Output Voltage
TSTG
PD
°C
W
°C
Storage Temperature
Power Dissipation
Lead Temperature Soldering (10 s)
1
TL
+260
CZAP = 100 pF
RZAP = 1.5 KΩ1
ESD Tolerance
2000
V
1. Value based on test complying with RAI-5-048-RA human body model ESD testing.
14.1.3 Capacitance
Symbol
Parameter
Input Pin Capacitance
Min
Typ
5
Max Unit
CIN
CIN1
CIO
CO
7
12
12
8
pF
pF
pF
pF
5
8
Clock Input Capacitance
I/O Pin Capacitance
10
6
Output Pin Capacitance
TA = 25°C, f = 1 MHz
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14.0 Device Characteristics (Continued)
14.1.4 Power Consumption under Recommended Operating Conditions
Symbol
Parameter
Conditions
Typ
Max
Unit
VIL = 0.5V, VIH = 2.4V
No Load
ICC
VDD Average Main Supply Current
32
50
mA
VDD Quiescent Main Supply Current VIL = VSS, VIH = VDD
ICCLP
IASB
ISB
1.3
1.7
TBD
15
mA
mA
mA
in Low Power Mode
No Load
AVDD Average Main Supply Current
TBD
VIL = 0.5V, VIH = 2.4V
No Load
VSB Average Main Supply Current
VSB Quiescent Main Supply Current
in Low Power Mode
VIL = VSS, VIH = VSB
No Load
ISBLP
IBAT
3
mA
nA
V
DD, VSB = 0 V,
VBAT = 3V
VBAT Battery Supply Current
250
14.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES
The following tables summarize the DC characteristics of all device pins described in the Signal/Pin Connection and De-
scription chapter. The characteristics describe the general I/O buffer types defined in Table 1. For exceptions, refer to Sec-
tion 14.2.15 on page 228. The DC characteristics of the system interface meet the PCI2.1 3.3V DC signaling.
14.2.1 Input, CMOS Compatible
Symbol: INC
Symbol
VIH
Parameter
Input High Voltage
Conditions
Min
Max
Unit
V
5.51
0.7 VDD
−0.51
VIL
0.3 VDD
V
Input Low Voltage
VIN = VDD
VIN = VSS
50
nA
nA
IIL
Input Leakage Current
−50
1. Not tested. Guaranteed by design.
14.2.2 Input, PCI 3.3V
Symbol: INPCI
Symbol
VIH
Parameter
Input High Voltage
Conditions
Min
Max
Unit
V
0.5VDD VDD + 0.5
VIL
−0.5
0.3 VDD
V
Input Low Voltage
1
0 < Vin < VDD
±10
µA
Input Leakage Current
lIL
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with TRI-STATE out-
puts.
14.2.3 Input, SMBus Compatible
Symbol: INSM
Symbol
Parameter
Input High Voltage
Conditions
Min
Max
Unit
5.51
VIH
1.4
V
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14.0 Device Characteristics (Continued)
Symbol
Parameter
Input Low Voltage
Conditions
Min
Max
Unit
VIL
−0.5
1
0.8
V
VIN = VDD
VIN = VSS
10
µA
µA
IIL
Input Leakage Current
−10
1. Not tested. Guaranteed by design.
14.2.4 Input, Strap Pin
Symbol: INSTRP
Symbol
Parameter
Input High Voltage
Conditions
Min
Max
Unit
0.6 VDD
5.51
150
−10
1
VIH
V
During Reset: VIN = VDD
VIN = VSS
µA
µA
IIL
Input Leakage Current
1. Not tested. Guaranteed by design.
14.2.5 Input, TTL Compatible
Symbol: INT
Symbol
VIH
Parameter
Input High Voltage
Conditions
Min
Max
Unit
V
5.51
0.8
2.0
−0.51
VIL
V
Input Low Voltage
VIN = VDD
VIN = VSS
10
µA
µA
IIL
Input Leakage Current
−10
1. Not tested. Guaranteed by design.
14.2.6 Input, TTL Compatible with Schmitt Trigger
Symbol: INTS
Symbol
VIH
Parameter
Input High Voltage
Conditions
Min
Max
Unit
V
5.51
0.8
2.0
1
VIL
V
Input Low Voltage
Input Leakage Current
Input Hysteresis
−0.5
VIN = VDD
VIN = VSS
10
µA
µA
mV
IIL
−10
VH
250
1. Not tested. Guaranteed by design.
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14.0 Device Characteristics (Continued)
14.2.7 Output, PCI 3.3V
Symbol: OPCI
Symbol
VOH
Parameter
Output High Voltage
Output Low Voltage
Conditions
lout = -500 µA
lout =1500 µA
Min
Max
Unit
V
0.9 VDD
VOL
0.1 VDD
V
14.2.8 Output, Totem-Pole Buffer
Symbol: Op/n
Output, Totem-Pole buffer that is capable of sourcing p mA and sinking n mA
Symbol
VOH
Parameter
Output High Voltage
Output Low Voltage
Conditions
IOH = −p mA
IOL = n mA
Min
Max
Unit
V
2.4
VOL
0.4
V
14.2.9 Output, Open-Drain Buffer
Symbol: ODn
Output, Open-Drain output buffer, capable of sinking n mA. Output from these signals is open-drain and cannot be forced high.
Symbol
Parameter
Output Low Voltage
Conditions
Min
Max
Unit
VOL
IOL = n mA
0.4
V
14.2.10 Input, Analog
Symbol: INAN1
Input, analog to VLM.
Conditions1
Symbol
Parameter
Min
Typ
Max
Unit
IAL
Analog Input Leakage Current
±1
250
15
µA
Ω
Analog Input Resistance2
Analog Input Capacitance
RAIN
CAIN
pF
1. All parameters specified for 0° C ≤ TA ≤ 70° C.
AVCC= 3.3V ± 10%, unless otherwise specified and VREF = 1.235 or AVDD.
2. The resistance between the device input and the internal analog input capacitance.
14.2.11 Input, Analog
Symbol: INAN2
Input, analog to reference voltage.
Conditions1
Symbol
Parameter
Min
Typ
1.235
Max
Unit
VREFE External Reference Voltage
TBD
5
TBD
36
V
VREF Input DC resistance2
RVREFE
KΩ
1. All parameters specified for 0° C ≤ TA ≤ 70° C.
AVCC= 3.3V ± 10%, unless otherwise specified and VREF = 1.235 or AVDD
.
2. Valid only for external VREF; value changes during the conversion.
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14.0 Device Characteristics (Continued)
14.2.12 Input, Analog
Symbol: INAN3
Input, analog to TMS.
Symbol
Parameter
D- Source Voltage
Conditions
Min
Typ
Max
Unit
VDN
0.7
V
14.2.13 Output, Analog
Symbol: OAN1
Output, analog to reference voltage.
Symbol
Parameter
Conditions
Min
Typ
Max
1.237
36
Unit
V
VREFE External Reference Voltage
1.233 1.235
5
VREF Input DC resistance1
RVREFE
KΩ
1. Valid only for external VREF; value changes during the conversion.
14.2.14 Output, Analog
Symbol: OAN2
Output, analog to TMS.
Symbol
Parameter
Diode Source Current
Conditions
Min
Typ
Max
Unit
IDPH
D+ = D- + 0.65V; High
Level
80
120
µA
IDPL
Low Level
8
12
µA
14.2.15 Exceptions
1. All pins are back-drive protected, except for the output pins with PCI Buffer Type.
2. The following pins have a static pull-up resistor and therefore may have input leakage current (when VIN = VSS) of about
(-)160µA: ACK, AFD_DSTRB, ERR, GPIO40-47, GPIO30-34, GPIO20-27, GPIO16-17, GPIO10-14. GPIO00-07, INIT,
P12, P16, P17, PE, SLIN_ASTRB, STB_WRITE.
3. The following pins have a static pull-down resistor and therefore may have input leakage current (when VIN = VDD) of
about 130µA: BUSY_WAIT, PE, SLCT.
4. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 Register is “0”) is open-drain in all SPP modes, except in
SPP-Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1.
Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used.
5. Output from ACK, ERR (and PE if bit 2 of PP Confg0 Register is set to 1) is open-drain in all SPP modes, except in SPP-
Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1.
Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used.
6. Output from STB, AFD, INIT, SLIN is open-drain in all SPP modes, except in SPP-Compatible mode when the setup
mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be
used.
7. Output from PD7-0 is open-drain in all SPP modes, except in SPP-Compatible mode when the setup mode is ECP-based
(FIFO) and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is Level 2. External 4.7
KΩ pull-up resistors should be used.
8. IOH is valid for a GPIO pin only when it is not configured as open-drain.
9. P12, P16 and P17 are driven high for about 100 ns after a low-to-high transition, during which it is capable of sourcing
2 mA.
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14.0 Device Characteristics (Continued)
14.3 INTERNAL RESISTORS
14.3.1 Pull-Up Resistor
Symbol: PUnn
.
Symbol
Parameter
Pull-up equivalent resistance
Conditions
Typical Min
Max
Unit
RPU
VDD = 3.3V
nn nn−30% nn+30%
KΩ
14.3.2 Pull-Down Resistor
Symbol: PDnn
.
Symbol
Parameter
Pull-down equivalent resistance
Conditions
Typical Min
Max
Unit
RPD
VDD = 3.3V
nn nn−30% nn+30%
KΩ
14.4 ANALOG CHARACTERISTICS
14.4.1 VLM
Conditions1
Symbol
Parameter
Min
Typical
Max
Unit
VRES
VDNL
VREF
ACU
VFS
Resolution
8
bit
LSB
V
Differential (non-linearity) Error2
Reference Voltage Input4
±0.53
±6
1.211
2.967
Accuracy5
0V ≤ VIN ≤ 0.95 VFS
LSB
V
Full Scale Voltage
VIN
Input Voltage Range
VLM Activation Time6
0
2.45*VREF
100
V
tACT
µs
1. All parameters specified for 0° C ≤ TA ≤ 70° C and AVCC= 3.3V ± 5% unless otherwise specified and external
REF = 1.211V.
V
2. The maximum difference between an ideal step size of 1 LSB and any actual step size.
3. No missing codes.
4. The voltage connected to this input serves as the reference voltage used to calculate the actual input
voltatge.
5. Total unadjusted error (incoludes the offset, gain, integral n0on-linearity and quantization (0.5 LSB) errors).
6. Time from when the VLMCFG register Standby Mode Enable bit = 0 until valid conversions are possible.
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14.0 Device Characteristics (Continued)
14.4.2 TMS
Conditions1
TA = -40°C to +125°C
TA = +40°C to +100°C
TA = -40°C to +125°C
TA = +40°C to +100°C
Symbol
Parameter
Min
Typ
Max
Unit
TRAC1 Accuracy Using Remote Diode
TRAC2
-9
-5
-5
-2
+9
+5
+5
+2
C
C
Accuracy Using Local Diode2
TLAC1
TLAC2
C
C
TRESB Resolution
TRESC
8
1
bits
°C
V
Reference Voltage Input3
VREF
1.211
tCONV Temperature Conversion Time
(per channel)
100
ms
1. All parameters specified for 0° C ≤ TA ≤ 70° C.
AVCC= 3.3V ± 10% unless otherwise specified and external VREF = 1.211V.
2. Not tested; guaranteed by design.
3. When using input with value other than specified, temperature reading accuracy is affected.
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14.0 Device Characteristics (Continued)
14.5 AC ELECTRICAL CHARACTERISTICS
14.5.1 AC Test Conditions
Load Circuit (Notes 1, 2, 3)
AC Testing Input, Output Waveform
VDD
S1
2.4
2.0
0.8
2.0
0.8
0.1 µf
Test Points
0.4
RL
Device
Input
Output
Under
Test
CL
Figure 49. AC Test Conditions, TA = 0 °C to 70 °C, VDD = 5.0V ±10%
Notes:
1. CL = 100 pF for all output pins except OPCI, and CL = 50pF for outputs of type OPCI. These values include both jig and
scope capacitance.
2. S1 = Open for push-pull output pins.
S1 = VDD for high impedance to active low and active low to high-impedance measurements.
S1 = GND for high impedance to active high and active high to high-impedance measurements.
RL = 1.0KΩ for µP interface pins.
3. For the FDC open-drive interface pins, S1 = VDD and RL = 150Ω.
14.5.2 Clock Timing
48 MHz
Symbol
Parameter
Min
8.4
8.4
20
Max
Unit
ns
Clock High Pulse Width1
Clock Low Pulse Width1
Clock Period1
tCH
tCL
tCP
ns
21.5
ns
1. Not tested. Guaranteed by design.
.
tCP
tCH
CLKIN
tCL
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14.0 Device Characteristics (Continued)
14.5.3 LCLK and LRESET
Symbol
Parameter
Min
Max
Units
1
30
ns
LCLK Cycle Time
LCLK High Time
LCLK Low Time
tCYC
tHIGH
11
11
1
ns
ns
tLOW
LCLK Slew Rate2
-
-
4
V/ns
mV/ns
LRESET Slew Rate3
50
1. The PCI may have any clock frequency between nominal DC and 33
MHz. Device operational parameters at frequencies under 16 MHz may
be guaranteed by design rather than by testing. The clock frequency
may be changed at any time during the operation of the system as long
as the clock edges remain “clean” (monotonic) and the minimum cycle
and high and low times are not violated. The clock may only be stopped
in a low state.
2. Rise and fall times are specified in terms of the edge rate measured in
V/ns. This slew rate must be met across the minimum peak-to-peak por-
tion of the clock wavering as shown below.
3. The minimum LRESET slew rate applies only to the rising (de-assertion)
edge of the reset signal and ensures that system noise cannot make an
otherwise monotonic signal appear to bounce in the switching range.
3.3V Clock
tHIGH
tLOW
0.6 VDD
0.5 VDD
0.4 VDD
0.3 VDD
0.4 VDD p-to-p
(minimum)
0.2 VDD
tCYC
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14.0 Device Characteristics (Continued)
14.5.4 LPC and SERIRQ Signals
Symbol
tVAL
tON
Figure
Output
Output
Output
Input
Description
Output Valid Delay
Float to Active Delay
Active to Float Delay
Input Setup Time
Input Hold Time
Reference Conditions
After RE CLK
Min
Max
Unit
ns
11
2
After RE CLK
After RE CLK
Before RE CLK
After RE CLK
ns
tOFF
tSU
28
ns
7
0
ns
tHI
Input
ns
Output
LCLK
tVAL
tON
LPC Signals/
SERIRQ
tOFF
Input
LCLK
tSU
tHI
LPC Signals/
SERIRQ
Input
Valid
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14.0 Device Characteristics (Continued)
14.5.5 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing
Symbol
Parameter
Conditions
Min
Max
Unit
tBTN − 251
tBTN − 2%
tBTN + 25
Transmitter
Receiver
ns
ns
ns
ns
ns
tBT
Single Bit Time in Serial Port and Sharp-IR
tBTN + 2%
tCWN + 25
tCWN − 252
500
Transmitter
Receiver
Modulation Signal Pulse Width in Sharp-IR
and Consumer Remote Control
tCMW
tCPN − 253
tCPN + 25
Transmitter
Modulation Signal Period in Sharp-IR and
Consumer Remote Control
tCMP
4
4
Receiver
ns
ns
tMMIN
tMMAX
(3/16) x tBTN − 151 (3/16) x tBTN + 151
Transmitter,
Variable
tSPW
SIR Signal Pulse Width
Transmitter,
Fixed
1.48
1
1.78
µs
µs
Receiver
Transmitter
Receiver
± 0.87%
± 2.0%
± 2.5%
± 6.5%
SIR Data Rate Tolerance.
% of Nominal Data Rate.
SDRT
Transmitter
Receiver
SIR Leading Edge Jitter.
% of Nominal Bit Duration.
tSJT
1. tBTN is the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is deter-
mined by the setting of the Baud Generator Divisor registers.
2. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes.
It is determined by the MCPW field (bits 7-5) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG
register.
3. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is
determined by the MCFR field (bits 4-0) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG reg-
ister.
4. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in
order for the signal to be accepted by the receiver. These time values are determined by the contents of the
IRRXDC register and the setting of the RXHSC bit (bit 5) of the RCCFG register.
t
BT
Serial Port
t
t
CMP
CMW
Sharp-IR
Consumer Remote Control
t
SPW
SIR
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14.0 Device Characteristics (Continued)
14.5.6 Modem Control Timing
Symbol
Parameter
Min
10
Max
Unit
ns
tL
RI2,1 Low Time
tH
RI2,1 High Time
10
ns
tSIM
Delay to Set IRQ from Modem Input
40
ns
CTS, DSR, DCD
INTERRUPT
tSIM
tSIM
tSIM
(Read MSR)
(Read MSR)
RI
tL
tH
14.5.7 FDC Write Data Timing
Symbol
tHDH
Parameter
Min
Max
Unit
µs
HDSEL Hold from WGATE Inactive1
100
100
HDSEL Setup to WGATE Active1
Write Data Pulse Width
µs
tHDS
tWDW
See tDRP, tICP and tWDW values in table below
1. Not tested. Guaranteed by design.
HDSEL
WGATE
tHDS
tHDH
tWDW
WDATA
t
DRP tICP tWDW Values
tDRP
tICP
tICP Nominal
tWDW
tWDW Minimum
Data Rate
1 Mbps
Unit
1
1
125
125
208
250
2 x tICP
2 x tICP
2 x tICP
2 x tICP
1000
2000
3333
4000
250
250
375
500
ns
ns
ns
ns
6 x tCP
500 Kbps
300 Kbps
250 Kbps
6 x tCP
1
10 x tCP
12 x tCP
1
1. tCP is the clock period defined in the Clock Timing section on page 231.
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14.0 Device Characteristics (Continued)
14.5.8 FDC Drive Control Timing
Symbol
tDST
tIW
Parameter
Min
6
Max
Unit
µs
DIR Setup to STEP Active1
Index Pulse Width
100
tSTR
8
ns
tSTD
tSTP
ms
µs
DIR Hold from STEP Inactive
STEP Active High Pulse Width1
STEP Rate Time1
0.5
ms
tSTR
1. Not tested. Guaranteed by design.
DIR
tSTD
tDST
STEP
tSTP
tSTR
INDEX
tIW
14.5.9 FDC Read Data Timing
Symbol
Parameter
Read Data Pulse Width
Min
Max
Unit
tRDW
50
ns
tRDW
RDATA
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14.0 Device Characteristics (Continued)
14.5.10 Standard Parallel Port Timing
Symbol
Parameter
Conditions
Typ
Max
Unit
These times are system dependent
and are therefore not tested.
500
ns
tPDH
Port Data Hold
Port Data Setup
Strobe Width
These times are system dependent
and are therefore not tested.
500
500
ns
ns
tPDS
tSW
These times are system dependent
and are therefore not tested.
Typical Data Exchange
BUSY
ACK
tPDH
tPDS
PD7-0
tSW
STB
14.5.11 Enhanced Parallel Port Timing
Symbol
tWW19a
tWW19ia
tWST19a
tWEST
Parameter
WRITE Active from WAIT Low
WRITE Inactive from WAIT Low
Min
Max EPP 1.7 EPP 1.9 Unit
45
45
65
✔
✔
✔
✔
✔
✔
✔
✔
ns
ns
ns
ns
ns
ns
ns
ns
DSTRB or ASTRB Active from WAIT Low
DSTRB or ASTRB Active after WRITE Active
PD7-0 Hold after WRITE Inactive
PD7-0 Valid after WRITE Active
10
0
✔
✔
✔
✔
✔
tWPDH
tWPDS
15
tEPDW
80
0
PD7-0 Valid Width
tEPDH
PD7-0 Hold after DSTRB or ASTRB Inactive
tWW19a
WRITE
DSTRB
or
ASTRB
tWST19a
tWPDH
tWEST
tEPDH
tWST19a
Valid
tEPDW
PD7-0
WAIT
tWPDS
tWW19ia
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14.0 Device Characteristics (Continued)
14.5.12 Extended Capabilities Port (ECP) Timing
Forward Mode
Symbol
tECDSF
Parameter
Data Setup before STB Active
Min
0
Max
Unit
ns
ns
ns
s
tECDHF
tECLHF
tECHHF
tECHLF
tECLLF
0
Data Hold after BUSY Inactive
BUSY Active after STB Active
STB Inactive after BUSY Active
BUSY Inactive after STB Active
STB Active after BUSY Inactive
75
0
1
0
35
ms
ns
0
tECDHF
PD7-0
AFD
tECDSF
tECLLF
STB
tECHLF
tECLHF
BUSY
tECHHF
Reverse Mode
Parameter
Symbol
Min
0
Max
Unit
ns
ns
ns
ms
s
tECDSR
tECDHR
tECLHR
tECHHR
tECHLR
tECLLR
Data Setup before ACK Active
Data Hold after AFD Active
AFD Inactive after ACK Active
ACK Inactive after AFD Inactive
AFD Active after ACK Inactive
ACK Active after AFD Active
0
75
0
35
1
0
0
ns
tECDHR
PD7-0
BUSY
tECDSR
ACK
AFD
tECLLR
tECHLR
tECHHR
tECLHR
www.national.com
238
Physical Dimensions
All dimensions are in millimeters.
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC87365-xxx/VLA
NS Package Number VLA128A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation, Americas
Email: new.feedback@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific
Fax: 65-250-4466
Email: ap.support@nsc.com
Tel: 65-254-4466
National Semiconductor
Japan
Fax: 81-3-5639-7507
Email: nsj.crc@jksmtp.nsc.com
Tel: 81-3-5639-7560
Fax: +49 (0) 1 80 530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 87 90
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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