PCA9539PWRG4 [TI]
具有中断输出、复位和配置寄存器的 16 位 2.3V 至 5.5V I2C/SMBus I/O 扩展器 | PW | 24 | -40 to 85;型号: | PCA9539PWRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有中断输出、复位和配置寄存器的 16 位 2.3V 至 5.5V I2C/SMBus I/O 扩展器 | PW | 24 | -40 to 85 时钟 光电二极管 外围集成电路 |
文件: | 总34页 (文件大小:778K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
FEATURES
•
Low Standby-Current Consumption of
1 µA Max
I2C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
Active-Low Reset Input
•
•
•
•
Address by Two Hardware Address Pins for
Use of up to Four Devices
•
•
•
•
•
•
•
Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
5-V Tolerant I/O Ports
ESD Protection Exceeds JESD 22
Compatible With Most Microcontrollers
400-kHz Fast I2C Bus
–
–
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model (C101)
Polarity Inversion Register
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGE PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
INT
A1
V
CC
2
SDA
SCL
A0
24 23 22 21 20 19
3
RESET
P00
1
2
3
4
5
6
18
17
16
15
14
13
P00
P01
P02
P03
P04
P05
A0
4
P17
P16
P15
P14
P13
5
P01
P02
P03
P17
P16
P15
P14
P13
P12
P11
P10
6
7
8
P04
P05
P06
P07
9
7
8 9 10 11 12
10
11
12
GND
DESCRIPTION/ORDERING INFORMATION
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
PCA9539DBR
TOP-SIDE MARKING
Reel of 2000
SSOP – DB
PCA9539
Tube of 60
PCA9539DB
QSOP – DBQ
TVSOP – DGV
Reel of 2500
Reel of 2000
Tube of 25
PCA9539DBQR
PCA9539DGVR
PCA9539DW
PCA9539DWR
PCA9539PW
PD9539
PD9539
–40°C to 85°C
SOIC – DW
PCA9539
Reel of 2000
Tube of 60
TSSOP – PW
QFN – RGE
Reel of 1200
Reel of 250
Reel of 3000
PCA9539PWR
PCA9539PWT
PCA9539RGER
PD9539
PD9539
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial
clock (SCL), serial data (SDA)].
The PCA9539 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data
for each input or output is kept in the corresponding Input or Output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the PCA9539 in the event of a timeout or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part.
The PCA9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9539 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low
current consumption.
The PCA9539 is identical to the PCA9555, except for the removal of the internal I/O pullup resistor, which
greatly reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different
address range.
Two hardware pins (A0 and A1) are used to program and vary the fixed I2C address and allow up to four
devices to share the same I2C bus or SMBus.
2
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
TERMINAL FUNCTIONS
NO.
SOIC (DW),
SSOP (DB),
QSOP (DBQ),
TSSOP (PW), AND
TVSOP (DGV)
NAME
DESCRIPTION
QFN (RGE)
1
2
22
23
INT
A1
Interrupt output. Connect to VCC through a pullup resistor.
Address input. Connect directly to VCC or ground.
Active-low reset input. Connect to VCC through a pullup resistor if no active
connection is used.
3
24
RESET
4
1
2
P00
P01
P02
P03
P04
P05
P06
P07
GND
P10
P11
P12
P13
P14
P15
P16
P17
A0
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
Ground
5
6
3
7
4
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
Address input. Connect directly to VCC or ground.
Serial clock bus. Connect to VCC through a pullup resistor.
Serial data bus. Connect to VCC through a pullup resistor.
Supply voltage
SCL
SDA
VCC
3
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
PCA9539
1
Interrupt
Logic
LP Filter
INT
21
2
A0
A1
P07−P00
P17−P10
22
23
SCL
SDA
2
Input
Filter
I C Bus
Shift
Register
I/O
Port
16 Bits
Control
Write Pulse
Read Pulse
3
RESET
Power-On
Reset
24
12
V
CC
GND
A. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
B. All I/Os are set to inputs at reset.
4
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
SIMPLIFIED SCHEMATIC OF P-PORT I/Os(1)
Data From
Output Port
Shift Register
Register Data
Configuration
Register
V
CC
Q1
Data From
Shift Register
D
Q
FF
CLK
D
Q
Q
Write Configuration
Pulse
Q
FF
CLK
I/O Pin
GND
Write Pulse
Output Port
Register
Q2
Input Port
Register
D
Q
Input Port
Register Data
FF
CLK
Read Pulse
Q
To INT
Data From
Shift Register
Polarity
Register Data
D
Q
Q
FF
CLK
Write Polarity
Pulse
Polarity Inversion
Register
(1) At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
5
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address.
After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during
the high of the ACK-related clock pulse. The address inputs (A0 and A1) of the slave device must not be
changed between the Start and Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 2. Bit Transfer
6
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Clock Pulse for
Condition
Acknowledgment
Figure 3. Acknowledgment on I2C Bus
Interface Definition
BIT
BYTE
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C slave address
P0x I/O data bus
P1x I/O data bus
H
H
H
L
H
A1
A0
R/W
P00
P10
P07
P17
P06
P16
P05
P15
P04
P14
P03
P13
P02
P12
P01
P11
7
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
Device Address
Figure 4 shows the address byte of the PCA9539.
R/W
Slave Address
1
1
1
0
1
A1 A0
Fixed
Programmable
Figure 4. PCA9539 Address
Address Reference
INPUTS
A1
I2C BUS SLAVE ADDRESS
A0
L
L
L
116 (decimal), 74 (hexadecimal)
117 (decimal), 75 (hexadecimal)
118 (decimal), 76 (hexadecimal)
119 (decimal), 77 (hexadecimal)
H
L
H
H
H
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9539. Three bits of this data byte state the operation (read or write) and
the internal register (input, output, polarity inversion or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until
a new command byte has been sent.
0
0
0
0
0
B2 B1 B0
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
COMMAND
BYTE (HEX)
POWER-UP
DEFAULT
REGISTER
PROTOCOL
B2
0
B1
0
B0
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Input Port 0
Input Port 1
Read byte
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
0000 0000
0000 0000
1111 1111
1111 1111
0
0
1
Read byte
0
1
0
Output Port 0
Read/write byte
Read/write byte
Read/write byte
Read/write byte
Read/write byte
Read/write byte
0
1
1
Output Port 1
1
0
0
Polarity Inversion Port 0
Polarity Inversion Port 1
Configuration Port 0
Configuration Port 1
1
0
1
1
1
0
1
1
1
8
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to
these registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register will be accessed next.
Registers 0 and 1 (Input Port Registers)
Bit
I0.7
X
I0.6
X
I0.5
X
I0.4
X
I0.3
X
I0.2
X
I0.1
X
I0.0
X
Default
Bit
I1.7
X
I1.6
X
I1.5
X
I1.4
X
I1.3
X
I1.2
X
I1.1
X
I1.0
X
Default
The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Registers 2 and 3 (Output Port Registers)
Bit
O0.7
1
O0.6
1
O0.5
1
O0.4
1
O0.3
1
O0.2
1
O0.1
1
O0.0
1
Default
Bit
O1.7
1
O1.6
1
O1.5
1
O1.4
1
O1.3
1
O1.2
1
O1.1
1
O1.0
1
Default
The Polarity Inversion registers (Registers 4 and 5) allow polarity inversion of pins defined as inputs by the
Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Registers 4 and 5 (Polarity Inversion Registers)
Bit
N0.7
0
N0.6
0
N0.5
0
N0.4
0
N0.3
0
N0.2
0
N0.1
0
N0.0
0
Default
Bit
N1.7
0
N1.6
0
N1.5
0
N1.4
0
N1.3
0
N1.2
0
N1.1
0
N1.0
0
Default
The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is
set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this
register is cleared to 0, the corresponding port pin is enabled as an output.
Registers 6 and 7 (Configuration Registers)
Bit
C0.7
1
C0.6
1
C0.5
1
C0.4
1
C0.3
1
C0.2
1
C0.1
1
C0.0
1
Default
Bit
C1.7
1
C1.6
1
C1.5
1
C1.4
1
C1.3
1
C1.2
1
C1.1
1
C1.0
1
Default
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9539 in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9539 registers and
I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and
then back up to the operating voltage for a power-reset cycle.
9
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA9539 registers and
I2C/SMBus state machine are held in their default states until RESET is once again high. This input requires a
pullup resistor to VCC, if no active connection is used.
Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt, or in a Stop event. Resetting occurs in the read
mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. In a
Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock
pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the
I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read
independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pullup resistor to VCC
.
Bus Transactions
Data is exchanged between the master and PCA9539 through write and read commands.
Writes
Data is transmitted to the PCA9539 by sending the device address and setting the least-significant bit to a logic
0 (see Figure 4 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte.
The eight registers within the PCA9539 are configured to operate as four register pairs. The four pairs are input
ports, output ports, polarity inversion ports, and configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent
to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
1
2
3
4
5
6
7
8
9
SCL
SDA
Command Byte
Data to Port 0
Data 0
Data to Port 1
Data 1
Slave Address
A
P
0.7
0.0
1.0
S
1
1
1
0
1
A1 A0
0
A
0
0
0
0
0
0
1
0
A
A
1.7
R/W
Acknowledge
From Slave
Acknowledge
From Slave
Start Condition
Acknowledge
From Slave
Write to Port
Data Out from Port 0
t
pv
Data Valid
Data Out from Port 1
t
pv
Figure 6. Write to Output Port Registers
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PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
1
2
3
4
5
6
7
8
9
1
2
0
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SCL
SDA
Slave Address
Command Byte
Data to Register
Data 0
Data to Register
Data1
MSB
LSB
MSB
LSB
S
1
1
1
0
1
A1 A0
0
A
0
0
0
0
1
1
0
A
A
A
P
Acknowledge
From Slave
Acknowledge
From Slave
R/W
Acknowledge
From Slave
Start Condition
Figure 7. Write to Configuration Registers
Reads
The bus master first must send the PCA9539 address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9539 (see Figure 8 through Figure 10).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The
original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into
the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read,
but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the
next byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Data From Lower
or Upper Byte
Slave Address
Slave Address
of Register
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Master
S
1
1
1
0
1
A1 A0
0
A
Command Byte
A
S
1
1
1
0
1
A1 A0
1
A
MSB
Data
LSB A
First Byte
R/W
R/W
At this moment, master
transmitter becomes master
receiver, and slave receiver
becomes slave transmitter.
Data From Upper
or Lower Byte
of Register
No Acknowledge
From Master
MSB
LSB NA
P
Data
Last Byte
Figure 8. Read From Register
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1
2
3
4
5
6
7
8
9
SCL
SDA
I0.x
I1.x
I0.x
I1.x
3
S
1
1
1
0
1
A1 A0
1
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
2
1
0
1
P
Acknowledge
From Master
R/W
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Slave
No Acknowledge
From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
t
t
ir
iv
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 9. Read Input Port Register, Scenario 1
<br/>
1
2
3
4
5
6
7
8
9
SCL
I0.x
I1.x
I0.x
I1.x
S
1
1
1
0
1
A1 A0
1
A
00
A
10
A
03
A
1
P
SDA
12
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Slave
Acknowledge
From Master
R/W
No Acknowledge
From Master
t
ps
t
ph
Read From Port 0
Data Into Port 0
Data 00
Data 01
Data 02
Data 03
t
t
ps
ph
Read From Port 1
11
12
Data
Data 10
Data
Data Into Port 1
INT
t
iv
t
ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 10. Read Input Port Register, Scenario 2
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Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)
6
V
VO
IIK
6
V
Input clamp current
VI < 0
–20
–20
±20
50
mA
mA
mA
mA
mA
IOK
IIOK
IOL
IOH
Output clamp current
VO < 0
Input/output clamp current
Continuous output low current
Continuous output high current
Continuous current through GND
Continuous current through VCC
VO < 0 or VO > VCC
VO = 0 to VCC
VO = 0 to VCC
–50
–250
160
63
ICC
mA
DB package
DBQ package
DGV package
DW package
PW package
RGE package
RGE package
61
86
θJA
Package thermal impedance, junction to free air(3)
°C/W
46
88
45
θJP
Package thermal impedance, junction to pad
Storage temperature range
1.5
150
°C/W
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN
2.3
MAX
5.5
UNIT
VCC
VIH
Supply voltage
V
SCL, SDA
0.7 × VCC
0.7 × VCC
–0.5
5.5
High-level input voltage
V
V
A0, A1, RESET, P07–P00, P17–P10
SCL, SDA
5.5
0.3 × VCC
0.3 × VCC
–10
VIL
Low-level input voltage
A0, A1, RESET, P07–P00, P17–P10
P07–P00, P17–P10
–0.5
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
P07–P00, P17–P00
25
–40
85
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Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
VCC
2.3 V to 5.5 V
VPOR
MIN TYP(1)
MAX UNIT
VIK
Input diode clamp voltage
Power-on reset voltage
–1.2
1.5
1.8
2.6
4.1
1.7
2.5
4
V
VPOR
VI = VCC or GND, IO = 0
1.65
V
2.3 V
IOH = –8 mA
3 V
4.75 V
2.3 V
VOH
P-port high-level output voltage(2)
V
IOH = –10 mA
3 V
4.75 V
SDA
VOL = 0.4 V
VOL = 0.5 V
VOL = 0.7 V
VOL = 0.4 V
3
8
10
3
20
24
IOL
P port(3)
2.3 V to 5.5 V
mA
INT
SCL, SDA
A0, A1, RESET
P port
±1
±1
1
II
VI = VCC or GND
2.3 V to 5.5 V
µA
IIH
IIL
VI = VCC
2.3 V to 5.5 V
2.3 V to 5.5 V
5.5 V
µA
µA
P port
VI = GND
–1
200
75
50
1
100
30
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz
Operating mode
3.6 V
2.7 V
20
ICC
µA
5.5 V
0.5
0.4
0.25
VI = GND, IO = 0, I/O = inputs,
fSCL = 0 kHz
Standby mode
3.6 V
0.9
0.8
2.7 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
Additional current in standby mode
2.3 V to 5.5 V
2.3 V to 5.5 V
200
µA
CI
SCL
VI = VCC or GND
3
3
7
7
pF
SDA
P port
Cio
VIO = VCC or GND
2.3 V to 5.5 V
pF
3.7
9.5
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
(2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum
current of 100 mA, for a device total of 200 mA.
(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
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I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11)
MIN
0
MAX
UNIT
kHz
µs
fscl
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
400
tsch
tscl
0.6
1.3
µs
tsp
50
ns
tsds
tsdh
ticr
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
100
ns
0
ns
(1)
20 + 0.1Cb
300
300
300
ns
(1)
(1)
ticf
20 + 0.1Cb
20 + 0.1Cb
ns
tocf
I2C output fall time
10-pF to 400-pF bus
ns
tbuf
I2C bus free time between Stop and Start
I2C Start or repeated Start condition setup
I2C Start or repeated Start condition hold
I2C Stop condition setup
1.3
0.6
0.6
0.6
50
µs
tsts
µs
tsth
µs
tsps
tvd(data)
tvd(ack)
Cb
µs
Valid-data time
SCL low to SDA output valid
ACK signal from SCL low to SDA (out) low
ns
Valid-data time of ACK condition
I2C bus capacitive load
0.1
0.9
µs
400
pF
(1) Cb = total capacitance of one bus line in pF
RESET Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 14)
MIN
6
MAX
UNIT
ns
tW
Reset pulse duration
Reset recovery time
Time to reset
tREC
tRESET
0
ns
400
ns
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 12 and
Figure 13)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
Interrupt valid time
MIN
MAX
UNIT
tiv
P port
SCL
INT
INT
4
4
µs
µs
ns
ns
µs
tir
Interrupt reset delay time
Output data valid
tpv
tps
tph
SCL
P port
SCL
SCL
200
Input data setup time
Input data hold time
P port
P port
150
1
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SCPS130D–AUGUST 2005–REVISED MARCH 2007
TYPICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
SUPPLY CURRENT
vs
TEMPERATURE
STANDBY SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
TEMPERATURE
SUPPLY VOLTAGE
55
50
45
40
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
30
25
20
15
10
5
SCL = VCC
fSCL = 400 kHz
I/Os Unloaded
VCC = 5 V
fSCL = 400 kHz
I/Os Unloaded
VCC = 5 V
VCC = 3.3 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 2.5 V
0
0
-50
-25
0
25
50
75
100
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-50
-25
0
25
50
75
100
TA – Free-Air Temperature – °C
VCC – Supply Voltage – V
TA – Free-Air Temperature – °C
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
TA = –40°C
TA = –40°C
TA = –40°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 125°C
TA = 125°C
TA = 125°C
0
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VOL – Output Low Voltage – V
V
OL – Output Low Voltage – V
VOL – Output Low Voltage – V
I/O OUTPUT LOW VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
vs
TEMPERATURE
300
275
250
225
200
175
150
125
100
75
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
VCC = 2.5 V, ISINK = 10 mA
VCC = 3.3 V
VCC = 2.5 V
TA = –40°C
TA = –40°C
TA = 25°C
TA = 25°C
VCC = 5 V, ISINK = 10 mA
TA = 125°C
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
TA = 125°C
50
25
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-50
-25
0
25
50
75
100
(VCC – VOH) – V
(VCC – VOH) – V
TA – Free-Air Temperature – °C
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O HIGH VOLTAGE
vs
TEMPERATURE
OUTPUT HIGH VOLTAGE
vs
SUPPLY VOLTAGE
300
275
250
225
200
175
150
125
100
75
300
275
250
225
200
175
150
125
100
75
75
VCC = 5 V
70
65
60
55
50
45
40
35
30
25
20
15
10
5
VCC = 2.5 V, IOL = 10 mA
VCC = 2.5 V, IOL = 10 mA
TA = –40°C
TA = 25°C
VCC = 5 V, IOL = 10 mA
VCC = 5 V, IOL = 10 mA
TA = 125°C
50
50
25
25
0
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
(VCC – VOH) – V
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
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SCPS130D–AUGUST 2005–REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
= 1 kΩ
SDA
DUT
C
L
= 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
Data
Bit 0 Condition
(LSB)
Stop
Address
Bit 6
Address
Bit 1
ACK
(A)
(P)
t
scl
t
sch
0.7 × V
0.3 × V
CC
SCL
SDA
CC
t
icr
t
sts
t
PHL
t
icf
t
buf
t
t
sp
PLH
0.7 × V
0.3 × V
CC
CC
t
icf
t
icr
t
sdh
t
sps
t
sth
t
sds
Repeat
Start
Condition
Stop
Condition
Start or
Repeat
Start
Condition
VOLTAGE WAVEFORMS
BYTE
1
DESCRIPTION
2
I C address
2, 3
P-port data
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 11. I2C Interface Load Circuit and Voltage Waveforms
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SCPS130D–AUGUST 2005–REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
R
L
= 4.7 kΩ
INT
DUT
C
L
= 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
Data From Port
Data 2
Data 1
A
1
P
S
1
1
1
0
1
A1 A0
1
A
1
2
3
4
5
6
7
8
A
A
t
ir
B
B
t
ir
INT
A
t
iv
t
sps
A
Data
Into
Port
Address
Data 1
Data 2
0.7 × V
0.3 × V
CC
0.7 × V
0.3 × V
CC
SCL
INT
Pn
R/W
A
CC
CC
t
iv
t
ir
0.7 × V
0.3 × V
0.7 × V
0.3 × V
CC
CC
INT
CC
CC
View A−A
A. CL includes probe and jig capacitance.
View B−B
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 12. Interrupt Load Circuit and Voltage Waveforms
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SCPS130D–AUGUST 2005–REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Pn
500 W
DUT
2 × V
CC
C
= 50 pF
L
500 W
(see Note A)
P-PORT LOAD CONFIGURATION
0.7 × V
CC
SCL
P0
A
P3
0.3 × V
CC
Slave
ACK
SDA
Pn
t
pv
(see Note B)
Last Stable Bit
Unstable
Data
WRITE MODE (R/W = 0)
0.7 × V
0.3 × V
CC
SCL
Pn
P0
A
P3
CC
t
ph
t
ps
0.7 × V
0.3 × V
CC
CC
READ MODE (R/W = 1)
A. CL includes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 13. P-Port Load Circuit and Voltage Waveforms
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SCPS130D–AUGUST 2005–REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
Pn
500 W
R
L
= 1 kΩ
DUT
2 × V
CC
SDA
DUT
C
L
= 50 pF
500 W
(see Note A)
C
L
= 50 pF
(see Note A)
SDA LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y V
CC
t
RESET
RESET
V /2
CC
t
REC
t
w
Pn
V /2
CC
t
RESET
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. I/Os are configured as inputs.
E. All parameters and waveforms are not applicable to all devices.
Figure 14. Reset Load Circuits and Voltage Waveforms
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SCPS130D–AUGUST 2005–REVISED MARCH 2007
APPLICATION INFORMATION
Figure 15 shows an application in which the PCA9539 can be used.
Subsystem 1
(e.g., Temperature
Sensor)
INT
V
CC
(5 V)
Subsystem 2
(e.g., Counter)
100 kW
24
2 kW
10 kW
10 kW 10 kW 10 kW
V
CC
V
CC
100 kW 100 kW
RESET
A
22
23
4
P00
SCL
SDA
INT
SCL
5
Master
P01
Controller
SDA
6
7
P02
P03
1
3
INT
GND
ENABLE
8
9
RESET
P04
P05
B
PCA9539
V
CC
10
Controlled Switch
(e.g., CBT Device)
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
11
13
14
15
16
17
18
19
20
2
ALARM
A1
A0
Keypad
Subsystem 3
(e.g., Alarm)
21
GND
12
A. Device address is configured as 1110100 for this example.
B. P00, P02, and P03 are configured as outputs.
C. P01 and P04 to P17 are configured as inputs.
D. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
Figure 15. Typical Application
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APPLICATION INFORMATION (continued)
Minimizing ICC When I/O Is Used to Control LED
When an I/O is used to control an LED, normally it is connected to VCC through a resistor (see Figure 15).
Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ∆ICC
parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For
battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC, when the
LED is off, to minimize current consumption.
Figure 16 shows a high-value resistor in parallel with the LED. Figure 17 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VCC at or above VCC and prevent additional
supply-current consumption when the LED is off.
V
CC
LED
100 kW
V
CC
Pn
Figure 16. High-Value Resistor in Parallel With LED
3.3 V
5 V
V
CC
LED
Pn
Figure 17. Device Supplied by Lower Voltage
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2006
PACKAGING INFORMATION
Orderable Device
PCA9539DB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
24
24
24
24
24
24
24
24
24
24
24
24
24
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9539DBQR
PCA9539DBQRG4
PCA9539DBR
PCA9539DGVR
PCA9539DW
SSOP/
QSOP
DBQ
DBQ
DB
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP
TVSOP
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
DW
DW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9539DWR
PCA9539PW
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9539PWE4
PCA9539PWR
PCA9539PWRE4
PCA9539RGER
PCA9539RHLR
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RHL
3000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2006
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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