PCA9554DWR_技术文档

Not Recommended for New Designs

PCA9554

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REMOTE 8-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

1

FEATURES

•

I²C to Parallel Port Expander

•

Power-Up With All Channels Configured as

Inputs

Open-Drain Active-Low Interrupt Output

•

No Glitch On Power Up

Operating Power-Supply Voltage Range of

2.3 V to 5.5 V

Latched Outputs With High-Current Drive

Maximum Capability for Directly Driving LEDs

•

5-V Tolerant I/Os

400-kHz Fast I²C Bus

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Three Hardware Address Pins Allow up to

Eight Devices on the I²C/SMBus

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

•

Input/Output Configuration Register

Polarity Inversion Register

Internal Power-On Reset

1000-V Charged-Device Model (C101)

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

RGV PACKAGE

(TOP VIEW)

RGT PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

A0

A1

V_CC

SDA

SCL

INT

P7

16 15 14 13

12

1

12

11

10

A2

P0

P1

SCL

INT

P7

1

2

3

4

A2

P0

P1

SCL

INT

A2

P0

P1

P2

2

3

4

11

10 P7

9

P2

P6

P5

9

P2

P6

5

6

7

8

P3

5

6

7

8

GND

P4

DESCRIPTION/ORDERING INFORMATION

This 8-bit I/O expander for the two-line bidirectional bus (I²C) is designed for 2.3-V to 5.5-V V_CCoperation. It

provides general-purpose remote I/O expansion for most microcontroller families via the I²C interface [serial clock

(SCL), serial data (SDA)].

The PCA9554 consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion

(active high or active low) registers. At power on, the I/Os are configured as inputs with a weak pullup to V_CC

.

However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration

bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the

Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system

master.

The system master can reset the PCA9554 in the event of a timeout or other improper operation by utilizing the

power-on reset feature, which puts the registers in their default state and initializes the I²C/SMBus state machine.

The PCA9554 open-drain interrupt (INT) output is activated when any input state differs from its corresponding

Input Port register state and is used to indicate to the system master that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the

remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via

the I²C bus. Thus, the PCA9554 can remain a simple slave device.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PCA9554

Not Recommended for New Designs

SCPS128B–JULY 2006–REVISED AUGUST 2008 ........................................................................................................................................................ www.ti.com

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current

consumption.

Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I²C address and allow up to eight

devices to share the same I²C bus or SMBus.

The PCA9554 is pin-to-pin and I²C address compatible with the PCF8574. However, software changes are

required, due to the enhancements in the PCA9554 over the PCF8574.

The PCA9554 and PCA9554A are identical except for their fixed I²C address. This allows for up to 16 of these

devices (eight of each) on the same I²C/SMBus.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾⁽²⁾

ORDERABLE PART NUMBER

PCA9554RGTR

PCA9554RGVR

PCA9554DBQR

PCA9554DW

TOP-SIDE MARKING

PREVIEW

QFN – RGT

QFN – RGV

QSOP – DBQ

Reel of 3000

Reel of 2500

Tube of 40

PREVIEW

PD554

SOIC – DW

SSOP – DB

PCA9554

PD554

Reel of 2000

Tube of 80

PCA9554DWR

–40°C to 85°C

PCA9554DB

Reel of 2000

Tube of 90

PCA9554DBR

PCA9554PW

TSSOP – PW

TVSOP – DGV

PD554

Reel of 2000

PCA9554PWR

PCA9554DGVR

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

2

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TERMINAL FUNCTIONS

NO.

QSOP (DBQ)

SOIC (DW),

SSOP (DB),

TSSOP (PW), AND

TVSOP (DGV)

NAME

DESCRIPTION

QFN (RGT) AND

QFN (RGV)

1

2

15

16

1

A0

A1

Address input. Connect directly to V_CCor ground.

P-port input/output. Push-pull design structure.

Ground

3

A2

4

2

P0

5

3

P1

6

4

P2

7

5

P3

8

6

GND

P4

9

7

P-port input/output. Push-pull design structure.

Interrupt output. Connect to V_CCthrough a pullup resistor.

Serial clock bus. Connect to V_CCthrough a pullup resistor.

Serial data bus. Connect to V_CCthrough a pullup resistor.

Supply voltage

10

11

12

13

14

15

16

8

P5

9

P6

10

11

12

13

14

P7

INT

SCL

SDA

V_CC

FUNCTIONAL BLOCK DIAGRAM

13

Interrupt

Logic

LP Filter

INT

1

A0

2

A1

3

A2

14

P7−P0

SCL

2

Input

Filter

I C Bus

Control

Shift

Register

I/O

Port

15

8 Bits

SDA

Write Pulse

Read Pulse

16

V

Power-On

Reset

CC

8

GND

A. Pin numbers shown are for the DB, DBQ, DGV, DW, N, or PW package.

B. All I/Os are set to inputs at reset.

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Simplified Schematic of P0 to P7

Data From

Shift Register

Output Port

Register Data

Configuration

Register

V

CC

Data From

Shift Register

Q1

D

Q

FF

K

100 kW

Write Configuration

Pulse

D

C

Q

C

Q

FF

P0 to P7

GND

Write Pulse

Q

K

Q2

Output Port

Register

Input Port

Register

Input Port

Register Data

D

Q

FF

Read Pulse

C

K

Q

INT

Data From

Shift Register

Polarity

Register Data

D

C

Q

FF

Write Polarity

Pulse

Q

K

Polarity

Inversion

Register

A. At power-on reset, all registers return to default values.

I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input with a

weak pullup (100 kΩ typ) to V_CC. The input voltage may be raised above V_CCto a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In

this case, there are low-impedance paths between the I/O pin and either V_CCor GND. The external voltage

applied to this I/O pin should not exceed the recommended levels for proper operation.

I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a master sending a start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address byte

is sent, MSB first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must

not be changed between the start and the stop conditions.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (start or stop) (see Figure 2).

4

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A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

Any number of data bytes can be transferred from the transmitter to the receiver between the start and the stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)

after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line

high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

SDA

SCL

S

P

Start Condition

Stop Condition

Figure 1. Definition of Start and Stop Conditions

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 2. Bit Transfer

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Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL From

1

2

8

9

Master

S

Start

Clock Pulse for

Condition

Acknowledgment

Figure 3. Acknowledgment on the I²C Bus

Interface Definition

BIT

BYTE

7 (MSB)

6

H

5

L

4

L

3

2

1

0 (LSB)

R/W

I²C slave address

Px I/O data bus

L

A2

P3

A1

P2

A0

P1

P7

P6

P5

P4

P0

6

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Device Address

Figure 4 shows the address byte for the PCA9554.

Slave Address

0

1

0

A2 A1

R/W

A0

Hardware

Selectable

Fixed

Figure 4. PCA9554 Address

Address Reference

INPUTS

I²C BUS SLAVE ADDRESS

A2

L

A1

L

A0

L

32 (decimal), 20 (hexadecimal)

33 (decimal), 21 (hexadecimal)

34 (decimal), 22 (hexadecimal)

35 (decimal), 23 (hexadecimal)

36 (decimal), 24 (hexadecimal)

37 (decimal), 25 (hexadecimal)

38 (decimal), 26 (hexadecimal)

39 (decimal), 27 (hexadecimal)

L

H

L

H

L

H

L

H

L

H

L

H

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read

is selected, while a low (0) selects a write operation.

Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is

stored in the control register in the PCA9554. Two bits of this command byte state the operation (read or write)

and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can

be written or read through the I²C bus. The command byte is sent only during a write transmission.

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a

new command byte has been sent.

0

B1 B0

Figure 5. Control Register Bits

Command Byte

CONTROL REGISTER BITS

COMMAND BYTE

(HEX)

POWER-UP

DEFAULT

REGISTER

PROTOCOL

B1

0

B0

0

0x00

0x01

0x02

0x03

Input Port Register

Output Port Register

Read byte

XXXX XXXX

1111 1111

0000 0000

1111 1111

0

1

Read/write byte

1

0

Polarity Inversion Register

Configuration Register

1

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Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is

defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these

registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I²C device that the

Input Port register will be accessed next.

Register 0 (Input Port Register) Table

BIT

I7

X

I6

X

I5

X

I4

X

I3

X

I2

X

I1

X

I0

X

DEFAULT

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this

register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

Register 1 (Output Port Register) Table

BIT

O7

1

O6

1

O5

1

O4

1

O3

1

O2

1

O1

1

O0

1

DEFAULT

The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration

register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this

register is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Register 2 (Polarity Inversion Register) Table

BIT

N7

0

N6

0

N5

0

N4

0

N3

0

N2

0

N1

0

N0

0

DEFAULT

The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,

the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is

cleared to 0, the corresponding port pin is enabled as an output.

Register 3 (Configuration Register) Table

BIT

C7

1

C6

1

C5

1

C4

1

C3

1

C2

1

C1

1

C0

1

DEFAULT

Power-On Reset

When power (from 0 V) is applied to V_CC, an internal power-on reset holds the PCA9554 in a reset condition until

V_CChas reached V_POR. At that point, the reset condition is released and the PCA9554 registers and I²C/SMBus

state machine initialize to their default states. After that, V_CCmust be lowered to below 0.2 V and then back up to

the operating voltage for a power-reset cycle.

8

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Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t_iv, the signal

INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting,

and data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read mode

at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts

that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt

during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the

state of the pin does not match the contents of the Input Port register.

INT has an open-drain structure and requires a pullup resistor to V_CC

.

Bus Transactions

Data is exchanged between the master and PCA9554 through write and read commands.

Writes

Data is transmitted to the PCA9554 by sending the device address and setting the least-significant bit to a logic 0

(see Figure 4 for device address). The command byte is sent after the address and determines which register

receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one

write transmission.

SCL

1

2

3

4

5

6

7

8

9

Slave Address

Command Byte

Data to Port

Data 1

S

0

1

0

0 A2 A1 A0

0

A

0

1

A

P

SDA

ACK From Slave

R/W ACK From Slave

Start Condition

Write to Port

Data Out

From Port

Data 1 Valid

t

pv

Figure 6. Write to Output Port Register

<br/>

SCL

1

2

3

4

5

6

7

8

0

9

Slave Address

Command Byte

Data to Register

Data

SDA

S

0

1

0

A2 A1 A0

A

0

1

1/0

A

P

Start Condition

R/W ACK From Slave

ACK From Slave

Data to

Register

Figure 7. Write to Configuration or Polarity Inversion Registers

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Reads

The bus master first must send the PCA9554 address with the least-significant bit set to a logic 0 (see Figure 4

for device address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data

from the register defined by the command byte then is sent by the PCA9554 (see Figure 8 and Figure 9). After a

restart, the value of the register defined by the command byte matches the register being accessed when the

restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation

on the number of data bytes received in one read transmission, but when the final byte is received, the bus

master must not acknowledge the data

ACK From

Master

ACK From

Slave

ACK From

Slave

ACK From

Slave

Data from Register

Data

Slave Address

Command Byte

A

S

A

0

1

0

A2 A1 A0

1

A

S

0

1

0

A2 A1 A0 0

A

R/W

NACK From

Master

Data from Register

Data

P

NA

Last Byte

Figure 8. Read From Register

<br/>

1

2

3

4

5

6

7

8

9

SCL

SDA

Data From Port

Data 1

Slave Address

Data From Port

Data 4

S

0

1

0

A2 A1 A0

R/W

1

A

P

A

NA

Start

Condition

NACK From

Master

ACK From

Slave

ACK From

Master

Stop

Condition

Read From

Port

Data Into

Port

Data 2

Data 3

Data 4

Data 5

t

ph

t

ps

INT

t

iv

t

ir

A. This figure assumes the command byte has previously been programmed with 00h.

B. Transfer of data can be stopped at any moment by a Stop condition.

C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from P port. See Figure 8 for these details.

Figure 9. Read From Input Port Register

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX UNIT

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

Output voltage range⁽²⁾

6

V

V_O

I_IK

6

V

Input clamp current

V_I< 0

–20

±20

50

mA

I_OK

I_IOK

I_OL

I_OH

Output clamp current

V_O< 0

Input/output clamp current

Continuous output low current

Continuous output high current

Continuous current through GND

Continuous current through V_CC

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

–50

–250

160

82

I_CC

DB package

DBQ package

DGV package

DW package

N package

90

120

57

θ_JA

Package thermal impedance⁽³⁾

°C/W

67

PW package

RGT package

RGV package

108

TBD

150

T_stg

Storage temperature range

–65

°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS

MIN

2.3

MAX

5.5

UNIT

V_CC

V_IH

Supply voltage

V

SCL, SDA

A2–A0, P7–P0

SCL, SDA

A2–A0, P7–P0

P7–P0

0.7 × V_CC

2

5.5

High-level input voltage

V

5.5

–0.5

0.3 × V_CC

0.8

V_IL

Low-level input voltage

–0.5

I_OH

I_OL

T_A

High-level output current

Low-level output current

Operating free-air temperature

–10

mA

°C

P7–P0

25

–40

85

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.3 V to 5.5 V

V_POR

MIN

TYP⁽¹⁾

MAX UNIT

V_IK

Input diode clamp voltage I_I= –18 mA

–1.2

V

V_POR

Power-on reset voltage

V_I= V_CCor GND, I_O= 0

1.5

1.65

V

2.3 V

1.8

2.6

3.1

4.1

1.7

2.5

3

3 V

I_OH= –8 mA

4.5 V

4.75 V

2.3 V

P-port high-level output

voltage⁽²⁾

V_OH

V

3 V

I_OH= –10 mA

V_OL= 0.4 V

V_OL= 0.5 V

4.5 V

4.75 V

2.3 V to 5.5 V

2.3 V

4

SDA

3

8

10

14

17

35

13

19

24

45

10

8

3 V

8

4.5 V

8

4.75 V

2.3 V

8

I_OL

P port⁽³⁾

mA

10

3

3 V

V_OL= 0.7 V

4.5 V

4.75 V

2.3 V to 5.5 V

INT

V_OL= 0.4 V

SCL, SDA

A2–A0

P port

±1

I_I

V_I= V_CCor GND

2.3 V to 5.5 V

µA

I_IH

I_IL

V_I= V_CC

2.3 V to 5.5 V

5.5 V

1

µA

V_I= GND

–100

175

90

104

50

V_I= V_CC, I_O= 0, I/O = inputs,

f_scl= 400 kHz, No load

3.6 V

2.7 V

20

65

Operating mode

5.5 V

60

150

40

V_I= V_CC, I_O= 0, I/O = inputs,

f_scl= 100 kHz, No load

3.6 V

15

2.7 V

8

20

I_CC

µA

5.5 V

450

300

225

0.25

0.2

0.1

700

600

500

1

V_I= GND, I_O= 0, I/O = inputs,

f_scl= 0 kHz, No load

3.6 V

2.7 V

Standby mode

5.5 V

V_I= V_CC, I_O= 0, I/O = inputs,

f_scl= 0 kHz, No load

3.6 V

0.9

0.8

2.7 V

One input at V_CC– 0.6 V,

Other inputs at V_CCor GND

2.3 V to 5.5 V

1.5

1

Additional current in

standby mode

ΔI_CC

mA

Every LED I/O at V_I= 4.3 V,

f_scl= 0 kHz

5.5 V

C_i

SCL

V_I= V_CCor GND

2.3 V to 5.5 V

4

5.5

8

5

6.5

9.5

pF

SDA

P port

C_io

V_IO= V_CCor GND

2.3 V to 5.5 V

(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V_CC) and T_A= 25°C.

(2) The total current sourced by all I/Os must be limited to 85 mA.

(3) Each I/O must be externally limited to a maximum of 25 mA, and the P port (P0 to P7) must be limited to a maximum current of 200 mA.

12

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I²C INTERFACE TIMING REQUIREMENTS

over operating free-air temperature range (unless otherwise noted) (see Figure 10)

STANDARD MODE

I²C BUS

FAST MODE

I²C BUS

UNIT

MIN

0

MAX

MIN

0

MAX

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

I²C input fall time

100

400

kHz

µs

ns

µs

4

0.6

1.3

4.7

50

t_sds

t_sdh

t_icr

250

0

100

0

(1)

1000

300

20 + 0.1C_b

300

(1)

t_icf

20 + 0.1C_b

t_ocf

t_buf

t_sts

t_sth

t_sps

I²C output fall time

10-pF to 400-pF bus

300

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

4.7

4

1.3

0.6

4

SCL low to SDA output

valid

t_vd(data)

Valid data time

300

0.3

50

ns

ACK signal from SCL low

to SDA (out) low

t_vd(ack)

C_b

Valid data time of ACK condition

I²C bus capacitive load

3.45

400

0.1

0.9

µs

400

ns

(1) C_b= Total capacitive load of one bus in pF

SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted) (see Figure 11 and Figure 12)

STANDARD MODE

FAST MODE

I²C BUS

MIN

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MAX

4

MIN

MAX

t_iv

Interrupt valid time

Interrupt reset delay time

Output data valid

P port

SCL

INT

4

µs

ns

µs

t_ir

4

t_pv

t_ps

t_ph

SCL

P7–P0

SCL

200

Input data setup time

Input data hold time

P port

100

1

100

1

SCL

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TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

TEMPERATURE

QUIESCENT SUPPLY CURRENT

vs

TEMPERATURE

35

30

25

20

15

10

5

55

50

45

40

35

30

25

20

15

10

5

V_CC= 5 V

V_CC= 3.3 V

f_SCL= 400 kHz

I/Os unloaded

V_CC= 3.3 V

V_CC= 2.5 V

SCL = V_CC

60

0

-40

-15

10

35

85

-40

-15

10

35

60

85

T_A– Free-Air Temperature – °C

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

SUPPLY CURRENT

vs

NUMBER OF I/Os HELD LOW

70

60

50

40

30

20

10

0

600

550

500

450

400

350

300

250

200

150

100

50

f_SCL= 400 kHz

I/Os unloaded

V_CC= 5 V

T_A= –40°C

T_A= 25°C

T_A= 85°C

0

2.3

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

0

1

2

3

4

5

6

7

8

V_CC– Supply Voltage – V

Number of I/Os Held Low

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TYPICAL CHARACTERISTICS (continued)

I/O OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

vs

TEMPERATURE

30

25

20

15

10

5

300

275

250

225

200

175

150

125

100

75

V_CC= 2.5 V

V_CC= 2.5 V, I_SINK= 10 mA

T_A= –40°C

T_A= 25°C

V_CC= 5 V, I_SINK= 10 mA

T_A= 85°C

V_CC= 2.5 V, I_SINK= 1 mA

V_CC= 5 V, I_SINK= 1 mA

50

25

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

-40

-15

10

35

60

85

V_OL– Output Low Voltage – V

T

_A– Free-Air Temperature – °C

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

60

55

50

45

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

V_CC= 5 V

V_CC= 3.3 V

T_A= –40°C

T_A= 25°C

T_A= 85°C

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_OL– Output Low Voltage – V

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TYPICAL CHARACTERISTICS (continued)

I/O OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

vs

TEMPERATURE

35

30

25

20

15

10

5

275

250

225

200

175

150

125

100

75

V_CC= 2.5 V

V_CC= 2.5 V, I_OL= 10 mA

T_A= –40°C

T_A= 25°C

V_CC= 5 V, I_OL= 10 mA

V_CC= 2.5 V, I_OL= 1 mA

T_A= 85°C

V_CC= 5 V, I_OL= 1 mA

50

25

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

-40

-15

10

35

60

85

(V_CC– V_OH) – Output High Voltage – V

T_A– Free-Air Temperature – °C

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

V_CC= 3.3 V

V_CC= 5 V

T_A= –40°C

T_A= 25°C

T_A= 85°C

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

(V_CC– V_OH) – Output High Voltage – V

16

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TYPICAL CHARACTERISTICS (continued)

OUTPUT HIGH VOLTAGE

vs

SUPPLY VOLTAGE

6

T_A= 25°C

5

4

I_OH= –8 mA

3

I_OH= –10 mA

2

1

0

2.3

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

V_CC– Supply Voltage – V

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PARAMETER MEASUREMENT INFORMATION

V

CC

R

L

= 1 kΩ

SDA

DUT

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

R/W

Bit 0

(LSB)

Data

Bit 07

(MSB)

Data

Bit 10 Condition

(LSB)

Stop

Address

Bit 6

Address

Bit 1

ACK

(A)

(P)

t

scl

t

sch

0.7 × V

0.3 × V

CC

SCL

SDA

CC

t

icr

t

sts

t

PHL

t

icf

t

buf

t

sp

PLH

0.7 × V

0.3 × V

CC

t

icf

t

icr

t

sdh

t

sps

t

sth

t

sds

Repeat

Start

Condition

Stop

Condition

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

1

DESCRIPTION

2

I C address

2, 3

P-port data

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 10. I²C Interface Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

V

CC

R

L

= 4.7 kΩ

INT

DUT

C

L

= 100 pF

(see Note A)

INTERRUPT LOAD CONFIGURATION

ACK

From Slave

ACK

From Slave

Start

Condition

8 Bits

(One Data Bytes)

From Port

R/W

Slave Address

Data From Port

Data 2

S

0

1

0

A2 A1 A0

1

A

Data 1

A

1

P

1

2

3

4

5

6

7

8

A

t

ir

B

t

ir

INT

A

t

iv

t

sps

A

Data

Into

Port

Address

Data 1

Data 2

0.7 ×V

0.3 ×V

CC

0.7 × V

0.3 ×V

CC

SCL

R/W

INT

A

CC

t

iv

t

ir

0.7 ×V

1.5 V

0.3 ×V

0.7 ×V

0.3 ×V

CC

INT

P

n

CC

View A−A

A. C_Lincludes probe and jig capacitance.

View B−B

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 11. Interrupt Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

Pn

500 W

2 ×V

DUT

CC

C

= 50 pF

L

500 W

(see Note A)

P-PORT LOAD CONFIGURATION

0.7 × V

CC

SCL

SDA

P0

A

P7

0.3 ×V

CC

Slave

ACK

t

pv

(see Note B)

P

n

Last Stable Bit

Unstable

Data

WRITE MODE (R/W = 0)

0.7 ×V

0.3 ×V

CC

SCL

P0

A

P7

t

ps

t

ph

0.7 ×V

1.5 V

0.3 ×V

CC

P

n

READ MODE (R/W = 1)

A. C_Lincludes probe and jig capacitance.

B. t_pvis measured from 0.7 × V_CCon SCL to 50% I/O pin output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 12. P-Port Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

V

CC

R

L

= 1 kΩ

Pn

500 W

2 × V

SDA

DUT

CC

DUT

C

= 50 pF

L

500 W

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

P-PORT LOAD CONFIGURATION

Start

SCL

ACK or Read Cycle

SDA

0.3 y V

CC

t

RESET

V /2

CC

t

REC

t

w

Pn

V /2

CC

t

RESET

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 13. Reset Load Circuits and Voltage Waveforms

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APPLICATION INFORMATION

Figure 14 shows an application in which the PCA9554 can be used.

V

CC

100 kW

(y3)

(5 V)

2 kW

10 kW

V

CC

V

CC

Subsystem 1

(e.g., temperature sensor)

SDA

SCL

INT

SDA

P0

P1

Master

SCL

INT

Controller

GND

INT

P2

P3

RESET

Subsystem 2

(e.g., counter)

PCA9554

P4

A

P5

P6

P7

Controlled Device

(e.g., CBT device)

A2

ENABLE

A1

A0

B

GND

ALARM

Subsystem 3

(e.g., alarm system)

V

CC

A. Device address is configured as 0100000 for this example.

B. P0, P2, and P3 are configured as outputs.

C. P1, P4, and P5 are configured as inputs.

D. P6 and P7 are not used and and have internal 100-kΩ pullup resistors to protect them from floating.

Figure 14. Typical Application

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Minimizing I_CCWhen I/Os Control LEDs

When the I/Os are used to control LEDs, they are normally connected to V_CCthrough a resistor as shown in

Figure 14. The LED acts as a diode, so when the LED is off, the I/O V_INis about 1.2 V less than V_CC. ΔI_CCin

Electrical Characteristics shows how I_CCincreases as V_INbecomes lower than V_CC

.

For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to V_CCwhen

the LED is off to minimize current consumption. Figure 15 shows a high-value resistor in parallel with the LED.

Figure 16 shows V_CCless than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O

V_INat or above V_CCand prevent additional supply-current consumption when the LED is off.

V

CC

LED

100 kW

V

CC

LEDx

Figure 15. High-Value Resistor in Parallel With LED

5 V

3.3 V

LED

V

CC

LEDx

Figure 16. Device Supplied by a Lower Voltage

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PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

PCA9554DBR

PCA9554DGVR

PCA9554DWR

PCA9554PWR

SSOP

TVSOP

SOIC

DB

DGV

DW

PW

16

2000

330.0

16.4

12.4

16.4

12.4

8.2

6.8

6.6

4.0

2.5

1.6

2.7

1.6

12.0

8.0

16.0

12.0

16.0

12.0

Q1

10.75 10.7

6.9 5.6

12.0

8.0

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

PCA9554DBR

PCA9554DGVR

PCA9554DWR

PCA9554PWR

SSOP

TVSOP

SOIC

DB

DGV

DW

PW

16

2000

367.0

38.0

35.0

38.0

35.0

TSSOP

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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型号：	PCA9554DWR
厂家：	TEXAS INSTRUMENTS
描述：	REMOTE 8-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS 远程8位I2C和SMBus I / O扩展器，带有中断输出和配置寄存器并行IO端口微控制器和处理器外围集成电路光电二极管输出元件时钟
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PCA9554DWR [TI]

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