PCA9557DTG4 [TI]
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS; 远程8位I2C和SMBus低功耗I / O扩展器,带有复位和配置寄存器型号: | PCA9557DTG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS |
文件: | 总36页 (文件大小:1174K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCA9557
www.ti.com.................................................................................................................................................... SCPS133I–DECEMBER 2005–REVISED JUNE 2008
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH RESET AND CONFIGURATION REGISTERS
1
FEATURES
•
Low Standby Current Consumption of
1 µA Max
I2C to Parallel Port Expander
•
•
•
Internal Power-On Reset
High-Impedance Open Drain on P0
•
•
Power Up With All Channels Configured as
Inputs
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
•
•
•
No Glitch on Power Up
•
•
•
5-V Tolerant I/O Ports
400-kHz Fast I2C Bus
Noise Filter on SCL/SDA Inputs
Latched Outputs With High Current Drive
Maximum Capability for Directly Driving LEDs
Three Hardware Address Pins Allow for Use of
up to Eight Devices on I2C/SMBus
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
Lower-Voltage Higher-Performance Migration
Path for PCA9556
ESD Protection Exceeds JESD 22
•
•
•
Input/Output Configuration Register
Polarity Inversion Register
Active-Low Reset Input
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
RGV PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCL
SDA
A0
16 15 14 13
1
16
2
3
4
5
6
7
15
14
13
12
11
10
SDA
A0
RESET
P7
RESET
P7
1
2
3
4
12
11
10
9
A0
A1
A2
P0
P7
P6
P5
P4
A1
P6
A1
P6
A2
P5
A2
P5
P0
P4
P0
P4
P1
P3
8
9
P1
P3
5
6
7
8
GND
P2
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. The
device provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface
[serial clock (SCL) and serial data (SDA)].
The PCA9557 consists of one 8-bit configuration (input or output selection), input port, output port, and polarity
inversion (active-high) registers. At power on, the I/Os are configured as inputs. However, the system master can
enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or
output is kept in the corresponding input or output register. The polarity of the input port register can be inverted
with the polarity inversion register. All registers can be read by the system master.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low
current consumption.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9557
SCPS133I–DECEMBER 2005–REVISED JUNE 2008.................................................................................................................................................... www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The system master can reset the PCA9557 in the event of a timeout or other improper operation by asserting a
low in the active-low reset (RESET) input. The power-on reset puts the registers in their default state and
initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without
depowering the part.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address, allowing up to eight
devices to share the same I2C bus or SMBus.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
PCA9557RGVR
PCA9557RGYR
PCA9557DR
TOP-SIDE MARKING
PD557
QFN – RGV
QFN – RGY
Reel of 2000
Reel of 1000
Reel of 2500
Reel of 250
Tube of 40
PD557
SOIC – D
PCA9557DT
PCA9557
PD557
PCA9557D
–40°C to 85°C
Reel of 2000
Tube of 80
PCA9557DBR
PCA9557DB
SSOP – DB
Reel of 2000
Reel of 250
Tube of 90
PCA9557PWR
PCA9557PWT
PCA9557PW
TSSOP – PW
TVSOP – DGV
PD557
PD557
Reel of 2000
PCA9557DGVR
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
TERMINAL FUNCTIONS
NO.
QFN (RGY)
SOIC (D),
SSOP (DB),
TSSOP (PW),
AND
NAME
DESCRIPTION
QFN (RGV)
TVSOP (DGV)
1
2
3
4
5
15
16
1
SCL
SDA
A0
Serial clock bus. Connect to VCC through a pullup resistor.
Serial data bus. Connect to VCC through a pullup resistor.
Address input. Connect directly to VCC or ground.
Address input. Connect directly to VCC or ground.
Address input. Connect directly to VCC or ground.
2
A1
3
A2
P-port input/output. High impedance open-drain design structure. Connect to VCC
through a pullup resistor.
6
4
P0
7
5
6
P1
GND
P2
P-port input/output. Push-pull design structure.
Ground
8
9
7
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
10
11
12
13
14
8
P3
9
P4
10
11
12
P5
P6
P7
Active-low reset input. Connect to VCC through a pullup resistor if no active
connection is used.
15
16
13
14
RESET
VCC
Supply voltage
2
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PCA9557
www.ti.com.................................................................................................................................................... SCPS133I–DECEMBER 2005–REVISED JUNE 2008
LOGIC DIAGRAM (POSITIVE LOGIC)
3
A0
4
A1
5
A2
1
2
P7−P0
SCL
SDA
2
Input
Filter
I C-Bus
Shift
Register
I/O
Port
Control
8 Bits
Write Pulse
Read Pulse
16
15
V
Power-On
Reset
CC
RESET
8
GND
A. Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.
B. All I/Os are set to inputs at reset.
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SCPS133I–DECEMBER 2005–REVISED JUNE 2008.................................................................................................................................................... www.ti.com
SIMPLIFIED SCHEMATIC DIAGRAM OF P0
Data From
Shift Register
Configuration
Register
Data From
Shift Register
Q
D
Output Port
Register Data
FF
Write Configuration
Pulse
D
Q
C
K
Q
FF
P0
Write Pulse
C
K
Q
ESD Protection Diode
Output
Port
Register
Input
Port
GND
Register
Input Port
Register Data
D
Q
FF
Read Pulse
C
K
Q
Data From
Shift Register
Polarity
Register Data
D
Q
FF
Write Polarity Pulse
C
K
Q
Polarity
Inversion
Register
A. On power up or reset, all registers return to default values.
4
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PCA9557
www.ti.com.................................................................................................................................................... SCPS133I–DECEMBER 2005–REVISED JUNE 2008
SIMPLIFIED SCHEMATIC DIAGRAM OF P7–P1
Data From
Shift Register
Output Port
Register Data
Configuration
Register
V
CC
Data From
Shift Register
Q
D
FF
Write Configuration
Pulse
D
Q
C
K
Q
FF
P7−P1
Write Pulse
C
K
Q
ESD Protection Diode
Output
Port
Register
Input
Port
GND
Register
Input Port
Register Data
D
Q
FF
Read Pulse
C
K
Q
Data From
Shift Register
Polarity
Register Data
D
Q
FF
Write Polarity Pulse
C
K
Q
Polarity
Inversion
Register
A. On power up or reset, all registers return to default values.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address byte
is sent, most-significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (A2–A0) inputs of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 2).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
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A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line Change
Figure 2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Clock Pulse for
Condition
Acknowledgment
Figure 3. Acknowledgment on the I2C Bus
Interface Definition
BIT
BYTE
7 (MSB)
6
L
5
H
4
H
3
2
1
0 (LSB)
I2C slave address
Px I/O data bus
L
A2
P3
A1
P2
A0
P1
R/W
P0
P7
P6
P5
P4
6
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www.ti.com.................................................................................................................................................... SCPS133I–DECEMBER 2005–REVISED JUNE 2008
Device Address
The address of the PCA9557 is shown in Figure 4.
Slave Address
0
0
1
1 A2 A1 A0
R/W
Fixed
Programmable
Figure 4. PCA9557 Address
Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
L
A1
L
A0
L
24 (decimal), 18 (hexadecimal)
25 (decimal), 19 (hexadecimal)
26 (decimal), 1A (hexadecimal)
27 (decimal), 1B (hexadecimal)
28 (decimal), 1C (hexadecimal)
29 (decimal), 1D (hexadecimal)
30 (decimal), 1E (hexadecimal)
31 (decimal), 1F (hexadecimal)
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9557. Two bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a new command byte has been sent, the register that was addressed continues to be accessed by reads
until a new command byte has been sent.
0
0
0
0
0
0
B1 B0
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
COMMAND BYTE
(HEX)
POWER-UP
DEFAULT
REGISTER
PROTOCOL
B1
0
B0
0
0x00
0x01
0x02
0x03
Input Port
Output Port
Read byte
xxxx xxxx
0000 0000
1111 0000
1111 1111
0
1
Read/write byte
Read/write byte
Read/write byte
1
0
Polarity Inversion
Configuration
1
1
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Register Descriptions
The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to signal the I2C device that the
input port register will be accessed next.
Register 0 (Input Port Register)
BIT
I7
X
I6
X
I5
X
I4
X
I3
X
I2
X
I1
X
I0
X
DEFAULT
The output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 (Output Port Register)
BIT
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
DEFAULT
The polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration
register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Register 2 (Polarity Inversion Register)
BIT
N7
1
N6
1
N5
1
N4
1
N3
0
N2
0
N1
0
N0
0
DEFAULT
The configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register)
BIT
C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
1
DEFAULT
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9557 in a reset condition until
VCC has reached VPOR. At that time, the reset condition is released, and the PCA9557 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and back up to the
operating voltage for a power-reset cycle. The RESET input can be asserted to reset the system, while keeping
the VCC at its operating level.
RESET
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA9557 registers and
I2C/SMBus state machine are held in their default states until RESET again is high. This input requires a pullup
resistor to VCC if no active connection is used.
8
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www.ti.com.................................................................................................................................................... SCPS133I–DECEMBER 2005–REVISED JUNE 2008
Bus Transactions
Data is exchanged between the master and PCA9557 through write and read commands.
Writes
Data is transmitted to the PCA9557 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission (see Figure 6 and Figure 7).
SCL
1
2
3
4
5
6
7
8
9
Slave Address
Command Byte
Data to Port
Data 1
0
SDA
S
0
1
1
A2 A1 A0
0
A
0
0
0
0
0
0
0
1
A
A
P
Start Condition
R/W ACK From Slave
ACK From Slave
ACK From Slave
Write to Port
Data Out
From Port
Data 1 Valid
t
pv
Figure 6. Write to Output Port Register
<br/>
SCL
9
1
2
3
4
5
6
7
8
0
Slave Address
Command Byte
Data to Register
Data
SDA
S
0
0
1
1 A2 A1 A0
A
0
0
0
0
0
0
0
1/0
A
A
P
Start Condition
R/W ACK From Slave
ACK From Slave
ACK From Slave
Figure 7. Write to Configuration or Polarity Inversion Registers
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Reads
The bus master first must send the PCA9557 address with the LSB set to a logic 0 (see Figure 4 for device
address). The command byte is sent after the address and determines which register is accessed. After a restart,
the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the
command byte then is sent by the PCA9557 (see Figure 8 and Figure 9). After a restart, the value of the register
defined by the command byte matches the register being accessed when the restart occurred. Data is clocked
into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes
received in one read transmission, but when the final byte is received, the bus master must not acknowledge the
data.
ACK From
Master
ACK From
Slave
ACK From
Slave
ACK From
Slave
Data from Register
Slave Address
Slave Address
Command Byte
A
S
A
0
0
1
1 A2 A1 A0
1
A
Data
S
0
0
1
1 A2 A1 A0
0
A
First Byte
R/W
R/W
At this moment, master-transmitter
becomes master-receiver, and
slave-receiver becomes
slave-transmitter
NACK From
Master
Data from Register
Data
NA P
Last Byte
Figure 8. Read From Register
<br/>
1
2
3
4
5
6
7
8
9
SCL
SDA
Data From Port
Data 1
Slave Address
Data From Port
Data 4
S
0
0
1
1
A2 A1 A0
R/W
1
A
A
NA P
Start
Condition
NACK From
Master
ACK From
Slave
ACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
Data 3
Data 4
Data 5
t
ph
t
ps
A. This figure assumes the command byte has been previously programmed with 00h.
B. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last
acknowledge phase is valid (output mode). Input data is lost.
C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8).
Figure 9. Read Input Port Register
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)
6
V
VO
IIK
6
V
Input clamp current
VI < 0
–20
–20
–20
50
mA
mA
µA
mA
mA
IOK
IIOK
IOL
IOH
Output clamp current
VO < 0
Input/output clamp current
Continuous output low current
Continuous output high current
Continuous current through GND
Continuous current through VCC
VO < 0 or VO > VCC
VO = 0 to VCC
VO = 0 to VCC
–50
–250
160
73
ICC
mA
D package
DB package
DGV package
PW package
RGV package
RGY package
82
120
108
51
θJA
Package thermal impedance(3)
°C/W
°C
47
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
MIN
2.3
MAX
5.5
UNIT
VCC
VIH
Supply voltage
V
SCL, SDA
0.7 × VCC
2
5.5
High-level input voltage
V
V
A2–A0, P7–P0, RESET
SCL, SDA
5.5
–0.5
0.3 × VCC
0.8
VIL
Low-level input voltage
A2–A0, P7–P0, RESET
P7–P1
–0.5
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
–10
mA
mA
°C
P7–P0
25
–40
85
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
VCC
2.3 V to 5.5 V
VPOR
MIN TYP(1)
MAX UNIT
VIK
Input diode clamp voltage
Power-on reset voltage
–1.2
1.65
1.8
2.6
3
V
VPOR
VI = VCC or GND, IO = 0
2.1
V
2.3 V
3 V
IOH = –8 mA
4.5 V
4.75 V
2.3 V
4.1
1.5
2.5
3
VOH
P-port high-level output voltage(2)
V
3 V
IOH = –10 mA
4.5 V
4.75 V
2.3 V to 5.5 V
4
SDA
VOL = 0.4 V
VOL = 0.5 V
VOL = 0.55 V
VOL = 0.7 V
VOH = 2.3 V
VOH = 4.6 V
VOH = 3.3 V
3
8
8
20
20
24
IOL
mA
P port(3)
2.3 V to 5.5 V
10
–4
P port, except for P0(3)
P0(3)
2.3 V to 5.5 V
4.6 V to 5.5 V
3.3 V to 5.5 V
mA
IOH
1
1
µA
SCL, SDA
A2–A0, RESET
P port
±1
±1
1
II
VI = VCC or GND
2.3 V to 5.5 V
µA
IIH
IIL
VI = VCC
2.3 V to 5.5 V
2.3 V to 5.5 V
5.5 V
µA
µA
P port
VI = GND
1
19
12
25
22
20
5
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz
3.6 V
2.7 V
8
Operating mode
5.5 V
1.5
1
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 100 kHz
ICC
3.6 V
4
µA
2.7 V
0.6
0.25
0.25
0.2
3
5.5 V
1
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 0 kHz
Standby mode
3.6 V
0.9
0.8
2.7 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
0.2
0.4
ΔICC
Additional current in Standby mode
mA
Every LED I/O at VI = 4.3 V,
fSCL = 0 kHz
5.5 V
CI
SCL
VI = VCC or GND
2.3 V to 5.5 V
4
5.5
7.5
6
8
pF
pF
SDA
P port
Cio
VIO = VCC or GND
2.3 V to 5.5 V
9.5
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
(2) The total current sourced by all I/Os must be limited to 85 mA per bit.
(3) Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7–P0) must be limited to a maximum current of 200 mA.
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I2C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial data setup time
I2C serial data hold time
I2C input rise time
100
400
kHz
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
4
0.6
1.3
4.7
50
50
tsds
tsdh
ticr
250
0
100
0
(1)
1000
300
20 + 0.1Cb
300
300
300
(1)
(1)
ticf
I2C input fall time
20 + 0.1Cb
20 + 0.1Cb
tocf
tbuf
tsts
tsth
tsps
I2C output fall time, 10-pF to 400-pF bus
I2C bus free time between Stop and Start
I2C Start or repeated Start condition setup time
I2C Start or repeated Start condition hold time
I2C Stop condition setup time
300
4.7
4.7
4
1.3
0.6
0.6
0.6
4
tvd(data) Valid data time, SCL low to SDA output valid
1
1
0.9
0.9
Valid data time of ACK condition, ACK signal from SCL low to
SDA (out) low
tvd(ack)
µs
Cb
I2C bus capacitive load
400
400
pF
(1) Cb = total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
16
MAX
MIN
16
MAX
tW
Reset pulse duration(1)
Reset recovery time
Time to reset(2)
ns
ns
ns
tREC
tRESET
0
0
400
400
(1) A pulse duration of 16 ns minimum must be applied to RESET to return the PCA9557 to its default state.
(2) The PCA9557 requires a minimum of 400 ns to be reset.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
PARAMETER
FROM
TO
UNIT
MIN
MAX
250
MIN
MAX
250
SCL
SCL
P0
P1–P7
SCL
tpv Output data valid
ns
200
200
tps Input data setup time
tph Input data hold time
P port
P port
0
0
ns
ns
SCL
200
200
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SCPS133I–DECEMBER 2005–REVISED JUNE 2008.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
STANDBY SUPPLY CURRENT
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
vs
TEMPERATURE
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
SCL = VCC
VCC = 5 V
fSCL = 400 kHz
I/Os unloaded
fSCL = 400 kHz
I/Os unloaded
VCC = 5 V
VCC = 3.3 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 2.5 V
0
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
VCC – Supply Voltage – V
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
TA = –40°C
TA = –40°C
TA = –40°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
TA = 85°C
0
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VOL – Output Low Voltage – V
VOL – Output Low Voltage – V
VOL – Output Low Voltage – V
I/O SOURCE CURRENT
I/O SOURCE CURRENT
I/O SOURCE CURRENT
vs
vs
vs
OUTPUT HIGH VOLTAGE
(P7–P1)
OUTPUT HIGH VOLTAGE
(P7–P1)
OUTPUT HIGH VOLTAGE
(P7–P1)
20
15
10
5
40
35
30
25
20
15
10
5
30
25
20
15
10
5
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
TA = –40°C
TA = –40°C
TA = –40°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
TA = 85°C
0
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
(VCC – VOH) – Output High Voltage – V
(VCC – VOH) – Output High Voltage – V
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TYPICAL CHARACTERISTICS (continued)
OUTPUT HIGH VOLTAGE
OUTPUT HIGH VOLTAGE
vs
vs
OUTPUT LOW VOLTAGE
vs
SUPPLY VOLTAGE
(P7–P1)
TEMPERATURE
(P7–P1)
TEMPERATURE
600
550
500
450
400
350
300
250
200
150
100
50
6
5
4
3
2
1
0
300
275
250
225
200
175
150
125
100
75
VCC = 2.5 V, ISINK = 10 mA
TA = 25°C
VCC = 2.5 V, ISOURCE = 10
IOH = –4 mA
VCC = 5 V, ISINK = 10 mA
VCC = 5 V, ISOURCE = 10
IOH = –8 mA
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
IOH = –10 mA
VCC = 2.5 V, ISOURCE = 1 mA
VCC = 5 V, ISOURCE = 1 mA
50
25
0
0
-50
-25
0
25
50
75
100
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-50
-25
0
25
50
75
100
TA – Free-Air Temperature – °C
VCC – Supply Voltage – V
TA – Free-Air Temperature – °C
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SCPS133I–DECEMBER 2005–REVISED JUNE 2008.................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
= 1 kΩ
SDA
DUT
C
L
= 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
R/W
Bit 0
(LSB)
Data
Bit 07
(MSB)
Data
Bit 10 Condition
(LSB)
Stop
Address
Bit 6
Address
Bit 1
ACK
(A)
(P)
t
scl
t
sch
0.7 × V
0.3 × V
CC
SCL
SDA
CC
t
icr
t
sts
t
PHL
t
icf
t
buf
t
t
sp
PLH
0.7 × V
0.3 × V
CC
CC
t
icf
t
icr
t
sdh
t
sps
t
sth
t
sds
Repeat
Start
Condition
Stop
Condition
Start or
Repeat
Start
Condition
VOLTAGE WAVEFORMS
BYTE
1
DESCRIPTION
2
I C address
2, 3
P-port data
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
R
L
= 4.7 kΩ
INT
DUT
C
L
= 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
ACK
From Slave
Start
Condition
8 Bits
(One Data Bytes)
From Port
R/W
Slave Address
Data From Port
Data 2
S
0
0
1
1
A2 A1 A0
1
A
Data 1
A
1
P
1
2
3
4
5
6
7
8
A
A
t
ir
B
B
t
ir
INT
A
t
iv
t
sps
A
Data
Into
Port
Address
Data 1
Data 2
0.7 × V
0.3 × V
CC
0.7 × V
0.3 × V
CC
SCL
R/W
INT
A
CC
CC
t
iv
t
ir
0.7 × V
0.7 × V
0.3 × V
CC
CC
INT
1.5 V
Pn
0.3 × V
CC
CC
View A−A
A. CL includes probe and jig capacitance.
View B−B
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
Pn
500 W
2 × V
DUT
CC
C
= 50 pF
L
500 W
(see Note A)
P-PORT LOAD CONFIGURATION
0.7 × V
CC
SCL
P0
A
P7
0.3 × V
CC
Slave
ACK
SDA
Pn
t
pv
(see Note B)
Last Stable Bit
Unstable
Data
WRITE MODE (R/W = 0)
0.7 × V
0.3 × V
CC
SCL
Pn
P0
A
P7
CC
t
ps
t
ph
0.7 × V
1.5 V
CC
0.3 × V
CC
READ MODE (R/W = 1)
A. CL includes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 12. P-Port Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
R
L
= 1 kΩ
Pn
500 W
2 × V
SDA
DUT
CC
DUT
C
= 50 pF
L
500 W
C
L
= 50 pF
(see Note A)
(see Note A)
SDA LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y V
CC
t
RESET
RESET
V /2
CC
t
REC
t
w
Pn
V /2
CC
t
RESET
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. I/Os are configured as inputs.
D. All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
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SCPS133I–DECEMBER 2005–REVISED JUNE 2008.................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
Figure 14 shows an application in which the PCA9557 can be used.
V
CC
(5 V)
620 Ω
100 kΩ (X 5)
V
CC
1.8 kΩ
1.8 kΩ
2 kΩ
2 kΩ
V
CC
SCL
SDA
SCL
SDA
P0
Subsystem 1
INT
Master
Controller
P1
RESET
RESET
P2
P3
RESET
Subsystem 2
(e.g., Counter)
GND
PCA9557
P4
P5
P6
P7
A
A2
Controlled Switch
(e.g., CBT Device)
ENABLE
A1
A0
B
GND
ALARM
Subsystem 3
(e.g., Alarm System)
GND
10 kΩ
A. Device address is configured as 0011100 for this example.
B. P1, P4, and P5 are configured as inputs.
C. P0, P2, and P3 are configured as outputs.
D. P6 and P7 are not used and must be configured as outputs.
Figure 14. Typical Application
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Minimizing ICC When I/O Is Used to Control LED
When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 14.
The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC parameter in
Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs needing to minimize
current consumption, such as battery power applications, should consider maintaining the I/O pins greater than
or equal to VCC when the LED is off.
Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply-current consumption when the LED is off.
V
CC
100 kW
LED
V
CC
Pn
Figure 15. High-Value Resistor in Parallel With the LED
3.3 V
5 V
LED
V
CC
Pn
Figure 16. Device Supplied by a Low Voltage
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2008
PACKAGING INFORMATION
Orderable Device
PCA9557D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9557DB
SSOP
SSOP
SSOP
SSOP
SOIC
DB
DB
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9557DBG4
PCA9557DBR
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9557DBRG4
PCA9557DG4
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9557DGVR
PCA9557DGVRG4G4
PCA9557DR
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9557DRG4
PCA9557DT
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9557DTG4
PCA9557PW
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
PW
PW
PW
PW
RGV
RGV
RGY
RGY
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9557PWG4
PCA9557PWR
PCA9557PWRG4
PCA9557PWT
PCA9557PWTG4
PCA9557RGVR
PCA9557RGVRG4
PCA9557RGYR
PCA9557RGYRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2008
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
PCA9557DBR
PCA9557DGVR
PCA9557DR
SSOP
TVSOP
SOIC
DB
DGV
D
16
16
16
16
16
16
2000
2000
2500
2000
2500
1000
330.0
330.0
330.0
330.0
330.0
180.0
16.4
12.4
16.4
12.4
12.4
12.4
8.2
6.8
6.5
7.0
4.3
3.8
6.6
4.0
10.3
5.6
4.3
4.3
2.5
1.6
2.1
1.6
1.5
1.5
12.0
8.0
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q2
Q1
PCA9557PWR
PCA9557RGVR
PCA9557RGYR
TSSOP
QFN
PW
RGV
RGY
QFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCA9557DBR
PCA9557DGVR
PCA9557DR
SSOP
TVSOP
SOIC
DB
DGV
D
16
16
16
16
16
16
2000
2000
2500
2000
2500
1000
346.0
346.0
346.0
346.0
346.0
190.5
346.0
346.0
346.0
346.0
346.0
212.7
33.0
29.0
33.0
29.0
29.0
31.8
PCA9557PWR
PCA9557RGVR
PCA9557RGYR
TSSOP
QFN
PW
RGV
RGY
QFN
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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