PCF8575PWG4 [TI]

REMOTE 16-BIT I2C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT; 远程16位I2C和SMBus I / O EXPANDERWITH中断输出


型号：	PCF8575PWG4
厂家：	TEXAS INSTRUMENTS
描述：	REMOTE 16-BIT I2C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT 远程16位I2C和SMBus I / O EXPANDERWITH中断输出并行IO端口微控制器和处理器外围集成电路光电二极管输出元件时钟
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中文：	中文翻译
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PCF8575

REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT

www.ti.com

SCPS121D–JANUARY 2005–REVISED APRIL 2007

FEATURES

•

Low Standby-Current Consumption of

Capability for Directly Driving LEDs

10 µA Max

•

Current Source to V_CCfor Actively Driving a

High at the Output

•

I²C to Parallel-Port Expander

Open-Drain Interrupt Output

Compatible With Most Microcontrollers

400-kHz Fast I²C Bus

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

Address by Three Hardware Address Pins for

Use of up to Eight Devices

•

Latched Outputs With High-Current Drive

1000-V Charged-Device Model (C101)

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

RGE PACKAGE

(TOP VIEW)

INT

SDA

SCL

24 23 22 21 20 19

18 A0

P00

P01

P03

P04

P05

P00

P01

P02

P03

P04

P05

P06

P07

GND

17 P17

P17

P16

P15

P14

P13

P12

P11

P10

16 P16

15 P15

14 P14

13 P13

8 9 10 11 12

DESCRIPTION/ORDERING INFORMATION

This 16-bit I/O expander for the two-line bidirectional bus (I²C) is designed for 2.5-V to 5.5-V V_CCoperation.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

PCF8575DBR

TOP-SIDE MARKING

PF575

SSOP – DB

Reel of 2000

QSOP – DBQ

TVSOP – DGV

Reel of 2500

Reel of 2000

Tube of 25

PCF8575DBQR

PCF8575DGVR

PCF8575DW

PCF8575

PF575

–40°C to 85°C

SOIC – DW

PCF8575

Reel of 2000

Tube of 60

PCF8575DWR

PCF8575PW

TSSOP – PW

QFN – RGE

PF575

Reel of 1200

Reel of 3000

PCF8575PWR

PCF8575RGER

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PCF8575

REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT

www.ti.com

SCPS121D–JANUARY 2005–REVISED APRIL 2007

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

The PCF8575 provides general-purpose remote I/O expansion for most microcontroller families via the I²C

interface serial clock (SCL) and serial data (SDA).

The device features a 16-bit quasi-bidirectional input/output (I/O) port (P07–P00, P17–P10), including latched

outputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as

an input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode,

only a current source (I_OH) to V_CCis active. An additional strong pullup to V_CC(I_OHT) allows fast-rising edges into

heavily loaded outputs. This device turns on when an output is written high and is switched off by the negative

edge of SCL. The I/Os should be high before being used as inputs. After power on, as all the I/Os are set high,

all of them can be used as inputs. Any change in setting of the I/Os as either input or outputs can be done with

the write mode. If a high is applied externally to an I/O that has been written earlier to low, a large current (I_OL

)

will flow to GND.

The PCF8575 provides an open-drain interrupt (INT) output, which can be connected to the interrupt input of a

microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After

time, t_iv, the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port

is changed to the original setting, or data is read from or written to the port that generated the interrupt.

Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal or in the

write mode at the ACK bit after the falling edge of the SCL signal. Interrupts that occur during the ACK clock

pulse can be lost (or be very short), due to the resetting of the interrupt during this pulse. Each change of the

I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not

affect the interrupt circuit.

By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data

on its ports, without having to communicate via the I²C bus. Thus, the PCF8575 can remain a simple slave

device.

Every data transmission to or from the PCF8575 must consist of an even number of bytes. The first data byte in

every pair refers to port 0 (P07–P00), and the second data byte in every pair refers to port 1 (P17–P10). To

write to the ports (output mode), the master first addresses the slave device, setting the last bit of the byte

containing the slave address to logic 0. The PCF8575 acknowledges, and the master sends the first data byte

for P07–P00. After the first data byte is acknowledged by the PCF8575, the second data byte (P17–P10) is sent

by the master. Once again, the PCF8575 acknowledges the receipt of the data, after which this 16-bit data is

presented on the port lines.

The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is

overwritten. When the PCF8575 receives the pairs of data bytes, the first byte is referred to as P07–P00 and the

second byte as P17–P10. The third byte is referred to as P07–P00, the fourth byte as P17–P10, and so on.

Before reading from the PCF8575, all ports desired as input should be set to logic 1. To read from the ports

(input mode), the master first addresses the slave device, setting the last bit of the byte containing the slave

address to logic 1. The data bytes that follow on the SDA are the values on the ports. If the data on the input

port changes faster than the master can read, this data may be lost.

When power is applied to V_CC, an internal power-on reset holds the PCF8575 in a reset state until V_CChas

reached V_POR. At that time, the reset condition is released, and the device I²C-bus state machine initializes the

bus to its default state.

The hardware pins (A0, A1, and A2) are used to program and vary the fixed I²C address and allow up to eight

devices to share the same I²C bus or SMBus. The fixed I²C address of the PCF8575 is the same as the

PCF8575C, PCF8574, PCA9535, and PCA9555, allowing up to eight of these devices, in any combination, to

share the same I²C bus or SMBus.

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PCF8575

REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

TERMINAL FUNCTIONS

NO.

NAME

FUNCTION

DB, DBQ, DGV,

DW, AND PW

RGE

INT

Interrupt output. Connect to V_CCthrough a pullup resistor.

Address input 1. Connect directly to V_CCor ground. Pullup resistors are not needed.

Address input 2. Connect directly to V_CCor ground. Pullup resistors are not needed.

P-port input/output. Push-pull design structure.

Ground

P00

P01

P02

P03

P04

P05

P06

P07

GND

P10

P11

P12

P13

P14

P15

P16

P17

P-port input/output. Push-pull design structure.

Address input 0. Connect directly to V_CCor ground. Pullup resistors are not needed.

Serial clock line. Connect to V_CCthrough a pullup resistor

Serial data line. Connect to V_CCthrough a pullup resistor.

Supply voltage

SCL

SDA

V_CC

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REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

LOGIC DIAGRAM (POSITIVE LOGIC)

PCF8575

Interrupt

Logic

LP Filter

INT

P07−P00

P17−P10

SCL

SDA

Input

Filter

I C Bus

Shift

I/O

Port

16 Bits

Control

Write Pulse

Read Pulse

Power-On

Reset

GND

SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT

Write Pulse

100 µA

OHT

Data From

Shift Register

P07−P00

P17−P10

Power-On

Reset

GND

Read Pulse

To Interrupt

Logic

Data To

Shift Register

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REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). This device does not respond

to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on

the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A2–A0) of the slave

device must not be changed between the Start and Stop conditions.

The data byte follows the address ACK. If the R/W bit is high, the data from this device are the values read from

the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is

followed by an ACK sent from this device. If other data bytes are sent from the master, following the ACK, they

are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output

data is valid at time (t_pv) after the low-to-high transition of SCL, during the clock cycle for the ACK.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 2).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

The number of data bytes transferred between the Start and Stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the

receiver can send an ACK bit.

A slave receiver that is addressed must generate an ACK after the reception of each byte. Also, a master must

generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device

that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low

during the high pulse of the ACK-related clock period (see Figure 3). Setup and hold times must be taken into

account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after

the last byte that has been clocked out of the slave. This is done by the master receiver by holding the SDA line

high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

SDA

SCL

Start Condition

Stop Condition

Figure 1. Definition of Start and Stop Conditions

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REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

SDA

SCL

Data Line

Stable;

Change

of Data

Data Valid

Allowed

Figure 2. Bit Transfer

Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL from

Master

Start

Clock Pulse for

Condition

Acknowledgment

Figure 3. Acknowledgment on I²C Bus

Interface Definition

BIT

BYTE

7 (MSB)

0 (LSB)

I²C slave address

P0x I/O data bus

P1x I/O data bus

R/W

P00

P10

P07

P06

P16

P05

P15

P04

P14

P03

P13

P02

P12

P01

P11

P17

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REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

Figure 4 and Figure 5 show the address and timing diagrams for the write and read modes, respectively.

Integral Multiples of Two Bytes

SCL

ACK

From Slave

Start

Condition

ACK

From Slave

ACK

From Slave

R/W

Slave Address (PCF8575)

Data to Port 0

Data to Port 1

SDA

A2 A1 A0

P07 P06

P00

P17

P10 A

P05

Write to

Port

Data A0

and B0

Valid

Data Output

Voltage

P05 Output

Voltage

P05 Pullup

Output

OHT

Current

INT

Figure 4. Write Mode (Output)

SCL

ACK

From Master

ACK

From Slave

ACK

From Master

R/W

P07 P06 P05 P04 P03 P02 P01 P00

P17 P16 P15 P14 P13 P12 P11 P10

SDA

P07 P06

A1 A0

Read From

Port

Data Into

Port

P17 to P10

P07 to P00

P17 to P10

P07 to P00

INT

A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment by

a stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.

Figure 5. Read Mode (Input)

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REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

Address Reference

INPUTS

I²C BUS SLAVE ADDRESS

32 (decimal), 20 (hexadecimal)

33 (decimal), 21 (hexadecimal)

34 (decimal), 22 (hexadecimal)

35 (decimal), 23 (hexadecimal)

36 (decimal), 24 (hexadecimal)

37 (decimal), 25 (hexadecimal)

38 (decimal), 26 (hexadecimal)

39 (decimal), 27 (hexadecimal)

Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

6.5

UNIT

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

Output voltage range⁽²⁾

V_CC+ 0.5

–20

V_O

I_IK

Input clamp current

V_I< 0

I_OK

I_OL

I_OH

Output clamp current

V_O< 0

Input/output clamp current

Continuous output low current

Continuous output high current

Continuous current through V_CCor GND

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

–4

±100

DB package

DBQ package

DGV package

DW package

PW package

RGE package

θ_JA

Package thermal impedance⁽³⁾

°C/W

T_stg

Storage temperature range

–65

150

°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions

MIN

2.5

MAX

5.5

UNIT

V_CC

V_IH

V_IL

Supply voltage

High-level input voltage

0.7 × V_CC

–0.5

V_CC+ 0.5

0.3 × V_CC

–1

Low-level input voltage

I_OH

I_OHT

I_OL

P-port high-level output current

P-port transient pullup current

P-port low-level output current

Operating free-air temperature

°C

–10

T_A

–40

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REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_I= –18 mA

V_CC

2.5 V to 5.5 V

V_POR

MIN TYP⁽¹⁾

MAX

UNIT

V_IK

Input diode clamp voltage

V_PORPower-on reset voltage⁽²⁾

–1.2

1.2

V_I= V_CCor GND, I_O= 0

V_O= GND

1.8

I_OHP port

2.5 V to 5.5 V

2.5 V

–30

–300

µA

I_OHTP-port transient pullup current

SDA

High during ACK, V_OH= GND

V_OL= 0.4 V

–0.5

–1

V_OL= 0.4 V

I_OL

P port

2.5 V to 5.5 V

V_OL= 1 V

1.6

INT

V_OL= 0.4 V

SCL, SDA

A0, A1, A2

P port

±5

±1

I_I

V_I= V_CCor GND

2.5 V to 5.5 V

µA

I_IHL

V_I≥ V_CCor V_I≤ GND

2.5 V to 5.5 V

5.5 V

±400

200

100

V_I= V_CCor GND, I_O= 0,

f_scl= 400 kHz

Operating mode

Standby mode

3.6 V

2.7 V

I_CC

µA

5.5 V

2.5

V_I= V_CCor GND, I_O= 0, f_scl= 0 kHz

3.6 V

2.7 V

One input at V_CC– 0.6 V,

Other inputs at V_CCor GND

∆I_CCSupply current increase

2.5 V to 5.5 V

200

µA

C_I

SCL

V_I= V_CCor GND

SDA

P port

C_io

V_IO= V_CCor GND

2.5 V to 5.5 V

(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V_CC) and T_A= 25°C.

(2) The power-on reset circuit resets the I²C bus logic with V_CC< V_PORand sets all I/Os to logic high (with current source to V_CC).

I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6)

MIN

MAX UNIT

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial data setup time

I²C serial data hold time

I²C input rise time

I²C input fall time

I²C output fall time

I²C bus free time between Stop and Start

I²C start or repeated Start condition setup

I²C start or repeated Start condition hold

I²C Stop condition setup

Valid-data time

400

kHz

µs

0.6

1.3

t_sds

t_sdh

t_icr

100

(1)

20 + 0.1C_b

300

(1)

t_icf

20 + 0.1C_b

t_ocf

t_buf

t_sts

t_sth

t_sps

t_vd

10-pF to 400-pF bus

1.3

0.6

SCL low to SDA output valid

1.2

C_b

I²C bus capacitive load

400

(1) C_b= total bus capacitance of one bus line in pF

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Switching Characteristics

over recommended operating free-air temperature range, C_L≤ 100 pF (unless otherwise noted) (see Figure 7 and Figure 8)

FROM

(INPUT)

(OUTPUT)

PARAMETER

MIN

MAX

UNIT

t_iv

t_ir

Interrupt valid time

Interrupt reset delay time

Output data valid

P port

SCL

INT

µs

t_pv

t_su

t_h

SCL

P port

SCL

Input data setup time

Input data hold time

P port

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TYPICAL OPERATING CHARACTERISTICS

T_A= 25°C (unless otherwise noted)

Standby Supply Current

Supply Current

vs Supply Voltage

Supply Current

vs Temperature

100

120

SCL = V

= 400 kHz

All I/Os unloaded

= 400 kHz

All I/Os unloaded

SCL

All I/Os unloaded

100

= 5 V

= 2.5 V

= 3.3 V

= 2.5 V

−50 −25

25 50 75 100 125

−50 −25

25 50 75 100 125

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Temperature (5C)

Supply Voltage (V)

I/O Sink Current

vs Output Low Voltage

= 2.5 V

= 3.3 V

= 5 V

= −40_C

= 25_C

= 85_C

0.0 0.1 0.2 0.3 0.4 0.5 0.6

(V)

Vol (V)

I/O Source Current

vs Output High Voltage

I/O Source Current

vs Output High Voltage

I/O Output Low Voltage

vs Temperature

600

500

400

300

200

100

= 2.5 V

= 3.3 V

= −40_C

= 25_C

= 5 V, I

= 10 mA

SINK

= −40_C

= 25_C

= 2.5 V, I

= 10 mA

= 5 V,

SINK

= 2.5 V,

= 1 mA

SINK

= 85_C

= 1 mA

SINK

−50 −25

25 50 75 100 125

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Temperature (5C)

− V (V)

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I/O Source Current

vs Output High Voltage

I/O High Voltage

vs Temperature

350

300

250

200

150

100

= 5 V

= −40_C

= 5 V

= 25_C

= 3.3 V

= 2.5 V

= 85_C

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

−50 −25

25 50 75 100 125

Temperature (5C)

− V (V)

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

PARAMETER MEASUREMENT INFORMATION

= 1 kΩ

SDA

DUT

= 50 pF

SDA LOAD CONFIGURATION

3 Bytes for Complete Device

Programming

Stop

Start

Address

Bit 7

(MSB)

R/W

Bit 0

(LSB)

Data

Bit 07

(MSB)

Data

Bit 10 Condition

(LSB)

Stop

ACK

(A)

Address

Bit 6

Address

Bit 1

Condition Condition

(P) (S)

(P)

scl

sch

0.7 × V

0.3 × V

SCL

SDA

icr

sts

PHL

icf

buf

PLH

0.7 × V

0.3 × V

icf

icr

sdh

sps

sth

sds

Repeat

Start

Condition

Stop

Condition

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

DESCRIPTION

I C address

2, 3

P-port data

Figure 6. I²C Interface Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

= 4.7 kΩ

INT

DUT

= 100 pF

INTERRUPT LOAD CONFIGURATION

ACK

From Slave

ACK

From Slave

Start

Condition

16 Bits

(2 Data Bytes)

R/W

From Port

Slave Address (PCF8575)

Data From Port

Data 3

A A

1 0

Data 1

Data 2

INT

sps

Data

Into

Port

Address

Data 1

Data 2

Data 3

0.7 × V

0.3 × V

0.7 × V

0.3 × V

SCL

INT

R/W

0.7 × V

0.3 × V

View A−A

View B−B

Figure 7. Interrupt Load Circuit and Voltage Waveforms

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SCPS121D–JANUARY 2005–REVISED APRIL 2007

PARAMETER MEASUREMENT INFORMATION (continued)

R = 1 kΩ

R = 4.7 kΩ

SDA

INT

DUT

C = 50 pF

C = 100 pF

GND

INTERRUPT LOAD CONFIGURATION

GND

P-PORT LOAD CONFIGURATION

SDA LOAD CONFIGURATION

0.7 × V

0.3 × V

SCL

SDA

P00

P17

Slave

ACK

Last Stable Bit

Unstable

Data

Write-Mode Timing (R/W = 0)

0.7 × V

0.3 × V

SCL

P00

P17

0.7 × V

0.3 × V

Read-Mode Timing (R/W = 1)

Figure 8. P-Port Load Circuits and Voltage Waveforms

Submit Documentation Feedback

PCF8575

REMOTE 16-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT

www.ti.com

SCPS121D–JANUARY 2005–REVISED APRIL 2007

THERMAL PAD MECHANICAL DATA

RGE (S-PQFP-N24)

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

16-Aug-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

PCF8575DBQR

PCF8575DBQRE4

PCF8575DBQRG4

PCF8575DBR

ACTIVE

SSOP

TVSOP

SOIC

DBQ

2500

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

PCF8575DBRE4

PCF8575DBRG4

PCF8575DGVR

PCF8575DGVRE4

PCF8575DGVRG4

PCF8575DW

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

DGV

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

PCF8575DWG4

PCF8575DWR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2000

Green (RoHS

& no Sb/Br)

PCF8575DWRG4

PCF8575PW

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

Green (RoHS

& no Sb/Br)

PCF8575PWE4

PCF8575PWG4

PCF8575PWR

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Aug-2012

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

PCF8575PWRE4

PCF8575PWRG4

PCF8575RGER

TSSOP

VQFN

2000

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

RGE

Green (RoHS

& no Sb/Br)

PCF8575RGERG4

VQFN

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

PCF8575DBQR

PCF8575DBR

PCF8575DGVR

PCF8575DWR

PCF8575PWR

PCF8575RGER

SSOP

TVSOP

SOIC

DBQ

2500

2000

3000

330.0

16.4

12.4

24.4

16.4

12.4

6.5

8.2

6.9

9.0

8.8

5.6

2.1

2.5

1.6

2.7

1.6

1.15

8.0

12.0

8.0

16.0

12.0

24.0

16.0

12.0

DGV

10.75 15.7

12.0

8.0

TSSOP

VQFN

6.95

4.25

8.3

RGE

4.25

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

PCF8575DBQR

PCF8575DBR

PCF8575DGVR

PCF8575DWR

PCF8575PWR

PCF8575RGER

SSOP

TVSOP

SOIC

DBQ

2500

2000

3000

367.0

38.0

35.0

45.0

38.0

35.0

DGV

TSSOP

VQFN

RGE

Pack Materials-Page 2

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

0,07

0,40

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

0,50

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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PCF8575PWG4 [TI]

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