PCI1451GJG [TI]
PC Card Controller; PC卡控制器
| 型号： | PCI1451GJG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PC Card Controller |
| 文件： | 总141页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCI1451 GJG
PC Card Controller
Data Manual
1999
PCIBus Solutions
Printed in U.S.A.
11/99
SCPS054
PCI1451
PC Card Controller
Data Manual
Literature Number: SCPS054
November 1999
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniquesareutilizedtotheextentTIdeemsnecessarytosupportthiswarranty. Specifictesting
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARENOTDESIGNED, AUTHORIZED, ORWARRANTED TOBESUITABLEFOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrantorrepresentthatanylicense, eitherexpressorimplied, isgrantedunderanypatentright,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Contents
Section
Title
Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1
1.2
1.3
1.4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
2 Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
3 Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.1
3.2
3.3
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3–2
3.3.1
3.3.2
PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Loading The Subsystem Identification
(EEPROM Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3.3.3
Serial Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3–5
3.4
PC Card Applications Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.4.12
PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3–6
P C Power Switch Interface (TPS2202A/2206) . . . . . . . . . 3–7
2
Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Zoomed Video Auto Detect . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Ultra Zoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
D3_STAT Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
SPKROUT Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3–13
PC Card 16 DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3.5
3.6
Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3.5.1
3.5.2
3.5.3
PC Card Functional And Card Status Change Interrupts . 3–15
Interrupt Masks And Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
CLKRUN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3–17
PCI Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
CardBus Device Class Power Management . . . . . . . . . . . . 3–18
Master List Of PME Context Bits and Global
Reset Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
iii
3.6.6
System Diagram Implementing CardBus Device Class
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
3.6.7
3.6.8
3.6.9
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
Requirements For SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . 3–20
Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
4 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . 4–1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . 4–1
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.12 CardBus Socket/ExCA Base-Address Register . . . . . . . . . . . . . . . . . . 4–7
4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.22 I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
4.28 PC Card 16-Bit I/F Legacy Mode Base Address Register . . . . . . . . . 4–16
4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4.30 Multimedia Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
4.31 General Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
4.32 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4–22
4.33 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . 4–22
4.34 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
4.35 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
4.36 Multifunction Routing Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
4.37 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
4.38 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
iv
4.39 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
4.40 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29
4.41 Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
4.42 Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
4.43 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
4.44 Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
4.45 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 4–33
4.46 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 4–34
4.47 Power Management Control/Status Register Bridge
Support Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35
4.48 General-Purpose Event Control/Status Register . . . . . . . . . . . . . . . . . 4–36
5 ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . . . . . 5–1
5.1
5.2
5.3
5.4
5.5
5.6
ExCA Identification and Revision Register (Index 00h) . . . . . . . . . . . 5–5
ExCA Interface Status Register (Index 01h) . . . . . . . . . . . . . . . . . . . . . 5–6
ExCA Power Control Register (Index 02h) . . . . . . . . . . . . . . . . . . . . . . 5–7
ExCA Interrupt and General Control Register (Index 03h) . . . . . . . . . 5–8
ExCA Card Status-Change Register (Index 04h) . . . . . . . . . . . . . . . . . 5–9
ExCA Card Status-Change Interrupt Configuration Register
(Index 05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
5.7
5.8
5.9
ExCA Address Window Enable Register (Index 06h) . . . . . . . . . . . . . 5–11
ExCA I/O Window Control Register (Index 07h) . . . . . . . . . . . . . . . . . 5–12
ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
(Index 08h, 0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
(Index 09h, ODh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
(Index 0Ah, 0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
(Index 0Bh, 0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte
Registers (Index 10h/18h/20h/28h/30h) . . . . . . . . . . . . . . . . . . . . . . . . 5–15
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte
Registers (Index 11h/19h/21h/29h/31h) . . . . . . . . . . . . . . . . . . . . . . . . 5–16
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers
(Index 12h/1Ah/22h/2Ah/32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers
(Index 13h/1Bh/23h/2Bh/33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers
(Index 14h/1Ch/24h/2Ch/34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
(Index 15h/1Dh/25h/2Dh/35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
5.19 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
(Index 36h, 38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21
5.20 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
(Index 37h, 39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21
5.21 ExCA Card Detect and General Control Register (Index 16h) . . . . . . 5–22
5.22 ExCA Global Control Register (Index 1Eh) . . . . . . . . . . . . . . . . . . . . . . 5–23
v
5.23 ExCA Memory Windows 0–4 Page Registers (Index 40h, 41h,
42h, 43h, 44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24
6 CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . 6–1
6.1
6.2
6.3
6.4
6.5
6.6
Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
7 Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
DMA Current Address/Base Address Register . . . . . . . . . . . . . . . . . . . 7–2
DMA Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
DMA Current Count/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . 7–3
DMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
DMA Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
DMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
DMA Master Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
DMA Multichannel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.1
8.2
8.3
Absolute Maximum Ratings Over Operating Temperature Ranges . 8–1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
Electrical Characteristics Over Recommended
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
8.4
8.5
PCI Clock/Reset Timing Requirements Over
Recommended Ranges of Supply Voltage and Operating
Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
PCI Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . 8–4
8.6
8.7
8.8
8.9
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5
PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . 8–6
PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature,
Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
8.10 Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature, I/O Cycles . . . 8–8
8.11 Switching Characteristics Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature,
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9
8.12 PC Card Parameter Measurement Information . . . . . . . . . . . . . . . . . . 8–9
9 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
vi
List of Illustrations
Figure
2–1
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
3–9
Title
Page
PCI1451 GJG Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
PCI1451 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
EEPROM Interface Subsystem Data Collection . . . . . . . . . . . . . . . . . . . . . 3–4
Serial EEPROM Start/Stop Conditions and BIt Transfers . . . . . . . . . . . . . 3–4
Serial EEPROM Protocol – Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
TPS2206 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
TPS2206 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3–10 Zoomed Video Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3–11 Zoomed Video With Auto Detect Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–12 SPKROUT Connection to Speaker Driver . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
3–13 Simplified Test Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3–14 Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3–15 System Diagram Implementing CardBus Device Class Power
Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
3–16 SUSPEND Functional Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
3–17 RI_OUT Functional Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
5–1
5–2
6–1
8–1
8–2
8–3
8–4
8–5
8–6
8–7
ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . 6–1
Load Circuit and Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5
PCLK Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
RSTIN Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
Shared Signals Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
PC Card Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9
PC Card I/O Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
Miscellaneous PC Card Delay Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
vii
List of Tables
Table
Title
Page
2–1
2–2
GJG Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals . 2–2
CardBus PC Card Signal Names Sorted Alphanumerically to GJG
Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–3
16-Bit PC Card Signal Names Sorted Alphanumerically to GJG
Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2–4
2–5
2–6
2–7
2–8
2–9
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
PC Card Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
PCI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
PCI Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
PCI Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
System Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2–10 PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2–11 Zoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2–12 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
2–13 16-Bit PC Card Address and Data (slots A and B) . . . . . . . . . . . . . . . . . . . 2–14
2–14 16-Bit PC Card Interface Control (slots A and B) . . . . . . . . . . . . . . . . . . . . 2–15
2–15 CardBus PC Card Interface System (slots A and B) . . . . . . . . . . . . . . . . . 2–16
2–16 CardBus PC Card Address and Data (slots A and B) . . . . . . . . . . . . . . . . 2–17
2–17 CardBus PC Card Interface Control (slots A and B) . . . . . . . . . . . . . . . . . 2–18
3–1
3–2
3–3
3–4
3–5
3–6
3–7
4–1
4–2
4–3
4–4
4–5
4–6
4–7
4–8
4–9
Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . . . . 3–5
PC Card – Card Detect and Voltage Sense Connections . . . . . . . . . . . . . 3–7
Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
PCI1451 Interrupt Masks and Flags Registers . . . . . . . . . . . . . . . . . . . . . . 3–16
Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Functions 0 and 1 PCI Configuration Register Map . . . . . . . . . . . . . . . . . . 4–1
PCI Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
Multimedia Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
General Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
4–10 General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . . 4–22
4–11 General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . . 4–22
4–12 General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . . 4–23
4–13 General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . . 4–23
viii
4–14 Multifunction Routing Status Register Description . . . . . . . . . . . . . . . . . . . 4–24
4–15 Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
4–16 Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27
4–17 Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
4–18 Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29
4–19 Socket DMA Register 0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
4–20 Socket DMA Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
4–21 Power Management Capabilities Register Description . . . . . . . . . . . . . . . 4–33
4–22 Power Management Control/Status Register Description . . . . . . . . . . . . . 4–34
4–23 Power Management Control/Status Register Bridge
Support Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35
4–24 GPE Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4–36
5–1
5–2
5–3
5–4
5–5
5–6
5–7
5–8
5–9
ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
ExCA Identification and Revision Register Description . . . . . . . . . . . . . . . 5–5
ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . 5–6
ExCA Power Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
ExCA Interrupt and General Control Register Description . . . . . . . . . . . . 5–8
ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . 5–9
ExCA Card Status-Change Interrupt Register Description . . . . . . . . . . . 5–10
ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . . 5–11
ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . 5–12
5–10 ExCA Memory Windows 0–4 Start-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
5–11 ExCA Memory Windows 0–4 End-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
5–12 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
5–13 ExCA Card Detect and General Control Register Description . . . . . . . . . 5–22
5–14 ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 5–23
6–1
6–2
6–3
6–4
6–5
6–6
6–7
7–1
7–2
7–3
7–4
7–5
8–1
8–2
8–3
8–4
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Socket Present State Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Socket Power Management Register Description . . . . . . . . . . . . . . . . . . . 6–8
Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
DDMA Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
DMA Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
DDMA Mode Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
DDMA Multichannel Mask Register Description . . . . . . . . . . . . . . . . . . . . . 7–6
PC Card Address Setup Time, t
, 8-Bit and 16-Bit PCI Cycles . . . . . 8–7
su(A)
PC Card Command Active Time, t
PC Card Command Active Time, t
, 8-Bit PCI Cycles . . . . . . . . . . . . . 8–7
, 16-Bit PCI Cycles . . . . . . . . . . . . 8–7
c(A)
c(A)
PC Card Address Hold Time, t
, 8-Bit and 16-Bit PCI Cycles . . . . . . . 8–7
h(A)
ix
x
1 Introduction
1.1 Description
The Texas Instruments PCI1451 is a high-performance PC Card controller with a 32-bit PCI interface. The
device supports two independent PC Card sockets compliant with the 1997 PC Card Standard and the PCI Bus
Interface Specification for PCI-to-CardBus Bridges. The PCI1451 provides features which make it the best
choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 and 1997
PC Cardt Standards retain the 16-bit PC Card specification defined in PCMCIA Release 2.1, and define the
new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1451 supports any
combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 Vdc or 3.3 Vdc as required.
The PCI1451 is compliant with the latest PCI Bus Power Management Specification. It is also compliant with
the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave
device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers, or CardBus PC Card bridging
transactions.
All card signals are internally buffered to allow hot insertion and removal. The PCI1451 is register compatible
with the Intel 82365SL-DF ExCA controller. The PCI1451 internal data-path logic allows the host to access 8-,
16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a
pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1451 can also
be programmed to accept fast posted writes to improve system bus utilization.
The PCI1451 provides an internally buffered zoom video (ZV) path. This reduces the design effort of PC board
manufacturers to add a ZV compatible solution and ensures compliance with the CardBus loading
specifications. Multiple system interrupt signaling options are provided: Serial ISA/Serial PCI, Serial
ISA/Parallel PCI, Parallel ISA/Parallel PCI, and PCI Only interrupts. Furthermore, general-purpose inputs and
outputs (GPIOs) are provided for the board designer to implement sideband functions. Many other features are
designed into the PCI1451 such as socket activity LED outputs, and are discussed in detail throughout the
design specification.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power
consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes allow the host power
management system to further reduce power consumption.
Unused PCI1451 inputs must be pulled up using a 43-kW resistor.
1.2 Features
The PCI1451 supports the following features:
•
•
•
•
•
•
Ultra zoomed video
Zoomed video auto-detect
Advanced filtering on card detect lines provide 90 microseconds of noise immunity.
Programmable D3 status pin
Internal ring oscillator
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
TI is a trademark of Texas Instruments.
1–1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Mix-and-match 5-V/3.3-V PC Card16 cards and 3.3-V CardBus cards
Two PC Card or CardBus slots with hot insertion and removal
Serial interface to TI TPS2206 dual power switch
132 Mbyte/sec. burst transfers to maximize data throughput on both the PCI bus and the CardBus bus
Serialized IRQ with PCI interrupts
Eight programmable multifunction pins
Interrupt modes supported: serial ISA/serial PCI, serial ISA/parallel PCI, parallel PCI only.
Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
Zoomed video with internal buffering
Dedicated pin for PCI CLKRUN
Four general-purpose event registers
Multifunction PCI device with separate configuration space for each socket
Five PCI memory windows and two I/O windows available to each PC Card16 socket
Two I/O windows and two memory windows available to each CardBus socket
ExCA -compatible registers are mapped in memory or I/O space
Distributed DMA and PC/PCI DMA
Intel 82365SL-DF register compatible
16-bit DMA on both PC Card sockets
Ring indicate, SUSPEND, and PCI CLKRUN
Advanced submicron, low-power CMOS technology
Provides VGA/palette memory and I/O, and subtractive decoding options
Socket activity LED pins
PCI bus lock (LOCK)
Packaged in a 257-pin Micro-Star BGA
1.3 Related Documents
•
•
•
•
•
•
•
1997 PC Card Standard
PCI Bus Power Management Interface Specification (Revision 1.1)
Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0)
PCI Local Bus Specification (Revision 2.2)
PC 98/99
PCI Bus Interface Specification for PCI-to-CardBus Bridges
PCI Bus Power Management Specification for PCI to CardBus Bridges Specification
1.4 Ordering Information
ORDERING NUMBER
NAME
VOLTAGE
PACKAGE
PCI1451
PC Card Controller
3.3 V, 5-V tolerant I/Os
257-ball Micro-Star BGA
1–2
2 Terminal Descriptions
The PCI1451 is packaged in a 257-ball MicroStar BGA package.
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
Figure 2–1. PCI1451 GJG Terminal Diagram
Table 2–1 shows the GJG terminal assignments for the CardBus and 16-bit PC Card signal names.
Table 2–2 shows the CardBus PC Card signal names sorted alphanumerically to the GJG terminal number.
Table 2–3 shows the 16-bit PC Card signal names sorted alphanumerically to the GJG terminal number.
2–1
Table 2–1. GJG Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals
SIGNAL NAME
CARDBUS
16-BIT
SIGNAL NAME
CARDBUS
16-BIT
SIGNAL NAME
CARDBUS
16-BIT
TERM.
NO.
TERM.
NO.
TERM.
NO.
A2
A3
A_CC/BE1
GND
A_ADDR8
GND
D5
D6
A_CAD13
A_CC/BE0
A_CAD5
GND
A_IORD
A_CE1
F14
F15
F16
F18
F19
G1
B_CAD15
B_CAD12
B_CAD13
B_IOWR
B_ADDR11
B_IORD
A4
A_CAD12
A_CAD10
A_CAD8
A_CAD3
A_CAD0
B_CAD29
A_ADDR11
A_CE2
D7
A_DATA6
GND
A5
D8
V
CCB
V
CCB
A6
A_DATA15
A_DATA5
A_DATA3
B_DATA1
D9
B_RSVD
B_CCD2
B_CAD26
B_CAD24
B_CAD23
B_DATA2
B_CD2
B_CAD11
GND
B_OE
A7
D10
D11
D12
D13
D14
D15
D16
D18
D19
E1
GND
A8
B_ADDR0
B_ADDR2
B_ADDR3
G2
A_CAD18
A_CAD19
A_CAD17
A_CC/BE2
A_CAD4
B_CAD7
B_CAD10
B_CAD9
B_CC/BE0
B_CAD8
GND
A_ADDR7
A_ADDR25
A_ADDR24
A_ADDR12
A_DATA12
B_DATA7
B_CE2
A9
G4
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
B_CSTSCHG B_BVD1(STSCHG/RI)
G5
V
CC
V
CC
V
CC
V
CC
G6
B_CC/BE3
B_CREQ
B_CVS2
B_CAD17
GND
B_REG
B_CFRAME
B_CBLOCK
B_RSVD
B_ADDR23
B_ADDR19
B_ADDR18
B_ADDR8
G7
B_INPACK
B_VS2
G13
G14
G15
G16
G18
G19
H1
B_ADDR24
GND
B_CC/BE1
B_ADDR10
B_CE1
V
CC
V
CC
B_CCLK
B_ADDR16
E2
A_CCLK
A_CGNT
A_ADDR16
A_WE
B_DATA15
GND
B_CDEVSEL B_ADDR21
E4
A_CPAR
A_RSVD
A_CAD16
A_CAD15
A_CAD11
A_ADDR13
A_ADDR18
A_ADDR17
A_IOWR
E5
A_CDEVSEL A_ADDR21
A_CAD20
A_CRST
A_CAD21
A_CAD22
A_CVS2
B_CAD4
B_RSVD
B_CAD5
B_CAD6
B_CAD3
A_CAD23
A_CC/BE3
A_CREQ
A_CAD24
A_CAD25
A_ADDR6
A_RESET
A_ADDR5
A_ADDR4
A_VS2
B2
E6
V
CC
V
CC
H2
B3
E7
A_RSVD
A_CAD1
A_DATA14
A_DATA4
H4
B4
E8
H5
B5
A_OE
E9
B_CAD31
B_CAD27
B_CINT
B_DATA10
B_DATA0
H6
B6
V
CCA
V
CCA
E10
E11
E12
E13
E14
E15
E16
E18
E19
F1
H14
H15
H16
H18
H19
J1
B_DATA12
B_DATA14
B_DATA6
B_DATA13
B_DATA5
A_ADDR3
A_REG
B7
A_CAD6
A_CAD2
B_CAD30
A_DATA13
A_DATA11
B_DATA9
B_READY(IREQ)
B_ADDR1
B_ADDR5
B_ADDR25
B_ADDR12
B_ADDR17
B_ADDR9
B8
B_CAD25
B_CAD21
B_CAD19
B_CC/BE2
B_CAD16
B_CAD14
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C1
B_CCLKRUN B_WP(IOIS16)
B_CVS1 B_VS1
V
CCB
V
CCB
J2
B_CAD22
B_CAD20
B_CAD18
B_CIRDY
B_CTRDY
B_CGNT
B_CSTOP
GND
B_ADDR4
B_ADDR6
B_ADDR7
B_ADDR15
B_ADDR22
B_WE
J4
A_INPACK
A_ADDR2
A_ADDR1
V
V
V
V
J5
CC
CC
J6
CCA
CCA
F2
A_CFRAME
A_CIRDY
A_CTRDY
A_CAD9
A_CAD7
A_CCD1
B_CAD28
B_CAUDIO
B_CSERR
GND
A_ADDR23
A_ADDR15
A_ADDR22
A_ADDR10
A_DATA7
A_CD1
J14
J15
J16
J18
J19
K1
V
CC
V
CC
F4
B_CAD1
B_CAD2
B_CAD0
B_CCD1
A_CVS1
A_CINT
B_DATA4
B_DATA11
B_DATA3
B_CD1
F5
B_ADDR20
GND
F6
F7
C2
A_CBLOCK
B_CPERR
B_CPAR
A_ADDR19
B_ADDR14
B_ADDR13
A_ADDR14
A_ADDR20
A_ADDR9
F8
A_VS1
C18
C19
D1
F9
B_DATA8
B_BVD2(SPKR)
B_WAIT
K2
A_READY(IREQ)
A_WAIT
F10
F11
F12
F13
K4
A_CSERR
A_CPERR
A_CSTOP
A_CAD14
K5
V
CCA
V
CCA
D2
GND
K6
A_CAD26
GNT
A_ADDR0
GNT
D4
B_CRST
B_RESET
K14
2–2
Table 2–1. GJG Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals (continued)
SIGNAL NAME
CARDBUS
16-BIT
SIGNAL NAME
CARDBUS
16-BIT
SIGNAL NAME
CARDBUS
16-BIT
TERM.
NO.
TERM.
NO.
TERM.
NO.
K15
K18
K19
L1
PCLK
PCLK
P9
P10
P11
P12
P13
P14
P15
P16
P18
P19
R1
MFUNC2
MFUNC1
GRST
MFUNC2
MFUNC1
GRST
T18
T19
U1
FRAME
IRDY
FRAME
IRDY
CLKRUN
PRST
CLKRUN
PRST
ZV_UV3
ZV_UV6
TRDY
ZV_UV3
ZV_UV6
TRDY
A_CSTSCHG
A_CCLKRUN
A_CCD2
A_CAD27
A_CAUDIO
REQ
A_BVD1(STSCHG/RI)
A_WP(IOIS16)
A_CD2
IRQSER
AD6
IRQSER
AD6
U2
L2
U18
U19
V1
L4
AD9
AD9
DEVSEL
ZV_UV5
ZV_SCLK
ZV_LRCLK
ZV_PCLK
RSVD
DEVSEL
ZV_UV5
ZV_SCLK
ZV_LRCLK
ZV_PCLK
RSVD
L5
A_DATA0
A_BVD2(SPKR)
REQ
V
CC
V
CC
L6
AD19
AD19
V2
L14
L15
L16
L18
L19
M1
M2
M4
M5
M6
M14
M15
M16
M18
M19
N1
AD21
AD21
V3
AD31
AD31
AD20
AD20
V4
AD28
AD28
ZV_Y7
ZV_UV0
ZV_UV2
MFUNC6
RSVD
RSVD
RSVD
MFUNC3
SUSPEND
RI_OUT
AD2
ZV_Y7
ZV_UV0
ZV_UV2
MFUNC6
RSVD
RSVD
RSVD
MFUNC3
SUSPEND
RI_OUT
AD2
V5
AD30
AD30
R2
V6
RSVD
RSVD
AD29
AD29
R4
V7
RSVD
RSVD
A_CAD29
GND
A_DATA1
GND
R5
V8
RSVD
RSVD
R6
V9
SCL
SCL
A_CAD30
A_RSVD
A_CAD28
C/BE3
A_DATA9
A_DATA2
A_DATA8
C/BE3
R7
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
V
CC
V
CC
R8
DATA
AD0
DATA
AD0
R9
R10
R11
R12
R13
R14
R15
R16
R18
R19
T1
V
CC
V
CC
AD27
AD27
GND
GND
AD26
AD26
AD11
AD11
AD25
AD25
AD5
AD5
AD14
AD14
AD24
AD24
AD8
AD8
PAR
PAR
ZV_HREF
ZV_VSYNC
ZV_Y0
ZV_HREF
ZV_VSYNC
ZV_Y0
AD16
AD16
PERR
PERR
N2
C/BE2
AD18
C/BE2
AD18
STOP
STOP
N4
ZV_UV7
ZV_MCLK
ZV_SDATA
MFUNC5
RSVD
ZV_UV7
ZV_MCLK
ZV_SDATA
MFUNC5
RSVD
N5
ZV_Y1
ZV_Y1
AD17
AD17
N6
ZV_Y2
ZV_Y2
ZV_UV1
ZV_UV4
GND
ZV_UV1
ZV_UV4
GND
N7
A_CAD31
AD3
A_DATA10
AD3
T2
N13
N14
N15
N16
N18
N19
P1
T4
AD22
AD22
T5
V
CC
V
CC
RSVD
RSVD
AD23
AD23
T6
RSVD
GND
RSVD
GND
RSVD
RSVD
GND
GND
T7
SDA
SDA
V
CCP
V
CCP
T8
RSVD
MFUNC4
SPKROUT
CLOCK
AD1
RSVD
MFUNC4
SPKROUT
CLOCK
AD1
MFUNC0
LATCH
GND
MFUNC0
LATCH
GND
IDSEL/MFUNC7 IDSEL/MFUNC7
T9
V
CC
V
CC
T10
T11
T12
T13
T14
T15
T16
P2
ZV_Y3
ZV_Y4
ZV_Y5
ZV_Y6
RSVD
RSVD
ZV_Y3
ZV_Y4
ZV_Y5
ZV_Y6
RSVD
RSVD
V
CCP
V
CCP
P4
AD7
AD7
P5
AD4
AD4
AD10
AD13
AD15
SERR
AD10
AD13
AD15
SERR
P6
C/BE0
AD12
C/BE0
AD12
P7
P8
C/BE1
C/BE1
2–3
Table 2–2. CardBus PC Card Signal Names Sorted Alphanumerically to GJG Terminal Number
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
A_CAD0
A8
E8
B8
A7
G7
D7
B7
F7
A6
F6
A5
B5
A4
D5
D4
B4
B3
G5
G2
G4
H1
H4
H5
J1
A_CFRAME
F2
E4
AD26
M16
M15
L16
L19
L18
L15
J18
J15
J16
H19
H14
H16
H18
G13
G18
G15
G14
F19
F15
F16
E18
F14
E16
A15
B15
E14
B14
E13
B13
D13
D12
E12
D11
E10
F9
B_CC/BE3
A12
J19
D10
A17
B10
A18
D15
B18
E11
B16
C19
C18
A13
F13
F11
B19
A10
B17
B11
A14
D9
A_CAD1
A_CGNT
A_CINT
A_CIRDY
A_CPAR
A_CPERR
A_CREQ
A_CRST
A_CSERR
A_CSTOP
A_CSTSCHG
A_CTRDY
A_CVS1
A_CVS2
A_RSVD
A_RSVD
A_RSVD
AD0
AD27
B_CCD1
B_CCD2
B_CCLK
B_CCLKRUN
B_CDEVSEL
B_CFRAME
B_CGNT
B_CINT
B_CIRDY
B_CPAR
B_CPERR
B_CREQ
B_CRST
B_CSERR
B_CSTOP
B_CSTSCHG
B_CTRDY
B_CVS1
B_CVS2
B_RSVD
B_RSVD
B_RSVD
C/BE0
A_CAD2
K2
AD28
A_CAD3
F4
AD29
A_CAD4
B1
AD30
A_CAD5
D1
AD31
A_CAD6
J4
B_CAD0
B_CAD1
B_CAD2
B_CAD3
B_CAD4
B_CAD5
B_CAD6
B_CAD7
B_CAD8
B_CAD9
B_CAD10
B_CAD11
B_CAD12
B_CAD13
B_CAD14
B_CAD15
B_CAD16
B_CAD17
B_CAD18
B_CAD19
B_CAD20
B_CAD21
B_CAD22
B_CAD23
B_CAD24
B_CAD25
B_CAD26
B_CAD27
B_CAD28
B_CAD29
B_CAD30
B_CAD31
B_CAUDIO
B_CBLOCK
B_CC/BE0
B_CC/BE1
B_CC/BE2
A_CAD7
H2
A_CAD8
K4
A_CAD9
D2
A_CAD10
A_CAD11
A_CAD12
A_CAD13
A_CAD14
A_CAD15
A_CAD16
A_CAD17
A_CAD18
A_CAD19
A_CAD20
A_CAD21
A_CAD22
A_CAD23
A_CAD24
A_CAD25
A_CAD26
A_CAD27
A_CAD28
A_CAD29
A_CAD30
A_CAD31
A_CAUDIO
A_CBLOCK
A_CC/BE0
A_CC/BE1
A_CC/BE2
A_CC/BE3
A_CCD1
L1
F5
K1
H6
B2
E7
M5
V12
T12
R12
N13
T13
R13
P13
W14
R14
P14
W15
V15
T15
W16
V16
W17
R15
R19
R18
P16
P19
P18
N14
N15
M19
M18
AD1
AD2
AD3
AD4
D18
H15
T14
T16
R16
M14
K18
T11
V11
U19
T18
A3
AD5
AD6
J5
AD7
C/BE1
J6
AD8
C/BE2
K6
L5
AD9
C/BE3
AD10
CLKRUN
CLOCK
DATA
M6
M1
M4
N7
L6
AD11
AD12
AD13
DEVSEL
FRAME
GND
AD14
AD15
C2
D6
A2
G6
J2
AD16
GND
A16
C1
AD17
GND
AD18
A9
GND
D8
AD19
B9
GND
F12
G1
AD20
E9
GND
F8
L4
AD21
F10
D16
G16
D19
E15
GND
G19
M2
A_CCD2
AD22
GND
A_CCLK
E2
L2
AD23
GND
N16
T4
A_CCLKRUN
A_CDEVSEL
AD24
GND
E5
AD25
GND
T7
2–4
Table 2–2. CardBus PC Card Signal Names Sorted Alphanumerically to GJG Terminal Number
(continued)
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
CC
SIGNAL NAME
GND
V14
W12
K14
P11
N19
T19
P12
W11
W10
P10
P9
RSVD
P7
P8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A11
D14
E1
ZV_PCLK
V4
V2
W4
R2
T1
R4
U1
T2
V1
U2
W2
N2
N4
N5
N6
P2
P4
P5
P6
R1
GND
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SCL
ZV_SCLK
ZV_SDATA
ZV_UV0
ZV_UV1
ZV_UV2
ZV_UV3
ZV_UV4
ZV_UV5
ZV_UV6
ZV_UV7
ZV_VSYNC
ZV_Y0
CC
GNT
R6
CC
GRST
R7
E6
CC
IDSEL/MFUNC7
IRDY
R8
E19
J14
P1
CC
T6
CC
IRQSER
LATCH
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PAR
T8
CC
V5
P15
T5
CC
V6
CC
V7
V10
V13
B6
CC
V8
CC
R9
W6
W7
W8
V9
CCA
CCA
CCA
CCB
CCB
CCP
CCP
T9
F1
W5
K5
ZV_Y1
R5
B12
F18
N18
W13
N1
ZV_Y2
V17
K15
V18
K19
L14
R11
SDA
W9
W18
T10
V19
R10
U18
ZV_Y3
PCLK
SERR
SPKROUT
STOP
SUSPEND
TRDY
ZV_Y4
PERR
ZV_Y5
PRST
ZV_HREF
ZV_LRCLK
ZV_MCLK
ZV_Y6
REQ
V3
ZV_Y7
RI_OUT
W3
2–5
Table 2–3. 16-Bit PC Card Signal Names Sorted Alphanumerically to GJG Terminal Number
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
A_ADDR0
K6
J6
A_DATA11
B8
G7
AD26
M16
M15
L16
L19
L18
L15
D11
E12
D12
D13
B13
E13
B14
B15
D19
E18
G15
F15
E15
C19
C18
B16
A17
E16
D18
D16
B19
A18
B17
D15
A15
E14
A10
F10
J19
D10
G16
G14
E10
A9
B_DATA5
H19
H16
G13
F9
A_ADDR1
A_ADDR2
A_ADDR3
A_ADDR4
A_ADDR5
A_ADDR6
A_ADDR7
A_ADDR8
A_ADDR9
A_ADDR10
A_ADDR11
A_ADDR12
A_ADDR13
A_ADDR14
A_ADDR15
A_ADDR16
A_ADDR17
A_ADDR18
A_ADDR19
A_ADDR20
A_ADDR21
A_ADDR22
A_ADDR23
A_ADDR24
A_ADDR25
A_BVD1(STSCHG/RI)
A_BVD2(SPKR)
A_CD1
A_DATA12
A_DATA13
A_DATA14
A_DATA15
A_INPACK
A_IORD
A_IOWR
A_OE
AD27
B_DATA6
B_DATA7
B_DATA8
B_DATA9
B_DATA10
B_DATA11
B_DATA12
B_DATA13
B_DATA14
B_DATA15
B_INPACK
B_IORD
B_IOWR
B_OE
J5
B7
AD28
J1
E7
AD29
H5
H4
H1
G2
A2
D4
F6
A4
G6
B1
D1
F4
E2
B3
B2
C2
D2
E5
F5
F2
G5
G4
L1
A6
AD30
B9
J4
AD31
E9
D5
B_ADDR0
B_ADDR1
B_ADDR2
B_ADDR3
B_ADDR4
B_ADDR5
B_ADDR6
B_ADDR7
B_ADDR8
B_ADDR9
B_ADDR10
B_ADDR11
B_ADDR12
B_ADDR13
B_ADDR14
B_ADDR15
B_ADDR16
B_ADDR17
B_ADDR18
B_ADDR19
B_ADDR20
B_ADDR21
B_ADDR22
B_ADDR23
B_ADDR24
B_ADDR25
B_BVD1(STSCHG/RI)
B_BVD2(SPKR)
B_CD1
J16
H14
H18
H15
G18
A13
F16
F14
F19
E11
A12
F13
B11
A14
F11
B18
B10
T14
T16
R16
M14
K18
T11
V11
U19
T18
A3
B4
B5
A_READY(IREQ)
A_REG
A_RESET
A_VS1
A_VS2
A_WAIT
A_WE
A_WP(IOIS16)
AD0
K2
J2
H2
K1
H6
K4
E4
B_READY(IREQ)
B_REG
B_RESET
B_VS1
L2
V12
T12
R12
N13
T13
R13
P13
W14
R14
P14
W15
V15
T15
W16
V16
W17
R15
R19
R18
P16
P19
P18
N14
N15
M19
M18
AD1
AD2
B_VS2
AD3
B_WAIT
B_WE
AD4
AD5
B_WP(IOIS16)
C/BE0
AD6
AD7
C/BE1
AD8
C/BE2
AD9
C/BE3
L6
AD10
CLKRUN
CLOCK
DATA
F8
L4
AD11
A_CD2
AD12
A_CE1
D6
A5
L5
AD13
DEVSEL
FRAME
GND
A_CE2
AD14
A_DATA0
AD15
A_DATA1
M1
M5
A8
E8
A7
D7
F7
M6
M4
N7
AD16
GND
A16
C1
A_DATA2
AD17
GND
A_DATA3
AD18
B_CD2
GND
D8
A_DATA4
AD19
B_CE1
GND
F12
G1
A_DATA5
AD20
B_CE2
GND
A_DATA6
AD21
B_DATA0
B_DATA1
B_DATA2
B_DATA3
B_DATA4
GND
G19
M2
A_DATA7
AD22
GND
A_DATA8
AD23
D9
GND
N16
T4
A_DATA9
AD24
J18
J15
GND
A_DATA10
AD25
GND
T7
2–6
Table 2–3. 16-Bit PC Card Signal Names Sorted Alphanumerically to GJG Terminal Number (continued)
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
CC
SIGNAL NAME
GND
V14
W12
K14
P11
N19
T19
P12
W11
W10
P10
P9
RSVD
P7
P8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A11
D14
E1
ZV_PCLK
V4
V2
W4
R2
T1
R4
U1
T2
V1
U2
W2
N2
N4
N5
N6
P2
P4
P5
P6
R1
GND
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SCL
ZV_SCLK
ZV_SDATA
ZV_UV0
ZV_UV1
ZV_UV2
ZV_UV3
ZV_UV4
ZV_UV5
ZV_UV6
ZV_UV7
ZV_VSYNC
ZV_Y0
CC
GNT
R6
CC
GRST
R7
E6
CC
IDSEL/MFUNC7
IRDY
R8
E19
J14
P1
CC
T6
CC
IRQSER
LATCH
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PAR
T8
CC
V5
P15
T5
CC
V6
CC
V7
V10
V13
B6
CC
V8
CC
R9
W6
W7
W8
V9
CCA
CCA
CCA
CCB
CCB
CCP
CCP
T9
F1
W5
K5
ZV_Y1
R5
B12
F18
N18
W13
N1
ZV_Y2
V17
K15
V18
K19
L14
R11
SDA
W9
W18
T10
V19
R10
U18
ZV_Y3
PCLK
SERR
SPKROUT
STOP
SUSPEND
TRDY
ZV_Y4
PERR
ZV_Y5
PRST
ZV_HREF
ZV_LRCLK
ZV_MCLK
ZV_Y6
REQ
V3
ZV_Y7
RI_OUT
W3
2–7
TheterminalsaregroupedintablesbyfunctionalitysuchasPCIsystemfunction, powersupplyfunction, etc., forquick
reference. The terminal numbers are also listed for convenient reference.
Table 2–4. Power Supply
TERMINAL
FUNCTION
NAME
NO.
A3, A16, C1, D8,
F12, G1, G19, M2,
N16, T4, T7, V14,
W12
GND
Device ground terminals
A11, D14, E1, E6,
E19, J14, P1, P15,
T5, V10, V13
Power supply terminal for core logic (3.3 Vdc)
V
CC
B6, F1, K5
B12, F18
N18, W13
Clamp voltage for PC Card A interface. Indicates Card A signaling environment.
Clamp voltage for PC Card B interface. Indicates Card B signaling environment.
Clamp voltage for PCI signaling (3.3 Vdc or 5 Vdc)
V
CCA
V
CCB
V
CCP
Table 2–5. PC Card Power Switch
TERMINAL
I/O
FUNCTION
NAME
NO.
3-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. This
terminal defaults as an input which means an external clock source must be used. If the internal ring
oscillator is used, then an external CLOCK source is not required. The internal oscillator may be enabled
by setting bit 27 (P2CCLK) of the system control register (PCI offset 80h, see Section 4.29) to a 1b.
CLOCK
T11
I/O
A 43-kW pulldown resistor should be tied to this terminal.
3-line power switch data. DATA is used to serially communicate socket power-control information to the
power switch.
DATA
V11
O
O
3-line power switch latch. LATCH is asserted by the PCI4450 to indicate to the PC Card power switch that
the data on the DATA line is valid.
LATCH
W11
Table 2–6. PCI System
TERMINAL
I/O
I/O
I
FUNCTION
NAME
NO.
PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to
slow it down, and the PCI4450 responds accordingly. If CLKRUN is not implemented, then this termomal
should be tied low. CLKRUN is enabled by default by bit 1 (KEEPCLK) in the system control register (PCI
offset 80h, see Section 4.29).
K18
CLKRUN
PCLK
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at
the rising edge of PCLK.
K15
K19
PCI bus reset. When the PCI bus reset is asserted, PRST causes the PCI4450 to place all output buffers
inahigh-impedancestateandresetallinternalregisters. WhenPRSTis asserted, the device is completely
nonfunctional. After PRST is deasserted, the PCI4450 is in its default state. When the SUSPEND mode
is enabled, the device is protected from the PRST and the internal registers are preserved. All outputs are
placed in a high-impedance state, but the contents of the registers are preserved.
I
I
PRST
GRST
Global reset. When the global reset is asserted, the GRST signal causes the PCI4450 to place all output
buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device is
completely in its default state. For systems that require wake-up from D3, GRST will normally be asserted
onlyduringinitialboot. PRSTshouldbeassertedfollowinginitialbootsothatPMEcontextisretainedwhen
transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST should be tied to
PRST.
P11
2–8
Table 2–7. PCI Address and Data
TERMINAL
NAME
I/O
FUNCTION
NO.
L15
L18
L19
L16
M15
M16
M18
M19
N15
N14
P18
P19
P16
R18
R19
R15
W17
V16
W16
T15
V15
W15
P14
R14
W14
P13
R13
T13
N13
R12
T12
V12
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
PCIaddress/databus. ThesesignalsmakeupthemultiplexedPCIaddressanddatabusontheprimaryinterface.
During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination
information. During the data phase, AD31–AD0 contain data.
I/O
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the
address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data phase, this
4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry
meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to
byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).
M14
R16
T16
T14
C/BE3
C/BE2
C/BE1
C/BE0
I/O
I/O
PCI bus parity. In all PCI bus read and write cycles, the PCI4450 calculates even parity across the AD31–AD0
and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI4450 outputs this parity indicator with a
one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator.
A compare error results in the assertion of a parity error (PERR).
PAR
V17
2–9
Table 2–8. PCI Interface Control
TERMINAL
NAME
I/O
FUNCTION
NO.
PCI device select. The PCI4450 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the bus, the PCI4450 monitors DEVSEL until a target responds. If no target responds before
timeout occurs, then the PCI4450 terminates the cycle with an initiator abort.
U19
I/O
DEVSEL
FRAME
GNT
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a
bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME
is deasserted, the PCI bus transaction is in the final data phase.
T18
K14
I/O
I
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI4450 access to the PCI bus after
the current data transaction has completed. GNT may or may not follow a PCI bus request, depending
on the PCI bus parking algorithm.
PCI bus lock. MFUNC7/LOCK can be configured as PCI LOCK and used to gain exclusive access
downstream. Since this functionality is not typically used, other functions may be accessed through this
terminal. MFUNC7/LOCK defaults to and can be configured through the multifunction routing status
register (PCI offset 8Ch, see Section 4.36).
LOCK
N19
I/O
(MFUNC7)
Initializationdeviceselect. IDSELselectsthePCI4450duringconfigurationspaceaccesses. IDSELcan
beconnected to one of the upper 24 PCI address lines on the PCI bus. If the LATCHterminal(W12/W11)
has an external pulldown resistor, then this terminal is configurable as MFUNC7 and IDSEL defaults to
the AD23 terminal.
IDSEL/MFUNC7
IRDY
N19
T19
I
PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of
the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are
asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.
I/O
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not
match PAR when PERR is enabled through bit 6 of the command register (PCI offset 04h, see
Section 4.4).
V18
L14
I/O
O
PERR
REQ
PCI bus request. REQ is asserted by the PCI4450 to request access to the PCI bus as an initiator.
PCI system error. SERR is an output that is pulsed from the PCI4450 when enabled through bit 8 of the
command register (PCI offset 04h, see Section 4.4), indicating a system error has occurred. The
PCI4450 need not be the target of the PCI cycle to assert this signal. When SERR is enabled by bit 1
in the bridge control register (PCI offset 3Eh, see Section 4.25), this signal also pulses, indicating that
an address parity error has occurred on a CardBus interface.
W18
O
SERR
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. STOP is used for target disconnects and is commonly asserted by target devices that do
not support burst data transfers.
V19
U18
I/O
I/O
STOP
TRDY
PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of
the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are
asserted. Until both IRDY and TRDY are asserted, wait states are inserted.
2–10
Table 2–9. System Interrupt
TERMINAL
NAME
I/O
FUNCTION
NO.
Parallel PCI interrupt. INTA can be mapped to MFUNC0 when parallel PCI interrupts are used.
INTA
(MFUNC0)
W10
I/O
See Section 3.5, Programmable Interrupt Subsystem, for details on interrupt signaling. MFUNC0/INTA
defaults to a general-purpose input.
Parallel PCI interrupt. INTB can be mapped to MFUNC1 when parallel PCI interrupts are used.
INTB
(MFUNC1)
P10
P12
I/O
I/O
See Section 3.5, Programmable Interrupt Subsystem, for details on interrupt signaling. MFUNC1/INTB
defaults to a general-purpose input.
Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme. Serialized PCI
interrupts can also be sent in the IRQSER stream. See Section 3.5, Programmable Interrupt Subsystem,
for details on interrupt signaling.
IRQSER
MFUNC6
MFUNC5
MFUNC4
MFUNC4
MFUNC3
MFUNC3
MFUNC2
MFUNC1
MFUNC0
R5
W5
T9
Interrupt request/secondary functions multiplexed. The primary function of these terminals is to provide
programmable options supported by the PCI4450. These interrupt multiplexer outputs can be mapped to
various functions. See Section 4.36, Multifunction Routing Status Register, for options.
T9
All of these terminals have secondary functions, such as PCI interrupts, PC/PCI DMA, GPE request/grant,
ring indicate output, and zoomed video status, that can be selected with the appropriate programming of
this register. When the secondary functions are enabled, the respective terminals are not available for
multifunction routing.
R9
O
O
R9
P9
See Section 4.36, Multifunction Routing Status Register, for programming options.
P10
W10
Ring indicate out and power management event output. Terminal provides an output to the system for
ring-indicate or PME signals. Alternately, RI_OUT can be routed on MFUNC7.
RI_OUT/PME
R11
Table 2–10. PC/PCI DMA
TERMINAL
I/O
FUNCTION
NAME
NO.
PCGNT
(MFUNC2)
P9
PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the
PC/PCI DMA scheme. PCGNT, is available on MFUNC2 or MFUNC3.
I/O
PCGNT
(MFUNC3)
R9
N19
T9
This terminal is also used for the serial EEPROM interface.
PCREQ
(MFUNC7)
PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system supporting the
PC/PCI DMA scheme. PCREQ is available on MFUNC7, MFUNC4, or MFUNC0.
PCREQ
(MFUNC4)
O
This terminal is also used for the serial EEPROM interface.
PCREQ
(MFUNC0)
W10
2–11
Table 2–11. Zoomed Video
TERMINAL
NAME
I/O AND MEMORY
INTERFACE SIGNAL
I/O
FUNCTION
NO.
N1
A10
A11
O
O
ZV_HREF
Horizontal sync to the zoomed video port
Vertical sync to the zoomed video port
N2
ZV_VSYNC
ZV_Y7
ZV_Y6
R1
P6
P5
P4
P2
N6
N5
N4
W2
U2
V1
T2
U1
R4
T1
R2
V2
W3
V4
V3
W4
A20
A14
A19
A13
A18
A8
ZV_Y5
ZV_Y4
O
Video data to the zoomed video port in YV:4:2:2 format
ZV_Y3
ZV_Y2
ZV_Y1
A17
A9
ZV_Y0
ZV_UV7
ZV_UV6
ZV_UV5
ZV_UV4
ZV_UV3
ZV_UV2
ZV_UV1
ZV_UV0
ZV_SCLK
ZV_MCLK
ZV_PCLK
ZV_LRCLK
ZV_SDATA
A25
A12
A24
A15
A23
A16
A22
A21
A7
O
Video data to the zoomed video port in YV:4:2:2 format
O
O
O
O
O
Audio SCLK PCM
A6
Audio MCLK PCM
IOIS16
INPACK
SPKR
Pixel clock to the zoomed video port
Audio LRCLK PCM
Audio SDATA PCM
2–12
Table 2–12. Miscellaneous
TERMINAL
NAME
I/O
I/O
I/O
I/O
I/O
FUNCTION
NO.
Multifunctionterminal 0. Defaults as a general-purpose input (GPI0), and can be programmed to perform
various functions. See Section 4.36, Multifunction Routing Status Register, for configuration details.
MFUNC0
MFUNC1
MFUNC2
MFUNC3
W10
Multifunctionterminal 1. Defaults as a general-purpose input (GPI1), and can be programmed to perform
various functions. See Section 4.36, Multifunction Routing Status Register, for configuration details.
P10
P9
Multifunctionterminal 2. Defaults as a general-purpose input (GPI2), and can be programmed to perform
various functions. See Section 4.36, Multifunction Routing Status Register, for configuration details.
Multifunctionterminal 3. Defaults as a general-purpose input (GPI3), and can be programmed to perform
various functions. See Section 4.36, Multifunction Routing Status Register, for configuration details.
R9
Multifunction terminal 4. Defaults as a high–impedance reserved input, and can be programmed to
perform various functions. See Section 4.36, Multifunction Routing Status Register, for configuration
details.
T9
W5
R5
I/O
I/O
I/O
I/O
MFUNC4
MFUNC5
Multifunction terminal 5. Defaults as a high-impedance reserved input, and can be programmed to
perform various functions. See Section 4.36, Multifunction Routing Status Register, for configuration
details.
Multifunction terminal 6. Defaults as a high-impedance reserved input, and can be programmed to
perform various functions. See Section 4.36, Multifunction Routing Status Register, for configuration
details.
MFUNC6
IDSEL and multifunction terminal 7. Defaults as IDSEL, but may be used as a multifunction terminal. See
Section 4.36, Multifunction Routing Status Register and Section 3.4, PC Card Applications Overview, for
configuration details.
IDSEL/MFUNC7
N19
Serial ROM clock. This terminal provides the SCL serial clock signaling in a two-wire serial ROM
implementation, and is sensed at reset for serial ROM detection.
SCL
SDA
V9
I/O
I/O
Serial ROM data. This terminal provides the SDA serial data signaling in a two-wire serial ROM
implementation.
W9
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the
PCI4450 from the PC Card interface. SPKROUT is driven as the XOR combination of card
SPKR//CAUDIO inputs.
T10
R10
O
I
SPKROUT
SUSPEND
Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See
Section 3.6.7, Suspend Mode for details.
2–13
Table 2–13. 16-Bit PC Card Address and Data (slots A and B)
TERMINAL
NO.
SLOT SLOT
I/O
FUNCTION
NAME
†
‡
A
B
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
G4
G5
F2
F5
E5
D2
C2
B2
B3
E2
F4
D1
B1
G6
A4
F6
D4
A2
G2
H1
H4
H5
J1
E14
A15
D15
B17
A18
B19
D16
D18
E16
A17
B16
C18
C19
E15
F15
G15
E18
D19
B15
B14
E13
B13
D13
D12
E12
D11
G18
H15
H18
H14
J16
E9
O
PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.
A8
A7
A6
A5
A4
A3
A2
J5
A1
J6
A0
K6
A6
E7
B7
G7
B8
N7
M4
M6
F7
D7
A7
E8
A8
M5
M1
L5
D15
D14
D13
D12
D11
D10
D9
B9
D8
F9
I/O
PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.
D7
G13
H16
H19
J15
J18
D9
D6
D5
D4
D3
D2
D1
A9
D0
E10
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal G2 is A_ADDR25.
Terminal name for slot B is preceded with B_. For example, the full name for terminal A16 is B_ADDR25.
2–14
Table 2–14. 16-Bit PC Card Interface Control (slots A and B)
TERMINAL
NO.
SLOT SLOT
I/O
FUNCTION
NAME
†
‡
A
B
Batteryvoltagedetect1. BVD1isgeneratedby16-bitmemoryPCCardsthatincludebatteries. BVD1
and BVD2 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are
kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and
should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the
memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration
Register, for the enable bits. See Section 5.5, ExCA Card Status-Change Register and Section 5.2,
ExCA Interface Status Register, for the status bits for this signal.
BVD1
(STSCHG/RI)
L1
A10
I
Status change. STSCHG is used to alert the system to a change in the READY, write protect, or
battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
Batteryvoltagedetect2. BVD2isgeneratedby16-bitmemoryPCCardsthatincludebatteries. BVD2
and BVD1 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are
high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should
be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC
Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for the
enable bits. See Section 5.5, ExCA Card Status-Change Register and Section 5.2, ExCA Interface
Status Register, for the status bits for this signal.
BVD2
(SPKR)
L6
F10
I
Speaker. SPKR is an optional binary audio signal available only when the card and socket have been
configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the
PCI4450 and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.
PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC
Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see
Section 5.2, ExCA Interface Status Register.
F8
L4
J19
CD1
CD2
I
D10
D6
A5
G16
G14
CE1
CE2
Cardenable1andcardenable2. CE1andCE2enableeven-andodd-numberedaddressbytes.CE1
enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.
O
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle
at the current address.
INPACK
J4
A13
I
DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit
PC Card that supports DMA. If used as a strobe, then the PC Card asserts this signal to indicate a
request for a DMA operation.
I/O read. IORD is asserted by the PCI4450 to enable 16-bit I/O PC Card data output during host I/O
read cycles.
D5
B4
B5
F16
F14
F19
O
O
O
IORD
IOWR
OE
DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that
supports DMA. The PCI4450 asserts IORD during DMA transfers from the PC Card to host memory.
I/O write. IOWR is driven low by the PCI4450 to strobe write data into 16-bit I/O PC Cards during host
I/O write cycles.
DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that
supports DMA. The PCI4450 asserts IOWR during transfers from host memory to the PC Card.
Outputenable. OE is driven low by the PCI4450 to enable 16-bit memory PC Card data output during
host memory read cycles.
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card
that supports DMA. The PCI4450 asserts OE to indicate TC for a DMA write operation.
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to
indicate that the memory card circuits are busy processing a previous write command. READY is
driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.
READY
(IREQ)
K2
E11
I
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on
the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no
interrupt is requested.
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal B5 is A_OE.
Terminal name for slot B is preceded with B_. For example, the full name for terminal F19 is B_OE.
2–15
Table 2–14. 16-Bit PC Card Interface Control (slots A and B) (continued)
TERMINAL
NO.
SLOT SLOT
I/O
FUNCTION
NAME
†
‡
A
B
Attribute memory select. REG remains high for all common memory accesses. When REG is asserted,
access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active).
Attribute memory is a separately accessed section of card memory and is generally used to record card
capacity and other configuration and attribute information.
J2
A12
O
REG
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC
Card that supports DMA. The PCI4450 asserts REG to indicate a DMA operation. REG is used in
conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.
RESET
WAIT
H2
K4
F13
F11
O
I
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory
or I/O cycle in progress.
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used
for memory PC Cards that employ programmable memory technologies.
DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA.
The PCI4450 asserts WE to indicate TC for a DMA read operation.
WE
E4
B18
O
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch
on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the
address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port
that is addressed is capable of 16-bit accesses.
WP
(IOIS16)
L2
B10
I
DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card
that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation.
VS1
VS2
K1
H6
B11
A14
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
determine the operating voltage of the 16-bit PC Card.
I/O
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal C1 is A_WE.
Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_WE.
Table 2–15. CardBus PC Card Interface System (slots A and B)
TERMINAL
NO.
I/O
FUNCTION
NAME
SLOT SLOT
†
‡
A
B
CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus
interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, and
CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the
rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the
low state or slowed down for power savings.
CCLK
E2
A17
O
CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the
CCLK frequency, and by the PCI4450 to indicate that the CCLK frequency is decreased. CardBus clock
run (CCLKRUN) follows the PCI clock run (CLKRUN).
L2
B10
F13
O
CCLKRUN
CRST
CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and
signals to a known state. When CRST is asserted, all CardBus PC Card signals must be placed in a
high-impedance state, and the PCI4450 drives these signals to a valid logic level. Assertion can be
asynchronous to CCLK, but deassertion must be synchronous to CCLK.
H2
I/O
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal E3 is A_CCLK.
Terminal name for slot B is preceded with B_. For example, the full name for terminal B17 is B_CCLK.
2–16
Table 2–16. CardBus PC Card Address and Data (slots A and B)
TERMINAL
NO.
SLOT SLOT
I/O
FUNCTION
NAME
†
‡
A
B
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
N7
M4
M1
M6
L5
E9
B9
A9
F9
E10
D11
E12
D12
D13
B13
E13
B14
E14
B15
A15
E16
F14
E18
F16
F15
F19
G14
G15
G18
G13
H18
H16
H14
H19
J16
J15
J18
K6
J6
J5
J1
H5
H4
H1
G4
G2
G5
B3
B4
D4
D5
A4
B5
A5
F6
A6
F7
B7
D7
G7
A7
B8
E8
A8
PC Card address and data. These signals make up the multiplexed CardBus address and data bus on
the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit
address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most
significant bit.
I/O
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus
terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 defines the bus command.
Duringthedataphase, this4-bitbusisusedasbyteenables. Thebyteenablesdeterminewhichbytepaths
of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1applies
to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3
(CAD31–CAD24).
J2
G6
A2
D6
A12
E15
D19
G16
CC/BE3
CC/BE2
CC/BE1
CC/BE0
I/O
I/O
CardBus parity. In all CardBus read and write cycles, the PCI4450 calculates even parity across the CAD
and CC/BE buses. As an initiator during CardBus cycles, the PCI4450 outputs CPAR with a one-CCLK
delay. AsatargetduringCardBuscycles, thecalculatedparityiscomparedtotheinitiator’sparityindicator;
a compare error results in a parity error assertion.
CPAR
B1
C19
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal C2 is A_CPAR.
Terminal name for slot B is preceded with B_. For example, the full name for terminal B20 is B_CPAR.
2–17
Table 2–17. CardBus PC Card Interface Control (slots A and B)
TERMINAL
NO.
SLOT SLOT
I/O
FUNCTION
NAME
†
‡
A
B
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI4450
supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CAUDIO
CBLOCK
L6
F10
D16
I
C2
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CCD1
CCD2
F8
L4
J19
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and
CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.
I
D10
CardBusdevice select. The PCI4450 asserts CDEVSEL to claim a CardBus cycle as the target device.
As a CardBus initiator on the bus, the PCI4450 monitors CDEVSEL until a target responds. If no target
responds before time-out occurs, then the PCI4450 terminates the cycle with an initiator abort.
E5
F2
A18
D15
I/O
CDEVSEL
CFRAME
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
I/O
CardBusbusgrant. CGNTisdrivenbythePCI4450tograntaCardBusPCCardaccesstotheCardBus
bus after the current data transaction has been completed.
E4
K2
B18
E11
I
I
CGNT
CINT
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the
host.
CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
F4
B16
I/O
CIRDY
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following that data when a parity error is detected.
D1
J4
C18
A13
I/O
I
CPERR
CREQ
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus
bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system errors that could lead
to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak
pullup, and may take several CCLK periods. The PCI4450 can report CSERR to the system by
assertion of SERR on the PCI interface.
K4
F11
I
CSERR
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that
do not support burst data transfers.
D2
L1
F5
B19
A10
B17
I/O
I
CSTOP
CSTSCHG
CTRDY
CardBus status change. CSTSCHG alerts the system to a change in the card’s status and is used as
a wake-up mechanism.
CardBustargetready. CTRDYindicatestheCardBustarget’sabilitytocompletethecurrentdataphase
of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY
are asserted; until this time, wait states are inserted.
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
CCD1andCCD2toidentifycardinsertionandinterrogatecardstodeterminetheoperatingvoltageand
card type.
K1
H6
B11
A14
CVS1
CVS2
I/O
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal M1 is A_CAUDIO.
Terminal name for slot B is preceded with B_. For example, the full name for terminal C11 is B_CAUDIO.
2–18
3 Feature/Protocol Descriptions
Figure 3–1 shows a simplified system implementation example using the PCI1451. The PCI interface includes all
address/data and control signals for PCI protocol. Highlighted in this diagram is the functionality supported by the
PCI1451. The PCI1451 supports PC/PCI DMA, PCI Way DMA (distributed DMA), PME wake-up from D3
through
cold
D0, 4 interrupt modes, an integrated zoomed video port, and 12 multifunction pins (8 MFUNC and 4 GPIO pins) that
can be programmed for a wide variety of functions.
PCI Bus
Real Time
Clock
Activity LED’s
CLKRUN
South Bridge
IRQSER
PCI1451
Clock
2
TPS2206
Power
ZV
Enable
DMA
PME
Switch
Embedded
Controller
Zoomed Video
PC Card
Socket A
VGA
Controller
68
19 Video
4 Audio
23 for ZV
(See Note)
PC Card
Socket B
68
Audio
Codec
23 for ZV
4 Audio
Interrupt Routing Options:
1) Serial ISA/Serial PCI
2) Serial ISA/Parallel PCI
3) Parallel PCI/Parallel ISA
4) Parallel PCI Only
NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing
the zoomed video signals to the VGA controller.
Figure 3–1. PCI1451 System Block Diagram
3.1 I/O Characteristics
Figure 3–2 shows a 3-state bidirectional buffer. Section 8.2, Recommended Operating Conditions, provides the
electrical characteristics of the inputs and outputs. The PCI1451 meets the ac specifications of the 1995 PC Card
Standard and the PCI Local Bus Specification.
3–1
V
CCP
Tied for Open Drain
OE
Pad
Figure 3–2. 3-State Bidirectional Buffer
3.2 Clamping Voltages
The I/O sites can be pulled through a clamping diode to a voltage rail for protection. The 3.3-V core power supply
is independent of the clamping voltages. The clamping (protection) diodes are required if the signaling environment
on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5 Vdc, and the PCI1451 must
reliablyaccommodatebothvoltagelevels.Thisisaccomplishedbyusinga3.3-VbufferwithaclampingdiodetoV
.
CCP
If a system design requires a 5-V PCI bus, then the V
would be connected to the 5-V power supply.
CCP
A standard die has only one clamping voltage for the sites as shown in Figure 3–2. After the terminal assignments
are fixed, the fabrication facility will support a design by splitting the clamping voltage for customization. The PCI1451
requires three separate clamping voltages since it supports a wide range of features. The three voltages are listed
and defined in Section 8.2, Recommended Operating Conditions.
3.3 Peripheral Component Interconnect (PCI) Interface
This section describes the PCI interface of the PCI1451, and how the device responds to and participates in PCI bus
cycles. ThePCI1451providesallrequiredsignalsforPCImaster/slavedevicesandmayoperateineither5-Vor3.3-V
PCI signaling environments by connecting the V
terminals to the desired signaling level.
CCP
3.3.1 PCI Bus Lock (LOCK)
The bus locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on
the PCI1451 as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the
terminal function defaults to a general-purpose input (GPI). The use of LOCK is only supported by PCI-to-CardBus
bridges in the downstream direction (away from the processor).
PCILOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions may proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible
for different initiators to use the PCI bus while a single master retains ownership of LOCK. To avoid confusion with
the PCI bus clock, the CardBus signal for this protocol is CBLOCK.
An agent may need to do an exclusive operation because a critical memory access to memory might be broken into
severaltransactions, butthemasterwantsexclusiverightstoaregionofmemory. Thegranularityofthelockisdefined
by PCI to be 16 bytes aligned. The lock protocol defined by PCI allows a resource lock without interfering with
nonexclusive, real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario
the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete
bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock
must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation
is in progress.
The PCI1451 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus
bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential
deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target
3–2
supports delayed transactions and blocks access as the target until it completes a delayed read. This target
characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using
LOCK.
3.3.2 Loading The Subsystem Identification (EEPROM Interface)
The subsystem vendor ID register (see Section 4.26) and subsystem ID register (see Section 4.27) make up a double
word of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register, used for system
and option card (mobile dock) identification purposes, is required by some operating systems. Implementation of this
unique identifier register is a PC 97 requirement.
The PCI1451 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism
relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers
is read-only, but the access mode may be made read/write by clearing bit 5 (SUBSYSRW) in the system control
register (PCI offset 80h, see Section 4.29). Once this bit is cleared (0), the BIOS may write a subsystem identification
value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor
ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of
implementing the serial EEPROM.
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier through a serial EEPROM interface. The PCI1451 loads the doubleword of
data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the PRST and GRST from
the entire PCI1451 core, including the serial EEPROM state machine (see Section 3.6.7, Suspend Mode, for details
on using SUSPEND). The PCI1451 provides a two-line serial bus interface to the serial EEPROM.
The system designer must implement a pullup resistor on the PCI1451 SDA terminal to indicate the serial EEPROM
mode. Only when this pullup resistor is present will the PCI1451 attempt to load data through the serial EEPROM
interface. Note that a pullup resistor is also required on the SCL terminal to implement the EEPROM interface
correctly. The serial EEPROM interface is a two-pin interface with one data signal (SDA) and one clock signal (SCL).
Figure 3–3 illustrates a typical PCI1451 application using the serial EEPROM interface.
V
CC
Serial
EEPROM
A0
SCL
SDA
A1 SCL
A2 SDA
PCI1451
Figure 3–3. Serial EEPROM Application
As stated above, when the PCI1451 is reset by GRST, the subsystem data is read automatically from the EEPROM.
The PCI1451 masters the serial EEPROM bus and reads four bytes as described in Figure 3–4.
3–3
Slave Address
Word Address
Slave Address
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
b6 b5 b4 b3 b2 b1 b0
1
A
R/W
Restart
Data Byte 3
R/W
Data Byte 0
M
Data Byte 1
M
Data Byte 2
M
M
P
S/P – Start/Stop Condition
A – Slave Acknowledgment
M – Master Acknowledgment
Figure 3–4. EEPROM Interface Subsystem Data Collection
The EEPROM is addressed at word address 00h, as indicated in Figure 3–4, and the address autoincrements after
each byte transfers according to the protocol. Thus, to provide the subsystem register with data AABBCCDDh the
EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh.
The serial EEPROM is addressed at slave address 1010000b by the PCI1451. All hardware address bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit, Figure 3–3, assumes the 1010b high address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
The serial EEPROM interface signals require pullup resistors. The serial EEPROM protocol allows bidirectional
transfers. Both the SCL and SDA signals are placed in a high-impedance state and pulled high when the bus is not
active. When the SDA line transitions to a logic low, this signals a start condition (S). A low-to-high transition of SDA
while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be
interpretedasacontrolsignal. Dataisvalidandstableduringtheclockhighperiod. Figure3–5illustratesthisprotocol.
SDA
SCL
Start
Stop
Change of
Condition
Condition
Data Allowed
Data Line Stable,
Data Valid
Figure 3–5. Serial EEPROM Start/Stop Conditions and BIt Transfers
Eachaddress byte and data transfer is followed by an acknowledge bit, as indicated in Figure 3–4. When the PCI1451
transmits the addresses, it returns the SDA signal to the high state and places the line in a high-impedance state.
The PCI1451 then generates an SCL clock cycle and expects the EEPROM to pull down the SDA line during the
acknowledge pulse. This procedure is referred to as a slave acknowledge with the PCI1451 transmitter and the
EEPROM receiver. Figure 3–6 illustrates general acknowledges.
During the data byte transfers from the serial EEPROM to the PCI1451, the EEPROM clocks the SCL signal. After
the EEPROM transmits the data to the PCI1451, it returns the SDA signal to the high state and places the line in a
high-impedance state. The EEPROM then generates an SCL clock cycle and expects the PCI1451 to pull down the
SDA line during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM
transmitter and the PCI1451 receiver. Figure 3–6 illustrates general acknowledges.
3–4
SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3–6. Serial EEPROM Protocol – Acknowledge
EEPROM interface status information is communicated through the general status register (PCI offset 85h, see
Section 4.31). Bit 2 (EEDETECT) in this register indicates whether or not the PCI1451 serial EEPROM circuitry
detects the pullup resistor on SDA. An error condition, such as a missing acknowledge, results in bit 1 (DATAERR)
being set. Bit 0 (EEBUSY) is set while the subsystem ID register is loading (serial EEPROM interface is busy).
3.3.3 Serial Bus EEPROM Application
When the PCI bus is reset and the serial bus interface is detected, the PCI1451 attempts to read the subsystem
identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be
loaded with defaults through the EEPROM are provided in Table 3–1.
Table 3–1. Registers and Bits Loadable Through Serial EEPROM
PCI
OFFSET
EEPROM OFFSET
REFERENCE
BITS LOADED FROM EEPROM TO
CORRESPONDING BITS IN REGISTER
REGISTER NAME
PCI 43h
PCI 42h
PCI 41h
PCI 40h
PCI 80h
PCI 81h
PCI 82h
PCI 83h
PCI 86h
PCI 89h
PCI 8Bh
PCI 8Ch
PCI 8Dh
PCI 8Eh
PCI 8Fh
PCI 91h
PCI 92h
PCI 93h
PCI A2h
ExCA 00h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
Subsystem ID (see Section 4.27)
Byte 1
Subsystem ID (see Section 4.27)
Byte 0
Subsystem vendor ID (see Section 4.26)
Subsystem vendor ID (see Section 4.26)
System control (see Section 4.29)
Byte 1
Byte 0
Byte 0, bits 6, 5, 4, 3, 1, 0
Byte 1, bits 7, 6
Byte 2, bits 6–0
Byte 3, bits 7, 6, 5, 3, 2, 0
No bits loaded
Bits 7, 6, 3, 2, 1, 0
Bits 3–0
System control (see Section 4.29)
System control (see Section 4.29)
System control (see Section 4.29)
Reserved
General-purpose event enable (see Section 4.33)
General-purpose output (see Section 4.35)
Multifunction routing status (see Section 4.36)
Multifunction routing status (see Section 4.36)
Multifunction routing status (see Section 4.36)
Multifunction routing status (see Section 4.36)
Card control (see Section 4.38)
Byte 0
Byte 1
Byte 2
Byte 3
Bits 7, 2, 1
Bits 7–0
Device control (see Section 4.39)
Diagnostic (see Section 4.40)
Bits 7, 4–0
Bit 15
Power management capabilities (see Section 4.45)
ExCA identificaton and revision (see Section 5.1)
Bits 7–0
TheEEPROMdataformatisdetailedinFigure3–7. ThisformatmustbefollowedforthePCI1451toloadinitializations
properly from a serial EEPROM. Any undefined condition results in a terminated load and sets the DATAERR bit in
the general status register (see Section 4.31).
3–5
Slave Address = 1010 0000b
PCI Offset
Word Address 21h
Reference(0)
PCI Offset
Reference(n)
Byte 3 (0)
Byte 2 (0)
Byte 1 (0)
Byte 0 (0)
RSVD
Word Address 22h
Word Address 23h
Word Address 24h
Word Address 25h
Word Address 8 × (n+3) + 1
Byte 3 (n)
Byte 2 (n)
Byte 1 (n)
Byte 0 (n)
RSVD
Word Address 8 × (n+3) + 2
Word Address 8 × (n+3) + 3
Word Address 8 × (n+3) + 4
Word Address 8 × (n+3) + 5
RSVD
RSVD
RSVD
PCI Offset
Reference(1)
Word Address 29h
RSVD
EOL = FFh
Word Address 8 × (n+4) + 1
Figure 3–7. EEPROM Data Format
The byte at EEPROM word address 00h must contain either a valid PCI offset, as listed in Table 3–1, or an end-of-list
(EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load from the EEPROM.
Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered when programming
the EEPROM.
The serial EEPROM is addressed at slave address 1010 0000b by the PCI1451. All hardware addres bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit (Figure 3–3) assumes the 1010b high-address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 3–4.
The address autoincrements after every byte transfer according to the doubleword read protocol. Note that the word
addresses align with the data format illustrated in Figure 3–7. The PCI1451 continues to load data from the serial
EEPROMuntil an end-of-list indicator is read. Three reserved bytes are stuffed to maintain eight-byte data structures.
Note that the eight-byte data structure is important to provide correct addressing per the doubleword read format
shown in Figure 3–4. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is,
01h, 02h, 03h, 04h. If the offsets are not sequential, the registers may be loaded incorrectly.
3.4 PC Card Applications Overview
This section describes the PC Card interfaces of the PCI1451. A discussion on PC Card recognition details the card
2
interrogation procedure. The card powering procedure is also discussed, including the protocol of the P C power
switch interface. The internal ZV buffering provided by the PCI1451 and programming model is also detailed. Also,
standardPCCardregistermodelsaredescribed, aswellasabriefdiscussionofthePCCardsoftwareprotocollayers.
3.4.1 PC Card Insertion/Removal and Recognition
The 1995 PC Card Standard addresses the card detection and recognition process through an interrogation
procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit vs. CardBus) are determined.
The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card
designer connects these four pins in a certain configuration depending on the type of card and the supply voltage.
The encoding scheme for this, defined in the 1997 PC Card Standard, is shown in Table 3–2.
3–6
Table 3–2. PC Card – Card Detect and Voltage Sense Connections
CD2//CCD2
Ground
CD1//CCD1
Ground
VS2//CVS2
Open
VS1//CVS1
Open
Key
5 V
5 V
Interface
Voltage
5 V
16-bit PC Card
16-bit PC Card
Ground
Ground
Open
Ground
5 V and 3.3 V
5 V, 3.3 V, and
X.X V
Ground
Ground
Ground
Ground
5 V
16-bit PC Card
Ground
Ground
Ground
Connect to CVS1
Ground
Open
Open
Ground
Connect to CCD1
Ground
LV
LV
LV
LV
16-bit PC Card
CardBus PC Card
16-bit PC Card
3.3 V
3.3 V
Ground
Ground
3.3 V and X.X V
3.3 V and X.X V
Connect to CVS2
Ground
Connect to CCD2
Ground
CardBus PC Card
3.3 V, X.X V, and
Y.Y V
Connect to CVS1
Ground
Ground
Connect to CCD2
LV
CardBus PC Card
Ground
Connect to CVS2
Ground
Ground
Ground
Ground
Connect to CCD2
Connect to CCD1
Open
Open
Open
LV
LV
LV
LV
16-bit PC Card
CardBus PC Card
CardBus PC Card
CardBus PC Card
Reserved
Y.Y V
Y.Y V
Connect to CVS2
Ground
Open
X.X V and Y.Y V
Y.Y V
Connect to CVS1
Ground
Connect to CCD2
Connect to CCD1
Ground
Connect to CVS1
Connect to CVS2
Ground
Ground
Connect to CCD1
Reserved
2
3.4.2 P C Power Switch Interface (TPS2202A/2206)
2
A power switch with a PCMCIA-to-peripheral control (P C) interface is required for the PC Card powering interface.
2
TheTITPS2206(orTPS2202A)Dual-SlotPCCardPower-InterfaceSwitchprovidestheP CinterfacetotheCLOCK,
DATA, and LATCH terminals of the PCI1451. Figure 3–8 shows the terminal assignments of the TPS2206. Figure 3–9
illustrates a typical application where the PCI1451 represents the PCMCIA controller.
There are two ways to provide a clock source to the power switch interface. The first method is to provide an external
clock source such as a 32 kHz real time clock to the CLOCK terminal. The second method is to use the internal ring
oscillator. If the internal ring oscillator is used, then the PCI1451 provides its own clock source for the PC Card
interrogation logic and the power switch interface. The mode of operation is determined by the setting of bit 27
(P2CCLK) of the system control register (PCI offset 80h). This bit is encoded as follows:
0 = CLOCK terminal is an input (default).
1 = CLOCK terminal is an output that utilizes the internal oscillator.
A 43 kW pulldown resistor should be tied to the CLOCK pin.
3–7
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
5V
5V
NC
NC
NC
NC
NC
12V
BVPP
BVCC
BVCC
BVCC
NC
OC
3.3V
3.3V
2
3
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
4
5
6
7
8
9
10
11
12
13
14
15
NC
RESET
3.3V
NC – No internal connection
Figure 3–8. TPS2206 Terminal Assignments
Power Supply
PC Card A
PP1
TPS2206
V
12 V
5 V
12 V
5 V
AVPP
V
V
V
PP2
3.3 V
3.3 V
AVCC
AVCC
AVCC
CC
CC
Supervisor
RESET
PC Card B
V
PP1
BVPP
V
V
V
PP2
BVCC
BVCC
BVCC
CC
3
CC
PCI1451
Serial I/F
PC Card Interface (68 pins/socket)
Figure 3–9. TPS2206 Typical Application
3.4.3 Zoomed Video Support
The zoomed video (ZV) port on the PCI1451 provides an internally buffered 16-bit ZV PC Card data path. This internal
routing is programmed through the multimedia control register. Figure 3–9 summarizes the zoomed video subsystem
implemented in the PCI1451, and details the bit functions found in the multimedia control register.
Anoutputport(PORTSEL)isalwaysselected. ThePCI1451defaultstosocket0(seethemultimediacontrolregister).
When ZVOUTEN is enabled, the zoomed video output terminals are enabled and allow the PCI1451 to route the
zoomed video data. However, no data is transmitted unless either bit 0 (ZVEN0) or bit 1 (ZVEN1) is enabled in the
multimedia control register. If the PORTSEL maps to a card port that is disabled (ZVEN =0 or ZVEN1 = 0), then the
zoomed video port is driven low (i.e., no data is transmitted).
3–8
Zoomed Video Subsystem
Card Output
Enable Logic
ZVEN0
ZVOUTEN
PC Card
PC Card
Socket 0
I/F
ZVSTAT†
23
VGA
19 Video Signals
PORTSEL
PC Card
Socket 1
PC Card
I/F
Audio
Codec
4 Audio Signals
ZVEN1
Card Output
Enable Logic
†
ZVSTATmustbeenabledthroughtheGPIOControlRegister.
Figure 3–10. Zoomed Video Subsystem
3.4.4 Zoomed Video Auto Detect
Zoomed video auto detect, when enabled, allows the PCI1451 to automatically detect zoomed video data by sensing
the pixel clock from each socket and/or from a third zoomed video source that may exist on the motherboard. The
PCI1451 automatically switches the internal zoomed video MUX to route the zoomed video stream to the PCI1451’s
zoomed video output port. This eliminates the need for software to switch the internal MUX using the multimedia
control register (PCI offset 84h, bits 6 and 7).
The PCI1451 can be programmed to switch a third zoomed video source by programming MFUNC2 or MFUNC3 as
a zoomed video pixel clock sense pin and connecting this pin to the pixel clock of the third zoomed video source.
ZVSTAT may then be programmed onto MFUNC4, MFUNC1, or MFUNC0 and this signal may switch the zoomed
video buffers from the third zoomed video source. To account for the possibility of several zoomed video sources
being enabled at the same time, a programmable priority scheme may be enabled.
3–9
Zoomed Video Subsystem
Card Output
Enable Logic
3rd Zoomed Video Source
ZVEN0
Pixel Clock Sense
Programmed on
23
MFUNC2 or MFUNC3
PC Card
I/F
PC Card
Socket 0
Buffers
Enable
23
ZVSTAT
Pixel Clock Sense
23
23
23
23
Auto Z/V Arbiter
and Buffer
VGA
19 Video Signals
ZV Data
Pixel Clock Sense
23
PC Card
Socket 1
Audio
Codec
PC Card
I/F
4 Audio Signals
ZVEN1
Card Output
Enable Logic
Figure 3–11. Zoomed Video With Auto Detect Enabled
The PCI1451 defaults with zoomed video auto-detect disabled so that it will function exactly like the PCI1250A and
PCI1451. To enable zoomed video auto-detect and the programmable priority scheme, the following bits must be set:
•
•
Multimedia control register (PCI offset 84h) bit 5: Writing a 1b enables zoomed video auto-detect
Multimedia control register (PCI offset 84h) bits 4–2: Set the programmable priority scheme
000 = Slot A, Slot B, External Source
001 = Slot A, External Source, Slot B
010 = Slot B, Slot A, External Source
011 = Slot B, External Source, Slot A
100 = External Source, Slot A, Slot B
101 = External Source, Slot B, Slot A
110 = External Source, Slot B, Slot A
111 = Reserved
3–10
If it is desired to switch a third zoomed video source, then the following bits must also be set:
•
•
MFUNC routing register (PCI offset 8Ch), bits 14–12 or 10–8: Write 111b to program MFUNC3 or MFUNC2
as a pixel clock input pin.
MFUNC routing register (PCI offset 8Ch), bits 18–16, 6–4, or 2–0: Write 111b to program MFUNC4,
MFUNC1, or MFUNC0 pin.
3.4.5 Ultra Zoomed Video
Ultra zoomed video is an enhancement to the PCI1451’s DMA engine and is intended to improve the 16-bit bandwidth
for MPEG I and MPEG II decoder PC Cards. This enhancement allows the 1451 to fetch 32 bits of data from memory
versus the 11XX/12XX 16-bit fetch capability. This enhancement allows a higher sustained throughput to the 16-bit
PC Card, because the 1451 prefetches an extra 16 bits (32 bits total) during each PCI read transaction. If the PCI
Bus becomes busy, then the 1451 has an extra 16 bits of data to perform back-to-back 16-bit transactions to the PC
Card before having to fetch more data. This feature is built into the DMA engine and software is not required to enable
this enhancement.
NOTE:The 11XX and 12XX series CardBus controllers have enough 16-bit bandwidth to
support MPEG II PC Card decoders. But it was decided to improve the bandwidth even more
in the 14XX series CardBus controllers.
3.4.6 D3_STAT Terminal
Additional functionality added for the 1451 versus the 1250A/1251 series is the D3_STAT (D3 status) terminal. This
terminal is asserted under the following two conditions (both conditions must be true before D3_STAT is asserted):
•
•
Function 0 and Function 1 are placed in D3
PME is enabled on either function
TheintentofincludingthisfeatureinthePCI1451istousethispintoswitchanexternalV /V
switch. Thisfeature
CC AUX
can be programmed on MFUNC7, MFUNC6, MFUNC2, or MFUNC1 by writing 100b to the appropriate multifunction
routing status register bits (PCI offset 8Ch).
3.4.7 Internal Ring Oscillator
The internal ring oscillator provides an internal clock source for the PCI1451 so that neither the PCI clock nor an
external clock is required in order for the PCI1451 to power down a socket or interrogate a PC Card. This internal
oscillator operates nominally at 16 kHz and can be enabled by setting bit 27 (P2CCLK) of the system control register
(PCI offset 80h) to a 1b. This function is disabled by default.
3–11
3.4.8 Integrated Pullup Resistors
The 1997 PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit card
configurations. Unlike the PCI1450/4450 which required external pullup resistors, the PCI1451 has integrated all of
these pullup resistors, except for the WP(IOIS16)/CLKRUN pullup resistor.
GJG PIN NUMBER
SIGNAL NAME
SOCKET A
SOCKET B
C18
E11
ADDR14/CPERR
READY/CINT
D1
K2
F4
F8
K1
C2
D2
E5
F5
H6
H2
K4
J4
ADDR15/CIRDY
CD1/CCD1
B16
J19
VS1/CVS1
B11
ADDR19/CBLOCK
ADDR20/CSTOP
ADDR21/CDEVSEL
ADDR22/CTRDY
VS2/CVS2
D16
B19
A18
B17
A14
F13
RESET/CRST
WAIT/CSERR
F11
INPACK/CREQ
A13
F10
BVD2(SPKR)/CAUDIO
BVD1(STSCHG)/CSTSCHG
CD2/CCD2
L6
L1
L4
A10
D10
†
L2
†
B10
WP(IOIS16)/CLKRUN
†
This pin requires pullup, but the PCI1451 lacks an integrated pullup
resistor.
3.4.9 SPKROUT Usage
The SPKROUT signal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is
configured for I/O mode, the BVD2 pin becomes SPKR. This terminal, also used in CardBus applications, is referred
to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI1451. The CardBus CAUDIO signal also can
pass a single amplitude, binary waveform. The binary audio signals from the two PC Card sockets are XOR’ed in the
PCI1451 to produce SPKROUT. Figure 3–12 illustrates the SPKROUT connection.
Bit 1, Card Control Register (offset 91h)
Card A SPKROUT Enable
Card A SPKR
SPKROUT
Speaker
Driver
Bit 1, Card Control Register (offset 91h)
Card B SPKROUT Enable
Card B SPKR
Card A SPKROUT Enable
Card B SPKROUT Enable
Figure 3–12. SPKROUT Connection to Speaker Driver
The SPKROUT signal is typically driven only by PC modem cards. To verify the SPKROUT on the PCI1451, a sample
circuit was constructed, and this simplified schematic is provided below. The PCI1130/1131 required a pullup resistor
on the SUSPEND/SPKROUT terminal. Since the PCI1451 does not multiplex any other function on SPKROUT, this
terminal does not require a pullup resistor.
3–12
V
CC
V
CC
SPKROUT
6
3
7
2
Speaker
1
8
+
–
4
LM386
Figure 3–13. Simplified Test Schematic
3.4.10 LED Socket Activity Indicators
The socket activity LEDs indicate when an access is occurring to a PC Card. The LED signals are programmable
via the MFUNC register. When configured for LED outputs, these terminals output an active high signal to indicate
socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity.
The active-high LED signal is driven for 64 ms durations. When the LED is not being driven high, then it is driven to
a low state. Either of the two circuits illustrated in Figure 3–14 can be implemented to provide the LED signaling, and
it is left for the board designer to implement the circuit to best fit the application.
Current Limiting
R ≈ 500 Ω
PCI1451
LED
Current Limiting
R ≈ 500 Ω
Application-
Specific Delay
PCI1451
LED
Figure 3–14. Two Sample LED Circuits
As indicated, the LED signals are driven for 64 ms, and this is accomplished by a counter circuit. To avoid the
possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when either
the SUSPEND signal is asserted or when the PCI clock is to be stopped per the CLKRUN protocol.
Furthermore, if any additional socket activity occurs during this counter cycle, then the counter is reset and the LED
signalremainsdriven. Ifsocketactivityisfrequent(atleastonceevery64ms), thentheLEDsignalswillremaindriven.
3.4.11 PC Card 16 DMA Support
The PCI1451 supports both PC/PCI (centralized) DMA and a distributed DMA slave engine for 16-bit PC Card DMA
support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA
engine. Table 3–3 provides the DDMA register configuration.
3–13
Table 3–3. Distributed DMA Registers
REGISTER NAME
DMA BASE
ADDRESS OFFSET
TYPE
R
W
R
Current address
00h
04h
08h
0Ch
Reserved
Reserved
Page
Base address
Current count
Reserved
W
R
Base count
N/A
Mode
N/A
Request
N/A
Status
Reserved
Reserved
W
R
Command
Multichannel
Mask
Reserved
W
Master clear
3.4.12 CardBus Socket Registers
The PCI1451 contains all registers for compatibility with the 1997 PC Card Standard. These registers exist as the
CardBus socket registers, and are listed in Table 3–4.
Table 3–4. CardBus Socket Registers
OFFSE
REGISTER NAME
T
Socket event
Socket mask
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
Socket present state
Socket force event
Socket control
Reserved
Reserved
Reserved
Socket power management
3.5 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI1451. The PCI1451 provides several interrupt signaling schemes to accommodate the needs of a variety of
platforms. The different mechanisms for dealing with interrupts in this device are based upon various specifications
and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the
CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1451 is therefore
backward compatible with existing interrupt control register definitions, and new registers have been defined where
required.
The PCI1451 detects PC Card interrupts and events at the PC Card interface and notifies the host controller via one
of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1451, PC Card interrupts
are classified as either card status change (CSC) or as functional interrupts.
The method by which any type of PCI1451 interrupt is communicated to the host interrupt controller varies from
system to system. The PCI1451 offers system designers the choice of using parallel PCI interrupt signaling, parallel
ISA type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. Traditional ISA IRQ
signaling is provided through eight IRQMUX terminals. It is possible to use the parallel PCI interrupts in combination
with either parallel IRQs or serialized IRQs, as detailed in the sections that follow.
3–14
3.5.1 PC Card Functional And Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service. They are
indicated by asserting specially defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC) type interrupts, defined as events at the PC Card interface which are detected by the
PCI1451, may warrant notification of host card and socket services software for service. CSC events include both
card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.
Table 3–5 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent upon the type of card inserted in the PC Card socket. The three types of
cards that may be inserted into any PC Card socket are: 16-bit memory card, 16-bit I/O card, and CardBus cards.
Functional interrupt events are valid only for 16-bit I/O and CardBus cards, that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal type CSC interrupts are independent of the
card type.
Table 3–5. PC Card Interrupt Events and Description
Card Type
Event
Type
Signal
Description
BVD1 (STSCHG) //
CSTSCHG
A transition on the BVD1 signal indicates a change in the
PC Card battery conditions.
CSC
Battery conditions
(BVD1, BVD2)
A transition on the BVD2 signal indicates a change in the
PC Card battery conditions.
CSC
CSC
BVD2 (SPKR) // CAUDIO
READY (IREQ) // CINT
16-bit Memory
Wait states
(READY)
A transition on the READY signal indicates a change in the
ability of the memory PC Card to accept or provide data.
Change in card status
(STSCHG)
BVD1 (STSCHG) //
CSTSCHG
The assertion of the STSCHG signal indicates a status
change on the PC Card.
CSC
16-bit I/O
CardBus
Interrupt request
(IREQ)
The assertion of the IREQ signal indicates an interrupt
request from the PC Card.
Functional
CSC
READY (IREQ) // CINT
Change in card status
(CSTSCHG)
BVD1 (STSCHG) //
CSTSCHG
The assertion of the CSTSCHG signal indicates a status
change on the PC Card.
Interrupt request
(CINT)
The assertion of the CINT signal indicates an interrupt
request from the PC Card.
Functional
CSC
READY (IREQ) // CINT
N/A
An interrupt is generated when a PC Card power-up cycle
has completed.
Power cycle complete
A transition on either the CD1//CCD1 signal or the
CD2//CCD2 signal indicates an insertion or removal of a
16-bit // CardBus PC Card.
Card insertion or
removal
CD1 // CCD1,
CD2 // CCD2
CSC
CSC
All PC Cards
An interrupt is generated when a PC Card power-up cycle
has completed.
Power cycle complete
N/A
The signal naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well
as CardBus. For example, the READY(IREQ)//CINT signal includes the READY signal for 16-bit memory cards, the
IREQ signal for 16-bit I/O cards, and the CINT signal for CardBus cards. The 16-bit memory card signal name is first,
with the I/O card signal name second enclosed in parentheses. The CardBus signal name follows after a forward
double slash (//).
The PC Card Standard describes the power-up sequence that must be followed by the PCI1451 when an insertion
event occurs and the host requests that the socket V
and V
be powered. Upon completion of this power-up
CC
PP
sequence, the PCI1451 interrupt scheme may be used to notify the host system, as in indicated in Table 3–5, denoted
by the power cycle complete event. This interrupt source is considered a PCI1451 internal event because it does not
depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket.
3–15
3.5.2 Interrupt Masks And Flags
Host software may individually mask, or disable, most of the potential interrupt sources listed in Table 3–6 by setting
the appropriate bits in the PCI1451. By individually masking the interrupt sources listed in these tables, software can
control which events will cause a PCI1451 interrupt. Host software has some control over which system interrupt the
PCI1451 will assert by programming the appropriate routing registers. The PCI1451 allows host software to route
PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing is somewhat specific
to the interrupt signaling method used. This will be discussed in more detail in the following sections.
When an interrupt is signaled by the PCI1451, the interrupt service routine must be able to discern which of the events
in Table 3–6 caused the interrupt. Internal registers in the PCI1451 provide flags which report which of the interrupt
sources was the cause of an interrupt. By reading these status bits, the interrupt service routine can determine which
action is to be taken.
Table 3–6 details the registers and bits associated with masking and reporting potential interrupts. All interrupts may
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Table 3–6. PCI1451 Interrupt Masks and Flags Registers
Card Type
Event
Mask
Flag
Battery conditions
(BVD1, BVD2)
ExCA Offset 05h/45h/805h
Bits 1 and 0
ExCA Offset 04h/44h/804h
Bits 1 and 0
16-bit Memory
Wait states
(READY)
ExCA Offset 05h/45h/805h
Bit 2
ExCA Offset 04h/44h/804h
Bit 2
Change in card status
(STSCHG)
ExCA Offset 05h/45h/805h
Bit 0
ExCA Offset 04h/44h/804h
Bit 0
16-bit I/O
Interrupt request
(IREQ)
PCI Configuration Offset 91h
Bit 0
Always enabled
ExCA Offset 05h/45h/805h
Bit 3
ExCA Offset 04h/44h/804h
Bit 3
All 16-bit PC Cards
Power cycle complete
Change in card status
(CSTSCHG)
Socket mask register
Bit 0
Socket event register
Bit 0
Interrupt request
(CINT)
PCI Configuration Offset 91h
Bit 0
Always enabled
CardBus
Socket mask register
Bit 3
Socket event register
Bit 3
Power cycle complete
Socket mask register
Bits 2 and 1
Socket event register
Bits 2 and 1
Card insertion or removal
There is no mask bit to stop the PCI1451 from passing PC Card functional interrupts through to the appropriate
interrupt scheme. Functional interrupts should not be fired until the PC Card is initialized and powered.
There are various methods of clearing the interrupt flag bits listed in Table 3–6. The flag bits in the ExCA registers
(16-bit PC Card related interrupt flags) may be cleared by two different methods. One method is an explicit write of
1 to the flag bit to clear, and the other is a reading of the flag bit register. The selection of flag bit clearing is made
by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the flag cleared on read method.
The CardBus related interrupt flags can only be cleared by an explicit write of 1 to the interrupt flag in the socket event
register. AlthoughsomeofthefunctionalityissharedbetweentheCardBusregistersandtheExCAregisters, software
should not program the chip through both register sets when a CardBus card is functioning.
3.5.3 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when in pure parallel PCI interrupt mode and are routed on MFUNC0–MFUNC2.
The PCI interrupt signaling is dependent upon the interrupt mode and is summarized in Table 3–7. The interrupt mode
is selected in the device control register (92h).
3–16
Table 3–7. Interrupt Pin Register Cross Reference
INTPIN
INTPIN
Function 1
Interrupt Signaling Mode
Function 0
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
Parallel PCI interrupts only
0x02 (INTB)
0x02 (INTB)
0x01 (INTA)
0x02 (INTB)
Reserved
IRQ serialized (IRQSER) & parallel PCI interrupts
IRQ & PCI serialized (IRQSER) interrupts (default)
3.6 Power Management Overview
In addition to the low-power CMOS technology process used for the PCI1451, various features are designed into the
device to allow implementation of popular power saving techniques. These features and techniques are discussed
in this section.
3.6.1 CLKRUN Protocol
CLKRUN is the primary method of power management on the PCI bus side of the PCI1451. Since some chipsets
do not implement CLKRUN, this is not always available to the system designer, and alternate power savings features
are provided.
If CLKRUN is not implemented, then the CLKRUN pin should be tied low. CLKRUN is enabled by default via bit 1
(KEEPCLK) in the system control register (80h).
3.6.2 CardBus PC Card Power Management
The PCI1451 implements its own card power management engine that can turn off the CCLK to a socket when there
is no activity to the CardBus PC Card. The CCLK can also be configured as divide by 16 instead of stopped. The
CLKRUN protocol is followed on the CardBus interface to control this clock management.
3.6.3 PCI Bus Power Management
The PCI Bus Power Management Interface Specification (PCIPM) establishes the infrastructure required to let the
operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations
to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four
software visible power management states, which result in varying levels of power savings.
The four power management states of PCI functions are: D0 - Fully On state, D1 and D2 - intermediate states, and
D3 - Off state. Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from
the device power state of the upstream bridge device.
For the operating system to manage the device power states on the PCI bus, the PCI function should support four
power management operations. The four operations are: capabilities reporting; power status reporting; setting the
power state; and system wake-up. The operating system identifies the capabilities of the PCI function by traversing
the new capabilities list. The presence of new capabilities is indicated by a 1b in bit 4 of the status register (PCI offset
06h). When software determines that the device has a capabilities list by seeing that bit 4 of the status register is set,
it will read the capability pointer register at PCI offset 14h. This value in the register points the location in PCI
configuration space of the capabilities linked list.
The first byte of each capability register block is required to be a unique ID of that capability. PCI power management
has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there
are no more items in the list, then the next item pointer should be set to 0. The registers following the next item pointer
are specific to the function’s capability. The PCIPM capability implements the following register block:
Power Management Register Block
Power management capabilities (PMC)
Data PMCSR bridge support extensions
Next item pointer
Capability ID
Offset = 0
Offset = 4
Power management control status (CSR)
3–17
The power management capabilities (PMC) register is a static read-only register that provides information on the
capabilities of the function, related to power management. The PMCSR register enables control of power
management states and enables/monitors power management events. The data register is an optional register that
provides a mechanism for state-dependent power measurements such as power consumed or heat dissipation.
3.6.4 CardBus Device Class Power Management
The PCI Bus Interface Specification for PCI-to-CardBus Bridges was approved by PCMCIA in December of 1997.
This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface
Specification published by the PCI Special Interest Group (SIG). The main issue addressed in the PCI Bus Interface
SpecificationforPCI-to-CardBusBridges is wake-up fromD3 orD3
PME context).
withoutlosingwake-upcontext(alsocalled
hot
cold
The specific issues addressed by the PCI Bus Interface Specification for PCI-to-CardBus Bridges for D3 wake-up
are as follows:
•
Preservation of device context: The PCI Power Management Specification version 1.0 states that PRST
must be asserted when transitioning from D3 to D0. Some method to preserve wake-up context must
be implemented so that PRST does not clear the PME context registers.
cold
•
Power source in D3 if wake-up support is required from this state.
cold
The Texas Instruments PCI1451 addresses these D3 wake-up issues in the following manner:
•
Preservation of device context: When PRST is asserted, bits required to preserve PME context are not
cleared. To clear all bits in the PCI1451, another reset pin is defined: GRST (global reset). GRST is normally
only asserted during the initial power-on sequence. After the initial boot, PRST should be asserted so that
PMEcontext is retained for D3-to-D0 transitions. Bits cleared by GRST, but not cleared by PRST (if the PME
enable bit is set), are referred to as PME context bits. Please refer to the master list of PME context bits
in Section 3.6.5.
•
Power source in D3
auxiliary power source must be switched to the PCI1451 V
break type of switch, so that V
if wake-up support is required from this state. Since V
is removed in D3
, an
cold
CC
cold
pins. This switch should be a make before
CC
to the PCI1451 is not interrupted.
CC
3.6.5 Master List Of PME Context Bits and Global Reset Only Bits
PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit is set (PCI offset
A4h, bit 8). If PME is not enabled, then these bits are cleared when either PRST or GRST is asserted.
Global reset only bits, as the name implies, are only cleared by GRST. These bits are never cleared by PRST
regardlessofthesettingofthePMEenablebit. (PCIoffsetA4h, bit8). TheGRSTsignalisgatedonlybytheSUSPEND
signal. This means that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register
contents.
Global reset only bits:
•
•
•
•
•
•
•
•
•
•
•
Subsystem ID/subsystem vendor ID (PCI offset 40h): bits 31–0
PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31–1
System control register (PCI offset 80h): bits 31–29, 27–24, 22–14, 6–3, 1, 0
Multimedia control register (PCI offset 84h): bits 7–0
General status register (PCI offset 85h): bits 2–0
General-purpose event status register (PCI offset 88h): bits 7, 6, 3–0
General-purpose event enable register (PCI offset 89h): bits 7, 6, 3–0
General-purpose input register (PCI offset 8Ah): bits 3–0
General-purpose output register (PCI offset 8Bh): bits 3–0
MFUNC routing register (PCI offset 8Ch): bits 31–0
Retry status register (PCI offset 90h): bits 7–1
3–18
•
•
•
•
•
•
Card control register (PCI offset 91h): bits 7, 6, 2, 1, 0
Device control register (PCI offset 92h): bits 7–0
Diagnostic register (PCI offset 93h): bits 7–0
Socket DMA register 0 (PCI offset 94h): bits 1–0
Socket DMA register 1 (PCI offset 98h): bits 15–0
GPE control/status register (PCI offset A8h): bits 10, 9, 8, 2, 1, 0
PME context bits
•
•
•
•
•
•
•
•
•
•
Bridge control register (PCI offset 3Eh): bit 6
Power management capabilities register (PCI offset A2h): bit 15
Power management control/status register (PCI offset A4h): bits 15, 8
ExCA power control register (ExCA 802h/842h): bits 7, 4, 3, 1, 0
ExCA interrupt and general control (ExCA 803h/843h): bit 6, 5
ExCA card status change register (ExCA 804h/844h): bits 3–0
ExCA card status change interrupt register (ExCA 805h/845h): bits 3–0
CardBus socket event register (CardBus offset 00h): bits 3–0
CardBus socket mask register (CardBus offset 04h): bits 3–0
CardBus socket control register (CardBus offset 10h): bits 6, 5, 4, 2, 1, 0
3.6.6 System Diagram Implementing CardBus Device Class Power Management
PCI Bus
Real Time
Clock‡
South Bridge
PRST
GRST†
Clock
CLKRUN
TPS2206
PCI1451
2
Power
Switch
Embedded
Controller
PME
Vcc
System Vcc
PC Card
Socket A
68
68
D3
Status
V
aux
PC Card
Socket B
Make before
break switch
†
‡
The system connection to GRST is implementation specific. GRST should be applied whenever V is applied to the PCI1451. PRST should be
cc
applied for subsequent warm resets.
Not required if internal oscillator is used.
Figure 3–15. System Diagram Implementing CardBus Device Class Power Management
3–19
3.6.7 Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the PCI1451. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the PCI1451
in order to minimize power consumption.
Gating PCLK does not create any issues with respect to the power switch interface in the PCI1451. This is because
the PCI1451 does not depend on the PCI clock to clock the power switch interface. There are two methods to clock
the power switch interface in the PCI1451:
•
•
Use an external clock to the PCI1451 CLOCK pin
Use the internal oscillator
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, thenthePCIclockwillhavetoberestartedinordertopasstheinterrupt, becauseneithertheinternaloscillator
nor an external clock is routed to the serial interrupt state machine.
PRST
GRST
PCI1451
Core
SUSPEND
GNT
PCLK
Figure 3–16. SUSPEND Functional Illustration
3.6.8 Requirements For SUSPEND
A requirement for implementing suspend mode is that the PCI bus must not be parked on the PCI1451 when
SUSPEND is asserted. The PCI1451 responds to SUSPEND being asserted by placing the REQ pin in a high
impedance state. The PCI1451 will also gate the internal clock and reset.
The GPIOs, MFUNC signals, and RI_OUT signals are all active during SUSPEND, unless they are disabled in the
appropriate PCI1451 registers.
3.6.9 Ring Indicate
The RI_OUT output is an important feature used in legacy power management. It is used so that a system can go
into a suspended mode and wake up on modem rings and other card events. The RI_OUT signal on the PCI1451
may be asserted under any of the following conditions:
•
•
•
A 16-bit PC Card modem in a powered socket asserts RI to indicate an incoming call to the system.
A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.
A card status change (CSC) event, such as insertion/removal of cards, battery voltage levels, occurs.
A CSTSCHG signal from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two
RI_OUT events are enabled separately. The following figure details various enable bits for the PCI1451 RI_OUT
function; however, it does not illustrate the masking of CSC events. See interrupt masks and flags for a detailed
description of CSC interrupt masks and flags.
RI_OUT is multiplexed on the same pin with PME. The default is for RI_OUT to be signaled on this pin. In PCI power
managed systems, the PME signal should be enabled by setting bit 0 (RI_OUT/PME) in the system control register
(80h) and clearing bit 7 (RIENB) in the card control register (91h).
3–20
RI_OUT Function
PC Card
Socket 0
Card
I/F
16-bit
Card
Bus
CSC
RI
CBWAKE
RIENB
RICSC(A)
RICSC(B)
RI_OUT
CSC
CBWAKE
RI
PC Card
Socket 1
Card
I/F
16-bIt
Card
Bus
Figure 3–17. RI_OUT Functional Illustration
Routing of CSC events to the RI_OUT signal, enabled on a per-socket basis, is programmed by the RICSC bit in the
card control register. This bit is socket dependent (not shared), as illustrated in Figure 3–17.
The RI signal from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the ExCA interrupt and
general control register. This is programmed on a per-socket basis, and is only applicable when a 16-bit card is
powered in the socket.
The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers.
3–21
3–22
4 PC Card Controller Programming Model
This chapter describes the PCI1451 PCI configuration registers that make up the 256-byte PCI configuration header
for each PCI1451 function. As noted below, some bits are global in nature and should be accessed only through
function 0.
4.1 PCI Configuration Registers (Functions 0 and 1)
The PCI1451 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The
configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, is PC 98/PC 99
compliant as well. Table 4–1 illustrates the PCI configuration header, which includes both the predefined portion of
the configuration space and the user definable registers.
Table 4–1. Functions 0 and 1 PCI Configuration Register Map
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
Command
04h
Class code
Header type
Revision ID
08h
BIST
Latency timer
Cache line size
0Ch
10h
CardBus socket/ExCA base address
Reserved
Secondary status
Capability pointer
PCI bus number
14h
CardBus latency timer
Subordinate bus number
CardBus bus number
18h
CardBus memory base register 0
CardBus memory limit register 0
CardBus memory base register 1
CardBus memory limit register 1
CardBus I/O base register 0
CardBus I/O limit register 0
1Ch
20h
24h
28h
2Ch
30h
CardBus I/O base register 1
CardBus I/O limit register 1
34h
38h
Bridge control
Subsystem ID
Interrupt pin
Interrupt line
3Ch
40h
Subsystem vendor ID
PC Card 16-bit I/F legacy mode base address
44h
Reserved
48h–7Fh
80h
System control
Reserved
Reserved
General-purpose input
Multifunction routing status
Device control Card control
Socket DMA register 0
General status
Multimedia control
84h
General-purpose output
General-purpose event enable General-purpose event status
88h
8Ch
90h
Diagnostic
Retry status
94h
Socket DMA register 1
Reserved
98h
9Ch
A0h
A4h
A8h
Power management capabilities
Next pointer item
Capability ID
Data (Reserved)
PMCSR bridge support extensions
Reserved
Power management control/status
GPE control/status
4–1
4.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Type:
Vendor ID
Read-only
Offset:
Default:
00h (Functions 0, 1)
104Ch
4.3 Device ID Register
The device ID register contains a value assigned to the PCI1451 by Texas Instruments. The device identification for
the PCI1451 is AC52h.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID
R
1
R
0
R
1
R
0
R
1
R
1
R
0
R
0
R
0
R
1
R
0
R
1
R
0
R
0
R
1
R
0
Register:
Type:
Device ID
Read-only
Offset:
Default:
02h (Functions 0, 1)
AC52h
4–2
4.4 Command Register
The command register provides control over the PCI1451 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, see Table 4–2. None of the bit functions in this register are shared
between the two PCI1451 PCI functions. Two command registers exist in the PCI1451, one for each function.
Software manipulates the two PCI1451 functions as separate entities when enabling functionality through the
command register. The SERR_EN (bit 8) and PERR_EN (bit 6) enable bits in this register are internally wired OR
between the two functions, and these control bits appear separate per function to software.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Command
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Command
Read-only, Read/Write
Offset:
Default:
04h
0000h
Table 4–2. PCI Command Register Description
FUNCTION
BIT
SIGNAL
TYPE
15–10
RSVD
R
Reserved. Bits 15–10 return 0s when read.
Fast back-to-back enable. The PCI1451 does not generate fast back-to-back transactions; therefore, bit 9returns
0 when read.
9
8
FBB_EN
R
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be
asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the PCI1451
to report address parity errors.
SERR_EN
R/W
0 = Disables the SERR output driver (default).
1 = Enables the SERR output driver.
Address/data stepping control. The PCI1451 does not support address/data stepping; therefore, bit 7 is
hardwired to 0.
7
6
STEP_EN
PERR_EN
R
Parity error response enable. Bit 6 controls the PCI1451’s response to parity errors through PERR. Data parity
errors are indicated by asserting PERR, while address parity errors are indicated by asserting SERR.
0 = PCI1451 ignores detected parity error (default).
R/W
1 = PCI1451 responds to detected parity errors.
VGA palette snoop. When bit 5 is set to 1, palette snooping is enabled (that is, the PCI1451 does not respond
5
VGA_EN
R/W to palette register writes and snoops the data). When this bit is 0, the PCI1451 treats all palette accesses like all
other accesses.
Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and
4
3
MWI_EN
SPECIAL
R
R
invalidate commands. The PCI1451 controller does not support memory write and invalidate commands, it uses
memory write commands instead; therefore, this bit is hardwired to 0.
Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1451 does not
respond to special cycle operations; therefore, this bit is hardwired to 0.
Bus master control. Bit 2 controls whether or not the PCI1451 can act as a PCI bus initiator (master). The PCI1451
can take control of the PCI bus only when this bit is set.
2
MAST_EN
R/W
0 = Disables the PCI1451’s ability to generate PCI bus accesses (default).
1 = Enables the PCI1451’s ability to generate PCI bus accesses.
Memory space enable. Bit 1 controls whether or not the PCI1451 may claim cycles in PCI memory space.
0 = Disables the PCI1451’s response to memory space accesses (default).
1 = Enables the PCI1451’s response to memory space accesses.
1
0
MEM_EN
IO_EN
R/W
R/W
I/O space control. Bit 0 controls whether or not the PCI1451 may claim cycles in PCI I/O space.
0 = Disables the PCI1451 from responding to I/O space accesses (default).
1 = Enables the PCI1451 to respond to I/O space accesses.
4–3
4.5 Status Register
The status register provides device information to the host system. Bits in this register may be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the PCI Local Bus Specification. PCI bus status is shown through each function.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Status
R/C
0
R/C
0
R/C
0
R/C
0
R/C
0
R
0
R
1
R/C
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Status
Read-only, Read/Write to Clear
06h (Functions 0, 1)
0210h
Table 4–3. Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. Bit 15 is set when a parity error (either address or data) is detected. Write a 1 to clear
this bit.
15
PAR_ERR
R/C
Signaledsystem error. Bit 14 is set when SERRis enabled and the PCI1451 signals a system error to the host.
Write a 1 to clear this bit.
14
13
SYS_ERR
MABORT
R/C
R/C
R/C
R/C
R
Receivedmaster abort. Bit 13 is set when a cycle initiated by the PCI1451 on the PCI bus has been terminated
by a master abort. Write a 1 to clear this bit.
Received target abort. Bit 12 is set when a cycle initiated by the PCI1451 on the PCI bus was terminated by
a target abort. Write a 1 to clear this bit.
12
TABT_REC
TABT_SIG
PCI_SPEED
Signaledtarget abort. Bit 11 is set by the PCI1451 when it terminates a transaction on the PCI bus with a target
abort. Write a 1 to clear this bit.
11
DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b indicating that the
PCI1451 asserts this signal at a medium speed on nonconfiguration cycle accesses.
10–9
Data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. PERR was asserted by any PCI device including the PCI1451.
b. The PCI1451 was the bus master during the data parity error.
c. Bit 6 (PERR_EN) is set in the command register (PCI offset 04h, see Section 4.4).
8
DATAPAR
R/C
Fast back-to-back capable. The PCI1451 cannot accept fast back-to-back transactions; therefore, bit 7 is
hardwired to 0.
7
6
5
FBB_CAP
UDF
R
R
R
User-definable feature support. The PCI1451 does not support the user definable features; therefore, bit 6
is hardwired to 0.
66-MHz capable. The PCI1451 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is
hardwired to 0.
66MHZ
Capabilities list. Bit 4 returns 1 when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power management capabilities is implemented in this
function.
4
CAPLIST
RSVD
R
R
3–0
Reserved. Bits 3–0 return 0s when read.
4–4
4.6 Revision ID Register
The revision ID register indicates the slicon revision of the PCI1451.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Revision ID
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Revision ID
Read-only
Offset:
Default:
08h (Functions 0, 1)
02h
4.7 PCI Class Code Register
The PCI class code register recognizes the PCI1451 functions 0 and 1 as a bridge device (06h) and CardBus bridge
device (07h) with a 00h programming interface.
Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Byte
Name
Type
Default
Base Class
Sub Class
Programming Interface
PCI class code
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
PCI class code
Read-only
Offset:
Default:
09h (Functions 0, 1)
060700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Cache line size
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Cache line size
Read/Write
Offset:
Default:
0Ch (Functions 0, 1)
00h
4–5
4.9 Latency Timer Register
The latency timer register specifies the latency timer for the PCI1451, in units of PCI clock cycles. When the PCI1451
is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires
before the PCI1451 transaction has terminated, then the PCI1451 terminates the transaction when its GNT is
deasserted.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Latency timer
Read/Write
0Dh
00h
4.10 Header Type Register
The header type register returns 82h when read, indicating that the PCI1451 functions 0 and 1 configuration spaces
adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and
80h–FFh are user-definable extension registers.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Header type
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Header type
Read-only
Offset:
Default:
0Eh (Functions 0, 1)
82h
4.11 BIST Register
Since the PCI1451 does not support a built-in self-test (BIST), this register returns the value of 00h when read. This
register returns 0s for the two PCI1451 functions.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
BIST
Read-only
Offset:
Default:
0Fh (Functions 0, 1)
00h
4–6
4.12 CardBus Socket/ExCA Base-Address Register
This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped
ExCA register set. Bits 31–12 are read/write and allow the base address to be located anywhere in the 32-bit PCI
memory address space on a 4-Kbyte boundary. Bits 11–0 are read-only, returning 0s when read. When software
writes all 1s to this register, the value read back will be FFFF F000h, indicating that at least 4K bytes of memory
address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers
begin at offset 800h. This register is not shared by functions 0 and 1, mapping each socket control register separately.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CardBus socket/ExCA base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus socket/ExCA base address
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
CardBus socket/ExCA base address
Read-only, Read/Write
10h
0000 0000h
4.13 Capability Pointer Register
ThecapabilitypointerregisterprovidesapointerintothePCIconfigurationheaderwherethePCIpowermanagement
register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each
socket has its own capability pointer register. This register returns A0h when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability pointer
R
1
R
0
R
1
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Capability pointer
Read-only
14h
A0h
4–7
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-PCI bridge secondary status register and indicates CardBus
related device information to the host system. This register is very similar to the status register (offset 06h, see
Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket functions, but
is accessed on a per socket basis.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary status
R/C
0
R/C
0
R/C
0
R/C
0
R/C
0
R
0
R
1
R/C
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Secondary status
Read-only, Read/Write to Clear
Offset:
Default:
16h
0200h
Table 4–4. Secondary Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. Bit 15 is set when a CardBus parity error (either address or data) is detected.
Write a 1 to clear this bit.
15
CBPARITY
R/C
Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1451 does
not assert the CSERR signal. Write a 1 to clear this bit.
14
13
CBSERR
CBMABORT
REC_CBTA
SIG_CBTA
CB_SPEED
R/C
R/C
R/C
R/C
R
Received master abort. Bit 13 is set when a cycle initiated by the PCI1451 on the CardBus bus has
been terminated by a master abort. Write a 1 to clear this bit.
Received target abort. Bit 12 is set when a cycle initiated by the PCI1451 on the CardBus bus was
terminated by a target abort. Write a 1 to clear this bit.
12
Signaled target abort. Bit 11 is set by the PCI1451 when it terminates a transaction on the CardBus
bus with a target abort. Write a 1 to clear this bit.
11
CDEVSEL timing. Bits 10 and 9 encode the timing of CDEVSEL and are hardwired to 01b, indicating
that the PCI1451 asserts this signal at a medium speed.
10–9
CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
8
CB_DPAR
R/C
b. The PCI1451 was the bus master during the data parity error.
c. Bit 0 (CPERREN) is set in the bridge control register (PCI offset 3Eh, see Section 4.25).
Fast back-to-back capable. The PCI1451 cannot accept fast back-to-back transactions; therefore, bit 7
is hardwired to 0.
7
6
CBFBB_CAP
CB_UDF
R
R
User-definable feature support. The PCI1451 does not support the user-definable features; therefore,
bit 6 is hardwired to 0.
66 MHz capable. The PCI1451 CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
5
CB66MHZ
RSVD
R
R
4–0
Reserved. Bits 4–0 return 0s when read.
4–8
4.15 PCI Bus Number Register
The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which
the PCI1451 is connected. The PCI1451 uses this register, in conjunction with the CardBus bus number and
subordinate bus number registers, to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PCI bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
PCI bus number
Read/Write
Offset:
Default:
18h (Functions 0, 1)
00h
4.16 CardBus Bus Number Register
The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus
to which the PCI1451 is connected. The PCI1451 uses this register, in conjunction with the PCI bus number and
subordinate bus number registers, to determine when to forward PCI configuration cycles to its secondary buses.
This register is separate for each PCI1451 controller function.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
CardBus bus number
Read/Write
19h
00h
4.17 Subordinate Bus Number Register
The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below
the CardBus bus. The PCI1451 uses this register, in conjunction with the PCI bus number and CardBus bus number
registers, to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for
each CardBus controller function.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Subordinate bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Subordinate bus number
Read/Write
1Ah
00h
4–9
4.18 CardBus Latency Timer Register
The CardBus latency timer register is programmed by the host system to specify the latency timer for the PCI1451
CardBus interface, in units of CCLK cycles. When the PCI1451 is a CardBus initiator and asserts CFRAME, the
CardBus latency timer begins counting. If the latency timer expires before the PCI1451 transaction has terminated,
then the PCI1451 terminates the transaction at the end of the next data phase. A recommended minimum value for
this register of 20h allows most transactions to be completed.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
CardBus latency timer
Read/Write
Offset:
Default:
1Bh (Functions 0, 1)
00h
4.19 Memory Base Registers 0, 1
The memory base registers indicate the lower address of a PCI memory address range. These registers are used
by the PCI1451 to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to the PCI bus. Bits 31–12 of these registers are read/write and allow the memory base to be located
anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write
transactions to these bits have no effect. Bits 8 (PREFETCH0) and 9 (PREFETCH1) of the bridge control register
(PCI offset 3Eh, see Section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable.
The memory base register or the memory limit register must be nonzero in order for the PCI1451 to claim any memory
transactions through CardBus memory windows (that is, these windows are not enabled by default to pass the first
4K bytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Memory base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Memory base registers 0, 1
Read-only, Read/Write
1Ch, 24h
0000 0000h
4–10
4.20 Memory Limit Registers 0, 1
The memory limit registers indicate the upper address of a PCI memory address range. These registers are used
by the PCI1451 to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to the PCI bus. Bits 31–12 of these registers are read/write and allow the memory base to be located
anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write
transactions to these bits have no effect. Bits 8 (PREFETCH0) and 9 (PREFETCH1) of the bridge control register
(PCI offset 3Eh, see Section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable.
The memory base register or the memory limit register must be nonzero in order for the PCI1451 to claim any memory
transactions through CardBus memory windows (that is, these windows are not enabled by default to pass the first
4K bytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Memory limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Memory limit registers 0, 1
Read-only, Read/Write
20h, 28h
0000 0000h
4.21 I/O Base Registers 0, 1
The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the
PCI1451 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page and the
upper 16 bits (31–16) are all 0s which locate this 64-Kbyte page in the first page of the 32-bit PCI I/O address space.
Bits31–16andbits1–0areread-onlyandalwaysreturn0s, forcingI/Owindowstobealignedonanaturaldoubleword
boundary in the first 64-Kbyte page of PCI I/O address space. These I/O windows are enabled when either the I/O
base register or the I/O limit register are nonzero. The I/O windows are not enabled by default to pass the first
doubleword of I/O to CardBus.
Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
I/O base registers 0, 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
I/O base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
I/O base registers 0, 1
Read-only, Read/Write
2Ch, 34h
0000 0000h
4–11
4.22 I/O Limit Registers 0, 1
TheI/OlimitregistersindicatetheupperaddressofaPCII/Oaddressrange. TheseregistersareusedbythePCI1451
to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to the PCI
bus. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page and the upper 16 bits
are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and
allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16 of the appropriate
I/O base register) on doubleword boundaries.
Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are
read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to
read-only bits have no effect. The PCI1451 assumes that the lower 2 bits of the limit address are 1s.
TheseI/OwindowsareenabledwheneithertheI/ObaseregisterortheI/Olimitregisterarenonzero. TheI/Owindows
are not enabled by default to pass the first doubleword of I/O to CardBus.
Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
I/O limit registers 0, 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
I/O limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
I/O limit registers 0, 1
Read-only, Read/Write
30h, 38h
0000 0000h
4.23 Interrupt Line Register
The interrupt line register communicates interrupt line routing information to the host system. This register is not used
bythePCI1451, sincetherearemanyprogrammableinterruptsignalingoptions. Thisregisterisconsideredreserved;
however, host software may read and write to this register. Each PCI1451 function has an interrupt line register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt line
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Register:
Type:
Offset:
Default:
Interrupt line
Read/Write
3Ch
FFh
4–12
4.24 Interrupt Pin Register
The value read from this register is function dependent and depends on bit 29 (INTRTIE) bit in the system control
register (PCI offset 80h, see Section 4.29) and bits 2 and 1 (INTMODE field) in the device control register (PCI offset
92h, see Section 4.39). When the INTRTIE bit is set, this register will read 0x01 (INTA) for both functions. The
PCI1450 defaults to signaling PCI & IRQ interrupts through the IRQSER serial interrupt terminal. Refer to Table 4–5
for a complete description of the register contents.
PCI function 0
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt pin – PCI function 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
PCI function 1
Bit
7
6
5
4
3
2
1
0
Name
Interrupt pin – PCI function 1
Type
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Default
Register:
Type:
Offset:
Default:
Interrupt pin
Read-only
3Dh
The default depends on the interrupt signaling mode.
Table 4–5. Interrupt Pin Register Cross Reference
INTPIN
INTPIN
INTERRUPT SIGNALING MODE
INTRTIE BIT
FUNCTION 0
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
FUNCTION 1
0x02 (INTB)
0x02 (INTB)
0x02 (INTB)
0x02 (INTB)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
Parallel PCI interrupts only
0
0
0
0
1
1
1
1
Parallel IRQ & parallel PCI interrupts
IRQ serialized (IRQSER) & parallel PCI Interrupts
IRQ & PCI serialized (IRQSER) interrupts (default)
Parallel PCI interrupts only
Parallel IRQ & parallel PCI interrupts
IRQ serialized (IRQSER) & parallel PCI interrupts
IRQ & PCI serialized (IRQSER) interrupts (default)
4–13
4.25 Bridge Control Register
The bridge control register provides control over various PCI1451 bridging functions. Bit 5 in this register is global
in nature and is accessed only through function 0.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Bridge control
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Bridge control
Read-only, Read/Write
3Eh (Function 0, 1)
0340h
Table 4–6. Bridge Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
15–11
RSVD
R
Reserved. Bits 15–11 return 0s when read.
Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables
posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst
cycles. Note that bursted write data can be posted, but various write transactions may not. Bit 10 is socket
dependent and is not shared between functions 0 and 1.
10
9
POSTEN
PREFETCH1
PREFETCH0
INTR
R/W
R/W
R/W
R/W
R/W
R/W
Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. Bit 9 is socket
dependent. This bit is encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. Bit 8 is
encoded as:
8
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
PCI interrupt – IREQ routing enable. Bit 7 selects whether PC Card functional interrupts are routed to PCI
interrupts or to the IRQ specified in the ExCA registers.
7
0 = Functional interrupts are routed to PCI interrupts (default).
1 = Functional interrupts are routed by ExCA registers.
CardBus reset. When bit 6 is set, the CRST signal is asserted on the CardBus interface. The CRST signal
may also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted.
6
CRST
1 = CRST is asserted (default).
Master abort mode. Bit 5 controls how the PCI1451 responds to a master abort when the PCI1451 is an
initiator on the CardBus interface. This bit is common between each socket.
0 = Master aborts not reported (default).
5
MABTMODE
1 = Signal target abort on PCI and signal SERR, if enabled.
4
3
RSVD
R
Reserved. Bit 4 returns 0 when read.
VGA enable. Bit 3 affects how the PCI1451 responds to VGA addresses. When this bit is set, accesses
to VGA addresses are forwarded.
VGAEN
R/W
ISA mode enable. Bit 2 affects how the PCI1451 passes I/O cycles within the 64-Kbyte ISA range. This
bit is not common between sockets. When this bit is set, the PCI1451 does not forward the last 768 bytes
of each 1K I/O range to CardBus.
2
1
ISAEN
R/W
R/W
CSERR enable. Bit 1 controls the response of the PCI1451 to CSERR signals on the CardBus bus. This
bit is separate for each socket.
CSERREN
0 = CSERR is not forwarded to PCI SERR.
1 = CSERR is forwarded to PCI SERR.
CardBusparityerrorresponseenable. Bit0controlstheresponseofthePCI1451toCardBusparityerrors.
This bit is separate for each socket.
0
CPERREN
R/W
0 = CardBus parity errors are ignored.
1 = CardBus parity errors are reported using CPERR.
4–14
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Subsystem vendor ID
Read-only (Read/Write if enabled by SUBSYSRW)
Offset:
Default:
40h (Functions 0, 1)
0000h
4.27 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29). If an EEPROM is present, then the subsystem ID and
subsystem vendor ID will be loaded from EEPROM after a reset.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Subsystem ID
Read-only (Read/Write if enabled by SUBSYSRW)
Offset:
Default:
42h (Functions 0, 1)
0000h
4–15
4.28 PC Card 16-Bit I/F Legacy Mode Base Address Register
The PCI1451 supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An
address written to this register is the address for the index register and the address+1 is the data address. Using this
access method, applications requiring index/data ExCA access can be supported. The base address can be mapped
anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. As specified in
the Yenta specification, this register is shared by functions 0 and 1. See Chapter 5, ExCA Compatibility Registers,
for register offsets.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PC Card 16-bit I/F legacy mode base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PC Card 16-bit I/F legacy mode base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
1
Register:
Type:
PC Card 16-bit I/F legacy mode base address
Read-only, Read/Write
Offset:
Default:
44h (Functions 0, 1)
0000 0001h
4–16
4.29 System Control Register
System-level initializations are performed through programming this doubleword register. Bits 31–29, 27, 26, 24, 15,
14, 6–3, 1, and 0 are global in nature and are accessed only through function 0.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
System control
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
7
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
Name
Type
Default
System control
R/W
1
R/W
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R/W
1
R/W
1
R/W
0
R/W
0
R
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
System control
Read-only, Read/Write
80h (Functions 0, 1)
0044 9060h
Table 4–7. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream
signalingandaccomplishanevendistributionofinterruptssignaledonthefourPCIinterruptslots. These
bits are global to both PCI1451 functions.
00 = INTA/INTB signal in INTA/INTB IRQSER slots (default)
01 = INTA/INTB signal in INTB/INTC IRQSER slots
31–30
SER_STEP
R/W
10 = INTA/INTB signal in INTC/INTD IRQSER slots
11 = INTA/INTB signal in INTD/INTA IRQSER slots
Tie internal PCI interrupts. When bit 29 is set, the INTA and INTB signals are tied together internally and
are signaled as INTA. INTA may then be shifted by using bits 31 and 30 (SER_STEP). This bit is global
to both PCI1451 functions.
29
28
INTRTIE
RSVD
R/W
R
0 = INTA and INTB are not tied together internally (default).
1 = INTA and INTB are tied together internally.
Reserved. Bit 28 returns 0 when read.
P2C power switch CLOCK. Bit 27 determines whether the CLOCK terminal (terminal U12) is an input
that requires an external clock source or if this terminal is an output that uses the internal oscillator.
0 = CLOCK terminal (terminal U12) is an input (default) (disabled).
27
P2CCLK
R/W
1 = CLOCK terminal is an output, the PCI1451 generated CLOCK.
A 43kW pulldown resistor should be tied to this terminal.
SMI interrupt routing. Bit 26 is shared between functions 0 and 1, and selects whether IRQ2 or CSC is
signaled when a write occurs to power a PC Card socket.
26
25
SMIROUTE
SMISTATUS
R/W
R/W
0 = PC Card power change interrupts routed to IRQ2 (default).
1 = A CSC interrupt is generated on PC Card power changes.
SMI interrupt status. This socket dependent bit is set when bit 24 (SMIENB) is set and a write occurs
to set the socket power. Writing a 1 to bit 25 clears the status.
0 = SMI interrupt is signaled.
1 = SMI interrupt is not signaled.
SMI interrupt mode enable. When bit 24 is set, the SMI interrupt signaling generates an interrupt when
a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled).
0 = SMI interrupt mode is disabled (default).
24
23
SMIENB
RSVD
R/W
R
1 = SMI interrupt mode is enabled.
Reserved. Bit 23 returns 0 when read.
4–17
Table 4–7. System Control Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
CardBus reserved terminals signaling. When bit 22 is set, the RSVD CardBus terminals are driven low
when a CardBus card is inserted. When bit 22 is low, as default, these signals are placed in a
high-impedance state.
22
CBRSVD
R/W
0 = Place the CardBus RSVD terminals in a high-impedance state
1 = Drive the Cardbus RSVD terminals low (default).
V
protection enable. This bit is socket dependent.
CC
0 = V
21
20
VCCPROT
R/W
R/W
protection is enabled for 16-bit cards (default).
protection is disabled for 16-bit cards.
CC
CC
1 = V
Reduced zoomed video enable. When bit 20 is enabled, terminals A25–A22 of the card interface for
PC Card 16 cards is placed in the high impedance state. This bit is encoded as:
0 = Reduced zoomed video is disabled (default).
REDUCEZV
1 = Reduced zoomed video is enabled.
PC/PCI DMA card enable. When bit 19 is set, the PCI1451 allows 16-bit PC Cards to request PC/PCI
DMA using the DREQ signaling. DREQ is selected through the socket DMA register 0 (PCI offset 94h,
see Section 4.41).
19
CDREQEN
R/W
0 = Ignore DREQ signaling from PC Cards (default).
1 = Signal DMA request on DREQ.
PC/PCI DMA channel assignment. Bits 18–16 are encoded as:
0–3 = 8-bit DMA channels
18–16
15
CDMACHAN
MRBURSTDN
MRBURSTUP
R/W
R/W
R/W
4 = PCI master; not used (default)
5–7 = 16-bit DMA channels
Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to
burst downstream.
0 = Downstream memory read burst is disabled.
1 = Downstream memory read burst is enabled (default).
Memoryreadburstenableupstream. Whenbit14isset, thePCI1451allowsmemoryreadtransactions
to burst upstream.
14
0 = Upstream memory read burst is disabled (default).
1 = Upstream memory read burst is enabled.
Socket activity status. When set, bit 13 indicates access has been performed to or from a PC Card,
and is cleared upon read of this status bit. This bit is socket dependent.
0 = No socket activity (default)
13
12
SOCACTIVE
RSVD
R
R
1 = Socket activity
Reserved. This bit returns 1 when read. This is the clamping voltage bit in functions 0 and 1.
Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch
is in progress and a powering change has been requested. This bit is cleared when the power stream
is complete.
11
10
9
PWRSTREAM
DELAYUP
R
R
R
0 = Power stream is complete, delay has expired.
1 = Power stream is in progress.
Power-updelay in progress status bit. When set, bit 10 indicates that a power-up stream has been sent
tothepowerswitchandproperpowermaynotyetbestable.Thisbitisclearedwhenthepower-updelay
has expired.
0 = Power-up delay has expired.
1 = Power-up stream sent to switch. Power might not be stable.
Power-downdelay in progress status bit. When set, bit 9 indicates that a power-down stream has been
sent to the power switch and proper power may not yet be stable. This bit is cleared when the
power-down delay has expired.
DELAYDOWN
0 = Power-down delay has expired.
1 = Power-down stream sent to switch. Power might not be stable.
Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when the
interrogation completes. This bit is socket dependent.
0 = Interrogation not in progress (default)
8
7
INTERROGATE
RSVD
R
R
1 = Interrogation in progress
Reserved. Bit 7 returns 0 when read.
4–18
Table 4–7. System Control Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
Power savings mode enable. When bit 6 is set, the PCI1451 will consume less power with no
performance loss. This bit is shared between the two PCI1451 functions.
0 = Power savings mode disabled
6
PWRSAVINGS
R/W
1 = Power savings mode enabled (default)
Subsystem ID (see Section 4.27), subsystem vendor ID (see Section 4.26), and the ExCA
identification and revision (see Section 5.1) registers read/write enable. Bit 5 is shared by functions 0
and 1.
0 = Subsystem ID, subsystem vendor ID, and the ExCA identification and revision registers are
read/write.
1 = Subsystem ID, subsystem vendor ID, and the ExCA identification and revision registers are
read-only (default).
5
4
SUBSYSRW
CB_DPAR
R/W
R/W
CardBus data parity SERR signaling enable.
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
PC/PCI DMA enable. Enables PC/PCI DMA when set. When PC/PCI DMA is enabled, PCREQ and
PCGNT should be routed to a multifunction routing terminal. See multifunction routing status register
(PCI offset 8Ch, see Section 4.36) for options.
3
2
CDMA_EN
RSVD
R/W
R
0 = Centralized DMA disabled (default)
1 = Centralized DMA enabled
Reserved. Bit 2 returns 0 when read.
Keep clock. When bit 1 is set, the PCI1451 will always follow CLKRUN protocol to maintain the system
PCLK and the CCLK (CardBus clock). This bit is global to the PCI1451 functions.
0 = Allow system PCLK and CCLK to stop (default)
1 = Never allow system PCLK or CCLK clock to stop
1
0
KEEPCLK
R/W
R/W
Note that the functionality of this bit has changed versus the PCI12XX series of TI CardBus controllers.
In these CardBus controllers, setting this bit would only maintain the PCI clock, not the CCLK. In the
PCI1451, setting this bit maintains both the PCI clock and the CCLK.
PME/RI_OUT select bit. When bit 0 is 1, the PME signal is routed on to the RI_OUT/PME terminal.
When this bit is 0 and bit 7 (RIENB) of the card control register (PCI offset 91h, see Section 4.38) is
1, the RI_OUT signal is routed on to the RI_OUT/PME terminal. If this bit is 0 and bit 7 (RIENB) of the
card control register is 0, then the output on the RI_OUT/PME terminal is placed in a high-impedance
state. This terminal is encoded as:
RIMUX
0 = RI_OUT signal is routed to the RI_OUT/PME terminal if bit 7 of the card control register is 1
(default).
1 = PME signal is routed on to the RI_OUT/PME terminal of the PCI1451 controller.
4–19
4.30 Multimedia Control Register
The multimedia control register provides port mapping for the PCI1451 zoomed video/data ports. See Section 3.4.3,
Zoomed Video Support, for details on the PCI1451 zoomed video support. Access this register only through
function 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Multimedia control
R/W R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Register:
Type:
Multimedia control
Read/Write
Offset:
Default:
84h (Functions 0, 1)
00h
Table 4–8. Multimedia Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
ZV output enable. Bit 7 enables the output for the PCI1451 outsourcing ZV terminals. When this bit is
reset, these terminals are in a high-impedance state.
7
ZVOUTEN
R/W
0 = PCI1451 ZV output terminals disabled (default)
1 = PCI1451 ZV output terminals enabled
ZV port select. Bit 6 controls the multiplexing control over which PC Card ZV port data is driven to the
outsourcing PCI1451 ZV port.
6
5
PORTSEL
ZVAUTO
R/W
R/W
0 = Output card 0 ZV if enabled (default)
1 = Output card 1 ZV if enabled
Zoomed video auto-detect. Bit 5 enables the zoomed video auto-detect feature. This bit is encoded as:
0 = Zoomed video auto detect disabled (default)
1 = Zoomed video auto detect enabled
Auto-detectpriority encoding. Bits 4–2 have meaning only if bit 5 (ZVAUTO) is enabled. If bit 5 is enabled,
then bits 4–2 are encoded as follows:
000 = Slot A, Slot B, External Source
001 = Slot A, External Source, Slot B
010 = Slot B, Slot A, External Source
011 = Slot B, External Source, Slot A
100 = External Source, Slot A, Slot B
101 = External Source, Slot B, Slot A
110 = Reserved
4–2
AUTODETECT
R/W
111 = Reserved
PC Card 1 ZV mode enable. Enables the zoomed video mode for socket 1. When bit 1 set, the PCI1451
inputs ZV data from the PC Card interface, and disables output drivers on ZV terminals.
0 = PC Card 1 ZV disabled (default)
1
0
ZVEN1
ZVEN0
R/W
R/W
1 = PC Card 1 ZV enabled
PC Card 0 ZV mode enable. Enables the zoomed video mode for socket 0. When bit 0 set, the PCI1451
inputs ZV data from the PC Card interface, and disables output drivers on ZV terminals.
0 = PC Card 0 ZV disabled (default)
1 = PC Card 0 ZV enabled
4–20
4.31 General Status Register
Thegeneralstatusregisterprovidesthegeneraldevicestatusinformation. ThestatusoftheserialEEPROMinterface
is provided through this register. Bits 2–0 are global in nature and are accessed only through function 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General status
R
0
R
0
R
0
R
0
R
0
R
X
R/C
0
R
0
Register:
Type:
Offset:
Default:
General status
Read-only, Read/Clear
85h (Functions 0)
00h
Table 4–9. General Status Register Description
FUNCTION
BIT
SIGNAL
TYPE
7–3
RSVD
R
Reserved. Bits 7–3 return 0s when read.
Serial EEPROM detect. When bit 2 is cleared, it indicates that the PCI1450 serial EEPROM circuitry has
detected an EEPROM. A pullup resistor must be implemented on the SDA terminal for this bit to be set.
This status bit is encoded as:
2
EEDETECT
R
0 = EEPROM not detected (default)
1 = EEPROM detected
Serial EEPROM data error status. Bit 1 indicates when a data error occurs on the serial EEPROM
interface. This bit will be set due to a missing acknowledge. This bit is cleared by a writeback of 1.
0 = No error detected. (default)
1
0
DATAERR
EEBUSY
R/C
R
1 = Data error detected.
Serial EEPROM busy status. Bit 0 indicates the status of the PCI1451 serial EEPROM circuitry. This bit
is set during the loading of the subsystem ID value.
0 = Serial EEPROM circuitry is not busy (default).
1 = Serial EEPROM circuitry is busy.
4–21
4.32 General-Purpose Event Status Register
The general-pupose event status register contains status bits that are set when general events occur and may be
programmed to generate general-purpose event signalling through GPE.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose event status
RCU
0
RCU
0
R
0
R
0
RCU
0
RCU
0
RCU
0
RCU
0
Register:
Type:
General-purpose event status
Read/Clear/Update
Offset:
Default:
88h
00h
Table 4–10. General-Purpose Event Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
PWR_STS
RCU
Power change status. Bit 7 is set when software changes the V
or V
power state of either socket.
PP
CC
12V V
for either socket.
request status. Bit 6 is set when software has changed the requested V level to or from 12 V
PP
PP
6
5–4
3
VPP12_STS
RSVD
RCU
R
Reserved. Bits 5 and 4 return 0s when read.
GPI3 status. Bit 3 is set on a change in status of the MFUNC3 terminal input level if configured as a
general-purpose input, GPI3.
GP3_STS
RCU
GPI2 status. Bit 2 is set on a change in status of the MFUNC2 terminal input level if configured as a
general-purpose input, GPI2.
2
1
0
GP2_STS
GP1_STS
GP0_STS
RCU
RCU
RCU
GPI1 status. Bit 1 is set on a change in status of the MFUNC1 terminal input level if configured as a
general-purpose input, GPI1.
GPI0 status. Bit 0 is set on a change in status of the MFUNC0 terminal input level if configured as a
general-purpose input, GPI0.
4.33 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable GPE signals.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose event enable
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General-purpose event enable
Read-only, Read/Write
Offset:
Default:
89h
00h
Table 4–11. General-Purpose Event Enable Register Description
BIT
7
SIGNAL
PWR_EN
VPP12_EN
RSVD
TYPE
R/W
R/W
R
FUNCTION
Power change GPE enable. When bit 7 is set, GPE is signaled on PWR_STS events.
12-Volt V GPE enable. When bit 6 is set, GPE is signaled on VPP12_STS events.
6
PP
5–4
3
Reserved. Bits 5 and 4 return 0s when read.
GP3_EN
GP2_EN
GP1_EN
GP0_EN
R/W
R/W
R/W
R/W
GPI3 GPE enable. When bit 3 is set, GPE is signaled on GP3_STS events.
GPI2 GPE enable. When bit 2 is set, GPE is signaled on GP2_STS events.
GPI1 GPE enable. When bit 1 is set, GPE is signaled on GP1_STS events.
GPI0 GPE enable. When bit 0 is set, GPE is signaled on GP0_STS events.
2
1
0
4–22
4.34 General-Purpose Input Register
The general-purpose input register contains GPI terminal status.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose input
R
0
R
0
R
0
R
0
RU
x
RU
x
RU
x
RU
x
Register:
Type:
Offset:
Default:
General-purpose input
Read/Update
8Ah
00h
Table 4–12. General-Purpose Input Register Description
BIT
7–4
3
SIGNAL
RSVD
TYPE
FUNCTION
R
Reserved. Bits 7–4 return 0s when read.
GPI3_DATA
GPI2_DATA
GPI1_DATA
GPI0_DATA
RU
RU
RU
RU
GPI3 data input. Bit 3 represents the logical value of the data input from GPI3.
GPI2 data input. Bit 2 represents the logical value of the data input from GPI2.
GPI1 data input. Bit 1 represents the logical value of the data input from GPI1.
GPI0 data input. Bit 0 represents the logical value of the data input from GPI0.
2
1
0
4.35 General-Purpose Output Register
The general-purpose output register is used to drive the GPO3–GPO0 outputs.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose output
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General-purpose output
Read-only, Read/Write
Offset:
Default:
8Bh
00h
Table 4–13. General-Purpose Output Register Description
BIT
7–4
3
SIGNAL
RSVD
TYPE
FUNCTION
R
Reserved. Bits 7–4 return 0s when read.
GPO3_DATA
GPO2_DATA
GPO1_DATA
GPO0_DATA
R/W
R/W
R/W
R/W
Bit 3 represents the logical value of the data driven to GPO3.
Bit 2 represents the logical value of the data driven to GPO2.
Bit 1 represents the logical value of the data driven to GPO1.
Bit 0 represents the logical value of the data driven to GPO0.
2
1
0
4–23
4.36 Multifunction Routing Status Register
The multifunction routing status register is used to configure MFUNC7–MFUNC0 terminals. These terminals may be
configured for various functions. This register is intended to be programmed once at power-on initialization. The
default value for this register may also be loaded through a serial ROM.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Multifunction routing status
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Multifunction routing status
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Multifunction routing status
Read/Write
8Ch
0000 0000h
Table 4–14. Multifunction Routing Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
RSVD
R
Reserved. Bit 31 returns 0 when read.
MFUNC7 select. Bits 30–28 control the mapping of MFUNC7 as follows:
000 = IDSEL
001 = RI_OUT
010 = RSVD
011 = PCREQ
100 = D3_STAT
101 = LOCK
110 = RSVD
111 = RSVD
30–28
27
MFUNC7_SEL
RSVD
R/W
R
Reserved. Bit 27 returns 0 when read.
MFUNC6 select. Bits 26–24 control the mapping of MFUNC6 as follows:
000 = RSVD
001 = RSVD
010 = RSVD
011 = RSVD
100 = D3_STAT
101 = RSVD
110 = CAUDPWM
111 = PCGNT
26–24
23
MFUNC6_SEL
RSVD
R/W
R
Reserved. Bit 23 returns 0 when read.
MFUNC5 select. Bits 22–20 control the mapping of MFUNC5 as follows:
000 = RSVD
001 = RSVD
010 = RSVD
011 = RSVD
100 = RSVD
101 = GPE
110 = CAUDPWM
111 = PCREQ
22–20
19
MFUNC5_SEL
RSVD
R/W
R
Reserved. Bit 19 returns 0 when read.
MFUNC4 select. Bits 18–16 control the mapping of MFUNC4 as follows:
000 = RSVD
001 = RSVD
010 = LEDA1
011 = PCREQ
100 = RSVD
101 = GPE
110 = RSVD
111 = ZV_STAT
18–16
15
MFUNC4_SEL
RSVD
R/W
R
Reserved. Bit 15 returns 0 when read.
MFUNC3 select. Bits 14–12 control the mapping of MFUNC3 as follows:
000 = GPI3
100 = RSVD
101 = LOCK
110 = RSVD
111 = C_ZVCLK
14–12
11
MFUNC3_SEL
RSVD
R/W
R
001 = GPO3
010 = LEDA2
011 = PCGNT
Reserved. Bit 11 returns 0 when read.
4–24
Table 4–14. Multifunction Routing Status Register Description (continued)
BIT
10–8
7
SIGNAL
MFUNC2_SEL
RSVD
TYPE
R/W
R
FUNCTION
MFUNC2 select. Bits 10–8 control the mapping of MFUNC2 as follows:
000 = GPI2
001 = GPO2
010 = INTC
011 = PCGNT
100 = D3_STAT
101 = RSVD
110 = RSVD
111 = C_ZVCLK
Reserved. Bit 7 returns 0 when read.
MFUNC1 select. Bits 6–4 control the mapping of MFUNC1 as follows:
000 = GPI1
001 = GPO1
010 = INTB
100 = D3_STAT
101 = LOCK
110 = CAUDPWM
111 = ZV_STAT
6–4
3
MFUNC1_SEL
RSVD
R/W
R
011 = TEST_MUX
Reserved. Bit 3 returns 0 when read.
MFUNC0 select. Bits 2–0 control the mapping of MFUNC0 as follows:
000 = GPI0
001 = GPO0
010 = INTA
011 = PCREQ
100 = RSVD
101 = GPE
110 = RSVD
111 = ZV_STAT
2–0
MFUNC0_SEL
R/W
4–25
4.37 Retry Status Register
The retry status register enables the retry time-out counters and displays the retry expiration status. The flags are
15
set when the PCI1451 retries a PCI or CardBus master request and the master does not return within 2 PCI clock
cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the command
register (see Section 4.4), status register (see Section 4.5), and bridge control register (see Section 4.25) by the PCI
SIG. Access this register only through function 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Retry status
R/W
1
R/W
1
R/C
0
R
0
R/C
0
R
0
R/C
0
R
0
Register:
Type:
Retry status
Read-only, Read/Write, Read/Write to Clear
Offset:
Default:
90h (Functions 0, 1)
C0h
Table 4–15. Retry Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PCI retry time-out counter enable. Bit 7 is encoded as:
0 = PCI retry counter disabled
7
PCIRETRY
R/W
1 = PCI retry counter enabled (default)
CardBus retry time-out counter enable. Bit 6 is encoded as:
0 = CardBus retry counter disabled
6
CBRETRY
R/W
1 = CardBus retry counter enabled (default)
CardBus target B retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
5
4
3
2
1
0
TEXP_CBB
RSVD
R/C
R
1 = Retry has expired.
Reserved. Bit 4 returns 0 when read.
CardBus target A retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
TEXP_CBA
RSVD
R/C
R
1 = Retry has expired.
Reserved. Bit 2 returns 0 when read.
PCI target retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
TEXP_PCI
RSVD
R/C
R
1 = Retry has expired.
Reserved. Bit 0 returns 0 when read.
4–26
4.38 Card Control Register
The card control register is provided for PCI1130 compatibility. The contents provide the PC Card function interrupt
flag (IFG) and an alias for the ZVEN0 and ZVEN1 bits found in the PCI1451 multimedia control register (see
Section 4.30). When this register is accessed by function 0, the ZVEN0 bit will alias with bit 6 (ZVENABLE). When
this register is accessed by function 1, the ZVEN1 bit will alias with bit 6 (ZVENABLE). Setting bit 6 only places the
PC Card socket interface ZV terminals in a high impedance state, but does not enable the PCI1451 to drive ZV data
onto the ZV terminals.
The RI_OUT signal is enabled through this register, and bit 7 (RIENB) is shared between functions 0 and 1.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Card control
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Card control
Read-only, Read/Write
Offset:
Default:
91h
00h
Table 4–16. Card Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Ring indicate enable. When bit 7 is 1, the RI_OUT output is enabled. This bit is global in nature and should
be accessed only through function 0. This bit defaults to 0.
7§
RIENB
R/W
Compatibility ZV mode enable. When bit 6 is 1, the corresponding PC Card socket interface ZV terminals
will enter a high impedance state. This bit defaults to 0.
6
ZVENABLE
R/W
5
RSVD
RSVD
R/W
R
Reserved.
4–3
Reserved. These bits default to 0.
CardBus Audio-to-MFUNC. When bit 2 is set, the CAUDIO CardBus signal must be routed through an
MFUNC terminal. If this bit is set for both functions, then function 0 gets routed.
2
1
AUD2MUX
R/W
0 = CAUDIO set to CAUDPWM on MFUNC terminal (default)
1 = CAUDIO is not routed.
Speaker output enable. When bit 1 is 1, it enables SPKR on the PC Card and routes it to SPKROUT on
the PCI bus. The SPKR signal from socket 0 is XOR’ed with the SPKR signal from socket 1 and sent to
SPKROUT. The SPKROUT terminal only drives data then either function’s SPKROUTEN bit is set. This
bit is encoded as:
SPKROUTEN
R/W
0 = SPKR to SPKROUT not enabled (default)
1 = SPKR to SPKROUT enabled
Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when
a functional interrupt is signaled from a PC Card interface, and is socket dependent (that is, not global).
Write back a 1 to clear this bit.
0
IFG
R/W
0 = No PC Card functional interrupt detected (default)
1 = PC Card functional interrupt detected
§
These bits are global in nature and should be accessed only through function 0.
4–27
4.39 Device Control Register
The device control register is provided for PCI1130 compatibility. It contains bits which are shared between functions
0 and 1. The interrupt mode select and the socket-capable force bits are programmed through this register. Bits 6
and 3–0 are global in nature and should be accessed only through function 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Device control
R/W
0
R/W
1
R/W
1
R
0
R/W
0
R/W
1
R/W
1
R/W
0
Register:
Type:
Offset:
Default:
Device control
Read-only, Read/Write
92h (Functions 0, 1)
66h
Table 4–17. Device Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Socketpowerlockbit. Whenbit7issetto1, softwarewillnotbeabletopowerdownthePCCardsocket
while in D3. This may be necessary to support wake on LAN or RING if the operating system is
programmed to power down a socket when the CardBus controller is placed in the D3 state.
7
SKTPWR_LOCK
R/W
3-V socket capable force bit.
0 = Not 3-V capable
6
3VCAPABLE
R/W
1 = 3-V capable (default)
5
4
3
IO16R2
RSVD
TEST
R/W
R
Diagnostic bit. Bit 5 defaults to 1.
Reserved. Bit 4 returns 0 when read. A write has no effect.
TI test bit. Write only 0 to this bit. This bit can be set to shorten the interrogation counter.
R/W
Interrupt mode. Bits 2–1 select the interrupt signaling mode. The interrupt mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Reserved
2–1
0
INTMODE
RSVD
R/W
R/W
10 = IRQ serialized interrupts & parallel PCI interrupts INTA and INTB
11 = IRQ & PCI serialized interrupts (default)
Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI1451, and it tests
only the terminals that are inputs or I/Os. Any output only terminal on the PCI1451 is excluded from
the NAND tree test.
4–28
4.40 Diagnostic Register
The diagnostic register is provided for internal Texas Instruments test purposes.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Diagnostic
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
Register:
Type:
Diagnostic
Read/Write
Offset:
Default:
93h (Functions 0, 1)
61h
Table 4–18. Diagnostic Register Description
FUNCTION
BIT
7
SIGNAL
TRUE_VAL
RSVD
TYPE
R/W
R/W
R/W
This bit defaults to 0. This bit is encoded as:
0 = Reads true values in vendor ID (see Section 4.2) and device ID (see Section 4.3) registers
(default).
1 = Reads all ones in reads to the PCI vendor ID and PCI device ID registers.
6
Reserved.
CSC interrupt routing control
0 = CSC interrupts routed to PCI if ExCA 803 (see Section 5.4) bit 4 = 1.
1 = CSC Interrupts routed to PCI if ExCA 805 (see Section 5.6) bits 7–4 = 0000b. (Default)
In this case, the setting of ExCA 803 bit 4 is a “don’t care.”
5
CSC
4
3
2
1
DIAG4
DIAG3
DIAG2
DIAG1
R/W
R/W
R/W
R/W
Diagnostic RETRY_DIS. Delayed transaction disable.
Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
10
15
15
Diagnostic DISCARD_TIM_SEL_CB. Set = 2 , Reset = 2
10
Diagnostic DISCARD_TIM_SEL_PCI. Set = 2 , Reset = 2
Asynchronous interrupt generation.
0
ASYNC_CSC
R/W
0 = CSC interrupt not generated asynchronously
1 = CSC interrupt is generated asynchronously (default)
4–29
4.41 Socket DMA Register 0
Socket DMA register 0 provides control over the PC Card DREQ (DMA request) signaling.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket DMA register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket DMA register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
DMA socket register 0
Read-only, Read/Write
94h (Functions 0, 1)
0000 0000h
Table 4–19. Socket DMA Register 0 Description
FUNCTION
BIT
SIGNAL
TYPE
31–2
RSVD
R
Reserved. Bits 31–2 return 0s when read.
DMA request (DREQ) terminal. Bits 1 and 0 indicate which terminal on the 16-bit PC Card interface
acts as the DREQ during DMA transfers. This field is encoded as:
00 = Socket not configured for DMA (default)
01 = DREQ uses SPKR
1–0
DREQPIN
R/W
10 = DREQ uses IOIS16
11 = DREQ uses INPACK
4–30
4.42 Socket DMA Register 1
Socket DMA register 1 provides control over the distributed DMA (DDMA) registers and the PCI portion of DMA
transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI
I/O address space. Note that 32-bit transfers to the 16-bit PC Card interface are not supported; the maximum transfer
possible to the PC Card interface is 16 bits. However, 32 bits of data are prefetched from the PCI bus, thus allowing
back-to-back 16-bit transfers to the PC Card interface.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket DMA register 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket DMA register 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
DMA socket register 1
Read-only, Read/Write
98h (Functions 0, 1)
0000 0000h
Table 4–20. Socket DMA Register 1 Description
FUNCTION
BIT
SIGNAL
TYPE
31–16
RSVD
R
Reserved. Bits 31–16 return 0s when read.
DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit
PCII/Oaddress. Theupper16bitsoftheaddressarehardwiredto0, forcingthiswindowtowithinthelower
64K bytes of I/O address space. The lower 4 bits are hardwired to 0, and are included in the address
decode. Thus, the window is aligned to a natural 16-byte boundary.
15–4
3
DMABASE
EXTMODE
R/W
R
Extended addressing. This feature is not supported by the PCI1451, and always returns a 0.
Transfersize. Bits2and1specifythewidthoftheDMAtransferonthePCCardinterface, andareencoded
as:
00 = Transfers are 8 bits (default).
01 = Transfers are 16 bits.
10 = Reserved
2–1
XFERSIZE
DDMAEN
R/W
R/W
11 = Reserved
DDMA registers decode enable. Enables the decoding of the distributed DMA registers based upon the
value of bits 15–4 (DMABASE field).
0
0 = Disabled (default)
1 = Enabled
4–31
4.43 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns
01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and
the value.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Capability ID
Read-only
A0h
01h
4.44 Next Item Pointer Register
The contents of this register indicate the next item in the linked list of the PCI power management capabilities. Since
the PCI1451 functions only include one capabilities item, this register returns 0s when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Next item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Next item pointer
Read-only
A1h
00h
4–32
4.45 Power Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PC Card function related
to power management. Both PCI1451 CardBus bridge functions support D0, D1, D2, and D3 power states.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
R/W
1
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Power management capabilities
Read-only, Read/Write
A2h (Functions 0, 1)
FE11h
Table 4–21. Power Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME support. This 5-bit field indicates the power states from which the PCI1451 device functions may
assert PME. A 0b (zero) for any bit indicates that the function cannot assert the PME signal while in
that power state. These five bits return 0Fh when read. Each of these bits is described below:
PME_Support
PME_Support
15
R/W
R
Bit 15 – defaults to a 1 indicating the PME signal can be asserted from the D3
state. This bit is
is contingent on the system providing an auxiliary
cold
read/write because wake-up support from D3
cold
terminals. If the system designer chooses not to provide an auxiliary power
power source to the V
source to the V
CC
CC
terminals for D3
cold
wake-up support, then BIOS should write a 0 to this bit.
14–11
Bit 14 – contains the value 1 to indicate that the PME signal can be asserted from the D3
hot
state.
Bit 13 – contains the value 1 to indicate that the PME signal can be asserted from the D2 state.
Bit 12 – contains the value 1 to indicate that the PME signal can be asserted from the D1 state.
Bit 11 – contains the value 1 to indicate that the PME signal can be asserted from the D0 state.
D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device
power state.
10
9
D2_Support
D1_Support
R
R
D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device
power state.
8–6
5
RSVD
DSI
R
R
Reserved. Bits 8–6 return 000b when read.
Device specific initialization. Bit 5 returns 0 when read.
Auxiliary power source. Bit 4 is meaningful only if bit 15 (PME_Support, D3
set, it indicates that support for PME in D3
cold
of a proprietary delivery vehicle. When bit 4 is 0, it indicates that the function supplies its own auxiliary
power source.
) is set. When bit 4 is
requires auxiliary power supplied by the system by way
cold
4
AUX_PWR
R
When bit 3 is 1, it indicates that the function relies on the presence of the PCI clock for PME operation.
When bit 3 is 0, it indicates that no PCI clock is required for the function to generate PME.
3
PMECLK
VERSION
R
R
Version. Bits 2–0 return 001b when read, indicating that there are 4 bytes of general-purpose power
management (PM) registers as described in the PCI Bus Power Management Interface Specification.
2–0
4–33
4.46 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI1451
CardBus function. The contents of this register are not affected by the internally generated reset caused by the
transition from the D3
to D0 state.
hot
All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3 -to-D0 state transition, with
hot
the exception of the PME context bits (if PME is enabled) and the GRST only bits.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status
R/C
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Power management control/status
Read-only, Read/Write, Read/Write to Clear
Offset:
Default:
A4h (Functions 0, 1)
0000h
Table 4–22. Power Management Control/Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME status. Bit 15 is set when the CardBus function would normally assert the PME signal,
independent of the state of bit 8 (PME_EN). Bit 15 is cleared by a write back of 1, and this also
clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect.
15
PMESTAT
R/C
Data scale. This 2-bit field returns 0s when read. The CardBus function does not return any
dynamic data, as indicated by bit 4 (DYN_DATA_PME_EN).
14–13
12–9
DATASCALE
DATASEL
R
R
Data select. This 4-bit field returns 0s when read. The CardBus function does not return any
dynamic data, as indicated by bit 4 (DYN_DATA_PME_EN).
PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, then assertion of PME
is disabled.
8
PME_EN
RSVD
R/W
R
7–5
4
Reserved. Bits 7–5 return 0s when read.
Dynamic data PME enable. Bit 4 returns 0 when read since the CardBus function does not report
dynamic data.
DYN_DATA_PME_EN
RSVD
R
3–2
R
Reserved. Bits 3 and 2 return 0s when read.
Power state. This 2-bit field is used both to determine the current power state of a function and
to set the function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
1–0
PWRSTATE
R/W
11 = D3
hot
4–34
4.47 Power Management Control/Status Register Bridge Support Extensions
This register supports PCI bridge specific functionality. It is required for all PCI-to-PCI bridges.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status register bridge support extensions
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Power management control/status register bridge support extensions
Read-only
Offset:
Default:
A6h (Functions 0, 1)
C0h
Table 4–23. Power Management Control/Status Register Bridge Support Extensions
BIT
SIGNAL
TYPE
FUNCTION
Bus power/clock control enable. This bit returns 1 when read. This bit is encoded as:
0 = Bus power/clock control is disabled.
1 = Bus power/clock control is enabled (default).
A0indicatesthatthebuspower/clockcontrolpoliciesdefinedinthePCIBusPowerManagementInterface
Specification are disabled. When the bus power/clock control enable mechanism is disabled, the bridge’s
power management control/status register power state field (see Section 4.46, bits 1–0) cannot be used
by the system software to control the power or the clock of the bridge’s secondary bus. A 1 indicates that
the bus power/clock control mechanism is enabled.
7
BPCC_EN
R
B2/B3 support for D3 . The state of this bit determines the action that is to occur as a direct result of
hot
programmingthefunctiontoD3 . Thisbitisonlymeaningfulifbit7(BPCC_EN)isa1. Thisbitisencoded
hot
as:
6
B2_B3
RSVD
R
R
0 = When the bridge is programmed to D3 , its secondary bus will have its power removed (B3).
hot
1 = When the bridge function is programmed to D3 , its secondary bus’s PCI clock is stopped (B2).
hot
(Default)
5–0
Reserved. Bits 5–0 return 0s when read.
4–35
4.48 General-Purpose Event Control/Status Register
If the GPE (general-purpose event) function is programmed onto the MFUNC5 terminal by writing 101b to bits 22–20
of the multifunction routing status register (PCI offset 8Ch, see Section 4.36), then this register may be used to
program which events will cause GPE to be asserted and report the status.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
GPE control/status
R
0
R
0
R
0
R
0
R
0
R/C
0
R/C
0
R/C
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General-purpose event control/status
Read-only, Read/Write, Read/Write to Clear
Offset:
Default:
A8h
0001h
Table 4–24. GPE Control/Status Register Description
BIT
15–11
10
SIGNAL
TYPE
R
FUNCTION
Reserved. Bits 15–11 return 0s when read.
RSVD
ZV1_STS
ZV0_STS
R/C
R/C
PC Card socket 1 status. Bit 10 is set on a change in status of the ZVENABLE bit in function 1.
PC Card socket 0 status. Bit 9 is set on a change in status of the ZVENABLE bit in function 0.
9
12-volt V
PP
request status. Bit 8 is set when software has changed the requested V
from 12 volts from either socket.
level to or
PP
8
7–3
2
VPP12_STS
RSVD
R/C
R
Reserved. Bits 7–3 return 0s when read.
PC Card socket 1 zoomed video event enable. When bit 2 is set, GPE is signaled on a change in
status of the ZVENABLE bit in function 1 of the PC Card controller.
ZV1_EN
R/W
PC Card socket 0 zoomed video event enable. When bit 1 is set, GPE is signaled on a change in
status of the ZVENABLE bit in function 0 of the PC Card controller.
1
0
ZV0_EN
R/W
R/W
12 Volt V
request event enable. When bit 0 is set, a GPE is signaled when software has changed
level to or from 12 Volts for either socket.
PP
VPP12_EN
the requested V
PP
4–36
5 ExCA Compatibility Registers (Functions 0 and 1)
The ExCA (exchangeable card architecture) registers implemented in the PCI1451 are register-compatible with the
Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible with the
legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this
scheme by writing the register offset value into the index register (I/O base), and reading or writing the data register
(I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy
mode base address register (see Section 4.28), which is shared by both card sockets. The offsets from this base
address run contiguously from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. Refer to Figure 5–1 for an
ExCA I/O mapping illustration. Table 5–1 identifies each ExCA register and its respective ExCA offset.
The TI PCI1451 also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI
memory space. They are located through the CardBus socket/ExCA base address register (PCI register 10h, see
Section 4.12) at memory offset 800h. Each socket has a separate base address programmable by function. Refer
to Figure 5–2 for an ExCA memory mapping illustration. Note that memory offsets are 800h–844h for both functions
0 and 1. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K
window at memory offset 0h.
The interrupt registers, as defined by the 82365SL Specification, in the ExCA register set control such card functions
as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers
and the host interrupt signaling method selected for the PCI1451 to ensure that all possible PCI1451 interrupts can
potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt
signaling are at memory address ExCA offset 803h and 805h.
Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity.
Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this section. Memory windows have 4K
byte granularity.
5–1
Offset
00h
Host I/O Space
PCI1451 Configuration Registers
PC Card A
ExCA
Registers
Card Bus Socket / ExCA Base Address 10h
Index
Data
3Fh
40h
16–bit Legacy Mode Base Address
44h
PC Card B
ExCA
Registers
7Fh
Note: The 16–bit legacy mode base address
register is shared by function 0 and 1 as
indicated by the shading.
Offset of desired register is placed in the Index register and
the data from that location is returned in the data register.
Figure 5–1. ExCA Register Access Through I/O
Host
Host
Memory Space
Memory Space
PCI1451 Configuration Registers
Offset
Offset
00h
.
.
.
CardBus
Socket A
Registers
CardBus Socket/ExCA Base Address
10h
44h
Offset
00h
20h
.
.
CardBus
Socket B
Registers
800h
ExCA
Registers
Card A
16-bit Legacy-Mode Base Address
20h
.
.
844h
800h
.
ExCA
Registers
Card B
Note: The CardBus Socket/ExCA Base
Address Mode Register is separate for
functions 0 and 1.
844h
Offsets are from the CardBus socket/ExCA base
Address register’s base address
Figure 5–2. ExCA Register Access Through Memory
5–2
Table 5–1. ExCA Registers and Offsets
PCI MEMORY
ADDRESS OFFSET
EXCA OFFSET EXCA OFFSET
REGISTER NAME
(CARD A)
(CARD B)
Identification and revision
800
801
802
803
804
805
806
807
808
809
80A
80B
80C
80D
80E
80F
810
811
812
813
814
815
816
817
818
819
81A
81B
81C
81D
81E
81F
820
821
822
823
824
825
826
827
828
829
82A
00
40
Interface status
01
41
Power control
02
42
Interrupt and general control
03
43
Card status change
04
44
Card status change interrupt configuration
Address window enable
05
45
06
46
I / O window control
07
47
I / O window 0 start-address low-byte
I / O window 0 start-address high-byte
I / O window 0 end-address low-byte
I / O window 0 end-address high-byte
I / O window 1 start-address low-byte
I / O window 1 start-address high-byte
I / O window 1 end-address low-byte
I / O window 1 end-address high-byte
Memory window 0 start-address low-byte
Memory window 0 start-address high-byte
Memory window 0 end-address low-byte
Memory window 0 end-address high-byte
Memory window 0 offset-address low-byte
Memory window 0 offset-address high-byte
Card detect and general control
Reserved
08
48
09
49
0A
0B
0C
0D
0E
0F
10
4A
4B
4C
4D
4E
4F
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
Memory window 1 start-address low-byte
Memory window 1 start-address high-byte
Memory window 1 end-address low-byte
Memory window 1 end-address high-byte
Memory window 1 offset-address low-byte
Memory window 1 offset-address high-byte
Global control
18
58
19
59
1A
1B
1C
1D
1E
1F
20
5A
5B
5C
5D
5E
5F
60
Reserved
Memory window 2 start-address low-byte
Memory window 2 start-address high-byte
Memory window 2 end-address low-byte
Memory window 2 end-address high-byte
Memory window 2 offset-address low-byte
Memory window 2 offset-address high-byte
Reserved
21
61
22
62
23
63
24
64
25
65
26
66
Reserved
27
67
Memory window 3 start-address low-byte
Memory window 3 start-address high-byte
Memory window 3 end-address low-byte
28
68
29
69
2A
6A
5–3
Table 5–1. ExCA Registers and Offsets (Continued)
PCI MEMORY
ADDRESS OFFSET
EXCA OFFSET EXCA OFFSET
REGISTER NAME
(CARD A)
(CARD B)
Memory window 3 end-address high-byte
Memory window 3 offset-address low-byte
Memory window 3 offset-address high-byte
Reserved
82B
82C
82D
82E
82F
830
831
832
833
834
835
836
837
838
839
83A
83B
83C
83D
83E
83F
840
841
842
843
844
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
-
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
-
Reserved
Memory window 4 start-address low-byte
Memory window 4 start-address high-byte
Memory window 4 end-address low-byte
Memory window 4 end-address high-byte
Memory window 4 offset-address low-byte
Memory window 4 offset-address high-byte
I/O window 0 offset-address low-byte
I/O window 0 offset-address high-byte
I/O window 1 offset-address low-byte
I/O window 1 offset-address high-byte
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory window page register 0
Memory window page register 1
Memory window page register 2
Memory window page register 3
Memory window page register 4
-
-
-
-
-
-
-
-
5–4
5.1 ExCA Identification and Revision Register (Index 00h)
This register provides the host software with information on 16-bit PC Card support and 82365SL-DF compatibility.
NOTE: If bit 5 (SUBSYRW) in the system control register (see Section 4.29) is 1, then this
register is read-only.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA identification and revision
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
Register:
Type:
ExCA identification and revision
Read/Write
Offset:
CardBus Socket Address + 800h:
Card A ExCA Offset 00h
Card B ExCA Offset 40h
Default:
84h
Table 5–2. ExCA Identification and Revision Register Description
BIT
7–6
5–4
3–0
SIGNAL
IFTYPE
RSVD
FUNCTION
TYPE
R/W
R/W
R/W
Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
PCI1451. The PCI1451 supports both I/O and memory 16-bit PC Cards.
These bits can be used for 82365SL emulation.
82365SL revision. This field stores the 82365SL revision supported by the PCI1451. Host software may read
this field to determine compatibility to the 82365SL register set. This field defaults to 0100b upon reset.
365REV
5–5
5.2 ExCA Interface Status Register (Index 01h)
This register provides information on current status of the PC Card interface. An x in the default bit values indicates
that the value of the bit after reset depends on the state of the PC Card interface.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA interface status
R
0
R
0
R
x
R
x
R
x
R
x
R
x
R
x
Register:
Type:
ExCA interface status
Read-only
Offset:
CardBus Socket Address + 801h:
Card A ExCA Offset 01h
Card B ExCA Offset 41h
Default:
00XX XXXXb
Table 5–3. ExCA Interface Status Register Description
FUNCTION
BIT
SIGNAL
TYPE
7
RSVD
R
This bit returns 0 when read. A write has no effect.
Cardpower. This bit indicates the current power status of the PC Card socket. This bit reflects how the ExCA
power control register has been programmed (see Section 5.3). The bit is encoded as:
6
5
CARDPWR
READY
R
R
0 = V
1 = V
and V
and V
to the socket is turned off (default).
to the socket is turned on.
CC
CC
PP
PP
This bit indicates the current status of the READY signal at the PC Card interface.
0 = PC Card is not ready for a data transfer.
1 = PC Card is ready for a data transfer.
Card write protect. This bit indicates the current status of the WP signal at the PC Card interface. This signal
reports to the PCI1451 whether or not the memory card is write protected. Further, write protection for an
entirePCI145116-bitmemorywindowisavailablebysettingtheappropriatebitintheExCAmemorywindow
offset-address high byte register (see Section 5.18).
4
CARDWP
R
0 = WP signal is 0. PC Card is R/W.
1 = WP signal is 1. PC Card is read-only.
Card detect 2. This bit indicates the status of the CD2 signal at the PC Card interface. Software may use
this and CDETECT1 to determine if a PC Card is fully seated in the socket.
3
2
CDETECT2
CDETECT1
R
R
0 = CD2 signal is 1. No PC Card inserted.
1 = CD2 signal is 0. PC Card at least partially inserted.
Card detect 1. This bit indicates the status of the CD1 signal at the PC Card interface. Software may use
this and CDETECT2 to determine if a PC Card is fully seated in the socket.
0 = CD1 signal is 1. No PC Card inserted.
1 = CD1 signal is 0. PC Card at least partially inserted.
Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery
voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 0 reflects the BVD1 status, and
bit 1 reflects BVD2.
00 = Battery is dead.
01 = Battery is dead.
10 = Battery is low; warning.
11 = Battery is good.
1–0
BVDSTAT
R
When a 16-bit I/O card is inserted, this field indicates the status of the SPKR (bit 1) signal and the STSCHG
(bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these
card outputs.
5–6
5.3 ExCA Power Control Register (Index 02h)
This register provides PC Card power control. Bit 7 of this register controls the 16-bit output enables on the socket
interface, and can be used for power management in 16-bit PC Card applications.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA power control
R/W
0
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
Register:
Type:
ExCA power control
Read-only, Read/Write
Offset:
CardBus Socket Address + 802h:
Card A ExCA Offset 02h
Card B ExCA Offset 42h
Default:
00h
Table 5–4. ExCA Power Control Register Description
BIT
7
SIGNAL
COE
TYPE
R/W
R
FUNCTION
Card output enable. This bit controls the state of all of the 16-bit outputs on the PCI1451. This bit is encoded
as:
0 = 16-bit PC Card outputs are disabled (default).
1 = 16-bit PC Card outputs are enabled.
6–5
RSVD
These bits return 0s when read. Writes have no effect.
V
CC
. These bits are used to request changes to card V . This field is encoded as:
CC
00 = 0 V (default)
01 = 0 V Reserved
10 = 5 V
4–3
2
EXCAVCC
RSVD
R/W
R
11 = 3 V
This bit returns 0 when read. A write has no effect.
V
. These bits are used to request changes to card V . The PCI1451 ignores this field unless V
to the
PP PP CC
socket is enabled (i.e., 5 Vdc or 3.3 Vdc). This field is encoded as:
00 = 0 V (default)
1–0
EXCAVPP
R/W
01 = V
CC
10 = 12 V
11 = 0 V Reserved
5–7
5.4 ExCA Interrupt and General Control Register (Index 03h)
This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA interrupt and general control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA interrupt and general control
Read/Write
Offset:
CardBus Socket Address + 803h:
Card A ExCA Offset 03h
Card B ExCA Offset 43h
Default:
00h
Table 5–5. ExCA Interrupt and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Card ring indicate enable. Enables the ring indicate function of the BVD1/RI pins. This bit is encoded as:
7
RINGEN
R/W
0 = Ring indicate disabled (default)
1 = Ring indicate enabled
Cardreset. Thisbitcontrolsthe16-bitPCCardRESETsignal, andallowshostsoftwaretoforceacardreset.
This bit affects 16-bit cards only. This bit is encoded as:
6
5
RESET
R/W
R/W
0 = RESET signal asserted (default)
1 = RESET signal deasserted.
Card type. This bit indicates the PC Card type. This bit is encoded as:
CARDTYPE
0 = Memory PC Card is installed (default)
1 = I/O PC Card is installed
PCI interrupt – CSC routing enable bit. This bit has meaning only if the CSC interrupt routing control bit (PCI
offset 93h, bit 5) is 0b. In this case, when this bit is set (high), the card status–change interrupts are routed
to PCI interrupts. When low, the card status–change interrupts are routed, using bits 7–4 in the ExCA card
status change interrupt configuration register (see Section 5.6). This bit is encoded as:
4
CSCROUTE
R/W
0 = CSC interrupts routed by ExCA registers (default)
1 = CSC interrupts routed to PCI interrupts
If the CSC interrupt routing control bit (PCI offset 93h, bit 5) is set to 1b, this bit has no meaning which is
the default case.
Card interrupt select for I/O PC Card functional interrupts. These bits select the interrupt routing for I/O PC
Card functional interrupts. This field is encoded as:
0000 = No ISA interrupt routing (default). CSC interrupts routed to PCI Interrupts.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
3–0
INTSELECT
R/W
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
5–8
5.5 ExCA Card Status-Change Register (Index 04h)
This register reflects the status of PC Card CSC interrupt sources. The ExCA card status change interrupt
configuration register (see Section 5.6) enables these interrupt sources to generate an interrupt to the host. When
the interrupt source is disabled, the corresponding bit in this register always reads as 0. When an interrupt source
is enabled and that particular event occurs, the corresponding bit in this register is set to indicate the interrupt source.
After generating the interrupt to the host, the interrupt service routine must read this register to determine the source
of the interrupt. The interrupt service routine is responsible for resetting the bits in this register, as well. Resetting a
bit is accomplished by one of two methods: a read of this register, or an explicit write back of 1 to the status bit. The
choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the ExCA global control register
(see Section 5.22).
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card status-change
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
ExCA card status-change
Read-only
Offset:
CardBus Socket Address + 804h:
Card A ExCA Offset 04h
Card B ExCA Offset 44h
Default:
00h
Table 5–6. ExCA Card Status-Change Register Description
BIT
SIGNAL
TYPE
FUNCTION
7–4
RSVD
R
These bits return 0s when read. Writes have no effect.
Card detect change. This bit indicates whether a change on the CD1 or CD2 signals occurred at the
PC Card interface. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:
3
2
CDCHANGE
R
R
0 = No change detected on either CD1 or CD2
1 = A change was detected on either CD1 or CD2
Ready change. When a 16-bit memory is installed in the socket, this bit includes whether the source
of a PCI1451 interrupt was due to a change on the READY signal at the PC Card interface indicating
that PC Card is now ready to accept new data. A read of this bit or writing a 1 to this bit clears it. This
bit is encoded as:
READYCHANGE
0 = No low-to-high transition detected on READY (default)
1 = Detected a low-to-high transition on READY
When a 16-bit I/O card is installed, this bit is always 0.
Batterywarningchange. Whena16-bitmemorycardisinstalledinthesocket, thisbitindicateswhether
thesource of a PCI1451 interrupt was due to a battery low warning condition. A read of this bit or writing
a 1 to this bit clears it. This bit is encoded as:
1
0
BATWARN
BATDEAD
R
R
0 = No battery warning condition (default)
1 = Detected a battery warning condition
When a 16-bit I/O card is installed, this bit is always 0.
Battery dead or status change. When a 16-bit memory card is installed in the socket, this bit indicates
whether the source of a PCI1451 interrupt was due to a battery dead condition. A read of this bit or
writing a 1 to this bit clears it. This bit is encoded as:
0 = STSCHG deasserted (default)
1 = STSCHG asserted
Ring indicate. When the PCI1451 is configured for ring indicate operation this bit indicates the status
of the RI pin.
5–9
5.6 ExCA Card Status-Change Interrupt Configuration Register (Index 05h)
This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card status-change interrupt configuration
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA card status-change interrupt configuration
Read/Write
Offset:
CardBus Socket Address + 805h:
Card A ExCA Offset 05h
Card B ExCA Offset 45h
Default:
00h
Table 5–7. ExCA Card Status-Change Interrupt Register Description
BIT
SIGNAL
TYPE
FUNCTION
Interrupt select for card status change. These bits select the interrupt routing for card status change
interrupts. This field is encoded as:
0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) (see
Section 4.40) is set to 1b. In this case bit 4 of ExCA 803 is a don’t care. This is the default
setting.
0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI offset 93h) (see Section 4.40) is
set to 0b. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h
to 1b.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
7–4
CSCSELECT
R/W
Card detect enable. Enables interrupts on CD1 or CD2 changes. This bit is encoded as:
3
2
CDEN
R/W
R/W
0 = Disables interrupts on CD1 or CD2 line changes (default)
1 = Enables interrupts on CD1 or CD2 line changes
Readyenable. Thisbitenables/disablesalow-to-hightransitiononthePCCardREADYsignaltogenerate
a host interrupt. This interrupt source is considered a card status change. This bit is encoded as:
READYEN
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
Battery warning enable. This bit enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
1
0
BATWARNEN
BATDEADEN
R/W
R/W
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
Batterydead enable. This bit enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
5–10
5.7 ExCA Address Window Enable Register (Index 06h)
This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card
are disabled. The PCI1451 will not acknowledge PCI memory or I/O cycles to the card if the corresponding enable
bit in this register is 0, regardless of the programming of the ExCA memory and I/O window start/end/offset address
registers (see Sections 5.9 through 5.20).
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA address window enable
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA address window enable
Read-only, Read/Write
Offset:
CardBus Socket Address + 806h:
Card A ExCA Offset 06h
Card B ExCA Offset 46h
Default:
00h
Table 5–8. ExCA Address Window Enable Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 enable. This bit enables/disables I/O window 1 for the card. This bit is encoded as:
7
IOWIN1EN
R/W
0 = I/O window 1 disabled (default)
1 = I/O window 1 enabled
I/O window 0 enable. This bit enables/disables I/O window 0 for the card. This bit is encoded as:
6
5
IOWIN0EN
RSVD
R/W
R
0 = I/O window 0 disabled (default)
1 = I/O window 0 enabled
This bit returns 0 when read. A write has no effect.
Memory window 4 enable. This bit enables/disables memory window 4 for the card. This bit is encoded
as:
4
3
2
1
0
MEMWIN4EN
MEMWIN3EN
MEMWIN2EN
MEMWIN1EN
MEMWIN0EN
R/W
R/W
R/W
R/W
R/W
0 = memory window 4 disabled (default)
1 = memory window 4 enabled
Memory window 3 enable. This bit enables/disables memory window 3 for the card. This bit is encoded
as:
0 = memory window 3 disabled (default)
1 = memory window 3 enabled
Memory window 2 enable. This bit enables/disables memory window 2 for the card. This bit is encoded
as:
0 = memory window 2 disabled (default)
1 = memory window 2 enabled
Memorywindow1enable. Thisbitenables/disablesmemorywindow1forthePCCard. Thisbitisencoded
as:
0 = memory window 1 disabled (default)
1 = memory window 1 enabled
Memorywindow0enable. Thisbitenables/disablesmemorywindow0forthePCCard. Thisbitisencoded
as:
0 = memory window 0 disabled (default)
1 = memory window 0 enabled
5–11
5.8 ExCA I/O Window Control Register (Index 07h)
This register contains parameters related to I/O window sizing and cycle timing.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA I/O window control
Read/Write
Offset:
CardBus Socket Address + 807h:
00h
Card A ExCA Offset 07h
Card B ExCA Offset 47h
Default:
Table 5–9. ExCA I/O Window Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 wait-state. This bit controls the I/O window 1 wait-state for 16-bit I/O accesses. This bit has
no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.
This bit is encoded as:
7
WAITSTATE1
R/W
R/W
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles extended by one equivalent ISA wait state
I/O window 1 zero wait-state. This bit controls the I/O window 1 wait-state for 8-bit I/O accesses.
NOTE: This bit has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used
by the 82365SL-DF.
6
ZEROWS1
0 = 8-bit cycles have standard length (default)
1 = 8-bit cycles reduced to equivalent of three ISA cycles
I/O window 1 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used
the IOIS16 signal from the PC Card to determine the data width of the I/O data transfer.
5
4
IOSIS16W1
DATASIZE1
R/W
R/W
0 = Window data width determined by DATASIZE1, bit 4 (default)
1 = Window data width determined by IOIS16
I/O window 1 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window
1 IOIS16 source bit (bit 5) is set. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
I/O window 0 wait-state. This bit controls the I/O window 0 wait-state for 16-bit I/O accesses. This bit has
no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.
This bit is encoded as:
3
2
WAITSTATE0
ZEROWS0
R/W
R/W
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles extended by one equivalent ISA wait state
I/O window 0 zero wait-state. This bit controls the I/O window 0 wait-state for 8-bit I/O accesses.
NOTE: This bit has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used
by the 82365SL-DF.
0 = 8-bit cycles have standard length (default)
1 = 8-bit cycles reduced to equivalent of three ISA cycles
I/O window 0 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used
the IOIS16 signal from the PC Card to determine the data width of the I/O data transfer.
1
0
IOIS16W0
R/W
R/W
0 = Window data width determined by DATASIZE0, bit 0 (default)
1 = Window data width determined by IOIS16
I/O window 0 data size. This bit controls the I/O window 0 data size. This bit is ignored if the I/O window
0 IOIS16 Source bit (bit 1) is set. This bit is encoded as:
DATASIZE0
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
5–12
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers (Index 08h, 0Ch)
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 start-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 start-address low-byte
CardBus Socket Address + 808h:
Card A ExCA Offset 08h
Card B ExCA Offset 48h
Register:
Offset:
ExCA I/O window 1 start-address low-byte
CardBus Socket Address + 80Ch:
Card A ExCA Offset 0Ch
Card B ExCA Offset 4Ch
Type:
Read/Write
00h
Default:
Size:
One byte
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers (Index 09h, ODh)
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 start-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 start-address high-byte
CardBus Socket Address + 809h:
Card A ExCA Offset 09h
Card B ExCA Offset 49h
Register:
Offset:
ExCA I/O window 1 start-address high-byte
CardBus Socket Address + 80Dh:
Card A ExCA Offset 0Dh
Card B ExCA Offset 4Dh
Type:
Read/Write
00h
Default:
Size:
One byte
5–13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers (Index 0Ah, 0Eh)
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 end-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 end-address low-byte
CardBus Socket Address + 80Ah:
Card A ExCA Offset 0Ah
Card B ExCA Offset 4Ah
Register:
Offset:
ExCA I/O window 1 end-address low-byte
CardBus Socket Address + 80Eh:
Card A ExCA Offset 0Eh
Card B ExCA Offset 4Eh
Type:
Read/Write
00h
Default:
Size:
One byte
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers (Index 0Bh, 0Fh)
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits
of these registers correspond to the upper eight bits of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 end-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 end-address high-byte
CardBus Socket Address + 80Bh:
Card A ExCA Offset 0Bh
Card B ExCA Offset 4Bh
Register:
Offset:
ExCA I/O window 1 end-address high-byte
CardBus Socket Address + 80Fh:
Card A ExCA Offset 0Fh
Card B ExCA Offset 4Fh
Type:
Read/Write
00h
Default:
Size:
One byte
5–14
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers (Index
10h/18h/20h/28h/30h)
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 start-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 start-address low-byte
CardBus Socket Address + 810h:
Card A ExCA Offset 10h
Card B ExCA Offset 50h
Register:
Offset:
ExCA memory window 1 start-address low-byte
CardBus Socket Address + 818h: Card A ExCA Offset 18h
Card B ExCA Offset 58h
ExCA memory window 2 start-address low-byte
CardBus Socket Address + 820h: Card A ExCA Offset 20h
Card B ExCA Offset 60h
ExCA memory window 3 start-address low-byte
CardBus Socket Address + 828h: Card A ExCA Offset 28h
Card B ExCA Offset 68h
ExCA memory window 4 start-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 830h:
Card A ExCA Offset 30h
Card B ExCA Offset 70h
Type:
Read/Write
00h
Default:
Size:
One byte
5–15
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers (Index
11h/19h/21h/29h/31h)
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory
window data width and wait states are set in this register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 start-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 start-address high-byte
CardBus Socket Address + 811h:
Card A ExCA Offset 11h
Card B ExCA Offset 51h
Register:
Offset:
ExCA memory window 1 start-address high-byte
CardBus Socket Address + 819h: Card A ExCA Offset 19h
Card B ExCA Offset 59h
ExCA memory window 2 start-address high-byte
CardBus Socket Address + 821h: Card A ExCA Offset 21h
Card B ExCA Offset 61h
ExCA memory window 3 start-address high-byte
CardBus Socket Address + 829h: Card A ExCA Offset 29h
Card B ExCA Offset 69h
ExCA memory window 4 start-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 831h:
Card A ExCA Offset 31h
Card B ExCA Offset 71h
Type:
Read/Write
00h
Default:
Size:
One byte
Table 5–10. ExCA Memory Windows 0–4 Start-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
This bit controls the memory window data width. This bit is encoded as:
7
DATASIZE
R/W
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
Zero wait-state. This bit controls the memory window wait state for 8- and 16-bit accesses. This wait state
timing emulates the ISA wait-state used by the 82365SL-DF. This bit is encoded as:
6
ZEROWAIT
R/W
0 = 8- and 16-bit cycles have standard length (default)
1 = 8-bit cycles reduced to equivalent of three ISA cycles
16-bit cycles reduce to the equivalent of two ISA cycles.
5–4
3–0
SCRATCH
STAHN
R/W
R/W
Scratch pad bits. These bits have no effect on memory window operation.
Startaddresshigh-nibble. ThesebitsrepresenttheupperaddressbitsA23–A20ofthememorywindowstart
address.
5–16
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers (Index
12h/1Ah/22h/2Ah/32h)
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 end-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 end-address low-byte
CardBus Socket Address + 812h:
Card A ExCA Offset 12h
Card B ExCA Offset 52h
Register:
Offset:
ExCA memory window 1 end-address low-byte
CardBus Socket Address + 81Ah: Card A ExCA Offset 1Ah
Card B ExCA Offset 5Ah
ExCA memory window 2 end-address low-byte
CardBus Socket Address + 822h: Card A ExCA Offset 22h
Card B ExCA Offset 62h
ExCA memory window 3 end-address low-byte
CardBus Socket Address + 82Ah: Card A ExCA Offset 2Ah
Card B ExCA Offset 6Ah
ExCA memory window 4 end-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 832h:
Card A ExCA Offset 32h
Card B ExCA Offset 72h
Type:
Read/Write
00h
Default:
Size:
One byte
5–17
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers (Index
13h/1Bh/23h/2Bh/33h)
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory
window wait states are set in this register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 end-address high-byte
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 end-address high-byte
CardBus Socket Address + 813h:
Card A ExCA Offset 13h
Card B ExCA Offset 53h
Register:
Offset:
ExCA memory window 1 end-address high-byte
CardBus Socket Address + 81Bh: Card A ExCA Offset 1Bh
Card B ExCA Offset 5Bh
ExCA memory window 2 end-address high-byte
CardBus Socket Address + 823h: Card A ExCA Offset 23h
Card B ExCA Offset 63h
ExCA memory window 3 end-address high-byte
CardBus Socket Address + 82Bh: Card A ExCA Offset 2Bh
Card B ExCA Offset 6Bh
ExCA Memory window 4 end-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 833h:
Card A ExCA Offset 33h
Card B ExCA Offset 73h
Type:
Read/Write, Read-only
Default:
Size:
00h
One byte
Table 5–11. ExCA Memory Windows 0–4 End-Address High-Byte Registers Description
BIT
7–6
5–4
3–0
SIGNAL
MEMWS
RSVD
TYPE
R/W
R
FUNCTION
Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory
accesses. The number of wait states added is equal to the binary value of these two bits.
These bits return 0s when read. Writes have no effect.
End address high-nibble. These bits represent the upper address bits A23–A20 of the memory window end
address.
ENDHN
R/W
5–18
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers (Index
14h/1Ch/24h/2Ch/34h)
These registers contain the low-byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the offset address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 offset-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 offset-address low-byte
CardBus Socket Address + 814h:
Card A ExCA Offset 14h
Card B ExCA Offset 54h
Register:
Offset:
ExCA memory window 1 offset-address low-byte
CardBus Socket Address + 81Ch: Card A ExCA Offset 1Ch
Card B ExCA Offset 5Ch
ExCA memory window 2 offset-address low-byte
CardBus Socket Address + 824h: Card A ExCA Offset 24h
Card B ExCA Offset 64h
ExCA memory window 3 offset-address low-byte
CardBus Socket Address + 82Ch: Card A ExCA Offset 2Ch
Card B ExCA Offset 6Ch
ExCA memory window 4 offset-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 834h:
Card A ExCA Offset 34h
Card B ExCA Offset 74h
Type:
Read/Write
00h
Default:
Size:
One byte
5–19
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers (Index
15h/1Dh/25h/2Dh/35h)
These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The lower 6 bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write
protection and common/attribute memory configurations are set in this register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 offset-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 offset-address high-byte
CardBus Socket Address + 815h:
Card A ExCA Offset 15h
Card B ExCA Offset 55h
Register:
Offset:
ExCA memory window 1 offset-address high-byte
CardBus Socket Address + 81Dh: Card A ExCA Offset 1Dh
Card B ExCA Offset 5Dh
ExCA memory window 2 offset-address high-byte
CardBus Socket Address + 825h: Card A ExCA Offset 25h
Card B ExCA Offset 65h
ExCA memory window 3 offset-address high-byte
CardBus Socket Address + 82Dh: Card A ExCA Offset 2Dh
Card B ExCA Offset 6Dh
ExCA memory window 4 offset-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 835h:
Card A ExCA Offset 35h
Card B ExCA Offset 75h
Type:
Read/Write
00h
Default:
Size:
One byte
Table 5–12. ExCA Memory Windows 0–4 Offset-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Write protect. This bit specifies whether write operations to this memory window are enabled.
This bit is encoded as:
7
WINWP
R/W
0 = Write operations are allowed (default)
1 = Write operations are not allowed
This bit specifies whether this memory window is mapped to card attribute or common memory.
This bit is encoded as:
6
REG
R/W
R/W
0 = Memory window is mapped to common memory (default)
1 = Memory window is mapped to attribute memory
Offset-address high byte. These bits represent the upper address bits A25–A20 of the memory-window offset
address.
5–0
OFFHB
5–20
5.19 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers (Index 36h, 38h)
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 offset-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
Register:
Offset:
ExCA I/O window 0 offset-address low-byte
CardBus Socket Address + 836h:
Card A ExCA Offset 36h
Card B ExCA Offset 76h
Register:
Offset:
ExCA I/O window 1 offset-address low-byte
CardBus Socket Address + 838h:
Card A ExCA Offset 38h
Card B ExCA Offset 78h
Type:
Read/Write
00h
Default:
Size:
One byte
5.20 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers (Index 37h, 39h)
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the offset address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 offset-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 offset-address high-byte
CardBus Socket Address + 837h:
Card A ExCA Offset 37h
Card B ExCA Offset 77h
Register:
Offset:
ExCA I/O window 1 offset-address high-byte
CardBus Socket Address + 839h:
Card A ExCA Offset 39h
Card B ExCA Offset 79h
Type:
Read/Write
00h
Default:
Size:
One byte
5–21
5.21 ExCA Card Detect and General Control Register (Index 16h)
This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the
VS1 and VS2 signals at the PC Card interface. Table 5–13 describes each bit in the ExCA card detect and general
control register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card detect and general control
R
X
R
X
W
0
R/W
0
R
0
R
0
R/W
0
R
0
Register:
Type:
ExCA card detect and general control
Read-only, Write-only, Read/Write
CardBus Socket Address + 816h:
Offset:
Card A ExCA Offset 16h
Card B ExCA Offset 56h
Default:
XX00 0000b
Table 5–13. ExCA Card Detect and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
VS2. This bit reports the current state of the VS2 signal at the PC Card interface, and, therefore, does not
have a default value.
7
VS2STAT
R
0 = VS2 is low
1 = VS2 is high
VS1. This bit reports the current state of the VS1 signal at the PC Card interface, and, therefore, does not
have a default value.
6
5
VS1STAT
SWCSC
R
0 = VS1 is low
1 = VS1 is high
Software card detect interrupt. If the card detect enable bit in the ExCA card status-change interrupt
configuration register (see Section 5.6) is set, then writing a 1 to this bit causes a card detect card status
change interrupt for the associated card socket.
W
If the card detect enable bit is cleared to 0 in the ExCA card status-change interrupt configuration register
(seeSection5.6), thenwritinga1tothesoftwarecarddetectinterruptbithasnoeffect.Thisbitiswrite-only.
A read operation of this bit always returns 0.
Card detect resume enable. If this bit is set to 1 and once a card detect change has been detected on the
CD1 and CD2 inputs, then the RI_OUT output will go from high to low. The RI_OUT remains low until the
card status change bit in the ExCA card status change register (see Section 5.5) is cleared. If this bit is
a 0, then the card detect resume functionality is disabled.
4
CDRESUME
R/W
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
3–2
1
RSVD
REGCONFIG
RSVD
R
R/W
R
These bits return 0s when read. Writes have no effect.
Register configuration upon card removal. This bit controls how the ExCA registers for the socket react
to a card removal event. This bit is encoded as:
0 = No change to ExCA registers upon card removal (default)
1 = Reset ExCA registers upon card removal
0
This bit returns 0 when read. A write has no effect.
5–22
5.22 ExCA Global Control Register (Index 1Eh)
This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in
this register are retained for 82365SL compatibility.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA global control
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA global control
Read-only, Read/Write
Offset:
CardBus Socket Address + 81Eh:
Card A ExCA Offset 1Eh
Card B ExCA Offset 5Eh
Default:
00h
Table 5–14. ExCA Global Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
7–5
RSVD
R
These bits return 0s when read. Writes have no effect.
Level/edge interrupt mode select – card B. This bit selects the signaling mode for the PCI1451 host interrupt
for Card B interrupts. This bit is encoded as:
4
3
2
1
INTMODEB
INTMODEA
IFCMODE
CSCMODE
R/W
R/W
R/W
R/W
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
Level/edge interrupt mode select – card A. This bit selects the signaling mode for the PCI1451 host interrupt
for card A interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register (see Section 5.5). This bit is encoded as:
0 = Interrupt flags cleared by read of CSC register (default)
1 = Interrupt flags cleared by explicit write back of 1
Card status change level/edge mode select. This bit selects the signaling mode for the PCI1451 host
interrupt for card status changes. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
PWRDWN mode select. When the bit is set to 1, the PCI1451 is in power-down mode. In power-down mode
the PCI1451 card outputs are placed in a high-impedance state until an active cycle is executed on the card
interface. Following an active cycle the outputs are again placed in a high-impedance state. The PCI1451
still receives DMA requests, functional interrupts and/or card status change interrupts; however, an actual
card access is required to wake up the interface. This bit is encoded as:
0
PWRDWN
R/W
0 = Power-down mode disabled (default)
1 = Power-down mode enabled
5–23
5.23 ExCA Memory Windows 0–4 Page Registers (Index 40h, 41h, 42h, 43h, 44h)
The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding
addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By
programming this register to a nonzero value, host software may locate 16-bit memory windows in any one of 256
16M-byte regions in the 4-Gigabyte PCI address space. These registers are only accessible when the ExCA registers
are memory-mapped, that is, these registers may not be accessed using the index/data I/O scheme.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 page
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA memory windows 0–4 page
Read/Write
Offset:
Default:
CardBus Socket Address + 840h, 841h, 842h, 843h, 844h
00h
5–24
6 CardBus Socket Registers (Functions 0 and 1)
The PCMCIA CardBus Specification requires a CardBus socket controller to provide five 32-bit registers which report
and control the socket-specific functions. The PCI1451 provides the CardBus socket/ExCA base address register
(PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each socket has a separate
base address register for accessing the CardBus socket registers, see Figure 6–1 below. Table 6–1 illustrates the
location of the socket registers in relation to the CardBus socket/ExCA base address.
Table 6–1. CardBus Socket Registers
REGISTER NAME
Socket event
OFFSET
00h
Socket mask
04h
Socket present state
Socket force event
Socket control
08h
0Ch
10h
Reserved
14h
Reserved
18h
Reserved
1Ch
20h
Socket power management
Host
Host
Memory Space
Memory Space
PCI1451 Configuration Registers
Offset
00h
.
.
CardBus
Socket A
Registers
.
CardBus Socket/ExCA Base Address
10h
44h
Offset
00h
20h
.
.
CardBus
Socket B
Registers
800h
ExCA
Registers
Card A
16-bit Legacy-Mode Base Address
20h
.
.
844h
800h
.
ExCA
Registers
Card B
Note: The CardBus Socket/ExCA Base
Address Mode Register is separate for
functions 0 and 1.
844h
Figure 6–1. Accessing CardBus Socket Registers Through PCI Memory
6–1
6.1 Socket Event Register
This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only
that one has occurred. Software must read the socket present state register (see Section 6.3) for current status. Each
bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software through
writing a 1 to the corresponding bit in the socket force event register (see Section 6.4). All bits in this register are
cleared by PCI reset. They may be immediately set again, if, when coming out of PC Card reset, the bridge finds the
status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software needs to clear this register before
enabling interrupts. If it is not cleared and interrupts are enabled, then an interrupt is generated based on any bit set
and not masked.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/WC R/WC R/WC R/WC
0
0
0
0
Register:
Type:
Socket event
Read-only, Read/Write to Clear
CardBus Socket Address + 00h
0000 0000h
Offset:
Default:
Table 6–2. Socket Event Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–4
RSVD
R
These bits return 0s when read.
Power cycle. This bit is set when the PCI1451 detects that the PWRCYCLE bit in the socket present state
register (see Section 6.3) has changed. This bit is cleared by writing a 1.
3
2
1
PWREVENT
CD2EVENT
CD1EVENT
R/WC
R/WC
R/WC
CCD2. This bit is set when the PCI1451 detects that the CDETECT2 field in the socket present state
register (see Section 6.3) has changed. This bit is cleared by writing a 1.
CCD1. This bit is set when the PCI1451 detects that the CDETECT1 field in the socket present state
register (see Section 6.3) has changed. This bit is cleared by writing a 1.
This bit is set when the CARDSTS field in the socket present state register (see Section 6.3) has changed
R/WC state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG signal. For 16-bit PC Cards,
this bit is set on both transitions of the CSTSCHG signal. This bit is reset by writing a 1.
CSTSEVENT.
CSTSCHG
0
6–2
6.2 Socket Mask Register
This register allows software to control the CardBus card events which generate a status change interrupt. Table 6–3
below describes each bit in this register. The state of these mask bits does not prevent the corresponding bits from
reacting in the socket event register (see Section 6.1).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Socket mask
Read-only, Read/Write
Offset:
Default:
CardBus Socket Address + 04h
0000 0000h
Table 6–3. Socket Mask Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–4
RSVD
R
These bits return 0s when read.
Power cycle. This bit masks the PWRCYCLE bit in the socket present state register (see Section 6.3) from
causing a status change interrupt.
3
2–1
0
PWRMASK
CDMASK
R/W
R/W
R/W
0 = PWRCYCLE event will not cause a CSC interrupt (default)
1 = PWRCYCLE event will cause a CSC interrupt
Carddetect mask. These bits mask the CDETECT1 and CDETECT2 bits in the socket present state register
(see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal will not cause CSC interrupt (default)
01 = Reserved (undefined)
10 = Reserved (undefined)
11 = Insertion/removal will cause CSC interrupt
CSTSCHG mask. This bit masks the CARDSTS field in the socket present state register (see Section 6.3)
from causing a CSC interrupt.
CSTSMASK
0 = CARDSTS event will not cause CSC interrupt (default)
1 = CARDSTS event will cause CSC interrupt
6–3
6.3 Socket Present State Register
This register reports information about the socket interface. Writes to the socket force event register (see Section 6.4)
are reflected here as well as general socket interface status. Information about PC Card V
support and card type
CC
is only updated at each insertion. Also note that the PCI1451 uses the CCD1 and CCD2 signals during card
identification, and changes on these signals during this operation are not reflected in this register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket present state
R
0
R
0
R
1
R
1
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket present state
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
0
R
0
R
0
R
X
R
X
R
X
Register:
Type:
Socket present state
Read-only
Offset:
Default:
CardBus Socket Address + 08h
3000 00XXh
Table 6–4. Socket Present State Register Description
BIT
SIGNAL
TYPE
FUNCTION
YV socket. This bit indicates whether or not the socket can supply V
does not support Y.YV V ; therefore, this bit is hardwired to 0.
CC
= Y.YV to PC Cards. The PCI1451
= X.XV to PC Cards. The PCI1451
CC
31
YVSOCKET
R
XV socket. This bit indicates whether or not the socket can supply V
does not support X.XV V ; therefore, this bit is hardwired to 0.
CC
CC
30
29
XVSOCKET
3VSOCKET
R
R
3-V socket. This bit indicates whether or not the socket can supply V
PCI1451 does support 3.3 V V ; therefore, this bit is always set unless overridden by the socket force
CC
event register (see Section 6.4).
= 3.3 Vdc to PC Cards. The
CC
5-V socket. This bit indicates whether or not the socket can supply V
PCI1451 does support 5.0 V V ; therefore, this bit is always 1 unless overridden by the device control
CC
register (bit 6) (see Section 4.39).
= 5.0 Vdc to PC Cards. The
CC
28
5VSOCKET
R
27–14
13
RSVD
R
R
These bits return 0s when read.
YV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
bit can be set by writing to the corresponding bit in the socket force event register (see Section 6.4).
= Y.Y Vdc. This
YVCARD
XV card. This bit indicates whether or not the PC Card inserted in the socket supports V = X.X Vdc. This
CC
bit can be set by writing to the corresponding bit in the socket force event register (see Section 6.4).
12
11
10
XVCARD
3VCARD
5VCARD
R
R
R
3-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
= 3.3 Vdc. This
CC
bit can be set by writing to the F3VCARD bit in the socket force event register (see Section 6.4).
5-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
= 5.0 Vdc. This
CC
bit can be set by writing to the F5VCARD bit in the socket force event register (see Section 6.4).
Bad V request. This bit indicates that the host software has requested that the socket be powered at
CC
an invalid voltage.
9
8
7
BADVCCREQ
DATALOST
R
R
R
0 = Normal operation (default)
1 = Invalid V
request by host software
CC
Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle
did not terminate properly or because write data still resides in the PCI1451.
0 = Normal operation (default)
1 = Potential data loss due to card removal
Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is
not updated until a valid PC Card is inserted into the socket.
NOTACARD
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
6–4
Table 6–4. Socket Present State Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC
Card interface.
6
IREQCINT
R
0 = READY(IREQ)//CINT is low
1 = READY(IREQ)//CINT is high
CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
5
4
CBCARD
R
R
16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
16BITCARD
Power cycle. This bit indicates the status of the card power request. This bit is encoded as:
3
2
PWRCYCLE
CDETECT2
R
R
0 = Socket is powered down (default)
1 = Socket is powered up
CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
0 = CCD2 is low (PC Card may be present)
1 = CCD2 is high (PC Card not present)
CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
1
0
CDETECT1
R
R
0 = CCD1 is low (PC Card may be present)
1 = CCD1 is high (PC Card not present)
This bit reflects the current status of the CSTSCHG signal at the PC Card interface.
CARDSTS.
CSTSCHG
0 = CSTSCHG is low
1 = CSTSCHG is high
6–5
6.4 Socket Force Event Register
This register is used to force changes to the socket event register (see Section 6.1) and the socket present state
register (see Section 6.3). The CVSTEST bit in this register must be written when forcing changes that require card
interrogation.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket force event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket force event
R
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
R
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
Socket force event
Read-only, Write-only
Offset:
Default:
CardBus Socket Address + 0Ch
0000 0000h
Table 6–5. Socket Force Event Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–15
RSVD
R
These bits return 0s when read.
Card VS test. When this bit is set, the PCI1451 reinterrogates the PC Card, updates the socket present
state register (see Section 6.3), and re-enables the socket power control.
14
13
12
11
10
9
CVSTEST
FYVCARD
W
Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register (see Section
6.3) to be written. When set, this bit disables the socket power control.
W
W
W
W
W
W
Force XV card. Writes to this bit cause the XVCARD bit in the socket present state register (see Section
6.3) to be written. When set, this bit disables the socket power control.
FXVCARD
Force 3-V card. Writes to this bit cause the 3VCARD bit in the socket present state register (see Section
6.3) to be written. When set, this bit disables the socket power control.
F3VCARD
Force 5-V card. Writes to this bit cause the 5VCARD bit in the socket present state register (see Section
6.3) to be written. When set, this bit disables the socket power control.
F5VCARD
Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register (see Section
6.3) can be made by writing this bit.
FBADVCCREQ
FDATALOST
Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register (see
Section 6.3) to be written.
8
Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register (see
Section 6.3) to be written.
7
6
5
FNOTACARD
RSVD
W
R
This bit returns 0 when read.
Force CardBus card. Writes to this bit cause the CBCARD bit in the socket present state register (see
Section 6.3) to be written.
FCBCARD
W
Force 16-bit card. Writes to this bit cause the 16BITCARD bit in the socket present state register (see
Section 6.3) to be written.
4
3
F16BITCARD
FPWRCYCLE
W
W
Force power cycle. Writes to this bit cause the PWREVENT bit in the socket event register (see Section
6.1) to be written, and the PWRCYCLE bit in the socket present state register (see Section 6.3) is
unaffected.
Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register (see Section 6.1)
to be written, and the CDETECT2 bit in the socket present state register (see Section 6.3) is unaffected.
2
1
0
FCDETECT2
FCDETECT1
FCARDSTS
W
W
W
Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register (see Section 6.1)
to be written, and the CDETECT1 bit in the socket present state register (see Section 6.3) is unaffected.
Force CSTSCHG. Writes to this bit cause the CSTSEVENT bit in the socket event register (see Section
6.1) to be written. The CARDSTS bit in the socket present state register (see Section 6.3) is unaffected.
6–6
6.5 Socket Control Register
This register provides control of the voltages applied to the socket’s V and V . The PCI1451 ensures that the
PP
CC
socket is powered up only at acceptable voltages when a CardBus card is inserted.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Socket control
Read-only, Read/Write
Offset:
Default:
CardBus Socket Address + 10h
0000 0000h
Table 6–6. Socket Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–8
RSVD
R
These bits return 0s when read.
This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock to the
CardBus Card:
0 = The PCI1451 Clock run master will request to stop the clock to the CardBus Card under the following
two
conditions:
The CardBus interface is idle for 8 clocks and
There is a request from the PCI master to stop the PCI clock.
7
STOPCLK
R/W
1 = The PCI1451 clock run master will try to stop the clock to the CardBus card under the following
condition:
The CardBus interface is idle for 8 clocks.
In summary, if this bit is set to1, then the CardBus controller will try to stop the clock to the CardBus card
independent of the PCI clock run signal if the CardBus interface is sampled idle for 8 clocks.
V
CC
control. These bits are used to request card V changes.
CC
000 = Request power off (default)
001 = Reserved
010 = Request V
011 = Request V
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= 5.0 V
= 3.3 V
= X.XV
= Y.YV
CC
CC
CC
CC
6–4
VCCCTRL
RSVD
R/W
3
R
This bit returns 0 when read.
control. These bits are used to request card VPP changes.
V
PP
000 = Request power off (default)
001 = Request V
010 = Request V
011 = Request V
= 12.0 V
= 5.0 V
= 3.3 V
= X.XV
= Y.YV
PP
PP
PP
2–0
VPPCTRL
R/W
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
PP
PP
6–7
6.6 Socket Power Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R/W
0
15
14
13
12
11
10
0
Name
Type
Default
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
Register:
Type:
Socket power management
Read-only, Read/Write
CardBus Socket Address + 20h
0000 0000h
Offset:
Default:
Table 6–7. Socket Power Management Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–26
RSVD
R
R
These bits return 0s when read.
Socket access status. This bit provides information on when a socket access has occurred. This bit is
cleared by a read access.
25
SKTACCES
0 = No PC Card access has occurred (default)
1 = PC Card has been accessed
Socket mode status. This bit provides clock mode information.
0 = Normal clock operation
24
23–17
16
SKTMODE
RSVD
R
R
1 = Clock frequency has changed
These bits return 0s when read.
CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL).
0 = Clock control disabled (default)
CLKCTRLEN
RSVD
R/W
R
1 = Clock control enabled
15–1
These bits return 0s when read.
CardBus clock control. This bit determines whether the CardBus CLKRUN protocol will attempt to stop or
slow the CardBus clock during idle states. The CLKCTRLEN bit enables this bit.
0
CLKCTRL
R/W
0 = Allows the CardBus CLKRUN protocol to attempt to stop the CardBus clock (default).
1 = Allows the CardBus CLKRUN protocol to attempt to slow the CardBus clock by a factor of 16.
6–8
7 Distributed DMA (DDMA) Registers
The DMA base address, programmable in PCI configuration space at offset 98h, points to a 16-byte region in PCI
I/O space where the DDMA registers reside. Table 7–1 summarizes the names and locations of these registers.
These registers are identical in function, but different in location from the Intel 8237 DMA controller. The similarity
between the register models retains some level of compatibility with legacy DMA and simplifies the translation
required by the master DMA device when forwarding legacy DMA writes to DMA channels.
These PCI1451 DMA register definitions are identical to those registers of the same name in the 8237 DMA controller;
however, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment. In such cases,
the PCI1451 will implement these obsolete register bits as nonfunctional, read-only bits. The reserved registers
shown in Table 7–1 are implemented as read-only, and return 0s when read. Writes to reserved registers have no
effect.
Table 7–1. Distributed DMA Registers
DMA BASE
TYPE
REGISTER NAME
ADDRESS
OFFSET
R
W
R
Current address
00h
04h
08h
0Ch
Reserved
Reserved
Page
Base address
Current count
Base count
Reserved
Reserved
W
R
N/A
Mode
N/A
Status
W
R
Request
N/A
Command
Multichannel
Reserved
Reserved
Master
clear
W
Mask
7–1
7.1 DMA Current Address/Base Address Register
This register is used to set the starting (base) memory address of a DMA transfer. Reads from this register indicate
the current memory address of a direct memory transfer.
For the 8-bit DMA transfer mode, the DMA current address register contents are presented on AD15–0 of the PCI
bus during the address phase. Bits 7–0 of the DMA page register are presented on AD23–AD16 of the PCI bus during
the address phase.
For the 16-bit DMA transfer mode, the DMA current address register contents are presented on AD16–AD1 of the
PCI bus during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the DMA page register (see Section 7.2)
are presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored.
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
Bit
DMA current address/base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Name
Type
Default
DMA current address/base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA current address/base address
Read/Write
Offset:
Default:
Size:
DMA Base Address + 00h
0000h
Two bytes
7.2 DMA Page Register
This register is used to set the upper byte of the address of a DMA transfer. Details of the address represented by
this register are explained in the DMA current address/base address register (see Section 7.1).
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA page
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA page
Read/Write
Offset:
Default:
Size:
DMA Base Address + 02h
00h
One byte
7–2
7.3 DMA Current Count/Base Count Register
This register is used to set the total transfer count, in bytes, of a direct memory transfer. Reads from this register
indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after
each transfer. Likewise, the count is decremented by 2 in 16-bit transfer mode.
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
Bit
DMA current count/base count
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Name
Type
Default
DMA current count/base count
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA current count/base count
Read/Write
Offset:
Default:
Size:
DMA Base Address + 04h
0000h
Two bytes
7.4 DMA Command Register
This register is used to enable and disable the controller; all other bits are reserved.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA command
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
Register:
Type:
DMA command
Read-only, Read/Write
DMA Base Address + 08h
00h
Offset:
Default:
Size:
One byte
Table 7–2. DDMA Command Register Description
FUNCTION
BIT
SIGNAL
TYPE
7–3
RSVD
R
These bits return 0s when read.
DMA controller enable. This bit enables and disables the distributed DMA slave controller in the PCI1451,
and defaults to the enabled state.
2
DMAEN
RSVD
R/W
R
0 = DMA controller enabled (default)
1 = DMA controller disabled
1–0
These bits return 0s when read.
7–3
7.5 DMA Status Register
This register indicates the terminal count and DMA request (DREQ) status.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA status
R
0
R
0
R
0
R
0
R/C
0
R/C
0
R/C
0
R/C
0
Register:
Type:
DMA status
Read-only
Offset:
Default:
Size:
DMA Base Address + 08h
00h
One byte
Table 7–3. DMA Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Channel request. In the 8237, these bits indicate the status of the DREQ signal of each DMA channel. In
the PCI1451, these bits indicate the DREQ status of the single socket being serviced by this register. All four
bits are set when the PC Card asserts its DREQ signal, and are reset when DREQ is deasserted. The status
of the mask bit in the DMA multichannel mask register (see Section 7.9) has no effect on these bits.
7–4
DREQSTAT
R
Channelterminal count. The 8327 uses these bits to indicate the TC status of each of its four DMA channels.
In the PCI1451, these bits report information about just a single DMA channel; therefore, all four of these
register bits indicate the TC status of the single socket being serviced by this register. All four bits are set
when the terminal count (TC) is reached by the DMA channel. These bits are reset when read or when the
DMA channel is reset.
3–0
TC
R/C
7.6 DMA Request Register
This register is used to request a DDMA transfer through software. Any write to this register enables software
requests. This register is to be used in block mode only.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA request
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
DMA request
Write-only
Offset:
Default:
Size:
DMA Base Address + 09h
00h
One byte
7–4
7.7 DMA Mode Register
This register is used to set the DMA transfer mode.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA mode
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Type:
DMA mode
Read-only, Read/Write
DMA Base Address + 0Bh
00h
Offset:
Default:
Size:
One byte
Table 7–4. DDMA Mode Register Description
BIT
SIGNAL
TYPE
FUNCTION
Mode select bits. The PCI1451 uses these bits to determine the transfer mode.
00 = Demand mode select (default)
01 = Single mode select
7–6
DMAMODE
R/W
10 = Block mode select
11 = Reserved
Address increment/decrement. The PCI1451 uses this register bit to select the memory address in the DMA
current address/base address register (see Section 7.1) to increment or decrement after each data transfer.
This is in accordance with the 8237 use of this register bit, and is encoded as follows:
0 = Addresses increment (default)
5
4
INCDEC
R/W
R/W
1 = Addresses decrement
Auto-initialization bit.
AUTOINIT
0 = Auto-initialization disabled (default)
1 = Auto-initialization enabled
Transfer type. These bits select the type of direct memory transfer to be performed. A memory write transfer
moves data from the PCI1451 PC Card interface to memory, and a memory read transfer moves data from
memory to the PCI1451 PC Card interface. The field is encoded as:
00 = No transfer selected (default)
01 = Write transfer
3–2
1–0
XFERTYPE
RSVD
R/W
R
10 = Read transfer
11 = Reserved
These bits return 0s when read.
7.8 DMA Master Clear Register
This register is used to reset the DDMA controller, and resets all DDMA registers.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA master clear
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
DMA master clear
Write-only
Offset:
Default:
Size:
DMA Base Address + 0Dh
00h
One byte
7–5
7.9 DMA Multichannel Mask Register
The PCI1451 uses only the least significant bit of this register to mask the PC Card DMA channel. The PCI1451 sets
the mask bit when the PC Card is removed. Host software is responsible for either resetting the socket DMA controller
or re-enabling the mask bit.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA multichannel mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
Register:
Type:
DMA multichannel mask
Read-only, Read/Write
DMA Base Address + 0Fh
00h
Offset:
Default:
Size:
One byte
Table 7–5. DDMA Multichannel Mask Register Description
BIT
SIGNAL
TYPE
FUNCTION
7–1
RSVD
R
These bits return 0s when read.
Mask select bit. This bit masks incoming DREQ signals from the PC Card. When set, the socket ignores DMA
requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced normally.
0 = DDMA service provided on card DREQ
0
MASKBIT
R/W
1 = Socket DREQ signal ignored (default)
7–6
8 Electrical Characteristics
†
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range, V
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
CCP, CCA, CCB
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCP
CCA
CCB
Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
CC
CCA
Output voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CCB
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V > V
does not apply to Misc terminals. PCI terminals are measured with
or V . The limit specified applies for a
I
CC
respect to V
instead of V . PC Card terminals are measured with respect to V
CC CCA
CCP
CCB
dc condition.
2. Applies for external output and bidirectional buffers. V > V
does not apply to Misc terminals. PCI terminals are measured with
instead of V . PC Card terminals are measured with respect to V or V . The limit specified applies for a
CC CCA
O
CC
respect to V
CCP
CCB
dc condition.
8–1
8.2 Recommended Operating Conditions (see Note 3)
OPERATION
MIN
3
NOM
3.3
3.3
5
MAX
3.6
UNIT
Core voltage, V
CC
Commercial
Commercial
3.3 V
3.3 V
5 V
V
3
3.6
PCI I/O voltage, V
CCP
V
V
4.75
3
5.25
3.6
3.3 V
5 V
3.3
5
PC Card I/O voltage, V
CC(A/B)
Commercial
PCI
4.75
5.25
3.3 V
5 V
0.5 V
V
CCP
CCP
2
V
CCP
3.3 V
5 V
0.475 V
V
V
CC(A/B)
CC(A/B)
PC Card
†
2.4
High-level Input voltage, V
IH
V
CC(A/B)
VS
3.3 V
3.3 V
2
V
V
V
CC
CC
CC
CD
2.4
2
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
‡
Miscellaneous
3.3 V
5 V
0.3 V
CCP
PCI
0.8
†
3.3 V
5 V
0.325 V
CC(A/B)
Low-level input voltage, V
V
V
IL
PC Card
0.8
‡
‡
‡
Miscellaneous
0.8
PCI
V
CCP
PC Card
V
V
Input voltage, V
CC(A/B)
I
Miscellaneous
PCI
V
CC
V
CCP
¶
PC Card
Output voltage, V
V
CC(A/B)
O
Miscellaneous
V
CC
4
PCI and PC Card
Input transition times (t and t ), t
t
ns
r
f
‡
Miscellaneous
6
Operating ambient temperature range, T
25
25
70
_C
_C
A
§
Virtual junction temperature, T
115
J
†
‡
Applies for external inputs and bidirectional buffers without hysteresis
Miscellaneous terminals are RI_OUT, CLOCK, DATA, LATCH, SPKROUT, SCL, SDA, SUSPEND, MFUNC terminals, VS terminals, CD
terminals, and ZV terminals.
§
¶
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
Applies for external output buffers
NOTE 3: Unused or floating terminals (input or I/O) must be held high or low.
8–2
8.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER
TERMINALS
PCI
OPERATION TEST CONDITIONS
MIN
MAX
UNIT
I
I
I
I
I
I
I
I
I
I
= –0.5 mA
= –2 mA
= –0.15 mA
= –0.15 mA
= –4 mA
= 1.5 mA
= 6 mA
0.9 V
3.3 V
5 V
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
CC
2.4
0.9 V
3.3 V
5 V
V
V
High-level output voltage (see Note 4)
CC
2.4
OH
OL
PC Card
Miscellaneous
PCI
§
V
–0.6
CC
0.1 V
3.3 V
5 V
CC
0.55
= 0.7 mA
= 0.7 mA
= 4 mA
0.1 V
CC
3.3 V
5 V
V
V
Low-level output voltage
PC Card
0.55
§
0.5
–1
–1
10
25
Miscellaneous
3.6 V
5.25 V
3.6 V
V = GND
I
Output-only
terminals
3-state-output, high-impedance-state
current (see Note 4)
I
I
µA
µA
OZL
V = GND
I
¶
V = V
Output-only
terminals
I
CC
CC
3-state-output, high-impedance-state
current
OZH
¶
5.25 V
V = V
I
Input-only
terminals
V = GND
I
–1
–10
†
V = GND
I
I
µA
µA
Low-level input current
I/O terminals
IL
Pullup
terminals
V = GND
–190
I
‡
¶
3.6 V
5.25 V
3.6 V
10
20
10
25
V = V
I
Input-only
terminals
CC
¶
¶
¶
V = V
I
CC
CC
CC
I
IH
High-level input current (see Note 5)
V = V
I
†
I/O terminals
5.25 V
V = V
I
†
‡
For I/O terminals, input leakage (I and I ) includes I
IL IH
leakage of the disabled output.
OZ
Pullup terminals: A_CPERR, A_CIRDY, A_CBLOCK, A_CSTOP, A_CDEVSEL, A_CTRDY, A_CSTSCHG, A_CAUDIO, A_CCD1, A_CCD2,
A_CREQ, A_CINT, A_CRST, A_CVS1, A_CVS2, A_CSERR, B_CPERR, B_CIRDY, B_CBLOCK, B_CSTOP, B_CDEVSEL, B_CTRDY,
B_CSTSCHG, B_CAUDIO, B_CCD1, B_CCD2, B_CREQ, B_CINT, B_CRST, B_CVS1, B_CVS2, B_CSERR, MFUNC5, MFUNC6, and LATCH.
Miscellaneous terminals are RI_OUT, CLOCK, DATA, LATCH, SPKROUT, SCL, SDA, SUSPEND, MFUNC terminals, VS terminals, CD
terminals, and ZV terminals.
§
¶
For PCI terminals, V = V
. For PC Card terminals, V = V
CCP
.
I
I
CC(A/B)
NOTES: 4. V
and I
are not tested on RI_OUTZ (pin P12) because they are open-drain outputs.
OH
OL
is not tested on pullup terminals because they are pulled up with an internal resistor.
5.
I
IH
8.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature (see Figure 8–2 and Figure 8–3)
PARAMETER
Cycle time, PCLK
ALTERNATE SYMBOL TEST CONDITIONS
MIN
30
11
11
1
MAX
UNIT
ns
t
t
t
t
cyc
c
Pulse duration, PCLK high
Pulse duration, PCLK low
Slew rate, PCLK
t
ns
wH
wL
high
t
ns
low
t , t
∆v/∆t
4
V/ns
ms
ms
r f
t
w
Pulse duration, RSTIN
t
1
rst
t
su
Setup time, PCLK active at end of RSTIN
t
100
rst-clk
8–3
8.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature (see Note 7, Figure 8–1 and Figure 8–4)
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
PCLK-to-shared signal
valid delay time
t
11
val
inv
C
= 50 pF,
L
t
Propagation delay time, See Note 6
ns
pd
See Note 7
PCLK-to-shared signal
invalid delay time
t
2
2
t
t
t
t
Enable time, high impedance-to-active delay time from PCLK
Disable time, active-to-high impedance delay time from PCLK
Setup time before PCLK valid
t
ns
ns
ns
ns
en
dis
su
h
on
t
28
off
t
7
0
su
Hold time after PCLK high
t
h
NOTES: 6. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
7. This data sheet uses the following conventions to describe time ( t ) intervals. The format is t , where subscript A indicates the type
A
ofdynamicparameterbeingrepresented. Oneofthefollowingisused:t =propagationdelaytime, t = delay time, t =setuptime,
pd su
d
and t = hold time.
h
8–4
8.6 Parameter Measurement Information
LOAD CIRCUIT PARAMETERS
I
†
‡
OL
TIMING
PARAMETER
C
I
I
V
LOAD
(pF)
OL
OH
LOAD
(V)
(mA)
(mA)
t
0
3
PZH
Test
Point
t
50
8
–8
en
t
t
t
PZL
PHZ
PLZ
From Output
Under Test
V
LOAD
t
t
50
50
8
8
–8
–8
1.5
‡
dis
pd
C
LOAD
†
‡
C
V
includes the typical load-circuit distributed capacitance.
LOAD
I
OH
– V
OL
LOAD
= 50 Ω, where V
= 0.6 V, I
= 8 mA
OL
OL
I
OL
LOAD CIRCUIT
V
Timing
Input
(see Note A)
CC
V
CC
50% V
High-Level
Input
CC
50% V
50% V
CC
CC
0 V
0 V
t
h
t
su
t
w
V
CC
90% V
Data
CC
V
CC
50% V
Input
50% V
CC
10% V
CC
CC
t
Low-Level
Input
0 V
50% V
50% V
CC
CC
0 V
t
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
Output
Control
(low-level
enabling)
V
CC
50% V
50% V
CC
CC
V
0 V
CC
Input
(see Note A)
t
50% V
50% V
CC
PZL
CC
t
PLZ
0 V
t
pd
V
t
CC
50% V
pd
V
Waveform 1
(see Notes B
and C)
CC
CC
OH
50% V
CC
In-Phase
Output
V
+ 0.3 V
OL
50% V
50% V
CC
CC
V
OL
V
OL
t
PHZ
t
pd
t
PZH
t
pd
V
OH
V
OH
Waveform 2
(see Notes B
and C)
V
– 0.3 V
OH
Out-of-Phase
Output
50% V
CC
50% V
50% V
CC
CC
50% V
V
OL
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, Z = 50 Ω, t = 6 ns.
O
r
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For t
and t
, V
PHZ OL
and V
are measured values.
OH
PLZ
Figure 8–1. Load Circuit and Voltage Waveforms
8–5
8.7 PCI Bus Parameter Measurement Information
t
high
t
low
2 V
0.8 V
2 V MIN Peak-to-Peak
t
f
t
r
t
cyc
Figure 8–2. PCLK Timing Waveform
PCLK
t
rst
RSTIN
t
srst-clk
Figure 8–3. RSTIN Timing Waveforms
PCLK
1.5 V
t
t
inv
val
1.5 V
Valid
PCI Output
PCI Input
t
t
on
off
Valid
t
su
t
h
Figure 8–4. Shared Signals Timing Waveforms
8.8 PC Card Cycle Timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O
window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and
hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles
that are as close to the Intel 82365SL-DF timing as possible, while always slightly exceeding the Intel 82365SL-DF
values. This ensures compatibility with existing software and maximizes throughput.
The PC Card address setup and hold times are a function of the wait-state bits. Table 8–1 shows address setup time
in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8–2 and Table 8–3 show command active time
in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8–4 shows address hold time in PCLK cycles
and nanoseconds for I/O and memory cycles.
8–6
Table 8–1. PC Card Address Setup Time, t
, 8-Bit and 16-Bit PCI Cycles
su(A)
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
3/90
Memory
Memory
WS1
WS1
0
1
2/60
4/120
Table 8–2. PC Card Command Active Time, t
, 8-Bit PCI Cycles
c(A)
WAIT-STATE BITS
TS1 – 0 = 01
(PCLK/ns)
WS
0
ZWS
0
X
1
19/570
23/690
7/210
1
I/O
0
00
01
10
11
00
0
19/570
23/690
23/690
23/690
7/210
X
X
X
1
Memory
Table 8–3. PC Card Command Active Time, t
, 16-Bit PCI Cycles
c(A)
WAIT-STATE BITS
TS1 – 0 = 01
(PCLK/ns)
WS
0
ZWS
0
X
1
7/210
11/330
N/A
1
I/O
0
00
01
10
11
00
0
9/270
13/390
17/510
23/630
5/150
X
X
X
1
Memory
Table 8–4. PC Card Address Hold Time, t
, 8-Bit and 16-Bit PCI Cycles
h(A)
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
2/60
2/60
3/90
Memory
Memory
WS1
WS1
0
1
8–7
8.9 Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature, Memory Cycles (for 100-ns Common Memory)
(see Note 8 and Figure 8–5)
ALTERNATE
SYMBOL
MIN
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, CE1 and CE2 before WE/OE low
Setup time, CA25–CA0 before WE/OE low
T1
60
+2PCLK
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su
su
su
pd
w
T2
t
su(A)
Setup time, REG before WE/OE low
T3
Propagation delay time, WE/OE low to WAIT low
Pulse duration, WE/OE low
T4
T5
200
120
Hold time, WE/OE low after WAIT high
T6
h
Hold time, CE1 and CE2 after WE/OE high
Setup time (read), CDATA15–CDATA0 valid before OE high
Hold time (read), CDATA15–CDATA0 valid after OE high
Hold time, CA25–CA0 and REG after WE/OE high
Setup time (write), CDATA15–CDATA0 valid before WE low
Hold time (write), CDATA15–CDATA0 valid after WE low
T7
h
T8
su
h
T9
0
+1PCLK
60
T10
T11
T12
t
h(A)
h
su
h
240
NOTE 8: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle
type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be
observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.
8.10 Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature, I/O Cycles
(see Figure 8–6)
ALTERNATE
MIN
MAX
UNIT
SYMBOL
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, REG before IORD/IOWR low
60
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su
su
su
pd
pd
w
Setup time, CE1 and CE2 before IORD/IOWR low
Setup time, CA25–CA0 valid before IORD/IOWR low
Propagation delay time, IOIS16 low after CA25–CA0 valid
Propagation delay time, IORD low to WAIT low
Pulse duration, IORD/IOWR low
t
+2PCLK
su(A)
35
35
T
cA
Hold time, IORD low after WAIT high
h
Hold time, REG low after IORD high
0
h
Hold time, CE1 and CE2 after IORD/IOWR high
Hold time, CA25–CA0 after IORD/IOWR high
Setup time (read), CDATA15–CDATA0 valid before IORD high
Hold time (read), CDATA15–CDATA0 valid after IORD high
Setup time (write), CDATA15–CDATA0 valid before IOWR low
Hold time (write), CDATA15–CDATA0 valid after IOWR high
120
h
t
+1PCLK
h
h(A)
10
0
su
h
90
90
su
h
8–8
8.11 Switching Characteristics Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature, Miscellaneous (see Figure 8–7)
ALTERNATE
SYMBOL
PARAMETER
MIN
MAX
UNIT
BVD2 low to SPKROUT low
BVD2 high to SPKROUT high
IREQ to IRQ15–IRQ3
30
30
30
30
T27
t
pd
Propagation delay time
ns
T28
STSCHG to IRQ15–IRQ3
8.12 PC Card Parameter Measurement Information
CA25–CA0
T10
REG
CE1, CE2
T1
T5
T7
WE, OE
WAIT
T3
T6
T2
T4
T12
T9
T11
CDATA15–CDATA0
(write)
T8
CDATA15–CDATA0
(read)
With no wait state
With wait state
Figure 8–5. PC Card Memory Cycle
8–9
CA25–CA0
IOIS16
T16
T22
REG
T20
T21
CE1, CE2
T14
T18
IORD, IOWR
WAIT
T13
T15
T19
T17
T26
T24
T25
CDATA15–CDATA0
(write)
T23
CDATA15–CDATA0
(read)
With no wait state
With wait state
Figure 8–6. PC Card I/O Cycle
BVD2
SPKROUT
IREQ
T27
T28
IRQ15–IRQ3
Figure 8–7. Miscellaneous PC Card Delay Times
8–10
9 Mechanical Data
GJG (S-PBGA-N257)
PLASTIC BALL GRID ARRAY
16,10
15,90
SQ
14,40 TYP
0,80
W
V
U
T
R
P
N
M
L
K
J
H
G
F
0,80
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,12
0,08
M
0,08
0,45
0,35
4173511/A 08/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
MicroStar is a trademark of Texas Instruments Incorporated.
9–1
9–2
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1999, Texas Instruments Incorporated
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