PCI1510ZVF [TI]
PC CARD CONTROLLERS; PC卡控制器
| 型号： | PCI1510ZVF |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PC CARD CONTROLLERS |
| 文件： | 总128页 (文件大小：713K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁ ꢂꢃ ꢄ ꢃ ꢅ ꢆ ꢆ ꢇ ꢈꢆ ꢉ ꢊꢈ ꢀꢆ ꢋꢈꢌ ꢆ ꢇꢈ ꢌꢉ ꢊ
ꢀꢁ ꢁ ꢍ ꢎꢏ ꢁ ꢐ ꢑ ꢒꢎꢐ ꢓꢓ ꢔꢎ ꢕ
Data Manual
December 2004
Connectivity Solutions
SCPS071E
IMPORTANT NOTICE
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Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
PCI1510 Data Manual Document History . . . . . . . . . . . . . . . . . . . . . . . 1−3
2
3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.1
2.2
PCI1510 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1
3.2
3.3
3.4
Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3−2
3.4.1
3.4.2
3.4.3
PCI GRST Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
Loading Subsystem Identification . . . . . . . . . . . . . . . . . . . . . 3−3
3.5
PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
3.5.1
3.5.2
3.5.3
3.5.4
PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3−4
Parallel Power-Switch Interface (TPS2211A) . . . . . . . . . . . 3−4
Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
Standardized Zoomed-Video Register Model . . . . . . . . . . . 3−6
3.5.4.1
Zoomed-Video Card Insertion and Configuration
Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . 3−8
LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3−8
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.6
Serial-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.6.1
3.6.2
3.6.3
3.6.4
Serial-Bus Interface Implementation . . . . . . . . . . . . . . . . . . . 3−9
Serial-Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
Serial-Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3−12
Accessing Serial-Bus Devices Through Software . . . . . . . 3−13
iii
Section
Title
Page
3.7
Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
PC Card Functional and Card Status Change Interrupts . 3−13
Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3−16
Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3−16
SMI Support in the PCI1510 Controller . . . . . . . . . . . . . . . . 3−16
3.8
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
3.8.9
3.8.10
3.8.11
Integrated Low-Dropout Voltage Regulator (LDO-VR) . . . . 3−17
Clock Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3−17
16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . 3−17
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18
Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3−18
Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19
PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19
CardBus Bridge Power Management . . . . . . . . . . . . . . . . . . 3−20
ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−21
Master List of PME Context Bits and Global Reset-Only
Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−22
4
PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4
PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
4.12 CardBus Socket/ExCA Base-Address Register . . . . . . . . . . . . . . . . . . 4−6
4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9
4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9
4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
iv
Section
Title
Page
4.22 I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12
4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13
4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13
4.28 PC Card 16-Bit I/F Legacy-Mode Base Address Register . . . . . . . . . 4−13
4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14
4.30 Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−16
4.31 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−17
4.32 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−18
4.33 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−19
4.34 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−20
4.35 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−20
4.36 Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−20
4.37 Power-Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 4−21
4.38 Power-Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 4−22
4.39 Power-Management Control/Status Register Bridge Support
Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−23
4.40 Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−23
4.41 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4−24
4.42 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . 4−25
4.43 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−26
4.44 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−26
4.45 Serial-Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−27
4.46 Serial-Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−27
4.47 Serial-Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−28
4.48 Serial-Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 4−29
ExCA Compatibility Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5−4
ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−5
ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−6
ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5−8
ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−9
ExCA Card Status-Change Interrupt Configuration Register . . . . . . . 5−10
ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5−11
ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−12
ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . 5−13
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . 5−13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . 5−13
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . 5−13
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers . . . 5−14
v
Section
Title
Page
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers . . . 5−14
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers . . . . 5−15
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers . . . 5−15
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers . . 5−16
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers . 5−16
5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5−17
5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−18
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . 5−19
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5−19
5.23 ExCA Memory Windows 0−4 Page Registers . . . . . . . . . . . . . . . . . . . 5−19
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1
6
7
6.1
6.2
6.3
6.4
6.5
6.6
Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2
Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3
Socket Present-State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4
Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−5
Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7
Socket Power-Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . 6−8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1
7.1
7.2
7.3
Absolute Maximum Ratings Over Operating Temperature Ranges . 7−1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7−2
Electrical Characteristics Over Recommended Operating
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−3
7.4
7.5
PCI Clock/Reset Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . 7−3
PCI Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . 7−4
8
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−1
vi
List of Illustrations
Figure
2−1
2−2
2−3
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
Title
Page
PCI1510 GGU-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
PCI1510 GVF-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
PCI1510 PGE-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
PCI1510 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
TPS2211A Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
Zoomed Video Implementation Using the PCI1510 Controller . . . . . . . . . 3−5
Zoomed Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
Sample Application of SPKROUT and CAUDPWM . . . . . . . . . . . . . . . . . . 3−8
Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
Serial-Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . 3−10
3−10 Serial-Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
3−11 Serial-Bus Protocol − Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
3−12 Serial-Bus Protocol − Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
3−13 EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . 3−12
3−14 IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16
3−15 Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18
3−16 RI_OUT Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19
3−17 Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−21
5−1
5−2
6−1
ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . 6−1
vii
List of Tables
Table
Title
Page
2−1
2−2
2−3
2−4
Signal Names Sorted by PGE Terminal Number . . . . . . . . . . . . . . . . . . . . 2−4
Signal Names Sorted by GGU Terminal Number . . . . . . . . . . . . . . . . . . . . 2−6
Signal Names Sorted by GVF Terminal Number . . . . . . . . . . . . . . . . . . . . 2−8
CardBus PC Card Signal Names Sorted Alphabetically to Device
Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11
2−5
16-Bit PC Card Signal Names Sorted Alphabetically to Device
Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13
2−6
2−7
2−8
2−9
Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15
PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15
PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−16
PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−17
2−10 PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−18
2−11 Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . 2−19
2−12 16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . 2−20
2−13 16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . 2−21
2−14 CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . . 2−22
2−15 CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . 2−23
2−16 CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . 2−24
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . . 3−4
Zoomed-Video Card Interrogation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
Register- and Bit-Loading Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−12
PCI1510 Registers Used to Program Serial-Bus Devices . . . . . . . . . . . . . 3−13
Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−14
PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3−14
SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16
3−10 Requirements for Internal/External 2.5-V Core Power Supply . . . . . . . . . 3−17
3−11 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−20
4−1
4−2
4−3
4−4
4−5
4−6
4−7
4−8
4−9
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2
Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4
Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12
System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14
Multifunction Routing Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 4−16
Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−17
viii
Table
Title
Page
4−10 Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−18
4−11 Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−19
4−12 Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−20
4−13 Power-Management Capabilities Register Description . . . . . . . . . . . . . . . 4−21
4−14 Power-Management Control/Status Register Description . . . . . . . . . . . . . 4−22
4−15 Power-Management Control/Status Register Bridge Support Extensions
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−23
4−16 General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . . 4−24
4−17 General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . . 4−25
4−18 General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . . 4−26
4−19 General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . . 4−26
4−20 Serial-Bus Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−27
4−21 Serial-Bus Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−27
4−22 Serial-Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . 4−28
4−23 Serial-Bus Control and Status Register Description . . . . . . . . . . . . . . . . . . 4−29
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2
ExCA Identification and Revision Register Description . . . . . . . . . . . . . . . 5−4
ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . 5−5
ExCA Power Control Register Description—82365SL Support . . . . . . . . 5−6
ExCA Power Control Register Description—82365SL-DF Support . . . . . 5−7
ExCA Interrupt and General Control Register Description . . . . . . . . . . . . 5−8
ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . . 5−9
ExCA Card Status-Change Interrupt Configuration Register
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−10
5−9
ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . . 5−11
5−10 ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . . 5−12
5−11 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−14
5−12 ExCA Memory Windows 0−4 End-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−15
5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−16
5−14 ExCA Card Detect and General Control Register Description . . . . . . . . . 5−17
5−15 ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 5−18
6−1
6−2
6−3
6−4
6−5
6−6
6−7
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1
Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2
Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3
Socket Present-State Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 6−4
Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6−6
Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7
Socket Power-Management Register Description . . . . . . . . . . . . . . . . . . . 6−8
ix
x
1 Introduction
1.1 Description
The Texas Instruments PCI1510 device, a 144-terminal or a 209-terminal single-slot CardBus controller designed
to meet the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges, is an ultralow-power
high-performance PCI-to-CardBus controller that supports a single PC card socket compliant with the PC Card
Standard (rev. 7.2). The controller provides features that make it the best choice for bridging between PCI and PC
Cards in both notebook and desktop computers. The PC Card Standard retains the 16-bit PC Card specification
defined in the PCI Local Bus Specification and defines the 32-bit PC Card, CardBus, capable of full 32-bit data
transfers at 33 MHz. The controller supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required.
The controller is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master
device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging transactions. The
controller is also compliant with PCI Bus Power Management Interface Specification (rev. 1.1).
All card signals are internally buffered to allow hot insertion and removal without external buffering. The controller
is register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The controller internal data path
logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance.
Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting.
The controller can also be programmed to accept fast posted writes to improve system-bus utilization.
Multiple system-interrupt signaling options are provided, including parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the PCI1510 controller, such as a socket activity light-emitting
diode (LED) outputs, are discussed in detail throughout this document.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption
while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management
system to further reduce power consumption.
1.2 Features
The controller supports the following features:
•
A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGA ball-grid array (GGU/ZGU) package,
or a 209-terminal PBGA (GVF/ZVF) package
•
2.5-V core logic and 3.3-V I/O with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling
environments
•
•
•
•
•
•
•
•
Integrated low-dropout voltage regulator (LDO-VR) eliminates the need for an external 2.5-V power supply
Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
A single PC Card or CardBus slot with hot insertion and removal
Parallel interface to TI TPS2211A single-slot PC Card power switch
Burst transfers to maximize data throughput with CardBus Cards
Interrupt configurations: parallel PCI, serialized PCI, parallel ISA, and serialized ISA
Serial EEPROM interface for loading subsystem ID, subsystem vendor ID, and other configuration registers
Pipelined architecture for greater than 130-Mbps throughput from CardBus-to-PCI and from PCI-to-
CardBus
1−1
•
•
•
•
•
•
•
•
•
•
Up to five general-purpose I/Os
Programmable output select for CLKRUN
Five PCI memory windows and two I/O windows available for the 16-bit interface
Two I/O windows and two memory windows available to the CardBus socket
Exchangeable-card-architecture- (ExCA-) compatible registers are mapped in memory and I/O space
Intel 82365SL-DF and 82365SL register compatible
Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN
Socket activity LED terminal
PCI bus lock (LOCK)
Internal ring oscillator
1.3 Related Documents
•
•
•
•
•
•
•
•
Advanced Configuration and Power Interface (ACPI) Specification (revision 1.1)
PCI Bus Power Management Interface Specification (revision 1.1)
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (revision 0.6)
PCI to PCMCIA CardBus Bridge Register Description (Yenta) (revision 2.1)
PCI Local Bus Specification (revision 2.2)
PCI Mobile Design Guide (revision 1.0)
PC Card Standard (revision 7.2)
Serialized IRQ Support for PCI Systems (revision 6)
1.4 Trademarks
Intel is a trademark of Intel Corporation.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
1.5 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are listed
below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary
field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit
hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number are
assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the logical
NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. RSVD indicates that the referenced item is reserved.
6. In Sections 4 through 6, the configuration space for the controller is defined. For each register bit, the
software access method is identified in an access column. The legend for this access column includes the
following entries:
r – read-only access
1−2
ru – read-only access with updates by the controller internal hardware
rw – read and write access
rcu – read access with the option to clear an asserted bit with a write-back of 1b including updates by
the controller internal hardware.
1.6 Ordering Information
ORDERING NUMBER
PCI1510
NAME
VOLTAGE
PACKAGE
144-terminal LQFP
PC Card controller
3.3 V, 5-V tolerant I/Os
144-ball PBGA (GGU or ZGU)
209-ball PBGA (GVF or ZVF)
1.7 PCI1510 Data Manual Document History
DATE
PAGE NUMBER
REVISION
01/2003
01/2003
01/2003
01/2003
2−23
3−2
Modified terminal number of CAD30 from 143 to 142 for PGE package
Added new subsection 3.4.1 to describe GRST during power up
3−11
3−20
Modified byte-read diagram (Figure 3−12) to better reflect a read transaction to the EEPROM
Modified the description of the power management capabilities register. This register is not a static
read-only register.
08/2003
08/2003
08/2003
10/2003
10/2003
10/2003
10/2003
07/2004
12/2004
1−3
2−1
8−4
1−1
1−3
2−8
8−2
Added lead-free (Pb, atomic number 82) MicroStar BGA package (ZGU) to ordering information
Added description for ZGU package
Added ZGU mechanical drawing
Added GVF package to features
Added GVF package to ordering information
Added GVF terminal descriptions, Table 2−3
Added GVF mechanical drawing.
Chapters 1, 2, 8 Added RGVF, RZVF, and ZVF packages and pinout.
Chapters 1, 2, 8 Removed RGVF and RZVF packages and pinout.
Added Section 1.5, Document Conventions
1−3
1−4
2 Terminal Descriptions
The PCI1510 controller is available in five packages, a 144-terminal quad flatpack (PGE), two 144-terminal MicroStar
BGA packages (GGU/ZGU), and two 209-terminal PBGA packages (GVF/ZVF). The GGU and ZGU packages are
mechanically and electrically identical, but the ZGU is a lead-free (Pb, atomic number 82) design. Throughout the
remainder of this manual, only the GGU package designator is used for either the GGU or ZGU package. The terminal
layout for the GGU package is shown in Figure 2−1. The GVF and ZVF packages are mechanically and electrically
identical, but the ZVF is a lead-free (Pb, atomic number 82) design. Throughout the remainder of this manual, only
the GVF package designator is used for either the GVF or ZVF package. The terminal layout for the GVF package
is shown in Figure 2−2. The terminal layout with signal names for the PGE package is shown in Figure 2−3.
GGU PACKAGE
(TOP VIEW)
13
12
11
10
9
C
C
C
C
C
C
C
C
C
C
C
C
C
C
P
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
M
T
C
T
T
C
C
C
C
C
C
C
C
C
P
P
P
C
C
C
C
T
M
C
C
C
M
M
M
M
P
8
7
M
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
6
C
C
C
C
P
P
P
P
5
4
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
3
P
P
P
P
P
2
1
P
P
A
B
C
D
E
F
G
H
J
K
L
M
N
P
C
T
PCI Interface
VCC
PC Card Interface
TPS Power Switch
MFUNC Pins
Ground (GND)
Miscellaneous
M
Figure 2−1. PCI1510 GGU-Package Terminal Diagram
2−1
GVF PACKAGE
(TOP VIEW)
C
C
C
C
C
N
N
N
N
N
N
N
N
N
N
19
18
17
16
15
14
13
12
11
10
9
C
C
C
C
C
C
C
C
C
C
N
N
C
C
C
N
N
N
N
N
N
N
P
C
C
C
C
C
C
C
C
N
N
T
C
C
C
C
C
C
C
C
N
N
T
C
C
C
C
C
C
C
C
N
N
M
C
C
C
C
C
C
C
C
C
C
N
N
N
N
N
N
N
N
N
N
N
P
P
P
P
N
N
N
N
N
N
P
P
P
P
P
N
N
N
N
N
N
P
P
P
P
P
C
C
C
C
C
C
C
N
T
N
N
N
N
N
P
P
P
P
C
C
C
8
P
7
N
T
M
M
M
P
P
P
P
P
P
P
P
P
P
6
N
P
P
5
4
N
M
M
M
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
3
P
P
2
N
P
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
P
PCI Interface
VCC
C
T
PC Card Interface
TPS Power Switch
MFUNC Pins
Ground (GND)
Miscellaneous
No Connection
N
M
Figure 2−2. PCI1510 GVF-Package Terminal Diagram
2−2
2.1 PCI1510 Terminal Assignments
Figure 2−3 and Table 2−1 show the terminal assignments for the PGE package. Table 2−2 and Table 2−3 list the
terminal assignments for the GGU and GVF packages, respectively. The signal names for the PC Card slot are given
in a CardBus // 16-bit signal format. All tables are arranged in order by increasing terminal designator, which is
numeric for the PGE package and alphanumeric for the other packages. Table 2−4 and Table 2−5 list the CardBus
and 16-bit signal names, respectively, in alphanumerical order with the corresponding terminal numbers for each
package.
PGE PACKAGE
(TOP VIEW)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
VCCCB
CIRDY//A15
CFRAME//A23
GND
VPPD1
VPPD0
VCC
109
110
111
112
113
114
MFUNC6
MFUNC5
MFUNC4
GRST
SUSPEND
MFUNC3
MFUNC2
VR_PORT
SPKROUT
GND
CC/BE2//A12
CAD17//A24
CAD18//A7
115
116
CAD19//A25
CVS2//VS2
117
118
CAD20//A6
CRST//RESET
CAD21//A5
119
120
121
122
CAD22//A4
CREQ//INPACK
CAD23//A3
MFUNC1
MFUNC0
RI_OUT/PME
AD0
123
124
CC/BE3//REG
VR_EN
125
126
VCC
AD1
CAD24//A2
VCC
127
128
129
130
CAD25//A1
53
52
AD2
CAD26//A0
AD3
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CVS1//VS1
AD4
131
132
CINT//READY(IREQ)
GND
AD5
AD6
133
134
CSERR//WAIT
CAUDIO//BVD2(SPKR)
CSTSCHG//BVD1(STSCHG/RI)
CCLKRUN//WP(IOIS16)
VCC
AD7
C/BE0
AD8
135
136
137
AD9
AD10
CCD2//CD2
AD11
138
139
CAD27//D0
AD12
140
CAD28//D8
AD13
141
142
CAD29//D1
GND
CAD30//D9
AD14
143
144
CRSVD//D2
AD15
CAD31//D10
C/BE1
Figure 2−3. PCI1510 PGE-Package Terminal Diagram
2−3
Table 2−1. Signal Names Sorted by PGE Terminal Number
SIGNAL NAME
SIGNAL NAME
TERMINAL
TERMINAL
CARDBUS
16-BIT
CARDBUS
16-BIT
1
REQ
REQ
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
AD11
AD10
AD9
AD8
C/BE0
AD7
AD6
AD5
AD4
AD3
AD2
AD11
AD10
AD9
AD8
C/BE0
AD7
AD6
AD5
AD4
AD3
AD2
2
GNT
GNT
3
AD31
AD30
AD29
AD28
AD27
GND
AD26
AD25
AD24
AD31
AD30
AD29
AD28
AD27
GND
AD26
AD25
AD24
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
V
CC
V
CC
V
CC
V
CC
C/BE3
IDSEL
AD23
AD22
AD21
AD20
PRST
PCLK
GND
C/BE3
IDSEL
AD23
AD22
AD21
AD20
PRST
PCLK
GND
AD1
AD0
AD1
AD0
RI_OUT/PME
MFUNC0
MFUNC1
GND
RI_OUT/PME
MFUNC0
MFUNC1
GND
SPKROUT
VR_PORT
MFUNC2
MFUNC3
SUSPEND
GRST
SPKROUT
VR_PORT
MFUNC2
MFUNC3
SUSPEND
GRST
AD19
AD18
AD17
AD16
C/BE2
AD19
AD18
AD17
AD16
C/BE2
FRAME
IRDY
MFUNC4
MFUNC5
MFUNC6
MFUNC4
MFUNC5
MFUNC6
FRAME
IRDY
V
CC
V
CC
TRDY
TRDY
DEVSEL
STOP
VPPD0
VPPD1
VCCD0
VCCD1
CCD1
CAD0
CAD2
CAD1
CAD4
GND
VPPD0
VPPD1
VCCD0
VCCD1
CD1
D3
DEVSEL
STOP
V
CC
V
CC
PERR
SERR
PAR
PERR
SERR
PAR
D11
V
CCP
V
CCP
D4
C/BE1
AD15
AD14
GND
C/BE1
AD15
AD14
GND
D12
GND
D5
CAD3
CAD6
CAD5
CRSVD
D13
AD13
AD12
AD13
AD12
D6
D14
2−4
Table 2−1. Signal Names Sorted by PGE Terminal Number (Continued)
SIGNAL NAME
SIGNAL NAME
TERMINAL
TERMINAL
CARDBUS
CLK_48_RSVD
CAD7
16-BIT
CARDBUS
16-BIT
85†
86
CLK_48_RSVD
D7
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
CAD18
CAD19
CVS2
A7
A25
87
CAD8
D15
VS2
A6
88
CC/BE0
CAD9
CE1
A10
CAD20
CRST
89
RESET
A5
90
CAD10
CE2
OE
CAD21
CAD22
CREQ
CAD23
91
CAD11
A4
92
CAD12
A11
INPACK
A3
93
GND
GND
IORD
IOWR
A9
94
CAD13
CC/BE3
VR_EN
REG
VR_EN
95
CAD15
96
CAD14
V
V
CC
CC
97
CAD16
A17
CAD24
CAD25
CAD26
CVS1
A2
98
CC/BE1
CRSVD
CPAR
A8
A1
99
A18
A0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
A13
VS1
CBLOCK
CPERR
CSTOP
A19
CINT
READY(IREQ)
GND
A14
GND
A20
CSERR
CAUDIO
CSTSCHG
CCLKRUN
WAIT
V
CC
V
CC
BVD2(SPKR)
BVD1(STSCHG/RI)
WP(IOIS16)
CGNT
WE
A21
A16
A22
CDEVSEL
CCLK
V
CC
V
CC
CTRDY
CCD2
CD2
D0
V
V
CAD27
CAD28
CAD29
CAD30
CRSVD
CAD31
CCCB
CCCB
CIRDY
CFRAME
GND
A15
A23
GND
A12
A24
D8
D1
D9
CC/BE2
CAD17
D2
D10
†
Terminal 85 is an NC on the PCI1510 to allow for terminal compatibility with the next generation of devices.
2−5
Table 2−2. Signal Names Sorted by GGU Terminal Number
SIGNAL NAME
SIGNAL NAME
TERMINAL
TERMINAL
CARDBUS
16-BIT
CARDBUS
16-BIT
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C/BE3
GND
C/BE3
GND
D2
D05
D06
D07
D08
D09
D10
D11
D12
D13
E01
E02
E03
E04
E10
E11
E12
E13
F01
F02
F03
F04
F10
F11
F12
F13
G01
G02
G03
G04
G10
G11
G12
G13
H01
H02
H03
V
V
CC
CC
CAUDIO
CAD25
CRST
BVD2(SPKR)
A1
CRSVD
CAD27
CCLKRUN
CINT
D0
RESET
A12
WP(IOIS16)
READY(IREQ)
CC/BE2
CAD23
CDEVSEL
CPERR
CGNT
A3
V
CC
V
CC
A21
CC/BE3
CVS2
REG
VS2
A23
A14
WE
CFRAME
GND
V
CC
V
CC
GND
A7
AD25
AD25
AD31
AD29
A20
CAD18
CBLOCK
AD27
AD31
A19
AD29
AD27
VS1
D10
D9
CSTOP
CC/BE1
CPAR
CRSVD
AD22
CVS1
A8
CAD31
CAD30
CCD2
A13
A18
CD2
WAIT
A2
AD22
IDSEL
AD24
AD26
A17
CSERR
CAD24
CREQ
CAD19
CAD17
IDSEL
AD24
INPACK
A25
AD26
CAD16
CAD14
CAD13
GND
A24
A9
V
V
IORD
GND
PCLK
AD20
PRST
AD21
OE
CCCB
CCCB
CAD22
CCLK
A4
A16
PCLK
AD20
GNT
GNT
REQ
REQ
PRST
AD21
AD23
AD23
CAD29
CAD28
CSTSCHG
CAD26
CAD21
CAD20
CIRDY
D1
CAD11
CAD9
CAD12
CAD10
AD17
D8
A10
BVD1(STSCHG/RI)
A11
A0
CE2
A5
AD17
AD19
AD18
A6
AD19
A15
AD18
C11
C12
C13
D01
D02
D03
D04
CAD15
CTRDY
IOWR
A22
H04
H10†
H11
H12
H13
J01
GND
GND
CLK_48_RSVD
CAD8
CLK_48_RSVD
D15
V
CC
V
CC
GND
GND
CAD7
D7
AD28
AD30
VR_EN
AD28
AD30
VR_EN
CC/BE0
FRAME
C/BE2
CE1
FRAME
C/BE2
J02
†
Terminal H10 is not bonded out in the packaged parts in order to have pin compatibility with future devices.
2−6
Table 2−2. Signal Names Sorted by GGU Terminal Number (Continued)
SIGNAL NAME
SIGNAL NAME
TERMINAL
TERMINAL
CARDBUS
16-BIT
CARDBUS
16-BIT
J03
J04
J10
J11
TRDY
AD16
CAD5
CAD4
TRDY
AD16
D6
L11
L12
GRST
GRST
VCCD1
CD1
VCCD1
CCD1
L13
D12
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
V
CC
V
CC
J12
J13
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
CRSVD
CAD3
D14
AD9
AD9
D5
C/BE1
AD15
C/BE1
AD15
AD10
AD5
IRDY
IRDY
DEVSEL
PERR
AD4
DEVSEL
PERR
AD4
AD10
AD5
AD1
AD1
AD13
AD13
C/BE0
MFUNC0
GND
RI_OUT/PME
SPKROUT
MFUNC4
VPPD1
CAD2
GND
RI_OUT/PME
SPKROUT
MFUNC4
VPPD1
D11
C/BE0
MFUNC0
GND
VPPD0
MFUNC3
CAD0
VPPD0
MFUNC3
D3
GND
PAR
PAR
CAD1
D4
GND
GND
CAD6
D13
AD12
AD12
STOP
SERR
STOP
SERR
AD8
AD8
AD7
AD7
V
CCP
V
CCP
AD3
AD3
AD11
AD11
AD14
AD6
V
CC
V
CC
AD14
AD0
AD0
AD6
MFUNC1
SUSPEND
MFUNC1
SUSPEND
AD2
AD2
VR_PORT
MFUNC2
MFUNC6
VR_PORT
MFUNC2
MFUNC6
V
CC
V
CC
MFUNC5
VCCD0
MFUNC5
VCCD0
2−7
Table 2−3. Signal Names Sorted by GVF Terminal Number
SIGNAL NAME
SIGNAL NAME
TERMINAL
TERMINAL
CARDBUS
VPPD0
16-BIT
CARDBUS
16-BIT
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
D01
D19
E01
E02
E03
E05
E06
VPPD0
E07
E08
E09
E10
E11
E12
E13
E14
E17
E18
E19
F01
F02
F03
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F17
F18
F19
G01
G02
G03
G05
G06
G14
G15
G17
G18
G19
H01
H02
H03
H05
NC
NC
V
V
CAD31
CAD28
D10
D8
CC
CC
NC
NC
GND
GND
CSERR
CAD25
CAD21
CAD18
CTRDY
CSTOP
CBLOCK
WAIT
A1
V
CC
V
CC
CSTSCHG
GND
BVD1(STSCHG/RI)
GND
A5
A7
V
V
A22
A20
A19
CCCB
CAD23
CCCB
A3
V
CC
V
CC
CAD19
GND
A25
V
CC
V
CC
GND
A21
MFUNC5
MFUNC3
MFUNC2
MFUNC0
NC
MFUNC5
MFUNC3
MFUNC2
MFUNC0
NC
CDEVSEL
VCCD1
NC
VCCD1
NC
NC
NC
CAD29
CCLKRUN
CVS1
CC/BE3
CREQ
CRST
CAD17
CFRAME
VPPD1
NC
D1
NC
NC
WP(IOIS16)
VS1
CRSVD
CAD27
CAUDIO
CAD26
CVS2
D2
D0
REG
INPACK
RESET
A24
BVD2(SPKR)
A0
VS2
CIRDY
CPAR
A15
A23
A13
VPPD1
NC
CPERR
CRSVD
CAD16
CAD14
A14
A18
NC
NC
A17
CAD30
CCD2
CINT
D9
A9
CD2
V
CC
V
CC
READY(IREQ)
A2
VR_PORT
SUSPEND
MFUNC4
MFUNC1
VR_PORT
SUSPEND
MFUNC4
MFUNC1
CAD24
CAD22
CAD20
CC/BE2
CCLK
NC
A4
A6
A12
V
V
CCCB
CCCB
A16
CC/BE1
CAD15
CAD13
GND
A8
NC
IOWR
IORD
GND
CGNT
GND
WE
GND
SPKROUT
NC
SPKROUT
NC
PCLK
PCLK
GRST
PRST
VR_EN
GRST
PRST
NC
NC
VCCD0
VCCD0
VR_EN
†
Terminal F06 is not bonded out in the packaged parts in order to have pin compatibility with future devices.
2−8
Table 2−3. Signal Names Sorted by GVF Terminal Number (Continued)
SIGNAL NAME
SIGNAL NAME
TERMINAL
TERMINAL
CARDBUS
MFUNC6
16-BIT
MFUNC6
CARDBUS
16-BIT
H06
H14
H15
H17
H18
H19
J01
J02
J03
J05
J06
J14
J15
J17
J18
J19
K01
K02
K03
K05
K06
K14
K15
K17
K18
K19
L01
L02
L03
L05
L06
L14
L15
L17
L18
L19
M01
M02
M03
M05
M06
M14
M15
M17
M18
M19
N01
N02
N03
N05
N06
N14
N15
N17
N18
N19
P01
P02
P03
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P17
P18
P19
R01
R02
R03
R06
R07
R08
R09
R10
R11
R12
R13
R14
R17
NC
NC
CAD11
CAD12
CAD10
CAD9
OE
NC
NC
A11
CE2
A10
NC
NC
GND
AD19
AD18
GND
AD19
AD18
FRAME
AD17
NC
V
CC
V
CC
GNT
GNT
REQ
FRAME
AD17
NC
REQ
RI_OUT/PME
AD31
RI_OUT/PME
AD31
AD30
D15
NC
NC
AD30
NC
NC
CAD8
CC/BE0
CAD7
CRSVD
CAD5
GND
NC
NC
CE1
NC
NC
D7
AD16
C/BE2
IRDY
STOP
TRDY
AD14
AD9
NC
AD16
C/BE2
IRDY
STOP
TRDY
AD14
AD9
NC
D14
D6
GND
AD29
AD28
AD27
AD26
D13
AD29
AD28
AD27
AD26
CAD6
CAD3
CAD4
CAD1
GND
NC
NC
D5
NC
NC
D12
NC
NC
D4
NC
NC
GND
NC
NC
V
CCP
V
CCP
NC
NC
AD25
AD25
AD24
IDSEL
C/BE3
D11
NC
NC
AD24
NC
NC
IDSEL
C/BE3
CAD2
GND
GND
V
CC
V
CC
DEVSEL
PERR
AD15
AD10
AD6
AD0
NC
DEVSEL
PERR
AD15
AD10
AD6
AD0
NC
CAD0
D3
CCD1
VR_PORT
CD1
VR_PORT
V
V
V
V
CC
CC
CC
CC
AD23
AD22
AD20
AD21
NC
AD23
AD22
AD20
AD21
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2−9
Table 2−3. Signal Names Sorted by GVF Terminal Number (Continued)
SIGNAL NAME
SIGNAL NAME
TERMINAL
TERMINAL
CARDBUS
16-BIT
CARDBUS
16-BIT
R18
R19
T01
T19
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
V05
V06
V07
V08
V09
NC
NC
V10
V11
NC
NC
NC
NC
NC
NC
PAR
NC
NC
NC
NC
NC
NC
PAR
NC
NC
SERR
NC
SERR
NC
V12
V13
C/BE1
AD12
AD8
AD5
AD1
NC
C/BE1
AD12
AD8
AD5
AD1
NC
V14
V15
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
V
CCP
V
CCP
GND
AD7
GND
AD7
NC
NC
V
CC
V
CC
NC
NC
AD3
NC
NC
NC
NC
NC
NC
NC
AD3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AD13
AD11
C/BE0
AD4
AD2
AD13
AD11
C/BE0
AD4
AD2
2−10
Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically to Device Terminals
TERMINAL
GGU
N08
M07
L07
TERMINAL
GGU
G10
G12
F12
F11
SIGNAL NAME
SIGNAL NAME
PGE
56
55
53
52
51
50
49
48
46
45
44
43
42
41
39
38
25
24
23
22
18
17
16
15
11
10
9
GVF
R09
U09
V09
W09
V08
U08
R08
W07
U07
P08
R07
V06
U06
V05
P07
R06
P01
N06
N03
N02
M05
M06
M03
M02
L03
L02
K06
K05
K03
K02
J06
PGE
91
GVF
H14
H15
G18
F19
G17
F18
B14
E13
A14
C13
E12
C12
A12
C11
E11
F11
F09
E09
B08
C08
E08
F10
V07
U05
P02
L06
E18
J15
G15
C14
B11
L17
C09
C15
B09
A16
B15
D19
C10
F13
—
AD0
CAD11
AD1
CAD12
CAD13
CAD14
CAD15
CAD16
CAD17
CAD18
CAD19
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD28
CAD29
CAD30
CAD31
CAUDIO
C/BE0
92
AD2
94
AD3
N06
K04
M06
L06
96
AD4
95
C11
F10
B10
A12
B09
C09
C08
B12
D10
B07
D07
C07
A04
C05
C04
B04
B03
D06
K06
M03
J02
AD5
97
AD6
114
115
116
118
120
121
123
127
128
129
139
140
141
142
144
134
47
AD7
N05
N04
M02
M05
L04
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CAD0
CAD1
CAD2
CAD3
CAD4
CAD5
CAD6
CAD7
CAD8
CAD9
N03
K05
L05
M04
J04
H01
H03
H02
G02
G04
F01
C03
F03
E02
F04
B01
D02
E04
D03
E03
K11
C/BE1
37
C/BE2
26
C/BE3
13
A01
A13
H13
E11
CBLOCK
CC/BE0
CC/BE1
CC/BE2
CC/BE3
CCD1
101
88
7
6
98
5
113
124
75
D09
A08
L13
4
3
J05
76
78
77
81
79
83
82
86
87
89
90
L15
K18
L14
K15
K17
J19
CCD2
138
107
136
106
111
105
131
110
85
B05
B13
A05
D11
A10
D13
A06
C10
H10
E12
D12
K12
M12
J13
CCLK
CCLKRUN
CDEVSEL
CFRAME
CGNT
J11
J10
K13
H12
H11
G11
G13
K14
J17
CINT
CIRDY
CLK_48_RSVD
CPAR
J14
H18
H17
100
102
F14
F15
CAD10
CPERR
2−11
Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically to Device Terminals (Continued)
TERMINAL
GGU
B08
D08
A03
E13
J12
TERMINAL
GGU
M10
N12
L10
SIGNAL NAME
CREQ
SIGNAL NAME
MFUNC4
PGE
122
119
84
GVF
B12
B13
F08
F17
J18
E10
E17
A09
E14
B10
F12
R02
N05
J01
H02
L05
P03
F05
G06
F03
F02
PGE
67
68
69
35
20
33
19
1
GVF
G05
F01
CRST
MFUNC5
MFUNC6
PAR
CRSVD
CRSVD
CRSVD
CSERR
CSTOP
CSTSCHG
CTRDY
CVS1
H06
W04
H01
R03
H03
J02
99
N01
G01
K03
143
133
103
135
108
130
117
30
PCLK
B06
E10
C06
C12
B02
A09
K02
J01
PERR
PRST
G03
C02
M08
L02
REQ
RI_OUT/PME
SERR
57
34
61
31
65
29
73
74
71
72
125
62
J03
T01
CVS2
SPKROUT
STOP
M09
L01
E02
DEVSEL
FRAME
GNT
P05
27
SUSPEND
TRDY
N10
J03
G03
P06
2
C01
L11
GRST
66
VCCD0
VCCD1
VPPD0
VPPD1
VR_EN
VR_PORT
N13
L12
E06
IDSEL
14
F02
B05
IRDY
28
K01
K07
N09
L09
K09
A04
MFUNC0
MFUNC1
MFUNC2
MFUNC3
58
M11
D04
L08
C05
H05
G02, L18
59
63
64
K10
2−12
Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically to Device Terminals
TERMINAL
GGU
N08
M07
L07
TERMINAL
GGU
G12
D09
E12
D12
C10
B13
F10
E13
A13
E10
D11
C12
A10
B10
B09
C06
D06
K06
M03
J02
SIGNAL NAME
SIGNAL NAME
PGE
56
55
53
52
51
50
49
48
46
45
44
43
42
41
39
38
25
24
23
22
18
17
16
15
11
GVF
R09
U09
V09
W09
V08
U08
R08
W07
U07
P08
R07
V06
U06
V05
P07
R06
P01
N06
N03
N02
M05
M06
M03
M02
L03
L02
K06
K05
K03
K02
J06
PGE
92
GVF
H15
C14
F14
F15
F13
C15
F18
F17
E18
E17
A16
E14
B15
B14
A14
A09
F10
V07
U05
P02
L06
L17
C09
J15
H17
—
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
A0
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
113
100
102
110
107
97
N06
K04
M06
L06
N05
N04
M02
M05
L04
99
101
103
106
108
111
114
116
135
134
47
N03
K05
L05
M04
J04
BVD1(STSCHG/RI)
BVD2(SPKR)
C/BE0
C/BE1
C/BE2
C/BE3
CD1
H01
H03
H02
G02
G04
F01
C03
F03
E02
F04
B01
D02
E04
D03
E03
C07
D07
B07
D10
B12
C08
C09
A12
E11
37
26
13
A01
L13
75
CD2
138
88
B05
H13
G13
H10
K02
A04
C04
A03
K11
K12
J13
CE1
CE2
90
10
9
CLK_48_RSVD
DEVSEL
D0
85
30
R02
F09
B08
F08
L15
K18
K15
J19
J17
E09
C08
E08
L14
K17
K14
J18
J14
7
139
141
143
76
6
D1
5
D2
4
D3
3
J05
D4
78
129
128
127
123
121
120
118
115
98
96
89
F11
D5
81
A1
E11
C11
A12
C12
E12
C13
E13
G15
F19
H18
D6
83
J10
A2
D7
86
H12
C05
B04
B03
M12
J11
A3
D8
140
142
144
77
A4
D9
A5
D10
A6
D11
A7
D12
79
A8
D13
82
K13
J12
A9
F11
D14
84
A10
G11
D15
87
H11
2−13
Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically to Device Terminals (Continued)
TERMINAL
GGU
J01
TERMINAL
GGU
A08
SIGNAL NAME
FRAME
SIGNAL NAME
PGE
27
2
GVF
N05
J01
PGE
124
1
GVF
B11
REG
REQ
GNT
C01
L11
C02
D08
M08
L02
J02
GRST
66
14
122
94
95
28
58
59
63
64
67
68
69
91
35
20
33
19
131
H02
L05
B12
G18
G17
P03
F05
G06
F03
F02
G05
F01
H06
H14
W04
H01
R03
H03
C10
RESET
RI_OUT/PME
SERR
119
57
B13
J03
IDSEL
F02
INPACK
IORD
B08
F12
34
T01
SPKROUT
STOP
61
M09
L01
E02
P05
G03
P06
E06
B05
A04
C05
H05
G02, L18
B10
F12
IOWR
C11
31
IRDY
K01
K07
N09
L09
SUSPEND
TRDY
65
N10
J03
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
OE
29
VCCD0
VCCD1
VPPD0
VPPD1
VR_EN
VR_PORT
VS1
73
N13
L12
74
K10
M10
N12
L10
71
K09
72
M11
D04
L08
125
62
G10
N01
G01
K03
G03
A06
130
117
133
105
136
B02
PAR
VS2
A09
PCLK
WAIT
B06
E10
D19
B09
PERR
WE
D13
A05
PRST
WP(IOIS16)
READY(IREQ)
2−14
2.2 Terminal Descriptions
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 2−6. Power Supply Terminals
TERMINAL
NUMBER
GGU
I/O
DESCRIPTION
NAME
PGE
GVF
A07, A10, A15,
E01, G19, K01,
K19, N01, P19,
W06
8, 21, 40,
60, 80, 93, F13, H04, K08,
112, 132 M13, N02
A02, A11, D01,
GND
Device ground terminals
A05, A08, A13,
E19, G01, H19,
L19, M01, R01,
W08
12, 32, 54, A07, C13, D05,
V
CC
70, 104,
126, 137
E01, M01, N07,
N11
Power supply terminals for I/O and internal voltage regulator
Clamp voltage for PC Card interface. Matches card signaling
environment, 5 V or 3.3 V
V
V
109
B11
A11, G14
CCCB
36
L03
D04
L01, W05
H05
Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
Internal voltage regulator enable. Active-low
CCP
VR_EN
125
I
Internal voltage regulator input/output. When VR_EN is low, the
regulator is enabled and this terminal is an output. An external
bypass capacitor is required on this terminal. When VR_EN is high,
the regulator is disabled and this terminal is an input for an external
2.5-V core power source.
VR_PORT
62
L08
G02, L18
Table 2−7. PC Card Power Switch Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
GGU
GVF
VCCD0
VCCD1
73
74
N13
L12
E06
B05
O
O
Logic controls to the TPS2211A PC Card power interface switch to control AVCC
Logic controls to the TPS2211A PC Card power interface switch to control AVPP
VPPD0
VPPD1
71
72
K09
M11
A04
C05
2−15
Table 2−8. PCI System Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
GGU
GVF
Global reset. When the global reset is asserted, the GRST signal causes the controller to
place all output buffers in a high-impedance state and reset all internal registers. When GRST
is asserted, the device is completely in its default state. For systems that require wake-up
from D3, GRST normally is asserted only during initial boot. PRST must be asserted following
initial boot so that PME context is retained during the transition from D3 to D0.
GRST
66
L11
H02
I
When the SUSPEND mode is enabled, the device is protected from GRST, and the internal
registers are preserved. All outputs are placed in a high-impedance state.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are
sampled at the rising edge of PCLK.
PCLK
PRST
20
19
G01
G03
H01
H03
I
I
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to place all
output buffers in a high-impedance state and reset internal registers. When PRST is asserted,
the device can generate the PME signal only if it is enabled. After PRST is deasserted, the
controller is in a default state.
When the SUSPEND mode is enabled, the device is protected from PRST, and the internal
registers are preserved. All outputs are placed in a high-impedance state.
2−16
Table 2−9. PCI Address and Data Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
3
GGU
E03
D03
E04
D02
B01
F04
E02
F03
C03
F01
G04
G02
H02
H03
H01
J04
GVF
J05
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
4
J06
5
K02
K03
K05
K06
L02
L03
M02
M03
M06
M05
N02
N03
N06
P01
R06
P07
V05
U06
V06
R04
P08
U07
W07
R08
U08
V08
W09
V09
U09
R09
6
7
9
10
11
15
16
17
18
22
23
24
25
38
39
41
42
43
44
45
46
48
49
50
51
52
53
55
56
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary-bus PCI cycle, AD31–AD0 contain a
32-bit address or other destination information. During the data phase, AD31–AD0 contain data.
I/O
M04
L05
K05
N03
L04
M05
M02
N04
N05
L06
M06
K04
N06
L07
M07
N08
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a primary-bus PCI cycle, C/BE3–C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable
determines which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to
byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2
(AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).
C/BE3
C/BE2
C/BE1
C/BE0
13
26
37
47
A01
J02
L06
P02
U05
V07
I/O
I/O
M03
K06
PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across
the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the controller outputs
this parity indicator with a one-PCLK delay. As a target during PCI cycles, the controller
compares its calculated parity to the parity indicator of the initiator. A compare error results in the
assertion of a parity error (PERR).
PAR
35
N01
W04
2−17
Table 2−10. PCI Interface Control Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
GGU
GVF
PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device.
As a PCI initiator on the bus, the controller monitors DEVSEL until a target responds. If no
target responds before timeout occurs, then the controller terminates the cycle with an initiator
abort.
DEVSEL
30
K02
R02
I/O
I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When FRAME is deasserted, the PCI bus transaction is in the final data phase.
FRAME
27
J01
N05
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the controller access to the PCI
bus after the current data transaction has completed. GNT may or may not follow a PCI bus
request, depending on the PCI bus parking algorithm.
GNT
2
C01
F02
J01
L05
I
I
Initialization device select. IDSEL selects the controller during configuration space accesses.
IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
IDSEL
14
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current
data phase of the transaction. A data phase is completed on a rising edge of PCLK where both
IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states
are inserted.
IRDY
28
K01
P03
I/O
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity
does not match PAR when PERR is enabled through bit 6 of the command register (PCI offset
04h, see Section 4.4).
PERR
REQ
33
1
K03
C02
R03
J02
I/O
O
PCI bus request. REQ is asserted by the controller to request access to the PCI bus as an
initiator.
PCI system error. SERR is an output that is pulsed from the controller when enabled through
bit 8 of the command register (PCI offset 04h, see Section 4.4) indicating a system error has
occurred. The controller need not be the target of the PCI cycle to assert this signal. When
SERR is enabled in the command register, this signal also pulses, indicating that an address
parity error has occurred on a CardBus interface.
SERR
34
L02
T01
O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current
PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
STOP
TRDY
31
29
L01
J03
P05
P06
I/O
I/O
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current
data phase of the transaction. A data phase is completed on a rising edge of PCLK when both
IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are
inserted.
2−18
Table 2−11. Multifunction and Miscellaneous Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
GGU
GVF
No connect. These terminals have no connection anywhere within the package.
Terminals H10 on the GGU package and 85 on the PGE package will be used as a
48-MHz clock input on future-generation devices.
CLK_48_RSVD
85
H10
—
Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA,
GPI0, GPO0, socket activity LED output, ZV switching output, CardBus audio PWM,
GPE, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for
configuration details.
MFUNC0
58
59
K07
N09
F05
G06
I/O
I/O
Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity
LED output, D3_STAT, ZV switching output, CardBus audio PWM, GPE, or a parallel
IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
Serial data (SDA). When VCCD0 and VCCD1 are detected high after a global reset, the
MFUNC1 terminal provides the SDA signaling for the serial bus interface. The
two-terminal serial interface loads the subsystem identification and other register
defaults from an EEPROM after a global reset. See Section 3.6.1, Serial Bus Interface
Implementation, for details on other serial bus applications.
MFUNC1
MFUNC2
Multifunction terminal 2. MFUNC2 can be configured as GPI2, GPO2, socket activity
LED output, ZV switching output, CardBus audio PWM, GPE, RI_OUT, D3_STAT, or a
parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
63
64
L09
K10
F03
F02
I/O
I/O
Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized
interrupt signal IRQSER. This terminal is IRQSER by default. See Section 4.30,
Multifunction Routing Register, for configuration details.
MFUNC3/
IRQSER
Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket
activity LED output, ZV switching output, CardBus audio PWM, GPE, D3_STAT,
RI_OUT, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for
configuration details.
MFUNC4
MFUNC5
67
68
M10
N12
G05
F01
I/O
I/O
Serial clock (SCL). When VCCD0 and VCCD1 are detected high after a global reset, the
MFUNC4 terminal provides the SCL signaling for the serial bus interface. The
two-terminal serial interface loads the subsystem identification and other register
defaults from an EEPROM after a global reset. See Section 3.6.1, Serial Bus Interface
Implementation, for details on other serial bus applications.
Multifunction terminal 5. MFUNC5 can be configured as GPI4, GPO4, socket activity
LED output, ZV switching output, CardBus audio PWM, D3_STAT, GPE, or a parallel
IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
MFUNC6/
CLKRUN
Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel
IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
69
57
L10
H06
J03
I/O
O
Ring indicate out and power management event output. Terminal provides an output for
ring- indicate or PME signals.
RI_OUT / PME
SPKROUT
M08
Speaker output. SPKROUT is the output to the host system that can carry SPKR or
CAUDIO through the controller from the PC Card interface. SPKROUT is driven as the
exclusive-OR combination of card SPKR//CAUDIO inputs.
61
65
M09
N10
E02
G03
O
I
Suspend. SUSPEND protects the internal registers from clearing when the GRST or
PRST signal is asserted. See Section 3.8.5, Suspend Mode, for details.
SUSPEND
2−19
Table 2−12. 16-Bit PC Card Address and Data Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
116
114
111
108
106
103
101
99
GGU
B09
B10
A10
C12
D11
E10
A13
E13
F10
B13
C10
D12
E12
D09
G12
G11
F11
E11
A12
C09
C08
B12
D10
B07
D07
C07
H11
J12
GVF
A14
B14
B15
E14
A16
E17
E18
F17
F18
C15
F13
F15
F14
C14
H15
H18
F19
G15
E13
C13
E12
C12
A12
C11
E11
F11
J14
J18
K14
K17
L14
E08
C08
E09
J17
J19
K15
K18
L15
F08
B08
F09
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
97
107
110
102
100
113
92
O
PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.
89
96
A8
98
A7
115
118
120
121
123
127
128
129
87
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
84
82
K13
J11
79
77
M12
B03
B04
C05
H12
J10
144
142
140
86
D8
I/O
PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.
D7
D6
83
D5
81
J13
D4
78
K12
K11
A03
C04
A04
D3
76
D2
143
141
139
D1
D0
2−20
Table 2−13. 16-Bit PC Card Interface Control Terminals
TERMINAL
NUMBER
PGE GGU GVF
I/O
DESCRIPTION
NAME
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include
batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is
low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the
battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6,
ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,
ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
BVD1
(STSCHG/RI)
135
C06
A09
I
Status change. STSCHG is used to alert the system to a change in the READY, write protect,
or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include
batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is
low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the
battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6,
ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,
ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
BVD2(SPKR)
134
D06
F10
I
Speaker. SPKR is an optional binary audio signal available only when the card and socket
have been configured for the 16-bit I/O interface.
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC
Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal
status, see Section 5.2, ExCA Interface Status Register.
CD1
CD2
75
L13
B05
L17
C09
I
138
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address
bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered
address bytes.
CE1
CE2
88
90
H13
J15
O
G13 H17
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read
cycle at the current address.
INPACK
IORD
IOWR
OE
122
94
B08
F12
C11
B12
G18
G17
I
I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data output during
host I/O read cycles.
O
O
O
I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O PC Cards
during host I/O write cycles.
95
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data
output during host memory read cycles.
91
G10 H14
Ready. The ready function is provided by READY when the 16-bit PC Card and the host
socket are configured for the memory-only interface. READY is driven low by the 16-bit
memory PC Cards to indicate that the memory card circuits are busy processing a previous
write command. READY is driven high when the 16-bit memory PC Card is ready to accept a
new data transfer command.
READY
(IREQ)
131
A06
C10
I
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a
device on the 16-bit I/O PC Card requires service by the host software. IREQ is high
(deasserted) when no interrupt is requested.
Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE or WE active) and to the I/O space
(IORD or IOWR active). Attribute memory is a separately accessed section of card memory
and is generally used to record card capacity and other configuration and attribute
information.
REG
124
119
A08
D08
B11
B13
O
O
RESET
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
2−21
Table 2−13. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
NUMBER
PGE GGU GVF
I/O
DESCRIPTION
NAME
VS1
130
117
B02
A09
B10
F12
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
determine the operating voltage of the PC Card.
I/O
VS2
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or
I/O in progress.
WAIT
133
105
B06
D13
E10
D19
I
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also
used for memory PC Cards that employ programmable memory technologies.
WE
O
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16)
function.
WP
(IOIS16)
136
A05
B09
I
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card
when the address on the bus corresponds to an address to which the 16-bit PC Card responds,
and the I/O port that is addressed is capable of 16-bit accesses.
Table 2−14. CardBus PC Card Interface System Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
GGU
GVF
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus
interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1,
CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are
defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but
it can be stopped in the low state or slowed down for power savings.
CCLK
107
B13
C15
O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the
CCLK frequency, and by the controller to indicate that the CCLK frequency is going to be
decreased.
CCLKRUN
CRST
136
119
A05
D08
B09
B13
I/O
O
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals
to a known state. When CRST is asserted, all CardBus PC Card signals are placed in a
high-impedance state, and the controller drives these signals to a valid logic level. Assertion
can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.
2−22
Table 2−15. CardBus PC Card Address and Data Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
144
142
141
140
139
129
128
127
123
121
120
118
116
115
114
97
GGU
B03
B04
C04
C05
A04
C07
D07
B07
D10
B12
C08
C09
B09
A12
B10
F10
C11
F11
F12
G12
G10
G13
G11
H11
H12
K13
J10
GVF
E08
C08
B08
E09
F09
F11
E11
C11
A12
C12
E12
C13
A14
E13
B14
F18
G17
F19
G18
H15
H14
H17
H18
J14
J17
K14
J19
K17
K15
L14
K18
L15
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CardBus address and data. These signals make up the multiplexed CardBus address and data
bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0
contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain
data. CAD31 is the most significant bit.
I/O
95
96
94
92
91
90
89
CAD8
87
CAD7
86
CAD6
82
CAD5
83
CAD4
79
J11
CAD3
81
J13
CAD2
77
M12
K12
K11
CAD1
78
CAD0
76
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same
CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 define the
bus command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable
determines which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies
to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2
(CAD23–CAD16), and CC/BE3 applies to byte (CAD31–CAD24).
CC/BE3
CC/BE2
CC/BE1
CC/BE0
124
113
98
A08
D09
E11
H13
B11
C14
G15
J15
I/O
I/O
88
CardBus parity. In all CardBus read and write cycles, the controller calculates even parity
across the CAD and CC/BE buses. As an initiator during CardBus cycles, the controller outputs
CPAR with a one-CCLK delay. As a target during CardBus cycles, the controller compares its
calculated parity to the parity indicator of the initiator; a compare error results in a parity error
assertion.
CPAR
100
E12
F14
2−23
Table 2−16. CardBus PC Card Interface Control Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
PGE
134
101
GGU
D06
A13
GVF
F10
E18
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The
controller supports the binary audio mode and outputs a binary signal from the card to
SPKROUT.
CAUDIO
CBLOCK
I
I/O CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with
CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating
voltage and card type.
CCD1
CCD2
75
L13
B05
L17
C09
I
138
CardBus device select. The controller asserts CDEVSEL to claim a CardBus cycle as the
target device. As a CardBus initiator on the bus, the controller monitors CDEVSEL until a
target responds. If no target responds before timeout occurs, then the controller terminates
the cycle with an initiator abort.
CDEVSEL
CFRAME
106
111
D11
A10
A16
B15
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME
is asserted to indicate that a bus transaction is beginning, and data transfers continue while
this signal is asserted.
I/O
When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
CardBus bus grant. CGNT is driven by the controller to grant a CardBus PC Card access to
the CardBus bus after the current data transaction has been completed.
CGNT
CINT
105
131
D13
A06
D19
C10
O
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt
servicing from the host.
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK
when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled
asserted, wait states are inserted.
CIRDY
110
C10
F13
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except
CPERR
CREQ
102
122
D12
B08
F15
B12
I/O during special cycles. It is driven low by a target two clocks following the data cycle during
which a parity error is detected.
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of
I
the CardBus bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system errors that
could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but
deasserted by a weak pullup; deassertion may take several CCLK periods. The controller
CSERR
133
B06
E10
I
can report CSERR to the system by assertion of SERR on the PCI interface.
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the
I/O current CardBus transaction. CSTOP is used for target disconnects, and is commonly
asserted by target devices that do not support burst data transfers.
CSTOP
103
135
108
E10
C06
C12
E17
A09
E14
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is
used as a wake-up mechanism.
CSTSCHG
CTRDY
I
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the
I/O current data phase of the transaction. A data phase is completed on a rising edge of CCLK,
when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in
I/O conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to
determine the operating voltage and card type.
CVS1
CVS2
130
117
B02
A09
B10
F12
2−24
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI1510 controller. Figure 3−1 shows a simplified block diagram of
the controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface
includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface
terminals include multifunction terminals: SUSPEND, RI_OUT/PME (power-management control signal), and
SPKROUT.
PCI Bus
INTA
Interrupt
Activity LED
Controller
TPS2211A
Power
Switch
PCI950
IRQSER
Deserializer
IRQSER
3
PCI1510
IRQ2−15
4
PC Card
Socket
68
Zoomed Video
19
VGA
Controller
23
Multiplexer
Zoomed Video
4
Audio
Subsystem
External ZV Port
NOTE: The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In ZV mode, 23 terminals are used for routing the ZV signals
to the VGA controller and audio subsystem.
Figure 3−1. PCI1510 Simplified Block Diagram
3.1 Power Supply Sequencing
The controller contains 3.3-V I/O buffers with 5-V tolerance requiring an I/O power supply and an LDO-VR power
supply for core logic. The core power supply, which is always 2.5 V, can be supplied through the VR_PORT terminal
(when VR_EN is high) or from the integrated LDO-VR. The LDO-VR needs a 3.3-V power supply via the V
CC
terminals. The clamping voltages (V
and V
) can be either 3.3 V or 5 V, depending on the interface. The
CCCB
CCP
following power-up and power-down sequences are recommended.
The power-up sequence is:
1. Assert GRST to the device to disable the outputs during power up. Output drivers must be powered up in
the high-impedance state to prevent high current levels through the clamp diodes to the 5-V clamping rails
(V
and V
).
CCCB
CCP
2. Apply 3.3-V power to V
.
CC
3. Apply the clamp voltage.
The power-down sequence is:
1. Assert GRST to the device to disable the outputs during power down. Output drivers must be powered down
in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V clamping
rails (V
and V
).
CCCB
CCP
3−1
2. Remove the clamp voltage.
3. Remove the 3.3-V power from V
.
CC
NOTE: The clamp voltage can be ramped up or ramped down along with the 3.3-V power. The
voltage difference between V and the clamp voltage must remain within 3.6 V.
CC
3.2 I/O Characteristics
Figure 3−2 shows a 3-state bidirectional buffer. Section 7.2, Recommended Operating Conditions, provides the
electrical characteristics of the inputs and outputs.
NOTE: The controller meets the ac specifications of the PC Card Standard and PCI Local Bus
Specification.
V
CCP
Tied for Open Drain
OE
Pad
Figure 3−2. 3-State Bidirectional Buffer
NOTE: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the controller is interfaced with, 3.3 V or 5 V.
The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals.
The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can
be either 3.3 V or 5 V, and the controller must reliably accommodate both voltage levels. This is accomplished by
using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires
a 5-V PCI bus, then V
can be connected to a 5-V power supply.
CCP
The controller requires three separate clamping voltages because it supports a wide range of features. The three
voltages are listed and defined in Section 7.2, Recommended Operating Conditions. GRST, SUSPEND, PME, and
CSTSCHG are not clamped to any of them.
3.4 Peripheral Component Interconnect (PCI) Interface
The controller is fully compliant with the PCI Local Bus Specification. The controller provides all required signals for
PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the V
CCP
terminal to the desired voltage level. In addition to the mandatory PCI signals, the controller provides the optional
interrupt signal INTA.
3.4.1 PCI GRST Signal
During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100 µs after PCLK
is stable. PRST can be deasserted at the same time as GRST or any time thereafter.
3−2
3.4.2 PCI Bus Lock (LOCK)
The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on
the controller as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal by
setting the appropriate values in bits 19−16 of the multifunction routing register. See Section 4.30, Multifunction
Routing Register, for details. Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the
downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible
for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus
signal for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter does not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A
complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete
bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked
operation is in progress.
The controller supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus
bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential
deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target
supports delayed transactions and blocks access to the target until it completes a delayed read. This target
characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using
LOCK.
3.4.3 Loading Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see
Section 4.27) make up a doubleword of PCI configuration space for function 0. This doubleword register is used for
system and option card (mobile dock) identification purposes and is required by some operating systems.
Implementation of this unique identifier register is a PC 99/PC 2001 requirement.
The controller offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism
relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers
is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system control register (PCI offset 80h,
see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem identification value into the registers at
PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem
ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically
erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier via a serial EEPROM. The controller loads the data from the serial EEPROM
after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire core, including the
serial-bus state machine (see Section 3.8.5, Suspend Mode, for details on using SUSPEND).
The controller provides a two-line serial-bus host controller that can interface to a serial EEPROM. See Section 3.6,
Serial-Bus Interface, for details on the two-wire serial-bus controller and applications.
3−3
3.5 PC Card Applications
This section describes the PC Card interfaces of the controller.
•
•
•
•
•
Card insertion/removal and recognition
Zoomed video support
Speaker and audio applications
LED socket activity indicators
CardBus socket registers
3.5.1 PC Card Insertion/Removal and Recognition
The PC Card Standard (release 7.2) addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the
card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the PC Card
Standard (release 7.2) and in Table 3−1.
Table 3−1. PC Card Card-Detect and Voltage-Sense Connections
CD2//CCD2
Ground
CD1//CCD1
Ground
VS2//CVS2
Open
VS1//CVS1
Open
KEY
5 V
5 V
5 V
LV
INTERFACE
16-bit PC Card
VOLTAGE
5 V
Ground
Ground
Open
Ground
16-bit PC Card
5 V and 3.3 V
5 V, 3.3 V, and X.X V
3.3 V
Ground
Ground
Ground
Ground
16-bit PC Card
Ground
Ground
Open
Ground
16-bit PC Card
Ground
Connect to CVS1
Ground
Open
Connect to CCD1
Ground
LV
CardBus PC Card
16-bit PC Card
3.3 V
Ground
Ground
LV
3.3 V and X.X V
3.3 V and X.X V
3.3 V, X.X V, and Y.Y V
X.X V
Connect to CVS2
Connect to CVS1
Ground
Ground
Connect to CCD2
Ground
Ground
LV
CardBus PC Card
CardBus PC Card
16-bit PC Card
Ground
Connect to CCD2
Open
LV
Ground
Ground
LV
Connect to CVS2
Ground
Ground
Connect to CCD2
Connect to CCD1
Open
Open
LV
CardBus PC Card
CardBus PC Card
CardBus PC Card
X.X V
Connect to CVS2
Ground
Open
LV
X.X V and Y.Y V
Y.Y V
Connect to CVS1
Ground
Connect to CCD2
Connect to CCD1
Ground
LV
Connect to CVS1
Connect to CVS2
Ground
Reserved
Reserved
Ground
Connect to CCD1
3.5.2 Parallel Power-Switch Interface (TPS2211A)
The controller provides a parallel interface for control of the PC Card power switch. The VCCD and VPPD terminals
are used with the TI TPS2211A single-slot PC Card power-switch interface to provide power-switch support.
Figure 3−3 illustrates a typical application, where the controller represents the PC Card controller.
3−4
Power Supply
TPS2211A
12 V
5 V
12V
5V
3.3 V
3.3V
AVPP
AVCC
V
V
V
V
PP1
PP2
CC
SHDN
SHDN
Supervisor
PC Card
CC
VCCD0
VCCD1
VPPD0
VPPD1
PCI1510
(PC Card
Controller)
Figure 3−3. TPS2211A Typical Application
3.5.3 Zoomed Video Support
The controller allows for the implementation of zoomed video (ZV) for PC Cards. Zoomed video is supported by
setting bit 6 (ZVENABLE) in the card control register (PCI offset 91h, see Section 4.32). Setting this bit puts 16-bit
PC Card address lines A25−A4 of the PC Card interface in the high-impedance state. These lines can then transfer
video and audio data directly to the appropriate controller. Card address lines A3−A0 can still access PC Card CIS
registers for PC Card configuration. Figure 3−4 illustrates a ZV implementation.
Speakers
CRT
Motherboard
PCI Bus
VGA
Controller
Audio
Codec
Zoomed Video
Port
PCM
Audio
Input
PC Card
19
19
4
Video
Audio
4
PC Card
Interface
PCI1510
Figure 3−4. Zoomed Video Implementation Using the PCI1510 Controller
Not shown in Figure 3−4 is the multiplexing scheme used to route a socket ZV source to the graphics controller. The
controller provides ZVSTAT and ZVSEL0 signals on the multifunction terminals to switch external bus drivers.
Figure 3−5 shows an implementation for switching between two ZV streams using external logic.
3−5
PCI1510
ZVSTAT
ZVSEL0
Figure 3−5. Zoomed Video Switching Application
Figure 3−5 illustrates an implementation using standard three-state bus drivers with active-low output enables.
ZVSEL0 is an active-low output indicating that the socket ZV mode is enabled.
3.5.4 Standardized Zoomed-Video Register Model
The standardized zoomed-video register model is defined for the purpose of standardizing the ZV port control for PC
Card controllers across the industry. The following list summarizes the standardized zoomed-video register model
changes to the existing PC Card register set.
•
•
•
Socket present state register (CardBus socket address + 08h, see Section 6.3)
Bit 27 (ZVSUPPORT) has been added. The platform BIOS can set this bit via the socket force event register
(CardBus socket address + 0Ch, see Section 6.4) to define whether zoomed video is supported on the
socket by the platform.
Socket force event register (CardBus socket address + 0Ch, see Section 6.4)
Bit 27 (FZVSUPPORT) has been added. The platform BIOS can use this bit to set the ZVSUPPORT bit in
the socket present state register (CardBus socket address + 08h, see Section 6.3) to define whether
zoomed video is supported on the socket by the platform.
Socket control register (CardBus socket address +10h, see Section 6.5)
Bit 11 (ZV_ACTIVITY) has been added. This bit is set when zoomed video is enabled for the PC Card socket.
Bit 10 (STDZVREG) has been added. This bit defines whether the PC Card controller supports the
standardized zoomed-video register model.
Bit 9 (ZVEN) is provided for software to enable or disable zoomed video.
If the STDZVEN bit (bit 0) in the diagnostic register (PCI offset 93h, see Section 4.34) is 1b, then the standardized
zoomed video register model is disabled. For backward compatibility, even if the STDZVEN bit is 0b (enabled), the
controller allows software to access zoomed video through the legacy address in the card control register (PCI offset
91h, see Section 4.32), or through the new register model in the socket control register (CardBus socket address +
10h, see Section 6.5).
3.5.4.1 Zoomed-Video Card Insertion and Configuration Procedure
1. A zoomed-video PC Card is inserted into an empty slot.
2. The card is detected and interrogated appropriately.
3−6
There are two types of PC Card controllers to consider.
•
Legacy controller not using the standardized ZV register model
Software reads bit 10 (STDZVREG) of the socket control register (CardBus socket address + 10h) to
determine if the standardized zoomed-video register model is supported. If the bit returns 0b, then software
must use legacy code to enable zoomed video.
•
Newer controller that uses the standardized ZV register model
Software reads bit 10 (STDZVREG) of the socket control register (CardBus socket address + 10h) to
determine if the standardized zoomed-video register model is supported. If the bit returns 1b, then software
can use the process/register model detailed in Table 3−2 to enable zoomed video.
Table 3−2. Zoomed-Video Card Interrogation
ZVSUPPORT
ZV_ACTIVITY
ACTION
1
0
Set ZVEN to enable zoomed video.
Display a user message such as, The zoomed video protocol required by this PC Card application is al-
ready in use by another card.
1
0
1
Display a user message such as, This platform does not support the zoomed-video protocol required by
this PC Card application.
X
3.5.5 Internal Ring Oscillator
The internal ring oscillator provides an internal clock source for the controller so that neither the PCI clock nor an
external clock is required in order for the controller to power down a socket or interrogate a PC Card. This internal
oscillator can be enabled by setting bit 27 (P2CCLK) of the system control register (PCI offset 80h, see Section 4.29)
to 1b. This function is enabled by default.
3.5.6 Integrated Pullup Resistors
The PC Card Standard (release 7.2) requires pullup resistors on various terminals to support both CardBus and 16-bit
card configurations. Unlike the PCI12XX, PCI1450, and PCI4450 controllers which required external pullup resistors,
the PCI1510 controller has integrated all of these pullup resistors. The I/O buffer on the BVD1(STSCHG)//CSTSCHG
terminal has the capability to switch either pullup or pulldown. The pullup resistor is turned on when a 16-bit PC Card
is inserted, and the pulldown resistor is turned on when a CardBus PC Card is inserted. This prevents unexpected
CSTSCHG signal assertion. The integrated pullup resistors are listed in Table 3−3.
Table 3−3. Integrated Pullup Resistors
TERMINAL NUMBER
TERMINAL NUMBER
SIGNAL NAME
SIGNAL NAME
PGE
GGU
D12
C10
A13
E10
D11
C12
C06
D06
L13
GVF
PGE
GGU
B05
B08
A06
D08
B02
A09
B06
A05
GVF
A14/CPERR
A15/CIRDY
102
110
101
103
106
108
135
134
75
F15
F13
E18
E17
A16
E14
A09
F10
L17
CD2/CCD2
INPACK/CREQ
READY/CINT
RESET/CRST
VS1/CVS1
138
122
131
119
130
117
133
136
C09
B12
C10
B13
B10
F12
E10
B09
A19/CBLOCK
A20/CSTOP
A21/CDEVSEL
A22/CTRDY
VS2/CVS2
BVD1(STSCHG)/CSTSCHG
BVD2(SPKR)/CAUDIO
CD1/CCD1
WAIT/CSERR
WP(IOIS16)/CCLKRUN
3−7
3.5.7 SPKROUT and CAUDPWM Usage
SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for
I/O mode, the BVD2 terminal becomes SPKR. This terminal is also used in CardBus binary audio applications, and
is referred to as CAUDIO. SPKR passes a TTL-level digital audio signal to the controller. The CardBus CAUDIO signal
also can pass a single-amplitude binary waveform. The binary audio signal from the PC Card socket is used in the
controller to produce SPKROUT. This output is enabled by bit 1 (SPKROUTEN) in the card control register (PCI offset
91h, see Section 4.32).
Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio chips
may not support both modes on one terminal and may have a separate terminal for binary and PWM. The
implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2
(AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM terminal to
CAUDPWM. See Section 4.30, Multifunction Routing Register, for details on configuring the MFUNC terminals.
Figure 3−6 provides an illustration of a sample application using SPKROUT and CAUDPWM.
System
Core Logic
BINARY_SPKR
SPKROUT
Speaker
Subsystem
PWM_SPKR
PCI1510
CAUDPWM
Figure 3−6. Sample Application of SPKROUT and CAUDPWM
3.5.8 LED Socket Activity Indicators
The socket activity LED is provided to indicate when a PC Card is being accessed. The LED_SKT signal can be routed
to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate
socket activity. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction
terminals.
The active-high LED signal is driven for 64-ms. When the LED is not being driven high, it is driven to a low state. Either
of the two circuits shown in Figure 3−7 can be implemented to provide LED signaling, and the board designer must
implement the circuit that best fits the application.
The LED activity signal is valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity
signal is pulsed when READY/IREQ is low. For CardBus cards, the LED activity signal is pulsed if CFRAME, IRDY,
or CREQ are active.
3−8
Current Limiting
R ≈ 500 Ω
LED
PCI1510
Current Limiting
R ≈ 500 Ω
Application-
Specific Delay
LED
PCI1510
Figure 3−7. Two Sample LED Circuits
As indicated, the LED signal is driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven.
3.5.9 CardBus Socket Registers
The controller contains all registers for compatibility with the PC Card Standard. These registers exist as the CardBus
socket registers and are listed in Table 3−4.
Table 3−4. CardBus Socket Registers
REGISTER NAME
OFFSET
00h
Socket event
Socket mask
04h
Socket present state
Socket force event
Socket control
08h
0Ch
10h
Reserved
14h−1Ch
20h
Socket power management
3.6 Serial-Bus Interface
The controller provides a serial-bus interface to load subsystem identification information and selected register
defaults from a serial EEPROM, and to provide a PC Card power-switch interface alternative. The serial-bus interface
2
is compatible with various I C and SMBus components.
3.6.1 Serial-Bus Interface Implementation
To enable the serial interface, a pullup resistor must be implemented on the VCCD0 and VCCD1 terminals and the
appropriate pullup resistors must be implemented on the SDA and SCL signals, that is, the MFUNC1 and MFUNC4
terminals. When the interface is detected, bit 3 (SBDETECT) in the serial bus control and status register (PCI offset
B3h, see Section 4.48) is set. The SBDETECT bit is cleared by a writeback of 1b.
The controller implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). When
pullup resistors are provided on the VCCD0 and VCCD1 terminals, the SCL signal is mapped to the MFUNC4 terminal
and the SDA signal is mapped to the MFUNC1 terminal. The controller drives SCL at nearly 100 kHz during data
3−9
2
transfers, which is the maximum specified frequency for standard-mode I C. The serial EEPROM must be located
at address A0h. Figure 3−8 illustrates an example application implementing the two-wire serial bus.
V
CC
Serial
EEPROM
5 V
PCI1510
VCCD0
VCCD1
A2
A1
A0
MFUNC4
MFUNC1
SCL
SDA
Figure 3−8. Serial EEPROM Application
Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other
devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches
are discussed in the sections that follow.
3.6.2 Serial-Bus Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−8.
2
The controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode I C using 7-bit
addressing.
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to low state while SCL is in the high state, as illustrated
in Figure 3−9. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high
transition of SDA while SCL is in the high state, as shown in Figure 3−9. Data on SDA must remain stable during the
high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control
signals, that is, a start or a stop condition.
SDA
SCL
Start
Stop
Change of
Condition
Condition
Data Allowed
Data Line Stable,
Data Valid
Figure 3−9. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−10
illustrates the acknowledge protocol.
3−10
SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3−10. Serial-Bus Protocol Acknowledge
The controller is a serial bus master; all other devices connected to the serial bus external to the controller are slave
devices. As the bus master, the controller drives the SCL clock at nearly 100 kHz during bus cycles and places SCL
in a high-impedance state (zero frequency) during idle states.
Typically, the controller masters byte reads and byte writes under software control. Doubleword reads are performed
by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See
Section 3.6.3, Serial-Bus EEPROM Application, for details on how the controller automatically loads the subsystem
identification and other register defaults through a serial-bus EEPROM.
Figure 3−11 illustrates a byte write. The controller issues a start condition and sends the 7-bit slave device address
and the command bit zero. A 0b in the R/W command bit indicates that the data transfer is a write. The slave device
acknowledges if it recognizes the address. If no acknowledgment is received by the controller, then an appropriate
status bit is set in the serial-bus control and status register (PCI offset B3h, see Section 4.48). The word address byte
is then sent by the controller, and another slave acknowledgment is expected. Then the controller delivers the data
byte MSB first and expects a final acknowledgment before issuing the stop condition.
Slave Address
Word Address
Data Byte
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
P
R/W
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3−11. Serial-Bus Protocol − Byte Write
Figure 3−12 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command
bit must be set to 1b to indicate a read-data transfer. In addition, the master must acknowledge reception of the read
bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL
signal remains driven by the master.
Slave Address
Word Address
Slave Address
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
b6 b5 b4 b3 b2 b1 b0
1
A
Start
R/W
Restart
R/W
Data Byte
b7 b6 b5 b4 b3 b2 b1 b0
M
P
Stop
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3−12. Serial-Bus Protocol − Byte Read
Figure 3−13 illustrates EEPROM interface doubleword data collection protocol.
3−11
Slave Address
Word Address
Slave Address
S
1
0
1
0
0
0
0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
1
0
1
0
0
0
0
1
A
Start
R/W
Restart
R/W
Data Byte 3
M
Data Byte 2
M
Data Byte 1
M
Data Byte 0
M
P
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3−13. EEPROM Interface Doubleword Data Collection
3.6.3 Serial-Bus EEPROM Application
When the PCI bus is reset and the serial-bus interface is detected, the controller attempts to read the subsystem
identification and other register defaults from a serial EEPROM. The registers and corresponding bits that can be
loaded with defaults through the EEPROM are provided in Table 3−5.
Table 3−5. Register- and Bit-Loading Map
EEPROM OFFSET REGISTER OFFSET
REGISTER BITS LOADED FROM EEPROM
01h: Load / FFh: do not load
00h
01h
Flag
PCI 04h
Command register, bit 8, 6−5, 2−0
Note: bits loaded per following:
bit 8 ← bit 7
bit 6 ← bit 6
bit 5 ← bit 5
bit 2 ← bit 2
bit 1 ← bit 1
bit 0 ← bit 0
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
PCI 40h
PCI 40h
PCI 42h
PCI 42h
PCI 44h
PCI 44h
PCI 44h
PCI 44h
PCI 80h
PCI 80h
PCI 80h
PCI 80h
PCI 8Ch
PCI 8Ch
PCI 8Ch
PCI 8Ch
PCI 90h
PCI 91h
PCI 92h
PCI 93h
PCI A2h
ExCA 00h
CB Socket + 0Ch
Subsystem vendor ID bits 7−0 ← bits 7−0
Subsystem vendor ID bits 15−8 ← bits 7−0
Subsystem ID bits 7−0 ← bits 7−0
Subsystem ID bits 15−8 ← bits 7−0
PC Card 16-bit I/F LBAR bits 7−1 ← bits 7−1
PC Card 16-bit I/F LBAR bits 15−8 ← bits 7−0
PC Card 16-bit I/F LBAR bits 23−16 ← bits 7−0
PC Card 16-bit I/F LBAR bits 31−24 ← bits 7−0
System control bits 7−0 ← bits 7−0
System control bits 15−8 ← bits 7−0
System control bits 23−16 ← bits 7−0
System control bits 31−24 ← bits 7−0
Multifunction routing bits 7−0 ← bits 7−0
Multifunction routing bits 15−8 ← bits 7−0
Multifunction routing bits 23−16 ← bits 7−0
Multifunction routing bits 27−24 ← bits 3−0
Retry status bits 7, 6 ← bits 7, 6
Card control bit 7 ← bit 7
Device control bits 6, 3−0 ← bits 6, 3−0
Diagnostic bits 7, 4–0 ← bits 7, 4−0
Power management capabilities bit 15 ← bit 7
ExCA identification and revision bits 7–0 ← bits 7−0
Socket force event, bit 27 ← bit 3
3−12
This format must be followed for the controller to load initializations from a serial EEPROM. All bit fields must be
considered when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the controller. All hardware address bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit (Figure 3−8) assumes the 1010b high-address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
3.6.4 Accessing Serial-Bus Devices Through Software
The controller provides a programming mechanism to control serial bus devices through software. The programming
is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−6 lists the registers used
to program a serial-bus device through software.
Table 3−6. PCI1510 Registers Used to Program Serial-Bus Devices
PCI OFFSET
REGISTER NAME
DESCRIPTION
B0h
Serial-bus data
Contains the data byte to send on write commands or the received data byte on read commands.
The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
B1h
B2h
B3h
Serial-bus index
Serial-bus slave
address
Write transactions to this register initiate a serial-bus transaction. The slave device address and the
R/W command selector are programmed through this register.
Serial-bus control
and status
Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol-select bit is programmed through this register.
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
controller. The controller provides several interrupt signaling schemes to accommodate the needs of a variety of
platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and
industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the
CardBus socket register set provides interrupt control for the CardBus PC Card functions. The controller is, therefore,
backward compatible with existing interrupt control register definitions, and new registers have been defined where
required.
The controller detects PC Card interrupts and events at the PC Card interface and notifies the host controller using
one of several interrupt signaling protocols. To simplify the discussion of interrupts in the controller, PC Card interrupts
are classified either as card status change (CSC) or as functional interrupts.
The method by which any type of interrupt is communicated to the host interrupt controller varies from system to
system. The controller offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type
IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel
PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All
interrupt signaling is provided through the seven multifunction terminals, MFUNC0−MFUNC6.
3.7.1 PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
controller and may warrant notification of host card and socket services software for service. CSC events include both
card insertion and removal from the PC Card socket, as well as transitions of certain PC Card signals.
3−13
Table 3−7 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards
that can be inserted into any PC Card socket are:
•
•
•
16-bit memory card
16-bit I/O card
CardBus cards
Table 3−7. Interrupt Mask and Flag Registers
CARD TYPE
EVENT
MASK
FLAG
Battery conditions (BVD1, BVD2)
Wait states (READY)
ExCA offset 05h/45h/805h bits 1 and 0 ExCA offset 04h/44h/804h bits 1 and 0
16-bit memory
ExCA offset 05h/45h/805h bit 2
ExCA offset 05h/45h/805h bit 0
Always enabled
ExCA offset 04h/44h/804h bit 2
ExCA offset 04h/44h/804h bit 0
PCI configuration offset 91h bit 0
Change in card status (STSCHG)
Interrupt request (IREQ)
16-bit I/O
All 16-bit PC
Cards
Power cycle complete
ExCA offset 05h/45h/805h bit 3
ExCA offset 04h/44h/804h bit 3
Change in card status (CSTSCHG)
Interrupt request (CINT)
Socket mask bit 0
Always enabled
Socket event bit 0
PCI configuration offset 91h bit 0
Socket event bit 3
CardBus
Power cycle complete
Socket mask bit 3
Socket mask bits 2 and 1
Card insertion or removal
Socket event bits 2 and 1
Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the
card type.
Table 3−8. PC Card Interrupt Events and Description
CARD TYPE
EVENT
TYPE
SIGNAL
DESCRIPTION
A transition on BVD1 indicates a change in the
PC Card battery conditions.
BVD1(STSCHG)//CSTSCHG
Battery conditions
(BVD1, BVD2)
CSC
A transition on BVD2 indicates a change in the
PC Card battery conditions.
BVD2(SPKR)//CAUDIO
READY(IREQ)//CINT
16-bit
memory
A transition on READY indicates a change in the
ability of the memory PC Card to accept or provide
data.
Wait states
(READY)
CSC
Change in card
status (STSCHG)
The assertion of STSCHG indicates a status change
on the PC Card.
CSC
Functional
CSC
BVD1(STSCHG)//CSTSCHG
READY(IREQ)//CINT
16-bit I/O
CardBus
Interrupt request
(IREQ)
The assertion of IREQ indicates an interrupt request
from the PC Card.
Change in card
status (CSTSCHG)
The assertion of CSTSCHG indicates a status
change on the PC Card.
BVD1(STSCHG)//CSTSCHG
READY(IREQ)//CINT
Interrupt request
(CINT)
The assertion of CINT indicates an interrupt request
from the PC Card.
Functional
A transition on either CD1//CCD1 or CD2//CCD2
indicates an insertion or removal of a 16-bit or
CardBus PC Card.
Card insertion
or removal
CD1//CCD1,
CD2//CCD2
CSC
CSC
All PC Cards
Power cycle
complete
An interrupt is generated when a PC Card power-up
cycle has completed.
N/A
The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For
example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for
CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in
parentheses. The CardBus signal name follows after a double slash (//).
3−14
The PC Card Standard describes the power-up sequence that must be followed by the controller when an insertion
event occurs and the host requests that the socket V and V be powered. Upon completion of this power-up
CC
PP
sequence, the interrupt scheme can be used to notify the host system (see Table 3−8), denoted by the power cycle
complete event. This interrupt source is considered an internal event, because it depends on the completion of
applying power to the socket rather than on a signal change at the PC Card interface.
3.7.2 Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−8 by setting
the appropriate bits in the controller. By individually masking the interrupt sources listed, software can control those
events that cause an interrupt. Host software has some control over the system interrupt the controller asserts by
programming the appropriate routing registers. The controller allows host software to route PC Card CSC and PC
Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling
method used is discussed in more detail in the following sections.
When an interrupt is signaled by the controller, the interrupt service routine must determine which of the events listed
in Table 3−7 caused the interrupt. Internal registers in the controller provide flags that report the source of an interrupt.
By reading these status bits, the interrupt service routine can determine the action to be taken.
Table 3−7 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Notice that there is not a mask bit to stop the controller from passing PC Card functional interrupts through to the
appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never
be a card interrupt that does not require service after proper initialization.
Table 3−7 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC
Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1b to the
flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by
bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20), and defaults to
the flag-cleared-on-read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1b to the interrupt flag in the socket event
register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software should not program the chip through both register sets when a CardBus card is functioning.
3.7.3 Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6−MFUNC0, implemented in the controller can be routed to obtain a
subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel
ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see
Section 4.33), to select the parallel IRQ signaling scheme. See Section 4.30, Multifunction Routing Register, for
details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement
is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal
for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11,
and IRQ15. The multifunction routing register must be programmed to a value of 0FBA 5432h. This value routes the
MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3−14. Not shown is
that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel
PCI interrupts to the host.
3−15
PCI1510
MFUNC1
PIC
IRQ3
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IRQ4
IRQ5
IRQ10
IRQ11
IRQ15
Figure 3−14. IRQ Implementation
Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration
of a system implementing the controller. See Section 4.30, Multifunction Routing Register, for details on configuring
the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the controller makes available.
3.7.4 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. Socket functional interrupts can be routed to INTA.
3.7.5 Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the controller uses a single terminal to communicate all interrupt
status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple
interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data
describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on
the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
3.7.6 SMI Support in the PCI1510 Controller
The controller provides a mechanism for interrupting the system when power changes have been made to the PC
Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme.
SMI interrupts are generated by the controller, when enabled, after a write cycle to either the socket control register
(CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA offset
02h/42h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−9 describes the SMI control
bits function.
Table 3−9. SMI Control
BIT NAME
SMIROUTE
SMISTAT
FUNCTION
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
This socket dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back 1b.
When set, SMI interrupt generation is enabled.
SMIENB
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt
can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset
1Eh/5Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing register (PCI offset 8Ch, see Section 4.30).
3−16
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the controller, various features are designed into
the device to allow implementation of popular power-saving techniques. These features and techniques are
discussed in this section.
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR)
The controller requires 2.5-V core voltage. The core power can be supplied by the controller itself using the internal
LDO-VR. The core power can alternatively be supplied by an external power supply through the VR_PORT terminal.
Table 3−10 lists the requirements for both the internal core power supply and the external core power supply.
Table 3−10. Requirements for Internal/External 2.5-V Core Power Supply
SUPPLY
V
CC
VR_EN
VR_PORT
NOTE
Internal
3.3 V
GND
2.5-V output
Internal 2.5-V LDO-VR is enabled. A 1.0-µF bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
External
3.3 V
V
CC
2.5-V input
Internal 2.5-V LDO-VR is disabled. An external 2.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1-µF bypass capacitor on the VR_PORT terminal is required.
3.8.2 Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the controller.
CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this
is not always available to the system designer, and alternate power-saving features are provided. For details on the
CLKRUN protocol see the PCI Mobile Design Guide.
The controller does not permit the central resource to stop the PCI clock under any of the following conditions:
•
•
•
•
•
•
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
The 16-bit PC Card- resource manager is busy.
The CardBus master state machine is busy. A cycle may be in progress on CardBus.
The master is busy. There may be posted data from CardBus to PCI in the controller.
Interrupts are pending.
The CardBus CCLK for either socket has not been stopped by the CCLKRUN manager.
The controller restarts the PCI clock using the CLKRUN protocol under any of the following conditions:
•
•
•
•
A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.
A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in either socket.
A CardBus attempts to start the CCLK using CCLKRUN.
A CardBus card arbitrates for the CardBus bus using CREQ.
3.8.3 CardBus PC Card Power Management
The controller implements its own card power-management engine that can turn off the CCLK to a socket when there
is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface
to control this clock management.
3.8.4 16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN
bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) bits are provided for 16-bit
PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The
power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN
bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function
when there is no card activity.
NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3−17
3.8.5 Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the controller. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the controller
in order to minimize power consumption.
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor
an external clock is routed to the serial-interrupt state machine. Figure 3−15 is a signal diagram of the suspend
function.
RESET
GNT
SUSPEND
PCLK
External Terminals
Internal Signals
RESETIN
SUSPENDIN
PCLKIN
Figure 3−15. Signal Diagram of Suspend Function
3.8.6 Requirements for Suspend Mode
The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which
would require the reconfiguration of the controller by software. Asserting the SUSPEND signal places the PCI outputs
of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI
transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the controller
when SUSPEND is asserted, because the outputs are in a high-impedance state.
The GPIOs, MFUNC signals, and RI_OUT signal are all active during SUSPEND, unless they are disabled in the
appropriate registers.
3−18
3.8.7 Ring Indicate
The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode
and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform
requirements. RI_OUT on the controller can be asserted under any of the following conditions:
•
A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an
incoming call.
•
•
A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.
A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery
voltage levels.
Figure 3−16 shows various enable bits for the RI_OUT function; however, it does not show the masking of CSC
events. See Table 3−7 for a detailed description of CSC interrupt masks and flags.
RI_OUT Function
CSTSMASK
RIENB
PC Card
Socket
RINGEN
Card
I/F
RI_OUT
CDRESUME
Figure 3−16. RI_OUT Functional Diagram
RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register
(ExCA offset 03h/43h/803h, see Section 5.4). This is only applicable when a 16-bit card is powered in the socket.
The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit (bit 0, CSTSMASK) is programmed through the socket mask register (CB offset 04h, see Section 6.2) in the
CardBus socket registers.
RI_OUT can be routed through any of three different pins, RI_OUT/PME, MFUNC2, or MFUNC4. The RI_OUT
function is enabled by setting RIENB in the card control register (PCI offset 91h, see Section 4.32). The PME function
is enabled by setting PMEEN in the power management control/status register (PCI offset A4h, see Section 4.38).
When RIMUX in the system control register (PCI offset 80h, see Section 4.29) is set to 0b, both the RI_OUT function
and the PME function are routed to the RI_OUT/PME terminal. If both functions are enabled and RIMUX is set to 0b,
the RI_OUT/PME terminal becomes RI_OUT only and PME assertions will never be seen. Therefore, in a system
using both the RI_OUT function and the PME function, RIMUX must be set to 1b and RI_OUT must be routed to either
MFUNC2 or MFUNC4.
3.8.8 PCI Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure
required to let the operating system control the power of PCI functions. This is done by defining a standard PCI
interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can
be assigned one of seven power-management states, resulting in varying levels of power savings.
The seven power-management states of PCI functions are:
•
•
•
•
D0-uninitialized − Before device configuration, device not fully functional
D0-active − Fully functional state
D1 − Low-power state
D2 − Low-power state
3−19
•
•
•
D3 − Low-power state. Transition state before D3
hot cold
D3
− PME signal-generation capable. Main power is removed and VAUX is available.
cold
D3 − No power and completely non-functional
off
NOTE:
In the D0-uninitialized state, the controller does not generate PME and/or interrupts. When the IO_EN and
MEM_EN bits (bits 0 and 1) of the command register (PCI offset 04h, see Section 4.4) are both set, the
controller switches the state to D0-active. Transition from D3
to the D0-uninitialized state happens at
cold
the deassertion of PRST. The assertion of GRST forces the controller to the D0-uninitialized state
immediately.
The PWR_STATE bits (bits 0−1) of the power-management control/status register (PCI offset A4h, see
Section 4.38) only code for four power states, D0, D1, D2, and D3 . The differences between the three
hot
D3 states is invisible to the software because the controller is not accessible in the D3
or D3 state.
cold
off
Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power
state of the originating bridge device.
For the operating system (OS) to manage the device power states on the PCI bus, the PCI function should support
four power-management operations. These operations are:
•
•
•
•
Capabilities reporting
Power status reporting
Setting the power state
System wake up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1b in bit 4 (CAPLIST) of the status register
(PCI offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the controller, a CardBus
bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first
byte of each capability register block is required to be a unique ID of that capability. PCI power management has been
assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more
items in the list, then the next item pointer must be set to 0b. The registers following the next item pointer are specific
to the capability of the function. The PCI power-management capability implements the register block outlined in
Table 3−11.
Table 3−11. Power-Management Registers
REGISTER NAME
Next-item pointer
OFFSET
Power-management capabilities
Power-management
Capability ID
A0h
Power-management data
control/status bridge
support extensions
Power-management control/status
A4h
The power management capabilities register (PCI offset A2h, see Section 4.37) provides information on the
capabilities of the function related to power management. The power-management control/status register (PCI offset
A4h, see Section 4.38) enables control of power-management states and enables/monitors power-management
events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges.
3.8.9 CardBus Bridge Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power
Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed
in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3 or D3
without losing wake-up context (also called PME context).
hot
cold
3−20
The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
for D3 wake up are as follows:
•
Preservation of device context. The specification states that a reset must occur during the transition from
D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear
the PME context registers.
•
Power source in D3
if wake-up support is required from this state.
cold
The PCI1510 controller addresses these D3 wake-up issues in the following manner:
•
Two resets are provided to handle preservation of PME context bits:
−
Global reset (GRST) is used only on the initial boot up of the system after power up. It places the
controller in its default state and requires BIOS to configure the device before becoming fully functional.
−
PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled,
then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.
Please see the master list of PME context bits in Section 3.8.11.
•
Power source in D3
auxiliary power source must be supplied to the V
for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for
if wake-up support is required from this state. Since V
is removed in D3
, an
cold
CC
cold
terminals. Consult the PCI14xx Implementation Guide
CC
further information.
3.8.10 ACPI Support
The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The controller offers a generic interface that is compliant with
ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI configuration space at offset A8h. The
programming model is broken into status and control functions. In compliance with ACPI, the top level event status
and enable bits reside in the general-purpose event status register (PCI offset A8h, see Section 4.41) and
general-purpose event enable register (PCI offset AAh, see Section 4.42). The status and enable bits are
implemented as defined by ACPI and illustrated in Figure 3−17.
Status Bit
Event Input
Event Output
Enable Bit
Figure 3−17. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.
3−21
3.8.11 Master List of PME Context Bits and Global Reset-Only Bits
If the PME enable bit (bit 8) of the power-management control/status register (PCI offset A4h, see section 4.38) is
asserted, then the assertion of PRST will not clear the following PME context bits. If the PME enable bit is not asserted,
then the PME context bits are cleared with PRST. The PME context bits are:
•
•
•
•
•
•
•
•
•
•
•
Bridge control register (PCI offset 3Eh): bit 6
System control register (PCI offset 80h): bits 10, 9, 8
Power-management control/status register (PCI offset A4h): bits 15, 8
†
†
ExCA power control register (ExCA offset 802h): bits 7, 5 , 4−3, 1−0 ( 82365SL mode only)
ExCA interrupt and general control register (ExCA offset 803h): bits 6−5
ExCA card status change register (ExCA offset 804h): bits 11−8, 3−0
ExCA card status-change-interrupt configuration register (ExCA offset 805h): bits 3−0
CardBus socket event register (CardBus offset 00h): bits 3−0
CardBus socket mask register (CardBus offset 04h): bits 3−0
CardBus socket present state register (CardBus offset 08h): bits 13−7, 5−1
CardBus socket control register (CardBus offset 10h): bits 6−4, 2−0
Global reset places all registers in their default state regardless of the state of the PME enable bit. The GRST signal
is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally,
thus preserving all register contents. The registers cleared only by GRST are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Status register (PCI offset 06h): bits 15−11, 8
Secondary status register (PCI offset 16h): bits 15−11, 8
Interrupt pin register (PCI offset 3Dh): bits 1,0
Subsystem vendor ID register (PCI offset 40h): bits 15–0
Subsystem ID register (PCI offset 42h): bits 15–0
PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31–1
System control register (PCI offset 80h): bits 31–29, 27–13, 11, 6−0
Multifunction routing register (PCI offset 8Ch): bits 27−0
Retry status register (PCI offset 90h): bits 7−5, 3, 1
Card control register (PCI offset 91h): bits 7−5, 2−0
Device control register (PCI offset 92h): bits 7−5, 3−0
Diagnostic register (PCI offset 93h): bits 7−0
Power management capabilities register (PCI offset A2h): bit 15
General-purpose event status register (PCI offset A8h): bits 15−14
General-purpose event enable register (PCI offset AAh): bits 15−14, 11, 8, 4−0
General-purpose output (PCI offset AEh): bits 4−0
Serial bus data (PCI offset B0h): bits 7−0
Serial bus index (PCI offset B1h): bits 7−0
Serial bus slave address register (PCI offset B2h): bits 7−0
Serial bus control and status register (PCI offset B3h): bits 7, 5−0
ExCA identification and revision register (ExCA offset 00h): bits 7−0
ExCA global control register (ExCA offset 1Eh): bits 2−0
Socket present state register (CardBus offset 08h): bit 29
Socket power management register (CardBus offset 20h): bits 25−24
3−22
4 PC Card Controller Programming Model
This chapter describes the PCI1510 PCI configuration registers that make up the 256-byte PCI configuration header.
4.1 PCI Configuration Registers
The configuration header is compliant with the PCI Local Bus Specification as a CardBus bridge header and is PC 99
compliant as well. Table 4−1 shows the PCI configuration header, which includes both the predefined portion of the
configuration space and the user-definable registers.
Table 4−1. PCI Configuration Registers
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
Command
04h
Class code
Header type
Revision ID
08h
BIST
Latency timer
Cache line size
0Ch
CardBus socket/ExCA base address
Reserved
10h
Secondary status
Capability pointer
PCI bus number
14h
CardBus latency timer
Subordinate bus number
CardBus bus number
18h
CardBus Memory base register 0
CardBus Memory limit register 0
CardBus Memory base register 1
CardBus Memory limit register 1
CardBus I/O base register 0
CardBus I/O limit register 0
1Ch
20h
24h
28h
2Ch
30h
CardBus I/O base register 1
CardBus I/O limit register 1
34h
38h
Bridge control
Subsystem ID
Interrupt pin
Interrupt line
3Ch
Subsystem vendor ID
40h
PC Card 16-bit I/F legacy-mode base address
44h
Reserved
System control
Reserved
48h−7Ch
80h
84h−88h
8Ch
Multifunction routing
Diagnostic
Device control
Card control
Retry status
Capability ID
90h
Reserved
94h−9Ch
A0h
Power-management capabilities
Power-management
Next-item pointer
Power-management data
control/status bridge
support extensions
Power-management control/status
A4h
General-purpose event enable
General-purpose output
Serial bus control/status Serial bus slave address
Reserved
General-purpose event status
General-purpose input
A8h
ACh
Serial bus index
Serial bus data
B0h
B4h−FCh
4−1
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, which appear in the signal column; a detailed field description, which appears in the function column;
and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field
access tags.
Table 4−2. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
Read
Write
Set
MEANING
R
W
S
Field may be read by software.
Field may be written by software to any value.
Field may be set by a write of 1b. Writes of 0b have no effect.
Field may be cleared by a write of 1b. Writes of 0b have no effect.
Field may be autonomously updated by the controller.
C
U
Clear
Update
4.2 Vendor ID Register
This 16-bit register contains a value allocated by the PCI Special Interest Group (SIG) and identifies the manufacturer
of the PCI device. The vendor ID assigned to TI is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
Register:
Offset:
Type:
Vendor ID
00h
Read-only
104Ch
Default:
4.3 Device ID Register
This 16-bit register contains a value assigned to the controller by TI. The device identification for the controller is
AC56h.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
1
0
1
0
1
1
0
0
0
1
0
1
0
1
1
0
Register:
Offset:
Type:
Device ID
02h
Read-only
AC56h
Default:
4−2
4.4 Command Register
The command register provides control over the controller interface to the PCI bus. All bit functions adhere to the
definitions in PCI Local Bus Specification. See Table 4−3 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Command
04h
Read-only, Read/Write
0000h
Default:
Table 4−3. Command Register Description
FUNCTION
BIT
SIGNAL
TYPE
15−10
RSVD
R
Reserved. Bits 15−10 return 00 0000b when read.
Fast back-to-back enable. The controller does not generate fast back-to-back transactions; therefore, bit 9
returns 0b when read.
9
8
7
6
FBB_EN
SERR_EN
STEP_EN
PERR_EN
R
RW
R
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can
be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the
controller to report address parity errors.
0 = Disable SERR output driver (default)
1 = Enable SERR output driver
Address/data stepping control. The controller does not support address/data stepping; therefore, bit 7 is
hardwired to 0b.
Parity error response enable. Bit 6 controls the controller response to parity errors through PERR. Data
parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting
SERR.
RW
0 = The controller ignores detected parity error (default)
1 = The controller responds to detected parity errors
VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette
registers.
5
4
3
VGA_EN
MWI_EN
SPECIAL
RW
R
Memory write-and-invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory
write-and-Invalidate commands. The controller does not support memory write-and-invalidate commands,
but uses memory write commands instead; therefore, this bit is hardwired to 0b.
Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The controller does
not respond to special cycle operations; therefore, this bit is hardwired to 0b.
R
Bus master control. Bit 2 controls whether or not the controller can act as a PCI bus initiator (master). The
controller can take control of the PCI bus only when this bit is set.
2
MAST_EN
RW
0 = Disables the controller from generating PCI bus accesses (default)
1 = Enables the controller to generate PCI bus accesses
Memory space enable. Bit 1 controls whether or not the controller can claim cycles in PCI memory space.
0 = Disables the controller from responding to memory space accesses (default)
1 = Enables the controller to respond to memory space accesses
1
0
MEM_EN
IO_EN
RW
RW
I/O space control. Bit 0 controls whether or not the controller can claim cycles in PCI I/O space.
0 = Disables the controller from responding to I/O space accesses (default)
1 = Enables the controller to respond to I/O space accesses
4−3
4.5 Status Register
The status register provides device information to the host system. Bits in this register can be read normally. A bit
in the status register is reset when a 1b is written to that bit location; a 0b written to a bit location has no effect. All
bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 4−4 for a complete description
of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
Register:
Offset:
Type:
Status
06h
Read-only, Read/Clear
0210h
Default:
Table 4−4. Status Register Description
BIT
15
SIGNAL
PAR_ERR
SYS_ERR
TYPE
RC
FUNCTION
Detected parity error. Bit 15 is set when a parity error is detected (either address or data).
14
RC
Signaled system error. Bit 14 is set when SERR is enabled and the controller signals a system error to the host.
Received master abort. Bit 13 is set when a cycle initiated by the controller on the PCI bus is terminated by a
master abort.
13
12
11
MABORT
TABT_REC
TABT_SIG
RC
RC
RC
R
Received target abort. Bit 12 is set when a cycle initiated by the controller on the PCI bus is terminated by a
target abort.
Signaled target abort. Bit 11 is set by the controller when it terminates a transaction on the PCI bus with a target
abort.
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the controller
asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.
10−9 PCI_SPEED
Data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred, and the following conditions were met:
a. PERR was asserted by any PCI device including the controller.
b. The controller was the bus master during the data parity error.
c. The parity error response bit is set in the command register (PCI offset 04h, see Section 4.4).
8
DATAPAR
RC
Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; therefore, bit 7 is
hardwired to 0b.
7
6
5
FBB_CAP
UDF
R
R
R
User-definable feature support. The controller does not support the user-definable features; therefore, bit 6 is
hardwired to 0b.
66-MHz capable. The controller operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is
hardwired to 0b.
66MHZ
Capabilities list. Bit 4 returns 1b when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this
function.
4
CAPLIST
RSVD
R
R
3−0
Reserved. Bits 3−0 return 0h when read.
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the controller.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Revision ID
08h
Read-only
00h
Default:
4−4
4.7 PCI Class Code Register
The class code register recognizes the controller as a bridge device (06h) and a CardBus bridge device (07h), with
a 00h programming interface.
Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10
Base class Subclass
9
8
7
6
5
4
3
2
1
0
Name
Default
Programming interface
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
PCI class code
09h
Read-only
06 0700h
Default:
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Cache line size
0Ch
Read/Write
00h
Default:
4.9 Latency Timer Register
The latency timer register specifies the latency time for the controller in units of PCI clock cycles. When the controller
is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires
before the transaction has terminated, then the controller terminates the transaction when its GNT is deasserted.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Latency timer
0Dh
Read/Write
00h
Default:
4.10 Header Type Register
This register returns 02h when read, indicating that the configuration space adheres to the CardBus bridge PCI
header. The CardBus bridge PCI header ranges from PCI register 00h to 7Fh, and 80h to FFh is user-definable
extension registers.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
0
Register:
Offset:
Type:
Header type
0Eh
Read-only
02h
Default:
4−5
4.11 BIST Register
Because the controller does not support a built-in self-test (BIST), this register returns the value of 00h when read.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
BIST
0Fh
Read-only
00h
Default:
4.12 CardBus Socket/ExCA Base-Address Register
The CardBus socket/ExCA base-address register is programmed with a base address referencing the CardBus
socket registers and the memory-mapped ExCA register set. Bits 31−12 are read/write and allow the base address
to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11−0 are read-only,
returning 000h when read. When software writes FFFF FFFFh to this register, the value read back is FFFF F000h,
indicating that at least 4 Kbytes of memory address space are required. The CardBus registers start at offset 000h,
and the memory-mapped ExCA registers begin at offset 800h.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
CardBus socket/ExCA base-address
10h
Read-only, Read/Write
0000 0000h
Default:
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI
power-management register block resides. PCI header doublewords at A0h and A4h provide the power-management
(PM) registers. This register returns A0h when read.
Bit
7
6
5
4
3
2
1
0
Default
1
0
1
0
0
0
0
0
Register:
Offset:
Type:
Capability pointer
14h
Read-only
A0h
Default:
4−6
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-to-PCI bridge secondary status register and indicates
CardBus-related device information to the host system. This register is very similar to the status register (offset 06h,
see Section 4.5); status bits are cleared by writing a 1b. See Table 4−5 for a complete description of the register
contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Secondary status
16h
Read-only, Read/Clear
0200h
Default:
Table 4−5. Secondary Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
CBPARITY
RC
Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data).
Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The controller does not
assert CSERR.
14
13
CBSERR
CBMABORT
REC_CBTA
SIG_CBTA
CB_SPEED
RC
RC
RC
RC
R
Received master abort. Bit 13 is set when a cycle initiated by the controller on the CardBus bus has been
terminated by a master abort.
Received target abort. Bit 12 is set when a cycle initiated by the controller on the CardBus bus is terminated
by a target abort.
12
Signaled target abort. Bit 11 is set by the controller when it terminates a transaction on the CardBus bus
with a target abort.
11
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the
controller asserts CB_SPEED at a medium speed.
10−9
CardBus data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
b. The controller was the bus master during the data parity error.
c. The parity error response bit is set in the bridge control.
8
CB_DPAR
RC
Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; therefore, bit 7
is hardwired to 0b.
7
6
CBFBB_CAP
CB_UDF
R
R
User-definable feature support. The controller does not support user-definable features; therefore, bit 6
is hardwired to 0b.
66-MHz capable. The CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore,
bit 5 is hardwired to 0b.
5
CB66MHZ
RSVD
R
R
4−0
Reserved. Bits 4−0 return 00000b when read.
4−7
4.15 PCI Bus Number Register
This register is programmed by the host system to indicate the bus number of the PCI bus to which the controller is
connected. The controller uses this register in conjunction with the CardBus bus number and subordinate bus number
registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
PCI bus number
18h
Read/Write
00h
Default:
4.16 CardBus Bus Number Register
This register is programmed by the host system to indicate the bus number of the CardBus bus to which the controller
is connected. The controller uses this register in conjunction with the PCI bus number and subordinate bus number
registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
CardBus bus number
19h
Read/Write
00h
Default:
4.17 Subordinate Bus Number Register
This register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The
controller uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine
when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Subordinate bus number
1Ah
Read/Write
00h
Default:
4.18 CardBus Latency Timer Register
This register is programmed by the host system to specify the latency timer for the CardBus interface in units of CCLK
cycles. When the controller is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting.
If the latency timer expires before the transaction has terminated, then the controller terminates the transaction at
the end of the next data phase. A recommended minimum value for this register is 40h, which allows most
transactions to be completed.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
CardBus latency timer
1Bh
Read/Write
00h
Default:
4−8
4.19 Memory Base Registers 0, 1
The memory base registers indicate the lower address of a PCI memory address range. These registers are used
by the controller to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 000h. Write
transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
for the controller to claim any memory transactions through CardBus memory windows (that is, these windows are
not enabled by default to pass the first 4 Kbytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Memory base registers 0, 1
1Ch, 24h
Read-only, Read/Write
0000 0000h
Default:
4.20 Memory Limit Registers 0, 1
The memory limit registers indicate the upper address of a PCI memory address range. These registers are used
by the controller to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 000h. Write
transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
for the controller to claim any memory transactions through CardBus memory windows; that is, these windows are
not enabled by default to pass the first 4 Kbytes of memory to CardBus.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Memory limit registers 0, 1
20h, 28h
Read-only, Read/Write
0000 0000h
Default:
4−9
4.21 I/O Base Registers 0, 1
The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the
controller to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page, and the
upper 16 bits (31−16) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 31−2
are read/write. Bits 1 and 0 are read-only and always return 00b, forcing I/O windows to be aligned on a natural
doubleword boundary.
NOTE: Either the I/O base register or the I/O limit register must be nonzero to enable any I/O
transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
I/O base registers 0, 1
2Ch, 34h
Read-only, Read/Write
0000 0000h
Default:
4.22 I/O Limit Registers 0, 1
The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the
controller to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16
bits are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15−2 are read/write and
allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31−16 of the appropriate
I/O base) on doubleword boundaries.
Bits 31−16 are read-only and always return 0000h when read. The page is set in the I/O base register. Bits 1 and 0
are read-only and always return 00b, forcing I/O windows to be aligned on a natural doubleword boundary. Write
transactions to read-only bits have no effect. The controller assumes that the lower 2 bits of the limit address are 11b.
NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
I/O limit registers 0, 1
30h, 38h
Read-only, Read/Write
0000 0000h
Default:
4−10
4.23 Interrupt Line Register
The interrupt line register communicates interrupt line routing information.
Bit
7
6
5
4
3
2
1
0
Default
1
1
1
1
1
1
1
1
Register:
Offset:
Type:
Interrupt line
3Ch
Read/Write
FFh
Default:
4.24 Interrupt Pin Register
The value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode,
selected through bits 2−1 (INTMODE field) of the device control register (PCI offset 92h, see Section 4.33).
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Interrupt pin
3Dh
Read-only
01h
Default:
4−11
4.25 Bridge Control Register
The bridge control register provides control over various bridging functions. See Table 4−6 for a complete description
of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
Register:
Offset:
Type:
Bridge control
3Eh
Read-only, Read/Write
0340h
Default:
Table 4−6. Bridge Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
15−11
RSVD
R
Reserved. Bits 15−11 return 00 0000b when read.
Write posting enable. Enables write posting to and from the CardBus socket. Write posting enables posting
of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles.
Note that burst write data can be posted, but various write transactions may not.
10
9
POSTEN
RW
RW
Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. Bit 9 is encoded
as:
PREFETCH1
0 = Memory window 1 is nonprefetchable
1 = Memory window 1 is prefetchable (default)
Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
8
7
6
5
PREFETCH0
INTR
RW
RW
RW
RW
0 = Memory window 0 is nonprefetchable
1 = Memory window 0 is prefetchable (default)
PCI interrupt − IREQ routing enable. Bit 7 selects whether PC Card functional interrupts are routed to PCI
interrupts or the IRQ specified in the ExCA registers.
0 = Functional interrupts routed to PCI interrupts (default)
1 = Functional interrupts routed by ExCAs
CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted
by passing a PRST assertion to CardBus.
0 = CRST deasserted
CRST
1 = CRST asserted (default)
Master abort mode. Bit 5 controls how the controller responds to a master abort when the controller is an
initiator on the CardBus interface. This bit is common between each socket.
0 = Master aborts not reported (default)
MABTMODE
1 = Signal target abort on PCI and SERR (if enabled)
4
3
RSVD
R
Reserved. Bit 4 returns 0b when read.
VGA enable. Bit 3 affects how the controller responds to VGA addresses. When this bit is set, accesses
to VGA addresses are forwarded.
VGAEN
RW
ISA mode enable. Bit 2 affects how the controller passes I/O cycles within the 64-Kbyte ISA range. When
this bit is set, the controller does not forward the last 768 bytes of each 1K I/O range to CardBus.
2
1
ISAEN
RW
RW
CSERR enable. Bit 1 controls the response of the controller to CSERR signals on the CardBus bus.
0 = CSERR is not forwarded to PCI SERR
CSERREN
1 = CSERR is forwarded to PCI SERR
CardBus parity error response enable. Bit 0 controls the response of the controller to CardBus parity
errors.
0
CPERREN
RW
0 = CardBus parity errors are ignored
1 = CardBus parity errors are reported using CPERR
4−12
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register is used for system and option-card identification purposes and may be required
for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Subsystem vendor ID
40h
Read-only (Read/Write if enabled by SUBSYSRW)
0000h
Default:
4.27 Subsystem ID Register
The subsystem ID register is used for system and option-card identification purposes and may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Subsystem ID
42h
Read-only (Read/Write if enabled by SUBSYSRW)
0000h
Default:
4.28 PC Card 16-Bit I/F Legacy-Mode Base Address Register
The controller supports the index/data scheme of accessing the ExCA registers, which are mapped by this register.
An address written to this register is the address for the index register and the address + 1 is the data address. Using
this access method, applications requiring index/data ExCA access can be supported. The base address can be
mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1b when read. See
Section 5, ExCA Compatibility Registers, for register offsets.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
PC Card 16-bit I/F legacy-mode base address
44h
Read-only, Read/Write
0000 0001h
Default:
4−13
4.29 System Control Register
System-level initializations are performed by programming this doubleword register. See Table 4−7 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
Register:
Offset:
Type:
System control
80h
Read-only, Read/Write, Read/Clear
0844 9060h
Default:
Table 4−7. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream signaling
and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots.
00 = INTA signal in INTA IRQSER slots
31−30
SER_STEP
RW
01 = INTA signal in INTB IRQSER slots
10 = INTA signal in INTC IRQSER slots
11 = INTA signal in INTD IRQSER slots
29−28
27
RSVD
OSEN
R
Reserved. Bit 28 returns 0b when read.
Internal oscillator enable.
R/W
0 = Internal oscillator is disabled
1 = Internal oscillator is enabled (default)
SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card
socket.
26
25
SMIROUTE
SMISTATUS
RW
RC
0 = PC Card power change interrupts routed to IRQ2 (default)
1 = A CSC interrupt is generated on PC Card power changes
SMI interrupt status. This bit is set when bit 24 (SMIENB) is set and a write occurs to set the socket power.
Writing a 1b to bit 25 clears the status.
0 = SMI interrupt signaled (default)
1 = SMI interrupt not signaled
SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI interrupt
signaling is enabled and generates an interrupt. This bit defaults to 0b (disabled).
24
23
SMIENB
RSVD
RW
R
Reserved. Bit 23 returns 0b when read.
CardBus reserved terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD CardBus
terminals are driven low. When this bit is 0b, these terminals are placed in a high-impedance state.
0 = Place CardBus RSVD terminals in a high-impedance state
22
21
CBRSVD
RW
RW
1 = Drive Cardbus RSVD terminals low (default)
V
protection enable.
CC
0 = V
VCCPROT
protection enabled for 16-bit cards (default)
protection disabled for 16-bit cards
CC
CC
1 = V
Reduced zoomed video enable. When this bit is enabled, terminals A25−A22 of the card interface for PC
Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV operation. This
bit is encoded as:
20
REDUCEZV
RSVD
RW
RW
0 = Reduced zoomed video disabled (default)
1 = Reduced zoomed video enabled
19−16
Reserved. Do not change the default value.
4−14
Table 4−7. System Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to
burst downstream.
15
MRBURSTDN
RW
0 = Downstream memory read burst is disabled
1 = Downstream memory read burst is enabled (default)
Memory read burst enable upstream. When bit 14 is set, the controller allows memory read transactions
to burst upstream.
14
MRBURSTUP
RW
0 = Upstream memory read burst is disabled (default)
1 = Upstream memory read burst is enabled
Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and
is cleared upon read of this status bit.
0 = No socket activity (default)
1 = Socket activity
13
12
SOCACTIVE
RSVD
R
R
Reserved. Bit 12 returns 1b when read.
Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch
is in progress and a powering change has been requested. This bit is cleared when the power stream is
complete.
11
PWRSTREAM
R
0 = Power stream is complete and delay has expired
1 = Power stream is in progress
Power-up delay in progress status. When set, bit 10 indicates that a power-up stream has been sent to
the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay
has expired.
10
9
DELAYUP
R
R
Power-down delay in progress status. When set, bit 9 indicates that a power-down stream has been sent
to the power switch and proper power may not yet be stable. This bit is cleared when the power-down
delay has expired.
DELAYDOWN
Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when
interrogation completes.
8
INTERROGATE
R
0 = Interrogation not in progress (default)
1 = Interrogation in progress
Auto power-switch enable
0 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is disabled (default)
7
6
AUTOPWRSWEN
PWRSAVINGS
R/W
RW
1 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is enabled
Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock,
then the applicable CB state machine will not be clocked.
Subsystem ID (PCI offset 42h, see Section 4.27), subsystem vendor ID (PCI offset 40H, see
Section 4.26), ExCA identification and revision (ExCA offset 00h/40h/800h, see Section 5.1) registers
read/write enable.
5
SUBSYSRW
RW
0 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read/write
1 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read-only
(default)
CardBus data parity SERR signaling enable
0 = CardBus data parity not signaled on PCI SERR
1 = CardBus data parity signaled on PCI SERR
4
3
2
CB_DPAR
RSVD
RW
RW
RW
Reserved. Do not change the default value.
ExCA power-control bit.
0 = Enables 3.3 V
1 = Enables 5 V
EXCAPOWER
Keep clock. This bit works with PCI and CB CLKRUN protocols.
1
0
KEEPCLK
RIMUX
RW
RW
0 = Allows normal functioning of both CLKRUN protocols (default)
1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols
RI_OUT/PME multiplex enable.
0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both functions are are enabled
at the same time, the terminal becomes RI_OUT only and PME assertions are not seen.
1 = Only PME is routed to the RI_OUT/PME terminal.
4−15
4.30 Multifunction Routing Register
The multifunction routing register is used to configure the MFUNC0−MFUNC6 terminals. These terminals may be
configured for various functions. All multifunction terminals default to the general-purpose input configuration. This
register is intended to be programmed once at power-on initialization. The default value for this register can also be
loaded through a serial bus EEPROM. See Table 4−8 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Multifunction routing
8Ch
Read-only, Read/Write
0000 1000h
Default:
Table 4−8. Multifunction Routing Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−28
RSVD
R
Bits 31−28 return 0h when read.
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
†
0000 = RSVD
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
1000 = IRQ8
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
27−24
23−20
MFUNC6
MFUNC5
RW
RW
0001 = CLKRUN
0010 = IRQ2
0011 = IRQ3
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
†
0000 = GPI4
0100 = IRQ4
0101 = D3_STAT 1001 = D3_STAT
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1100 = LED_SKT
1101 = LED_SKT
1110 = GPE
0001 = GPO4
0010 = PCGNT
0011 = IRQ3
1010 = IRQ10
1011 = IRQ11
1111 = IRQ15
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the
MFUNC4 terminal provides the SCL signaling.
19−16
MFUNC4
RW
†
0000 = GPI3
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = RI_OUT
1101 = LED_SKT
1110 = GPE
0001 = GPO3
0010 = LOCK PCI
0011 = IRQ3
1111 = D3_STAT
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD
0001 = IRQSER
0010 = IRQ2
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
1000 = IRQ8
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
15−12
11−8
MFUNC3
MFUNC2
RW
RW
†
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
†
0000 = GPI2
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = RI_OUT
1101 = D3_STAT
1110 = GPE
0001 = GPO2
0010 = PCREQ
0011 = IRQ3
1111 = IRQ7
4−16
Table 4−8. Multifunction Routing Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the
MFUNC1 terminal provides the SDA signaling.
7−4
MFUNC1
RW
RW
†
0000 = GPI1
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LED_SKT
1101 = IRQ13
1110 = GPE
0001 = GPO1
0010 = D3_STAT
0011 = IRQ3
1111 = IRQ15
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
†
0000 = GPI0
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LED_SKT
1101 = IRQ13
1110 = GPE
3−0
MFUNC0
0001 = GPO0
0010 = INTA
0011 = IRQ3
1111 = IRQ15
†
Default value
4.31 Retry Status Register
The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set
15
when the controller retries a PCI or CardBus master request and the master does not return within 2 PCI clock
cycles. The flags are cleared by writing a 1b to the bit. These bits are expected to be incorporated into the PCI
command, PCI status, and bridge control registers by the PCI SIG. See Table 4−9 for a complete description of the
register contents.
Bit
7
6
5
4
3
2
1
0
Default
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Retry status
90h
Read-only, Read/Write, Read/Clear
C0h
Default:
Table 4−9. Retry Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PCI retry timeout counter enable. Bit 7 is encoded:
0 = PCI retry counter disabled
7
PCIRETRY
RW
1 = PCI retry counter enabled (default)
CardBus retry timeout counter enable. Bit 6 is encoded:
0 = CardBus retry counter disabled
6
CBRETRY
RW
1 = CardBus retry counter enabled (default)
CardBus target B retry expired. Write a 1b to clear bit 5.
0 = Inactive (default)
5
4
3
2
1
0
TEXP_CBB
RSVD
RC
R
1 = Retry has expired
Reserved. Bit 4 returns 0b when read.
CardBus target A retry expired. Write a 1b to clear bit 3.
0 = Inactive (default)
TEXP_CBA
RSVD
RC
R
1 = Retry has expired
Reserved. Bit 2 returns 0b when read.
PCI target retry expired. Write a 1b to clear bit 1.
0 = Inactive (default)
TEXP_PCI
RSVD
RC
R
1 = Retry has expired
Reserved. Bit 0 returns 0b when read.
4−17
4.32 Card Control Register
The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register. See
Table 4−10 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Card control
91h
Read-only, Read/Write, Read/Clear
00h
Default:
Table 4−10. Card Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Ring indicate output enable.
0 = Disables any routing of RI_OUT signal (default)
1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal, when RIMUX is set to 0b,
and for routing to MFUNC2 or MFUNC4
7
RIENB
RW
Compatibility ZV mode enable. When set, the corresponding PC Card socket interface ZV terminals enter
a high-impedance state. This bit defaults to 0b.
6
ZVENABLE
RW
5
RSVD
RSVD
RW
R
Reserved. Do not change default value.
4−3
Reserved. Bits 4 and 3 return 00b when read.
CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding
multifunction terminal which may be configured for CAUDPWM.
2
1
AUD2MUX
RW
Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The
SPKROUT terminal drives data only when the SPKROUTEN bit is set. This bit is encoded as:
0 = SPKR to SPKROUT not enabled
SPKROUTEN
RW
1 = SPKR to SPKROUT enabled
Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a
functional interrupt is signaled from a PC Card interface. Write back a 1b to clear this bit.
0 = No PC Card functional interrupt detected (default).
0
IFG
RC
1 = PC Card functional interrupt detected.
4−18
4.33 Device Control Register
The device control register is provided for PCI1130 compatibility. See Table 4−11 for a complete description of the
register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
1
1
0
0
1
1
0
Register:
Offset:
Type:
Device control
92h
Read-only, Read/Write
66h
Default:
Table 4−11. Device Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Socket power lock bit. When this bit is set to 1b, software cannot power down the PC Card socket while
in D3. This may be necessary to support wake on LAN or RING if the operating system is programmed
to power down a socket when the CardBus controller is placed in the D3 state.
7
SKTPWR_LOCK
RW
3-V socket capable force
0 = Not 3-V capable
6
3VCAPABLE
RW
1 = 3-V capable (default)
5
4
3
IO16V2
RSVD
TEST
RW
R
Diagnostic bit. This bit defaults to 1b.
Reserved. Bit 4 returns 0b when read.
TI test. Only a 0b should be written to bit 3.
RW
Interrupt signaling mode. Bits 2 and 1 select the interrupt signaling mode. The interrupt signaling
mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Parallel IRQ and parallel PCI interrupts
10 = IRQ serialized interrupts and parallel PCI interrupt
11 = IRQ and PCI serialized interrupts (default)
2−1
0
INTMODE
RSVD
RW
RW
Reserved. Bit 0 is reserved for test purposes. Only 0b should be written to this bit.
4−19
4.34 Diagnostic Register
The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 00h should be
written to it. See Table 4−12 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
1
1
0
0
0
0
0
Register:
Offset:
Type:
Diagnostic
93h
Read/Write
60h
Default:
Table 4−12. Diagnostic Register Description
FUNCTION
BIT
7
SIGNAL
TRUE_VAL
RSVD
TYPE
RW
R
This bit defaults to 0b. This bit is encoded as:
0 = Reads true values in PCI vendor ID and PCI device ID registers (default)
1 = Reads all 1s in reads from the PCI vendor ID and PCI device ID registers
6
Reserved. Bit 6 returns 1b when read.
CSC interrupt routing control
0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1b
1 = CSC interrupts routed to PCI if ExCA 805 bits 7−4 = 0000b (default)
In this case, the setting of ExCA 803 bit 4 is a don’t care.
5
CSC
RW
4
3
2
1
DIAG4
DIAG3
DIAG2
DIAG1
RW
RW
RW
RW
Diagnostic RETRY_DIS. Delayed transaction disable.
Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
10
15
.
Diagnostic DISCARD_TIM_SEL_CB. Set = 2 , reset = 2
10
15
.
Diagnostic DISCARD_TIM_SEL_PCI. Set = 2 , reset = 2
Standardized zoomed video register model enable.
0
STDZVEN
RW
0 = Enable the standardized zoomed video register model (default)
1 = Disable the standardized zoomed video register model
4.35 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns
01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and
the value.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Capability ID
A0h
Read-only
01h
Default:
4.36 Next-Item Pointer Register
The next-item pointer register indicates the next item in the linked list of the PCI power-management capabilities.
Because the controller function includes only one capabilities item, this register returns 00h when read.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Next-item pointer
A1h
Read-only
00h
Default:
4−20
4.37 Power-Management Capabilities Register
This register contains information on the capabilities of the PC Card function related to power management. The
CardBus bridge supports the D0, D1, D2, and D3 power states. See Table 4−13 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
Register:
Offset:
Type:
Power-management capabilities
A2h
Read/Write, Read-only
FE12h
Default:
Table 4−13. Power-Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME support. This 5-bit field indicates the power states from which the controller function may assert PME.
A 0b for any bit indicates that the function cannot assert the PME signal while in that power state. These
five bits return 11111b when read. Each of these bits is described below:
15
PME_Support
RW
Bit 15 defaults to 1b indicating the PME signal can be asserted from the D3
because wake-up support from D3
cold
state. This bit is R/W
is contingent on the system providing an auxiliary power source to
cold
the V
terminals for D3
cold
terminals. If the system designer chooses not to provide an auxiliary power source to the V
CC
CC
wake-up support, then BIOS should write a 0b to this bit.
Bit 14 contains the value 1b, indicating that the PME signal can be asserted from D3
hot
state.
Bit 13 contains the value 1b, indicating that the PME signal can be asserted from D2 state.
Bit 12 contains the value 1b, indicating that the PME signal can be asserted from D1 state.
Bit 11 contains the value 1b, indicating that the PME signal can be asserted from the D0 state.
14−11 PME_Support
R
R
D2 support. Bit 10 returns a 1b when read, indicating that the CardBus function supports the D2 device
power state.
10
D2_Support
D1 support. Bit 9 returns a 1b when read, indicating that the CardBus function supports the D1 device
power state.
9
D1_Support
RSVD
R
R
8−6
Reserved. Bits 8−6 return 000b when read.
Device-specific initialization. Bit 5 returns 1b when read, indicating that the CardBus controller function
requires special initialization (beyond the standard PCI configuration header) before the generic-class
device driver is able to use it.
5
DSI
R
Auxiliary power source. Bit 4 is tied to bit 15. When bit 4 is set, it indicates that support for PME in D3
requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. When bit 4 is 0b,
it indicates that the function supplies its own auxiliary power source.
cold
4
3
AUX_PWR
PMECLK
VERSION
R
R
R
PME clock. Bit 3 returns 0b when read, indicating that no host bus clock is required for the controller to
generate PME.
Version. Bits 2−0 return 010b when read, indicating that the power-management registers (PCI offsets
A4h−A7h, see Sections 4.38−4.40) are defined in the PCI Bus Power Management Interface Specification
version 1.1.
2−0
4−21
4.38 Power-Management Control/Status Register
The power-management control/status register determines and changes the current power state of the controller
CardBus function. The contents of this register are not affected by the internally-generated reset caused by the
transition from D3
to D0 state. All PCI, ExCA, and CardBus registers are reset as a result of a D3
to D0 state
hot
hot
transition. TI-specific registers, PCI power-management registers, and the PC Card 16-bit legacy-mode base
address register (PCI offset 44h, see Section 4.28) are not reset. See Table 4−14 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Power-management control/status
A4h
Read-only, Read/Write, Read/Clear
0000h
Default:
Table 4−14. Power-Management Control/Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME status. Bit 15 is set when the CardBus function would normally assert PME, independent
of the state of bit 8 (PME_EN). Bit 15 is cleared by a writeback of 1b, and this also clears the PME
signal if PME was asserted by this function. Writing a 0b to this bit has no effect.
15
PMESTAT
RC
Data scale. This 2-bit field returns 00b when read. The CardBus function does not return any
dynamic data.
14−13
12−9
DATASCALE
DATASEL
R
R
Data select. This 4-bit field returns 0h when read. The CardBus function does not return any
dynamic data.
PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, then assertion of PME
is disabled.
8
PME_EN
RSVD
RW
R
7−2
Reserved. Bits 7−2 return 000000b when read.
Power state. This 2-bit field is used both to determine the current power state of a function and
to set the function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
1−0
PWR_STATE
RW
11 = D3
hot
4−22
4.39 Power-Management Control/Status Register Bridge Support Extensions
The power-management control/status register bridge support extensions support PCI bridge specific functionality.
See Table 4−15 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Power-management control/status register bridge support extensions
A6h
Read-only
C0h
Default:
Table 4−15. Power-Management Control/Status Register Bridge Support Extensions Description
BIT
SIGNAL
TYPE
FUNCTION
BPCC_Enable. Bus power/clock control enable. This bit returns 1b when read.
This bit is encoded as:
0 = Bus power/clock control is disabled
1 = Bus power/clock control is enabled (default)
7
BPCC_EN
R
A 0b indicates that the bus power/clock control policies defined in the PCI Bus Power Management
Interface Specification are disabled. When the bus power/clock control enable mechanism is disabled,
the bridge power-management control/status register power state field (see Section 4.38, bits 1−0)
cannot be used by the system software to control the power or the clock of the bridge secondary bus. A
1b indicates that the bus power/clock control mechanism is enabled.
B2/B3 support for D3 . The state of this bit determines the action that is to occur as a direct result of
hot
programming the function to D3 . This bit is only meaningful if bit 7 (BPCC_EN) is a 1b. This bit is
hot
encoded as:
6
B2_B3
RSVD
R
R
0 = When the bridge is programmed to D3 , its secondary bus has its power removed (B3)
1 = When the bridge function is programmed to D3 , its secondary bus PCI clock is
hot
hot
stopped (B2) (default)
5−0
Reserved. Bits 5−0 return 000000b when read.
4.40 Power-Management Data Register
The power-management data register returns 00h when read, because the CardBus function does not report dynamic
data.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Power-management data
A7h
Read-only
00h
Default:
4−23
4.41 General-Purpose Event Status Register
The general-purpose event status register contains status bits that are set when events occur that are controlled by
the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1b
to the corresponding bit location. The status bits in this register do not depend upon the states of corresponding bits
in the general-purpose enable register. See Table 4−16 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
General-purpose event status
A8h
Read-only, Read/Clear
0000h
Default:
Table 4−16. General-Purpose Event Status Register Description
BIT
15
SIGNAL
ZV_STS
RSVD
TYPE
RC
R
FUNCTION
PC Card socket 0 ZV status. Bit 15 is set on a change in status of bit 6 (ZVENABLE) in the function 0 card
control register (PCI offset 91h, see Section 4.32).
14−12
11
Reserved. Bits 14−12 return 000b when read.
Power-change status. Bit 11 is set when software has changed the power state of the socket. A change
PWR_STS
RSVD
RC
R
in either V
CC
or V causes this bit to be set.
PP
10−9
8
Reserved. Bits 10 and 9 return 00b when read.
12-V V request status. Bit 8 is set when software has changed the requested V
level to or from 12 V
PP
PP
VPP12_STS
RC
for the PC Card socket.
7−5
4
RSVD
R
Reserved. Bits 7−5 return 000b when read.
GP4_STS
GP3_STS
GP2_STS
GP1_STS
GP0_STS
RC
RC
RC
RC
RC
GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level.
GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level.
GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level.
GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level.
GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.
3
2
1
0
4−24
4.42 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven
until the corresponding status bit is cleared and the event is serviced. The GPE can only be signaled if one of the
multifunction terminals, MFUNC6−MFUNC0, is configured for GPE signaling. See Table 4−17 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
General-purpose event enable
AAh
Read-only, Read/Write
0000h
Default:
Table 4−17. General-Purpose Event Enable Register Description
BIT
15
SIGNAL
ZV0_EN
RSVD
TYPE
RW
R
FUNCTION
PC Card ZV enable. When bit 15 is set, a GPE is signaled on a change in status of bit 6 (ZVENABLE) in
the card control register (PCI offset 91h, see Section 4.32).
14−12
11
Reserved. Bits 14−12 return 000b when read.
Power change enable. When bit 11 is set, a GPE is signaled on when software has changed the power
state.
PWR_EN
RSVD
RW
R
10−9
8
Reserved. Bits 10 and 9 return 00b when read.
12-V V
request enable. When bit 8 is set, a GPE is signaled when software has changed the requested
level to or from 12 V.
PP
VPP12_EN
RSVD
RW
R
V
PP
7−5
4
Reserved. Bits 7−5 return 000b when read.
GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5
terminal input level if configured as GPI4.
GP4_EN
RW
GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4
terminal input level if configured as GPI3.
3
2
1
0
GP3_EN
GP2_EN
GP1_EN
GP0_EN
RW
RW
RW
RW
GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2
terminal input if configured as GPI2.
GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1
terminal input if configured as GPI1.
GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0
terminal input if configured as GPI0.
4−25
4.43 General-Purpose Input Register
The general-purpose input register provides the logical value of the data input from the GPI terminals, MFUNC5,
MFUNC4, and MFUNC2−MFUNC0. See Table 4−18 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
Register:
Offset:
Type:
General-purpose input
ACh
Read-only
00XXh
Default:
Table 4−18. General-Purpose Input Register Description
FUNCTION
BIT
SIGNAL
RSVD
TYPE
15−5
R
R
R
R
R
R
Reserved. Bits 15−5 return 0s when read.
4
3
2
1
0
GPI4_DATA
GPI3_DATA
GPI2_DATA
GPI1_DATA
GPI0_DATA
GPI4 data bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal.
GPI3 data bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal.
GPI2 data bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal.
GPI1 data bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal.
GPI0 data bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal.
4.44 General-Purpose Output Register
The general-purpose output register is used for control of the general-purpose outputs. See Table 4−19 for a
complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
General-purpose output
AEh
Read-only, Read/Write
0000h
Default:
Table 4−19. General-Purpose Output Register Description
BIT
SIGNAL
TYPE
FUNCTION
15−5
RSVD
R
Reserved. Bits 15−5 return 0s when read.
GPO4 data bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5
terminal if configured as GPO4. Read transactions return the last data value written.
4
3
2
1
0
GPO4_DATA
GPO3_DATA
GPO2_DATA
GPO1_DATA
GPO0_DATA
RW
GPIO3 data bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4
terminal if configured as GPO3. Read transactions return the last data value written.
RW
RW
RW
RW
GPO2 data bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2
terminal if configured as GPO2. Read transactions return the last data value written.
GPO1 data bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1
terminal if configured as GPO1. Read transactions return the last data value written.
GPO0 data bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0
terminal if configured as GPO0. Read transactions return the last data value written.
4−26
4.45 Serial-Bus Data Register
The serial-bus data register is for programmable serial-bus byte reads and writes. This register represents the data
when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data,
the serial bus index register must be programmed with the byte address, the serial-bus slave address must be
programmed with the 7-bit slave address, and the read/write indicator bit must be reset.
On byte reads, the byte address is programmed into the serial-bus index register, the serial bus slave address register
must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the
serial bus control and status register (PCI offset B3h, see Section 4.48) must be polled until clear. Then the contents
of this register are valid read data from the serial bus interface. See Table 4−20 for a complete description of the
register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Serial-bus data
B0h
Read/Write
00h
Default:
Table 4−20. Serial-Bus Data Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serial-bus data. This bit field represents the data byte in a read or write transaction on the serial interface.
On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid.
7−0
SBDATA
RW
4.46 Serial-Bus Index Register
The serial-bus index register is for programmable serial-bus byte reads and writes. This register represents the byte
address when generating cycles on the serial-bus interface. To write a byte, the serial-bus data register must be
programmed with the data, this register must be programmed with the byte address, and the serial-bus slave address
register must be programmed with both the 7-bit slave address and the read/write indicator bit.
On byte reads, the word address is programmed into this register, the serial-bus slave address must be programmed
with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial-bus control and
status register (see Section 4.48) must be polled until clear. Then the contents of the serial-bus data register are valid
read data from the serial-bus interface. See Table 4−21 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Serial-bus index
B1h
Read/Write
00h
Default:
Table 4−21. Serial-Bus Index Register Description
BIT
SIGNAL
TYPE
FUNCTION
7−0
SBINDEX
RW
Serial-bus index. This bit field represents the byte address in a read or write transaction on the serial interface.
4−27
4.47 Serial-Bus Slave Address Register
The serial-bus slave address register is for programmable serial-bus byte read and write transactions. To write a byte,
the serial-bus data register must be programmed with the data, the serial-bus index register must be programmed
with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write
indicator bit.
On byte reads, the byte address is programmed into the serial bus index register, this register must be programmed
with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial-bus control and
status register (PCI offset B3h, see Section 4.48) must be polled until clear. Then the contents of the serial-bus data
register are valid read data from the serial-bus interface. See Table 4−22 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Serial-bus slave address
B2h
Read/Write
00h
Default:
Table 4−22. Serial-Bus Slave Address Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serial-bus slave address. This bit field represents the slave address of a read or write transaction on the
serial interface.
7−1
SLAVADDR
RW
RW
Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read
and write accesses.
0
RWCMD
0 = A byte write access is requested to the serial bus interface
1 = A byte read access is requested to the serial bus interface
4−28
4.48 Serial-Bus Control and Status Register
The serial-bus control and status register communicates serial-bus status information and selects the quick
command protocol. Bit 5 (REQBUSY) in this register must be polled during serial-bus byte reads to indicate when
data is valid in the serial-bus data register. See Table 4−23 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Serial-bus control and status
B3h (function 0)
Read-only, Read/Write, Read/Clear
00h
Default:
Table 4−23. Serial-Bus Control and Status Register Description
BIT
7
SIGNAL
PROT_SEL
RSVD
TYPE
RW
R
FUNCTION
Protocol select. When bit 7 is set, the send-byte protocol is used on write requests and the receive-byte
protocol is used on read commands. The word-address byte in the serial-bus index register (PCI offset B1h,
see Section 4.46) is not output by the controller when bit 7 is set.
6
Reserved. Bit 6 returns 0b when read.
Requested serial-bus access busy. Bit 5 indicates that a requested serial-bus access (byte read or write)
is in progress. A request is made, and bit 5 is set, by writing to the serial-bus slave address register (PCI
offset B2h, see Section 4.47). Bit 5 must be polled on reads from the serial interface. After the byte read
access has been requested, the read data is valid in the serial-bus data register.
5
4
REQBUSY
ROMBUSY
R
R
Serial EEPROM busy status. Bit 4 indicates the status of the serial EEPROM circuitry. Bit 4 is set during
the loading of the subsystem ID and other default values from the serial-bus EEPROM.
0 = Serial EEPROM circuitry is not busy
1 = Serial EEPROM circuitry is busy
Serial-bus detect. When bit 3 is set, it indicates that the serial-bus interface is detected through pullup
resistors on the VCCD0 and VCCD1 terminals after reset. If bit 3 is reset, then the MFUNC4 and MFUNC1
terminals can be used for alternate functions such as general-purpose inputs and outputs.
0 = Serial-bus interface not detected
3
SBDETECT
RC
1 = Serial-bus interface detected
Serial-bus test. When bit 2 is set, the serial-bus clock frequency is increased for test purposes.
0 = Serial-bus clock at normal operating frequency, ꢀ 100 kHz (default)
1 = Serial-bus clock frequency increased for test purposes
2
1
SBTEST
RW
RC
Requested serial-bus access error. Bit 1 indicates when a data error occurs on the serial interface during
a requested cycle, and can be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1b.
0 = No error detected during user-requested byte read or write cycle
REQ_ERR
1 = Data error detected during user-requested byte read or write cycle
EEPROM data-error status. Bit 0 indicates when a data error occurs on the serial interface during the
auto-load from the serial-bus EEPROM, and can be set due to a missing acknowledge. Bit 0 is also set on
invalid EEPROM data formats. See Section 3.6.1, Serial Bus Interface Implementation, for details on
EEPROM data format. Bit 0 is cleared by a writeback of 1b.
0
ROM_ERR
RC
0 = No error detected during auto-load from serial-bus EEPROM
1 = Data error detected during auto-load from serial-bus EEPROM
4−29
4−30
5 ExCA Compatibility Registers
The ExCA registers implemented in the PCI1510 controller are register-compatible with the Intel 82365SL−DF
PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data
scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the
register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O
base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy-mode base address
register (PCI offset 44h, see Section 4.28). The offsets from this base address run contiguously from 00h to 3Fh. See
Figure 5−1 for an ExCA I/O mapping illustration.
PCI1510 Configuration Registers
Host I/O Space
Offset
Offset
00h
PC Card A
ExCA
Registers
10h
Index
Data
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
3Fh
44h
Figure 5−1. ExCA Register Access Through I/O
The controller also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI memory
space. They are located through the CardBus socket/ExCA base-address register (PCI offset 10h, see Section 4.12)
at memory offset 800h. See Figure 5−2 for an ExCA memory mapping illustration. This illustration also identifies the
CardBus socket register mapping, which is mapped into the same 4-K window at memory offset 00h.
Host
Memory Space
PCI1510 Configuration Registers
Offset
Offset
00h
CardBus
Socket
Registers
10h
44h
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
20h
800h
ExCA
Registers
844h
Figure 5−2. ExCA Register Access Through Memory
The interrupt registers in the ExCA register set, as defined by the 82365SL−DL specification, control such card
functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing
registers and the host interrupt signaling method selected for the controller to ensure that all possible interrupts can
potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt
5−1
signaling are the ExCA interrupt and general control register (ExCA offset 03h/43h/803h, see Section 5.4) and the
ExCA card status-change interrupt configuration register (05h/45h/805h, see Section 5.6).
Access to I/O mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity.
Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this section. Table 5−1 identifies each
ExCA register and its respective ExCA offset. Memory windows have 4-Kbyte granularity.
Table 5−1. ExCA Registers and Offsets
PCI MEMORY ADDRESS
OFFSET (HEX)
ExCA OFFSET
(HEX)
EXCA REGISTER NAME
Identification and revision
800
801
802
803
804
805
806
807
808
809
80A
80B
80C
80D
80E
80F
810
811
812
813
814
815
816
817
818
819
81A
81B
81C
81D
81E
81F
820
821
822
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
Interface status
Power control
Interrupt and general control
Card status change
Card status-change interrupt configuration
Address window enable
I / O window control
I / O window 0 start-address low byte
I / O window 0 start-address high byte
I / O window 0 end-address low byte
I / O window 0 end-address high byte
I / O window 1 start-address low byte
I / O window 1 start-address high byte
I / O window 1 end-address low byte
I / O window 1 end-address high byte
Memory window 0 start-address low byte
Memory window 0 start-address high byte
Memory window 0 end-address low byte
Memory window 0 end-address high byte
Memory window 0 offset-address low byte
Memory window 0 offset-address high byte
Card detect and general control
Reserved
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
Memory window 1 start-address low byte
Memory window 1 start-address high byte
Memory window 1 end-address low byte
Memory window 1 end-address high byte
Memory window 1 offset-address low byte
Memory window 1 offset-address high byte
Global control
Reserved
Memory window 2 start-address low byte
Memory window 2 start-address high byte
Memory window 2 end-address low byte
5−2
Table 5−1. ExCA Registers and Offsets (Continued)
PCI MEMORY ADDRESS
OFFSET (HEX)
ExCA OFFSET
EXCA REGISTER NAME
(HEX)
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
−
Memory window 2 end-address high byte
Memory window 2 offset-address low byte
Memory window 2 offset-address high byte
Reserved
823
824
825
826
827
828
829
82A
82B
82C
82D
82E
82F
830
831
832
833
834
835
836
837
838
839
83A
83B
83C
83D
83E
83F
840
841
842
843
844
Reserved
Memory window 3 start-address low byte
Memory window 3 start-address high byte
Memory window 3 end-address low byte
Memory window 3 end-address high byte
Memory window 3 offset-address low byte
Memory window 3 offset-address high byte
Reserved
Reserved
Memory window 4 start-address low byte
Memory window 4 start-address high byte
Memory window 4 end-address low byte
Memory window 4 end-address high byte
Memory window 4 offset-address low byte
Memory window 4 offset-address high byte
I/O window 0 offset-address low byte
I/O window 0 offset-address high byte
I/O window 1 offset-address low byte
I/O window 1 offset-address high byte
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory window page 0
Memory window page 1
−
Memory window page 2
−
Memory window page 3
−
Memory window page 4
−
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, which appear in the signal column; a detailed field description, which appears in the function column;
and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field
access tags.
5−3
5.1 ExCA Identification and Revision Register
The ExCA identification and revision register provides host software with information on 16-bit PC Card support and
Intel 82365SL-DF compatibility. This register is read-only or read/write, depending on the setting of bit 5
(SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). See Table 5−2 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
1
0
0
0
0
1
0
0
Register:
Offset:
Type:
ExCA identification and revision
CardBus socket address + 800h; ExCA offset 00h
Read-only, Read/Write
84h
Default:
Table 5−2. ExCA Identification and Revision Register Description
BIT
7−6
5−4
SIGNAL
IFTYPE
RSVD
TYPE
FUNCTION
Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
controller. The controller supports both I/O and memory 16-bit PC cards.
R
RW
Reserved. Bits 5 and 4 can be used for Intel 82365SL-DF emulation.
Intel 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the controller. Host
software can read this field to determine compatibility to the Intel 82365SL-DF register set. Writing 0010b to
this field puts the controller in 82365SL mode.
3−0
365REV
RW
5−4
5.2 ExCA Interface Status Register
The ExCA interface status register provides information on the current status of the PC Card interface. An X in the
default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See
Table 5−3 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
X
X
X
X
X
X
Register:
Offset:
Type:
ExCA interface status
CardBus socket address + 801h; ExCA offset 01h
Read-only
Default:
00XX XXXXb
Table 5−3. ExCA Interface Status Register Description
FUNCTION
BIT
SIGNAL
TYPE
7
RSVD
R
Reserved. Bit 7 returns 0b when read.
Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the ExCA
power control register (ExCA offset 02h/42h/802h, see Section 5.3) is programmed. Bit 6 is encoded as:
6
5
CARDPWR
READY
R
R
0 = V
1 = V
and V
and V
to the socket turned off (default)
to the socket turned on
CC
CC
PP
PP
Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.
0 = PC Card not ready for data transfer
1 = PC Card ready for data transfer
Card write protect (WP). Bit 4 indicates the current status of WP at the PC Card interface. This signal reports
to the controller whether or not the memory card is write protected. Furthermore, write protection for an entire
16-bit memory window is available by setting the appropriate bit in the memory window offset-address
high-byte register.
4
CARDWP
R
0 = WP is 0b. PC Card is read/write.
1 = WP is 1b. PC Card is read-only.
Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and bit 2
(CDETECT1) to determine if a PC Card is fully seated in the socket.
0 = CD2 is 1b. No PC Card is inserted.
3
2
CDETECT2
CDETECT1
R
R
1 = CD2 is 0b. PC Card is at least partially inserted.
Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and bit 3
(CDETECT2) to determine if a PC Card is fully seated in the socket.
0 = CD1 is 1b. No PC Card is inserted.
1 = CD1 is 0b. PC Card is at least partially inserted.
Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery
voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0
reflects BVD1.
00 = Battery dead
01 = Battery dead
10 = Battery low; warning
11 = Battery good
1−0
BVDSTAT
R
When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the
PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.
5−5
5.3 ExCA Power Control Register
The ExCA power control register provides PC Card power control. Bit 7 (COE) of this register controls the 16-bit output
enables on the socket interface, and can be used for power management in 16-bit PC Card applications. See
Table 5−4 and Table 5−5 for a complete description of the register contents.
The controller supports both the 82365SL and 82365SL-DF register models. Bits 3−0 (365REV) of the ExCA
identification and revision register (ExCA offset 00h, see Section 5.1) control which register model is supported.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA power control—82365SL support
CardBus socket address + 802h; ExCA offset 02h
Read-only, Read/Write
00h
Default:
Table 5−4. ExCA Power Control Register Description—82365SL Support
BIT
SIGNAL
TYPE
FUNCTION
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the controller. This bit is
encoded as:
7
COE
RW
0 = 16-bit PC Card outputs disabled (default)
1 = 16-bit PC Card outputs enabled
6
5
RSVD
R
Reserved. Bit 6 returns 0b when read.
Auto power switch enable.
AUTOPWRSWEN
RW
0 = Automatic socket power switching based on card detects is disabled
1 = Automatic socket power switching based on card detects is enabled
PC Card power enable.
0 = V
1 = V
= No connection
CC
CC
4
CAPWREN
RSVD
RW
R
is enabled and controlled by bit 2 (EXCAPOWER) of the system control register
(PCI offset 80h, see Section 4.29)
3−2
Reserved. Bits 3 and 2 return 00b when read.
PC Card V
PP
power control. Bits 1 and 0 request changes to card V . The controller ignores this field
PP
unless V
to the socket is enabled. This field is encoded as:
CC
00 = No connection (default)
01 = V
1−0
EXCAVPP
RW
CC
10 = 12 V
11 = Reserved
5−6
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA power control—82365SL-DF support
CardBus socket address + 802h; ExCA offset 02h
Read-only, Read/Write
Default:
00h
Table 5−5. ExCA Power Control Register Description—82365SL-DF Support
BIT
7
SIGNAL
TYPE
RW
R
FUNCTION
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the controller. This bit is encoded as:
0 = 16-bit PC Card outputs disabled (default)
COE
1 = 16-bit PC Card outputs enabled
6−5
RSVD
Reserved. Bits 6 and 5 return 00b when read.
V
CC
. Bits 4 and 3 request changes to card V . This field is encoded as:
CC
00 = 0 V (default)
01 = 0 V reserved
10 = 5 V
4−3
2
EXCAVCC
RSVD
RW
R
11 = 3.3 V
Reserved. Bit 2 returns 0b when read.
V
. Bits 1 and 0 request changes to card V . The controller ignores this field unless V to the socket is
PP PP CC
enabled. This field is encoded as:
00 = No connection (default)
1−0
EXCAVPP
RW
01 = V
10 = 12 V
CC
11 = Reserved
5−7
5.4 ExCA Interrupt and General Control Register
The ExCA interrupt and general control register controls interrupt routing for I/O interrupts, as well as other critical
16-bit PC Card functions. See Table 5−6 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA interrupt and general control
CardBus socket address + 803h; ExCA offset 03h
Read/Write
00h
Default:
Table 5−6. ExCA Interrupt and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as:
0 = Ring indicate disabled (default)
7
RINGEN
RW
1 = Ring indicate enabled
Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6
affects 16-bit cards only. This bit is encoded as:
6
5
RESET
RW
RW
0 = RESET signal asserted (default)
1 = RESET signal deasserted
Card type. Bit 5 indicates the PC card type. This bit is encoded as:
0 = Memory PC Card installed (default)
CARDTYPE
1 = I/O PC Card installed
PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed
to PCI interrupts. When low, the card status change interrupts are routed using bits 7−4 (CSCSELECT field)
in the ExCA card status-change interrupt configuration register (ExCA offset 05h/45h/805h, see
Section 5.6). This bit is encoded as:
4
CSCROUTE
RW
0 = CSC interrupts are routed by ExCA registers (default)
1 = CSC interrupts are routed to PCI interrupts
Card interrupt select for I/O PC Card functional interrupts. Bits 3−0 select the interrupt routing for I/O
PC Card functional interrupts. This field is encoded as:
0000 = No interrupt routing (default). CSC interrupts are routed to PCI interrupts. This bit setting is
ORed with bit 4 (CSCROUTE) for backward compatibility.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
3−0
INTSELECT
RW
0100 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
5−8
5.5 ExCA Card Status-Change Register
The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC
Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt
source is disabled, the corresponding bit in this register always reads 0b. When an interrupt source is enabled, the
corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to
the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt
service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of
two methods: a read of this register or an explicit write back of 1b to the status bit. The choice of these two methods
is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (ExCA offset 1E/5E/81E, see
Section 5.20). See Table 5−7 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA card status-change
CardBus socket address + 804h; ExCA offset 04h
Read-only
00h
Default:
Table 5−7. ExCA Card Status-Change Register Description
BIT
SIGNAL
TYPE
FUNCTION
7−4
RSVD
R
Reserved. Bits 7−4 return 0h when read.
Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface.
This bit is encoded as:
3
2
CDCHANGE
R
R
0 = No change detected on either CD1 or CD2
1 = Change detected on either CD1 or CD2
Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of an
interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now
ready to accept new data. This bit is encoded as:
READYCHANGE
0 = No low-to-high transition detected on READY (default)
1 = Detected low-to-high transition on READY
When a 16-bit I/O card is installed, bit 2 is always 0b.
Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the
source of an interrupt was due to a battery-low warning condition. This bit is encoded as:
0 = No battery warning condition (default)
1
0
BATWARN
BATDEAD
R
R
1 = Detected battery warning condition
When a 16-bit I/O card is installed, bit 1 is always 0b.
Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates
whether the source of an interrupt was due to a battery dead condition. This bit is encoded as:
0 = STSCHG deasserted (default)
1 = STSCHG asserted
Ring indicate. When the controller is configured for ring indicate operation, bit 0 indicates the status of
RI.
5−9
5.6 ExCA Card Status-Change Interrupt Configuration Register
The ExCA card status-change interrupt configuration register controls interrupt routing for card status-change
interrupts, as well as masking CSC interrupt sources. See Table 5−8 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA card status-change interrupt configuration
CardBus socket address + 805h; ExCA offset 05h
Read/Write
00h
Default:
Table 5−8. ExCA Card Status-Change Interrupt Configuration Register Description
BIT
SIGNAL
TYPE
FUNCTION
Interrupt select for card status change. Bits 7−4 select the interrupt routing for card status-change
interrupts.
0000 = CSC interrupts routed to PCI interrupts if bit 5 (CSC) of the diagnostic register (PCI offset 93h, see
Section 4.34) is set to 1b. In this case bit 4 (CSCROUTE) of the ExCA interrupt and general control register
(ExCA offset 03h/43h/803h, see Section 5.4) is a don’t care. This is the default setting.
0000 = No ISA interrupt routing if bit 5 (CSC) of the diagnostic register is set to 0b (see Section 4.34). In
this case, CSC interrupts are routed to PCI interrupts by setting bit 4 (CSCROUTE) of the ExCA interrupt
and general control register (ExCA offset 03h/43h/803h, see Section 5.4) to 1b.
7−4
CSCSELECT
RW
This field is encoded as:
0000 = No interrupt routing (default)
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:
0 = Disables interrupts on CD1 or CD2 line changes (default)
3
2
CDEN
RW
RW
1 = Enables interrupts on CD1 or CD2 line changes
Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host
interrupt. This interrupt source is considered a card status change. This bit is encoded as:
0 = Disables host interrupt generation (default)
READYEN
1 = Enables host interrupt generation
Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
1
0
BATWARNEN
BATDEADEN
RW
RW
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
5−10
5.7 ExCA Address Window Enable Register
The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By
default, all windows to the card are disabled. The controller does not acknowledge PCI memory or I/O cycles to the
card if the corresponding enable bit in this register is 0b, regardless of the programming of the memory or I/O window
start/end/offset address registers. See Table 5−9 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA address window enable
CardBus socket address + 806h; ExCA offset 06h
Read-only, Read/Write
00h
Default:
Table 5−9. ExCA Address Window Enable Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as:
0 = I/O window 1 disabled (default)
7
IOWIN1EN
RW
1 = I/O window 1 enabled
I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as:
0 = I/O window 0 disabled (default)
6
5
IOWIN0EN
RSVD
RW
R
1 = I/O window 0 enabled
Reserved. Bit 5 returns 0b when read.
Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is
encoded as:
4
3
2
1
0
MEMWIN4EN
MEMWIN3EN
MEMWIN2EN
MEMWIN1EN
MEMWIN0EN
RW
RW
RW
RW
RW
0 = Memory window 4 disabled (default)
1 = Memory window 4 enabled
Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is
encoded as:
0 = Memory window 3 disabled (default)
1 = Memory window 3 enabled
Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is
encoded as:
0 = Memory window 2 disabled (default)
1 = Memory window 2 enabled
Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is
encoded as:
0 = Memory window 1 disabled (default)
1 = Memory window 1 enabled
Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is
encoded as:
0 = Memory window 0 disabled (default)
1 = Memory window 0 enabled
5−11
5.8 ExCA I/O Window Control Register
The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See
Table 5−10 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA I/O window control
CardBus socket address + 807h; ExCA offset 07h
Read/Write
00h
Default:
Table 5−10. ExCA I/O Window Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
7
WAITSTATE1
RW
RW
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles are extended by one equivalent ISA wait state
I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
6
ZEROWS1
0 = 8-bit cycles have standard length (default)
1 = 8-bit cycles are reduced to equivalent of three ISA cycles
I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width determined by DATASIZE1, bit 4 (default)
5
4
IOIS16W1
RW
RW
1 = Window data width determined by IOIS16
I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOSIS16W1) is
set. This bit is encoded as:
DATASIZE1
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
3
2
WAITSTATE0
ZEROWS0
RW
RW
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles are extended by one equivalent ISA wait state
I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default)
1 = 8-bit cycles are reduced to equivalent of three ISA cycles
I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width is determined by DATASIZE0, bit 0 (default)
1
0
IOIS16W0
RW
RW
1 = Window data width is determined by IOIS16
I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOSIS16W0) is
set. This bit is encoded as:
DATASIZE0
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
5−12
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 start-address low-byte
CardBus socket address + 808h; ExCA offset 08h
ExCA I/O window 1 start-address low-byte
CardBus socket address + 80Ch; ExCA offset 0Ch
Read/Write
Type:
Default:
00h
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 start-address high-byte
CardBus socket address + 809h; ExCA offset 09h
ExCA I/O window 1 start-address high-byte
CardBus socket address + 80Dh; ExCA offset 0Dh
Read/write
Type:
Default:
00h
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 end-address low-byte
CardBus socket address + 80Ah; ExCA offset 0Ah
ExCA I/O window 1 end-address low-byte
CardBus socket address + 80Eh; ExCA offset 0Eh
Read/Write
Type:
Default:
00h
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the upper 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 end-address high-byte
CardBus socket address + 80Bh; ExCA offset 0Bh
ExCA I/O window 1 end-address high-byte
CardBus socket address + 80Fh; ExCA offset 0Fh
Read/write
Type:
Default:
00h
5−13
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19−A12 of the start address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
ExCA memory window 0 start-address low-byte
CardBus socket address + 810h; ExCA offset 10h
ExCA memory window 1 start-address low-byte
CardBus socket address + 818h; ExCA offset 18h
ExCA memory window 2 start-address low-byte
CardBus socket address + 820h; ExCA offset 20h
ExCA memory window 3 start-address low-byte
CardBus socket address + 828h; ExCA offset 28h
ExCA memory window 4 start-address low-byte
CardBus socket address + 830h; ExCA offset 30h
Read/Write
Register:
Offset:
Type:
Default:
00h
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5−11 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
ExCA memory window 0 start-address high-byte
CardBus socket address + 811h; ExCA offset 11h
ExCA memory window 1 start-address high-byte
CardBus socket address + 819h; ExCA offset 19h
ExCA memory window 2 start-address high-byte
CardBus socket address + 821h; ExCA offset 21h
ExCA memory window 3 start-address high-byte
CardBus socket address + 829h; ExCA offset 29h
ExCA memory window 4 start-address high-byte
CardBus socket address + 831h; ExCA offset 31h
Read/Write
Register:
Offset:
Type:
Default:
00h
Table 5−11. ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Data size. Bit 7 controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default)
7
DATASIZE
RW
1 = Window data width is 16 bits
Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing
emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default)
6
ZEROWAIT
RW
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
16-bit cycles are reduced to equivalent of two ISA cycles.
5−4
3−0
SCRATCH
STAHN
RW
RW
Scratch pad bits. Bits 5 and 4 have no effect on memory window operation.
Start-address high nibble. Bits 3−0 represent the upper address bits A23−A20 of the memory window
start address.
5−14
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19−A12 of the end address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
ExCA memory window 0 end-address low-byte
CardBus socket address + 812h; ExCA offset 12h
ExCA memory window 1 end-address low-byte
CardBus socket address + 81Ah; ExCA offset 1Ah
ExCA memory window 2 end-address low-byte
CardBus socket address + 822h; ExCA offset 22h
ExCA memory window 3 end-address low-byte
CardBus socket address + 82Ah; ExCA offset 2Ah
ExCA memory window 4 end-address low-byte
CardBus socket address + 832h; ExCA offset 32h
Read/Write
Register:
Offset:
Type:
Default:
00h
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5−12 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
ExCA memory window 0 end-address high-byte
CardBus socket address + 813h; ExCA offset 13h
ExCA memory window 1 end-address high-byte
CardBus socket address + 81Bh; ExCA offset 1Bh
ExCA memory window 2 end-address high-byte
CardBus socket address + 823h; ExCA offset 23h
ExCA memory window 3 end-address high-byte
CardBus socket address + 82Bh; ExCA offset 2Bh
ExCA memory window 4 end-address high-byte
CardBus socket address + 833h; ExCA offset 33h
Read-only, Read/Write
Register:
Offset:
Type:
Default:
00h
Table 5−12. ExCA Memory Windows 0−4 End-Address High-Byte Registers Description
BIT
7−6
5−4
3−0
SIGNAL
MEMWS
RSVD
TYPE
RW
R
FUNCTION
Wait state. Bits 7 and 6 specify the number of equivalent ISA wait states to be added to 16-bit memory
accesses. The number of wait states added is equal to the binary value of these two bits.
Reserved. Bits 5 and 4 return 00b when read.
End-address high nibble. Bits 3−0 represent the upper address bits A23−A20 of the memory window end
address.
ENDHN
RW
5−15
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19−A12 of the offset address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
ExCA memory window 0 offset-address low-byte
CardBus socket address + 814h; ExCA offset 14h
ExCA memory window 1 offset-address low-byte
CardBus socket address + 81Ch; ExCA offset 1Ch
ExCA memory window 2 offset-address low-byte
CardBus socket address + 824h; ExCA offset 24h
ExCA memory window 3 offset-address low-byte
CardBus socket address + 82Ch; ExCA offset 2Ch
ExCA memory window 4 offset-address low-byte
CardBus socket address + 834h; ExCA offset 34h
Read/Write
Register:
Offset:
Type:
Default:
00h
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the write
protection and common/attribute memory configurations are set in this register. See Table 5−13 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
ExCA memory window 0 offset-address high-byte
CardBus socket address + 815h; ExCA offset 15h
ExCA memory window 1 offset-address high-byte
CardBus socket address + 81Dh; A ExCA offset 1Dh
ExCA memory window 2 offset-address high-byte
CardBus socket address + 825h; ExCA offset 25h
ExCA memory window 3 offset-address high-byte
CardBus socket address + 82Dh; ExCA offset 2Dh
ExCA memory window 4 offset-address high-byte
CardBus socket address + 835h; ExCA offset 35h
Read/Write
Register:
Offset:
Type:
Default:
00h
Table 5−13. ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description
BIT
SIGNAL TYPE
FUNCTION
Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is encoded as:
0 = Write operations are allowed (default)
7
WINWP
RW
1 = Write operations are not allowed
Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded
as:
6
REG
RW
RW
0 = Memory window is mapped to common memory (default)
1 = Memory window is mapped to attribute memory
Offset-address high byte. Bits 5−0 represent the upper address bits A25−A20 of the memory window
offset address.
5−0
OFFHB
5−16
5.19 ExCA Card Detect and General Control Register
The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card
removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 5−14 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
X
X
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA card detect and general control
CardBus socket address + 816h; ExCA offset 16h
Read-only, Read/Write
Default:
XX00 0000b
Table 5−14. ExCA Card Detect and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have
a default value.
0 = VS2 low
7
VS2STAT
R
1 = VS2 high
VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have
a default value.
0 = VS1 low
6
5
VS1STAT
SWCSC
R
1 = VS1 high
Software card detect interrupt. If bit 3 (CDEN) in the ExCA card status-change interrupt configuration
register (ExCA offset 05h/45h/805, see Section 5.6) is set, then writing a 1b to bit 5 causes a card-detect
card-status change interrupt for the associated card socket. If bit 3 (CDEN) in the ExCA card
status-change-interrupt configuration register (ExCA offset 05h/45h/805, see Section 5.6) is cleared to 0b,
then writing a 1b to bit 5 has no effect. A read operation of this bit always returns 0b.
RW
Card detect resume enable. If bit 4 is set to 1b, then once a card detect change has been detected on CD1
and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until bit 0 (card status change) in
the ExCA card status-change register is cleared (see Section 5.5). If this bit is a 0b, then the card detect
resume functionality is disabled.
4
CDRESUME
RW
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
3−2
1
RSVD
REGCONFIG
RSVD
R
RW
R
Reserved. Bits 3 and 2 return 00b when read.
Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card
removal event. This bit is encoded as:
0 = No change to ExCA registers on card removal (default)
1 = Reset ExCA registers on card removal
0
Reserved. Bit 0 returns 0b when read.
5−17
5.20 ExCA Global Control Register
The host interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See Table 5−15 for a
complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA global control
CardBus socket address + 81Eh; ExCA offset 1Eh
Read-only, Read/Write
00h
Default:
Table 5−15. ExCA Global Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
7−5
RSVD
R
Reserved. Bits 7−5 return 000b when read.
Level/edge interrupt mode select − card B. Bit 4 selects the signaling mode for the controller host interrupt
for card B interrupts. This bit is encoded as:
4
3
2
1
INTMODEB
INTMODEA
IFCMODE
CSCMODE
RW
RW
RW
RW
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
Level/edge interrupt mode select − card A. Bit 3 selects the signaling mode for the controller host interrupt
for card A interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register (ExCA offset 04h/44h/804h, see Section 5.5). This bit is encoded as:
0 = Interrupt flags are cleared by read of CSC register (default)
1 = Interrupt flags are cleared by explicit writeback of 1b
Card status change level/edge mode select. Bit 1 selects the signaling mode for the controller host interrupt
for card status changes. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
Power-down mode select. When bit 0 is set to 1b, the controller is in power-down mode. In power-down
mode, the controller card outputs are high-impedance until an active cycle is executed on the card interface.
Following an active cycle, the outputs are again high-impedance. The controller still receives functional
interrupts and/or card status-change interrupts; however, an actual card access is required to wake up the
interface. This bit is encoded as:
0
PWRDWN
RW
0 = Power-down mode is disabled (default)
1 = Power-down mode is enabled
5−18
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0b.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 offset-address low-byte
CardBus socket address + 836h; ExCA offset 36h
ExCA I/O window 1 offset-address low-byte
CardBus socket address + 838h; ExCA offset 38h
Read-only, Read/Write
Type:
Default:
00h
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the offset address.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 offset-address high-byte
CardBus socket address + 837h; ExCA offset 37h
ExCA I/O window 1 offset-address high-byte
CardBus socket address + 839h; ExCA offset 39h
Read/Write
Type:
Default:
00h
5.23 ExCA Memory Windows 0−4 Page Registers
The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding
addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By
programming this register to a nonzero value, host software can locate 16-bit memory windows in any 1 of 256
16-Mbyte regions in the 4-Gbyte PCI address space. These registers are only accessible when the ExCA registers
are memory-mapped; that is, these registers cannot be accessed using the index/data I/O scheme.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
ExCA memory windows 0−4 page
CardBus socket address + 840h, 841h, 842h, 843h, 844h
Read/Write
00h
Default:
5−19
5−20
6 CardBus Socket Registers
The PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control
socket-specific functions. The PCI1510 controller provides the CardBus socket/ExCA base-address register (PCI
offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Table 6−1 gives
the location of the socket registers in relation to the CardBus socket/ExCA base address.
The controller implements an additional register at offset 20h that provides power management control for the socket.
Host
Memory Space
PCI1510 Configuration Registers
Offset
Offset
00h
CardBus
Socket
Registers
10h
44h
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
20h
800h
ExCA
Registers
844h
Figure 6−1. Accessing CardBus Socket Registers Through PCI Memory
Table 6−1. CardBus Socket Registers
REGISTER NAME
OFFSET
00h
Socket event
Socket mask
04h
Socket present-state
Socket force event
Socket control
08h
0Ch
10h
Reserved
14h−1Ch
20h
Socket power-management
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, which appear in the signal column; a detailed field description, which appears in the function column;
and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field
access tags.
6−1
6.1 Socket Event Register
The socket event register indicates a change in socket status has occurred. These bits do not indicate what the
change is, only that one has occurred. Software must read the socket present-state register (CB offset 08h, see
Section 6.3) for current status. Each bit in this register can be cleared by writing a 1b to that bit. The bits in this register
can be set to a 1b by software by writing a 1b to the corresponding bit in the socket force event register (CB offset
0Ch, see Section 6.4). All bits in this register are cleared by PCI reset. They can be immediately set again, if, when
coming out of PC Card reset, the bridge finds the status unchanged (that is, CSTSCHG reasserted or card detect
is still true). Software must clear this register before enabling interrupts. If it is not cleared when interrupts are enabled,
then an interrupt is generated (but not masked) based on any bit set. See Table 6−2 for a complete description of
the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Socket event
CardBus socket address + 00h
Read-only, Read/Write, Read/Clear
0000 0000h
Default:
Table 6−2. Socket Event Register Description
FUNCTION
BIT
SIGNAL
TYPE
31−4
RSVD
R
Reserved. Bits 31−4 return 000 0000h when read.
Power cycle. Bit 3 is set when the controller detects that bit 3 (PWRCYCLE) in the socket present-state
register (CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1b.
3
2
1
PWREVENT
CD2EVENT
CD1EVENT
R/C
R/C
R/C
CCD2. Bit 2 is set when the controller detects that bit 2 (CDETECT2) in the socket present-state register
(CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1b.
CCD1. Bit 1 is set when the controller detects that bit 1 (CDETECT1) in the socket present-state register
(CB offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1b.
CSTSCHG. Bit 0 is set when bit 0 (CARDSTS) in the socket present-state register (CB offset 08h, see
Section 6.3) has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For 16-bit
PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1b.
0
CSTSEVENT
R/C
6−2
6.2 Socket Mask Register
The socket mask register allows software to control the CardBus card events that generate a status change interrupt.
The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (CB
offset 00h, see Section 6.1). See Table 6−3 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Socket mask
CardBus socket address + 04h
Read-only, Read/Write
0000 0000h
Default:
Table 6−3. Socket Mask Register Description
FUNCTION
BIT
SIGNAL
TYPE
31−4
RSVD
R
Reserved. Bits 31−4 return 000 0000b when read.
Power cycle. Bit 3 masks bit 3 (PWRCYCLE) in the socket present-state register (CB offset 08h, see
Section 6.3) from causing a status change interrupt.
3
2−1
0
PWRMASK
CDMASK
RW
RW
RW
0 = PWRCYCLE event does not cause CSC interrupt (default)
1 = PWRCYCLE event causes CSC interrupt
Card detect mask. Bits 2 and 1 mask bits 1 and 2 (CDETECT1 and CDETECT2) in the socket present-state
register (CB offset 08h, see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal does not cause CSC interrupt (default)
01 = Reserved (undefined)
10 = Reserved (undefined)
11 = Insertion/removal causes CSC interrupt
CSTSCHG mask. Bit 0 masks bit 0 (CARDSTS) in the socket present-state register (CB offset 08h, see
Section 6.3) from causing a CSC interrupt.
CSTSMASK
0 = CARDSTS event does not cause CSC interrupt (default)
1 = CARDSTS event causes CSC interrupt
6−3
6.3 Socket Present-State Register
The socket present-state register reports information about the socket interface. Write transactions to the socket force
event register (CB offset 0Ch, see Section 6.4) are reflected here, as well as general socket interface status.
Information about PC Card V
support and card type is only updated at each insertion. Also note that the controller
CC
uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected
in this register. See Table 6−4 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
X
0
0
0
X
X
X
Register:
Offset:
Type:
Socket present-state
CardBus socket address + 08h
Read-only
Default:
3000 00XXh
Table 6−4. Socket Present-State Register Description
BIT
SIGNAL
TYPE
FUNCTION
YV socket. Bit 31 indicates whether or not the socket can supply V
does not support Y.Y-V V ; therefore, this bit is always reset unless overridden by the socket force event
CC
register (CB offset 0Ch, see Section 6.4). This bit is hardwired to 0b.
= Y.Y V to PC Cards. The controller
CC
31
YVSOCKET
R
R
R
XV socket. Bit 30 indicates whether or not the socket can supply V
does not support X.X-V V ; therefore, this bit is always reset unless overridden by the socket force event
CC
register (CB offset 0Ch, see Section 6.4). This bit is hardwired to 0b.
= X.X V to PC Cards. The controller
CC
30
29
XVSOCKET
3VSOCKET
3-V socket. Bit 29 indicates whether or not the socket can supply V
does support 3.3-V V ; therefore, this bit is always set unless overridden by the socket force event
CC
register (CB offset 0Ch, see Section 6.4).
= 3.3 V to PC Cards. The controller
CC
5-V socket. Bit 28 indicates whether or not the socket can supply V
does support 5-V V ; therefore, this bit is always set unless overridden by the socket force event register
CC
(CB offset 0Ch, see Section 6.4).
= 5 V to PC Cards. The controller
CC
28
27
5VSOCKET
R
R
ZVSUPPORT
Zoomed-video support. This bit indicates whether or not the socket has support for zoomed video.
0 = Zoomed video is not supported
1 = Zoomed video is supported
26−14
13
RSVD
R
R
Reserved. Bits 26−14 return 0s when read.
YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports V
= Y.Y V.
= X.X V.
= 3.3 V.
CC
YVCARD
0 = Y.Y-V V
1 = Y.Y-V V
is not supported
is supported
CC
CC
XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports V
CC
12
11
XVCARD
3VCARD
R
R
0 = X.X-V V
1 = X.X-V V
is not supported
is supported
CC
CC
3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports V
CC
0 = 3.3-V V
1 = 3.3-V V
is not supported
is supported
CC
CC
6−4
Table 6−4. Socket Present-State Register (Continued)
BIT
SIGNAL
TYPE
FUNCTION
5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports V
= 5 V.
CC
10
5VCARD
R
0 = 5-V V
1 = 5-V V
is not supported.
is supported.
CC
CC
Bad V
invalid voltage.
request. Bit 9 indicates that the host software has requested that the socket be powered at an
CC
9
8
BADVCCREQ
DATALOST
R
0 = Normal operation (default)
1 = Invalid V
CC
request by host software
Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did
not terminate properly or because write data still resides in the controller.
0 = Normal operation (default)
R
1 = Potential data loss due to card removal
Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not
updated until a valid PC Card is inserted into the socket.
0 = Normal operation (default)
7
6
NOTACARD
IREQCINT
R
R
1 = Unrecognizable PC Card detected
READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface.
0 = READY(IREQ)//CINT low
1 = READY(IREQ)//CINT high
CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
5
4
CBCARD
R
R
16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated
until another card interrogation sequence occurs (card insertion).
16BITCARD
Power cycle. Bit 3 indicates the status of each card powering request. This bit is encoded as:
0 = Socket powered down (default)
3
2
PWRCYCLE
CDETECT2
R
R
1 = Socket powered up
CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
0 = CCD2 low (PC Card may be present)
1 = CCD2 high (PC Card not present)
CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
1
0
CDETECT1
CARDSTS
R
R
0 = CCD1 low (PC Card may be present)
1 = CCD1 high (PC Card not present)
CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface.
0 = CSTSCHG low
1 = CSTSCHG high
6.4 Socket Force Event Register
The socket force event register is used to force changes to the socket event register (CB offset 00h, see Section 6.1)
and the socket present-state register (see Section 6.3). Bit 14 (CVSTEST) in this register must be written when
forcing changes that require card interrogation. See Table 6−5 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Socket force event
CardBus socket address + 0Ch
Read-only, Write-only
0000 0000h
Default:
6−5
Table 6−5. Socket Force Event Register Description
FUNCTION
BIT
31−28
27
SIGNAL
RSVD
TYPE
R
Reserved. Bits 31−28 return 0h when read.
FZVSUPPORT
RSVD
W
Zoomed-video support. This bit indicates whether or not the socket has support for zoomed video.
Reserved. Bits 26−15 return 000h when read.
26−15
R
Card VS test. When bit 14 is set, the controller re-interrogates the PC Card, updates the socket present-state
register (CB offset 08h, see Section 6.3), and enables the socket control register (CB offset 10h, see
Section 6.5).
14
13
12
11
10
CVSTEST
FYVCARD
FXVCARD
F3VCARD
F5VCARD
W
W
W
W
W
Force YV card. Write transactions to bit 13 cause bit 13 (YVCARD) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
Force XV card. Write transactions to bit 12 cause bit 12 (XVCARD) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
Force 3-V card. Write transactions to bit 11 cause bit 11 (3VCARD) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
Force 5-V card. Write transactions to bit 10 cause bit 10 (5VCARD) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
Force bad V
CC
request. Changes to bit 9 (BADVCCREQ) in the socket present-state register (CB offset 08h,
see Section 6.3) can be made by writing to bit 9.
9
8
FBADVCCREQ
FDATALOST
W
W
Force data lost. Write transactions to bit 8 cause bit 8 (DATALOST) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written.
Force not-a-card. Write transactions to bit 7 cause bit 7 (NOTACARD) in the socket present-state register
(CB offset 08h, see Section 6.3) to be written.
7
6
5
FNOTACARD
RSVD
W
R
Reserved. Bit 6 returns 0b when read.
Force CardBus card. Write transactions to bit 5 cause bit 5 (CBCARD) in the socket present-state register
(CB offset 08h, see Section 6.3) to be written.
FCBCARD
W
Force 16-bit card. Write transactions to bit 4 cause bit 4 (16BITCARD) in the socket present-state register
(CB offset 08h, see Section 6.3) to be written.
4
3
F16BITCARD
FPWRCYCLE
W
W
Force power cycle. Write transactions to bit 3 cause bit 3 (PWREVENT) in the socket event register (CB
offset 00h, see Section 6.1) to be written, and bit 3 (PWRCYCLE) in the socket present-state register (CB
offset 08h, see Section 6.3) is unaffected.
Force CCD2. Write transactions to bit 2 cause bit 2 (CD2EVENT) in the socket event register (CB offset 00h,
see Section 6.1) to be written, and bit 2 (CDETECT2) in the socket present-state register (CB offset 08h,
see Section 6.3) is unaffected.
2
1
0
FCDETECT2
FCDETECT1
FCARDSTS
W
W
W
Force CCD1. Write transactions to bit 1 cause bit 1 (CD1EVENT) in the socket event register (CB offset 00h,
see Section 6.1) to be written, and bit 1 (CDETECT1) in the socket present-state register (CB offset 08h,
see Section 6.3) is unaffected.
Force CSTSCHG. Write transactions to bit 0 cause bit 0 (CSTSEVENT) in the socket event register (CB
offset 00h, see Section 6.1) to be written, and bit 0 (CARDSTS) in the socket present-state register (CB
offset 08h, see Section 6.3) is unaffected.
6−6
6.5 Socket Control Register
The socket control register provides control of the voltages applied to the socket and instructions for the CB CLKRUN
protocol. The controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is
inserted. See Table 6−6 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Socket control
CardBus socket address + 10h
Read-only, Read/Write
0000 0400h
Default:
Table 6−6. Socket Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−12
RSVD
R
Reserved. These bits return 00000h when read. A write to these bits has no effect.
Zoomed video activity. This bit returns 0b when the ZVEN bit is 0b (disabled). If the ZVEN bit is set to
1b, the ZV_ACTIVITY bit returns 1b.
11
10
ZV_ACTIVITY
STDZVREG
R
R
Standardized zoomed video register model support. This bit returns 1b when the STDZVEN bit (bit 0)
in the diagnostic register is cleared (PCI offset 93h, see Section 4.34).
9
8
ZVEN
RSVD
RW
R
Zoomed video enable. This bit enables zoomed video for this socket.
Reserved. ThIs bit returns 0b when read. A write to thIs bit has no effect.
CB CLKRUN protocol instructions.
0 = CB CLKRUN protocol can only attempt to stop/slow the CB clock if the socket is idle and the
PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock
1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle
7
STOPCLK
RW
V
CC
control. Bits 6−4 request card V
CC
changes.
000 = Request power off (default)
001 = Reserved
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= X.X V
= Y.Y V
CC
CC
6−4
3
VCCCTRL
RSVD
RW
R
010 = Request V
= 5 V
CC
CC
011 = Request V
= 3.3 V
Reserved. Bit 3 returns 0b when read.
V
PP
control. Bits 2−0 request card V
000 = Request power off (default)
changes.
PP
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= X.X V
= Y.Y V
PP
PP
001 = Request V
010 = Request V
011 = Request V
= 12 V
= 5 V
= 3.3 V
2−0
VPPCTRL
RW
PP
PP
PP
6−7
6.6 Socket Power-Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Socket power-management
Read-only, Read/Write
CardBus socket address + 20h
0000 0000h
Table 6−7. Socket Power-Management Register Description
BIT
SIGNAL
TYPE
FUNCTION
Reserved. Bits 31−26 return 00 0000b when read.
31−26
RSVD
R
R
Socket access status. This bit provides information on when a socket access has occurred. This bit is
cleared by a read access.
25
SKTACCES
0 = A PC card access has not occurred (default)
1 = A PC card access has occurred
Socket mode status. This bit provides clock mode information.
0 = Clock is operating normally
24
23−17
16
SKTMODE
RSVD
R
R
1 = Clock frequency has changed
Reserved. Bits 23−17 return 000 0000b when read.
CardBus clock control enable. When bit 16 is set, bit 0 (CLKCTRL) is enabled.
0 = Clock control is disabled (default)
CLKCTRLEN
RSVD
RW
R
1 = Clock control is enabled
15−1
Reserved. Bits 15−1 return 0s when read.
CardBus clock control. This bit determines whether the CB CLKRUN protocol stops or slows the CB clock
during idle states. Bit 16 (CLKCTRLEN) enables this bit.
0
CLKCTRL
RW
0 = Allows CB CLKRUN protocol to stop the CB clock (default)
1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16
6−8
7 Electrical Characteristics
†
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range, V
Clamping voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
CCP, CCCB
Input voltage range, V : PCI, miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCP
PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V
CCCB
CC
CCP
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
Output voltage range, V : PCI, miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V
CCCB
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals and miscellaneous
I
CC
terminals are measured with respect to V
specified applies for a dc condition.
instead of V . PC Card terminals are measured with respect to V
. The limit
CCCB
CCP
CC
2. Applies for external output and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals and miscellaneous
. The limit
O
CC
terminals are measured with respect to V
specified applies for a dc condition.
instead of V . PC Card terminals are measured with respect to V
CC CCCB
CCP
7−1
7.2 Recommended Operating Conditions (see Note 3)
OPERATION
MIN
NOM
3.3
3.3
5
MAX
3.6
UNIT
V
V
Commercial
Commercial
3.3 V
3.3 V
5 V
3
V
Core voltage
CC
3
4.75
3
3.6
PCI and miscellaneous I/O clamp
voltage
V
V
CCP
5.25
3.6
3.3 V
5 V
3.3
5
V
Commercial
PCI
PC Card I/O clamp voltage
CCCB
4.75
5.25
3.3 V
5 V
0.5 V
CCP
V
CCP
2
V
CCP
†
3.3 V
5 V
0.475 V
V
High-level input voltage
V
V
CCCB
CCCB
CCCB
IH
PC Card
2.4
V
‡
Miscellaneous
2
0
0
0
V
CC
3.3 V
5 V
0.3 V
CCP
0.8
PCI
†
3.3 V
5 V
0.325 V
Low-level input voltage
V
V
V
CCCB
0.8
IL
PC Card
0
0
0
0
0
0
0
0
1
0
0
0
‡
‡
‡
Miscellaneous
0.8
PCI
V
CCP
PC Card
V
CCCB
V
V
Input voltage
I
Miscellaneous
PCI
V
V
V
V
CC
CC
CC
§
PC Card
Output voltage
V
O
Miscellaneous
CC
4
PCI and PC Card
t
t
Input transition time (t and t )
ns
r
f
‡
Miscellaneous
6
T
Operating ambient temperature range
Virtual junction temperature
25
25
70
°C
°C
A
¶
T
J
115
†
‡
Applies to external inputs and bidirectional buffers without hysteresis
Miscellaneous terminals are 65, 66, 75, 117, 130, and 138 for the PGE-packaged device; A09, B02, B05, L11, L13, and N10 for the
GGU-packaged device; and B10, C09, F12, G03, H02, and L17 for the GVF-packaged device (SUSPEND, GRST, CDx, and VSx terminals).
Applies to external output buffers
§
¶
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
7−2
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER
TERMINALS
OPERATION TEST CONDITIONS
MIN
MAX
UNIT
I
I
I
I
= −0.5 mA
= −2 mA
0.9 V
3.3 V
5 V
OH
OH
OH
OH
CC
2.4
PCI
V
= −0.15 mA
= −0.15 mA
0.9 V
3.3 V
5 V
V
High-level output voltage
CC
2.4
OH
OL
PC Card
Miscellaneous
PCI
V
V
I
I
I
I
I
I
= −4 mA
= 1.5 mA
= 6 mA
V
CC
−0.6
OH
OL
OL
OL
OL
OL
0.1 V
3.3 V
5 V
CC
0.55
= 0.7 mA
= 0.7 mA
= 4 mA
0.1 V
CC
3.3 V
5 V
V
Low-level output voltage
PC Card
0.55
0.5
−1
−1
10
Miscellaneous
Output terminals
3.6 V
5.25 V
3.6 V
V = V
I
CC
CC
CC
High-impedance, low-level output
current
I
I
µA
µA
OZL
V = V
I
†
†
V = V
I
High-impedance, high-level output
current
Output terminals
OZH
5.25 V
25
−1
V = V
I
CC
Input terminals
I/O terminals
V = GND
I
V = GND
I
−10
−330
10
I
I
µA
µA
Low-level input current
IL
Pullup terminals
V = GND
I
‡
3.6 V
V = V
I
CC
Input terminals
‡
‡
‡
‡
5.25 V
3.6 V
20
10
25
30
V = V
I
CC
CC
CC
CC
High-level input current
V = V
I
IH
I/O terminals
Pulldown
5.25 V
5.25 V
V = V
I
V = V
I
†
‡
For PCI and miscellaneous terminals, V = V
. For PC Card terminals, V = V .
I
CCP
I
CCCB
For I/O terminals, input leakage (I and I ) includes I
leakage of the disabled output.
IL IH OZ
7.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t
t
t
Cycle time, PCLK
t
30
11
11
1
ns
ns
c
cyc
Pulse duration (width), PCLK high
Pulse duration (width), PCLK low
Slew rate, PCLK
t
high
w(H)
w(L)
t
ns
low
∆v/∆t
t , t
r
4
V/ns
ms
ms
f
t
w
Pulse duration (width), PRST
Setup time, PCLK active at end of PRST
t
1
rst
t
su
t
100
rst-clk
7−3
7.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature
This data manual uses the following conventions to describe time ( t ) intervals. The format is t , where subscript A
A
indicates the type of dynamic parameter being represented. One of the following is used: t = propagation delay time,
pd
t (t , t ) = delay time, t = setup time, and t = hold time.
d
en dis
su
h
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
PCLK-to-shared signal
valid delay time
t
11
val
inv
C
= 50 pF,
L
t
Propagation delay time, See Note 4
ns
pd
See Note 4
PCLK-to-shared signal
invalid delay time
t
2
2
t
t
t
t
Enable time, high impedance-to-active delay time from PCLK
Disable time, active-to-high impedance delay time from PCLK
Setup time before PCLK valid
t
ns
ns
ns
ns
en
dis
su
h
on
t
28
off
t
7
0
su
Hold time after PCLK high
t
h
NOTE 4: PCI shared signals are AD31−AD0, C/BE3−C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
7−4
8 Mechanical Information
The PCI1510 is packaged in either a 144-ball GGU or ZGU BGA, 209-ball GVF or ZVF BGA, or a 144-pin PGE
package. The following shows the mechanical dimensions for the GGU, GVF, PGE, ZGU, and ZVF packages.
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY
12,10
11,90
SQ
9,60 TYP
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 11 12 13
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,12
0,08
M
0,08
0,45
0,35
4073221-2/B 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
MicroStar BGA is a trademark of Texas Instruments.
8−1
GVF (S−PBGA−N209)
PLASTIC BALL GRID ARRAY
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
8−2
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
M
0,08
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°−ā7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: C. All linear dimensions are in millimeters.
D. This drawing is subject to change without notice.
E. Falls within JEDEC MS-026
8−3
ZGU (S−PBGA−N144)
PLASTIC BALL GRID ARRAY
12,10
11,90
SQ
9,60 TYP
0,80
N
M
L
K
J
0,80
H
G
F
E
D
C
B
A
A1 Corner
1
2
3
4
5
6
7
8
9 10 11 12 13
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,08
0,45
0,35
4204394/A 04/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
D. This package is lead-free.
8−4
ZVF (S−PBGA−N209)
PLASTIC BALL GRID ARRAY
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. This package is lead-free.
8−5
8−6
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