PCI1515GHK [TI]
PCMCIA BUS CONTROLLER, PBGA257, PLASTIC, BGA-257;
| 型号： | PCI1515GHK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCMCIA BUS CONTROLLER, PBGA257, PLASTIC, BGA-257 时钟 数据传输 PC 外围集成电路 |
| 文件： | 总124页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄꢃ ꢄ
ꢅ ꢆꢇ ꢈꢉ ꢊ ꢅ ꢋ ꢌꢍ ꢊꢎ ꢁꢏ ꢐꢑꢒ ꢓꢔ ꢁ ꢋꢇꢎ ꢐꢋ ꢉ ꢉ ꢊꢐ
Data Manual
July 2004
CS Computer Segment
SCPS099
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Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1
Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1.1
1.1.2
1.1.3
1.1.4
PCI1515 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Multifunctional Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
PCI Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.2
1.3
1.4
1.5
1.6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
2
3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1
3.2
3.3
3.4
Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3−2
3.4.1
3.4.2
3.4.3
3.4.4
Device Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
Serial EEPROM I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
2
Function 0 (CardBus) Subsystem Identification . . . . . . . . . 3−3
3.5
PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3−4
Low Voltage CardBus Card Detection . . . . . . . . . . . . . . . . . 3−4
Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
Integrated Pullup Resistors for PC Card Interface . . . . . . . 3−6
SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . 3−7
LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3−7
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.6
Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.6.1
3.6.2
3.6.3
3.6.4
Serial-Bus Interface Implementation . . . . . . . . . . . . . . . . . . . 3−8
Accessing Serial-Bus Devices Through Software . . . . . . . 3−8
Serial-Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
Serial-Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3−10
iii
Section
Title
Page
3.7
Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−12
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
PC Card Functional and Card Status Change Interrupts . 3−12
Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13
Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3−14
Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3−14
Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3−15
SMI Support in the PCI1515 Controller . . . . . . . . . . . . . . . . 3−15
3.8
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
3.8.9
3.8.10
3.8.11
Integrated Low-Dropout Voltage Regulator (LDO-VR) . . . . 3−16
CardBus (Function 0) Clock Run Protocol . . . . . . . . . . . . . . 3−16
CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3−17
16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . 3−17
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3−18
Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18
PCI Power Management (Function 0) . . . . . . . . . . . . . . . . . 3−19
CardBus Bridge Power Management . . . . . . . . . . . . . . . . . . 3−20
ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−21
Master List of PME Context Bits and Global Reset-Only
Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−21
4
PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
PCI Configuration Register Map (Function 0) . . . . . . . . . . . . . . . . . . . . 4−1
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2
Device ID Register Function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
4.12 CardBus Socket Registers/ExCA Base Address Register . . . . . . . . . 4−8
4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9
4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.19 CardBus Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.20 CardBus Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12
4.21 CardBus I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12
iv
Section
Title
Page
4.22 CardBus I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13
4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13
4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14
4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15
4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−16
4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−16
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register . . . . . . . . . 4−16
4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−17
4.30 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−19
4.31 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4−20
4.32 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . 4−21
4.33 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−21
4.34 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−22
4.35 Multifunction Routing Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4−23
4.36 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−24
4.37 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−25
4.38 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−26
4.39 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−27
4.40 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−28
4.41 Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−28
4.42 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 4−29
4.43 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 4−30
4.44 Power Management Control/Status Bridge Support Extensions
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−31
4.45 Power-Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−31
4.46 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−32
4.47 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−32
4.48 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−33
4.49 Serial Bus Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−34
ExCA Compatibility Registers (Function 0) . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5−5
ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−6
ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−7
ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5−8
ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−9
ExCA Card Status-Change Interrupt Configuration Register . . . . . . . 5−10
ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5−11
ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−12
ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . 5−13
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . 5−13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . 5−13
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . 5−14
v
Section
Title
Page
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers . . . 5−14
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers . . . 5−15
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers . . . . 5−16
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers . . . 5−16
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers . . 5−17
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers . 5−18
5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5−19
5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−20
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . 5−21
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5−21
5.23 ExCA Memory Windows 0−4 Page Registers . . . . . . . . . . . . . . . . . . . 5−21
CardBus Socket Registers (Function 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1
6
7
6.1
6.2
6.3
6.4
6.5
6.6
Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2
Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3
Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4
Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−5
Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7
Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1
7.1
7.2
7.3
Absolute Maximum Ratings Over Operating Temperature Ranges . 7−1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1
Electrical Characteristics Over Recommended Operating
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−3
7.4
7.5
7.6
PCI Clock/Reset Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . 7−3
PCI Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . 7−4
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−4
8
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−1
vi
List of Illustrations
Figure
2−1
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
Title
Page
PCI1515 GHK/ZHK-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . 2−1
PCI1515 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
Serial ROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
SPKROUT Connection to Speaker Driver . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Sample LED Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Serial-Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . 3−9
Serial-Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
Serial-Bus Protocol—Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
Serial-Bus Protocol—Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
3−10 EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . 3−10
3−11 IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−14
3−12 System Diagram Implementing CardBus Device Class Power
Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16
3−13 Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18
3−14 RI_OUT Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19
3−15 Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−21
5−1
5−2
6−1
7−1
ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2
ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2
Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . 6−1
Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−4
vii
List of Tables
Table
Title
Page
1−1
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
Signal Names by GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
CardBus PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . 2−5
16-Bit PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . 2−7
Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9
PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9
PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9
PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−10
PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11
Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . 2−12
2−10 16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . 2−13
2−11 16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . 2−14
2−12 CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . . 2−15
2−13 CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . 2−16
2−14 CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . 2−17
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
PC Card—Card Detect and Voltage Sense Connections . . . . . . . . . . . . . 3−5
TPS2228 Control Logic—xVPP/VCORE . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
TPS2228 Control Logic—xVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
TPS2226A Control Logic—xVPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
TPS2226A Control Logic—xVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
PCI1515 Registers Used to Program Serial-Bus Devices . . . . . . . . . . . . . 3−8
EEPROM Loading Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−12
3−10 PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13
3−11 SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
3−12 Requirements for Internal/External 1.5-V Core Power Supply . . . . . . . . . 3−16
3−13 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−20
4−1
4−2
4−3
4−4
4−5
4−6
4−7
4−8
4−9
Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
Function 0 PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . 4−1
Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9
Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15
System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−17
General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−19
General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . . 4−20
viii
Table
Title
Page
4−10 General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . . 4−21
4−11 General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . . 4−21
4−12 General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . . 4−22
4−13 Multifunction Routing Status Register Description . . . . . . . . . . . . . . . . . . . 4−23
4−14 Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−24
4−15 Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−25
4−16 Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−26
4−17 Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−27
4−18 Power Management Capabilities Register Description . . . . . . . . . . . . . . . 4−29
4−19 Power Management Control/Status Register Description . . . . . . . . . . . . . 4−30
4−20 Power Management Control/Status Bridge Support Extensions Register
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−31
4−21 Serial Bus Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−32
4−22 Serial Bus Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−32
4−23 Serial Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . 4−33
4−24 Serial Bus Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . 4−34
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−3
ExCA Identification and Revision Register Description . . . . . . . . . . . . . . . 5−5
ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . 5−6
ExCA Power Control Register Description—82365SL Support . . . . . . . . 5−7
ExCA Power Control Register Description—82365SL-DF Support . . . . . 5−7
ExCA Interrupt and General Control Register Description . . . . . . . . . . . . 5−8
ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . . 5−9
ExCA Card Status-Change Interrupt Configuration Register
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−10
5−9
ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . . 5−11
5−10 ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . . 5−12
5−11 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−15
5−12 ExCA Memory Windows 0−4 End-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−16
5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−18
5−14 ExCA Card Detect and General Control Register Description . . . . . . . . . 5−19
5−15 ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 5−20
6−1
6−2
6−3
6−4
6−5
6−6
6−7
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1
Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2
Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3
Socket Present State Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 6−4
Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6−6
Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7
Socket Power Management Register Description . . . . . . . . . . . . . . . . . . . 6−8
ix
x
1 Introduction
The Texas Instruments PCI1515 controller is a single-socket PC Card controller. This high-performance solution
provides the latest in PC Card technology.
1.1 Controller Functional Description
1.1.1 PCI1515 Controller
The PCI1515 controller is a single-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
Function 0 provides a PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI1515
controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports
16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1515
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1515 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI1515 controller can be programmed to accept posted writes to improve bus utilization.
1.1.2 Multifunctional Terminals
Various implementation-specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PCI LOCK, serial and parallel interrupts,
PC Card activity indicator LEDs, and other platform-specific signals. PCI complaint general-purpose events may be
programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is
included for the general-purpose inputs and outputs.
1.1.3 PCI Bus Power Management
The PCI1515 controller is compliant with the latest PCI Bus Power Management Specification, and provides several
low-power modes, which enable the host power system to further reduce power consumption.
1.1.4 Power Switch Interface
The PCI1515 controller also has a three-pin serial interface compatible with the Texas Instruments TPS2228
(default), TPS2226A, TPS2224A, TPS2223A, and TPS2220A power switches. All five power switches provide power
to the CardBus socket on the PCI1515 controller.
1.2 Features
The PCI1515 controller supports the following features:
•
•
•
•
•
•
PC Card Standard 8.1 compliant
PCI Bus Power Management Interface Specification 1.1 compliant
Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant
PCI Local Bus Specification Revision 2.3 compliant
PC 98/99 and PC2001 compliant
Windows Logo Program 2.0 compliant
1−1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PCI Bus Interface Specification for PCI-to-CardBus Bridges
1.5-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.5-V core V
Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Supports PC Card or CardBus with hot insertion and removal
CC
Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
Supports serialized IRQ with PCI interrupts
Programmable multifunction terminals
Many interrupt modes supported
Serial ROM interface for loading subsystem ID and subsystem vendor ID
ExCA-compatible registers are mapped in memory or I/O space
Intel 82365SL-DF register compatible
Supports ring indicate, SUSPEND, and PCI CLKRUN protocols and PCI bus Lock (LOCK)
Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
Compliant with Intel Mobile Power Guideline 2000
PCI power-management D0, D1, D2, and D3 power states
Advanced submicron, low-power CMOS technology
1.3 Related Documents
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0)
PC Card Standard (Release 8.1)
PCI Bus Power Management Interface Specification (Revision 1.1)
Serial Bus Protocol 2 (SBP-2)
Serialized IRQ Support for PCI Systems
PCI Mobile Design Guide
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
PCI14xx Implementation Guide for D3 Wake-Up
PCI to PCMCIA CardBus Bridge Register Description
Texas Instruments TPS2220A, TPS2223A, TPS2224A, and TPS2226A product data sheet, SLVS428A
Texas Instruments TPS2228 product data sheet, SLVS419
PCI Local Bus Specification (Revision 2.3)
PCMCIA Proposal (262)
ISO Standards for Identification Cards ISO/IEC 7816
1.4 Trademarks
Intel is a trademark of Intel Corporation.
TI and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
1−2
1.5 Terms and Definitions
Terms and definitions used in this document are given in Table 1−1.
Table 1−1. Terms and Definitions
TERM
DEFINITIONS
AT
AT (advanced technology, as in PC AT) attachment interface
CIS
Card information structure. Tuple list defined by the PC Card standard to communicate card information to the host
computer.
CSR
Control and status register
PCMCIA
RSVD
Personal Computer Memory Card International Association. Standards body that governs the PC Card standards.
Reserved for future use
1.6 Ordering Information
ORDERING NUMBER
NAME
Single Socket CardBus Controller
VOLTAGE
PACKAGE
PCI1515
3.3-V, 5-V tolerant I/Os
257-ball PBGA
(GHK or ZHK)
1−3
1−4
2 Terminal Descriptions
The PCI1515 controller is available in the 257-terminal MicroStar BGA package (GHK) or the 257-terminal lead-free
(Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2−1 is a pin diagram of the PCI1515 package.
NC
NC
NC
NC
AD16
NC
TRDY SERR
AD15
VCCP
AD12
AD13
AD11
AD10
AD9
C/BE0
AD7
AD4
AD3
AD2
TEST3
TEST2
TEST1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
W
V
U
T
NC
NC
IRDY
STOP C/BE1
NC
VCC
NC
NC
NC
NC
C/BE2 DEVSEL PAR
AD6
GND
GND
VCC
NC
GND
NC
AD18
AD22
AD17
AD21
NC
NC
AD19
AD23
AD24
AD29
REQ
FRAME PERR
AD14
VCC
AD8
AD5
VCC
AD0
AD1
RSVD
NC
GND
VCC
NC
GND
TEST4
NC
NC
R
P
N
M
L
VR_
PORT
A_CAD0
//A_D3
VCCP C/BE3
AD20
IDSEL
AD27
VCC
GND
AD28
VCC
GND
VCC
GND
RSVD
VCC
NC
GND
GND
TEST0
VCC
NC
A_CCD1
//A_CD1
A_CAD2 A_CAD1 A_CAD4
//A_D11 //A_D4 //A_D12
AD26
AD31
AD25
AD30
GNT
A_CAD3
//A_D5
A_CAD6 A_CAD5 A_RSVD
//A_D13 //A_D6 //A_D14
GND
VCC
GND
VCC
RI_OUT
//PME
A_CAD9
//A_A10
A_CC/BE0 A_CAD8 A_CAD7
PCLK
//A_CE1 //A_D15
//A_D7
A_CAD12
//A_A11
A_CAD11 A_CAD10
VR_PORT
VR_PORT
VR_EN PRST
GRST
SUSPEND
MFUNC1
NC
K
J
//A_OE
//A_CE2
A_CAD14
//A_A9
A_CAD15 A_CAD13
//A_IOWR //A_IORD
MFUNC4 MFUNC5 MFUNC6
MFUNC3 MFUNC2 SPKROUT
VCCA
A_CPAR A_CBLOCK
A_RSVD A_CC/BE1 A_CAD16
//A_A18 //A_A8 //A_A17
H
G
F
//A_A19
//A_A13
A_CTRDY
//A_A22
A_CGNT A_CSTOP A_CPERR
MFUNC0
RSVD
NC
SCL
NC
NC
NC
NC
NC
NC
SDA
NC
NC
NC
NC
NC
NC
GND
//A_WE
//A_A20
//A_A14
A_CDEVSEL
//A_A21
A_CAD29
//A_D1
A_CAD17
//A_A24
A_CIRDY A_CCLK
//A_A15 //A_A16
NC
GND
NC
NC
NC
VCC
NC
GND
VCC
GND
VCC
A_CINT//
A_READY
(IREQ)
A_CAD28
//A_D8
A_CC/BE3 A_CAD21
//A_REG //A_A5
A_CAD18 A_CC/BE2 A_CFRAME
A_USB_EN
NC
E
D
C
B
A
//A_A23
//A_A7
//A_A12
A_CAD19
//A_A25
NC
NC
NC
A_CAD31 A_CAD27 A_CSERR A_CAD25 A_CREQ
//A_D10
A_CRST
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LATCH
DATA
NC
NC
NC
NC
NC
NC
NC
NC
NC
//A_INPACK //A_RESET
//A_D0 //A_WAIT //A_A1
A_CAUDIO
A_RSVD A_CCD2
A_CAD26 A_CAD23 A_CAD22 A_CVS2
//A_BVD2
(SPKR)
NC
//A_D2
//A_CD2
//A_A0
//A_A3
//A_A4
//A_VS2
A_CCLKRUN A_CSTSCHG
A_CAD30
//A_D9
A_CVS1 A_CAD24
A_CAD20
//A_A6
//A_WP
//A_BVD1
CLOCK
VCCA
//A_VS1
//A_A2
(IOIS16) (STSCHG/RI)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 2−1. PCI1515 GHK/ZHK-Package Terminal Diagram
2−1
Table 2−1 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for
both CardBus and 16-bit PC Cards for the PCI1515 GHK package. Table 2−2 and Table 2−3 list the terminal
assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for the GHK
package; Table 2−2 is for CardBus signal names and Table 2−3 is for 16-bit PC Card signal names.
Terminal E5 on the GHK package is an identification ball used for device orientation.
Table 2−1. Signal Names by GHK Terminal Number
SIGNAL NAME
SIGNAL NAME
TERMINAL
NUMBER
TERMINAL
NUMBER
CardBus PC Card
16-Bit PC Card
CardBus PC Card
16-Bit PC Card
NC
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C01
C02
NC
NC
NC
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
D01
D02
D03
D17
D18
D19
E01
E02
E03
E06
E07
E08
E09
E10
E11
E12
E13
E14
E17
E18
E19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LATCH
A_CAD31
A_CAD27
A_CSERR
A_CAD25
A_CREQ
A_CRST
NC
LATCH
A_D10
A_D0
A_WAIT
A_A1
A_INPACK
A_RESET
NC
CLOCK
A_CAD30
A_CCLKRUN
A_CSTSCHG
A_CVS1
A_CAD24
CLOCK
A_D9
A_WP(IOIS16)
A_BVD1(STSCHG/RI)
A_VS1
A_A2
V
CCA
V
CCA
A_CAD20
NC
A_A6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A_CAD19
NC
A_A25
NC
NC
NC
NC
NC
NC
NC
DATA
A_RSVD
A_CCD2
A_CAUDIO
A_CAD26
A_CAD23
A_CAD22
A_CVS2
NC
DATA
A_D2
A_CD2
A_BVD2(SPKR)
A_A0
A_A3
A_A4
A_VS2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A_USB_EN
A_CAD28
A_CINT
A_CC/BE3
A_CAD21
A_CAD18
A_CC/BE2
A_CFRAME
A_USB_EN
A_D8
A_READY(IREQ)
A_REG
A_A5
A_A7
A_A12
A_A23
NC
NC
NC
NC
NC
NC
NC
NC
2−2
Table 2−1. Signal Names by GHK Terminal Number (Continued)
SIGNAL NAME
SIGNAL NAME
TERMINAL
NUMBER
TERMINAL
NUMBER
CardBus PC Card
16-Bit PC Card
CardBus PC Card
A_CAD13
16-Bit PC Card
F01
F02
F03
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F17
F18
F19
G01
G02
G03
G05
G06
G14
G15
G17
G18
G19
H01
H02
H03
H05
H06
H14
H15
H17
H18
H19
J01
J02
J03
J05
J06
J14
J15
J17
RSVD
NC
RSVD
NC
J18
J19
A_IORD
V
CCA
V
CCA
NC
NC
K01
K02
K03
K05
K06
K14
K15
K17
K18
K19
L01
L02
L03
L05
L06
L14
L15
L17
L18
L19
M01
M02
M03
M05
M06
M14
M15
M17
M18
M19
N01
N02
N03
N05
N06
N14
N15
N17
N18
N19
P01
P02
P03
VR_PORT
VR_EN
PRST
VR_PORT
VR_EN
PRST
NC
NC
V
CC
V
CC
GND
NC
GND
NC
GRST
GRST
GND
GND
V
CC
V
CC
GND
GND
GND
GND
A_CAD12
A_CAD11
A_CAD10
VR_PORT
PCLK
A_A11
A_CAD29
A_D1
A_OE
V
CC
GND
V
CC
GND
A_CE2
VR_PORT
PCLK
V
CC
V
CC
A_CAD17
A_CIRDY
A_CCLK
A_CDEVSEL
MFUNC0
SCL
A_A24
A_A15
A_A16
A_A21
MFUNC0
SCL
GNT
GNT
REQ
REQ
RI_OUT/PME
RI_OUT/PME
V
V
V
V
CC
CC
CC
CC
A_CAD9
A_CC/BE0
A_CAD8
A_CAD7
AD31
A_A10
A_CE1
A_D15
A_D7
AD31
AD30
AD29
AD27
AD28
GND
SDA
SDA
NC
NC
RSVD
RSVD
GND
GND
A_CTRDY
A_CGNT
A_CSTOP
A_CPERR
MFUNC3
MFUNC2
SPKROUT
MFUNC1
GND
A_A22
A_WE
AD30
AD29
A_A20
A_A14
MFUNC3
MFUNC2
SPKROUT
MFUNC1
GND
AD27
AD28
GND
A_CAD3
A_CAD6
A_CAD5
A_RSVD
AD26
A_D5
A_D13
A_D6
A_D14
AD26
AD25
AD24
IDSEL
GND
A_CPAR
A_CBLOCK
A_RSVD
A_CC/BE1
A_CAD16
MFUNC4
MFUNC5
MFUNC6
SUSPEND
A_A13
A_A19
A_A18
A_A8
AD25
AD24
IDSEL
A_A17
MFUNC4
MFUNC5
MFUNC6
SUSPEND
GND
NC
NC
A_CCD1
A_CAD2
A_CAD1
A_CAD4
A_CD1
A_D11
A_D4
A_D12
V
V
V
V
CC
CC
V
CCP
V
CCP
CC
CC
A_CAD14
A_CAD15
A_A9
C/BE3
AD23
C/BE3
AD23
A_IOWR
2−3
Table 2−1. Signal Names by GHK Terminal Number (Continued)
SIGNAL NAME
SIGNAL NAME
TERMINAL
NUMBER
TERMINAL
NUMBER
CardBus PC Card
AD20
16-Bit PC Card
CardBus PC Card
16-Bit PC Card
AD2
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P17
P18
P19
R01
R02
R03
R06
R07
R08
R09
R10
R11
R12
R13
R14
R17
R18
R19
T01
T02
T03
T17
T18
T19
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
AD20
U11
U12
U13
U14
U15
U16
U17
U18
U19
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
AD2
TEST1
GND
V
V
CC
GND
TEST1
GND
CC
GND
V
CC
GND
V
CC
GND
GND
GND
V
CC
V
CC
V
CC
V
CC
NC
NC
NC
NC
AD1
AD1
TEST0
TEST0
GND
GND
V
V
V
V
V
CC
V
CC
CC
CC
NC
NC
NC
NC
CC
CC
VR_PORT
TEST4
NC
VR_PORT
TEST4
NC
NC
NC
NC
NC
A_CAD0
AD22
AD21
AD19
FRAME
PERR
AD14
AD8
A_D3
AD22
AD21
AD19
FRAME
PERR
AD14
AD8
IRDY
STOP
C/BE1
AD12
AD10
AD7
AD3
TEST2
NC
IRDY
STOP
C/BE1
AD12
AD10
AD7
AD3
TEST2
NC
AD5
AD5
AD0
AD0
NC
NC
RSVD
NC
RSVD
NC
NC
NC
NC
NC
GND
GND
NC
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AD18
AD17
NC
AD18
AD17
NC
NC
NC
AD16
TRDY
SERR
AD15
AD16
TRDY
SERR
AD15
NC
NC
NC
NC
NC
NC
V
CCP
V
CCP
NC
NC
AD11
C/BE0
AD4
TEST3
NC
AD11
C/BE0
AD4
TEST3
NC
NC
NC
NC
NC
NC
NC
C/BE2
DEVSEL
PAR
AD13
AD9
C/BE2
DEVSEL
PAR
AD13
AD9
NC
NC
NC
NC
NC
NC
NC
NC
AD6
AD6
NC
NC
2−4
Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically
SIGNAL
NAME
TERMINAL
NUMBER
TERMINAL
NUMBER
SIGNAL
NAME
TERMINAL
NUMBER
SIGNAL
NAME
TERMINAL
NUMBER
SIGNAL NAME
AD0
AD1
R11
P11
U11
V11
W11
R10
U10
V10
R09
U09
V09
W09
V08
U08
R08
W07
W04
T02
T01
R03
P05
R02
R01
P03
N03
N02
N01
M05
M06
M03
M02
M01
P19
N18
N17
M15
N19
M18
M17
L19
A_CAD11
A_CAD12
A_CAD13
A_CAD14
A_CAD15
A_CAD16
A_CAD17
A_CAD18
A_CAD19
A_CAD20
A_CAD21
A_CAD22
A_CAD23
A_CAD24
A_CAD25
A_CAD26
A_CAD27
A_CAD28
A_CAD29
A_CAD30
A_CAD31
A_CAUDIO
A_CBLOCK
A_CC/BE0
A_CC/BE1
A_CC/BE2
A_CC/BE3
A_CCD1
K17
K15
J18
A_CTRDY
A_CVS1
A_CVS2
A_RSVD
A_RSVD
A_RSVD
A_USB_EN
C/BE0
C/BE1
C/BE2
C/BE3
CLOCK
DATA
G15
A13
B16
B10
H17
M19
E10
W10
V07
U05
P02
A09
B09
U06
R06
F07
F10
F13
G14
H06
K06
K14
M14
N06
P07
P09
R14
R17
U13
U14
U18
L02
K05
N05
V05
C09
G01
H05
H02
H01
J01
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A02
A03
A04
A05
A06
A07
A08
A17
A18
B01
B02
B03
B04
B05
B06
B07
B08
B17
B18
B19
C01
C02
C03
C04
C05
C06
C07
C08
C16
C17
C18
C19
D01
D02
D03
D17
D18
E01
E02
E03
E06
E07
E08
AD2
AD3
J15
AD4
J17
AD5
H19
F15
E17
D19
A16
E14
B15
B14
A14
C13
B13
C11
E11
F11
A10
C10
B12
H15
L17
H18
E18
E13
N15
B11
F18
A11
F19
E19
G17
E12
F17
H14
G19
C14
C15
C12
G18
A12
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
DEVSEL
FRAME
GND
AD14
AD15
AD16
GND
AD17
GND
AD18
GND
AD19
GND
AD20
GND
AD21
GND
AD22
GND
AD23
GND
AD24
GND
AD25
GND
AD26
GND
AD27
GND
AD28
A_CCD2
GND
AD29
A_CCLK
GND
AD30
A_CCLKRUN
A_CDEVSEL
A_CFRAME
A_CGNT
GND
AD31
GNT
A_CAD0
A_CAD1
A_CAD2
A_CAD3
A_CAD4
A_CAD5
A_CAD6
A_CAD7
A_CAD8
A_CAD9
A_CAD10
GRST
IDSEL
IRDY
A_CINT
A_CIRDY
A_CPAR
LATCH
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
A_CPERR
A_CREQ
A_CRST
L18
A_CSERR
A_CSTOP
A_CSTSCHG
L15
J02
K18
J03
2−5
Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL
NAME
TERMINAL
NUMBER
SIGNAL
NAME
TERMINAL
NUMBER
TERMINAL
NUMBER
SIGNAL
NAME
TERMINAL
NUMBER
SIGNAL NAME
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E09
F02
F03
F05
F08
G05
N14
P18
R13
R18
R19
T03
T17
T18
T19
U01
U02
U03
U04
U16
U17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PAR
PCLK
V01
V02
V03
V04
V13
V14
V15
V16
V17
V18
V19
W02
W03
W13
W14
W15
W16
W17
W18
U07
L01
PERR
PRST
R07
K03
L03
L05
F01
G06
R12
G02
G03
W06
H03
V06
J05
V
V
V
V
V
V
V
V
V
V
V
V
V
F12
F14
J06
J14
L06
L14
P06
P08
P10
P13
P14
U15
U19
A15
J19
P01
W08
K02
K01
K19
P15
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
REQ
RI_OUT/PME
RSVD
RSVD
RSVD
SCL
SDA
SERR
SPKROUT
STOP
SUSPEND
TEST0
TEST1
TEST2
TEST3
TEST4
TRDY
P12
U12
V12
W12
P17
W05
F06
F09
V
CCA
V
CCA
V
CCP
V
CCP
VR_EN
VR_PORT
VR_PORT
VR_PORT
V
V
CC
CC
2−6
Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically
SIGNAL
NAME
TERMINAL
NUMBER
TERMINAL
NUMBER
TERMINAL
NUMBER
SIGNAL
NAME
TERMINAL
NUMBER
SIGNAL NAME
SIGNAL NAME
AD0
AD1
R11
P11
U11
V11
W11
R10
U10
V10
R09
U09
V09
W09
V08
U08
R08
W07
W04
T02
T01
R03
P05
R02
R01
P03
N03
N02
N01
M05
M06
M03
M02
M01
B13
C13
A14
B14
B15
E14
A16
E17
H18
J15
A_A11
A_A12
K15
E18
H14
G19
F17
F18
H19
H17
H15
G18
F19
G15
E19
F15
D19
A12
B12
N15
B11
L17
K18
C11
F11
B10
P19
N18
M15
M18
L19
E11
A10
C10
N17
N19
M17
M19
L18
C14
J18
A_RESET
A_USB_EN
A_VS1
A_VS2
A_WAIT
A_WE
A_WP(IOIS16)
C/BE0
C/BE1
C/BE2
C/BE3
CLOCK
DATA
C15
E10
A13
B16
C12
G17
A11
W10
V07
U05
P02
A09
B09
U06
R06
F07
F10
F13
G14
H06
K06
K14
M14
N06
P07
P09
R14
R17
U13
U14
U18
L02
K05
N05
V05
C09
G01
H05
H02
H01
J01
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A02
A03
A04
A05
A06
A07
A08
A17
A18
B01
B02
B03
B04
B05
B06
B07
B08
B17
B18
B19
C01
C02
C03
C04
C05
C06
C07
C08
C16
C17
C18
C19
D01
D02
D03
D17
D18
E01
E02
E03
E06
E07
E08
AD2
A_A13
AD3
A_A14
AD4
A_A15
AD5
A_A16
AD6
A_A17
AD7
A_A18
AD8
A_A19
AD9
A_A20
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
A_A0
A_A1
A_A2
A_A3
A_A4
A_A5
A_A6
A_A7
A_A8
A_A9
A_A10
A_A21
A_A22
A_A23
A_A24
DEVSEL
FRAME
GND
A_A25
A_BVD1(STSCHG/RI)
A_BVD2(SPKR)
A_CD1
A_CD2
A_CE1
A_CE2
A_D0
GND
GND
GND
GND
GND
GND
A_D1
GND
A_D2
GND
A_D3
GND
A_D4
GND
A_D5
GND
A_D6
GND
A_D7
GND
A_D8
GND
A_D9
GND
A_D10
GNT
A_D11
GRST
A_D12
IDSEL
IRDY
A_D13
A_D14
LATCH
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
A_D15
A_INPACK
A_IORD
A_IOWR
A_OE
J17
K17
E12
E13
A_READY(IREQ)
A_REG
J02
L15
J03
2−7
Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)
TERMINAL
NUMBER
SIGNAL
NAME
TERMINAL
NUMBER
SIGNAL
NAME
TERMINAL
NUMBER
SIGNAL
NAME
TERMINAL
NUMBER
SIGNAL NAME
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E09
F02
F03
F05
F08
G05
N14
P18
R13
R18
R19
T03
T17
T18
T19
U01
U02
U03
U04
U16
U17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PAR
PCLK
V01
V02
V03
V04
V13
V14
V15
V16
V17
V18
V19
W02
W03
W13
W14
W15
W16
W17
W18
U07
L01
PERR
PRST
R07
K03
L03
L05
F01
G06
R12
G02
G03
W06
H03
V06
J05
V
V
V
V
V
V
V
V
V
V
V
V
V
F12
F14
J06
J14
L06
L14
P06
P08
P10
P13
P14
U15
U19
A15
J19
P01
W08
K02
K01
K19
P15
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
REQ
RI_OUT/PME
RSVD
RSVD
RSVD
SCL
SDA
SERR
SPKROUT
STOP
SUSPEND
TEST0
TEST1
TEST2
TEST3
TEST4
TRDY
P12
U12
V12
W12
P17
W05
F06
F09
V
CCA
V
CCA
V
CCP
V
CCP
VR_EN
VR_PORT
VR_PORT
VR_PORT
V
V
CC
CC
2−8
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 2−4. Power Supply Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
F07, F10, F13,
G14, H06, K06,
K14, M14, N06,
P07, P09, R14,
R17, U13, U14,
U18
GND
—
Digital ground terminal
F06, F09, F12,
F14, J06, J14,
L06, L14, P06,
P08, P10, P13,
P14, U15, U19
V
CC
—
3.3-V power supply terminal for I/O and internal voltage regulator
V
V
A15, J19
P01, W08
K02
—
—
I
Clamp voltage for PC Card A interface. Matches card A signaling environment, 5 V or 3.3 V
Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
Internal voltage regulator enable. Active low
CCA
CCP
VR_EN
VR_PORT
K01, K19, P15
I/O
1.5-V output from the internal voltage regulator
Table 2−5. PC Card Power Switch Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults
CLOCK
A09
I/O to an input, but can be changed to an output by using bit 27 (P2CCLK) in the system control register (offset
80h, see Section 4.29).
Power switch data. DATA is used to communicate socket power control information serially to the power
switch.
DATA
B09
C09
O
Power switch latch. LATCH is asserted by the controller to indicate to the power switch that the data on the
DATA line is valid.
LATCH
O
Table 2−6. PCI System Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
Global reset. When the global reset is asserted, the GRST signal causes the controller to place all output buffers
in a high-impedance state and reset all internal registers. When GRST is asserted, the controller is completely
in its default state. For systems that require wake-up from D3, GRST is normally asserted only during initial boot.
PRST must be asserted following initial boot so that PME context is retained when transitioning from D3 to D0.
For systems that do not require wake-up from D3, GRST must be tied to PRST. When the SUSPEND mode
is enabled, the controller is protected from the GRST, and the internal registers are preserved. All outputs are
placed in a high-impedance state, but the contents of the registers are preserved.
GRST
K05
I
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
PCLK
PRST
L01
K03
I
I
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to place all output buffers in
a high-impedance state and reset some internal registers. When PRST is asserted, the controller is completely
nonfunctional. After PRST is deasserted, the controller is in a default state.
When SUSPEND and PRST are asserted, the controller is protected from PRST clearing the internal registers.
All outputs are placed in a high-impedance state, but the contents of the registers are preserved.
2−9
Table 2−7. PCI Address and Data Terminals
TERMINAL
I/O
DESCRIPTION
NAME NUMBER
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
M01
M02
M03
M06
M05
N01
N02
N03
P03
R01
R02
P05
R03
T01
T02
W04
W07
R08
U08
V08
W09
V09
U09
R09
V10
U10
R10
W11
V11
U11
P11
R11
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a 32-bit address or other
destination information. During the data phase, AD31−AD0 contain data.
I/O
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the
address phase of a primary-bus PCI cycle, C/BE3−C/BE0 define the bus command. During the data phase, this
4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry
meaningful data. C/BE0 applies to byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8), C/BE2 applies to
byte 2 (AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24).
P02
U05
V07
W10
C/BE3
C/BE2
C/BE1
C/BE0
I/O
I/O
PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across the AD31−AD0
and C/BE3−C/BE0 buses. As an initiator during PCI cycles, the controller outputs this parity indicator with a
one-PCLK delay. As a target during PCI cycles, the controller compares its calculated parity to the parity
indicator of the initiator. A compare error results in the assertion of a parity error (PERR).
PAR
U07
2−10
Table 2−8. PCI Interface Control Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator
U06
R06
I/O on the bus, the controller monitors DEVSEL until a target responds. If no target responds before timeout occurs,
then the controller terminates the cycle with an initiator abort.
DEVSEL
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus
I/O transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted,
the PCI bus transaction is in the final data phase.
FRAME
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the controller access to the PCI bus after the current
L02
N05
V05
I
I
data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus
parking algorithm.
GNT
Initialization device select. IDSEL selects the controller during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines on the PCI bus.
IDSEL
IRDY
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the
I/O transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until
IRDY and TRDY are both sampled asserted, wait states are inserted.
PCI parity error indicator. PERR is driven by a PCI controller to indicate that calculated parity does not match
PAR when PERR is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4).
R07
L03
I/O
PERR
REQ
O
O
PCI bus request. REQ is asserted by the controller to request access to the PCI bus as an initiator.
PCI system error. SERR is an output that is pulsed from the controller when enabled through bit 8 of the
command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The controller need
not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register, this signal
also pulses, indicating that an address parity error has occurred on a CardBus interface.
W06
SERR
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
V06
I/O transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support
burst data transfers.
STOP
TRDY
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the
I/O transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until
both IRDY and TRDY are asserted, wait states are inserted.
W05
2−11
Table 2−9. Multifunction and Miscellaneous Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
USB enable. This output terminal controls an external CBT switch when an USB
card is inserted into the socket.
E10
O
A_USB_EN
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
G01
H05
H02
H01
J01
J02
J03
Multifunction terminals 0−6. See Section 4.35, Multifunction Routing Status
Register, for configuration details.
I/O
A02, A03, A04, A05, A06, A07,
A08, A17, A18, B01, B02, B03,
B04, B05, B06, B07, B08, B17,
B18, B19, C01, C02, C03, C04,
C05, C06, C07, C08, C16, C17,
C18, C19, D01, D02, D03, D17,
D18, E01, E02, E03, E06, E07,
E08, E09, F02, F03, F05, F08,
G05, N14, P18, R13, R18, R19,
T03, T17, T18, T19, U01, U02,
U03, U04, U16, U17, V01, V02,
V03, V04, V13, V14, V15, V16,
V17, V18, V19, W02, W03, W13,
W14, W15, W16, W17, W18
NC
—
Reserved. This terminal has no connection anywhere within the package.
RSVD
RSVD
F01, R12
G06
—
—
Reserved. This terminal must be tied to ground.
Reserved. This terminal must be connected to V
or GND.
CC
RI_OUT/
PME
Ring indicate out and power management event output. This terminal provides an
output for ring-indicate or PME signals.
L05
O
Serial clock. At PRST, the SCL signal is sampled to determine if a two-wire serial
ROM is present. If the serial ROM is detected, then this terminal provides the serial
clock signaling and is implemented as open-drain. For normal operation (a ROM is
SCL
SDA
G02
I/O
implemented in the design), this terminal must be pulled high to the ROM V
a 2.7-kΩ resistor. Otherwise, it must be pulled low to ground with a 220-Ω resistor.
with
DD
Serial data. If the serial ROM is detected, then this terminal provides the serial data
signaling and is implemented as open-drain. For normal operation (a ROM is
G03
I/O
implemented in the design), this terminal must be pulled high to the ROM V
a 2.7-kΩ resistor. Otherwise, it must be pulled low to ground with a 220-Ω resistor.
with
DD
Speaker output. SPKROUT is the output to the host system that can carry SPKR
or CAUDIO through the controller from the PC Card interface. SPKROUT is driven
as the exclusive-OR combination of card SPKR//CAUDIO inputs.
H03
J05
O
I
SPKROUT
SUSPEND
Suspend. SUSPEND protects the internal registers from clearing when the GRST
or PRST signal is asserted. See Section 3.8.5, Suspend Mode, for details.
TEST0
TEST1
TEST2
TEST3
P12
U12
V12
W12
Terminals TEST0−TEST3 are used for factory test of the controller and must be
connected to ground for normal operation.
I/O
TEST4
P17
I/O Terminal TEST4 is not for customer use. It must be pulled high with a 4.7-kΩ resistor.
2−12
Table 2−10. 16-Bit PC Card Address and Data Terminals
TERMINAL
NAME
I/O
DESCRIPTION
NUMBER
D19
F15
E19
G15
F19
G18
H15
H17
H19
F18
F17
G19
H14
E18
K15
L15
A_A25
A_A24
A_A23
A_A22
A_A21
A_A20
A_A19
A_A18
A_A17
A_A16
A_A15
A_A14
A_A13
A_A12
A_A11
A_A10
A_A9
O
PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.
J15
A_A8
H18
E17
A16
E14
B15
B14
A14
C13
B13
A_A7
A_A6
A_A5
A_A4
A_A3
A_A2
A_A1
A_A0
A_D15
A_D14
A_D13
A_D12
A_D11
A_D10
A_D9
A_D8
A_D7
A_D6
A_D5
A_D4
A_D3
A_D2
A_D1
A_D0
L18
M19
M17
N19
N17
C10
A10
E11
L19
M18
M15
N18
P19
B10
F11
I/O
PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.
C11
2−13
Table 2−11. 16-Bit PC Card Interface Control Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is
used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and
BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must
be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card
is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See
Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
A_BVD1
(STSCHG/RI)
A12
I
Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery
voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is
used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and
BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must
be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card
is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See
Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
A_BVD2
(SPKR)
B12
I
Speaker. SPKR is an optional binary audio signal available only when the card and socket have been
configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the controller
and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card
that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When
a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see Section 5.2, ExCA
Interface Status Register.
N15
B11
A_CD1
A_CD2
I
L17
K18
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1
enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.
A_CE1
A_CE2
O
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the
current address.
DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC
Card that supports DMA. If it is used as a strobe, then the PC Card asserts this signal to indicate a request
for a DMA operation.
A_INPACK
C14
I
I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data output during host I/O read
cycles.
DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that
supports DMA. The controller asserts IORD during DMA transfers from the PC Card to host memory.
J18
J17
O
O
A_IORD
A_IOWR
I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O PC Cards during host I/O
write cycles.
DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that
supports DMA. The controller asserts IOWR during transfers from host memory to the PC Card.
2−14
Table 2−11. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during host
memory read cycles.
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that
supports DMA. The controller asserts OE to indicate TC for a DMA write operation.
A_OE
K17
O
Ready. The ready function is provided when the 16-bit PC Card and the host socket are configured for the
memory-only interface. READY is driven low by 16-bit memory PC Cards to indicate that the memory card
circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC
Card is ready to accept a new data transfer command.
A_READY
(IREQ)
E12
I
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a controller on the
16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is
requested.
Attribute memory select. REG remains high for all common memory accesses. When REG is asserted,
access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute
memory is a separately accessed section of card memory and is generally used to record card capacity and
other configuration and attribute information.
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card
that supports DMA. The controller asserts REG to indicate a DMA operation. REG is used in conjunction with
the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.
E13
C15
O
A_REG
A_RESET
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
A_VS1
A_VS2
A13
B16
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine
the operating voltage of the PC Card.
I/O
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in
progress.
C12
I
A_WAIT
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for
memory PC Cards that employ programmable memory technologies.
DMA terminal count. WE is used as a TC during DMA operations to a 16-bit PC Card that supports DMA.
The controller asserts WE to indicate the TC for a DMA read operation.
A_WE
G17
O
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on
16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the
address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that
is addressed is capable of 16-bit accesses.
A_WP
(IOIS16)
A11
I
DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that
supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA operation.
Table 2−12. CardBus PC Card Interface System Terminals
SOCKET A TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All
signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are
sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this
signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down
for power savings.
A_CCLK
F18
O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK
frequency, and by the controller to indicate that the CCLK frequency is going to be decreased.
A11
C15
I/O
O
A_CCLKRUN
A_CRST
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known
state. When CRST is asserted, all CardBus PC Card signals are placed in a high-impedance state, and
the controller drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but
deassertion must be synchronous to CCLK.
2−15
Table 2−13. CardBus PC Card Address and Data Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
C10
A10
F11
A_CAD31
A_CAD30
A_CAD29
A_CAD28
A_CAD27
A_CAD26
A_CAD25
A_CAD24
A_CAD23
A_CAD22
A_CAD21
A_CAD20
A_CAD19
A_CAD18
A_CAD17
A_CAD16
A_CAD15
A_CAD14
A_CAD13
A_CAD12
A_CAD11
A_CAD10
A_CAD9
A_CAD8
A_CAD7
A_CAD6
A_CAD5
A_CAD4
A_CAD3
A_CAD2
A_CAD1
A_CAD0
E11
C11
B13
C13
A14
B14
B15
E14
A16
D19
E17
F15
H19
J17
CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the
CardBus interface. During the address phase of a CardBus cycle, CAD31−CAD0 contain a 32-bit address.
During the data phase of a CardBus cycle, CAD31−CAD0 contain data. CAD31 is the most significant bit.
I/O
J15
J18
K15
K17
K18
L15
L18
L19
M17
M18
N19
M15
N17
N18
P19
CardBus bus commands and byte enables. CC/BE3−CC/BE0 are multiplexed on the same CardBus
terminals. During the address phase of a CardBus cycle, CC/BE3−CC/BE0 define the bus command. During
the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the
full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7−CAD0), CC/BE1 applies to
byte 1 (CAD15−CAD8), CC/BE2 applies to byte 2 (CAD23−CAD16), and CC/BE3 applies to byte 3
(CAD31−CAD24).
E13
E18
H18
L17
A_CC/BE3
A_CC/BE2
A_CC/BE1
A_CC/BE0
I/O
I/O
CardBus parity. In all CardBus read and write cycles, the controller calculates even parity across the CAD
and CC/BE buses. As an initiator during CardBus cycles, the controller outputs CPAR with a one-CCLK
delay. As a target during CardBus cycles, the controller compares its calculated parity to the parity indicator
of the initiator; a compare error results in a parity error assertion.
A_CPAR
H14
2−16
Table 2−14. CardBus PC Card Interface Control Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The controller
supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
A_CAUDIO
A_CBLOCK
B12
I
H15
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
N15
B11
A_CCD1
A_CCD2
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2
to identify card insertion and interrogate cards to determine the operating voltage and card type.
I
CardBus device select. The controller asserts CDEVSEL to claim a CardBus cycle as the target device.
As a CardBus initiator on the bus, the controller monitors CDEVSEL until a target responds. If no target
responds before timeout occurs, then the controller terminates the cycle with an initiator abort.
F19
E19
I/O
A_CDEVSEL
A_CFRAME
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
I/O
CardBus bus grant. CGNT is driven by the controller to grant a CardBus PC Card access to the CardBus
bus after the current data transaction has been completed.
G17
E12
O
I
A_CGNT
A_CINT
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
F17
I/O
A_CIRDY
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following the data cycle during which a parity error is detected.
G19
C14
I/O
I
A_CPERR
A_CREQ
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus
bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system errors that could lead to
catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup;
deassertion may take several CCLK periods. The controller can report CSERR to the system by assertion
of SERR on the PCI interface.
C12
I
A_CSERR
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do
not support burst data transfers.
G18
A12
G15
I/O
I
A_CSTOP
A_CSTSCHG
A_CTRDY
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as a
wake-up mechanism.
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and
CTRDY are asserted; until this time, wait states are inserted.
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.
A_CVS1
A_CVS2
A13
B16
I/O
2−17
2−18
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI1515 controller. Figure 3−1 shows the connections to the PCI1515
controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface
includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
PCI Bus
EEPROM
(Optional)
Power Switch
PC Card
PCI1515
Figure 3−1. PCI1515 System Block Diagram
3.1 Power Supply Sequencing
The PCI1515 controller contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp
voltages. The core power supply is always 1.5 V. The clamp voltages can be either 3.3 V or 5 V, depending on the
interface. The following power-up and power-down sequences are recommended.
The power-up sequence is:
1. Power core 1.5 V.
2. Apply the I/O voltage.
3. Apply the clamp voltage.
The power-down sequence is:
1. Remove the clamp voltage.
2. Remove the I/O voltage.
3. Remove power from the core.
NOTE: If the voltage regulator is enabled, then steps 2 and 3 of the power-up sequence and
steps 1 and 2 of the power-down sequence all occur simultaneously.
3.2 I/O Characteristics
The PCI1515 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI Local Bus
Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 7.2, Recommended Operating Conditions,
provides the electrical characteristics of the inputs and outputs.
3−1
V
CCP
Tied for Open Drain
OE
Pad
Figure 3−2. 3-State Bidirectional Buffer
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI1515 controller is interfaced with:
3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external
signals. The core power supply is 1.5 V and is independent of the clamping voltages. For example, PCI signaling can
be either 3.3 V or 5 V, and the PCI1515 controller must reliably accommodate both voltage levels. This is
accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system
designer desires a 5-V PCI bus, then V
can be connected to a 5-V power supply.
CCP
3.4 Peripheral Component Interconnect (PCI) Interface
The PCI1515 controller is fully compliant with the PCI Local Bus Specification. The PCI1515 controller provides all
required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment
by connecting the V
controller provides the INTA interrupt signal.
terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI1515
CCP
3.4.1 Device Resets
During the power-up sequence, GRST and PRST must be asserted. GRST is deasserted a minimum of 2 ms after
V
is stable. PRST can be deasserted a minimum of 100 µs after PCLK is stable or any time thereafter.
CC
3.4.2 PCI Bus Lock (LOCK)
The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on
the PCI1515 controller as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4
terminal by setting the appropriate values in bits 19−16 of the multifunction routing status register. See Section 4.35,
Multifunction Routing Status Register, for details. Note that the use of LOCK is only supported by PCI-to-CardBus
bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not assure control of LOCK; control of LOCK is obtained under its own protocol. It is possible for
different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal
for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter does not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A
complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete
bus LOCK must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked
operation is in progress.
The PCI1515 controller supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve
3−2
a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus
target supports delayed transactions and blocks access to the target until it completes a delayed read. This target
characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using
LOCK.
2
3.4.3 Serial EEPROM I C Bus
The PCI1515 controller offers many choices for modes of operation, and these choices are selected by programming
several configuration registers. For system board applications, these registers are normally programmed through the
BIOS routine. For add-in card and docking-station/port-replicator applications, the PCI1515 controller provides a
2
two-wire inter-integrated circuit (IIC or I C) serial bus for use with an external serial EEPROM.
The PCI1515 controller is always the bus master, and the EEPROM is always the slave. Either device can drive the
bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors on the
SCL and SDA signal lines. The PCI1515 controller is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and
SDA terminals. If the PCI1515 controller detects a logic-high level on the SCL terminal at the end of GRST, then it
2
initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I C limit of 16 Kbits can
be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the PCI1515 controller.
Figure 3−3 shows a serial EEPROM application.
2
In addition to loading configuration data from an EEPROM, the PCI1515 I C bus can be used to read and write from
2
2
other I C serial devices. A system designer can control the I C bus, using the PCI1515 controller as bus master, by
reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI
offset B3h, see Section 4.49) causes the PCI1515 controller to route the SDA and SCL signals to the SDA and SCL
terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the
serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h; see Sections
4.46, 4.47, and 4.48, respectively).
EEPROM interface status information is communicated through the serial bus control and status register (PCI offset
B3h, see Section 4.49). Bit 3 (SBDETECT) in this register indicates whether or not the PCI1515 serial ROM circuitry
detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit 0
(ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM interface is
busy).
V
CC
Serial
ROM
A0
SCL
SDA
A1 SCL
A2 SDA
PCI1515
Figure 3−3. Serial ROM Application
3.4.4 Function 0 (CardBus) Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see
Section 4.27) make up a doubleword of PCI configuration space for function 0. This doubleword register is used for
3−3
system and option card (mobile dock) identification purposes and is required by some operating systems.
Implementation of this unique identifier register is a PC 99/PC 2001 requirement.
The PCI1515 controller offers two mechanisms to load a read-only value into the subsystem registers. The first
mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system control
register (PCI offset 80h, see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem identification
value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor
ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of
implementing the serial electrically erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier via a serial EEPROM. The PCI1515 controller loads the data from the serial
EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI1515
core, including the serial-bus state machine (see Section 3.8.5, Suspend Mode, for details on using SUSPEND).
The PCI1515 controller provides a two-line serial-bus host controller that can interface to a serial EEPROM. See
Section 3.6, Serial EEPROM Interface, for details on the two-wire serial-bus controller and applications.
3.5 PC Card Applications
The PCI1515 controller supports all the PC Card features and applications as described below.
•
•
•
•
•
Card insertion/removal and recognition per the PC Card Standard (release 8.1)
Speaker and audio applications
LED socket activity indicators
PC Card controller programming model
CardBus socket registers
3.5.1 PC Card Insertion/Removal and Recognition
The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the
card type and voltage requirements of the PC Card interface.
3.5.2 Low Voltage CardBus Card Detection
The card detection logic of the PCI1515 controller includes the detection of Cardbus cards with V
= 3.3 V and
CC
V
= 1.8 V. The reporting of the 1.8-V CardBus card (V
= 3.3 V, V = 1.8 V) is reported through the socket present
PP
CC PP
state register as follows based on bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see
Section 4.30):
•
If the 12V_SW_SEL bit is 0 (TPS2228 is used), then the 1.8-V CardBus card causes the 3VCARD bit in the
socket present state register to be set.
•
If the 12V_SW_SEL bit is 1 (TPS2226A is used), then the 1.8-V CardBus card causes the XVCARD bit in
the socket present state register to be set.
3.5.3 Card Detection
The PCI1515 controller is capable of detecting USB custom cards as defined by the PC Card Standard. The detection
of these devices is made possible through circuitry included in the PCI1515 controller and the adapters used to
interface these devices with the PC Card/CardBus socket. No additional hardware requirements are placed on the
system designer in order to support these devices.
3−4
The PC Card Standard addresses the card detection and recognition process through an interrogation procedure that
the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage
requirements and interface type (16-bit vs. CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2
signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four terminals in a certain
configuration to indicate the type of card and its supply voltage requirements. The encoding scheme for this, defined
in the PC Card Standard, is shown in Table 3−1.
Table 3−1. PC Card—Card Detect and Voltage Sense Connections
CD2//CCD2
Ground
CD1//CCD1
Ground
VS2//CVS2
Open
VS1//CVS1
Open
Key
5 V
5 V
Interface
V
V
/V
CC
PP CORE
16-bit PC Card
16-bit PC Card
5 V
5 V and 3.3 V
5 V, 3.3 V, and
X.X V
Per CIS (V
Per CIS (V
Per CIS (V
)
)
)
PP
PP
PP
Ground
Ground
Open
Ground
Ground
Ground
Ground
Ground
5 V
16-bit PC Card
Ground
Ground
Ground
Ground
Open
Open
Ground
LV
LV
LV
LV
16-bit PC Card
CardBus PC Card
16-bit PC Card
3.3 V
Per CIS (V
Per CIS (V
Per CIS (V
Per CIS (V
Per CIS (V
)
)
)
)
)
PP
PP
PP
PP
PP
Connect to
CVS1
Connect to
CCD1
3.3 V
Ground
Ground
Ground
Ground
Ground
3.3 V and X.X V
3.3 V and X.X V
Connect to
CVS2
Connect to
CCD2
CardBus PC Card
Connect to
CVS1
Connect to
CCD2
3.3 V, X.X V,
and Y.Y V
Ground
Ground
Ground
LV
CardBus PC Card
Ground
Ground
Ground
Open
Open
LV
LV
16-bit PC Card
X.X V
3.3 V
Per CIS (V
)
PP
Connect to
CVS2
Connect to
CCD2
CardBus PC Card
1.8 V (V )
CORE
Connect to
CVS2
Connect to
CCD1
Ground
Open
LV
LV
LV
CardBus PC Card
CardBus PC Card
Custom Card
X.X V and Y.Y V
Y.Y V
Per CIS (V
Per CIS (V
)
PP
Connect to
CVS1
Connect to
CCD2
Ground
Open
)
PP
Connect to
CVS1
Connect to
CCD1
Ground
Ground
Ground
Per query terminals
Reserved
Connect to
CVS2
Connect to
CCD1
Ground
Reserved
3.5.4 Power Switch Interface
The power switch interface of the PCI1515 controller is a 3-pin serial interface. This 3-pin interface is implemented
such that the PCI1515 controller can connect to the TPS2228, TPS2226A, TPS2224A, TPS2223A, and TPS2220A
power switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.30) selects the
power switch that is implemented. The PCI1515 controller defaults to use the control logic for the TPS2228 power
switch. See Table 3−2 through Table 3−5 for the power switch control logic. The TPS2224A, TPS2223A, and
TPS2220A power switches have similar power control logic as the TPS2226A power switch. Refer to SLVS428A for
details.
3−5
Table 3−2. TPS2228 Control Logic—xVPP/VCORE
AVPP/VCORE CONTROL SIGNALS
OUTPUT
BVPP/VCORE CONTROL SIGNALS
OUTPUT
V_AVPP/VCORE
V_BVPP/VCORE
D8(SHDN)
D0
0
D1
0
D9
X
0
D8(SHDN)
D4
0
D5
0
D10
X
1
1
1
1
1
1
0
0 V
3.3 V
5 V
1
1
1
1
1
1
0
0 V
3.3 V
5 V
0
1
0
1
0
0
1
1
0
1
1
1
0
X
0
Hi-Z
Hi-Z
1.8 V
Hi-Z
1
0
X
Hi-Z
Hi-Z
1.8 V
Hi-Z
1
1
1
1
0
1
1
1
1
1
1
X
X
X
X
X
X
Table 3−3. TPS2228 Control Logic—xVCC
AVCC CONTROL SIGNALS
OUTPUT
V_AVCC
BVCC CONTROL SIGNALS
OUTPUT
V_BVCC
D8(SHDN)
D3
0
D2
0
D8(SHDN)
D6
0
D7
0
1
1
1
1
0
0 V
3.3 V
5 V
1
1
1
1
0
0 V
3.3 V
5 V
0
1
0
1
1
0
1
0
1
1
0 V
1
1
0 V
X
X
Hi-Z
X
X
Hi-Z
Table 3−4. TPS2226A Control Logic—xVPP
AVPP CONTROL SIGNALS
OUTPUT
V_AVPP
BVPP CONTROL SIGNALS
OUTPUT
V_BVPP
D8(SHDN)
D0
0
D1
0
D9
X
0
D8(SHDN)
D4
0
D5
0
D10
X
1
1
1
1
1
0
0 V
3.3 V
5 V
1
1
1
1
1
0
0 V
3.3 V
5 V
0
1
0
1
0
0
1
1
0
1
1
1
0
X
X
X
12 V
Hi-Z
Hi-Z
1
0
X
12 V
Hi-Z
Hi-Z
1
1
1
1
X
X
X
X
X
X
Table 3−5. TPS2226A Control Logic—xVCC
AVCC CONTROL SIGNALS
OUTPUT
V_AVCC
BVCC CONTROL SIGNALS
OUTPUT
V_BVCC
D8(SHDN)
D3
0
D2
0
D8(SHDN)
D6
0
D7
0
1
1
1
1
0
0 V
3.3 V
5 V
1
1
1
1
0
0 V
3.3 V
5 V
0
1
0
1
1
0
1
0
1
1
0 V
1
1
0 V
X
X
Hi-Z
X
X
Hi-Z
3.5.5 Internal Ring Oscillator
The internal ring oscillator provides an internal clock source for the PCI1515 controller so that neither the PCI clock
nor an external clock is required in order for the PCI1515 controller to power down a socket or interrogate a PC Card.
This internal oscillator, operating nominally at 16 kHz, is always enabled.
3.5.6 Integrated Pullup Resistors for PC Card Interface
The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card
configurations. The PCI1515 controller has integrated all of these pullup resistors and requires no additional external
components. The I/O buffer on the BVD1(STSCHG)/CSTSCHG terminal has the capability to switch to an internal
pullup resistor when a 16-bit PC Card is inserted, or switch to an internal pulldown resistor when a CardBus card is
inserted. This prevents inadvertent CSTSCHG events.
3−6
3.5.7 SPKROUT and CAUDPWM Usage
The SPKROUT terminal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is
configured for I/O mode, the BVD2 terminal becomes the SPKR input terminal from the card. This terminal, in
CardBus applications, is referred to as CAUDIO. SPKR passes a TTL-level binary audio signal to the PCI1515
controller. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform as well as a PWM signal.
The binary audio signal from the PC Card socket is enabled by bit 1 (SPKROUTEN) of the card control register (PCI
offset 91h, see Section 4.37).
Older controllers support CAUDIO in binary or PWM mode, but use the same output terminal (SPKROUT). Some
audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM.
The PCI1515 implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal.
Bit 2 (AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM terminal
to CAUDPWM. See Section 4.35, Multifunction Routing Register, for details on configuring the MFUNC terminals.
Figure 3−4 illustrates the SPKROUT connection.
System
Core Logic
BINARY_SPKR
SPKROUT
Speaker
Subsystem
PCI1515
PWM_SPKR
CAUDPWM
Figure 3−4. SPKROUT Connection to Speaker Driver
3.5.8 LED Socket Activity Indicators
The socket activity LED is provided to indicate when a PC Card is being accessed. The LEDA1 signal can be routed
to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate
socket activity. LEDA1 indicates socket A (card A) activity. The LED_SKT output also indicates socket activity for
socket A for compatibility with two socket controllers. See Section 4.35, Multifunction Routing Status Register, for
details on configuring the multifunction terminals.
The active-high LED signal is driven for 64 ms. When the LED is not being driven high, it is driven to a low state. Either
of the two circuits shown in Figure 3−5 can be implemented to provide LED signaling, and the board designer must
implement the circuit that best fits the application.
The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity
signals are pulsed when READY(IREQ) is low. For CardBus cards, the LED activity signals are pulsed if CFRAME,
IRDY, or CREQ are active.
Current Limiting
R ≈ 150 Ω
MFUNCx
Socket A
LED
PCI1515
Figure 3−5. Sample LED Circuit
As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
3−7
If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven.
3.5.9 CardBus Socket Registers
The PCI1515 controller contains all registers for compatibility with the PCI Local Bus Specification and the PC Card
Standard. These registers, which exist as the CardBus socket registers, are listed in Table 3−6.
Table 3−6. CardBus Socket Registers
REGISTER NAME
OFFSET
00h
Socket event
Socket mask
04h
Socket present state
Socket force event
Socket control
08h
0Ch
10h
Reserved
14h−1Ch
20h
Socket power management
3.6 Serial EEPROM Interface
The PCI1515 controller has a dedicated serial bus interface that can be used with an EEPROM to load certain
registers in the PCI1515 controller. The EEPROM is detected by a pullup resistor on the SCL terminal. See Table 3−8
for the EEPROM loading map.
3.6.1 Serial-Bus Interface Implementation
The PCI1515 controller drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency
2
for standard mode I C. The serial EEPROM must be located at address A0h.
Some serial device applications may include PC Card power switches, card ejectors, or other devices that may
enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed
in the sections that follow.
3.6.2 Accessing Serial-Bus Devices Through Software
The PCI1515 controller provides a programming mechanism to control serial bus devices through software. The
programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−7 lists the
registers used to program a serial-bus device through software.
Table 3−7. PCI1515 Registers Used to Program Serial-Bus Devices
PCI OFFSET
REGISTER NAME
DESCRIPTION
B0h
Serial-bus data
Contains the data byte to send on write commands or the received data byte on read commands.
The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
B1h
B2h
B3h
Serial-bus index
Serial-bus slave
address
Write transactions to this register initiate a serial-bus transaction. The slave device address and the
R/W command selector are programmed through this register.
Serial-bus control
and status
Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol-select bit is programmed through this register.
3.6.3 Serial-Bus Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−3.
2
The PCI1515 controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode I C using
7-bit addressing.
3−8
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as shown
in Figure 3−6. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high
transition of SDA while SCL is in the high state, as shown in Figure 3−6. Data on SDA must remain stable during the
high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control
signals, that is, a start or a stop condition.
SDA
SCL
Start
Stop
Change of
Condition
Condition
Data Allowed
Data Line Stable,
Data Valid
Figure 3−6. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−7
illustrates the acknowledge protocol.
SCL From
1
2
3
7
8
9
Master
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3−7. Serial-Bus Protocol Acknowledge
The PCI1515 controller is a serial bus master; all other devices connected to the serial bus external to the PCI1515
controller are slave devices. As the bus master, the PCI1515 controller drives the SCL clock at nearly 100 kHz during
bus cycles and places SCL in a high-impedance state (zero frequency) during idle states.
Typically, the PCI1515 controller masters byte reads and byte writes under software control. Doubleword reads are
performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software
control. See Section 3.6.4, Serial-Bus EEPROM Application, for details on how the PCI1515 controller automatically
loads the subsystem identification and other register defaults through a serial-bus EEPROM.
Figure 3−8 illustrates a byte write. The PCI1515 controller issues a start condition and sends the 7-bit slave device
address and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The slave
device acknowledges if it recognizes the address. If no acknowledgment is received by the PCI1515 controller, then
an appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see Section 4.49). The word
address byte is then sent by the PCI1515 controller, and another slave acknowledgment is expected. Then the
PCI1515 controller delivers the data byte MSB first and expects a final acknowledgment before issuing the stop
condition.
3−9
Slave Address
Word Address
Data Byte
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
P
R/W
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3−8. Serial-Bus Protocol—Byte Write
Figure 3−9 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command
bit must be set to 1 to indicate a read-data transfer. In addition, the PCI1515 master must acknowledge reception
of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers.
The SCL signal remains driven by the PCI1515 master.
Slave Address
Word Address
Slave Address
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
b6 b5 b4 b3 b2 b1 b0
1
A
Start
R/W
Restart
R/W
Data Byte
b7 b6 b5 b4 b3 b2 b1 b0
M
P
Stop
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3−9. Serial-Bus Protocol—Byte Read
Figure 3−10 illustrates EEPROM interface doubleword data collection protocol.
Slave Address
Word Address
Slave Address
S
1
0
1
0
0
0
0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
1
0
1
0
0
0
0
1
A
Start
R/W
Restart
R/W
Data Byte 3
M
Data Byte 2
M
Data Byte 1
M
Data Byte 0
M
P
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3−10. EEPROM Interface Doubleword Data Collection
3.6.4 Serial-Bus EEPROM Application
When the PCI bus is reset and the serial-bus interface is detected, the PCI1515 controller attempts to read the
subsystem identification and other register defaults from a serial EEPROM.
This format must be followed for the PCI1515 controller to load initializations from a serial EEPROM. All bit fields must
be considered when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the PCI1515 controller. All hardware address bits
for the EEPROM must be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application (Figure 3−10) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs
to the chip, and the sample application shows these terminal inputs tied to GND.
3−10
Table 3−8. EEPROM Loading Map
SERIAL ROM
OFFSET
BYTE DESCRIPTION
00h
01h
CardBus function indicator (00h)
Number of bytes (20h)
PCI 04h, command register, function 0, bits 8, 6−5, 2−0
02h
[7]
[6]
[5]
[4:3]
[2]
[1]
[0]
Command
Command
Command
RSVD
Command
Command
Command
register, bit 8
register, bit 6
register, bit 5
register, bit 2
register, bit 1
register, bit 0
PCI 04h, command register, function 1, bits 8, 6−5, 2−0
03h
[7]
[6]
[5]
[4:3]
[2]
[1]
[0]
Command
Command
Command
RSVD
Command
Command
Command
register, bit 8
register, bit 6
register, bit 5
register, bit 2
register, bit 1
register, bit 0
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
PCI 40h, subsystem vendor ID, byte 0
PCI 41h, subsystem vendor ID, byte 1
PCI 42h, subsystem ID, byte 0
PCI 43h, subsystem ID, byte 1
PCI 44h, PC Card 16-bit I/F legacy mode base address register, byte 0, bits 7−1
PCI 45h, PC Card 16-bit I/F legacy mode base address register, byte 1
PCI 46h, PC Card 16-bit I/F legacy mode base address register, byte 2
PCI 47h, PC Card 16-bit I/F legacy mode base address register, byte 3
PCI 80h, system control, function 0, byte 0, bits 6−0
PCI 80h, system control, function 1, byte 0, bit 2
PCI 81h, system control, byte 1
Reserved load all 0s (PCI 82h, system control, byte 2)
PCI 83h, system control, byte 3
PCI 8Ch, MFUNC routing, byte 0
PCI 8Dh, MFUNC routing, byte 1
PCI 8Eh, MFUNC routing, byte 2
PCI 8Fh, MFUNC routing, byte 3
PCI 90h, retry status, bits 7, 6
PCI 91h, card control, bit 7
PCI 92h, device control, bits 6, 5, 3−0
PCI 93h, diagnostic, bits 7, 4−0
PCI A2h, power-management capabilities, function 0, bit 15 (bit 7 of EEPROM offset 16h corresponds to bit 15)
PCI A2h, power-management capabilities, function 1, bit 15 (bit 7 of EEPROM offset 16h corresponds to bit 15)
CB Socket + 0Ch, function 0 socket force event, bit 27 (bit 3 of EEPROM offset 17h corresponds to bit 27)
CB Socket + 0Ch, function 1 socket force event, bit 27 (bit 3 of EEPROM offset 18h corresponds to bit 27)
ExCA 00h, ExCA identification and revision, bits 7−0
PCI 86h, general control, byte 0, bits 7−0
PCI 87h, general control, byte 1, bits 7, 6, 4−0
PCI 89h, GPE enable, bits 7, 6, 4−0
PCI 8Bh, general-purpose output, bits 4−0
End-of-list indicator (80h)
3−11
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI1515 controller. The PCI1515 controller provides several interrupt signaling schemes to accommodate the needs
of a variety of platforms. The different mechanisms for dealing with interrupts in this controller are based on various
specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card
functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The
PCI1515 controller is, therefore, backward compatible with existing interrupt control register definitions, and new
registers have been defined where required.
The PCI1515 controller detects PC Card interrupts and events at the PC Card interface and notifies the host controller
using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1515 controller,
PC Card interrupts are classified either as card status change (CSC) or as functional interrupts.
The method by which any type of PCI1515 interrupt is communicated to the host interrupt controller varies from
system to system. The PCI1515 controller offers system designers the choice of using parallel PCI interrupt signaling,
parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible
to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections
that follow. All interrupt signaling is provided through the seven multifunction terminals, MFUNC0−MFUNC6.
3.7.1 PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
PCI1515 controller and may warrant notification of host card and socket services software for service. CSC events
include both card insertion and removal from the PC Card socket, as well as transitions of certain PC Card signals.
Table 3−9 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards
that can be inserted into any PC Card socket are:
•
•
•
16-bit memory card
16-bit I/O card
CardBus cards
Table 3−9. Interrupt Mask and Flag Registers
CARD TYPE
EVENT
MASK
ExCA offset 05h/805h bits 1 and 0
ExCA offset 05h/805h bit 2
ExCA offset 05h/805h bit 0
Always enabled
FLAG
Battery conditions (BVD1, BVD2)
Wait states (READY)
ExCA offset 04h/804h bits 1 and 0
ExCA offset 04h/804h bit 2
ExCA offset 04h/804h bit 0
PCI configuration offset 91h bit 0
16-bit memory
16-bit I/O
16-bit I/O
Change in card status (STSCHG)
Interrupt request (IREQ)
All 16-bit PC
Cards/
Smart Card
adapters
Power cycle complete
ExCA offset 05h/805h bit 3
ExCA offset 04h/804h bit 3
Change in card status (CSTSCHG)
Interrupt request (CINT)
Socket mask bit 0
Always enabled
Socket event bit 0
PCI configuration offset 91h bit 0
Socket event bit 3
CardBus
Power cycle complete
Socket mask bit 3
Socket mask bits 2 and 1
Card insertion or removal
Socket event bits 2 and 1
Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the
card type.
3−12
Table 3−10. PC Card Interrupt Events and Description
CARD TYPE
EVENT
TYPE
SIGNAL
DESCRIPTION
A transition on BVD1 indicates a change in the
PC Card battery conditions.
BVD1(STSCHG)//CSTSCHG
Battery conditions
(BVD1, BVD2)
CSC
A transition on BVD2 indicates a change in the
PC Card battery conditions.
BVD2(SPKR)//CAUDIO
READY(IREQ)//CINT
16-bit
memory
A transition on READY indicates a change in the
ability of the memory PC Card to accept or provide
data.
Wait states
(READY)
CSC
Change in card
status (STSCHG)
The assertion of STSCHG indicates a status change
on the PC Card.
16-bit I/O
16-bit I/O
CSC
Functional
CSC
BVD1(STSCHG)//CSTSCHG
READY(IREQ)//CINT
Interrupt request
(IREQ)
The assertion of IREQ indicates an interrupt request
from the PC Card.
Change in card
status (CSTSCHG)
The assertion of CSTSCHG indicates a status
change on the PC Card.
BVD1(STSCHG)//CSTSCHG
READY(IREQ)//CINT
CardBus
Interrupt request
(CINT)
The assertion of CINT indicates an interrupt request
from the PC Card.
Functional
A transition on either CD1//CCD1 or CD2//CCD2
indicates an insertion or removal of a 16-bit or
CardBus PC Card.
Card insertion
or removal
CD1//CCD1,
CD2//CCD2
CSC
CSC
All PC Cards/
Smart Card
adapters
Power cycle
complete
An interrupt is generated when a PC Card power-up
cycle has completed.
N/A
The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For
example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for
CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in
parentheses. The CardBus signal name follows after a double slash (//).
The 1997 PC Card Standard describes the power-up sequence that must be followed by the PCI1515 controller when
an insertion event occurs and the host requests that the socket V
and V be powered. Upon completion of this
CC
PP
power-up sequence, the PCI1515 interrupt scheme can be used to notify the host system (see Table 3−10), denoted
by the power cycle complete event. This interrupt source is considered a PCI1515 internal event, because it depends
on the completion of applying power to the socket rather than on a signal change at the PC Card interface.
3.7.2 Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−10 by setting
the appropriate bits in the PCI1515 controller. By individually masking the interrupt sources listed, software can
control those events that cause a PCI1515 interrupt. Host software has some control over the system interrupt the
PCI1515 controller asserts by programming the appropriate routing registers. The PCI1515 controller allows host
software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing
somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections.
When an interrupt is signaled by the PCI1515 controller, the interrupt service routine must determine which of the
events listed in Table 3−9 caused the interrupt. Internal registers in the PCI1515 controller provide flags that report
the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be
taken.
Table 3−9 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Notice that there is not a mask bit to stop the PCI1515 controller from passing PC Card functional interrupts through
to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there must
never be a card interrupt that does not require service after proper initialization.
3−13
Table 3−9 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC
Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the
flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by
bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20), and defaults to the
flag-cleared-on-read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event
register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software must not program the chip through both register sets when a CardBus card is functioning.
3.7.3 Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6−MFUNC0, implemented in the PCI1515 controller can be routed to
obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use
the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see
Section 4.38), to select the parallel IRQ signaling scheme. See Section 4.35, Multifunction Routing Status Register,
for details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement
is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal
for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ9, IRQ10,
and IRQ15. The multifunction routing status register must be programmed to a value of 0A9F 5432h. This value
routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3−11. Not
shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that
provides parallel PCI interrupts to the host.
PCI6515
MFUNC1
PIC
IRQ3
IRQ4
IRQ5
IRQ15
IRQ9
IRQ10
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
Figure 3−11. IRQ Implementation
Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ
configuration of a system implementing the PCI1515 controller. The multifunction routing status register is a global
register that is shared between the four PCI1515 functions. See Section 4.35, Multifunction Routing Status Register,
for details on configuring the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the PCI1515 controller makes
available.
3.7.4 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. The INTA interrupt signal is routed to the MFUNC0 terminal.
3−14
3.7.5 Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI1515 controller uses a single terminal to communicate all
interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle,
multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The
packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For
details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
3.7.6 SMI Support in the PCI1515 Controller
The PCI1515 controller provides a mechanism for interrupting the system when power changes have been made to
the PC Card socket interface. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI)
scheme. SMI interrupts are generated by the PCI1515 controller, when enabled, after a write cycle to the socket
control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA
offset 02h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−11 describes the SMI control
bits function.
Table 3−11. SMI Control
BIT NAME
SMIROUTE
SMISTAT
FUNCTION
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
When set, SMI interrupt generation is enabled.
SMIENB
The CSC interrupt can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control
register (ExCA offset 1Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.35).
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the PCI1515 controller, various features are
designed into the controller to allow implementation of popular power-saving techniques. These features and
techniques are as follows:
•
•
•
•
•
•
•
•
Clock run protocol
Cardbus PC Card power management
16-bit PC Card power management
Suspend mode
Ring indicate
PCI power management
Cardbus bridge power management
ACPI support
3−15
PCI Bus
Power Switch
EEPROM
PCI1515
PC Card
†
The system connection to GRST is implementation-specific. GRST must be asserted on initial power up of the PCI1515 controller. PRST must
be asserted for subsequent warm resets.
Figure 3−12. System Diagram Implementing CardBus Device Class Power Management
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR)
The PCI1515 controller requires 1.5-V core voltage. The core power can be supplied by the PCI1515 controller itself
using the internal LDO-VR. The core power can alternatively be supplied by an external power supply through the
VR_PORT terminal. Table 3−12 lists the requirements for both the internal core power supply and the external core
power supply.
Table 3−12. Requirements for Internal/External 1.5-V Core Power Supply
SUPPLY
V
CC
VR_EN
VR_PORT NOTE
Internal
3.3 V
GND
1.5-V output Internal 1.5-V LDO-VR is enabled. A 1.0-µF bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
External
3.3 V
V
CC
1.5-V input Internal 1.5-V LDO-VR is disabled. An external 1.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1-µF bypass capacitor on the VR_PORT terminal is required.
3.8.2 CardBus (Function 0) Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1515 controller.
CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this
is not always available to the system designer, and alternate power-saving features are provided. For details on the
CLKRUN protocol see the PCI Mobile Design Guide.
The PCI1515 controller does not permit the central resource to stop the PCI clock under any of the following
conditions:
•
•
•
•
•
•
•
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
The 16-bit PC Card resource manager is busy.
The PCI1515 CardBus master state machine is busy. A cycle may be in progress on CardBus.
The PCI1515 master is busy. There may be posted data from CardBus to PCI in the PCI1515 controller.
Interrupts are pending.
The CardBus CCLK for the socket has not been stopped by the PCI1515 CCLKRUN manager.
PC Card interrogation is in progress.
3−16
The PCI1515 controller restarts the PCI clock using the CLKRUN protocol under any of the following conditions:
•
•
•
•
•
•
•
•
A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.
A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in the socket.
A CardBus attempts to start the CCLK using CCLKRUN.
A CardBus card arbitrates for the CardBus bus using CREQ.
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
Data is in any of the FIFOs (receive or transmit).
The master state machine is busy.
There are pending interrupts.
3.8.3 CardBus PC Card Power Management
The PCI1515 controller implements its own card power-management engine that can turn off the CCLK to a socket
when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN
interface to control this clock management.
3.8.4 16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/802h, see Section 5.3) and PWRDWN bit
(bit 0) of the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20) are provided for 16-bit PC Card
power management. The COE bit places the card interface in a high-impedance state to save power. The power
savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN bit does
not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function when
there is no card activity.
NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3.8.5 Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the PCI1515 controller. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the
PCI1515 controller in order to minimize power consumption.
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor
an external clock is routed to the serial-interrupt state machine. Figure 3−13 is a signal diagram of the suspend
function.
3−17
RESET
GNT
SUSPEND
PCLK
External Terminals
Internal Signals
RESETIN
SUSPENDIN
PCLKIN
Figure 3−13. Signal Diagram of Suspend Function
3.8.6 Requirements for Suspend Mode
The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which
would require the reconfiguration of the PCI1515 controller by software. Asserting the SUSPEND signal places the
PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless
a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the
PCI1515 controller when SUSPEND is asserted because the outputs are in a high-impedance state.
The GPIOs, MFUNC signals, and RI_OUT signal are all active during SUSPEND, unless they are disabled in the
appropriate PCI1515 registers.
3.8.7 Ring Indicate
The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode
and wake-up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform
requirements. RI_OUT on the PCI1515 controller can be asserted under any of the following conditions:
•
A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an
incoming call.
•
•
A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake-up.
A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery
voltage levels.
Figure 3−14 shows various enable bits for the PCI1515 RI_OUT function; however, it does not show the masking of
CSC events. See Table 3−9 for a detailed description of CSC interrupt masks and flags.
3−18
RI_OUT Function
RIENB
CSTSMASK
CSC
PC Card
Socket A
RINGEN
Card
I/F
RI_OUT
RI
CDRESUME
CSC
Figure 3−14. RI_OUT Functional Diagram
RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register
(ExCA offset 03h/803h, see Section 5.4). This is only applicable when a 16-bit card is powered in the socket.
The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit (bit 0, CSTSMASK) is programmed through the socket mask register (CB offset 04h, see Section 6.2) in the
CardBus socket registers.
RI_OUT can be routed through any of three different pins, RI_OUT/PME, MFUNC2, or MFUNC4. The RI_OUT
function is enabled by setting bit 7 (RIENB) in the card control register (PCI offset 91h, see Section 4.37). The PME
function is enabled by setting bit 8 (PME_ENABLE) in the power-management control/status register (PCI offset A4h,
see Section 4.43). When bit 0 (RIMUX) in the system control register (PCI offset 80h, see Section 4.29) is set to 0,
both the RI_OUT function and the PME function are routed to the RI_OUT/PME terminal. If both functions are enabled
and RIMUX is set to 0, then the RI_OUT/PME terminal becomes RI_OUT only and PME assertions are never seen.
Therefore, in a system using both the RI_OUT function and the PME function, RIMUX must be set to 1 and RI_OUT
must be routed to either MFUNC2 or MFUNC4.
3.8.8 PCI Power Management (Function 0)
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure
required to let the operating system control the power of PCI functions. This is done by defining a standard PCI
interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can
be assigned one of seven power-management states, resulting in varying levels of power savings.
The seven power-management states of PCI functions are:
•
•
•
•
•
•
•
D0-uninitialized − Before controller configuration, controller not fully functional
D0-active − Fully functional state
D1 − Low-power state
D2 − Low-power state
D3 − Low-power state. Transition state before D3
hot
cold
D3
− PME signal-generation capable. Main power is removed and VAUX is available.
cold
D3 − No power and completely nonfunctional
off
NOTE 1: In the D0-uninitialized state, the PCI1515 controller does not generate PME and/or interrupts. When bits 0 (IO_EN) and 1 (MEM_EN)
of the command register (PCI offset 04h, see Section 4.4) are both set, the PCI1515 controller switches the state to D0-active. Transition
from D3
cold
to the D0-uninitialized state happens at the deassertion of PRST. The assertion of GRST forces the controller to the
D0-uninitialized state immediately.
NOTE 2: The PWR_STATE bits (bits 1−0) of the power-management control/status register (PCI offset A4h, see Section 4.43) only code for four
power states, D0, D1, D2, and D3 . The differences between the three D3 states is invisible to the software because the controller
hot
is not accessible in the D3
or D3 state.
off
cold
Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power
state of the originating bridge device.
3−19
For the operating system (OS) to manage the controller power states on the PCI bus, the PCI function must support
four power-management operations. These operations are:
•
•
•
•
Capabilities reporting
Power status reporting
Setting the power state
System wake-up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI
offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1515 controller,
a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h.
The first byte of each capability register block is required to be a unique ID of that capability. PCI power management
has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there
are no more items in the list, then the next item pointer must be set to 0. The registers following the next item pointer
are specific to the capability of the function. The PCI power-management capability implements the register block
outlined in Table 3−13.
Table 3−13. Power-Management Registers
REGISTER NAME
Power-management capabilities
Power-management control/status register bridge support extensions
OFFSET
A0h
Next item pointer
Capability ID
Data
Power-management control/status (CSR)
A4h
The power-management capabilities register (PCI offset A2h, see Section 4.42) provides information on the
capabilities of the function related to power management. The power-management control/status register (PCI offset
A4h, see Section 4.43) enables control of power-management states and enables/monitors power-management
events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges.
3.8.9 CardBus Bridge Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power
Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed
in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3 or D3
without losing wake-up context (also called PME context).
hot
cold
The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
for D3 wake-up are as follows:
•
Preservation of device context. The specification states that a reset must occur during the transition from
D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear
the PME context registers.
•
Power source in D3
if wake-up support is required from this state.
cold
The Texas Instruments PCI1515 controller addresses these D3 wake-up issues in the following manner:
Two resets are provided to handle preservation of PME context bits:
•
−
Global reset (GRST) is used only on the initial boot up of the system after power up. It places the
PCI1515 controller in its default state and requires BIOS to configure the controller before becoming
fully functional.
−
PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled,
then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.
Please see the master list of PME context bits in Section 3.8.11.
3−20
•
Power source in D3
auxiliary power source must be supplied to the PCI1515 V
if wake-up support is required from this state. Since V
is removed in D3
, an
cold
CC
cold
terminals. Consult the PCI14xx
CC
Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to
CardBus Bridges for further information.
3.8.10 ACPI Support
The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The PCI1515 controller offers a generic interface that is
compliant with ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI1515 PCI configuration space at offset
88h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event
status and enable bits reside in the general-purpose event status register (PCI offset 88h, see Section 4.31) and
general-purpose event enable register (PCI offset 89h, see Section 4.32). The status and enable bits are
implemented as defined by ACPI and illustrated in Figure 3−15.
Status Bit
Event Input
Event Output
Enable Bit
Figure 3−15. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.
3.8.11 Master List of PME Context Bits and Global Reset-Only Bits
PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit, bit 8 of the
power management control/status register (PCI offset A4h, see Section 4.43) is set. If PME is not enabled, then these
bits are cleared when either PRST or GRST is asserted.
The PME context bits (function 0) are:
•
•
•
•
•
•
•
•
•
•
•
•
Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6
System control register (PCI offset 80h, see Section 4.29): bits 10−8
Power management control/status register (PCI offset A4h, see Section 4.43): bit 15
ExCA power control register (ExCA 802h, see Section 5.3): bits 7, 5 (82365SL mode only), 4, 3, 1, 0
ExCA interrupt and general control (ExCA 803h, see Section 5.4): bits 6, 5
ExCA card status-change register (ExCA 804h, see Section 5.5): bits 3−0
ExCA card status-change interrupt configuration register (ExCA 805h, see Section 5.6): bits 3−0
ExCA card detect and general control register (ExCA 816h, see Section 5.19): bits 7, 6
Socket event register (CardBus offset 00h, see Section 6.1): bits 3−0
Socket mask register (CardBus offset 04h, see Section 6.2): bits 3−0
Socket present state register (CardBus offset 08h, see Section 6.3): bits 13−7, 5−1
Socket control register (CardBus offset 10h, see Section 6.5): bits 6−4, 2−0
Global reset-only bits, as the name implies, are cleared only by GRST. These bits are never cleared by PRST,
regardless of the setting of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means
that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register contents. Figure 3−12 is
a diagram showing the application of GRST and PRST.
3−21
The global reset-only bits (function 0) are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Status register (PCI offset 06h, see Section 4.5): bits 15−11, 8
Secondary status register (PCI offset 16h, see Section 4.14): bits 15−11, 8
Subsystem vendor ID register (PCI offset 40h, see Section 4.26): bits 15–0
Subsystem ID register (PCI offset 42h, see Section 4.27): bits 15–0
PC Card 16-bit I/F legacy-mode base-address register (PCI offset 44h, see Section 4.28): bits 31−0
System control register (PCI offset 80h, see Section 4.29): bits 31−24, 22−13, 11, 6−0
General control register (PCI offset 86h, see Section 4.30): bits 13−10, 7, 5−3, 1, 0
General-purpose event status register (PCI offset 88h, see Section 4.31): bits 7, 6, 4−0
General-purpose event enable register (PCI offset 89h, see Section 4.32): bits 7, 6, 4−0
General-purpose output register (PCI offset 8Bh, see Section 4.34): bits 4−0
Multifunction routing register (PCI offset 8Ch, see Section 4.35): bits 31−0
Retry status register (PCI offset 90h, see Section 4.36): bits 7−5, 3, 1
Card control register (PCI offset 91h, see Section 4.37): bits 7, 2−0
Device control register (PCI offset 92h, see Section 4.38): bits 7−5, 3−0
Diagnostic register (PCI offset 93h, see Section 4.39): bits 7−0
Power management capabilities register (PCI offset A2h, see Section 4.42): bit 15
Power management CSR register (PCI offset A4h, see Section 4.43): bits 15, 8
Serial bus data register (PCI offset B0h, see Section 4.46): bits 7−0
Serial bus index register (PCI offset B1h, see Section 4.47): bits 7−0
Serial bus slave address register (PCI offset B2h, see Section 4.48): bits 7−0
Serial bus control/status register (PCI offset B3h, see Section 4.49): bits 7, 3−0
ExCA identification and revision register (ExCA 800h, see Section 5.1): bits 7−0
ExCA global control register (ExCA 81Eh, see Section 5.20): bits 2−0
CardBus socket power management register (CardBus 20h, see Section 6.6): bits 25, 24
3−22
4 PC Card Controller Programming Model
This chapter describes the PCI1515 PCI configuration registers that make up the 256-byte PCI configuration header
for each PCI1515 function.
Any bit followed by a † is not cleared by the assertion of PRST (see CardBus Bridge Power Management,
Section 3.8.9, for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared only by
GRST. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes referred to
as PME context bits and are implemented to allow PME context to be preserved during the transition from D3
or
hot
D3
to D0.
cold
If a bit is followed by a ‡, then this bit is cleared only by GRST in all cases (not conditional on PME being enabled).
These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm
resets.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
Table 4−1. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
Read
Write
Set
MEANING
R
W
S
Field can be read by software.
Field can be written by software to any value.
Field can be set by a write of 1. Writes of 0 have no effect.
Field can be cleared by a write of 1. Writes of 0 have no effect.
Field can be autonomously updated by the PCI1515 controller.
C
U
Clear
Update
4.1 PCI Configuration Register Map (Function 0)
The PCI1515 controller is a single function PC Card controller (PCI function 0). The configuration header, compliant
with the PCI Local Bus Specification as a CardBus bridge header, is PC99/PC2001 compliant as well. Table 4−2
illustrates the PCI configuration register map, which includes both the predefined portion of the configuration space
and the user-definable registers.
Table 4−2. Function 0 PCI Configuration Register Map
REGISTER NAME
OFFSET
00h
Device ID
Status ‡
Vendor ID
Command
04h
Class code
Header type
Revision ID
08h
BIST
Latency timer
Cache line size
0Ch
10h
CardBus socket registers/ExCA base address register
Secondary status ‡
CardBus latency timer Subordinate bus number
Reserved
Capability pointer
PCI bus number
14h
CardBus bus number
18h
CardBus memory base register 0
1Ch
20h
CardBus memory limit register 0
CardBus memory base register 1
CardBus memory limit register 1
24h
28h
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−1
Table 4−2. Function 0 PCI Configuration Register Map (Continued)
REGISTER NAME
OFFSET
2Ch
CardBus I/O base register 0
CardBus I/O limit register 0
CardBus I/O base register 1
CardBus I/O limit register 1
30h
34h
38h
Bridge control †
Subsystem ID ‡
Interrupt pin
Interrupt line
3Ch
Subsystem vendor ID ‡
40h
PC Card 16-bit I/F legacy-mode base-address ‡
44h
Reserved
48h−7Ch
80h
System control †‡
General control ‡
Reserved
84h
General-purpose event
General-purpose event
status ‡
General-purpose output ‡
General-purpose input
88h
enable ‡
Multifunction routing status ‡
8Ch
90h
Diagnostic ‡
Device control ‡
Card control ‡
Retry status ‡
Capability ID
Reserved
94h−9Ch
A0h
Power management capabilities ‡
Next item pointer
Power management
control/status bridge support
extensions
Power management data
(Reserved)
A4h
Power management control/status †‡
Reserved
Serial bus slave address ‡
Reserved
A8h−ACh
B0h
Serial bus control/status ‡
Serial bus index ‡
Serial bus data ‡
B4h−FCh
†
‡
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.
4.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Offset:
Type:
Vendor ID
00h (Function 0)
Read-only
104Ch
Default:
4−2
4.3 Device ID Register Function 0
This read-only register contains the device ID assigned by TI to the PCI1515 CardBus controller functions (PCI
function 0).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID—Smart Card enabled
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
1
R
1
R
0
Register:
Offset:
Type:
Device ID
02h (Function 0)
Read-only
8036h
Default:
4.4 Command Register
The PCI command register provides control over the PCI1515 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification (see Table 4−3).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Command
R
0
R
0
R
0
R
0
R
0
RW
0
R
0
RW
0
R
0
RW
0
RW
0
R
0
R
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Command
04h
Read-only, Read/Write
0000h
Default:
4−3
Table 4−3. Command Register Description
FUNCTION
BIT
SIGNAL
TYPE
15−11
RSVD
R
Reserved. Bits 15−11 return 0s when read.
INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
10
9
INT_DISABLE
FBB_EN
RW
R
1 = INTx assertion is disabled
Fast back-to-back enable. The PCI1515 controller does not generate fast back-to-back transactions;
therefore, this bit is read-only. This bit returns a 0 when read.
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the PCI1515 controller to report address parity errors.
8
7
6
SERR_EN
RSVD
RW
R
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
Reserved. Bit 7 returns 0 when read.
Parity error response enable. This bit controls the PCI1515 response to parity errors through the PERR
signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by
asserting SERR.
PERR_EN
RW
0 = PCI1515 controller ignores detected parity errors (default).
1 = PCI1515 controller responds to detected parity errors.
VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI1515 controller does not
respond to palette register writes and snoops the data). When the bit is 0, the PCI1515 controller treats
all palette accesses like all other accesses.
5
4
3
2
VGA_EN
MWI_EN
SPECIAL
MAST_EN
RW
R
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI1515 controller does not support memory write-and-invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI1515
controller does not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
R
Bus master control. This bit controls whether or not the PCI1515 controller can act as a PCI bus initiator
(master). The PCI1515 controller can take control of the PCI bus only when this bit is set.
0 = Disables the PCI1515 ability to generate PCI bus accesses (default)
RW
1 = Enables the PCI1515 ability to generate PCI bus accesses
Memory space enable. This bit controls whether or not the PCI1515 controller can claim cycles in PCI
memory space.
1
0
MEM_EN
IO_EN
RW
RW
0 = Disables the PCI1515 response to memory space accesses (default)
1 = Enables the PCI1515 response to memory space accesses
I/O space control. This bit controls whether or not the PCI1515 controller can claim cycles in PCI I/O space.
0 = Disables the PCI1515 controller from responding to I/O space accesses (default)
1 = Enables the PCI1515 controller to respond to I/O space accesses
4−4
4.5 Status Register
The status register provides device information to the host system. Bits in this register can be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. See Table 4−4 for a
complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Status
RW
0
RW
0
RW
0
RW
0
RW
0
R
0
R
1
RW
0
R
0
R
0
R
0
R
1
RU
0
R
0
R
0
R
0
Register:
Offset:
Type:
Status
06h (Function 0)
Read-only, Read/Write
0210h
Default:
Table 4−4. Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. This bit is set when a parity error is detected, either an address or data parity error.
Write a 1 to clear this bit.
15 ‡
PAR_ERR
RW
Signaled system error. This bit is set when SERR is enabled and the PCI1515 controller signaled a system
error to the host. Write a 1 to clear this bit.
14 ‡
13 ‡
12 ‡
11 ‡
10−9
SYS_ERR
MABORT
RW
RW
RW
RW
R
Received master abort. This bit is set when a cycle initiated by the PCI1515 controller on the PCI bus has
been terminated by a master abort. Write a 1 to clear this bit.
Received target abort. This bit is set when a cycle initiated by the PCI1515 controller on the PCI bus was
terminated by a target abort. Write a 1 to clear this bit.
TABT_REC
TABT_SIG
PCI_SPEED
Signaled target abort. This bit is set by the PCI1515 controller when it terminates a transaction on the PCI
bus with a target abort. Write a 1 to clear this bit.
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the
PCI1515 controller asserts this signal at a medium speed on nonconfiguration cycle accesses.
Data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. PERR was asserted by any PCI device including the PCI1515 controller.
b. The PCI1515 controller was the bus master during the data parity error.
c. The parity error response bit is set in the command register.
8 ‡
DATAPAR
RW
Fast back-to-back capable. The PCI1515 controller cannot accept fast back-to-back transactions; thus, this
bit is hardwired to 0.
7
6
5
FBB_CAP
UDF
R
R
R
UDF supported. The PCI1515 controller does not support user-definable features; therefore, this bit is
hardwired to 0.
66-MHz capable. The PCI1515 controller operates at a maximum PCLK frequency of 33 MHz; therefore,
this bit is hardwired to 0.
66MHZ
Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this
function.
4
CAPLIST
R
Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the
command register (PCI offset 04h, see Section 4.4) is a 0 and this bit is a 1, is the function’s INTx signal
asserted. Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit.
3
INT_STATUS
RSVD
RU
R
2−0
Reserved. These bits return 0s when read.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−5
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the PCI1515 controller.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Revision ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Revision ID
08h (Function 0)
Read-only
00h
Default:
4.7 Class Code Register
The class code register recognizes PCI1515 function 0 as a bridge device (06h) and a CardBus bridge device (07h),
with a 00h programming interface.
Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
PCI class code
Base class
Subclass
Programming interface
Type
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
Register:
Offset:
Type:
PCI class code
09h (Function 0)
Read-only
Default:
06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Cache line size
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Cache line size
0Ch (Function 0)
Read/Write
00h
Default:
4−6
4.9 Latency Timer Register
The latency timer register specifies the latency timer for the PCI1515 controller, in units of PCI clock cycles. When
the PCI1515 controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the
latency timer expires before the PCI1515 transaction has terminated, then the PCI1515 controller terminates the
transaction when its GNT is deasserted.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Latency timer
0Dh
Read/Write
00h
Default:
4.10 Header Type Register
The header type register returns 82h when read, indicating that the PCI1515 function 0 configuration spaces adhere
to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers 00h−7Fh, and
80h−FFh is user-definable extension registers.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Header type
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Offset:
Type:
Header type
0Eh (Function 0)
Read-only
82h
Default:
4.11 BIST Register
Because the PCI1515 controller does not support a built-in self-test (BIST), this register returns the value of 00h when
read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
BIST
0Fh (Function 0)
Read-only
00h
Default:
4−7
4.12 CardBus Socket Registers/ExCA Base Address Register
This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped
ExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI
memory address space on a 4-Kbyte boundary. Bits 11−0 are read-only, returning 0s when read. When software
writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address
space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at
offset 800h.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
CardBus socket registers/ExCA base address
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus socket registers/ExCA base address
RW
0
RW
0
RW
0
RW
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
CardBus socket registers/ExCA base address
10h
Read-only, Read/Write
0000 0000h
Default:
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power management
register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. This
register is read-only and returns A0h when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability pointer
R
1
R
0
R
1
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Capability pointer
14h
Read-only
A0h
Default:
4−8
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates
CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI
offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. See Table 4−5 for a complete description
of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary status
RC
0
RC
0
RC
0
RC
0
RC
0
R
0
R
1
RC
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Secondary status
16h
Read-only, Read/Clear
0200h
Default:
Table 4−5. Secondary Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. This bit is set when a CardBus parity error is detected, either an address or data
parity error. Write a 1 to clear this bit.
15 ‡
CBPARITY
RC
Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI1515 controller
does not assert the CSERR signal. Write a 1 to clear this bit.
14 ‡
13 ‡
12 ‡
11 ‡
10−9
CBSERR
CBMABORT
REC_CBTA
SIG_CBTA
CB_SPEED
RC
RC
RC
RC
R
Received master abort. This bit is set when a cycle initiated by the PCI1515 controller on the CardBus bus
is terminated by a master abort. Write a 1 to clear this bit.
Received target abort. This bit is set when a cycle initiated by the PCI1515 controller on the CardBus bus
is terminated by a target abort. Write a 1 to clear this bit.
Signaled target abort. This bit is set by the PCI1515 controller when it terminates a transaction on the
CardBus bus with a target abort. Write a 1 to clear this bit.
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the
PCI1515 controller asserts this signal at a medium speed.
CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
8 ‡
CB_DPAR
RC
b. The PCI1515 controller was the bus master during the data parity error.
c. The parity error response enable bit (bit 0) is set in the bridge control register (PCI offset 3Eh,
see Section 4.25).
Fast back-to-back capable. The PCI1515 controller cannot accept fast back-to-back transactions;
therefore, this bit is hardwired to 0.
7
6
CBFBB_CAP
CB_UDF
R
R
User-definable feature support. The PCI1515 controller does not support user-definable features;
therefore, this bit is hardwired to 0.
66-MHz capable. The PCI1515 CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore, this bit is hardwired to 0.
5
CB66MHZ
RSVD
R
R
4−0
These bits return 0s when read.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−9
4.15 PCI Bus Number Register
The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which
the PCI1515 controller is connected. The PCI1515 controller uses this register in conjunction with the CardBus bus
number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary
buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PCI bus number
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
PCI bus number
18h (Function 0)
Read/Write
00h
Default:
4.16 CardBus Bus Number Register
The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus
to which the PCI1515 controller is connected. The PCI1515 controller uses this register in conjunction with the PCI
bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its
secondary buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus bus number
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
CardBus bus number
19h
Read/Write
00h
Default:
4.17 Subordinate Bus Number Register
The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below
the CardBus bus. The PCI1515 controller uses this register in conjunction with the PCI bus number and CardBus bus
number registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Subordinate bus number
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Subordinate bus number
1Ah
Read/Write
00h
Default:
4−10
4.18 CardBus Latency Timer Register
The CardBus latency timer register is programmed by the host system to specify the latency timer for the PCI1515
CardBus interface, in units of CCLK cycles. When the PCI1515 controller is a CardBus initiator and asserts CFRAME,
the CardBus latency timer begins counting. If the latency timer expires before the PCI1515 transaction has
terminated, then the PCI1515 controller terminates the transaction at the end of the next data phase. A recommended
minimum value for this register of 20h allows most transactions to be completed.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus latency timer
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
CardBus latency timer
1Bh (Function 0)
Read/Write
Default:
00h
4.19 CardBus Memory Base Registers 0, 1
These registers indicate the lower address of a PCI memory address range. They are used by the PCI1515 controller
to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus
cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere in the
32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 0s. Writes to these bits
have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section 4.25) specify whether memory
windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must
be nonzero in order for the PCI1515 controller to claim any memory transactions through CardBus memory windows
(i.e., these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Memory base registers 0, 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory base registers 0, 1
RW
0
RW
0
RW
0
RW
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Memory base registers 0, 1
1Ch, 24h
Read-only, Read/Write
0000 0000h
Default:
4−11
4.20 CardBus Memory Limit Registers 0, 1
These registers indicate the upper address of a PCI memory address range. They are used by the PCI1515 controller
to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus
cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere in the
32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 0s. Writes to these bits
have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section 4.25) specify whether memory
windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must
be nonzero in order for the PCI1515 controller to claim any memory transactions through CardBus memory windows
(i.e., these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Memory limit registers 0, 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory limit registers 0, 1
RW
0
RW
0
RW
0
RW
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Memory limit registers 0, 1
20h, 28h
Read-only, Read/Write
0000 0000h
Default:
4.21 CardBus I/O Base Registers 0, 1
These registers indicate the lower address of a PCI I/O address range. They are used by the PCI1515 controller to
determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle
to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page. The upper
16 bits (31−16) are all 0s, which locates this 64-Kbyte page in the first page of the 32-bit PCI I/O address space. Bits
31−2 are read/write and always return 0s forcing I/O windows to be aligned on a natural doubleword boundary in the
first 64-Kbyte page of PCI I/O address space. Bits 1−0 are read-only, returning 00 or 01 when read, depending on
the value of bit 11 (IO_BASE_SEL) in the general control register (PCI offset 86h, see Section 4.30). These I/O
windows are enabled when either the I/O base register or the I/O limit register is nonzero. The I/O windows by default
are not enabled to pass the first doubleword of I/O to CardBus.
Either the I/O base register or the I/O limit register must be nonzero to enable any I/O transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
I/O base registers 0, 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
I/O base registers 0, 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
R
0
R
X
Register:
Offset:
Type:
I/O base registers 0, 1
2Ch, 34h
Read-only, Read/Write
0000 000Xh
Default:
4−12
4.22 CardBus I/O Limit Registers 0, 1
These registers indicate the upper address of a PCI I/O address range. They are used by the PCI1515 controller to
determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle
to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16
bits are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15−2 are read/write
and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31−16 of the appropriate
I/O base register) on doubleword boundaries.
Bits 31−16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 15−2 are
read/write and bits 1−0 are read-only, returning 00 or 01 when read, depending on the value of bit 12 (IO_LIMIT_SEL)
in the general control register (PCI offset 86h, see Section 4.30). Writes to read-only bits have no effect.
These I/O windows are enabled when either the I/O base register or the I/O limit register is nonzero. By default, the
I/O windows are not enabled to pass the first doubleword of I/O to CardBus.
Either the I/O base register or the I/O limit register must be nonzero to enable any I/O transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
I/O limit registers 0, 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
I/O limit registers 0, 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
R
0
R
X
Register:
Offset:
Type:
I/O limit registers 0, 1
30h, 38h
Read-only, Read/Write
0000 000Xh
Default:
4.23 Interrupt Line Register
The interrupt line register is a read/write register used by the host software. As part of the interrupt routing procedure,
the host software writes this register with the value of the system IRQ assigned to the function.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt line
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Register:
Offset:
Type:
Interrupt line
3Ch
Read/Write
FFh
Default:
4−13
4.24 Interrupt Pin Register
The value read from this register is function dependent. The value for function 0 is fixed to 01h (INTA).
PCI function 0
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt pin − PCI function 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Offset:
Type:
Interrupt pin
3Dh
Read-only
01h (function 0)
Default:
4−14
4.25 Bridge Control Register
The bridge control register provides control over various PCI1515 bridging functions. See Table 4−6 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Bridge control
R
0
R
0
R
0
R
0
R
0
RW
0
RW
1
RW
1
RW
0
RW
1
RW
0
R
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Bridge control
3Eh (Function 0)
Read-only, Read/Write
0340h
Default:
Table 4−6. Bridge Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
15−11
RSVD
R
These bits return 0s when read.
Write posting enable. Enables write posting to and from the CardBus socket. Write posting enables the
posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not.
10
9
POSTEN
RW
RW
Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is
encoded as:
PREFETCH1
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
8
7
PREFETCH0
INTR
RW
RW
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
PCI interrupt − IREQ routing enable. This bit is used to select whether PC Card functional interrupts are
routed to PCI interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts are routed to PCI interrupts (default).
1 = Functional interrupts are routed by ExCA registers.
CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST
signal can also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted.
1 = CRST is asserted (default).
This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.
6 †
CRST
RW
RW
Master abort mode. This bit controls how the PCI1515 controller responds to a master abort when the
PCI1515 controller is an initiator on the CardBus interface.
5
MABTMODE
0 = Master aborts not reported (default).
1 = Signal target abort on PCI and signal SERR, if enabled.
4
3
RSVD
R
This bit returns 0 when read.
VGA enable. This bit affects how the PCI1515 controller responds to VGA addresses. When this bit is set,
accesses to VGA addresses are forwarded.
VGAEN
RW
ISA mode enable. This bit affects how the PCI1515 controller passes I/O cycles within the 64-Kbyte ISA
range. When this bit is set, the PCI1515 controller does not forward the last 768 bytes of each 1K I/O range
to CardBus.
2
1
ISAEN
RW
RW
CSERR enable. This bit controls the response of the PCI1515 controller to CSERR signals on the CardBus
bus.
CSERREN
0 = CSERR is not forwarded to PCI SERR (default)
1 = CSERR is forwarded to PCI SERR.
CardBus parity error response enable. This bit controls the response of the PCI1515 to CardBus parity
errors.
0
CPERREN
RW
0 = CardBus parity errors are ignored (default).
1 = CardBus parity errors are reported using CPERR.
†
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
4−15
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI offset 80h, See Section 4.29). When bit 5 is 0, this register is read/write; when bit 5
is 1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Subsystem vendor ID
40h (Function 0)
Read-only, (Read/Write when bit 5 in the system control register is 0)
0000h
Default:
4.27 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0, this register is read/write; when bit 5 is
1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
If an EEPROM is present, then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after a reset.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Subsystem ID
42h (Function 0)
Read-only, (Read/Write when bit 5 in the system control register is 0)
0000h
Default:
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register
The PCI1515 controller supports the index/data scheme of accessing the ExCA registers, which is mapped by this
register. An address written to this register is the address for the index register and the address+1 is the data address.
Using this access method, applications requiring index/data ExCA access can be supported. The base address can
be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. See
the ExCA register set description in Section 5 for register offsets. All bits in this register are reset by GRST only.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
PC Card 16-bit I/F legacy-mode base-address
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PC Card 16-bit I/F legacy-mode base-address
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
R
1
Register:
Offset:
Type:
PC Card 16-bit I/F legacy-mode base-address
44h (Function 0)
Read-only, Read/Write
0000 0001h
Default:
4−16
4.29 System Control Register
System-level initializations are performed through programming this doubleword register. See Table 4−7 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
System control
RW
0
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
R
0
RW
1
RW
0
RW
0
R
0
R
1
R
0
R
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
System control
RW
1
RW
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
RW
1
RW
1
RW
0
RW
0
R
0
RW
0
RW
0
Register:
Offset:
Type:
System control
80h (Function 0)
Read-only, Read/Write
0844 9060h
Default:
Table 4−7. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serial input stepping. In serial PCI interrupt mode, these bits are used to configure the serial stream PCI
interrupt frames, and can be used to accomplish an even distribution of interrupts signaled on the four PCI
interrupt slots.
00 = INTA/INTB/INTC/INTD signal in INTA/INTB/INTC/INTD slots (default)
01 = INTA/INTB/INTC/INTD signal in INTB/INTC/INTD/INTA slots
10 = INTA/INTB/INTC/INTD signal in INTC/INTD/INTA/INTB slots
11 = INTA/INTB/INTC/INTD signal in INTD/INTA/INTB/INTC slots
31−30 ‡
SER_STEP
RW
29−28
27 ‡
RSVD
RW
RW
Reserved. These bits are reserved, reads or writes have no effect on functionality.
P2C power switch clock. The PCI1515 CLOCK signal clocks the serial interface power switch and the
internal state machine. The default state for this bit is 0, requiring an external clock source provided to the
CLOCK terminal. Bit 27 can be set to 1, allowing the internal oscillator to provide the clock signal.
0 = CLOCK is provided externally, input to the PCI1515 controller.
PSCCLK
1 = CLOCK is generated by the internal oscillator and driven by the PCI1515 controller. (default)
SMI interrupt routing. This bit selects whether IRQ2 or CSC is signaled when a write occurs to power a
PC Card socket.
26 ‡
25 ‡
SMIROUTE
SMISTATUS
RW
RW
0 = PC Card power change interrupts are routed to IRQ2 (default).
1 = A CSC interrupt is generated on PC Card power changes.
SMI interrupt status. This bit is set when a write occurs to set the socket power, and the SMIENB bit is set.
Writing a 1 to this bit clears the status.
0 = SMI interrupt is signaled.
1 = SMI interrupt is not signaled.
SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when
a write to the socket power control occurs. This bit defaults to 0 (disabled).
0 = SMI interrupt mode is disabled (default).
24 ‡
23
SMIENB
RSVD
RW
R
1 = SMI interrupt mode is enabled.
Reserved
CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven low
when a CardBus card has been inserted. When this bit is low, these signals are placed in a high-impedance
state.
22 ‡
CBRSVD
RW
0 = Place the CardBus RSVD terminals in a high-impedance state.
1 = Drive the CardBus RSVD terminals low (default).
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−17
Table 4−7. System Control Register Description (continued)
BIT
21 ‡
SIGNAL
VCCPROT
RSVD
TYPE
FUNCTION
V
protection enable.
CC
0 = V
RW
protection is enabled for 16-bit cards (default).
protection is disabled for 16-bit cards.
CC
CC
1 = V
20−16 ‡
RW
These bits are reserved. Do not change the value of these bits.
Memory read burst enable downstream. When this bit is set, the PCI1515 controller allows memory
read transactions to burst downstream.
15 ‡
14 ‡
MRBURSTDN
MRBURSTUP
RW
RW
0 = MRBURSTDN downstream is disabled.
1 = MRBURSTDN downstream is enabled (default).
Memory read burst enable upstream. When this bit is set, the PCI1515 controller allows memory read
transactions to burst upstream.
0 = MRBURSTUP upstream is disabled (default).
1 = MRBURSTUP upstream is enabled.
Socket activity status. When set, this bit indicates access has been performed to or from a PC Card.
Reading this bit causes it to be cleared.
0 = No socket activity (default)
1 = Socket activity
13 ‡
12
SOCACTIVE
RSVD
R
R
Reserved. This bit returns 1 when read.
Power-stream-in-progress status bit. When set, this bit indicates that a power stream to the power
switch is in progress and a powering change has been requested. When this bit is cleared, it indicates
that the power stream is complete.
11 ‡
10 †
9 †
PWRSTREAM
DELAYUP
R
R
R
0 = Power stream is complete, delay has expired (default).
1 = Power stream is in progress.
Power-up delay-in-progress status bit. When set, this bit indicates that a power-up stream has been
sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up
delay has expired.
0 = Power-up delay has expired (default).
1 = Power-up stream sent to switch. Power might not be stable.
Power-down delay-in-progress status bit. When set, this bit indicates that a power-down stream has
been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the
power-down delay has expired.
DELAYDOWN
0 = Power-down delay has expired (default).
1 = Power-down stream sent to switch. Power might not be stable.
Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when
the interrogation completes.
8 †
7
INTERROGATE
RSVD
R
R
0 = Interrogation not in progress (default)
1 = Interrogation in progress
Reserved. This bit returns 0 when read.
Power savings mode enable. When this bit is set, the PCI1515 controller consumes less power with
no performance loss.
6 ‡
PWRSAVINGS
RW
0 = Power savings mode disabled
1 = Power savings mode enabled (default)
Subsystem ID and subsystem vendor ID, ExCA ID and revision register read/write enable.
0 = Registers are read/write.
5 ‡
SUBSYSRW
RW
1 = Registers are read-only (default).
CardBus data parity SERR signaling enable.
4 ‡
3 ‡
CB_DPAR
RSVD
RW
R
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
Reserved. This bit returns 0 when read.
†
‡
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.
4−18
Table 4−7. System Control Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
ExCA power control bit.
0 = Enables 3.3 V (default)
1 = Enables 5 V
2 ‡
EXCAPOWER
R
Keep clock. When this bit is set, the PCI1515 controller follows the CLKRUN protocol to maintain the
system PCLK and the CCLK (CardBus clock).
0 = Allow system PCLK and CCLK clocks to stop (default)
1 = Never allow system PCLK or CCLK clock to stop
1 ‡
KEEPCLK
RW
Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus
controllers. In these CardBus controllers, setting this bit only maintains the PCI clock, not the CCLK.
In the PCI1515 controller, setting this bit maintains both the PCI clock and the CCLK.
PME/RI_OUT select bit. When this bit is 1, the PME signal is routed to the PME/RI_OUT terminal (R03).
When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal is routed to the
PME/RI_OUT terminal. If this bit is 0 and bit 7 (RIENB) of the card control register is 0, then the output
is placed in a high-impedance state. This terminal is encoded as:
0 = RI_OUT signal is routed to the PME/RI_OUT terminal if bit 7 of the card control register is 1.
(default)
0 ‡
RIMUX
RW
1 = PME signal is routed to the PME/RI_OUT terminal of the PCI1515 controller.
NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register (PCI offset 91h, see Section 4.37) is
0, then the output on the PME/RI_OUT terminal is placed in a high-impedance state.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4.30 General Control Register
The general control register provides top level PCI arbitration control. It also provides control over miscellaneous new
functionality. See Table 4−8 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
General control
RW
0
RWU
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
1
Register:
Offset:
Type:
General control
86h
Read/Write, Read-only
0003h
Default:
Table 4−8. General Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
15−13
RSVD
RW
Reserved, these bits have no effect on device operation.
When this bit is set, bit 0 in the I/O limit registers (PCI offsets 30h and 38h) is set.
0 = Bit 0 in the I/O limit registers is 0 (default)
12 ‡
11 ‡
IO_LIMIT_SEL
IO_BASE_SEL
RW
RW
1 = Bit 0 in the I/O limit registers is 1
When this bit is set, bit 0 in the I/O base registers (PCI offsets 2Ch and 34h) is set.
0 = Bit 0 in the I/O base registers is 0 (default)
1 = Bit 0 in the I/O base registers is 1
Power switch select. This bit selects which power switch is implemented in the system.
0 = A 1.8-V capable power switch (TPS2228) is used (default)
1 = A 12-V capable power switch (TPS2226) is used
10 ‡
9−0
12V_SW_SEL
RSVD
RW
RW
Reserved, these bits have no effect on device operation.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−19
4.31 General-Purpose Event Status Register
The general-purpose event status register contains status bits that are set when general events occur, and can be
programmed to generate general-purpose event signaling through GPE. See Table 4−9 for a complete description
of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose event status
RCU
0
RCU
0
R
0
RCU
0
RCU
0
RCU
0
RCU
0
RCU
0
Register:
Offset:
Type:
General-purpose event status
88h
Read/Clear/Update, Read-only
00h
Default:
Table 4−9. General-Purpose Event Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
7 ‡
PWR_STS
RCU
Power change status. This bit is set when software changes the V
or V
PP
power state of the socket.
level to or from 12 V
CC
12-V V
for the socket.
request status. This bit is set when software has changed the requested V
PP
PP
6 ‡
5
VPP12_STS
RSVD
RCU
R
Reserved. This bit returns 0 when read. A write has no effect.
GPI4 status. This bit is set on a change in status of the MFUNC5 terminal input level if configured as a
general-purpose input, GPI4.
4 ‡
GP4_STS
RCU
GPI3 status. This bit is set on a change in status of the MFUNC4 terminal input level if configured as a
general-purpose input, GPI3.
3 ‡
2 ‡
1 ‡
0 ‡
GP3_STS
GP2_STS
GP1_STS
GP0_STS
RCU
RCU
RCU
RCU
GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a
general-purpose input, GPI2.
GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a
general-purpose input, GPI1.
GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a
general-purpose input, GPI0.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−20
4.32 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−10 for a
complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose event enable
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
General-purpose event enable
89h
Read-only, Read/Write
00h
Default:
Table 4−10. General-Purpose Event Enable Register Description
BIT
7 ‡
6 ‡
5
SIGNAL
PWR_EN
VPP12_EN
RSVD
TYPE
RW
RW
R
FUNCTION
Power change GPE enable. When this bit is set, GPE is signaled on PWR_STS events.
12-V V GPE enable. When this bit is set, GPE is signaled on VPP12_STS events.
PP
Reserved. This bit returns 0 when read. A write has no effect.
4 ‡
3 ‡
2 ‡
1 ‡
0 ‡
GP4_EN
GP3_EN
GP2_EN
GP1_EN
GP0_EN
RW
RW
RW
RW
RW
GPI4 GPE enable. When this bit is set, GPE is signaled on GP4_STS events.
GPI3 GPE enable. When this bit is set, GPE is signaled on GP3_STS events.
GPI2 GPE enable. When this bit is set, GPE is signaled on GP2_STS events.
GPI1 GPE enable. When this bit is set, GPE is signaled on GP1_STS events.
GPI0 GPE enable. When this bit is set, GPE is signaled on GP0_STS events.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4.33 General-Purpose Input Register
The general-purpose input register contains the logical value of the data input to the GPI terminals. See Table 4−11
for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose input
R
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Offset:
Type:
General-purpose input
8Ah
Read/Update, Read-only
XXh
Default:
Table 4−11. General-Purpose Input Register Description
FUNCTION
BIT
7−5
4
SIGNAL
RSVD
TYPE
R
Reserved. These bits return 0s when read. Writes have no effect.
GPI4_DATA
GPI3_DATA
GPI2_DATA
GPI1_DATA
GPI0_DATA
RU
RU
RU
RU
RU
GPI4 data input. This bit represents the logical value of the data input from GPI4.
GPI3 data input. This bit represents the logical value of the data input from GPI3.
GPI2 data input. This bit represents the logical value of the data input from GPI2.
GPI1 data input. This bit represents the logical value of the data input from GPI1.
GPI0 data input. This bit represents the logical value of the data input from GPI0.
3
2
1
0
4−21
4.34 General-Purpose Output Register
The general-purpose output register is used to drive the GPO4−GPO0 outputs. See Table 4−12 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose output
R
0
R
0
R
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
General-purpose output
8Bh
Read-only, Read/Write
00h
Default:
Table 4−12. General-Purpose Output Register Description
BIT
7−5
4 ‡
3 ‡
2 ‡
1 ‡
0 ‡
SIGNAL
RSVD
TYPE
FUNCTION
Reserved. These bits return 0s when read. Writes have no effect.
This bit represents the logical value of the data driven to GPO4.
This bit represents the logical value of the data driven to GPO3.
This bit represents the logical value of the data driven to GPO2.
This bit represents the logical value of the data driven to GPO1.
This bit represents the logical value of the data driven to GPO0.
R
GPO4_DATA
GPO3_DATA
GPO2_DATA
GPO1_DATA
GPO0_DATA
RW
RW
RW
RW
RW
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−22
4.35 Multifunction Routing Status Register
The multifunction routing status register is used to configure the MFUNC6−MFUNC0 terminals. These terminals may
be configured for various functions. This register is intended to be programmed once at power-on initialization. The
default value for this register can also be loaded through a serial EEPROM. See Table 4−13 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Multifunction routing status
R
0
RW
0
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Multifunction routing status
R
0
RW
0
RW
0
RW
1
R
0
RW
0
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Multifunction routing status
8Ch
Read/Write, Read-only
0000 1000h
Default:
Table 4−13. Multifunction Routing Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−28 ‡
RSVD
R
Bits 31−28 return 0s when read.
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
0000 = RSVD
0001 = CLKRUN
0010 = IRQ2
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
1000 = IRQ8
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
27−24 ‡
23−20 ‡
MFUNC6
MFUNC5
RW
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
0000 = GPI4
0001 = GPO4
0010 = RSVD
0011 = IRQ3
0100 = RSVD
0101 = IRQ5
0110 = RSVD
0111 = RSVD
1000 = CAUDPWM
1001 = IRQ9
1010 = RSVD
1011 = RSVD
1100 = LEDA1
1101 = LED_SKT
1110 = GPE
RW
RW
1111 = IRQ15
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
0000 = GPI3
0100 = IRQ4
0101 = RSVD
0110 = RSVD
0111 = RSVD
1000 = CAUDPWM
1001 = IRQ9
1010 = RSVD
1011 = RSVD
1100 = RI_OUT
1101 = LED_SKT
1110 = GPE
19−16 ‡
MFUNC4
0001 = GPO3
0010 = LOCK PCI
0011 = IRQ3
1111 = IRQ15
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD
0001 = IRQSER
0010 = IRQ2
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
1000 = IRQ8
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
15−12 ‡
11−8 ‡
MFUNC3
MFUNC2
RW
RW
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
0000 = GPI2
0001 = GPO2
0010 = RSVD
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = RSVD
0111 = RSVD
1000 = CAUDPWM
1001 = RSVD
1010 = IRQ10
1011 = RSVD
1100 = RI_OUT
1101 = TEST_MUX
1110 = GPE
1111 = IRQ7
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−23
Table 4−13. Multifunction Routing Status Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
0000 = GPI1
0001 = GPO1
0010 = RSVD
0011 = IRQ3
0100 = RSVD
0101 = IRQ5
0110 = RSVD
0111 = RSVD
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LEDA1
1101 = RSVD
1110 = GPE
7−4 ‡
MFUNC1
RW
1111 = IRQ15
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
0000 = GPI0
0001 = GPO0
0010 = INTA
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = RSVD
0111 = RSVD
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LEDA1
1101 = RSVD
1110 = GPE
3−0 ‡
MFUNC0
RW
1111 = IRQ15
‡
One or more bits in this register are cleared only by the assertion of GRST.
4.36 Retry Status Register
The contents of the retry status register enable the retry time-out counters and display the retry expiration status. The
15
flags are set when the PCI1515 controller, as a master, receives a retry and does not retry the request within 2 clock
cycles. The flags are cleared by writing a 1 to the bit. See Table 4−14 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Retry status
RW
1
RW
1
RC
0
R
0
RC
0
R
0
RC
0
R
0
Register:
Offset:
Type:
Retry status
90h (Function 0)
Read-only, Read/Write, Read/Clear
C0h
Default:
Table 4−14. Retry Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PCI retry time-out counter enable. This bit is encoded as:
0 = PCI retry counter disabled
7 ‡
PCIRETRY
RW
1 = PCI retry counter enabled (default)
CardBus retry time-out counter enable. This bit is encoded as:
0 = CardBus retry counter disabled
6 ‡
CBRETRY
RW
1 = CardBus retry counter enabled (default)
CardBus target B retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
5 ‡
4
TEXP_CBB
RSVD
RC
R
1 = Retry has expired.
Reserved. This bit returns 0 when read.
CardBus target A retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
3 ‡
2
TEXP_CBA
RSVD
RC
R
1 = Retry has expired.
Reserved. This bit returns 0 when read.
PCI target retry expired. Write a 1 to clear this bit.
1 ‡
0
TEXP_PCI
RSVD
RC
R
0 = Inactive (default)
1 = Retry has expired.
Reserved. This bit returns 0 when read.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−24
4.37 Card Control Register
The card control register is provided for PCI1130 compatibility. The RI_OUT signal is enabled through this register.
See Table 4−15 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Card control
RW
0
RW
0
RW
0
R
0
R
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Card control
91h
Read-only, Read/Write
00h
Default:
Table 4−15. Card Control Register Description
BIT
7 ‡
SIGNAL
RIENB
RSVD
TYPE
RW
FUNCTION
Ring indicate enable. When this bit is 1, the RI_OUT output is enabled. This bit defaults to 0.
These bits are reserved. Do not change the value of these bits.
6−3
RW
CardBus audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal must be routed through an
MFUNC terminal.
2 ‡
1 ‡
0 ‡
AUD2MUX
SPKROUTEN
IFG
RW
RW
RW
0 = CAUDIO set to CAUDPWM on MFUNC terminal (default)
1 = CAUDIO is not routed.
When bit 1 is set, the SPKR terminal from the PC Card is enabled and is routed to tthe SPKROUT terminal.
The SPKROUT terminal drives data only when the SPKROUTEN bit is set. This bit is encoded as:
0 = SPKR to SPKROUT not enabled (default)
1 = SPKR to SPKROUT enabled
Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when
a functional interrupt is signaled from a PC Card interface. Write back a 1 to clear this bit.
0 = No PC Card functional interrupt detected (default)
1 = PC Card functional interrupt detected
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−25
4.38 Device Control Register
The device control register is provided for PCI1130 compatibility. The interrupt mode select is programmed through
this register. The socket-capable force bits are also programmed through this register. See Table 4−16 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Device control
RW
0
RW
1
RW
1
R
0
RW
0
RW
1
RW
1
RW
0
Register:
Offset:
Type:
Device control
92h (Function 0)
Read-only, Read/Write
66h
Default:
Table 4−16. Device Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Socket power lock bit. When this bit is set to 1, software cannot power down the PC Card socket while
in D3. It may be necessary to lock socket power in order to support wake on LAN or RING if the
operating system is programmed to power down a socket when the CardBus controller is placed in the
D3 state.
7 ‡
SKTPWR_LOCK
RW
3-V socket capable force bit.
0 = Not 3-V capable
6 ‡
3VCAPABLE
RW
1 = 3-V capable (default)
5 ‡
4
IO16R2
RSVD
TEST
RW
R
Diagnostic bit. This bit defaults to 1.
Reserved. This bit returns 0 when read. A write has no effect.
TI test bit. Write only 0 to this bit.
3 ‡
RW
Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Reserved
2−1 ‡
INTMODE
RW
10 = IRQ serialized interrupts and parallel PCI interrupts INTA, INTB, INTC, and INTD
11 = IRQ and PCI serialized interrupts (default)
0 ‡
RSVD
RW
Reserved. Bit 0 is reserved for test purposes. Only a 0 must be written to this bit.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−26
4.39 Diagnostic Register
The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be written
to it. See Table 4−17 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Diagnostic
RW
0
R
1
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Diagnostic
93h (Function 0)
Read/Write
60h
Default:
Table 4−17. Diagnostic Register Description
FUNCTION
BIT
7 ‡
6 ‡
SIGNAL
TRUE_VAL
RSVD
TYPE
RW
R
This bit defaults to 0. This bit is encoded as:
0 = Reads true values in PCI vendor ID and PCI device ID registers (default)
1 = Returns all 1s to reads from the PCI vendor ID and PCI device ID registers
Reserved. This bit is read-only and returns 1 when read.
CSC interrupt routing control
0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1
1 = CSC interrupts routed to PCI if ExCA 805 bits 7−4 = 0000b (default).
In this case, the setting of ExCA 803 bit 4 is a don’t care.
5 ‡
CSC
RW
4 ‡
3 ‡
2 ‡
1 ‡
0 ‡
DIAG4
DIAG3
DIAG2
DIAG1
RSVD
RW
RW
RW
RW
RW
Diagnostic RETRY_DIS. Delayed transaction disable.
Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
10
15
.
Diagnostic DISCARD_TIM_SEL_CB. Set = 2 , reset = 2
10
15
.
Diagnostic DISCARD_TIM_SEL_PCI. Set = 2 , reset = 2
These bits are reserved. Do not change the value of these bits.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−27
4.40 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns
01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and
the value.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Offset:
Type:
Capability ID
A0h
Read-only
01h
Default:
4.41 Next Item Pointer Register
The contents of this register indicate the next item in the linked list of the PCI power management capabilities.
Because the PCI1515 functions only include one capabilities item, this register returns 0s when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Next item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Next item pointer
A1h
Read-only
00h
Default:
4−28
4.42 Power Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PC Card function related
to power management. The PCI1515 CardBus bridge function supports the D0, D1, D2, and D3 power states. The
default register value is FE12h for operation in accordance with PCI Bus Power Management Interface Specification
revision 1.1. See Table 4−18 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
RW
1
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
0
Register:
Offset:
Type:
Power management capabilities
A2h (Function 0)
Read-only, Read/Write
FE12h
Default:
Table 4−18. Power Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
This 5-bit field indicates the power states from which the PCI1515 controller functions can assert PME.
A 0 for any bit indicates that the function cannot assert the PME signal while in that power state. These
5 bits return 11111b when read. Each of these bits is described below:
15 ‡
RW
R
Bit 15 − defaults to a 1 indicating the PME signal can be asserted from the D3
because wake-up support from D3
cold
state. This bit is read/write
is contingent on the system providing an auxiliary power source
cold
to the V
terminals for D3
cold
terminals. If the system designer chooses not to provide an auxiliary power source to the V
PME support
CC
CC
wake-up support, then BIOS must write a 0 to this bit.
14−11
Bit 14 − contains the value 1 to indicate that the PME signal can be asserted from the D3 state.
hot
Bit 13 − contains the value 1 to indicate that the PME signal can be asserted from the D2 state.
Bit 12 − contains the value 1 to indicate that the PME signal can be asserted from the D1 state.
Bit 11 − contains the value 1 to indicate that the PME signal can be asserted from the D0 state.
10
9
D2_Support
D1_Support
RSVD
R
R
R
R
This bit returns a 1 when read, indicating that the function supports the D2 device power state.
This bit returns a 1 when read, indicating that the function supports the D1 device power state.
Reserved. These bits return 000b when read.
8−6
5
DSI
Device-specific initialization. This bit returns 0 when read.
Auxiliary power source. This bit is meaningful only if bit 15 (D3
supporting PME) is set. When this bit
cold
requires auxiliary power supplied by the system by way
is set, it indicates that support for PME in D3
of a proprietary delivery vehicle.
cold
4
AUX_PWR
R
A 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source.
If the function does not support PME while in the D3
0.
state (bit 15=0), then this field must always return
cold
When this bit is 1, it indicates that the function relies on the presence of the PCI clock for PME operation.
When this bit is 0, it indicates that no PCI clock is required for the function to generate PME.
3
PMECLK
Version
R
R
Functions that do not support PME generation in any state must return 0 for this field.
These 3 bits return 010b when read, indicating that there are 4 bytes of general-purpose power
management (PM) registers as described in draft revision 1.1 of the PCI Bus Power Management Interface
Specification.
2−0
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−29
4.43 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI1515
CardBus function. The contents of this register are not affected by the internally generated reset caused by the
transition from the D3
to D0 state. See Table 4−19 for a complete description of the register contents.
hot
All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3 -to-D0 state transition, with
hot
the exception of the PME context bits (if PME is enabled) and the GRST only bits.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status
RWC
0
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
RW
0
Register:
Offset:
Type:
Power management control/status
A4h (Function 0)
Read-only, Read/Write, Read/Write/Clear
0000h
Default:
Table 4−19. Power Management Control/Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME status. This bit is set when the CardBus function would normally assert the PME signal, independent
of the state of the PME_EN bit. This bit is cleared by a writeback of 1, and this also clears the PME signal
if PME was asserted by this function. Writing a 0 to this bit has no effect.
15 †
PMESTAT
RC
14−13
12−9
DATASCALE
DATASEL
R
R
This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data.
Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data.
This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This
bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.
8 ‡
PME_ENABLE
RSVD
RW
R
7−2
Reserved. These bits return 0s when read.
Power state. This 2-bit field is used both to determine the current power state of a function and to set the
function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
1−0
PWRSTATE
RW
11 = D3
hot
†
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.
‡
4−30
4.44 Power Management Control/Status Bridge Support Extensions Register
This register supports PCI bridge-specific functionality. It is required for all PCI-to-PCI bridges. See Table 4−20 for
a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status bridge support extensions
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Power management control/status bridge support extensions
A6h (Function 0)
Read-only
C0h
Default:
Table 4−20. Power Management Control/Status Bridge Support Extensions Register Description
BIT
SIGNAL
TYPE
FUNCTION
Bus power/clock control enable. This bit returns 1 when read. This bit is encoded as:
0 = Bus power/clock control is disabled.
1 = Bus power/clock control is enabled (default).
A 0 indicates that the bus power/clock control policies defined in the PCI Bus Power Management Interface
Specification are disabled. When the bus power/clock control enable mechanism is disabled, the power
state field (bits 1−0) of the power management control/status register (PCI offset A4h, see Section 4.43)
cannot be used by the system software to control the power or the clock of the secondary bus. A 1 indicates
that the bus power/clock control mechanism is enabled.
7
BPCC_EN
R
B2/B3 support for D3 . The state of this bit determines the action that is to occur as a direct result of
hot
programming the function to D3 . This bit is only meaningful if bit 7 (BPCC_EN) is a 1. This bit is encoded
hot
as:
6
B2_B3
RSVD
R
R
0 = When the bridge is programmed to D3 , its secondary bus has its power removed (B3).
hot
1 = When the bridge function is programmed to D3 , its secondary bus PCI clock is stopped (B2)
hot
(default).
5−0
Reserved. These bits return 0s when read.
4.45 Power-Management Data Register
The power-management data register returns 0s when read, because the CardBus functions do not report dynamic
data.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power-management data
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Power-management data
A7h (Function 0)
Read-only
Default:
00h
4−31
4.46 Serial Bus Data Register
The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data
when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data,
the serial bus index register must be programmed with the byte address, the serial bus slave address must be
programmed with the 7-bit slave address, and the read/write indicator bit must be reset.
On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address register
must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the
serial bus control and status register (see Section 4.49) must be polled until clear. Then the contents of this register
are valid read data from the serial bus interface. See Table 4−21 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Serial bus data
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Serial bus data
B0h (Function 0)
Read/Write
00h
Default:
Table 4−21. Serial Bus Data Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface.
On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid.
7−0 ‡
SBDATA
RW
‡
One or more bits in this register are cleared only by the assertion of GRST.
4.47 Serial Bus Index Register
The serial bus index register is for programmable serial bus byte reads and writes. This register represents the byte
address when generating cycles on the serial bus interface. To write a byte, the serial bus data register must be
programmed with the data, this register must be programmed with the byte address, and the serial bus slave address
must be programmed with both the 7-bit slave address and the read/write indicator.
On byte reads, the word address is programmed into this register, the serial bus slave address must be programmed
with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and
status register (see Section 4.49) must be polled until clear. Then the contents of the serial bus data register are valid
read data from the serial bus interface. See Table 4−22 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Serial bus index
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Serial bus index
B1h (Function 0)
Read/Write
00h
Default:
Table 4−22. Serial Bus Index Register Description
BIT
SIGNAL
TYPE
FUNCTION
7−0 ‡
SBINDEX
RW
Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−32
4.48 Serial Bus Slave Address Register
The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte,
the serial bus data register must be programmed with the data, the serial bus index register must be programmed
with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write
indicator bit.
On byte reads, the byte address is programmed into the serial bus index register, this register must be programmed
with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and
status register (see Section 4.49) must be polled until clear. Then the contents of the serial bus data register are valid
read data from the serial bus interface. See Table 4−23 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Serial bus slave address
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Serial bus slave address
B2h (Function 0)
Read/Write
Default:
00h
Table 4−23. Serial Bus Slave Address Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serial bus slave address. This bit field represents the slave address of a read or write transaction on the
serial interface.
7−1 ‡
SLAVADDR
RW
RW
Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read
and write accesses.
0 ‡
RWCMD
0 = A byte write access is requested to the serial bus interface.
1 = A byte read access is requested to the serial bus interface.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−33
4.49 Serial Bus Control/Status Register
The serial bus control and status register communicates serial bus status information and selects the quick command
protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid
in the serial bus data register. See Table 4−24 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Serial bus control/status
RW
0
R
0
R
0
R
0
RW
0
RW
0
RC
0
RC
0
Register:
Offset:
Type:
Serial bus control/status
B3h (Function 0)
Read-only, Read/Write, Read/Clear
00h
Default:
Table 4−24. Serial Bus Control/Status Register Description
BIT
7 ‡
6
SIGNAL
PROT_SEL
RSVD
TYPE
FUNCTION
Protocol select. When bit 7 is set, the send-byte protocol is used on write requests and the receive-byte
protocol is used on read commands. The word address byte in the serial bus index register (see
Section 4.47) is not output by the PCI1515 controller when bit 7 is set.
RW
R
Reserved. Bit 6 returns 0 when read.
Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write)
is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see
Section 4.48). Bit 5 must be polled on reads from the serial interface. After the byte read access has been
completed, this bit is cleared and the read data is valid in the serial bus data register.
5
4
REQBUSY
ROMBUSY
R
R
Serial EEPROM busy status. Bit 4 indicates the status of the PCI1515 serial EEPROM circuitry. Bit 4 is set
during the loading of the subsystem ID and other default values from the serial bus EEPROM.
0 = Serial EEPROM circuitry is not busy
1 = Serial EEPROM circuitry is busy
Serial bus detect. When the serial bus interface is detected through a pullup resistor on the SCL terminal
after reset, this bit is set to 1.
3 ‡
2 ‡
1 ‡
SBDETECT
SBTEST
RW
RW
RC
0 = Serial bus interface not detected
1 = Serial bus interface detected
Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.
0 = Serial bus clock at normal operating frequency, ꢀ 100 kHz (default)
1 = Serial bus clock frequency increased for test purposes
Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during
a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1.
0 = No error detected during user-requested byte read or write cycle
REQ_ERR
1 = Data error detected during user-requested byte read or write cycle
EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the
auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on
invalid EEPROM data formats. See Section 3.6.4, Serial Bus EEPROM Application, for details on
EEPROM data format. Bit 0 is cleared by a writeback of 1.
0 ‡
ROM_ERR
RC
0 = No error detected during autoload from serial bus EEPROM
1 = Data error detected during autoload from serial bus EEPROM
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−34
5 ExCA Compatibility Registers (Function 0)
The ExCA (exchangeable card architecture) registers implemented in the PCI1515 controller are register-compatible
with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible
with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed
through this scheme by writing the register offset value into the index register (I/O base), and reading or writing the
data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit
I/F legacy mode base address register. The offsets from this base address run contiguously from 00h to 3Fh for socket
A. See Figure 5−1 for an ExCA I/O mapping illustration. Table 5−1 identifies each ExCA register and its respective
ExCA offset.
The PCI1515 controller also provides a memory-mapped alias of the ExCA registers by directly mapping them into
PCI memory space. They are located through the CardBus socket registers/ExCA registers base address register
(PCI register 10h) at memory offset 800h. See Figure 5−2 for an ExCA memory mapping illustration. Note that
memory offsets are 800h−844h for function 0. This illustration also identifies the CardBus socket register mapping,
which is mapped into the same 4K window at memory offset 0h.
The interrupt registers in the ExCA register set, as defined by the 82365SL specification, control such card functions
as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers
and the host interrupt signaling method selected for the PCI1515 controller to ensure that all possible PCI1515
interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to
the interrupt signaling are at memory address ExCA offsets 803h and 805h.
Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this chapter. I/O windows have byte granularity.
Access to memory-mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this chapter. Memory windows have
4-Kbyte granularity.
A bit location followed by a ‡ means that this bit is not cleared by the assertion of PRST. This bit is only cleared by
the assertion of GRST. This is necessary to retain device context during the transition from D3 to D0.
5−1
Host I/O Space
Offset
00h
PCI1515 Configuration Registers
Offset
PC Card A
ExCA
Registers
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
10h
44h
Index
Data
3Fh
Offset of desired register is placed in the index register and the
data from that location is returned in the data register.
Figure 5−1. ExCA Register Access Through I/O
Host
Memory Space
PCI1515 Configuration Registers
Offset
00h
Offset
CardBus
Socket A
Registers
10h
44h
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
20h
800h
ExCA
Registers
Card A
844h
Offsets are from the CardBus socket/ExCA base
address register’s base address.
Figure 5−2. ExCA Register Access Through Memory
5−2
Table 5−1. ExCA Registers and Offsets
PCI MEMORY ADDRESS EXCA OFFSET
EXCA REGISTER NAME
OFFSET (HEX)
(CARD A)
Identification and revision ‡
Interface status
800
00
801
01
Power control †
802†
803†
804†
805†
806
02
Interrupt and general control †
Card status change †
03
04
Card status change interrupt configuration †
Address window enable
05
06
I / O window control
807
07
I / O window 0 start-address low-byte
I / O window 0 start-address high-byte
I / O window 0 end-address low-byte
I / O window 0 end-address high-byte
I / O window 1 start-address low-byte
I / O window 1 start-address high-byte
I / O window 1 end-address low-byte
I / O window 1 end-address high-byte
Memory window 0 start-address low-byte
Memory window 0 start-address high-byte
Memory window 0 end-address low-byte
Memory window 0 end-address high-byte
Memory window 0 offset-address low-byte
Memory window 0 offset-address high-byte
Card detect and general control †
Reserved
808
08
809
09
80A
80B
80C
80D
80E
80F
0A
0B
0C
0D
0E
0F
10
810
811
11
812
12
813
13
814
14
815
15
816
16
817
17
Memory window 1 start-address low-byte
Memory window 1 start-address high-byte
Memory window 1 end-address low-byte
Memory window 1 end-address high-byte
Memory window 1 offset-address low-byte
Memory window 1 offset-address high-byte
Global control ‡
818
18
819
19
81A
81B
81C
81D
81E
81F
1A
1B
1C
1D
1E
1F
20
Reserved
Memory window 2 start-address low-byte
Memory window 2 start-address high-byte
Memory window 2 end-address low-byte
Memory window 2 end-address high-byte
Memory window 2 offset-address low-byte
Memory window 2 offset-address high-byte
820
821
21
822
22
823
23
824
24
825
25
†
One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared
by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.
‡
5−3
Table 5−1. ExCA Registers and Offsets (continued)
PCI MEMORY ADDRESS EXCA OFFSET
EXCA REGISTER NAME
OFFSET (HEX)
(CARD A)
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
−
Reserved
Reserved
826
827
Memory window 3 start-address low-byte
Memory window 3 start-address high-byte
Memory window 3 end-address low-byte
Memory window 3 end-address high-byte
Memory window 3 offset-address low-byte
Memory window 3 offset-address high-byte
Reserved
828
829
82A
82B
82C
82D
82E
82F
830
Reserved
Memory window 4 start-address low-byte
Memory window 4 start-address high-byte
Memory window 4 end-address low-byte
Memory window 4 end-address high-byte
Memory window 4 offset-address low-byte
Memory window 4 offset-address high-byte
I/O window 0 offset-address low-byte
I/O window 0 offset-address high-byte
I/O window 1 offset-address low-byte
I/O window 1 offset-address high-byte
Reserved
831
832
833
834
835
836
837
838
839
83A
83B
83C
83D
83E
83F
840
Reserved
Reserved
Reserved
Reserved
Reserved
Memory window page register 0
Memory window page register 1
Memory window page register 2
Memory window page register 3
Memory window page register 4
841
−
842
−
843
−
844
−
5−4
5.1 ExCA Identification and Revision Register
This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. See
Table 5−2 for a complete description of the register contents.
NOTE: If bit 5 (SUBSYRW) in the system control register is 1, then this register is read-only.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA identification and revision
R
1
R
0
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
Register:
Offset:
Type:
ExCA identification and revision
CardBus Socket Address + 800h:
Read/Write, Read-only
84h
Card A ExCA Offset 00h
Default:
Table 5−2. ExCA Identification and Revision Register Description
BIT
SIGNAL
IFTYPE
RSVD
TYPE
FUNCTION
Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
PCI1515 controller. The PCI1515 controller supports both I/O and memory 16-bit PC Cards.
7−6 ‡
5−4 ‡
R
RW
These bits can be used for 82365SL emulation.
82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCI1515 controller.
Host software can read this field to determine compatibility to the 82365SL-DF register set. This field defaults
to 0100b upon reset. Writing 0010b to this field places the controller in the 82356SL mode.
3−0 ‡
365REV
RW
‡
One or more bits in this register are cleared only by the assertion of GRST.
5−5
5.2 ExCA Interface Status Register
This register provides information on current status of the PC Card interface. An X in the default bit values indicates
that the value of the bit after reset depends on the state of the PC Card interface. See Table 5−3 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA interface status
R
0
R
0
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Offset:
Type:
ExCA interface status
CardBus Socket Address + 801h:
Read-only
Card A ExCA Offset 01h
Default:
00XX XXXXb
Table 5−3. ExCA Interface Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
This bit returns 0 when read. A write has no effect.
7
RSVD
R
CARDPWR. Card power. This bit indicates the current power status of the PC Card socket. This bit reflects
how the ExCA power control register has been programmed. The bit is encoded as:
6
5
CARDPWR
READY
R
0 = V
1 = V
and V
and V
to the socket are turned off (default).
to the socket are turned on.
CC
CC
PP
PP
This bit indicates the current status of the READY signal at the PC Card interface.
R
R
0 = PC Card is not ready for a data transfer.
1 = PC Card is ready for a data transfer.
Card write protect. This bit indicates the current status of the WP signal at the PC Card interface. This signal
reports to the PCI1515 controller whether or not the memory card is write protected. Further, write
protection for an entire PCI1515 16-bit memory window is available by setting the appropriate bit in the
ExCA memory window offset-address high-byte register.
4
CARDWP
0 = WP signal is 0. PC Card is R/W.
1 = WP signal is 1. PC Card is read-only.
Card detect 2. This bit indicates the status of the CD2 signal at the PC Card interface. Software can use
this and CDETECT1 to determine if a PC Card is fully seated in the socket.
3
2
CDETECT2
CDETECT1
R
R
0 = CD2 signal is 1. No PC Card inserted.
1 = CD2 signal is 0. PC Card at least partially inserted.
Card detect 1. This bit indicates the status of the CD1 signal at the PC Card interface. Software can use
this and CDETECT2 to determine if a PC Card is fully seated in the socket.
0 = CD1 signal is 1. No PC Card inserted.
1 = CD1 signal is 0. PC Card at least partially inserted.
Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery
voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 0 reflects the BVD1 status, and
bit 1 reflects BVD2.
00 = Battery is dead.
01 = Battery is dead.
10 = Battery is low; warning.
11 = Battery is good.
1−0
BVDSTAT
R
When a 16-bit I/O card is inserted, this field indicates the status of the SPKR (bit 1) signal and the STSCHG
(bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these
card outputs.
5−6
5.3 ExCA Power Control Register
This register provides PC Card power control. Bit 7 of this register enables the 16-bit outputs on the socket interface,
and can be used for power management in 16-bit PC Card applications. See Table 5−5 for a complete description
of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA power control
RW
0
R
0
R
0
RW
0
RW
0
R
0
RW
0
RW
0
Register:
Offset:
Type:
ExCA power control
CardBus Socket Address + 802h:
Read-only, Read/Write
00h
Card A ExCA Offset 02h
Default:
Table 5−4. ExCA Power Control Register Description—82365SL Support
BIT
SIGNAL
TYPE
FUNCTION
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1515 controller. This bit
is encoded as:
7
COE
RW
0 = 16-bit PC Card outputs disabled (default)
1 = 16-bit PC Card outputs enabled
6
RSVD
R
Reserved. Bit 6 returns 0 when read.
Auto power switch enable.
5 †
AUTOPWRSWEN
RW
0 = Automatic socket power switching based on card detects is disabled.
1 = Automatic socket power switching based on card detects is enabled.
PC Card power enable.
0 = V
1 = V
= No connection
CC
CC
4
CAPWREN
RSVD
RW
R
is enabled and controlled by bit 2 (EXCAPOWER) of the system control register
(PCI offset 80h, see Section 4.29).
3−2
1−0
Reserved. Bits 3 and 2 return 0s when read.
PC Card V
PP
ignores this field unless V
power control. Bits 1 and 0 are used to request changes to card V . The PCI1515 controller
PP
to the socket is enabled. This field is encoded as:
CC
EXCAVPP
RW
00 = No connection (default)
01 = V
10 = 12 V
11 = Reserved
CC
†
One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared
by the assertion of PRST or GRST.
Table 5−5. ExCA Power Control Register Description—82365SL-DF Support
BIT
SIGNAL
TYPE
FUNCTION
Card output enable. This bit controls the state of all of the 16-bit outputs on the PCI1515 controller. This
bit is encoded as:
7 †
COE
RW
0 = 16-bit PC Card outputs are disabled (default).
1 = 16-bit PC Card outputs are enabled.
6−5
4−3 †
2
RSVD
EXCAVCC
RSVD
R
RW
R
Reserved. These bits return 0s when read. Writes have no effect.
V
. These bits are used to request changes to card V . This field is encoded as:
CC
CC
00 = 0 V (default)
01 = 0 V reserved
10 = 5 V
11 = 3.3 V
This bit returns 0 when read. A write has no effect.
V
V
. These bits are used to request changes to card V . The PCI1515 controller ignores this field unless
PP
PP
to the socket is enabled (i.e., 5 Vdc or 3.3 Vdc). This field is encoded as:
CC
1−0 †
EXCAVPP
RW
00 = 0 V (default)
01 = V
10 = 12 V
11 = 0 V reserved
CC
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5−7
5.4 ExCA Interrupt and General Control Register
This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. See
Table 5−6 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA interrupt and general control
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
ExCA interrupt and general control
CardBus Socket Address + 803h:
Read/Write
00h
Card A ExCA Offset 03h
Default:
Table 5−6. ExCA Interrupt and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Card ring indicate enable. Enables the ring indicate function of the BVD1/RI terminals. This bit is encoded
as:
7
RINGEN
RW
0 = Ring indicate disabled (default)
1 = Ring indicate enabled
Card reset. This bit controls the 16-bit PC Card RESET signal, and allows host software to force a card
reset. This bit affects 16-bit cards only. This bit is encoded as:
0 = RESET signal asserted (default)
6 †
5 †
RESET
RW
RW
1 = RESET signal deasserted.
Card type. This bit indicates the PC Card type. This bit is encoded as:
CARDTYPE
0 = Memory PC Card is installed (default)
1 = I/O PC Card is installed
PCI interrupt − CSC routing enable bit. This bit has meaning only if the CSC interrupt routing control bit
(PCI offset 93h, bit 5) is 0. In this case, when this bit is set (high), the card status change interrupts are
routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7−4 in the ExCA
card status-change interrupt configuration register (ExCA offset 805h, see Section 5.6). This bit is encoded
as:
4
CSCROUTE
RW
0 = CSC interrupts routed by ExCA registers (default)
1 = CSC interrupts routed to PCI interrupts
If the CSC interrupt routing control bit (bit 5) of the diagnostic register (PCI offset 93h, see Section 4.39)
is set to 1, this bit has no meaning, which is the default case.
Card interrupt select for I/O PC Card functional interrupts. These bits select the interrupt routing for I/O
PC Card functional interrupts. This field is encoded as:
0000 = No IRQ selected (default). CSC interrupts are routed to PCI Interrupts. This bit setting is ORed
with bit 4 (CSCROUTE) for backward compatibility.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
3−0
INTSELECT
RW
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5−8
5.5 ExCA Card Status-Change Register
The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC
Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt
source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the
corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to
the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt
service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of
two methods: a read of this register or an explicit writeback of 1 to the status bit. The choice of these two methods
is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (CB offset 81Eh, see
Section 5.20). See Table 5−7 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card status-change
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
ExCA card status-change
Read-only
Offset:
Default:
CardBus socket address + 804h; Card A ExCA offset 04h
00h
Table 5−7. ExCA Card Status-Change Register Description
BIT
SIGNAL
TYPE
FUNCTION
7−4
RSVD
R
Reserved. Bits 7−4 return 0s when read.
Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card
interface. This bit is encoded as:
3 †
2 †
CDCHANGE
R
R
0 = No change detected on either CD1 or CD2
1 = Change detected on either CD1 or CD2
Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of
a PCI1515 interrupt was due to a change on READY at the PC Card interface, indicating that the
PC Card is now ready to accept new data. This bit is encoded as:
READYCHANGE
0 = No low-to-high transition detected on READY (default)
1 = Detected low-to-high transition on READY
When a 16-bit I/O card is installed, bit 2 is always 0.
Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether
the source of a PCI1515 interrupt was due to a battery-low warning condition. This bit is encoded as:
0 = No battery warning condition (default)
1 †
0 †
BATWARN
BATDEAD
R
R
1 = Detected battery warning condition
When a 16-bit I/O card is installed, bit 1 is always 0.
Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates
whether the source of a PCI1515 interrupt was due to a battery dead condition. This bit is encoded as:
0 = STSCHG deasserted (default)
1 = STSCHG asserted
Ring indicate. When the PCI1515 is configured for ring indicate operation, bit 0 indicates the status of
RI.
†
These are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then these bits are
cleared by the assertion of PRST or GRST.
5−9
5.6 ExCA Card Status-Change Interrupt Configuration Register
This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. See
Table 5−8 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card status-change interrupt configuration
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
ExCA card status-change interrupt configuration
CardBus Socket Address + 805h:
Card A ExCA Offset 05h
Read/Write
00h
Default:
Table 5−8. ExCA Card Status-Change Interrupt Configuration Register Description
BIT
SIGNAL
TYPE
FUNCTION
Interrupt select for card status change. These bits select the interrupt routing for card status-change
interrupts. This field is encoded as:
0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) is set
to 1b. In this case bit 4 of ExCA 803 is a don’t care. This is the default setting.
0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI offset 93h) is set to 0b. In this case,
CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h to 1b.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
7−4
CSCSELECT
RW
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
Card detect enable. Enables interrupts on CD1 or CD2 changes. This bit is encoded as:
3†
2†
CDEN
RW
RW
0 = Disables interrupts on CD1 or CD2 line changes (default)
1 = Enables interrupts on CD1 or CD2 line changes
Ready enable. This bit enables/disables a low-to-high transition on the PC Card READY signal to generate
a host interrupt. This interrupt source is considered a card status change. This bit is encoded as:
READYEN
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
Battery warning enable. This bit enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
1†
0†
BATWARNEN
BATDEADEN
RW
RW
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
Battery dead enable. This bit enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5−10
5.7 ExCA Address Window Enable Register
The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By
default, all windows to the card are disabled. The PCI1515 controller does not acknowledge PCI memory or I/O cycles
to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O
window start/end/offset address registers. See Table 5−9 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA address window enable
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Type:
ExCA address window enable
Read-only, Read/Write
Offset:
Default:
CardBus socket address + 806h; Card A ExCA offset 06h
00h
Table 5−9. ExCA Address Window Enable Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as:
0 = I/O window 1 disabled (default)
7
IOWIN1EN
RW
1 = I/O window 1 enabled
I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as:
0 = I/O window 0 disabled (default)
6
5
IOWIN0EN
RSVD
RW
R
1 = I/O window 0 enabled
Reserved. Bit 5 returns 0 when read.
Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is
encoded as:
4
3
2
1
0
MEMWIN4EN
MEMWIN3EN
MEMWIN2EN
MEMWIN1EN
MEMWIN0EN
RW
RW
RW
RW
RW
0 = Memory window 4 disabled (default)
1 = Memory window 4 enabled
Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is
encoded as:
0 = Memory window 3 disabled (default)
1 = Memory window 3 enabled
Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is
encoded as:
0 = Memory window 2 disabled (default)
1 = Memory window 2 enabled
Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is
encoded as:
0 = Memory window 1 disabled (default)
1 = Memory window 1 enabled
Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is
encoded as:
0 = Memory window 0 disabled (default)
1 = Memory window 0 enabled
5−11
5.8 ExCA I/O Window Control Register
The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See
Table 5−10 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window control
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Type:
ExCA I/O window control
Read/Write
Offset:
Default:
CardBus socket address + 807h: Card A ExCA offset 07h
00h
Table 5−10. ExCA I/O Window Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
7
WAITSTATE1
RW
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
6
ZEROWS1
RW
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data-sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width determined by DATASIZE1, bit 4 (default).
5
4
IOSIS16W1
DATASIZE1
RW
RW
1 = Window data width determined by IOIS16.
I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOSIS16W1) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
3
2
WAITSTATE0
ZEROWS0
RW
RW
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width is determined by DATASIZE0, bit 0 (default).
1
0
IOSIS16W0
DATASIZE0
RW
RW
1 = Window data width is determined by IOIS16.
I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOSIS16W0) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
5−12
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 start-address low-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 start-address low-byte
CardBus Socket Address + 808h: Card A ExCA Offset 08h
ExCA I/O window 1 start-address low-byte
CardBus Socket Address + 80Ch:
Card A ExCA Offset 0Ch
Type:
Default:
Read/Write
00h
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 start-address high-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 start-address high-byte
CardBus Socket Address + 809h: Card A ExCA Offset 09h
ExCA I/O window 1 start-address high-byte
CardBus Socket Address + 80Dh:
Card A ExCA Offset 0Dh
Type:
Default:
Read/Write
00h
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 end-address low-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 end-address low-byte
CardBus Socket Address + 80Ah: Card A ExCA Offset 0Ah
ExCA I/O window 1 end-address low-byte
CardBus Socket Address + 80Eh:
Card A ExCA Offset 0Eh
Type:
Default:
Read/Write
00h
5−13
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the upper 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 end-address high-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 end-address high-byte
CardBus Socket Address + 80Bh: Card A ExCA Offset 0Bh
ExCA I/O window 1 end-address high-byte
CardBus Socket Address + 80Fh:
Card A ExCA Offset 0Fh
Type:
Default:
Read/Write
00h
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4.
The 8 bits of these registers correspond to bits A19−A12 of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0−4 start-address low-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA memory window 0 start-address low-byte
CardBus Socket Address + 810h: Card A ExCA Offset 10h
ExCA memory window 1 start-address low-byte
CardBus Socket Address + 818h:
Card A ExCA Offset 18h
Register:
Offset:
ExCA memory window 2 start-address low-byte
CardBus Socket Address + 820h:
Card A ExCA Offset 20h
Register:
Offset:
ExCA memory window 3 start-address low-byte
CardBus Socket Address + 828h:
Card A ExCA Offset 28h
Register:
Offset:
ExCA memory window 4 start-address low-byte
CardBus Socket Address + 830h:
Card A ExCA Offset 30h
Type:
Default:
Read/Write
00h
5−14
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5−11 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0−4 start-address high-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA memory window 0 start-address high-byte
CardBus Socket Address + 811h: Card A ExCA Offset 11h
ExCA memory window 1 start-address high-byte
CardBus Socket Address + 819h:
Card A ExCA Offset 19h
Register:
Offset:
ExCA memory window 2 start-address high-byte
CardBus Socket Address + 821h:
Card A ExCA Offset 21h
Register:
Offset:
ExCA memory window 3 start-address high-byte
CardBus Socket Address + 829h:
Card A ExCA Offset 29h
Register:
Offset:
ExCA memory window 4 start-address high-byte
CardBus Socket Address + 831h:
Card A ExCA Offset 31h
Type:
Default:
Read/Write
00h
Table 5−11. ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
This bit controls the memory window data width. This bit is encoded as:
7
DATASIZE
RW
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
Zero wait-state. This bit controls the memory window wait state for 8- and 16-bit accesses. This wait-state
timing emulates the ISA wait state used by the 82365SL-DF. This bit is encoded as:
6
ZEROWAIT
RW
0 = 8- and 16-bit cycles have standard length (default).
1 = 8-bit cycles reduced to equivalent of three ISA cycles
16-bit cycles reduced to the equivalent of two ISA cycles
5−4
3−0
SCRATCH
STAHN
RW
RW
Scratch pad bits. These bits have no effect on memory window operation.
Start address high-nibble. These bits represent the upper address bits A23−A20 of the memory window
start address.
5−15
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4.
The 8 bits of these registers correspond to bits A19−A12 of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0−4 end-address low-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA memory window 0 end-address low-byte
CardBus Socket Address + 812h: Card A ExCA Offset 12h
ExCA memory window 1 end-address low-byte
CardBus Socket Address + 81Ah:
Card A ExCA Offset 1Ah
Register:
Offset:
ExCA memory window 2 end-address low-byte
CardBus Socket Address + 822h:
Card A ExCA Offset 22h
Register:
Offset:
ExCA memory window 3 end-address low-byte
CardBus Socket Address + 82Ah:
Card A ExCA Offset 2Ah
Register:
Offset:
ExCA memory window 4 end-address low-byte
CardBus Socket Address + 832h:
Card A ExCA Offset 32h
Type:
Default:
Read/Write
00h
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5−12 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0−4 end-address high-byte
RW
0
RW
0
R
0
R
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA memory window 0 end-address high-byte
CardBus Socket Address + 813h: Card A ExCA Offset 13h
ExCA memory window 1 end-address high-byte
CardBus Socket Address + 81Bh:
Card A ExCA Offset 1Bh
Register:
Offset:
ExCA memory window 2 end-address high-byte
CardBus Socket Address + 823h:
Card A ExCA Offset 23h
Register:
Offset:
ExCA memory window 3 end-address high-byte
CardBus Socket Address + 82Bh:
Card A ExCA Offset 2Bh
Register:
Offset:
Type:
ExCA Memory window 4 end-address high-byte
CardBus Socket Address + 833h:
Read/Write, Read-only
00h
Card A ExCA Offset 33h
Default:
Table 5−12. ExCA Memory Windows 0−4 End-Address High-Byte Registers Description
BIT
7−6
5−4
3−0
SIGNAL
MEMWS
RSVD
TYPE
RW
R
FUNCTION
Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory
accesses. The number of wait states added is equal to the binary value of these 2 bits.
Reserved. These bits return 0s when read. Writes have no effect.
End-address high nibble. These bits represent the upper address bits A23−A20 of the memory window end
address.
ENDHN
RW
5−16
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The 8 bits of these registers correspond to bits A19−A12 of the offset address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0−4 offset-address low-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA memory window 0 offset-address low-byte
CardBus Socket Address + 814h: Card A ExCA Offset 14h
ExCA memory window 1 offset-address low-byte
CardBus Socket Address + 81Ch:
Card A ExCA Offset 1Ch
Register:
Offset:
ExCA memory window 2 offset-address low-byte
CardBus Socket Address + 824h:
Card A ExCA Offset 24h
Register:
Offset:
ExCA memory window 3 offset-address low-byte
CardBus Socket Address + 82Ch:
Card A ExCA Offset 2Ch
Register:
Offset:
ExCA memory window 4 offset-address low-byte
CardBus Socket Address + 834h:
Card A ExCA Offset 34h
Type:
Default:
Read/Write
00h
5−17
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the write
protection and common/attribute memory configurations are set in this register. See Table 5−13 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0−4 offset-address high-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA memory window 0 offset-address high-byte
CardBus Socket Address + 815h: Card A ExCA Offset 15h
ExCA memory window 1 offset-address high-byte
CardBus Socket Address + 81Dh:
Card A ExCA Offset 1Dh
Register:
Offset:
ExCA memory window 2 offset-address high-byte
CardBus Socket Address + 825h:
Card A ExCA Offset 25h
Register:
Offset:
ExCA memory window 3 offset-address high-byte
CardBus Socket Address + 82Dh:
Card A ExCA Offset 2Dh
Register:
Offset:
ExCA memory window 4 offset-address high-byte
CardBus Socket Address + 835h:
Card A ExCA Offset 35h
Type:
Default:
Read/Write
00h
Table 5−13. ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Write protect. This bit specifies whether write operations to this memory window are enabled.
This bit is encoded as:
7
WINWP
RW
0 = Write operations are allowed (default).
1 = Write operations are not allowed.
This bit specifies whether this memory window is mapped to card attribute or common memory.
This bit is encoded as:
6
REG
RW
RW
0 = Memory window is mapped to common memory (default).
1 = Memory window is mapped to attribute memory.
Offset-address high byte. These bits represent the upper address bits A25−A20 of the memory window offset
address.
5−0
OFFHB
5−18
5.19 ExCA Card Detect and General Control Register
This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the
VS1 and VS2 signals at the PC Card interface. Table 5−14 describes each bit in the ExCA card detect and general
control register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card detect and general control
R
X
R
X
W
0
RW
0
R
0
R
0
RW
0
R
0
Register:
Offset:
Type:
ExCA card detect and general control
CardBus Socket Address + 816h:
Read-only, Write-only, Read/Write
XX00 0000b
Card A ExCA Offset 16h
Default:
Table 5−14. ExCA Card Detect and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
VS2. This bit reports the current state of the VS2 signal at the PC Card interface, and, therefore, does not
have a default value.
7 †
VS2STAT
R
0 = VS2 is low.
1 = VS2 is high.
VS1. This bit reports the current state of the VS1 signal at the PC Card interface, and, therefore, does not
have a default value.
6 †
VS1STAT
SWCSC
R
0 = VS1 is low.
1 = VS1 is high.
Software card detect interrupt. If card detect enable, bit 3 in the ExCA card status change interrupt
configuration register (ExCA offset 805h, see Section 5.6) is set, then writing a 1 to this bit causes a
card-detect card-status-change interrupt for the card socket.
If the card-detect enable bit is cleared to 0 in the ExCA card status-change interrupt configuration register
(ExCA offset 805h, see Section 5.6), then writing a 1 to the software card-detect interrupt bit has no effect.
This bit is write-only.
5
W
A read operation of this bit always returns 0. Writing a 1 to this bit also clears it. If bit 2 of the ExCA global
control register (ExCA offset 81Eh, see Section 5.20) is set and a 1 is written to clear bit 3 of the ExCA
card status change interrupt register, then this bit also is cleared.
Card detect resume enable. If this bit is set to 1 and a card detect change has been detected on the CD1
and CD2 inputs, then the RI_OUT output goes from high to low. The RI_OUT remains low until the card
status change bit in the ExCA card status-change register (ExCA offset 804h, see Section 5.5) is cleared.
If this bit is a 0, then the card detect resume functionality is disabled.
4
CDRESUME
RW
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
3−2
1
RSVD
REGCONFIG
RSVD
R
RW
R
These bits return 0s when read. Writes have no effect.
Register configuration upon card removal. This bit controls how the ExCA registers for the socket react
to a card removal event. This bit is encoded as:
0 = No change to ExCA registers upon card removal (default)
1 = Reset ExCA registers upon card removal
0
This bit returns 0 when read. A write has no effect.
†
One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared
by the assertion of PRST or GRST.
5−19
5.20 ExCA Global Control Register
This register controls the PC Card socket. The host interrupt mode bits in this register are retained for 82365SL-DF
compatibility. See Table 5−15 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA global control
R
0
R
0
R
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
ExCA global control
CardBus Socket Address + 81Eh:
Read-only, Read/Write
00h
Card A ExCA Offset 1Eh
Default:
Table 5−15. ExCA Global Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
These bits return 0s when read. Writes have no effect.
7−5
RSVD
R
Level/edge interrupt mode select, card B. This bit selects the signaling mode for the PCI1515 host interrupt
for card B interrupts. This bit is encoded as:
4
INTMODEB
INTMODEA
IFCMODE
CSCMODE
RW
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
Level/edge interrupt mode select, card A. This bit selects the signaling mode for the PCI1515 host interrupt
for card A interrupts. This bit is encoded as:
3
RW
RW
RW
0 = Host interrupt is edge-mode (default).
1 = Host interrupt is level-mode.
Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register. This bit is encoded as:
2 ‡
1 ‡
0 = Interrupt flags cleared by read of CSC register (default)
1 = Interrupt flags cleared by explicit writeback of 1
Card status change level/edge mode select. This bit selects the signaling mode for the PCI1515 host
interrupt for card status changes. This bit is encoded as:
0 = Host interrupt is edge-mode (default).
1 = Host interrupt is level-mode.
Power-down mode select. When this bit is set to 1, the PCI1515 controller is in power-down mode. In
power-down mode the PCI1515 card outputs are placed in a high-impedance state until an active cycle
is executed on the card interface. Following an active cycle the outputs are again placed in a
high-impedance state. The PCI1515 controller still receives functional interrupts and/or card status
change interrupts; however, an actual card access is required to wake up the interface. This bit is encoded
as:
0 ‡
PWRDWN
RW
0 = Power-down mode disabled (default)
1 = Power-down mode enabled
‡
One or more bits in this register are cleared only by the assertion of GRST.
5−20
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 offset-address low-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
R
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 offset-address low-byte
CardBus Socket Address + 836h: Card A ExCA Offset 36h
ExCA I/O window 1 offset-address low-byte
CardBus Socket Address + 838h:
Read/Write, Read-only
00h
Card A ExCA Offset 38h
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the offset address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 offset-address high-byte
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 offset-address high-byte
CardBus Socket Address + 837h: Card A ExCA Offset 37h
ExCA I/O window 1 offset-address high-byte
CardBus Socket Address + 839h:
Card A ExCA Offset 39h
Type:
Default:
Read/Write
00h
5.23 ExCA Memory Windows 0−4 Page Registers
The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding
addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By
programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256
16-Mbyte regions in the 4-gigabyte PCI address space. These registers are only accessible when the ExCA registers
are memory-mapped, that is, these registers may not be accessed using the index/data I/O scheme.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0−4 page
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
R
0
Register:
Offset:
Type:
ExCA memory windows 0−4 page
CardBus Socket Address + 840h, 841h, 842h, 843h, 844h
Read/Write
00h
Default:
5−21
5−22
6 CardBus Socket Registers (Function 0)
The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and
control socket-specific functions. The PCI1515 controller provides the CardBus socket/ExCA base address register
(PCI offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Table 6−1
gives the location of the socket registers in relation to the CardBus socket/ExCA base address.
In addition to the five required registers, the PCI1515 controller implements a register at offset 20h that provides
power management control for the socket.
Host
Memory Space
PCI1515 Configuration Registers
Offset
00h
Offset
CardBus
Socket A
Registers
10h
44h
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
20h
800h
ExCA
Registers
Card A
844h
Offsets are from the CardBus socket/ExCA base
address register’s base address.
Figure 6−1. Accessing CardBus Socket Registers Through PCI Memory
Table 6−1. CardBus Socket Registers
REGISTER NAME
OFFSET
00h
Socket event †
Socket mask †
04h
Socket present state †
Socket force event
Socket control †
08h
0Ch
10h
Reserved
14h−1Ch
20h
Socket power management ‡
†
‡
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.
6−1
6.1 Socket Event Register
This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only
that one has occurred. Software must read the socket present state register for current status. Each bit in this register
can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software through writing a 1 to
the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They can be
immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG
reasserted or card detect is still true). Software needs to clear this register before enabling interrupts. If it is not cleared
and interrupts are enabled, then an unmasked interrupt is generated based on any bit that is set. See Table 6−2 for
a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RWC RWC RWC RWC
0
0
0
0
Register:
Offset:
Type:
Socket event
CardBus Socket Address + 00h
Read-only, Read/Write to Clear
0000 0000h
Default:
Table 6−2. Socket Event Register Description
FUNCTION
BIT
SIGNAL
TYPE
31−4
RSVD
R
These bits return 0s when read.
Power cycle. This bit is set when the PCI1515 controller detects that the PWRCYCLE bit in the socket
present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
†
3
†
2
†
1
PWREVENT
CD2EVENT
CD1EVENT
RWC
RWC
RWC
CCD2. This bit is set when the PCI1515 controller detects that the CDETECT2 field in the socket present
state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
CCD1. This bit is set when the PCI1515 controller detects that the CDETECT1 field in the socket present
state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
CSTSCHG. This bit is set when the CARDSTS field in the socket present state register (offset 08h, see
Section 6.3) has changed state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG
signal. For 16-bit PC Cards, this bit is set on both transitions of the CSTSCHG signal. This bit is reset by
writing a 1.
†
0
CSTSEVENT
RWC
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
6−2
6.2 Socket Mask Register
This register allows software to control the CardBus card events which generate a status change interrupt. The state
of these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, see
Section 6.1). See Table 6−3 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Socket mask
CardBus Socket Address + 04h
Read-only, Read/Write
0000 0000h
Default:
Table 6−3. Socket Mask Register Description
FUNCTION
BIT
SIGNAL
TYPE
31−4
RSVD
R
These bits return 0s when read.
Power cycle. This bit masks the PWRCYCLE bit in the socket present state register (offset 08h, see
Section 6.3) from causing a status change interrupt.
†
3
PWRMASK
CDMASK
RW
RW
RW
0 = PWRCYCLE event does not cause a CSC interrupt (default).
1 = PWRCYCLE event causes a CSC interrupt.
Card detect mask. These bits mask the CDETECT1 and CDETECT2 bits in the socket present state
register (offset 08h, see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal does not cause a CSC interrupt (default).
01 = Reserved (undefined)
10 = Reserved (undefined)
†
2−1
11 = Insertion/removal causes a CSC interrupt.
CSTSCHG mask. This bit masks the CARDSTS field in the socket present state register (offset 08h, see
Section 6.3) from causing a CSC interrupt.
†
0
CSTSMASK
0 = CARDSTS event does not cause a CSC interrupt (default).
1 = CARDSTS event causes a CSC interrupt.
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
6−3
6.3 Socket Present State Register
This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see
Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card V
support
CC
and card type is only updated at each insertion. Also note that the PCI1515 controller uses the CCD1 and CCD2
signals during card identification, and changes on these signals during this operation are not reflected in this register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Socket present state
R
0
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Socket present state
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
0
R
0
R
0
R
X
R
X
R
X
Register:
Offset:
Type:
Socket present state
CardBus Socket Address + 08h
Read-only
Default:
3000 00XXh
Table 6−4. Socket Present State Register Description
BIT
SIGNAL
TYPE
FUNCTION
YV socket. This bit indicates whether or not the socket can supply V
PCI1515 controller does not support Y.Y-V V ; therefore, this bit is always reset unless overridden
CC
by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
= Y.Y V to PC Cards. The
CC
31
YVSOCKET
R
R
R
XV socket. This bit indicates whether or not the socket can supply V
PCI1515 controller does not support X.X-V V ; therefore, this bit is always reset unless overridden
CC
by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
= X.X V to PC Cards. The
CC
30
29
XVSOCKET
3VSOCKET
3-V socket. This bit indicates whether or not the socket can supply V
PCI1515 controller does support 3.3-V V ; therefore, this bit is always set unless overridden by the
CC
socket force event register (offset 0Ch, see Section 6.4).
= 3.3 Vdc to PC Cards. The
CC
5-V socket. This bit indicates whether or not the socket can supply V
PCI1515 controller does support 5-V V ; therefore, this bit is always set unless overridden by bit 6
CC
of the device control register (PCI offset 92h, see Section 4.38).
= 5 Vdc to PC Cards. The
CC
28
5VSOCKET
RSVD
R
R
R
27−14
13 †
These bits return 0s when read.
YV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= Y.Y Vdc.
YVCARD
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
XV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= X.X Vdc.
12 †
11 †
10 †
XVCARD
3VCARD
5VCARD
R
R
R
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
3-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
= 3.3 Vdc.
5-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
= 5 Vdc.
†
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
6−4
Table 6−4. Socket Present State Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Bad V
an invalid voltage.
request. This bit indicates that the host software has requested that the socket be powered at
CC
9 †
BADVCCREQ
R
0 = Normal operation (default)
1 = Invalid V
CC
request by host software
Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle
did not terminate properly or because write data still resides in the PCI1515 controller.
0 = Normal operation (default)
8 †
7 †
6
DATALOST
NOTACARD
IREQCINT
R
R
R
1 = Potential data loss due to card removal
Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is
not updated until a valid PC Card is inserted into the socket.
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC
Card interface.
0 = READY(IREQ)//CINT is low.
1 = READY(IREQ)//CINT is high.
CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
5 †
4 †
CBCARD
R
R
16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
16BITCARD
Power cycle. This bit indicates the status of each card powering request. This bit is encoded as:
0 = Socket is powered down (default).
3 †
2 †
PWRCYCLE
CDETECT2
R
R
1 = Socket is powered up.
CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
0 = CCD2 is low (PC Card may be present)
1 = CCD2 is high (PC Card not present)
CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
1 †
0
CDETECT1
CARDSTS
R
R
0 = CCD1 is low (PC Card may be present).
1 = CCD1 is high (PC Card not present).
CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface.
0 = CSTSCHG is low.
1 = CSTSCHG is high.
†
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
6.4 Socket Force Event Register
This register is used to force changes to the socket event register (offset 00h, see Section 6.1) and the socket present
state register (offset 08h, see Section 6.3). The CVSTEST bit (bit 14) in this register must be written when forcing
changes that require card interrogation. See Table 6−5 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Socket force event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Socket force event
R
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
R
X
W
X
W
X
W
X
W
X
W
X
W
X
Register:
Offset:
Type:
Socket force event
CardBus Socket Address + 0Ch
Read-only, Write-only
0000 XXXXh
Default:
6−5
Table 6−5. Socket Force Event Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−15
RSVD
R
Reserved. These bits return 0s when read.
Card VS test. When this bit is set, the PCI1515 controller reinterrogates the PC Card, updates the
socket present state register (offset 08h, see Section 6.3), and re-enables the socket power control.
14
13
12
11
10
9
CVSTEST
FYVCARD
W
Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
W
W
W
W
W
W
Force XV card. Writes to this bit cause the XVCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
FXVCARD
Force 3-V card. Writes to this bit cause the 3VCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
F3VCARD
Force 5-V card. Writes to this bit cause the 5VCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
F5VCARD
Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register (offset 08h,
see Section 6.3) can be made by writing this bit.
FBADVCCREQ
FDATALOST
Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register (offset
08h, see Section 6.3) to be written.
8
Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
7
6
5
FNOTACARD
RSVD
W
R
This bit returns 0 when read.
Force CardBus card. Writes to this bit cause the CBCARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
FCBCARD
W
Force 16-bit card. Writes to this bit cause the 16BITCARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
4
3
F16BITCARD
FPWRCYCLE
W
W
Force power cycle. Writes to this bit cause the PWREVENT bit in the socket event register (offset 00h,
see Section 6.1) to be written, and the PWRCYCLE bit in the socket present state register (offset 08h,
see Section 6.3) is unaffected.
Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register (offset 00h, see
Section 6.1) to be written, and the CDETECT2 bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.
2
1
0
FCDETECT2
FCDETECT1
FCARDSTS
W
W
W
Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register (offset 00h, see
Section 6.1) to be written, and the CDETECT1 bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.
Force CSTSCHG. Writes to this bit cause the CSTSEVENT bit in the socket event register (offset 00h,
see Section 6.1) to be written. The CARDSTS bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.
6−6
6.5 Socket Control Register
This register provides control of the voltages applied to the socket V and V . The PCI1515 controller ensures that
PP
CC
the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6−6 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
R
0
RW
0
RW
0
RW
0
RW
0
R
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Socket control
CardBus Socket Address + 10h
Read-only, Read/Write
0000 0000h
Default:
Table 6−6. Socket Control Register Description
BIT
31−11
10
SIGNAL
TYPE
FUNCTION
RSVD
RSVD
RSVD
R
R
R
These bits return 0s when read.
This bit returns 1 when read.
These bits return 0s when read.
9−8
This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock
to the CardBus card:
0 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the
sockethas been idle for 8 clocks and the PCI CLKRUN protocol is preparing to stop/slow the
PCI bus clock.
7
STOPCLK
RW
1 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the
socket has been idle for 8 clocks, regardless of the state of the PCI CLKRUN signal.
V
CC
control. These bits are used to request card V changes.
CC
000 = Request power off (default)
001 = Reserved
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= X.X V
= Y.Y V
CC
CC
6−4 †
3
VCCCTRL
RSVD
RW
R
010 = Request V
011 = Request V
= 5 V
= 3.3 V
CC
CC
This bit returns 0 when read.
control. These bits are used to request card V
V
changes.
PP
PP
000 = Request power off (default)
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= X.X V
= Y.Y V
PP
PP
2−0 †
VPPCTRL
RW
001 = Request V
010 = Request V
011 = Request V
= 12 V
= 5 V
= 3.3 V
PP
PP
PP
†
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
6−7
6.6 Socket Power Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
Register:
Offset:
Type:
Socket power management
CardBus Socket Address + 20h
Read-only, Read/Write
0000 0000h
Default:
Table 6−7. Socket Power Management Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−26
RSVD
R
Reserved. These bits return 0s when read.
Socket access status. This bit provides information on whether a socket access has occurred. This bit is
cleared by a read access.
25 ‡
SKTACCES
R
0 = No PC Card access has occurred (default).
1 = PC Card has been accessed.
Socket mode status. This bit provides clock mode information.
24 ‡
23−17
16
SKTMODE
RSVD
R
R
0 = Normal clock operation
1 = Clock frequency has changed.
These bits return 0s when read.
CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL).
CLKCTRLEN
RSVD
RW
R
0 = Clock control disabled (default)
1 = Clock control enabled
15−1
These bits return 0s when read.
CardBus clock control. This bit determines whether the CardBus CLKRUN protocol attempts to stop or
slow the CardBus clock during idle states. The CLKCTRLEN bit enables this bit.
0
CLKCTRL
RW
0 = Allows the CardBus CLKRUN protocol to attempt to stop the CardBus clock (default)
1 = Allows the CardBus CLKRUN protocol to attempt to slow the CardBus clock by a factor of 16
‡
One or more bits in this register are cleared only by the assertion of GRST.
6−8
7 Electrical Characteristics
†
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range, VR_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 1.836 V
V
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
CCA
CCP
Clamping voltage range, V
Input voltage range, V : PCI, CardBus, SC, miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
CCP
CCCB
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V : PCI, CardBus, SC, miscellaneous . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
OK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O O CC
Operating free-air temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals and miscellaneous
I
CC
terminals are measured with respect to V
limit specified applies for a dc condition.
instead of V . PC Card terminals are measured with respect to CardBus V . The
CC CC
CCP
2. Applies for external output and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals and miscellaneous
O
CC
terminals are measured with respect to V
limit specified applies for a dc condition.
instead of V . PC Card terminals are measured with respect to CardBus V . The
CC CC
CCP
7.2 Recommended Operating Conditions (see Note 3)
OPERATION
MIN
NOM
MAX
UNIT
V
VR_PORT
1.5 V
1.35
1.5
1.65
(see Table 2−4 for description)
V
3.3 V
3.3 V
5 V
3
3
3.3
3.3
5
3.6
3.6
V
CC
V
CCP
V
V
PCI and miscellaneous I/O clamp voltage
PC Card I/O clamp voltage
4.75
3
5.25
3.6
3.3 V
5 V
3.3
5
V
CCA
4.75
5.25
NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
7−1
Recommended Operating Conditions (continued)
OPERATION
MIN
0.5 V
NOM
MAX
UNIT
3.3 V
V
CCP
CCP
k
PCI
5 V
2
V
CCP
3.3 V CardBus
High-level input
voltage
0.475 V
V
V
V
CC(A/B)
2
CC(A/B)
CC(A/B)
CC(A/B)
†
3.3 V 16-bit
5 V 16-bit
PC Card
V
V
IH
2.4
2
‡
Miscellaneous
V
CC
CC
TEST1:3
0.7 V
V
CC
0
3.3 V
5 V
0.3 V
CCP
0.8
k
PCI
0
0
0
0
0
0
0
0
0
0
0
0
1
0
2
0
0
3.3 V CardBus
3.3 V 16-bit
5 V 16-bit
0.325 V
CC(A/B)
0.8
Low-level input
voltage
†
V
V
V
IL
PC Card
0.8
0.8
‡
‡
Miscellaneous
k
PCI
V
CCP
PC Card
V
CCCB
V
V
Input voltage
I
Miscellaneous
TEST1:3
V
CC
CC
CC
CC
0.2 V
k
PCI
V
V
V
§
PC Card
Output voltage
V
O
‡
Miscellaneous
CC
4
PCI and PC Card
Input transition time
(t and t )
t
t
ns
t
‡
Miscellaneous
6
r
f
Powerup reset time GRST input
Operating ambient temperature range
Virtual junction temperature
ms
°C
°C
PU
T
A
25
25
70
T
115
J#
†
‡
Applies to external inputs and bidirectional buffers without hysteresis
Miscellaneous terminals are: A9, B9, C9, G2, G3, J5, K5, P12, P17 (CLOCK, DATA, LATCH, SCL, SDA, SUSPEND, GRST, TEST0, TEST4
terminals).
Applies to external output buffers
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
§
#
kMFUNC(0:6) share the same specifications as the PCI terminals.
7−2
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER
TERMINALS
OPERATION
3.3 V
TEST CONDITIONS
MIN
MAX
UNIT
I
= −0.5 mA
= −2 mA
0.9 V
OH
OH
OH
OH
OH
CC
2.4
¶
PCI
I
I
I
I
5 V
3.3 V CardBus
3.3 V 16-bit
5 V 16-bit
= −0.15 mA
= −0.15 mA
= −0.15 mA
0.9 V
CC
2.4
V
OH
V
High-level output voltage
PC Card
2.8
§
Miscellaneous
I
I
I
I
I
I
I
= −4 mA
= 1.5 mA
= 6 mA
V
CC
−0.6
OH
OL
OL
OL
OL
OL
OL
0.1 V
3.3 V
5 V
CC
¶
PCI
0.55
= 0.7 mA
= 0.7 mA
= 0.7 mA
= 4 mA
0.1 V
CC
3.3 V CardBus
3.3 V 16-bit
5 V 16-bit
Low-level output voltage
V
OL
V
0.4
PC Card
0.55
0.5
§
Miscellaneous
3-state output
high-impedance
I
I
Output terminals
Output terminals
3.6 V
V
= V
or GND
20
µA
µA
OZ
O CC
3.6 V
5.25 V
3.6 V
V = V
I CC
−1
−1
10
High-impedance,
low-level output current
OZL
OZH
IL
V = V
I
CC
CC
CC
†
†
V = V
I
High-impedance,
high-level output current
I
I
Output terminals
µA
µA
5.25 V
3.6 V
3.6 V
3.6 V
3.6 V
3.6 V
25
20
V = V
I
Input terminals
I/O terminals
V = GND
I
Low-level input current
High-level input current
V = GND
I
20
20
¶
PCI
‡
20
V = V
I
CC
CC
CC
‡
‡
Others
V = V
I
10
V = V
I
I
IH
µA
Input terminals
‡
‡
‡
5.25 V
3.6 V
20
10
25
V = V
I
CC
CC
CC
V = V
I
I/O terminals
5.25 V
V = V
I
†
‡
§
For PCI and miscellaneous terminals, V = V
. For PC Card terminals, V = V .
CCA
I
CCP
I
For I/O terminals, input leakage (I and I ) includes I
leakage of the disabled output.
IL IH OZ
Miscellaneous terminals are: A9, B9, C9, G2, G3, J5, K5, P12, P17 (CLOCK, DATA, LATCH, SCL, SDA, SUSPEND, GRST, TEST0, TEST4
terminals).
¶
MFUNC(0:6) share the same specifications as the PCI terminals.
7.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t
t
t
Cycle time, PCLK
t
30
11
11
1
ns
ns
c
cyc
Pulse duration (width), PCLK high
Pulse duration (width), PCLK low
Slew rate, PCLK
t
high
w(H)
w(L)
t
ns
low
∆v/∆t
t , t
r f
4
V/ns
ms
ms
t
w
Pulse duration (width), GRST
Setup time, PCLK active at end of PRST
t
1
rst
t
su
t
100
rst-clk
7−3
7.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature
This data manual uses the following conventions to describe time ( t ) intervals. The format is t , where subscript A
A
indicates the type of dynamic parameter being represented. One of the following is used: t = propagation delay time,
pd
t (t , t ) = delay time, t = setup time, and t = hold time.
d
en dis
su
h
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
PCLK-to-shared signal
valid delay time
t
11
val
inv
C
= 50 pF,
L
t
Propagation delay time, See Note 4
ns
pd
See Note 4
PCLK-to-shared signal
invalid delay time
t
2
2
t
t
t
t
Enable time, high impedance-to-active delay time from PCLK
Disable time, active-to-high impedance delay time from PCLK
Setup time before PCLK valid
t
ns
ns
ns
ns
en
dis
su
h
on
t
28
off
t
7
0
su
Hold time after PCLK high
t
h
NOTE 4: PCI shared signals are AD31−AD0, C/BE3−C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
7.6 Reset Timing
t
t
t
prst−idsel
grst
clk−prst
3 V
V
CC
0.
0.
PCLK
0.
0.
GRST
PRST
IDSEL
0.
0.
0.
0.
Figure 7−1. Reset Timing Diagram
PARAMETER
MIN
2
MAX
UNIT
ms
µs
t
t
t
V
≥ 3.0 V to GRST ↑
grst
CC
PCLK ↑ to PRST ↑
PRST ↑ to IDSEL ↑
100
3
clk-prst
µs
prst-idsel
NOTES: 5. GRST may be asynchronously deasserted, that is, it does not require a valid PCLK.
6. There is no specific timing relationship of GRST to PRST. However, if GRST is deasserted after PRST then the PCLK to PRST ↑
and PRST ↑ to IDSEL ↑ apply to GRST.
7−4
8 Mechanical Information
The PCI1515 device is available in the 257-terminal MicroStar BGA package (GHK) or the 257-terminal lead (Pb
atomic number 82) free MicroStar BGA package (ZHK). The following figure shows the mechanical dimensions for
the GHK package. The GHK and ZHK packages are mechanically identical; therefore, only the GHK mechanical
drawing is shown.
GHK (S−PBGA−N257)
PLASTIC BALL GRID ARRAY
16,10
15,90
14,40 TYP
0,80
SQ
W
V
U
T
R
P
N
M
L
0,80
K
J
H
G
F
E
D
C
B
A
A1 Corner
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,12
0,55
0,45
0,08
0,45
0,35
4145273-3/E 08/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration
MicroStar BGA is a trademark of Texas Instruments.
8−1
8−2
相关型号：
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