PCI2050APDV_技术文档

PCI2050

PCIĆtoĆPCI Bridge

Data Manual

1999

PCIBus Solutions

Printed in U.S.A., 12/99

SCPS053

PCI2050

PCI-to-PCI Bridge

Data Manual

Literature Number: SCPS053

December 1999

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products

or to discontinue any product or service without notice, and advise customers to obtain the latest

version of relevant information to verify, before placing orders, that information being relied on

is current and complete. All products are sold subject to the terms and conditions of sale supplied

at the time of order acknowledgement, including those pertaining to warranty, patent

infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the

time of sale in accordance with TI’s standard warranty. Testing and other quality control

techniquesareutilizedtotheextentTIdeemsnecessarytosupportthiswarranty. Specifictesting

of all parameters of each device is not necessarily performed, except those mandated by

government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE

POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR

ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR

PRODUCTS ARENOTDESIGNED, AUTHORIZED, ORWARRANTED TOBESUITABLEFOR

USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY

AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and

operating safeguards must be provided by the customer to minimize inherent or procedural

hazards.

TI assumes no liability for applications assistance or customer product design. TI does not

warrantorrepresentthatanylicense, eitherexpressorimplied, isgrantedunderanypatentright,

copyright, mask work right, or other intellectual property right of TI covering or relating to any

combination, machine, or process in which such semiconductor products or services might be

or are used. TI’s publication of information regarding any third party’s products or services does

not constitute TI’s approval, warranty or endorsement thereof.

Contents

Section

Title

Page

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1

1.2

1.3

1.4

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

2

3

Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1

3.2

3.3

3.4

3.5

3.6

Introduction to the PCI2050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Special Cycle Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Secondary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

3.6.1

3.6.2

3.6.3

Primary Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Internal Secondary Bus Arbitration . . . . . . . . . . . . . . . . . . . . 3–5

External Secondary Bus Arbitration . . . . . . . . . . . . . . . . . . . 3–6

3.7

3.8

Decode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

System Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

3.8.1

3.8.2

3.8.3

3.8.4

3.8.5

3.8.6

3.8.7

Posted Write Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Posted Write Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Target Abort on Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Master Abort on Posted Writes . . . . . . . . . . . . . . . . . . . . . . . 3–7

Master Delayed Write Timeout . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Master Delayed Read Timeout . . . . . . . . . . . . . . . . . . . . . . . 3–7

Secondary SERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

3.9

Parity Handling and Parity Error Reporting . . . . . . . . . . . . . . . . . . . . . . 3–7

3.9.1

3.9.2

Address Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Data Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

3.10 Master and Target Abort Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

3.11 Discard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

3.12 Delayed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3.13 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3.14 Compact PCI Hot-Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3.15 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

3.15.1

3.16 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

3.16.1 Secondary Clock Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

Test Port Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

iii

3.16.2

3.17 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

3.17.1 Behavior in Low Power States . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Transaction Forwarding Control . . . . . . . . . . . . . . . . . . . . . . . 3–15

4

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Primary Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

4.10 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

4.11 Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

4.12 Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

4.13 Primary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

4.14 Secondary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4.15 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4.16 Secondary Bus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4.17 I/O Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

4.18 I/O Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

4.19 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

4.20 Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.21 Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.22 Prefetchable Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.23 Prefetchable Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

4.24 Prefetchable Base Upper 32 Bits Register . . . . . . . . . . . . . . . . . . . . . . 4–12

4.25 Prefetchable Limit Upper 32 Bits Register . . . . . . . . . . . . . . . . . . . . . . 4–13

4.26 I/O Base Upper 16 Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

4.27 I/O Limit Upper 16 Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

4.28 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

4.29 Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . 4–14

4.30 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

4.31 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

4.32 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Chip Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Extended Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

P_SERR Event Disable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

GPIO Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

GPIO Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

GPIO Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

iv

5.8

5.9

Secondary Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

P_SERR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

5.10 PM Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

5.11 PM Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5.12 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 5–9

5.13 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 5–10

5.14 PMCSR Bridge Support Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

5.15 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

5.16 HS Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12

5.17 HS Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12

5.18 Hot Swap Control Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6

6.1

6.2

6.3

6.4

6.5

Absolute Maximum Ratings Over Operating Temperature Ranges . 6–1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

Recommended Operating Conditions for PCI Interface . . . . . . . . . . . 6–2

Electrical Characteristics Over Recommended Operating Conditions 6–3

PCI Clock/Reset Timing Requirements Over Recommended

Ranges Of Supply Voltage And Operating Free-Air Temperature . . . 6–4

6.6

PCI Timing Requirements Over Recommended Ranges Of

Supply Voltage And Operating Free-Air Temperature . . . . . . . . . . . . . 6–5

6.7

6.8

Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . 6–7

7

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

v

List of Illustrations

Figure

2–1

3–1

3–2

3–3

3–4

3–5

3–6

6–1

6–2

6–3

6–4

Title

Page

PCI2050 Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle 3–2

PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle 3–3

Bus Hierarchy and Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Secondary Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Clock Mask Read Timing After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

Load Circuit and Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

PCLK Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

RSTIN Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

Shared-Signals Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

vi

List of Tables

Table

Title

Page

2–1

2–2

2–3

2–4

2–5

2–6

2–7

2–8

2–9

208-Terminal PDV Signal Names Sorted by Terminal Number . . . . . . . . 2–2

Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

208-Terminal GHK Signal Names Sorted by Terminal Number . . . . . . . . 2–6

Primary PCI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Primary PCI Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Primary PCI Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Secondary PCI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Secondary PCI Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

Secondary PCI Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2–10 Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2–11 JTAG Interface Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

2–12 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

3–1

3–2

PCI Command Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

PCI S_AD31–S_AD16 During the Address Phase of a Type 0

Configuration Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

3–3

3–4

3–5

3–6

4–1

4–2

4–3

4–4

4–5

5–1

5–2

5–3

5–4

5–5

5–6

5–7

5–8

5–9

Configuration Via MS0 and MS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

JTAG Instructions and Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Boundary Scan Terminal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Clock Mask Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

Chip Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Extended Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

P_SERR Event Disable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

GPIO Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

GPIO Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

GPIO Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

Secondary Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

P_SERR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

5–10 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5–11 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . 5–10

5–12 PMCSR Bridge Support Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

5–13 Hot Swap Control Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13

vii

viii

1 Introduction

1.1 Description

The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high performance connection path between two

peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets

on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge

supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act

independently.

The PCI2050 bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical

loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The

PCI2050 provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with

an external secondary PCI bus arbiter.

The compact-PCI hot-swap extended PCI capability is provided which makes the PCI2050 an ideal solution for

multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050 bridge is compliant with the PCI-to-PCI Bridge Specification 1.1. The PCI 2050 provides compliance

for PCI Power Management 1.0 and 1.1. The PCI2050 has been designed to lead the industry in power conservation.

An advanced CMOS process is used to achieve low system power consumption while operating at PCI clock rates

up to 33 MHz.

1.2 Features

The PCI2050 supports the following features:

•

Configurable for PCI Bus Power Management Interface Specification

Provides compact PCI hot-swap functionality

3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

Two 32-bit, 33-MHz PCI buses

Provides internal two-tier arbitration for up to nine secondary bus masters and supports an external

secondary bus arbiter

•

Burst data transfers with pipeline architecture to maximize data throughput in both directions

Independent read and write buffers for each direction

Up to three delayed transactions in both directions

Provides 10 secondary PCI clock outputs

Predictable latency per PCI Local Bus Specification

Propagates bus locking

Secondary bus is driven low during reset

Provides VGA/palette memory and I/O, and subtractive decoding options

Advanced submicron, low-power CMOS technology

Packaged in 208-terminal QFP or 209-terminal MicroStar BGA

1–1

1.3 Related Documents

•

Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0)

PCI Local Bus Specification (Revision 2.2)

PCI-to-PCI Bridge Architecture Specification (Revision 1.1)

PCI Bus Power Management Interface Specification (Revision 1.1)

PICMG Compact-PCI Hot Swap Specification (Revision 1.0)

1.4 Ordering Information

ORDERING NUMBER

NAME

PCI–PCI Bridge

VOLTAGE

PACKAGE

208-terminal QFP

209-terminal MicroStar BGA

PCI2050

3.3 V, 5-V Tolerant I/Os

1–2

2 Terminal Descriptions

PDV LOW-PROFILE QUAD FLAT PACKAGE

TOP VIEW

V

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

CC

GND

S_AD11

GND

V

NC

CC

P_AD10

GND

P_AD11

P_AD12

S_AD12

S_AD13

V

CC

S_AD14

S_AD15

GND

S_C/BE1

S_PAR

V

CC

P_AD13

P_AD14

GND

P_AD15

P_C/BE1

S_SERR

V

CC

P_PAR

S_PERR

S_LOCK

S_STOP

GND

P_SERR

P_PERR

P_LOCK

GND

P_STOP

P_DEVSEL

P_TRDY

P_IRDY

S_DEVSEL

S_TRDY

S_IRDY

V

CC

S_FRAME

S_C/BE2

GND

S_AD16

S_AD17

V

CC

PCI2050

P_FRAME

P_C/BE2

GND

V

P_AD16

P_AD17

CC

S_AD18

S_AD19

GND

V

CC

P_AD18

P_AD19

GND

S_AD20

S_AD21

V

P_AD20

P_AD21

CC

S_AD22

S_AD23

V

CC

P_AD22

P_AD23

GND

S_C/BE3

S_AD24

V

P_IDSEL

P_C/BE3

P_AD24

CC

S_AD25

S_AD26

GND

V

CC

S_AD27

P_AD25

P_AD26

GND

S_AD28

V

CC

S_AD29

S_AD30

P_AD27

P_AD28

V

CC

GND

S_AD31

S_REQ0

P_AD29

GND

V

CC

Figure 2–1. PCI2050 Terminal Diagram

2–1

Table 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number

PDV GHK

NO.

SIGNAL NAME

NO.

D1

E3

NO.

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

NO.

P2

N5

P3

R1

P6

R2

P5

R3

T1

NO.

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

1

V

BPCCE

P_CLK

P_GNT

P_REQ

GND

87

V12 P_LOCK

U12 P_PERR

P12 P_SERR

R12 P_PAR

K17 TDO

K15

CC

2

S_REQ1

S_REQ2

88

V

CC

3

F5

89

K14 TMS

J19 TCLK

J18 TRST

4

G6 S_REQ3

90

5

E2

E1

F3

F2

S_REQ4

S_REQ5

S_REQ6

S_REQ7

91

W13

V

CC

6

P_AD31

P_AD30

92

V13 P_C/BE1

U13 P_AD15

P13 GND

J17 S_V

CCP

7

93

J14 GND

8

V

CC

GND

94

J15 S_AD0

H19 S_AD1

9

G5 S_REQ8

95

W14 P_AD14

V14 P_AD13

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

F1

H6

S_GNT0

S_GNT1

W4

U5

R6

P7

V5

V

CC

96

H18

V

CC

GND

97

R13

V

CC

H17 S_AD2

H14 S_AD3

H15 GND

G3 GND

P_AD29

98

U14 P_AD12

W15 P_AD11

P14 GND

G2 S_GNT2

G1 S_GNT3

V

99

CC

P_AD28

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

G19 S_AD4

G18 S_AD5

H5

H3

H2

H1

J1

S_GNT4

S_GNT5

S_GNT6

S_GNT7

S_GNT8

GND

W5 P_AD27

V15 P_AD10

R14 NC

U6

V6

R7

W6

P8

U7

V7

GND

G17

V

CC

P_AD26

P_AD25

U15

W16 GND

T19

V

CC

G14 S_AD6

F19 S_AD7

F18 GND

V

CC

V

CC

J2

P_AD24

P_C/BE3

P_IDSEL

R17 MS1

G15 S_C/BE0

F17 S_AD8

J3

S_CLK

P15 P_AD9

J5

S_RST

N14

V

CC

E19

V

CC

J6

S_CFN

W7 GND

R18 P_AD8

R19 P_C/BE0

P17 GND

F14 S_AD9

E18 S_M66ENA

F15 S_AD10

E17 MS0

K1

K2

K3

K5

K6

L1

L2

L3

L6

L5

M1

HSSWITCH/GPIO3

GPIO2

R8

U8

V8

P_AD23

P_AD22

V

CC

P18 P_AD7

N15 P_AD6

CC

GPIO1

W8 P_AD21

W9 P_AD20

D19 GND

GPIO0

P19

V

CC

A16

V

CC

S_CLKOUT0

S_CLKOUT1

GND

V9

U9

R9

P9

GND

M14 P_AD5

N17 P_AD4

N18 GND

C15 GND

P_AD19

P_AD18

E14 S_AD11

F13 GND

S_CLKOUT2

S_CLKOUT3

V

CC

N19 P_AD3

M15 P_AD2

B15 S_AD12

A15 S_AD13

W10 P_AD17

V10 P_AD16

U10 GND

V

M17

V

CC

C14

V

CC

M2 S_CLKOUT4

M3 S_CLKOUT5

M6 GND

M18 P_AD1

M19 P_AD0

L19 GND

B14 S_AD14

E13 S_AD15

A14 GND

R10 P_C/BE2

P10 P_FRAME

M5 S_CLKOUT6

W11

V

CC

L18 P_V

L17 NC

F12 S_C/BE1

C13 S_PAR

B13 S_SERR

CCP

N1

N2

N3

N6

P1

S_CLKOUT7

V11 P_IRDY

U11 P_TRDY

P11 P_DEVSEL

R11 P_STOP

W12 GND

V

L15 MSK_IN

L14 HSENUM

K19 HSLED

K18 TDI

CC

S_CLKOUT8

S_CLKOUT9

P_RST

A13

V

CC

E12 S_PERR

C12 S_LOCK

2–2

Table 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number (continued)

PDV GHK

SIGNAL NAME

NO.

173

174

175

176

177

178

179

180

181

NO.

182

183

184

185

186

187

188

189

190

NO.

191

192

193

194

195

196

197

198

199

NO.

B8

C8

F8

E8

A7

B7

C7

F7

A6

NO.

200

201

202

203

204

205

206

207

208

NO.

B6

E7

C6

A5

F6

B12 S_STOP

A12 GND

C10 S_AD16

E10 S_AD17

S_AD22

S_AD23

GND

S_AD27

S_AD28

A11 S_DEVSEL

B11 S_TRDY

C11 S_IRDY

F10

A9

B9

C9

F9

V

CC

V

CC

S_AD18

S_AD19

GND

S_C/BE3

S_AD24

S_AD29

S_AD30

GND

E11

V

CC

V

CC

B5

E6

C5

A4

F11 S_FRAME

A10 S_C/BE2

B10 GND

S_AD20

S_AD21

S_AD25

S_AD26

GND

S_AD31

S_REQ0

E9

A8

V

CC

V

CC

2–3

Table 2–2. Signal Names Sorted Alphabetically

PDV GHK

SIGNAL NAME

BPCCE

SIGNAL NAME

NO.

P2

G3

J2

NO.

122

121

119

118

116

115

113

112

109

107

101

99

NO.

194

23

21

29

30

32

33

35

36

38

39

41

42

175

179

10

11

NO.

44

P_AD0

P_AD1

P_AD2

P_AD3

M19 P_PAR

M18 P_PERR

M15 P_REQ

N19 P_RST

N17 P_SERR

M14 P_STOP

N15 P_TRDY

90

R12 S_C/BE3

U12 S_CFN

E8

GND

12

88

J6

GND

20

47

R1

P1

S_CLK

J3

GND

31

L3

43

S_CLKOUT0

L1

GND

37

M6 P_AD4

89

P12 S_CLKOUT1

R11 S_CLKOUT2

U11 S_CLKOUT3

L18 S_CLKOUT4

J15 S_CLKOUT5

H19 S_CLKOUT6

H17 S_CLKOUT7

H14 S_CLKOUT8

G19 S_CLKOUT9

G18 S_DEVSEL

G14 S_FRAME

F19 S_GNT0

L2

GND

48

P6

T1

U5

U6

P_AD5

P_AD6

P_AD7

P_AD8

85

L6

GND

52

83

L5

GND

54

P18 P_V

CCP

124

137

138

140

141

143

144

146

147

150

152

154

159

161

162

164

165

182

183

185

186

188

189

191

192

195

197

198

200

201

203

204

206

149

167

180

M2

M3

M5

N1

N3

N6

A11

F11

F1

GND

59

R18 S_AD0

P15 S_AD1

V15 S_AD2

W15 S_AD3

U14 S_AD4

V14 S_AD5

W14 S_AD6

U13 S_AD7

V10 S_AD8

W10 S_AD9

GND

66

W7 P_AD9

V9 P_AD10

GND

72

GND

78

U10 P_AD11

W12 P_AD12

P13 P_AD13

P14 P_AD14

W16 P_AD15

P17 P_AD16

N18 P_AD17

L19 P_AD18

J14 P_AD19

H15 P_AD20

F18 P_AD21

D19 P_AD22

C15 P_AD23

F13 P_AD24

A14 P_AD25

A12 P_AD26

B10 P_AD27

GND

86

98

GND

94

96

GND

100

104

111

117

123

136

142

148

156

158

160

166

174

181

187

193

199

205

28

95

GND

93

GND

77

F17 S_GNT1

H6

G2

G1

H5

H3

H2

H1

J1

GND

76

F14 S_GNT2

13

14

15

16

17

18

19

177

172

153

168

171

207

2

GND

74

R9

U9

S_AD10

S_AD11

F15 S_GNT3

GND

73

E14 S_GNT4

GND

71

W9 S_AD12

W8 S_AD13

B15 S_GNT5

GND

70

A15 S_GNT6

GND

68

U8

R8

P8

R7

V6

S_AD14

S_AD15

S_AD16

S_AD17

S_AD18

B14 S_GNT7

GND

67

E13 S_GNT8

GND

63

C10 S_IRDY

C11

C12

E18

C13

E12

C5

E3

GND

61

E10 S_LOCK

GND

60

A9

B9

F9

E9

B8

C8

A7

C7

F7

B6

E7

A5

F6

E6

S_M66ENA

S_PAR

GND

58

W5 S_AD19

GND

C9

F8

A6

B5

K6

K5

K2

P_AD28

P_AD29

P_AD30

P_AD31

P_C/BE0

P_C/BE1

P_C/BE2

57

V5

R6

P5

R2

S_AD20

S_AD21

S_AD22

S_AD23

S_PERR

S_REQ0

S_REQ1

S_REQ2

S_REQ3

S_REQ4

S_REQ5

S_REQ6

S_REQ7

S_REQ8

S_RST

GND

55

GND

50

GND

49

3

F5

GPIO0

GPIO1

GPIO2

HSENUM

HSLED

HSSWITCH/GPIO3

MS0

110

92

R19 S_AD24

V13 S_AD25

R10 S_AD26

4

G6

E2

27

5

25

79

6

E1

127

128

24

L14 P_C/BE3

K19 P_CLK

64

U7

N5

S_AD27

S_AD28

7

F3

45

8

F2

K1

P_DEVSEL

84

P11 S_AD29

P10 S_AD30

9

G5

J5

155

106

126

102

125

E17 P_FRAME

R17 P_GNT

L15 P_IDSEL

R14 P_IRDY

L17 P_LOCK

80

22

169

173

176

135

MS1

46

P3

V7

S_AD31

S_SERR

B13

B12

B11

J17

MSK_IN

NC

65

S_C/BE0

G15 S_STOP

F12 S_TRDY

82

V11 S_C/BE1

V12 S_C/BE2

NC

87

A10 S_V

CCP

2–4

Table 2–2. Signal Names Sorted Alphabetically (continued)

PDV GHK

SIGNAL NAME

NO.

133

129

130

132

134

1

NO.

J19

K18

K17

K14

J18

D1

NO.

51

53

56

62

69

75

81

91

97

NO.

103

105

108

114

120

131

139

145

151

NO.

U15

T19

N14

P19

M17

K15

H18

G17

E19

NO.

157

163

170

178

184

190

196

202

208

NO.

A16

C14

A13

E11

F10

A8

TCLK

TDI

V

R3

V

CC

V

W4

P7

V

TDO

TMS

TRST

W6

V8

V

CC

V

CC

V

CC

V

CC

P9

26

K3

W11

W13

R13

B7

34

M1

C6

40

N2

A4

2–5

Table 2–3. 209-Terminal GHK Signal Names Sorted by Terminal Number

GHK

NO.

GHK

NO.

GHK

NO.

GHK

NO.

GHK

NO.

SIGNAL NAME

A4

A5

A6

A7

A8

A9

V

E9

S_AD21

H17 S_AD2

H18

H19 S_AD1

N1

N2

S_CLKOUT7

T19

U5

U6

U7

U8

U9

V

CC

S_AD29

E10 S_AD17

E11

V

CC

V

CC

GND

V

CC

N3

S_CLKOUT8

P_CLK

GND

S_AD24

E12 S_PERR

E13 S_AD15

E14 S_AD11

E17 MS0

J1

J2

J3

J5

J6

S_GNT8

GND

N5

P_C/BE3

P_AD22

P_AD19

V

N6

S_CLKOUT9

CC

S_AD18

S_CLK

S_RST

S_CFN

N14

V

CC

A10 S_C/BE2

A11 S_DEVSEL

A12 GND

N15 P_AD6

N17 P_AD4

N18 GND

U10 GND

E18 S_M66ENA

U11 P_TRDY

U12 P_PERR

U13 P_AD15

U14 P_AD12

E19

F1

V

CC

J14 GND

A13

V

CC

S_GNT0

S_REQ7

S_REQ6

S_REQ2

S_AD30

S_AD26

GND

J15 S_AD0

N19 P_AD3

A14 GND

F2

J17 S_V

CCP

P1

P2

P3

P5

P6

P7

P8

P9

P_RST

BPCCE

P_GNT

P_AD30

GND

A15 S_AD13

F3

J18 TRST

J19 TCLK

U15

V5

V6

V7

V8

V9

V

CC

A16

B5

B6

B7

B8

B9

V

CC

F5

P_AD28

P_AD26

P_IDSEL

GND

F6

K1

K2

K3

K5

K6

HSSWITCH/GPIO3

GPIO2

S_AD27

F7

V

CC

F8

V

CC

V

CC

GND

CC

P_AD24

S_AD22

S_AD19

F9

S_AD20

GPIO1

GPIO0

F10

V

CC

V

CC

V10 P_AD16

V11 P_IRDY

V12 P_LOCK

V13 P_C/BE1

V14 P_AD13

V15 P_AD10

B10 GND

F11 S_FRAME

F12 S_C/BE1

F13 GND

K14 TMS

K15

P10 P_FRAME

P11 P_DEVSEL

P12 P_SERR

P13 GND

B11 S_TRDY

B12 S_STOP

B13 S_SERR

B14 S_AD14

B15 S_AD12

V

CC

K17 TDO

K18 TDI

F14 S_AD9

F15 S_AD10

F17 S_AD8

F18 GND

K19 HSLED

P14 GND

L1

L2

L3

L5

L6

S_CLKOUT0

P15 P_AD9

P17 GND

W4

W5 P_AD27

W6

V

CC

C5

C6

C7

C8

C9

S_REQ0

S_CLKOUT1

GND

V

CC

F19 S_AD7

G1 S_GNT3

G2 S_GNT2

G3 GND

P18 P_AD7

V

CC

S_AD25

S_AD23

GND

S_CLKOUT3

S_CLKOUT2

P19

R1

R2

R3

R6

R7

R8

R9

R10

V

CC

W7 GND

P_REQ

P_AD31

W8 P_AD21

W9 P_AD20

W10 P_AD17

L14 HSENUM

L15 MSK_IN

L17 NC

C10 S_AD16

C11 S_IRDY

C12 S_LOCK

C13 S_PAR

G5 S_REQ8

G6 S_REQ3

G14 S_AD6

G15 S_C/BE0

V

CC

P_AD29

P_AD25

P_AD23

P_AD18

W11

W12 GND

W13

V

CC

L18 P_V

CCP

L19 GND

M1

V

CC

C14

C15 GND

D1

D19 GND

V

CC

G17

V

CC

V

CC

W14 P_AD14

W15 P_AD11

W16 GND

G18 S_AD5

G19 S_AD4

M2 S_CLKOUT4

M3 S_CLKOUT5

M5 S_CLKOUT6

M6 GND

V

CC

V

CC

R11 P_STOP

R12 P_PAR

H1

H2

H3

H5

H6

S_GNT7

S_GNT6

S_GNT5

S_GNT4

S_GNT1

E1

E2

E3

E6

E7

E8

S_REQ5

R13

V

CC

S_REQ4

S_REQ1

S_AD31

S_AD28

S_C/BE3

M14 P_AD5

R14 NC

M15 P_AD2

R17 MS1

M17

V

CC

R18 P_AD8

R19 P_C/BE0

H14 S_AD3

H15 GND

M18 P_AD1

M19 P_AD0

T1

GND

2–6

Table 2–4. Primary PCI System

TERMINAL

PDV

I/O

DESCRIPTION

GHK

NO.

NAME

NO.

Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI

signals are sampled at rising edge of P_CLK.

P_CLK

P_RST

45

N5

I

PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers

in a high–impedance state and reset all internal registers. When asserted, the device is completely

nonfunctional.DuringP_RST, thesecondaryinterfaceisdrivenlow. AfterP_RSTisdeasserted, thebridge

is in its default state.

43

P1

I

Table 2–5. Primary PCI Address and Data

TERMINAL

PDV

I/O

DESCRIPTION

GHK

NAME

NO.

P_AD31

P_AD30

P_AD29

P_AD28

P_AD27

P_AD26

P_AD25

P_AD24

P_AD23

P_AD22

P_AD21

P_AD20

P_AD19

P_AD18

P_AD17

P_AD16

P_AD15

P_AD14

P_AD13

P_AD12

P_AD11

P_AD10

P_AD9

49

50

55

57

58

60

61

63

67

68

70

71

73

74

76

77

93

R2

P5

R6

V5

W5

V6

R7

P8

R8

U8

W8

W9

U9

R9

W10

V10

U13

W14

V14

U14

W15

V15

P15

R18

P18

N15

M14

N17

N19

M15

M18

M19

Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the

primary interface. During the address phase of a primary bus PCI cycle, P_AD31–P_AD0 contain a

32-bit address or other destination information. During the data phase, P_AD31–P_AD0 contain data.

I/O

95

96

98

99

101

107

109

112

113

115

116

118

119

121

122

P_AD8

P_AD7

P_AD6

P_AD5

P_AD4

P_AD3

P_AD2

P_AD1

P_AD0

Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.

During the address phase of a primary bus PCI cycle, P_C/BE3–P_C/BE0 define the bus command.

During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte

paths of the full 32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7–P_AD0),

P_C/BE1 applies to byte 1 (P_AD15–P_AD8), P_C/BE2 applies to byte 2 (P_AD23–P_AD16), and

P_C/BE3 applies to byte 3 (P_AD31–P_AD24).

64

79

92

U7

P_C/BE3

P_C/BE2

P_C/BE1

P_C/BE0

R10

V13

R19

I/O

110

2–7

Table 2–6. Primary PCI Interface Control

TERMINAL

PDV

I/O

DESCRIPTION

GHK

NO.

NAME

NO.

Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As

a PCI initiator on the primary bus, the bridge monitors P_DEVSEL until a target responds. If no target

responds before time-out occurs, then the bridge terminates the cycle with an initiator abort.

P_DEVSEL

P_FRAME

P_GNT

84

P11

P10

P3

I/O

I

Primary cycle frame. P_FRAME is driven by the initiator of a primary bus cycle. P_FRAME is asserted

to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.

When P_FRAME is deasserted, the primary bus transaction is in the final data phase.

80

46

Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access

to the primary PCI bus after the current data transaction has completed. P_GNT may or may not follow

a primary bus request, depending on the primary bus parking algorithm.

Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses.

P_IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus.

P_IDSEL

65

V7

I

Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space

of the bridge can only be accessed from the primary bus.

Primaryinitiatorready. P_IRDYindicatesabilityoftheprimarybusinitiatortocompletethecurrentdata

phase of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY

and P_TRDY are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are

inserted.

P_IRDY

P_LOCK

P_PAR

82

87

90

V11

V12

R12

I/O

PrimaryPCIbuslock. P_LOCKisusedtolocktheprimarybusandgainexclusiveaccessasaninitiator.

Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the

P_ADandP_C/BEbuses. AsaninitiatorduringPCIwritecycles, thebridgeoutputsthisparityindicator

with a one-P_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the

parity indicator of the initiator; a miscompare can result in a parity error assertion (P_PERR).

Primaryparity error indicator. P_PERR is driven by a primary bus PCIdevicetoindicatethatcalculated

parity does not match P_PAR when P_PERR is enabled through bit 6 of the command register.

88

47

U12

R1

I/O

O

P_PERR

P_REQ

Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as an

initiator.

Primary system error. Output pulsed from the bridge when enabled through the command register

indicating a system error has occurred. The bridge needs not be the target of the primary PCI cycle

to assert this signal. When bit 6 is enabled in the bridge control register (offset 3Eh, see Section 4.32),

this signal also pulses indicating that a system error has occurred on one of the subordinate buses

downstream from the bridge.

P_SERR

89

P12

O

Primary cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current

primary bus transaction. This signal is used for target disconnects and is commonly asserted by target

devices which do not support burst data transfers.

P_STOP

P_TRDY

85

83

R11

U11

I/O

Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current

data phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both

P_IRDY and P_TRDY are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are

inserted.

2–8

Table 2–7. Secondary PCI System

TERMINAL

PDV

I/O

DESCRIPTION

GHK

NO.

NAME

NO.

42

41

39

38

36

35

33

32

30

29

N6

N3

N1

M5

M3

M2

L5

L6

L2

L1

S_CLKOUT9

S_CLKOUT8

S_CLKOUT7

S_CLKOUT6

S_CLKOUT5

S_CLKOUT4

S_CLKOUT3

S_CLKOUT2

S_CLKOUT1

S_CLKOUT0

Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each

secondary bus device samples all secondary PCI signals at the rising edge of its corresponding

S_CLKOUT input.

O

21

J3

J6

I

Secondary PCI bus clock input. This input syncronizes the PCI2050 to the secondary bus clocks.

S_CLK

Secondaryexternalarbiterenable. Whenthissignalishigh, thesecondaryexternalarbiterisenabled.

When the external arbiter is enabled, the PCI2050 S_REQ0 pin is reconfigured as a secondary bus

grant input to the bridge and S_GNT0 is reconfigured as a secondary bus master request to the

external arbiter on the secondary bus.

S_CFN

23

Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit

(bit 6) of the bridge control register (offset 3Eh, see Section 4.32). S_RST is asynchronous with

respect to the state of the secondary interface CLK signal.

S_RST

22

J5

O

2–9

Table 2–8. Secondary PCI Address and Data

TERMINAL

PDV

I/O

DESCRIPTION

GHK

NO.

NAME

NO.

206

204

203

201

200

198

197

195

192

191

189

188

186

185

183

182

165

164

162

161

159

154

152

150

147

146

144

143

141

140

138

137

E6

F6

A5

E7

B6

F7

C7

A7

C8

B8

E9

F9

B9

S_AD31

S_AD30

S_AD29

S_AD28

S_AD27

S_AD26

S_AD25

S_AD24

S_AD23

S_AD22

S_AD21

S_AD20

S_AD19

S_AD18

S_AD17

S_AD16

S_AD15

S_AD14

S_AD13

S_AD12

S_AD11

S_AD10

S_AD9

A9

E10

C10

E13

B14

A15

B15

E14

F15

F14

F17

F19

G14

G18

G19

H14

H17

H19

J15

Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on

the secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31–S_AD0

contain a 32-bit address or other destination information. During the data phase, S_AD31–S_AD0

contain data.

I/O

S_AD8

S_AD7

S_AD6

S_AD5

S_AD4

S_AD3

S_AD2

S_AD1

S_AD0

Secondary bus commands and byte enables. These signals are multiplexed on the same PCI

terminals. During the address phase of a secondary bus PCI cycle, S_C/BE3–S_C/BE0define the bus

command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine

which byte paths of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0

(S_AD7–S_AD0), S_C/BE1 applies to byte 1 (S_AD15–S_AD8), S_C/BE2 applies to byte 2

(S_AD23–S_AD16), and S_C/BE3 applies to byte 3 (S_AD31–S_AD24).

S_C/BE3

S_C/BE2

S_C/BE1

S_C/BE0

194

180

167

149

E8

A10

F12

G15

I/O

Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As

aPCIinitiatoronthesecondarybus,thebridgemonitorsS_DEVSELuntilatargetresponds.Ifnotarget

responds before timeout occurs, then the bridge terminates the cycle with an initiator abort.

S_DEVSEL

S_FRAME

175

179

A11

F11

I/O

Secondary cycle frame. S_FRAME is driven by the initiator of a secondary bus cycle. S_FRAME is

asserted to indicate that a bus transaction is beginning and data transfers continue while S_FRAME

is asserted. When S_FRAME is deasserted, the secondary bus transaction is in the final data phase.

S_GNT8

S_GNT7

S_GNT6

S_GNT5

S_GNT4

S_GNT3

S_GNT2

S_GNT1

S_GNT0

19

18

17

16

15

14

13

11

10

J1

H1

H2

H3

H5

G1

G2

H6

F1

Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used

to grant potential secondary PCI bus masters access to the bus. Ten potential initiators (including the

bridge) can be located on the secondary PCI bus.

O

When the internal arbiter is disabled, S_GNT0 is reconfigured as an external secondary bus request

signal for the bridge.

2–10

Table 2–9. Secondary PCI Interface Control

TERMINAL

PDV

I/O

DESCRIPTION

GHK

NO.

NAME

NO.

Secondary initiator ready. S_IRDY indicates the ability of the secondary bus initiator to complete the

current data phase of the transaction. A data phase is completed on a rising edge of S_PCLKn where

both S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are

inserted.

S_IRDY

S_LOCK

S_PAR

177

C11

C12

C13

E12

I/O

Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as an

initiator.

172

168

171

Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across

the S_AD and S_C/BE buses. As an initiator during PCI write cycles, the bridge outputs this parity

indicator with a one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared

to the initiator parity indicator. A miscompare can result in a parity error assertion (S_PERR).

Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that

calculated parity does not match S_PAR when enabled through the command register.

S_PERR

S_REQ8

S_REQ7

S_REQ6

S_REQ5

S_REQ4

S_REQ3

S_REQ2

S_REQ1

S_REQ0

9

8

7

6

5

4

3

2

207

G5

F2

F3

E1

E2

G6

F5

E3

C5

Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used

as inputs from secondary PCI bus initiators requesting the bus. Ten potential initiators (including the

bridge) can be located on the secondary PCI bus.

I

When the internal arbiter is disabled, the S_REQ0 signal is reconfigures as an external secondary bus

grant for the bridge.

Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled

through the bridge control register. S_SERR is never asserted by the bridge.

169

173

B13

I

S_SERR

S_STOP

Secondary cycle stop signal. S_STOP is driven by a PCI target to request the initiator to stop the current

secondary bus transaction. S_STOP is used for target disconnects and is commonly asserted by target

devices that do not support burst data transfers.

B12

I/O

Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the

current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both

S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.

S_TRDY

176

B11

I/O

Table 2–10. Miscellaneous Terminals

TERMINAL

PDV

I/O

DESCRIPTION

GHK

NO.

NAME

NO.

Bus/powerclock control management terminal. When signal BPCCE is tied high, and when the

PCI2050 is placed in the D3 power state, it enables the PCI2050 to place the secondary bus

in the B2 power state. The PCI2050 disables the secondary clocks and drives them to 0. When

tied low, placing the PCI2050 in the D3 power state has no effect on the secondary bus clocks.

BPCCE

44

P2

I

GPIO3/HSSWITCH

GPIO2

24

25

27

28

K1

K2

K5

K6

General-purpose I/O pins

I

GPIO3 is HSSWITCH in CPCI mode.

GPIO1

GPIO0

HSSWITCH provides the status of the ejector handle switch to the CPCI logic.

HSENUM

HSLED

MS0

127

128

155

106

L14

K19

E17

R17

O

I

Hot swap ENUM

Hot swap LED output

Mode select 0

I

Mode select 1

MS1

102

125

R14

L17

NC

O

These terminals have no function on the PCI2050.

Secondary bus 66-MHz enable pin. This pin is always driven low to incicate that the secondary

bus speed is 33 MHz.

S_M66ENA

153

E18

2–11

Table 2–11. JTAG Interface Terminals

TERMINAL

PDV

I/O

DESCRIPTION

GHK

NO.

NAME

NO.

TCLK

TDI

133

J19

I

JTAG boundary-scan clock. TCLK is the clock controlling the JTAG logic.

JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the

JTAG interface. The new data on TDI is sampled on the rising edge of TCLK.

129

K18

JTAG serial data out. TDO is the serial output through which test instructions and data from the test

logic leave the PCI2050.

TDO

TMS

130

132

134

K17

K14

J18

O

I

JTAG test mode select. TMS causes state transitions in the test access port controller.

JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter

a reset state and initialize the test logic.

TRST

I

Table 2–12. Power Supply

TERMINAL

DESCRIPTION

GHK NO.

NAME

PDV NO.

12, 20, 31, 37, 48, 52, 54,

59, 66, 72, 78, 86, 94, 100,

104, 111, 117, 123, 136,

142, 148, 156, 158, 160,

166, 174, 181, 187, 193,

199, 205

A6, A12, A14, B5, B10, C9,

C15, D19, F8, F13, F18,

G3, H15, J2, J14, L3, L19,

Device ground terminals

M6, N18, P6, P13, P14,

P17, T1, U5, U6, U10, V9,

W7, W12, W16

GND

1, 26, 34, 40, 51, 53, 56, 62, A4, A8, A13, A16, B7, C6,

69, 75, 81, 91, 97, 103, 105,

108, 114, 120, 131, 139,

145, 151, 157, 163, 170,

178, 184, 190, 196, 202,

208

C14, D1, E11, E19, F10,

G17, H18, K3, K15, M1,

M17, N2, N14, P7, P9, P19,

R3, R13, T19, U15, V8, W4,

W6, W11, W13

V

CC

Power-supply terminal for core logic (3.3 V)

Primary bus-signaling environment supply. P_V

protection circuitry on primary bus I/O signals.

is used in

CCP

P_V

S_V

124

135

L18

J17

CCP

Secondary bus-signaling environment supply. S_V

protection circuitry on secondary bus I/O signals.

CCP

2–12

3 Feature/Protocol Descriptions

The following sections give an overview of the PCI2050 PCI-to-PCI bridge features and functionality. Figure 3–1

shows a simplified block diagram of a typical system implementation using the PCI2050.

Host Bus

Memory

CPU

Host

PCI

Bridge

Device

PCI Bus 0

PCI Option Card

PCI2050

PCI Bus 2

PCI Bus 1

PCI

Device

PCI

Device

(Option)

PCI2050

PCI Option Slot

Figure 3–1. System Block Diagram

3.1 Introduction to the PCI2050

The PCI2050 is a bridge between two PCI buses and is compliant with both the PCI Local Bus Specification and the

PCI-to-PCI Bridge Specification. The bridge supports two 32-bit PCI buses operating at a maximum of 33 MHz. The

primary and secondary buses operate independently in either a 3.3-V or 5-V signaling environment. The core logic

of the bridge, however, is powered at 3.3 V to reduce power consumption.

Host software interacts with the bridge through internal registers. These internal registers provide the standard PCI

status and control for both the primary and secondary buses. Many vendor-specific features that exist in the TI

extension register set are included in the bridge. The PCI configuration header of the bridge is only accessible from

the primary PCI interface.

The bridge provides internal arbitration for the nine possible secondary bus masters, and provides each with a

dedicated active low request/grant pair (REQ/GNT). The arbiter features a two-tier rotational scheme with the

PCI2050 bridge defaulting to the highest priority tier.

Upon system power up, power-on self-test (POST) software configures the bridge according to the devices that exist

on subordinate buses, and enables performance-enhancing features of the PCI2050. In a typical system, this is the

only communication with the bridge internal register set.

3–1

3.2 PCI Commands

The bridge responds to PCI bus cycles as a PCI target device based on the decoding of each address phase and

internal register settings. Table 3–1 lists the valid PCI bus cycles and their encoding on the command/byte enables

(C/BE) bus during the address phase of a bus cycle.

Table 3–1. PCI Command Definition

COMMAND

Interrupt acknowledge

Special cycle

C/BE3–C/BE0

0000

0001

0010

0011

I/O read

I/O write

0100

0101

0110

Reserved

Memory read

0111

Memory write

1000

1001

1010

1011

Reserved

Configuration read

Configuration write

Memory read multiple

Dual address cycle

Memory read line

Memory write and invalidate

1100

1101

1110

1111

The bridge never responds as a PCI target to the interrupt acknowledge, special cycle, or reserved commands. The

bridge does, however, initiate special cycles on both interfaces when a type 1 configuration cycle issues the special

cycle request. The remaining PCI commands address either memory, I/O, or configuration space. The bridge accepts

PCI cycles by asserting DEVSEL as a medium-speed device, i.e., DEVSEL is asserted two clock cycles after the

address phase.

The PCI2050 converts memory write and invalidate commands to memory write commands when forwarding

transactionsfromeithertheprimaryorsecondarysideofthebridgeifthebridgecannotguaranteethatanentirecache

line will be delivered.

3.3 Configuration Cycles

PCI Local Bus Specification defines two types of PCI configuration read and write cycles: type 0 and type 1. The

bridge decodes each type differently. Type 0 configuration cycles are intended for devices on the primary bus, while

type 1 configuration cycles are intended for devices on some hierarchically subordinate bus. The difference between

these two types of cycles is the encoding of the primary PCI (P_AD) bus during the address phase of the cycle.

Figure 3–2 shows the P_AD bus encoding during the address phase of a type 0 configuration cycle. The 6-bit register

number field represents an 8-bit address with the two lower bits masked to 0, indicating a double-word boundary. This

results in a 256-byte configuration address space per function per device. Individual byte accesses may be selected

within a doubleword by using the P_C/BE signals during the data phase of the cycle.

31

11

10

Function

Number

8

7

2

1

0

Register

Number

Reserved

Figure 3–2. PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle

The bridge claims only type 0 configuration cycles when its P_IDSEL terminal is asserted during the address phase

of the cycle and the PCI function number encoded in the cycle is 0. If the function number is 1 or greater, then the

3–2

bridge does not recognize the configuration command. In this case, the bridge does not assert DEVSEL, and the

configuration transaction results in a master abort. The bridge services valid type 0 configuration read or write cycles

by accessing internal registers from the configuration header (see Table 4–1).

Because type 1 configuration cycles are issued to devices on subordinate buses, the bridge claims type 1 cycles

based on the bus number of the destination bus. The P_AD bus encoding during the address phase of a type 1 cycle

is shown in Figure 3–3. The device number and bus number fields define the destination bus and device for the cycle.

31

24

23

16

15

11

10

Function

Number

8

7

2

1

0

1

Device

Number

Register

Number

Reserved

Bus Number

Figure 3–3. PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle

Several bridge configuration registers shown in Table 4–1 are significant when decoding and claiming type 1

configuration cycles. The destination bus number encoded on the P_AD bus is compared to the values programmed

in the bridge configuration registers 18h, 19h, and 1Ah, which are the primary bus number, secondary bus number,

and subordinate bus number registers, respectively. These registers default to 00h and are programmed by host

software to reflect the bus hierarchy in the system (see Figure 3–4 for an example of a system bus hierarchy and how

the PCI2050 bus number registers would be programmed in this case).

When the PCI2050 claims a type 1 configuration cycle that has a bus number equal to its secondary bus number,

the PCI2050 converts the type 1 configuration cycle to a type 0 configuration cycle and asserts the proper S_AD line

as the IDSEL (see Table 3–2). All other type 1 transactions that access a bus number greater than the bridge

secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1 configuration

cycles.

Table 3–2. PCI S_AD31–S_AD16 During the Address

Phase of a Type 0 Configuration Cycle

SECONDARY IDSEL

S_AD31–S_AD16

S_AD

ASSERTED

DEVICE

NUMBER

0h

1h

0000 0000 0000 0001

0000 0000 0000 0010

0000 0000 0000 0100

0000 0000 0000 1000

0000 0000 0001 0000

0000 0000 0010 0000

0000 0000 0100 0000

0000 0000 1000 0000

0000 0001 0000 0000

0000 0010 0000 0000

0000 0100 0000 0000

0000 1000 0000 0000

0001 0000 0000 0000

0010 0000 0000 0000

0100 0000 0000 0000

1000 0000 0000 0000

0000 0000 0000 0000

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

–

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

10h–1Eh

3–3

PCI Bus 0

PCI2050

Primary Bus

Secondary Bus

Subordinate Bus

PCI2050

Primary Bus

Secondary Bus

Subordinate Bus

00h

01h

02h

00h

03h

PCI Bus 1

PCI Bus 3

PCI2050

Primary Bus

Secondary Bus

Subordinate Bus

01h

02h

PCI Bus 2

Figure 3–4. Bus Hierarchy and Numbering

3.4 Special Cycle Generation

The bridge is designed to generate special cycles on both buses through a type 1 cycle conversion. During a type 1

configuration cycle, if the bus number field matches the bridge secondary bus number, the device number field is 1Fh,

and the function number field is 07h, then the bridge generates a special cycle on the secondary bus with a message

that matches the type 1 configuration cycle data. If the bus number is a subordinate bus and not the secondary, then

the bridge passes the type 1 special cycle request through to the secondary interface along with the proper message.

Special cycles are never passed through the bridge. Type 1 configuration cycles with a special cycle request can

propagate in both directions.

3.5 Secondary Clocks

The PCI2050 provides 10 secondary clock outputs (S_CLKOUT[0:9]). Nine are provided for clocking secondary

devices. The tenth clock should be routed back into the PCI2050 S_CLK input to ensure all secondary bus devices

see the same clock.

3–4

S_CLK

PCI2050

S_CLKOUT9

S_CLKOUT3

PCI

Device

PCI

Device

S_CLKOUT2

S_CLKOUT1

PCI

Device

PCI

Device

S_CLKOUT0

Figure 3–5. Secondary Clock Block Diagram

3.6 Bus Arbitration

The PCI2050 implements bus request (P_REQ) and bus grant (P_GNT) terminals for primary PCI bus arbitration.

Nine secondary bus requests and nine secondary bus grants are provided on the secondary of the PCI2050. Ten

potential initiators, including the bridge, can be located on the secondary bus. The PCI2050 provides a two-tier

arbitration scheme on the secondary bus for priority bus-master handling.

The two-tier arbitration scheme improves performance in systems in which master devices do not all require the same

bandwidth. Any master that requires frequent use of the bus can be programmed to be in the higher priority tier.

3.6.1 Primary Bus Arbitration

The PCI2050, acting as an initiator on the primary bus, asserts P_REQ when forwarding transactions upstream to

the primary bus. If a target disconnect, a target retry, or a target abort is received in response to a transaction initiated

on the primary bus by the PCI2050, then the device deasserts P_REQ for two PCI clock cycles.

When the primary bus arbiter asserts P_GNT in response to a P_REQ from the PCI2050, the device initiates a

transaction on the primary bus during the next PCI clock cycle after the primary bus is sampled idle.

When P_REQ is not asserted and the primary bus arbiter asserts P_GNT to the PCI2050, the device responds by

parking the P_AD31–P_AD0 bus, the C/BE3–C/BE0 bus, and primary parity (P_PAR) by driving them to valid logic

levels. If the PCI2050 is parking the primary bus and wants to initiate a transaction on the bus, then it can start the

transaction on the next PCI clock by asserting the primary cycle frame (P_FRAME) while P_GNT is still asserted. If

P_GNT is deasserted, then the bridge must rearbitrate for the bus to initiate a transaction.

3.6.2 Internal Secondary Bus Arbitration

S_CFN controls the state of the secondary internal arbiter. The internal arbiter can be enabled by pulling S_CFN low

or disabled by pulling S_CFN high. The PCI2050 provides nine secondary bus request terminals and nine secondary

3–5

bus grant terminals. Including the bridge, there are a total of ten potential secondary bus masters. These request and

grant signals are connected to the internal arbiter. When an external arbiter is implemented, S_REQ8–S_REQ1 and

S_GNT8–S_GNT1 are placed in a high impedance mode.

3.6.3 External Secondary Bus Arbitration

An external secondary bus arbiter can be used instead of the PCI2050 internal bus arbiter. When using an external

arbiter, the PCI2050 internal arbiter should be disabled by pulling S_CFN high.

When an external secondary bus arbiter is used, the PCI2050 internally reconfigures the S_REQ0 and S_GNT0

signals so that S_REQ0 becomes the secondary bus grant for the bridge and S_GNT0 becomes the secondary bus

request for the bridge. This is done because S_REQ0 is an input and can thus be used to provide the grant input to

the bridge, and S_GNT0 is an output and can thus provide the request output from the bridge.

When an external arbiter is used, all unused secondary bus grant outputs (S_GNT8–S_GNT1) are placed in a high

impedance mode. Any unused secondary bus request inputs (S_REQ8–S_REQ1) should be pulled high to prevent

the inputs from oscillating.

3.7 Decode Options

The PCI2050 supports positive decoding on the primary interface and negative decoding on the secondary interface.

Positive decoding is a method of address decoding in which a device responds only to accesses within an assigned

address range. Negative decoding is a method of address decoding in which a device responds only to accesses

outside of an assigned address range.

3.8 System Error Handling

The PCI2050 can be configured to signal a system error (SERR) for a variety of conditions. The P_SERR event

disable register (offset 64h, see Section 5.4) and the P_SERR status register (offset 6Ah, see Section 5.9) provide

control and status bits for each condition for which the bridge can signal SERR. These individual bits enable SERR

reporting for both downstream and upstream transactions.

By default, the PCI2050 will not signal SERR. If the PCI2050 is configured to signal SERR by setting bit 8 in the

command register (offset 04h, see Section 4.3), then the bridge signals SERR if any of the error conditions in the

P_SERR event disable register occur and that condition is enabled. By default, all error conditions are enabled in the

P_SERR event disable register. When the bridge signals SERR, bit 14 in the secondary status register (offset 1Eh,

see Section 4.19) is set.

3.8.1 Posted Write Parity Error

If bit 1 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0, then parity errors on the target bus

duringapostedwritearepassedtotheinitiatingbusasaSERR. When this occurs, bit 1 of the P_SERR status register

(offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

3.8.2 Posted Write Timeout

If bit 2 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while

attempting to complete a posted write, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 2

of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

3.8.3 Target Abort on Posted Writes

If bit 3 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the bridge receives a target abort

during a posted write transaction, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 3 of

the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

3–6

3.8.4 Master Abort on Posted Writes

If bit 4 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and a posted write transaction results

in a master abort, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 4 of the P_SERR status

register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

3.8.5 Master Delayed Write Timeout

If bit 5 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while

attempting to complete a delayed write, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 5

of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

3.8.6 Master Delayed Read Timeout

If bit 6 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while

attempting to complete a delayed read, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 6

of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.

3.8.7 Secondary SERR

The PCI2050 passes SERR from the secondary bus to the primary bus if it is enabled for SERR response (bit 8 in

the command register (offset 04h, see Section 4.3) is 1) and bit 1 in the bridge control register (offset 3Eh, see

Section 4.32) is set.

3.9 Parity Handling and Parity Error Reporting

When forwarding transactions, the PCI2050 attempts to pass the data parity condition from one interface to the other

unchanged, whenever possible, to allow the master and target devices to handle the error condition.

3.9.1 Address Parity Error

If the parity error response bit (bit 6) in the command register (offset 04h, see Section 4.3) is set, then the PCI2050

signals SERR on address parity errors and target abort transactions.

3.9.2 Data Parity Error

If the parity error response bit (bit 6) in the command register (offset 04h, see Section 4.3) is set, then the PCI2050

signalsPERR when it receives bad data. When the bridge detects bad parity, bit 15 (detected parity error) in the status

register (offset 06h, see Section 4.4) is set.

If the bridge is configured to respond to parity errors via bit 6 in the command register (offset 04h, see Section 4.3),

then bit 8 (data parity error detected) in the status register (offset 06h, see Section 4.4) is set when the bridge detects

bad parity. The data parity error detected bit is also set when the bridge, as a bus master, asserts PERR or detects

PERR.

3.10 Master and Target Abort Handling

If the PCI2050 receives a target abort during a write burst, then it signals target abort back on the initiator bus. If it

receives a target abort during a read burst, then it provides all of the valid data on the initiator bus and disconnects.

Target aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge Specification.

MasterabortsforpostedandnonpostedtransactionsarereportedasspecifiedinthePCI-to-PCIBridgeSpecification.

If a transaction is attempted on the primary bus after a secondary reset is asserted, then the PCI2050 follows bit 5

(master abort mode) in the bridge control register (offset 3Eh, see Section 4.32) for reporting errors.

3.11 Discard Timer

The PCI2050 is free to discard the data or status of a delayed transaction that was completed with a delayed

10

15

transaction termination when a bus master has not repeated the request within 2 or 2 PCI clocks (approximately

3–7

15

30 µs and 993 µs, respectively). PCI Local Bus Specification recommends that a bridge wait 2 PCI clocks before

discarding the transaction data or status.

The PCI2050 implements a discard timer for use in delayed transactions. After a delayed transaction is completed

on the destination bus, the bridge may discard it under two conditions. The first condition occurs when a read

transaction is made to a region of memory that is inside a defined prefetchable memory region, or when the command

is a memory read line or a memory read multiple, implying that the memory region is prefetchable. The othercondition

occurs when the master originating the transaction (either a read or a write, prefetchable or nonprefetchable) has not

10

15

retried the transaction within 2 or 2 clocks. The number of clocks is tracked by a timer referred to as the discard

timer. When the discard timer expires, the bridge is required to discard the data. The PCI2050 default value for the

15

10

discard timer is 2 clocks; however, this value can be set to 2 clocks by setting bit 9 in the bridge control register

(offset 3Eh, see Section 4.32). For more information on the discard timer, see error conditions in PCI Local Bus

Specification.

3.12 Delayed Transactions

ThebridgesupportsdelayedtransactionsasdefinedinPCILocalBusSpecification. Atargetmustbeabletocomplete

the initial data phase in 16 PCI clocks or less from the assertion of the cycle frame (FRAME), and subsequent data

phases must complete in eight PCI clocks or less. A delayed transaction consists of three phases:

•

An initiator device issues a request.

The target completes the request on the destination bus and signals the completion to the initiator.

The initiator completes the request on the originating bus.

If the bridge is the target of a PCI transaction and it must access a slow device to write or read the requested data,

and the transaction takes longer than 16 clocks, then the bridge must latch the address, the command, and the byte

enables, and then issue a retry to the initiator. The initiator must end the transaction without any transfer of data and

is required to retry the transaction later using the same address, command, and byte enables. This is the first phase

of the delayed transaction.

During the second phase, if the transaction is a read cycle, the bridge fetches the requested data on the destination

bus, stores it internally, and obtains the completion status, thus completing the transaction on the destination bus.

If it is a write transaction, then the bridge writes the data and obtains the completion status, thus completing the

transaction on the destination bus. The bridge stores the completion status until the master on the initiating bus retries

the initial request.

During the third phase, the initiator rearbitrates for the bus. When the bridge sees the initiator retry the transaction,

it compares the second request to the first request. If the address, command, and byte enables match the values

latched in the first request, then the completion status (and data if the request was a read) is transferred to the initiator.

At this point, the delayed transaction is complete. If the second request from the initiator does not match the first

request exactly, then the bridge issues another retry to the initiator.

The PCI supports up to three delayed transactions in each direction at any given time.

3.13 Mode Selection

Table 3–3 shows the mode selection via MS0 (PDV terminal 155, GHK terminal E17) and MS1 (PDV terminal 106,

GHK terminal R17).

3–8

Table 3–3. Configuration Via MS0 and MS1

MS1

MODE

Compact PCI hot-swap friendly

PCI Bus Power Management Interface Specification Revision 1.1

HSSWITCH/GPIO(3) functions as HSSWITCH

MS0

0

1

0

1

Compact PCI hot-swap disabled

PCI Bus Power Management Interface Specification Revision 1.1

HSSWITCH/GPIO(3) functions as GPIO(3)

X

Intel compatible

No CPCI hot swap,

PCI Bus Power Management Interface Specification Revision 1.0

3.14 Compact PCI Hot-Swap Support

The PCI2050 is hot-swap friendly silicon that supports all of the hot-swap capable features, contains support for

software control, and integrates circuitry required by the CPCI Hot-Swap Specification. To be hot-swap capable, the

PCI2050 supports the following:

•

Compliance with PCI Local Bus Specification

Tolerance of V from early power

CC

Asynchronous reset

Tolerance of precharge voltage

I/O buffers must meet modified V/I requirements

Limited I/O pin voltage at precharge voltage

Hot-swap control and status programming via extended PCI capabilities linked list

Hot-swap terminals: HS_ENUM, HS_SWITCH, and HS_LED

CPCI hot-swap defines a process for installing and removing PCI boards without adversely affecting a running

system. The PCI2050 provides this functionality such that it can be implemented on a board that can be removed

and inserted in a hot-swap system.

The PCI2050 provides three terminals to support hot-swap when configured to be in hot-swap mode: HS_ENUM

(output), HS_SWITCH (input), and HS_LED (output). The HS_ENUM output indicates to the system that an insertion

event occurred or that a removal event is about to occur. The HS_SWITCH input indicates the state of a board ejector

handle, and the HS_LED output lights a blue LED to signal insertion and removal ready status.

3–9

3.15 JTAG Support

The PCI2050 implements a JTAG test port based on the IEEE Standard 1149.1, IEEE Standard Test Access Port and

Boundary-Scan Architecture. The JTAG test port consists of the following:

•

A 5-wire test access port

A test access port controller

An instruction register

A bypass register

A boundary-scan register

3.15.1 Test Port Instructions

The PCI 2050 supports the following JTAG instructions:

•

EXTEST, BYPASS, and SAMPLE

HIGHZ and CLAMP

Private (various private instructions used by TI for test purposes)

Table 3–4. JTAG Instructions and Op Codes

INSTRUCTION

EXTEST

SAMPLE

CLAMP

OP CODE

00000

00001

00100

00101

11111

DESCRIPTION

External test: drives terminals from the boundary scan register

Sample I/O terminals

Drives terminals from the boundary scan register and selects the bypass register for shifts

Puts all outputs and I/O terminals except for the TDO terminal in a high–impedance state

Selects the bypass register for shifts

HIGHZ

BYPASS

Table 3–5. Boundary Scan Terminal Order

BOUNDARY SCAN

REGISTER NO.

PDV TERMINAL

NUMBER

GHK TERMINAL

NUMBER

GROUP DISABLE

REGISTER

BOUNDARY-SCAN

CELL TYPE

TERMINAL NAME

0

1

137

138

140

141

143

144

146

147

149

150

152

153

154

155

158

161

162

164

165

–

J15

H19

H17

H14

G19

G18

G14

F19

G15

F17

F14

E18

F15

E17

C15

B15

A15

B14

E13

–

S_AD0

S_AD1

S_AD2

S_AD3

S_AD4

S_AD5

S_AD6

S_AD7

S_C/BE0

S_AD8

S_AD9

S_M66ENA

S_AD10

MS0

19

–

Bidirectional

Input

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

S_AD11

S_AD12

S_AD13

S_AD14

S_AD15

–

19

–

Bidirectional

Control

3–10

Table 3–5. Boundary Scan Terminal Order (continued)

BOUNDARY SCAN

REGISTER NO.

PDV TERMINAL

GHK TERMINAL

NUMBER

GROUP DISABLE

BOUNDARY-SCAN

CELL TYPE

TERMINAL NAME

NUMBER

167

168

169

171

172

173

–

REGISTER

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

F12

C13

B13

E13

C12

B12

–

S_C/BE1

S_PAR

19

–

Bidirectional

Input

S_SERR

S_PERR

S_LOCK

S_STOP

–

26

–

Bidirectional

Control

175

176

177

179

180

182

183

185

186

188

189

191

192

194

195

197

198

200

201

203

204

–

A11

B11

C11

F11

A10

C10

E10

A9

S_DEVSEL

S_TRDY

S_IRDY

S_FRAME

S_C/BE2

S_AD16

S_AD17

S_AD18

S_AD19

S_AD20

S_AD21

S_AD22

S_AD23

S_C/BE3

S_AD24

S_AD25

S_AD26

S_AD27

S_AD28

S_AD29

S_AD30

–

26

48

–

Bidirectional

Control

B9

F9

E9

B8

C8

E8

A7

C7

F7

B6

E7

A5

F6

–

206

207

2

E6

S_AD31

S_REQ0

S_REQ1

S_REQ2

S_REQ3

S_REQ4

S_REQ5

S_REQ6

S_REQ7

S_REQ8

48

–

Bidirectional

Input

C5

E3

–

Input

3

F5

–

Input

4

G6

E2

–

Input

5

–

Input

6

E1

–

Input

7

F3

–

Input

8

F2

–

Input

9

G5

–

Input

3–11

Table 3–5. Boundary Scan Terminal Order (continued)

BOUNDARY SCAN

REGISTER NO.

PDV TERMINAL

GHK TERMINAL

NUMBER

GROUP DISABLE

BOUNDARY-SCAN

CELL TYPE

TERMINAL NAME

NUMBER

10

11

REGISTER

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

F1

H6

–

S_GNT0

S_GNT1

–

61

–

Output

–

Control

Output

13

14

15

16

17

18

19

21

22

23

24

25

27

28

29

30

–

G2

G1

H5

H3

H2

H1

J1

S_GNT2

S_GNT3

S_GNT4

S_GNT5

S_GNT6

S_GNT7

S_GNT8

S_CLK

61

–

Output

J3

Input

J5

S_RST

78

–

Output

J6

S_CFN

Input

K1

K2

K5

K6

L1

L2

–

GPIO3

78

–

Bidirectional

Output

GPIO2

GPIO1

GPIO0

S_CLKOUT0

S_CLKOUT1

–

Output

–

Output

32

33

35

36

38

39

41

42

43

44

45

46

47

–

L6

L5

M2

M3

M5

N1

N3

N6

P1

P2

N5

P3

R1

–

S_CLKOUT2

S_CLKOUT3

S_CLKOUT4

S_CLKOUT5

S_CLKOUT6

S_CLKOUT7

S_CLKOUT8

S_CLKOUT9

P_RST

–

Output

–

Output

–

Output

–

Output

–

Output

–

Output

–

Output

–

Output

–

Input

BPCCE

–

Input

P_CLK

–

Input

P_GNT

–

Input

P_REQ

92

–

Output

–

Control

Bidirectional

49

50

55

57

58

R2

P5

R6

V5

W5

P_AD31

P_AD30

P_AD29

P_AD28

P_AD27

111

3–12

Table 3–5. Boundary Scan Terminal Order (continued)

BOUNDARY SCAN

REGISTER NO.

PDV TERMINAL

GHK TERMINAL

NUMBER

GROUP DISABLE

BOUNDARY-SCAN

CELL TYPE

TERMINAL NAME

NUMBER

REGISTER

111

–

98

60

V6

R7

P_AD26

P_AD25

P_AD24

P_C/BE3

P_IDSEL

P_AD23

P_AD22

P_AD21

P_AD20

P_AD19

P_AD18

P_AD17

P_AD16

–

Bidirectional

Input

99

61

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

63

W6

U7

64

65

V7

67

R8

111

–

Bidirectional

Control

68

U8

70

W8

W9

U9

71

73

74

R9

76

W10

V10

–

77

–

79

R10

P10

V11

U11

P11

R11

–

P_C/BE2

P_FRAME

P_IRDY

P_TRDY

P_DEVSEL

P_STOP

–

111

118

–

Bidirectional

Control

80

82

83

84

85

–

87

V12

U12

P12

R12

V13

U13

W14

V14

U14

W15

V15

R17

P15

R18

R19

P18

N15

M14

N17

N19

P_LOCK

P_PERR

P_SERR

P_PAR

118

142

–

Input

88

Bidirectional

Output

89

90

Bidirectional

Input

92

P_C/BE1

P_AD15

P_AD14

P_AD13

P_AD12

P_AD11

P_AD10

MS1

93

95

96

98

99

101

106

107

109

110

112

113

115

116

118

P_AD9

142

Bidirectional

P_AD8

P_C/BE0

P_AD7

P_AD6

P_AD5

P_AD4

P_AD3

3–13

Table 3–5. Boundary Scan Terminal Order (continued)

BOUNDARY SCAN

REGISTER NO.

PDV TERMINAL

GHK TERMINAL

NUMBER

GROUP DISABLE

BOUNDARY-SCAN

CELL TYPE

TERMINAL NAME

NUMBER

119

121

122

–

REGISTER

139

140

141

142

143

144

145

146

M15

M18

M19

–

P_AD2

P_AD1

P_AD0

–

142

–

Bidirectional

–

126

–

L15

–

MSK_IN

–

Input

–

Control

Output

127

128

L14

K19

HS_ENUM

HS_LED

144

Output

3.16 GPIO Interface

The PCI2050 implements a four-terminal general-purpose I/O interface. Besides functioning as a general-purpose

I/O interface, the GPIO terminals can be used to read in the secondary clock mask and to stop the bridge from

accepting I/O and memory transactions.

3.16.1 Secondary Clock Mask

The PCI2050 uses GPIO0, GPIO2, and MSK_IN to shift in the secondary clock mask from an external shift register.

MSK_IN

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GPIO2

GPIO0

P_RST

S_RST

Figure 3–6. Clock Mask Read Timing After Reset

Table 3–6. Clock Mask Data Format

BIT

[0:1]

[2:3]

[4:5]

[6:7]

8

CLOCK

S_CLKOUT0

S_CLKOUT1

S_CLKOUT2

S_CLKOUT3

S_CLKOUT4

S_CLKOUT5

S_CLKOUT6

S_CLKOUT7

S_CLKOUT8

S_CLKOUT9 (PCI2050 S_CLK input)

Reserved

9

10

11

12

13

[14:15]

3–14

3.16.2 Transaction Forwarding Control

The PCI 2050 will stop forwarding I/O and memory transactions if bit 5 of the chip control register (offset 40h, see

Section 5.1) is set to 1 and GPIO3 is driven high. The bridge will complete all queued posted writes and delayed

requests, but delayed completions will not be returned until GPIO3 is driven low and transaction forwarding is

resumed. The bridge will continue to accept configuration cycles in this mode. This feature is not available when in

compact PCI hot-swap mode because GPIO3 iis used as the HS_SWITCH input in this mode.

3.17 PCI Power Management

The PCI Power Management Specification establishes the infrastructure required to let the operating system control

the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power

of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software visible power

management states, which result in varying levels of power savings.

The four power management states of PCI functions are D0 — fully on state, D1 and D2 — intermediate states, and

D3 — off state. Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from

the device power state of the originating PCI2050 device.

For the operating system to manage the device power states on the PCI bus, the PCI function supports four power

management operations:

•

Capabilities reporting

Power status reporting

Setting the power state

System wake-up

The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The

presence of the new capabilities list is indicated by a bit in the status register (offset 06h, see Section 4.4) which

provides access to the capabilities list.

3.17.1 Behavior in Low Power States

The PCI2050 supports D0, D1, D2, and D3

power states when in TI mode. The PCI2050 only supports D0 and

hot

D3 power states when in Intel mode. The PCI2050 is fully functional only in D0 state. In the lower power states, the

bridge does not accept any memory or I/O transactions. These transactions are aborted by the master. The bridge

accepts type 0 configuration cycles in all power states except D3

cycles but does not pass these cycles to the secondary bus in any of the lower power states. Type 1 configuration

. The bridge also accepts type 1 configuration

cold

writes are discarded and reads return all 1s. All error reporting is done in the low power states. When in D2 and D3

states, the bridge turns off all secondary clocks for further power savings.

hot

When going from D3

to D0, an internal reset is generated. This reset initializes all PCI configuration registers to

hot

their default values. All TI specific registers (40h – FFh) are not reset. Power management registers are also not reset.

3–15

3–16

4 Bridge Configuration Header

The PCI2050 bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI

Bridge Architecture Specification 1.0. Table 4–1 shows the PCI configuration header, which includes the predefined

portion of the bridge’s configuration space. The PCI configuration offset is shown in the right column under the

OFFSET heading.

Table 4–1. Bridge Configuration Header

REGISTER NAME

OFFSET

00h

Device ID

Status

Vendor ID

Command

04h

Class code

Header type

Revision ID

08h

BIST

Primary latency timer

Cache line size

0Ch

10h

Base address 0

Base address 1

14h

Secondary bus latency timer

Subordinate bus number

Secondary bus number

I/O limit

Primary bus number

I/O base

18h

Secondary status

1Ch

20h

Memory limit

Memory base

Prefetchable memory limit

Prefetchable memory base

24h

Prefetchable base upper 32 bits

Prefetchable limit upper 32 bits

28h

2Ch

30h

I/O limit upper 16 bits

I/O base upper 16 bits

Reserved

Expansion ROM base address

Interrupt pin

Capability pointer

34h

38h

Bridge control

Arbiter control

Interrupt line

Chip control

3Ch

40h

Extended diagnostic

Reserved

44h

48h

4Ch

50h

54h

58h

Reserved

5Ch

60h

Reserved

GPIO input data

Reserved

GPIO output enable

P_SERR status

GPIO output data

P_SERR event disable

64h

Secondary clock control

68h

Reserved

6Ch–D8h

DCh

E0h

E4h

E8h–FFh

Power management capabilities

PM next item pointer

PM capability ID

Data

PMCSR bridge support

Hot swap control status

Power management control/status

Reserved

HS next item pointer

HS capability ID

Reserved

4–1

4.1 Vendor ID Register

This 16-bit value is allocated by the PCI Special Interest Group (SIG) and identifies TI as the manufacturer of this

device. The vendor ID assigned to TI is 104Ch.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Vendor ID

R

0

R

0

R

0

R

1

R

0

R

0

R

0

R

0

R

0

R

1

R

0

R

0

R

1

R

1

R

0

R

0

Register:

Type:

Offset:

Default:

Vendor ID

Read-only

00h

104Ch

4.2 Device ID Register

This 16-bit value is allocated by the vendor and identifies the PCI device. The device ID for the PCI2050 is AC23h.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Device ID

R

1

R

0

R

1

R

0

R

1

R

1

R

0

R

0

R

0

R

0

R

1

R

0

R

0

R

0

R

1

R

1

Register:

Type:

Offset:

Default:

Device ID

Read-only

02h

AC23h

4–2

4.3 Command Register

The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is

enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification. Table 4–2

describes the bit functions in the command register.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Command

R

0

R

0

R

0

R

0

R

0

R

0

R/W

0

R/W

0

R

0

R/W

0

R/W

0

R

0

R

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Command

Read-only, read/write (see individual bit descriptions)

Offset:

Default:

04h

0000h

Table 4–2. Command Register

BIT

TYPE

FUNCTION

15–10

R

Reserved

Fast back-to-back enable. The bridge does not generate fast back-to-back transactions on the primary PCI bus. Bit 9 is

read/write, but does not affect the bridge when set. This bit defaults to 0.

9

8

7

6

R/W

System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the primary interface.

0 = Disable SERR driver on primary interface (default)

R/W

R

1 = Enable the SERR driver on primary interface

Wait cycle control. Bit 7 controls address/data stepping by the bridge on both interfaces. The bridge does not support

address/data stepping and this bit is hardwired to 0.

Parity error response enable. Bit 6 controls the bridge response to parity errors.

0 = Parity error response disabled (default)

R/W

1 = Parity error response enabled

VGA palette snoop enable. When set, the bridge passes I/O writes on the primary PCI bus with addresses 3C6h, 3C8h,

and 3C9h inclusive of ISA aliases (i.e., only bits AD9–AD0 are included in the decode).

5

4

3

R/W

R

Memory write and invalidate enable. In a PCI-to-PCI bridge, bit 4 must be read-only and return 0 when read.

Special cycle enable. A PCI-to-PCI bridge cannot respond as a target to special cycle transactions, so bit 3 is defined as

read-only and must return 0 when read.

R

Bus master enable. Bit 2 controls the ability of the bridge to initiate a cycle on the primary PCI bus. When bit 2 is 0, the bridge

does not respond to any memory or I/O transactions on the secondary interface since they cannot be forwarded to the

primary PCI bus.

2

R/W

0 = Bus master capability disabled (default)

1 = Bus master capability enabled

Memory space enable. Bit 1 controls the bridge response to memory accesses for both prefetchable and nonprefetchable

memory spaces on the primary PCI bus. Only when bit 1 is set will the bridge forward memory accesses to the secondary

bus from a primary bus initiator.

1

0

R/W

0 = Memory space disabled (default)

1 = Memory space enabled

I/O space enable. Bit 0 controls the bridge response to I/O accesses on the primary interface. Only when bit 0 is set will

the bridge forward I/O accesses to the secondary bus from a primary bus initiator.

0 = I/O space disabled (default)

1 = I/O space enabled

4–3

4.4 Status Register

The status register provides device information to the host system. Bits in this register are cleared by writing a 1 to

the respective bit; writing a 0 to a bit location has no effect. Table 4–3 describes the status register.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Status

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

1

R/W

0

R

0

R

0

R

0

R

1

R

0

R

0

R

0

R

0

Register:

Type:

Status

Read-only, read/write (see individual bit descriptions)

Offset:

Default:

06h

0210h

Table 4–3. Status Register

BIT

TYPE

FUNCTION

15

R/W

Detected parity error. Bit 15 is set when a parity error is detected.

Signaled system error (SERR). Bit 14 is set if SERR is enabled in the command register (offset 04h, see Section 4.3) and

the bridge signals a system error (SERR). See Section 3.8, System Error Handling.

0 = No SERR signaled (default)

14

13

12

R/W

1 = Signals SERR

Received master abort. Bit 13 is set when a cycle initiated by the bridge on the primary bus has been terminated by a master

abort.

R/W

0 = No master abort received (default)

1 = Master abort received

Received target abort. Bit 12 is set when a cycle initiated by the bridge on the primary bus has been terminated by a target

abort.

0 = No target abort received (default)

1 = Target abort received

Signaled target abort. Bit 11 is set by the bridge when it terminates a transaction on the primary bus with a target abort.

0 = No target abort signaled by the bridge (default)

11

R/W

R

1 = Target abort signaled by the bridge

DEVSEL timing. These read-only bits encode the timing of P_DEVSEL and are hardwired 01b, indicating that the bridge

asserts this signal at a medium speed.

10–9

Data parity error detected. Bit 8 is encoded as:

0 = The conditions for setting this bit have not been met. No parity error detected. (default)

1 = A data parity error occurred and the following conditions were met:

a. P_PERR was asserted by any PCI device including the bridge.

8

R/W

b. The bridge was the bus master during the data parity error.

c. The parity error response bit (bit 6) is set in the command register (offset 04h, see Section 4.3).

Fast back-to-back capable. The bridge does not support fast back-to-back transactions as a target; therefore, bit 7 is

hardwired to 0.

7

R

User-definable feature (UDF) support. The PCI2050 does not support the user-definable features; therefore, bit 6 is

hardwired to 0.

6

5

R

66-MHz capable. The PCI2050 operates at a maximum P_CLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0.

Capabilities list. Bit 4 is read-only and is hardwired to 1, indicating that capabilities additional to standard PCI are

implemented. The linked list of PCI power management capabilities is implemented by this function.

4

3–0

Reserved. Bits 3–0 return 0s when read.

4–4

4.5 Revision ID Register

The revision ID register indicates the silicon revision of the PCI2050.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Revision ID

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Register:

Type:

Offset:

Default:

Revision ID

Read-only

08h

00h (reflects the current revision of the silicon)

4.6 Class Code Register

This register categorizes the PCI2050 as a PCI-to-PCI bridge device (0604h) with a 00h programming interface.

Bit

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Name

Class code

Base class

Sub class

Programming interface

Type

R

0

R

0

R

0

R

0

R

0

R

1

R

1

R

0

R

0

R

0

R

0

R

0

R

0

R

1

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Default

Register:

Type:

Offset:

Default:

Class code

Read-only

09h

060400h

4.7 Cache Line Size Register

The cache line size register is programmed by host software to indicate the system cache line size needed by the

bridge on memory read line and memory read multiple transactions.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Cache line size

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

Cache line size

Read/write

0Ch

00h

4–5

4.8 Primary Latency Timer Register

The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is

aprimaryPCIbusinitiatorandassertsP_FRAME, thelatencytimerbeginscountingfrom0. Ifthelatencytimerexpires

before the bridge transaction has terminated, then the bridge terminates the transaction when its P_GNT is

deasserted.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Latency timer

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

Latency timer

Read/write

0Dh

00h

4.9 Header Type Register

The header type register is read-only and returns 01h when read, indicating that the PCI2050 configuration space

adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes 10h–3Fh of configuration space is

considered.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Header type

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

1

Register:

Type:

Offset:

Default:

Header type

Read-only

0Eh

01h

4.10 BIST Register

The PCI2050 does not support built-in self test (BIST). The BIST register is read-only and returns the value 00h when

read.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

BIST

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Register:

Type:

Offset:

Default:

BIST

Read-only

0Fh

00h

4–6

4.11 Base Address Register 0

The bridge requires no additional resources. Base address register 0 is read-only and returns 0s when read.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Default

Bit

Base address register 0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

9

R

0

8

R

0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

15

14

13

12

11

10

Name

Type

Default

Base address register 0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Register:

Type:

Base address register 0

Read-only

Offset:

Default:

10h

0000 0000h

4.12 Base Address Register 1

The bridge requires no additional resources. Base address register 1 is read-only and returns 0s when read.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Default

Bit

Base address register 1

R

0

R

0

R

0

R

0

R

0

R

0

R

0

9

R

0

8

R

0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

15

14

13

12

11

10

Name

Type

Default

Base address register 1

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Register:

Type:

Base address register 1

Read-only

Offset:

Default:

14h

0000 0000h

4.13 Primary Bus Number Register

The primary bus number register indicates the primary bus number to which the bridge is connected. The bridge uses

this register, in conjunction with the secondary bus number and subordinate bus number registers, to determine when

to forward PCI configuration cycles to the secondary buses.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Primary bus number

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

Primary bus number

Read/write

18h

00h

4–7

4.14 Secondary Bus Number Register

The secondary bus number register indicates the secondary bus number to which the bridge is connected. The

PCI2050 uses this register, in conjunction with the primary bus number and subordinate bus number registers, to

determine when to forward PCI configuration cycles to the secondary buses. Configuration cycles directed to the

secondary bus are converted to type 0 configuration cycles.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Secondary bus number

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

Secondary bus number

Read/write

19h

00h

4.15 Subordinate Bus Number Register

The subordinate bus number register indicates the bus number of the highest numbered bus beyond the primary bus

existingbehindthebridge. ThePCI2050usesthisregister, inconjunctionwiththeprimarybusnumberandsecondary

bus number registers, to determine when to forward PCI configuration cycles to the subordinate buses. Configuration

cycles directed to a subordinate bus (not the secondary bus) remain type 1 cycles as the cycle crosses the bridge.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Subordinate bus number

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

Subordinate bus number

Read/write

1Ah

00h

4.16 Secondary Bus Latency Timer Register

ThesecondarybuslatencytimerspecifiesthelatencytimerforthebridgeinunitsofPCIclockcycles. Whenthebridge

is a secondary PCI bus initiator and asserts S_FRAME, the latency timer begins counting from 0. If the latency timer

expires before the bridge transaction has terminated, then the bridge terminates the transaction when its S_GNT is

deasserted. The PCI-to-PCI bridge S_GNT is an internal signal and is removed when another secondary bus master

arbitrates for the bus.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Secondary bus latency timer

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

Secondary bus latency timer

Read/write

1Bh

00h

4–8

4.17 I/O Base Register

The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O

addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable and correspond to

address bits AD15–AD12. The lower 12 address bits of the I/O base address are considered 0. Thus, the bottom of

the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O base

address corresponds to the contents of the I/O base upper 16 bits register (offset 30h, see Section 4.26).

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

I/O base

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

0

R

0

R

1

Register:

Type:

I/O base

Read-only, read/write

Offset:

Default:

1Ch

01h

4.18 I/O Limit Register

The I/O limit register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O

addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable and correspond to

address bits AD15–AD12. The lower 12 address bits of the I/O limit address are considered FFFh. Thus, the top of

the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O limit

address corresponds to the contents of the I/O limit upper 16 bits register (offset 32h, see Section 4.27).

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

I/O limit

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

0

R

0

R

1

Register:

Type:

I/O limit

Read-only, read/write

Offset:

Default:

1Dh

01h

4–9

4.19 Secondary Status Register

The secondary status register is similar in function to the status register (offset 06h, see Section 4.4); however, its

bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a 1 to the respective

bit.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Secondary status

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

1

R/W

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Register:

Type:

Secondary status

Read-only, read/write (see individual bit descriptions)

Offset:

Default:

1Eh

0200h

Table 4–4. Secondary Status Register

BIT

TYPE

FUNCTION

Detected parity error. Bit 15 is set when a parity error is detected on the secondary interface.

0 = No parity error detected on the secondary bus (default)

15

R/W

1 = Parity error detected on the secondary bus

Received system error. Bit 14 is set when the secondary interface detects S_SERR asserted. Note that the bridge never

asserts S_SERR.

14

13

12

R/W

0 = No S_SERR detected on the secondary bus (default)

1 = S_SERR detected on the secondary bus

Received master abort. Bit 13 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a

master abort.

R/W

0 = No master abort received (default)

1 = Bridge master aborted the cycle

Receivedtargetabort. Bit12issetwhenacycleinitiatedbythebridgeonthesecondarybushasbeenterminatedbyatarget

abort.

0 = No target abort received (default)

1 = Bridge received a target abort

Signaled target abort. Bit 11 is set by the bridge when it terminates a transaction on the secondary bus with a target abort.

0 = No target abort signaled (default)

11

R/W

R

1 = Bridge signaled a target abort

DEVSEL timing. These read-only bits encode the timing of S_DEVSEL and are hardwired to 01b, indicating that the bridge

asserts this signal at a medium speed.

10–9

Data parity error detected.

0 = The conditions for setting this bit have not been met

1 = A data parity error occurred and the following conditions were met:

a. S_PERR was asserted by any PCI device including the bridge.

b. The bridge was the bus master during the data parity error.

c. The parity error response bit (bit 1) is set in the bridge control register (offset 3Eh, see Section 4.32).

8

R/W

7

6

R

Fast back-to-back capable. Bit 7 is hardwired to 0.

User-definable feature (UDF) support. Bit 6 is hardwired to 0.

66 MHz capable. Bit 5 is hardwired to 0.

5

4–0

Reserved. Bits 4–0 return 0s when read.

4–10

4.20 Memory Base Register

The memory base register defines the base address of a memory-mapped I/O address range used by the bridge to

determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register

are read/write and correspond to the address bits AD31–AD20. The lower 20 address bits are considered 0s; thus,

the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Memory base

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

0

R

0

R

0

Register:

Type:

Memory base

Read-only, read/write

Offset:

Default:

20h

0000h

4.21 Memory Limit Register

The memory limit register defines the upper-limit address of a memory-mapped I/O address range used to determine

when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write

and correspond to the address bits AD31–AD20. The lower 20 address bits are considered 1s; thus, the address

range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Memory limit

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

0

R

0

R

0

Register:

Type:

Memory limit

Read-only, read/write

Offset:

Default:

22h

0000h

4.22 Prefetchable Memory Base Register

The prefetchable memory base register defines the base address of a prefetchable memory address range used by

the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of

this register are read/write and correspond to the address bits AD31–AD20. The lower 20 address bits are considered

0; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s

when read.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Prefetchable memory base

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

0

R

0

R

0

Register:

Type:

Prefetchable memory base

Read-only, read/write

Offset:

Default:

24h

0000h

4–11

4.23 Prefetchable Memory Limit Register

The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used

to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register

are read/write and correspond to the address bits AD31–AD20. The lower 20 address bits are considered 1s; thus,

the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Prefetchable memory limit

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

0

R

0

R

0

Register:

Type:

Prefetchable memory limit

Read-only, read/write

Offset:

Default:

26h

0000h

4.24 Prefetchable Base Upper 32 Bits Register

The prefetchable base upper 32 bits register plus the prefetchable memory base register defines the base address

of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory

transactions from one interface to the other. The prefetchable base upper 32 bits register should be programmed to

all zeros when 32-bit addressing is being used.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Default

Bit

Prefetchable base upper 32 bits

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Prefetchable base upper 32 bits

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

Prefetchable base upper 32 bits

Read/Write

28h

0000 0000h

4–12

4.25 Prefetchable Limit Upper 32 Bits Register

The prefetchable LIMIT upper 32 bits register plus the prefetchable memory LIMIT register defines the base address

of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory

transactions from one interface to the other. The prefetchable LIMIT upper 32 bits register should be programmed

to all zeros when 32-bit addressing is being used.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Default

Bit

Prefetchable limit upper 32 bits

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Prefetchable limit upper 32 bits

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

Prefetchable limit upper 32 bits

Read/Write

2Ch

0000 0000h

4.26 I/O Base Upper 16 Bits Register

The I/O base upper 16 bits register specifies the upper 16 bits corresponding to AD31–AD16 of the 32-bit address

that specifies the base of the I/O range to forward from the primary PCI bus to the secondary PCI bus.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

I/O base upper 16 bits

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

I/O base upper 16 bits

Read/Write

30h

0000h

4.27 I/O Limit Upper 16 Bits Register

The I/O limit upper 16-bits register specifies the upper 16 bits corresponding to AD31–AD16 of the 32-bit address

that specifies the upper limit of the I/O range to forward from the primary PCI bus to the secondary PCI bus.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

I/O limit upper 16 bits

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Offset:

Default:

I/O limit upper 16 bits

Read/Write

32h

0000h

4–13

4.28 Capability Pointer Register

ThecapabilitypointerregisterprovidesthepointertothePCIconfigurationheaderwherethePCIpowermanagement

register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The

capability pointer register is read-only and returns DCh when read, indicating the power management registers are

located at PCI header offset DCh.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Capability pointer register

R

1

R

1

R

0

R

1

R

1

R

1

R

0

R

0

Register:

Type:

Offset:

Default:

capability pointer

Read-only

34h

DCh

4.29 Expansion ROM Base Address Register

The PCI2050 does not implement the expansion ROM remapping feature. The expansion ROM base address

register returns all 0s when read.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Type

Default

Bit

Expansion ROM base address

R

0

R

0

R

0

R

0

R

0

R

0

R

0

9

R

0

8

R

0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

15

14

13

12

11

10

Name

Type

Default

Expansion ROM base address

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Register:

Type:

Offset:

Default:

Expansion ROM base address

Read-only

38h

0000 0000h

4.30 Interrupt Line Register

The interrupt line register is read/write and is used to communicate interrupt line routing information. Since the bridge

does not implement an interrupt signal terminal, this register defaults to FFh.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Interrupt line

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Register:

Type:

Offset:

Default:

Interrupt line

Read/write

3Ch

FFh

4–14

4.31 Interrupt Pin Register

The bridge default state does not implement any interrupt terminals. Reads from bits 7–0 of this register return 0s.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Interrupt pin

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Register:

Type:

Offset:

Default:

Interrupt pin

Read-only

3Dh

00h

4.32 Bridge Control Register

The bridge control register provides many of the same controls for the secondary interface that are provided by the

command register for the primary interface. Some bits affect the operation of both interfaces.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Bridge control

R

0

R

0

R

0

R

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R/W

0

R/W

0

R

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Bridge control

Read-only, read/write (see individual bit descriptions)

Offset:

Default:

3Eh

0000h

Table 4–5. Bridge Control Register

BIT

TYPE

FUNCTION

15–12

R

Reserved. Bits 15–12 return 0s when read.

Discard timer SERR enable.

11

10

R/W

0 = SERR signaling disabled for primary discard timeouts (default)

1 = SERR signaling enabled for primary discard timeouts

Discard timer status. Once set, this bit must be cleared by writing 1 to this bit.

0 = No discard timer error (default)

R/W

1 = Discard timer error. Either primary or secondary discard timer expired and a delayed transaction was discarded from

the queue in the bridge.

Secondary discard timer. Selects the number of PCI clocks that the bridge will wait for a master on the secondary interface

to repeat a delayed transaction request.

9

15

0 = Secondary discard timer counts 2 PCI clock cycles (default)

10

1 = Secondary discard timer counts 2 PCI clock cycles

Primary discard timer. Selects the number of PCI clocks that the bridge will wait for a master on the primary interface to

repeat a delayed transaction request.

8

7

6

R/W

R

15

0 = the primary discard timer counts 2 PCI clock cycles (default)

10

1 = the primary discard timer counts 2 PCI clock cycles

Fast back-to-back capable. The bridge never generates fast back-to-back transactions to different secondary devices. Bit

7 returns 0 when read.

Secondary bus reset. When bit 6 is set, the secondary reset signal (S_RST) is asserted. S_RST is deasserted by resetting

this bit. Bit 6 is encoded as:

R/W

0 = Do not force the assertion of S_RST (default).

1 = Force the assertion of S_RST.

4–15

Table 4–5. Bridge Control Register (continued)

BIT

TYPE

FUNCTION

Master abort mode. Bit 5 controls how the bridge responds to a master abort that occurs on either interface when the bridge

is the master. If this bit is set, the posted write transaction has completed on the requesting interface, and SERR enable

(bit 8) of the command register (offset 04h, see Section 4.3) is 1, then P_SERR is asserted when a master abort occurs.

If the transaction has not completed, then a target abort is signaled. If the bit is cleared, then all 1s are returned on reads

and write data is accepted and discarded when a transaction that crosses the bridge is terminated with master abort. The

default state of bit 5 after a reset is 0.

5

R/W

0 = Do not report master aborts (return FFFF FFFFh on reads and discard data on writes) (default).

1 = Report master aborts by signaling target abort if possible, or if SERR is enabled via bit 1 of this register, by

asserting SERR.

4

3

R

Reserved. Returns 0 when read. Writes have no effect.

VGA enable. When bit 3 is set, the bridge positively decodes and forwards VGA-compatible memory addresses in the video

frame buffer range 000A 0000h–000B FFFFh, I/O addresses in the range 03B0h–03BBh, and 03C0–03DFh from the

primary to the secondary interface, independent of the I/O and memory address ranges. When this bit is set, the bridge

blocks forwarding of these addresses from the secondary to the primary. Reset clears this bit. Bit 3 is encoded as:

0 = Do not forward VGA-compatible memory and I/O addresses from the primary to the secondary interface

(default).

R/W

1 = Forward VGA-compatible memory and I/O addresses from the primary to the secondary, independent of the I/O

and memory address ranges and independent of the ISA enable bit.

ISA enable. When bit 2 is set, the bridge blocks the forwarding of ISA I/O transactions from the primary to the secondary,

addressingthelast768bytesineach1K-byteblock. Thisappliesonlytotheaddresses(definedbytheI/Owindowregisters)

that are located in the first 64K bytes of PCI I/O address space. From the secondary to the primary, I/O transactions are

forwardediftheyaddressthelast768bytesineach1K-byteblockintheaddressrangespecifiedintheI/Owindowregisters.

Bit 2 is encoded as:

2

R/W

0 = Forward all I/O addresses in the address range defined by the I/O base and I/O limit registers (default).

1 = Block forwarding of ISA I/O addresses in the address range defined by the I/O base and I/O limit registers when

these I/O addresses are in the first 64K bytes of PCI I/O address space and address the top 768 bytes of each

1K-byte block.

SERR enable. Bit 1 controls the forwarding of secondary interface SERR assertions to the primary interface. Only when

this bit is set will the bridge forward S_SERR to the primary bus signal P_SERR. For the primary interface to assert SERR,

bit 8 of the command register (offset 04h, see Section 4.3) must be set.

0 = SERR disabled (default)

1

0

R/W

1 = SERR enabled

Parity error response enable. Bit 0 controls the bridge response to parity errors on the secondary interface. When this bit

is set, the bridge asserts S_PERR to report parity errors on the secondary interface.

0 = Ignore address and parity errors on the secondary interface (default).

1 = Enable parity error reporting and detection on the secondary interface.

4–16

5 Extension Registers

The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration

space (i.e., registers 40h–FFh in PCI configuration space in the PCI2050). These registers can be accessed through

configuration reads and writes. The TI extension registers add flexibility and performance benefits to the standard

PCI-to-PCI bridge.

5.1 Chip Control Register

The chip control register contains read/write and read-only bits has a default value of 00h. This register is used to

control the functionality of certain PCI transactions.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Chip control

R

0

R

0

R/W

0

R/W

0

R

0

R

0

R/W

0

R

0

Register:

Type:

Offset:

Default:

Chip control

Read/Write

40h

00h

Table 5–1. Chip Control Register

BIT

TYPE

FUNCTION

7–6

R

Reserved. Bits 7–5 return 0s when read.

Transaction forwarding control for I/O and memory cycles.

5

R/W

0 = Transaction forwarding controlled by bits 0 and 1 of the command register (offset 04h, see Section 4.3) (default).

1 = Transaction forwarding will be disabled if GPIO3 is driven high.

Memory read prefetch. When set, bit 4 enables the memory read prefetch.

0 = Upstream memory reads are disabled (default).

1 = Upstream memory reads are enabled

4

3–2

1

R/W

R

Reserved. Bits 3 and 2 return 0s when read.

Memory write and memory write and invalidate disconnect control.

0 = Disconnects on queue full or 4-KB boundaries (default)

R/W

R

1 = Disconnects on queue full, 4-KB boundaries and cacheline boundries.

0

Reserved. Bit 0 returns 0 when read.

5–1

5.2 Extended Diagnostic Register

The extended diagnostic register is read or write and has a default value of 00h. Bit 0 of this register is used to reset

both the PCI2050 and the secondary bus.

Bit

7

6

5

4

3

2

1

0

Name

Type

Default

Extended diagnostic

R

0

R

0

R

0

R

0

R

0

R

0

R

0

W

0

Register:

Type:

Extended diagnostic

Read-only, Write-only

Offset:

Default:

41h

00h

Table 5–2. Extended Diagnostic Register

BIT

TYPE

FUNCTION

7–1

R

Reserved. Bits 7–1 return 0s when read.

Writing a 1 to this bit causes the PCI2050 to set bit 6 of the bridge control register (offset 3Eh, see Section 4.32) and then

internally reset the PCI2050. Bit 6 of the bridge control register will not be reset by the internal reset. Bit 0 is self-clearing.

0

W

5–2

5.3 Arbiter Control Register

The arbiter control register is used for the bridge’s internal arbiter. The arbitration scheme used is a two-tier rotational

arbitration. The PCI2050 bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Type

Default

Arbiter control

R

0

R

0

R

0

R

0

R

0

R

0

R/W

1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register:

Type:

Arbiter control

Read-only, Read/Write

Offset:

Default:

42h

0200h

Table 5–3. Arbiter Control Register

BIT

TYPE

FUNCTION

15–10

R

Reserved. Bits 15–10 return 0s when read.

Bridge tier select. This bit determines in which tier the PCI2250 bridge is placed in the two-tier arbitration scheme.

9

8

7

6

5

4

3

2

1

R/W

0 = Lowest priority tier

1 = Highest priority tier (default)

GNT8 tier select. This bit determines in which tier the S_GNT8 is placed in the arbitration scheme. This bit is encoded as:

R/W