PCI4450 [TI]
PC Card and OHCI Controller; PC卡和OHCI控制器
| 型号： | PCI4450 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PC Card and OHCI Controller |
| 文件： | 总197页 (文件大小：1876K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
D
D
1997 PC Standard Compliant
PCI Bus Power Management Interface
Specification 1.1 Compliant
D
D
D
D
Dedicated Pin for PCI CLKRUN
Four General-Purpose Event Registers
Multifunction PCI Device with Separate
Configuration Space for each Socket
Five PCI Memory Windows and Two I/O
Windows Available to each PC Card16
Socket
Two I/O Windows and Two Memory
Windows Available to each CardBus
Socket
ExCA -Compatible Registers are Mapped
in Memory or I/O Space
Supports Distributed DMA and PC/PCI
DMA
Intel 82365SL-DF Register Compatible
Supports 16-bit DMA on Both PC Card
Sockets
Supports Ring Indicate, SUSPEND, and
PCI CLKRUN
Advanced Submicron, Low-Power CMOS
Technology
Provides VGA / Palette Memory and I/O,
and Subtractive Decoding Options
D
ACPI 1.0 Compliant
PCI Local Bus Specification Revision
2.1/2.2 Compliant
D
D
D
D
PC 98/99 Compliant
Compliant with the PCI Bus Interface
Specification for PCI-to-CardBus Bridges
D
Fully Compliant with the PCI Bus Power
Management Specification for PCI to
CardBus Bridges Specification
D
D
D
D
D
Ultra Zoomed Video
Zoomed Video Auto-Detect
D
Advanced filtering on Card Detect Lines
Provide 90 Microseconds of Noise
Immunity.
D
D
D
D
D
D
D
D
D
D
Programmable D3 Status Pin
Internal Ring Oscillator
3.3-V Core Logic with Universal PCI
Interfaces Compatible with 3.3-V and 5-V
PCI Signaling Environments
D
D
D
D
Mix-and-Match 5-V/3.3-V PC Card16 Cards
and 3.3-V CardBus Cards
LED Activity Pins
Supports PCI Bus Lock (LOCK)
Packaged in a 256-pin BGA or 257-pin
Micro-Star BGA
OHCI Link Function Designed to IEEE 1394
Open Host Controller Interface (OHCI)
Specification
Implements PCI Burst Transfers and Deep
FIFOs to Tolerate Large Host Latency
Supports Physical Write Posting of up to 3
Outstanding Transactions
OHCI Link Function is IEEE 1394-1995
Compliant and Compatible with
Proposal 1394a
Supports Two PC Card or CardBus Slots
With Hot Insertion and Removal
Uses Serial Interface to TI TPS2206 Dual
Power Switch
D
Supports 132 Mbyte/sec. Burst Transfers
to Maximize Data Throughput on Both the
PCI Bus and the CardBus Bus
D
D
D
D
Supports Serialized IRQ with PCI
Interrupts
D
8 Programmable Multifunction Pins
D
Interrupt Modes Supported: Serial
ISA/Serial PCI, Serial ISA/Parallel PCI,
Parallel PCI Only.
D
D
Supports Serial Bus Data Rates of 100,
200, and 400 Mbits/second
Provides Bus-Hold Buffers on the
PHY-Link I/F for Low-cost Single Capacitor
Isolation
D
D
Serial EEPROM Interface for Loading
Subsystem ID and Subsystem Vendor ID
Supports Zoomed Video with Internal
Buffering
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation.
PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA).
TI is a trademark of TexasInstrumentsIncorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
TerminalAssignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SerialEEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Signal Names and TerminalAssignments . . . . . . . . . . . . . . . . . . . 5 AbsoluteMaximumRatings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
PCI4450 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 RecommendedOperatingConditions . . . . . . . . . . . . . . . . . . . . . . . 186
TerminalFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ElectricalCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCI Clock/Reset TimingRequirements . . . . . . . . . . . . . . . . . . . . . 188
ClampingVoltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCI TimingRequirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Switrching Characteristics for PHY-LinkInterface . . . . . . . . . . . . . 188
PC Card Applications Overview . . . . . . . . . . . . . . . . . . . . . . . . . 28 ParameterMeasurementInformation . . . . . . . . . . . . . . . . . . . . . . . 189
ProgrammableInterruptSubsystem . . . . . . . . . . . . . . . . . . . . . . 35 PCIBusParameterMeasurementInformation . . . . . . . . . . . . . . . 190
PowerManagementOverview . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . 43 Timing Requirements, (Memory Cycles) . . . . . . . . . . . . . . . . . . . . 192
PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . 44 Timing Requirements, (I/O Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . 197
ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . . 82 SwitchingCharacteristics(Miscellaneous) . . . . . . . . . . . . . . . . . . 193
CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . 106 PCCardParameterMesasurementInformation . . . . . . . . . . . . . . 193
Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . 114 MechanicalData . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
description
The Texas Instruments PCI4450 is an integrated dual-socket PC Card controller and IEEE 1394 Open HCI host
controller. This high-performance integrated solution provides the latest in both PC Card and IEEE 1394
technology.
The PCI4450 is a three-function PCI device compliant with PCI Local Bus Specification 2.2. Functions 0 and
1 provide the independent PC Card socket controllers compliant with the 1997 PC Card Standard. The PCI4450
provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports
any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The
PCI4450 is register compatible with the Intel 82365SL–DF ExCA controller. The PCI4450 internal data path
logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance.
Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained
bursting. The PCI4450 can be programmed to accept posted writes to improve bus utilization.
Function 2 of the PCI4450 is compatible with IEEE1394A and the latest 1394 open host controller interface
(OHCI) specifications. The chip provides the IEEE1394 link function and is compatible with data rates of 100,
200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host
bus latencies. The PCI4450 provides physical write posting and a highly tuned physical data path for SBP-2
performance. Multiple cache line burst transfers, advanced internal arbitration, and bus holding buffers on the
PHY/Link interface are other features that make the PCI4450 the best-in-class 1394 Open HCI solution.
The PCI4450 provides an internally buffered zoomed video (ZV) path. This reduces the design effort of PC
board manufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loading
specifications.
Various implementation specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PC/PCI DMA, PCI LOCK and parallel
interrupts, PC Card activity indicator LEDs, and other platform specific signals. ACPI-complaint
general-purpose events may be programmed and controlled through the multifunction terminals, and an
ACPI-compliant programming interface is included for the general-purpose inputs and outputs.
The PCI4450 is compliant with the latest PCI Bus Power Management Specification, and provides several
low-power modes which enable the host power system to further reduce power consumption. The PC Card
(CardBus) Controller and IEEE 1394 Host Controller Device Class Specifications required for Microsoft
OnNowt Power Management are supported. Furthermore, an advanced complementary metal-oxide
semiconductor (CMOS) process achieves low system power consumption.
Unused PCI4450 inputs must be pulled to a valid logic level using a 43 kΩ resistor.
use of symbols in this document
Throughout this data sheet the overbar symbol denotes an active-low signal. For example: FRAME denotes
that this is an active-low signal.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal assignments
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
B
B
B
B
B
B
B
B
B
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
P
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Z
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Z
A
B
C
D
E
F
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Z
B
B
A
A
A
G
H
J
B
P
K
L
Bottom View
A
A
M
N
P
R
T
P
P
P
Z
Z
Z
Z
Z
P
P
P
P
P
P
P
P
T
T
T
S
S
S
S
S
Z
Z
Z
Z
U
V
W
Y
P
P
P
P
P
P
P
S
S
S
S
S
S
S
S
Z
Z
Z
Z
Z
S
S
Z
Z
Z
Z
Z
Z
P
A
B
Z
PCIInterface
PC Card A
VCC 3.3 Volt
Ground (GND)
PC Card B
T
TPS Power Switch
Miscellaneous
Zoom Video
1394PHY/Link
S
Figure 1. PCI4450 Pin Diagram
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
signal names and terminal assignments
Signal names and their terminal assignments are shown in Tables 1 and 2 and are sorted alphanumerically by
the assigned terminal.
Table 1. GFN Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI
GFN
SIGNAL NAME
GFN
SIGNAL NAME
B_RSVD//B_D2
GFN
SIGNAL NAME
A_CVS2//A_VS2
A1
GND
C9
G1
A2
A_CAD16//A_A17
A_CAD11//A_OE
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
B_CAD27//B_D0
B_CAUDIO//B_BVD2(SPKR)
B_CAD26//B_A0
B_CC/BE3//B_REG
B_CAD22//B_A4
B_CVS2//B_VS2
B_CAD17//B_A24
B_CTRDY//B_A22
B_CBLOCK//B_A19
B_RSVD//B_A18
B_CAD14//B_A9
A_CDEVSEL//A_A21
A_CBLOCK//A_A19
A_CPERR//A_A14
GND
G2
A_CAD19//A_A25
A_CAD18//A_A7
A_CFRAME//A_A23
B_CAD10//B_CE2
B_CAD8//B_D15
B_RSVD//B_D14
B_CAD5//B_D6
A_CAD21//A_A5
A_CRST//A_RESET
A_CAD20//A_A6
GND
A3
G3
A4
A_CC/BE0//A_CE1
A_RSVD//A_D14
G4
A5
G17
G18
G19
G20
H1
A6
A_CAD3//A_D5
A7
A_CAD1//A_D4
A8
A_CCD1//A_CD1
A9
B_CAD29//B_D1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B_CCLKRUN//B_WP(IOIS16)
B_CSTSCHG//B_BVD1(STSCHG/RI)
B_CINT//B_READY(IREQ)
B_CAD24//B_A2
H2
H3
H4
H17
H18
H19
H20
J1
GND
B_CAD23//B_A3
D2
B_CAD6//B_D13
B_CAD3//B_D5
B_CAD4//B_D12
A_CC/BE3//A_REG
A_CAD23//A_A3
A_CREQ//A_INPACK
A_CAD22//A_A4
B_CAD1//B_D4
B_CAD2//B_D11
B_CAD0//B_D3
B_CCD1//B_CD1
A_CAD26//A_A0
A_CAD24//A_A2
A_CAD25//A_A1
B_CAD21//B_A5
D3
B_CAD19//B_A25
B_CC/BE2//B_A12
B_CFRAME//B_A23
B_CGNT//B_WE
D4
D5
A_CAD13//A_IORD
D6
V
CC
J2
D7
A_CAD7//A_D7
J3
B_CSTOP//B_A20
A_RSVD//A_A18
D8
GND
J4
D9
B_CAD31//B_D10
B_CAD28//B_D8
J17
J18
J19
J20
K1
B2
A_CAD14//A_A9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
B3
A_CAD15//A_IOWR
A_CAD10//A_CE2
V
CC
B_CAD25//B_A1
B4
B5
V
CCA
GND
B6
A_CAD5//A_D6
A_CAD4//A_D12
A_CAD0//A_D3
B_CAD30//B_D9
B_CCD2//B_CD2
B_CSERR//B_WAIT
B_CVS1//B_VS1
B_CAD20//B_A6
K2
B7
V
CC
K3
B8
B_CIRDY//B_A15
K4
V
CC
PCLK
B9
GND
K17
K18
K19
K20
L1
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
B_CC/BE1//B_A8
B_CAD15//B_IOWR
B_CAD13//B_IORD
A_CIRDY//A_A15
A_CTRDY//A_A22
A_CCLK//A_A16
A_CSTOP//A_A20
B_CAD16//B_A17
B_CAD12//B_A11
CLKRUN
PRST
GNT
V
CCB
A_CVS1//A_VS1
A_CINT//A_READY(IREQ)
A_CSERR//A_WAIT
B_CREQ//B_INPACK
B_CRST//B_RESET
B_CAD18//B_A7
B_CCLK//B_A16
B_CDEVSEL//B_A21
B_CPERR//B_A14
B_CPAR//B_A13
A_CGNT//A_WE
A_CPAR//A_A13
A_CC/BE1//A_A8
A_CAD12//A_A11
A_CAD9//A_A10
A_CAD8//A_D15
A_CAD6//A_D13
A_CAD2//A_D11
E2
L2
E3
L3
E4
L4
V
V
CCA
E17
E18
E19
E20
F1
L17
L18
L19
L20
M1
M2
M3
M4
M17
M18
M19
M20
CC
AD31
V
CCB
AD30
B_CAD9//B_A10
A_CAD17//A_A24
A_CC/BE2//A_A12
REQ
A_CAUDIO//A_BVD2(SPKR)
C2
F2
A_CSTSCHG//A_BVD1(STSCHG/RI)
C3
F3
V
V
V
A_CCLKRUN//A_WP(IOIS16)
CCA
CC
C4
F4
A_CCD2//A_CD2
AD26
C5
F17
F18
F19
F20
CC
C6
B_CAD11//B_OE
B_CC/BE0//B_CE1
B_CAD7//B_D7
AD27
C7
AD28
C8
AD29
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
signal names and terminal assignments (continued)
Table 1. GFN Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI (Continued)
GFN
SIGNAL NAME
A_CAD27//A_D0
GFN
SIGNAL NAME
GFN
SIGNAL NAME
ZV_MCLK
N1
U7
PHY_CTL0
GND
W4
N2
A_CAD28//A_D8
A_CAD29//A_D1
GND
U8
W5
LPS
N3
U9
PHY_DATA6
W6
PHY_CTL1
PHY_DATA1
PHY_DATA4
MFUNC4
SCL
N4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V1
V
CC
W7
N17
N18
N19
N20
P1
GND
SUSPEND
CLOCK
GND
W8
C/BE3
W9
AD24
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
AD25
AD6
MFUNC0
LATCH
IRQSER
AD2
A_CAD30//A_D9
A_RSVD//A_D2
ZV_HREF
ZV_Y1
V
CC
AD12
P2
P3
GND
P4
TRDY
AD4
P17
P18
P19
P20
R1
AD20
DEVSEL
C/BE2
C/BE0
AD23
AD10
V
CCP
ZV_Y7
AD14
IDSEL/MFUNC7
A_CAD31//A_D10
ZV_VSYNC
V2
ZV_UV1
ZV_UV3
ZV_LRCLK
MFUNC5
PHY_CLK
PHY_DATA0
PHY_DATA3
PHY_DATA7
MFUNC3
SPKROUT
DATA
PAR
V3
PERR
R2
V4
ZV_UV5
ZV_UV7
ZV_PCLK
MFUNC6
PHY_LREQ
LINKON
PHY_DATA2
PHY_DATA5
SDA
R3
ZV_Y2
V5
Y2
R4
V
V
V6
Y3
CC
R17
R18
R19
R20
T1
V7
Y4
CC
AD19
V8
Y5
AD21
V9
Y6
AD22
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W1
W2
W3
Y7
ZV_Y0
ZV_Y3
ZV_Y5
ZV_UV0
IRDY
Y8
T2
Y9
T3
AD0
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
MFUNC2
MFUNC1
G_RST
RI_OUT
AD1
T4
V
CCP
AD7
T17
T18
T19
T20
U1
AD16
AD9
AD17
AD13
AD18
C/BE1
STOP
AD3
ZV_Y4
ZV_Y6
ZV_UV2
GND
AD5
U2
FRAME
ZV_UV4
ZV_UV6
ZV_SCLK
AD8
U3
AD11
U4
AD15
U5
ZV_SDATA
SERR
U6
V
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
signal names and terminal assignments (continued)
Table 2. GJG Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI
NO.
SIGNAL NAME
A_CC/BE1//A_A8
NO.
SIGNAL NAME
B_CAD24//B_A2
B_CAD23//B_A3
NO.
SIGNAL NAME
B_CC/BE0//B_CE1
A2
D12
D13
D14
D15
D16
D18
D19
E1
G16
G18
G19
H1
A3
GND
B_CAD8//B_D15
GND
A4
A_CAD12//A_A11
A_CAD10//A_CE2
A_CAD8//A_D15
A_CAD3//A_D5
V
CC
A5
B_CFRAME//B_A23
B_CBLOCK//B_A19
B_RSVD//B_A18
B_CC/BE1//B_A8
A_CAD20//A_A6
A_CRST//A_RESET
A_CAD21//A_A5
A_CAD22//A_A4
A_CVS2//A_VS2
B_CAD4//B_D12
B_RSVD//B_D14
B_CAD5//B_D6
B_CAD6//B_D13
B_CAD3//B_D5
A_CAD23//A_A3
A_CC/BE3//A_REG
A_CREQ//A_INPACK
A_CAD24//A_A2
A_CAD25//A_A1
A6
H2
A7
H4
A8
A_CAD0//A_D3
H5
A9
B_CAD29//B_D1
B_CSTSCHG//B_BVD1(STSCHG/RI)
V
CC
H6
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
E2
A_CCLK//A_A16
A_CGNT//A_WE
A_CDEVSEL//A_A21
H14
H15
H16
H18
H19
J1
V
CC
E4
B_CC/BE3//B_REG
B_CREQ//B_INPACK
B_CVS2//B_VS2
B_CAD17//B_A24
GND
E5
E6
V
CC
A_RSVD//A_D14
E7
E8
A_CAD1//A_D4
E9
B_CAD31//B_D10
B_CAD27//B_D0
B_CINT//B_READY(IREQ)
B_CAD25//B_A1
B_CAD21//B_A5
B_CAD19//B_A25
B_CC/BE2//B_A12
B_CAD16//B_A17
B_CAD14//B_A9
J2
B_CCLK//B_A16
B_CDEVSEL//B_A21
A_CPAR//A_A13
A_RSVD//A_A18
A_CAD16//A_A17
A_CAD15//A_IOWR
A_CAD11//A_OE
E10
E11
E12
E13
E14
E15
E16
E18
E19
F1
J4
J5
J6
B2
J14
J15
J16
J18
J19
K1
V
CC
B_CAD1//B_D4
B3
B4
B_CAD2//B_D11
B5
B_CAD0//B_D3
B6
V
CCA
B_CCD1//B_CD1
A_CVS1//A_VS1
A_CINT//A_READY(IREQ)
A_CSERR//A_WAIT
B7
A_CAD6//A_D13
V
V
CC
B8
A_CAD2//A_D11
K2
CCA
B9
B_CAD30//B_D9
F2
A_CFRAME//A_A23
A_CIRDY//A_A15
A_CTRDY//A_A22
A_CAD9//A_A10
A_CAD7//A_D7
K4
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C1
B_CCLKRUN//B_WP(IOIS16)
B_CVS1//B_VS1
F4
K5
V
CCA
A_CAD26//A_A0
F5
K6
V
CCB
F6
K14
K15
K18
K19
L1
GNT
B_CAD22//B_A4
B_CAD20//B_A6
B_CAD18//B_A7
B_CIRDY//B_A15
B_CTRDY//B_A22
B_CGNT//B_WE
B_CSTOP//B_A20
GND
F7
PCLK
F8
A_CCD1//A_CD1
B_CAD28//B_D8
B_CAUDIO//B_BVD2(SPKR)
B_CSERR//B_WAIT
GND
CLKRUN
F9
PRST
F10
F11
F12
F13
F14
F15
F16
F18
F19
G1
A_CSTSCHG//A_BVD1(STSCHG/RI)
L2
A_CCLKRUN//A_WP(IOIS16)
L4
A_CCD2//A_CD2
A_CAD27//A_D0
A_CAUDIO//A_BVD2(SPKR)
REQ
B_CRST//B_RESET
B_CAD15//B_IOWR
B_CAD12//B_A11
B_CAD13//B_IORD
L5
L6
C2
A_CBLOCK//A_A19
B_CPERR//B_A14
B_CPAR//B_A13
A_CPERR//A_A14
A_CSTOP//A_A20
A_CAD14//A_A9
A_CAD13//A_IORD
A_CC/BE0//A_CE1
A_CAD5//A_D6
GND
L14
L15
L16
L18
L19
M1
M2
M4
M5
M6
M14
M15
M16
C18
C19
D1
AD31
V
CCB
AD28
B_CAD11//B_OE
AD30
D2
GND
AD29
D4
G2
A_CAD18//A_A7
A_CAD19//A_A25
A_CAD17//A_A24
A_CC/BE2//A_A12
A_CAD4//A_D12
B_CAD7//B_D7
B_CAD10//B_CE2
B_CAD9//B_A10
A_CAD29//A_D1
GND
D5
G4
D6
G5
A_CAD30//A_D9
A_RSVD//A_D2
A_CAD28//A_D8
C/BE3
D7
G6
D8
G7
D9
B_RSVD//B_D2
B_CCD2//B_CD2
B_CAD26//B_A0
G13
G14
G15
D10
D11
AD27
AD26
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
signal names and terminal assignments (continued)
Table 2. GJG Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI (Continued)
NO.
SIGNAL NAME
NO.
SIGNAL NAME
NO.
SIGNAL NAME
ZV_SCLK
M18
M19
N1
AD25
AD24
R6
PHY_LREQ
V2
R7
PHY_DATA0
PHY_DATA7
MFUNC3
SUSPEND
RI_OUT
AD2
V3
ZV_LRCLK
ZV_PCLK
LPS
ZV_HREF
ZV_VSYNC
ZV_Y0
R8
V4
N2
R9
V5
N4
R10
R11
R12
R13
R14
R15
R16
R18
R19
T1
V6
PHY_CTL1
PHY_DATA1
PHY_DATA5
SCL
N5
ZV_Y1
V7
N6
ZV_Y2
V8
N7
A_CAD31//A_D10
AD3
AD5
V9
N13
N14
N15
N16
N18
N19
P1
AD8
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W2
V
CC
DATA
AD22
AD16
AD23
C/BE2
AD0
GND
AD18
V
CC
GND
V
AD17
CCP
IDSEL/MFUNC7
ZV_UV1
ZV_UV4
GND
AD11
V
CC
T2
AD14
P2
ZV_Y3
T4
PAR
P4
ZV_Y4
T5
V
CC
PERR
P5
ZV_Y5
T6
PHY_CLK
STOP
P6
ZV_Y6
T7
GND
ZV_UV7
ZV_MCLK
ZV_SDATA
MFUNC5
PHY_CTL0
PHY_DATA2
PHY_DATA4
SDA
P7
LINKON
PHY_DATA3
MFUNC2
MFUNC1
G_RST
IRQSER
AD6
T8
PHY_DATA6
MFUNC4
SPKROUT
CLOCK
AD1
W3
P8
T9
W4
P9
T10
T11
T12
T13
T14
T15
T16
T18
T19
U1
W5
P10
P11
P12
P13
P14
P15
P16
P18
P19
R1
W6
W7
AD4
W8
C/BE0
W9
AD9
AD12
W10
W11
W12
W13
W14
W15
W16
W17
W18
MFUNC0
LATCH
V
CC
C/BE1
AD19
FRAME
IRDY
GND
AD21
V
CCP
AD7
AD20
ZV_UV3
ZV_UV6
TRDY
ZV_Y7
ZV_UV0
ZV_UV2
MFUNC6
U2
AD10
AD13
AD15
SERR
R2
U18
U19
V1
R4
DEVSEL
ZV_UV5
R5
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PCI4450 System Block Diagram
Figure 2 shows a simplified system implementation example using the PCI4450. The PCI interface includes
all address/data and control signals for PCI protocol. Highlighted in this diagram is the functionality supported
by the PCI4450. The PCI4450 supports PC/PCI DMA, PCI Way DMA (distributed DMA), PME wake-up from
D3
through D0, 4 interrupt modes, an integrated zoomed video port, and 12 multifunction pins (8 MFUNC,
cold
and 4 GPIO pins) that can be programmed for a wide variety of functions.
PCI Bus
Activity LED’s
Real Time
Clock
South Bridge
CLKRUN
IRQSER
PCI4450
Clock
2
TPS2206
Power
ZV
Enable
DMA
PME
Switch
Embedded
Controller
23
4
4
PC Card
Socket A
Zoomed Video
19 Video
68
VGA
Controller
23 for ZV†
PC Card
Socket B
14
68
23 for ZV
Audio
Codec
OHCI-PHY
Interface
4 Audio
PHY
Interrupt Routing Options:
1) Serial ISA/Serial PCI
2) Serial ISA/Parallel PCI
1394 Ports
†
ThePC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used forroutingthezoomedvideosignals
to the VGA controller.
Figure 2. PCI4450 System Block Diagram
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions
This sectiondescribesthePCI4450terminalfunctions. Theterminalsaregroupedintablesbyfunctionalitysuch
as PCI system function, power supply function, etc., for quick reference. The terminal numbers are also listed
for convenient reference.
Table 3. Power Supply
TERMINAL
FUNCTION
NAME
GFN NO.
A1, D4, D8, D13, D17, H4, H17, A3, A16, C1, D8, F12, G1, G19,
N4, N17, U4, U8, U13, U17 M2, N16, T4, T7, V14, W12
D6, D11, D15, F4, F17, K4, L17, A11, D14, E1, E6, E19, J14, P1,
GJG NO.
GND
Device ground terminals
V
CC
Power supply terminal for core logic (3.3 Vdc)
R4, R17, U6, U10, U15
P15, T5, V10, V13
Clamp voltage for PC Card A interface. Indicates Card A
signaling environment.
V
CCA
B5, F3, L4
B6, F1, K5
Clamp voltage for PC Card B interface. Indicates Card B
signaling environment.
V
V
B13, E19
P19, V14
B12, F18
N18, W13
CCB
Clamp voltage for PCI signaling (3.3 Vdc or 5 Vdc)
CCP
Table 4. PC Card Power Switch
TERMINAL
I/O
TYPE
FUNCTION
NAME
GFN NO.
GJG NO.
3-linepower switch clock. Information on the DATA line is sampled at the rising edge of
CLOCK. This terminal defaults as an input which means an external clock source must
be used. If the internal ring oscillator is used, then an external CLOCK source is not
required.The internal oscillator may be enabled by setting bit 27 of the system control
register (PCI offset 80h) to a 1b.
CLOCK
U12
T11
I/O
A 43 kW pulldown resistor should be tied to this terminal.
3-line power switch data. DATA is used to serially communicate socket power-control
information to the power switch.
DATA
V12
V11
O
O
3-linepower switch latch. LATCH is asserted by the PCI4450 to indicate to the PC Card
power switch that the data on the DATA line is valid.
LATCH
W12
W11
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 5. PCI System
TERMINAL
GFN NO.
I/O
TYPE
FUNCTION
NAME
GJG NO.
PCI clock run. CLKRUN is used by the central resource to request permission to stop the
PCI clock or to slow it down, and the PCI4450 responds accordingly. If CLKRUN is not
implemented, then this pin should be tied low. CLKRUN is enabled by default by bit 1
(KEEPCLK) in the system control register.
K18
K17
K18
I/O
I
CLKRUN
PCIbus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are
sampledat the rising edge of PCLK.
PCLK
PRST
K15
K19
PCIreset.WhenthePCIbusresetisasserted,PRSTcausesthePCI4450toplacealloutput
buffers in a high-impedance state and reset all internal registers. When PRST is asserted,
the device is completely nonfunctional. After PRST is deasserted, the PCI4450 is in its
default state.WhentheSUSPENDmodeisenabled,thedeviceisprotectedfromthePRST
and the internal registers are preserved. All outputs are placed in a high-impedance state,
but the contents of the registers are preserved.
K19
Y12
I
I
Global reset. When the global reset is asserted, the G_RST signal causes the PCI4450 to
place all output buffers in a high-impedance state and reset all internal registers. When
G_RST is asserted, the device is completely in its default state. For systems that require
wake-upfrom D3, G_RSTwillnormallybeassertedonlyduringinitialboot.PRSTshouldbe
assertedfollowinginitialboot so that PME context is retained when transitioning from D3 to
D0. For systems that do not require wake-up from D3, G_RST should be tied to PRST.
G_RST
P11
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 6. PCI Address and Data
TERMINAL
I/O
TYPE
FUNCTION
NAME GFN NO. GJG NO.
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
L18
L19
L15
L18
L19
M20
M19
M18
M17
N20
N19
P18
R20
R19
P17
R18
T20
T19
T18
Y19
W18
V17
U16
Y18
W17
V16
Y17
V15
U14
Y16
W15
Y15
W14
Y14
V13
L16
M15
M16
M18
M19
N15
N14
P18
P19
P16
R18
R19
R15
W17
V16
W16
T15
V15
W15
P14
R14
W14
P13
R13
T13
N13
R12
T12
V12
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primaryinterface. DuringtheaddressphaseofaprimarybusPCIcycle, AD31–AD0containa32-bit
addressor other destination information. During the data phase, AD31–AD0 contain data.
I/O
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which
byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0),
C/BE1appliestobyte1(AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to
byte 3(AD31–AD24).
N18
U20
V18
W16
M14
R16
T16
T14
C/BE3
C/BE2
C/BE1
C/BE0
I/O
I/O
PCI bus parity. In all PCI bus read and write cycles, the PCI4450 calculates even parity across the
AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI4450 outputs this
parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is
comparedto the initiator’s parity indicator. A compare error results in the assertion of a parity error
(PERR).
PAR
W19
V17
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 7. PCI Interface Control
TERMINAL
I/O
TYPE
FUNCTION
NAME
GFN NO. GJG NO.
PCIdeviceselect.ThePCI4450assertsDEVSELtoclaimaPCIcycleasthetargetdevice.
As a PCI initiator on the bus, the PCI4450 monitors DEVSEL until a target responds. If no
target responds before timeout occurs, then the PCI4450 terminates the cycle with an
initiator abort.
DEVSEL
U19
U19
I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to
indicatethat a bus transaction is beginning, and data transfers continue while this signal
isasserted.WhenFRAMEisdeasserted,thePCIbustransactionisinthefinaldataphase.
FRAME
GNT
V20
K20
T18
K14
I/O
I
PCI bus grant. GNTisdrivenbythePCIbusarbitertograntthePCI4450accesstothePCI
bus after the current data transaction has completed. GNT may or may not follow a PCI
bus request, depending on the PCI bus parking algorithm.
PCIbus lock. MFUNC7/LOCK can be configured as PCI LOCKandusedtogainexclusive
access downstream. Since this functionality is not typically used, other functions may be
accessed through this terminal. MFUNC7/LOCK defaults to and can be configured
throughthe multifunction routing status register.
LOCK
(MFUNC7)
P20
P20
T17
N19
N19
T19
I/O
I
Initialization device select. IDSEL selects the PCI4450 during configuration space
accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI
bus. If the LATCH terminal (W12/W11) has an external pulldown resistor, then this
terminalis configurable as MFUNC7 and IDSEL defaults to the AD23 terminal.
IDSEL/MFUNC7
IRDY
PCIinitiatorready. IRDYindicatesthePCIbusinitiator’sabilitytocompletethecurrentdata
phaseof the transaction. A data phase is completed on a rising edge of PCLK where both
IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait
states are inserted.
I/O
PCIparity error indicator. PERR is driven by a PCI device to indicate that calculated parity
does not match PAR when PERR is enabled through bit 6 of the command register.
W20
L20
V18
L14
I/O
O
PERR
REQ
PCI bus request. REQ is asserted by the PCI4450 to request access to the PCI bus as an
initiator.
PCIsystemerror.SERR isanoutputthatispulsedfromthePCI4450whenenabledthrough
thecommand register, indicating a system error has occurred. The PCI4450 need not be
thetargetofthePCIcycletoassertthissignal. WhenSERRisenabledinthebridgecontrol
register, this signal also pulses, indicating that an address parity error has occurred on a
CardBusinterface.
SERR
Y20
W18
O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the
current PCI bus transaction. STOP is used for target disconnects and is commonly
asserted by target devices that do not support burst data transfers.
STOP
TRDY
V19
U18
V19
U18
I/O
I/O
PCI target ready. TRDY indicates the primary bus target’s ability to complete the current
data phase of the transaction. A data phase is completed on a rising edge of PCLK when
both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states
areinserted.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 8. System Interrupt
TERMINAL
NAME GFN NO. GJG NO.
I/O
TYPE
FUNCTION
Parallel PCI interrupt. INTA can be mapped to MFUNC0 when parallel PCI interrupts are
INTA
(MFUNC0)
used.
W11
Y11
W10
P10
I/O
I/O
See programmable interrupt subsystem for details on interrupt signaling. MFUNC0/INTA
defaultsto a general-purpose input.
Parallel PCI interrupt. INTB can be mapped to MFUNC1 when parallel PCI interrupts are
used.
See programmable interrupt subsystem for details on interrupt signaling. MFUNC1/INTB
defaultsto a general-purpose input.
INTB
(MFUNC1)
Parallel PCI interrupt. INTC can be mapped to MFUNC2 when parallel PCI interrupts are
INTC
(MFUNC2)
used.
Y10
P9
I/O
I/O
See programmable interrupt subsystem for details on interrupt signaling. MFUNC2/INTC
defaultsto a general-purpose input.
Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme.
Serialized PCI interrupts can also be sent in the IRQSER stream. See programmable
interruptsubsystem for details on interrupt signaling.
IRQSER
W13
P12
Interrupt request/secondary functions multiplexed. The primary function of these terminals
is to provide programmable options supported by the PCI4450. These interrupt multiplexer
outputs can be mapped to various functions. See multifunction routing status register for
options.
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
MFUNC0
Y4
V5
R5
W5
T9
R9
P9
W9
V10
Y10
Y11
W11
Alloftheseterminalshavesecondaryfunctions,suchasPCIinterrupts,PC/PCIDMA,OHCI
LEDs, GPE request/grant, ring indicate output, and zoomed video status, that can be
selectedwith the appropriate programming of this register. When the secondary functions
are enabled, the respective terminals are not available for multifunction routing.
O
O
P10
W10
See the multifunctionroutingstatusregister for programming options.
Ring indicate out and power management event output. Terminal provides an output to the
system for ring-indicate or PME signals. Alternately, RI_OUT can be routed on MFUNC7.
RI_OUT/PME
Y13
R11
Table 9. PC/PCI DMA
TERMINAL
GFN NO. GJG NO.
I/O
TYPE
FUNCTION
NAME
PCGNT
(MFUNC2)
PCGNT
PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system
supportingthe PC/PCI DMA scheme. PCGNT, is available on MFUNC2 or MFUNC3.
Y10
V10
P9
R9
I/O
This terminal is also used for the serial EEPROM interface.
(MFUNC3)
PCREQ
(MFUNC7)
PCREQ
(MFUNC4)
PCREQ
P20
W9
N19
T9
PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system
supporting the PC/PCI DMA scheme. PCREQ is available on MFUNC7, MFUNC4, or
MFUNC0.
O
This terminal is also used for the serial EEPROM interface.
W11
W10
(MFUNC0)
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 10. Zoomed Video
TERMINAL
I/O AND MEMORY
INTERFACE
I/O
TYPE
FUNCTION
GFN
NO.
NAME
GJG NO.
SIGNAL
ZV_HREF
P3
R2
N1
N2
A10
O
O
Horizontal sync to the zoomed video port
ZV_VSYNC
A11
Vertical sync to the zoomed video port
ZV_Y7
ZV_Y6
ZV_Y5
ZV_Y4
ZV_Y3
ZV_Y2
ZV_Y1
ZV_Y0
V1
U2
T3
U1
T2
R3
P4
T1
R1
P6
P5
P4
P2
N6
N5
N4
A20
A14
A19
A13
A18
A8
O
Video data to the zoomed video port in YV:4:2:2format
A17
A9
ZV_UV7
ZV_UV6
ZV_UV5
ZV_UV4
ZV_UV3
ZV_UV2
ZV_UV1
ZV_UV0
Y2
W2
Y1
W1
V3
U3
V2
T4
W2
U2
V1
T2
U1
R4
T1
R2
A25
A12
A24
A15
A23
A16
A22
A21
O
Video data to the zoomed video port in YV:4:2:2format
ZV_SCLK
ZV_MCLK
ZV_PCLK
ZV_LRCLK
ZV_SDATA
W3
W4
Y3
V4
U5
V2
W3
V4
A7
A6
O
O
O
O
O
Audio SCLK PCM
Audio MCLK PCM
IOIS16
INPACK
SPKR
Pixel clock to the zoomed video port
Audio LRCLK PCM
V3
W4
Audio SDATA PCM
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 11. Miscellaneous
TERMINAL
I/O
FUNCTION
GFN
NO.
GJG
NO.
TYPE
NAME
Multifunctionterminal0.Defaultsasageneral-purposeinput(GPI0),andcanbeprogrammed
to perform various functions. Refer to multifunctionroutingregister description.
MFUNC0
W11
W10
I/O
Multifunctionterminal1.Defaultsasageneral-purposeinput(GPI1),andcanbeprogrammed
to perform various functions. Refer to multifunctionroutingregister description.
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IDSEL/MFUNC7
SCL
Y11
Y10
V10
P10
P9
I/O
I/O
I/O
Multifunctionterminal2.Defaultsasageneral-purposeinput(GPI2),andcanbeprogrammed
to perform various functions. Refer to multifunctionroutingregister description.
Multifunctionterminal3.Defaultsasageneral-purposeinput(GPI3),andcanbeprogrammed
to perform various functions. Refer to multifunctionroutingregister description.
R9
Multifunction terminal 4. Defaults as a high–impedance reserved input, and can be
programmed to perform various functions. Refer to multifunctionroutingregisterdescription.
W9
V5
T9
W5
R5
I/O
I/O
I/O
I/O
I/O
I/O
Multifunction terminal 5. Defaults as a high–impedance reserved input, and can be
programmed to perform various functions. Refer to multifunctionroutingregisterdescription.
Multifunction terminal 6. Defaults as a high–impedance reserved input, and can be
programmed to perform various functions. Refer to multifunctionroutingregisterdescription.
Y4
IDSEL and multifunction terminal 7. Defaults as IDSEL, but may be used as amultifunction
terminal. Refer to multifunctionroutingregister description and Section 3.4 for details.
P20
W10
Y9
N19
V9
Serial ROM clock. This terminal provides the SCL serial clock signaling in a two–wire serial
ROM implementation, and is sensed at reset for serial ROM detection.
SerialROMdata.ThisterminalprovidestheSDAserialdatasignalinginatwo–wireserialROM
implementation.
SDA
W9
Speakeroutput. SPKROUT is the output to the host system that can carry SPKR or CAUDIO
throughthePCI4450fromthePCCardinterface.SPKROUTisdrivenastheXORcombination
of card SPKR//CAUDIO inputs.
V11
U11
T10
R10
O
I
SPKROUT
SUSPEND
Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is
asserted. See suspend mode fordetails.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 12. 16-bit PC Card Address and Data (slots A and B)
TERMINAL
GFN NO.
SLOT SLOT SLOT
GJG NO.
SLOT
I/O
TYPE
FUNCTION
NAME
†
‡
†
‡
A
B
A
B
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
G2
F1
G4
E2
D1
E4
D2
B1
A2
E3
E1
D3
C2
F2
C4
C5
B2
C3
G3
H3
H1
J4
A16
C16
A18
C17
B18
A20
C18
C19
E17
B17
D16
B19
B20
A17
E18
E20
C20
D18
B16
D14
A15
C14
A14
A13
D12
C12
G4
G5
F2
F5
E5
D2
C2
B2
B3
E2
F4
D1
B1
G6
A4
F6
D4
A2
G2
H1
H4
H5
J1
E14
A15
D15
B17
A18
B19
D16
D18
E16
A17
B16
C18
C19
E15
F15
G15
E18
D19
B15
B14
E13
B13
D13
D12
E12
D11
O
PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.
J2
K2
K3
K1
J5
J6
K6
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
C6
A5
C7
B7
C8
R1
P1
N2
D7
B6
A6
A7
B8
P2
N3
N1
G18
G19
H18
H20
J18
D9
A6
E7
B7
G7
B8
N7
M4
M6
F7
D7
A7
E8
A8
M5
M1
L5
G18
H15
H18
H14
J16
E9
B9
B9
F9
D10
F20
G20
H19
J17
J19
C9
I/O
PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.
G13
H16
H19
J15
J18
D9
D4
D3
D2
D1
A9
C10
A9
E10
D0
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal G2 is A_A25.
Terminal name for slot B is preceded with B_. For example, the full name for terminal A16 is B_A25.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 13. 16-bit PC Card Interface Control (slots A and B)
TERMINAL
GFN NO.
GJG NO.
I/O
TYPE
FUNCTION
NAME
SLOT SLOT SLOT SLOT
†
A
‡
B
†
A
‡
B
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that
include batteries. BVD1 and BVD2 indicate the condition of the batteries on a
memoryPC Card. Both BVD1 and BVD2 are kept high when the battery is good.
When BVD2 is low and BVD1 is high, the battery is weak and should be replaced.
WhenBVD1islow,thebatteryisnolongerserviceableandthedatainthememory
PC Card is lost. See ExCA card status-change interrupt configuration register for
the enable bits. See ExCA card status-change register and the ExCA interface
status register for the status bits for this signal.
BVD1
(STSCHG/RI)
M2
A11
L1
A10
I
Status change. STSCHG is used to alert the system to a change in the READY,
write protect, or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that
include batteries. BVD2 and BVD1 indicate the condition of the batteries on a
memoryPC Card. Both BVD1 and BVD2 are high when the battery is good. When
BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When
BVD1 is low, the battery is no longer serviceable and the data in the memory PC
Card is lost. See ExCA card status-change interrupt configuration register for
enablebits. See ExCA card status-change register and the ExCA interface status
register for the status bits for this signal.
BVD2
(SPKR)
M1
C11
L6
F10
I
Speaker. SPKRisanoptionalbinaryaudiosignalavailableonlywhenthecardand
socket have been configured for the 16-bit I/O interface. The audio signals from
cards A and B are combined by the PCI4450 and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA
operationsto a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to
indicatea request for a DMA operation.
PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected
togroundonthePCCard.WhenaPCCardisinsertedintoasocket,CD1andCD2
are pulled low. For signal status, see ExCA interface status register.
A8
M4
J20
B10
F8
L4
J19
D10
CD1
CD2
I
Cardenable 1 and card enable 2. CE1 and CE2enableeven-andodd-numbered
address bytes. CE1 enables even-numbered address bytes, and CE2 enables
odd-numbered address bytes.
A4
B4
F19
G17
D6
A5
G16
G14
CE1
CE2
O
Inputacknowledge.INPACK isassertedbythePCCardwhenitcanrespondtoan
I/O read cycle at the current address.
INPACK
IORD
J3
D5
B3
B14
D20
D19
J4
D5
B4
A13
F16
F14
I
DMA request. INPACK can be used as the DMA request signal during DMA
operationsfrom a 16-bit PC Card that supports DMA. If used as a strobe, the PC
Card asserts this signal to indicate a request for a DMA operation.
I/Oread.IORDisassertedbythePCI4450toenable16-bitI/OPCCarddataoutput
during host I/O read cycles.
O
O
DMA write. IORD is used as the DMA write strobe during DMA operations from a
16-bit PC Card that supports DMA. The PCI4450 asserts IORD during DMA
transfers from the PC Card to host memory.
I/Owrite. IOWRis driven lowbythePCI4450tostrobewritedatainto16-bitI/OPC
Cards during host I/O write cycles.
IOWR
DMA read. IOWR is used as the DMA write strobe during DMA operations from a
16-bit PC Card that supports DMA. The PCI4450 asserts IOWR during transfers
from host memory to the PC Card.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 13. 16-bit PC Card Interface Control (slots A and B) (continued)
TERMINAL
GFN NO.
GJG NO.
I/O
TYPE
FUNCTION
NAME
SLOT SLOT SLOT SLOT
†
A
‡
B
†
A
‡
B
Outputenable. OE is driven low by the PCI4450 to enable 16-bit memory PC Card
dataoutput during host memory read cycles.
OE
A3
L2
F18
A12
B5
K2
F19
E11
O
DMAterminal count. OE is used as terminal count (TC) duringDMAoperationsto
a 16-bit PC Card that supports DMA. The PCI4450 asserts OE to indicate TC for
a DMA write operation.
Ready.ThereadyfunctionisprovidedbyREADYwhenthe16-bitPCCardandthe
hostsocketareconfiguredforthememory-onlyinterface.READY is driven low by
the 16-bit memory PC Cards to indicate that the memory card circuits are busy
processing a previous write command. READY is driven high when the 16-bit
memoryPC Card is ready to accept a new data transfer command.
READY
(IREQ)
I
Interruptrequest. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host
that a device on the 16-bit I /O PC Card requires service by the host software.
IREQ is high (deasserted) when no interrupt is requested.
Attribute memory select. REG remains high for all common memory accesses.
When REG is asserted, access is limited to attribute memory (OE or WE active)
and to the I/O space (IORD or IOWR active). Attribute memory is a separately
accessed section of card memory and is generally used to record card capacity
andotherconfigurationandattributeinformation.
REG
J1
C13
J2
A12
O
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA
operationsto a 16-bit PC Card that supports DMA. The PCI4450 asserts REG to
indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR)
or DMA write (IORD) strobes to transfer data.
RESET
WAIT
H2
L3
B15
B11
H2
K4
F13
F11
O
I
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
Bus cycle wait. WAITis driven by a 16-bit PC Card to delay the completion of (i.e.,
extend) the memory or I/O cycle in progress.
Write enable. WE is used to strobe memory write data into 16-bit memory PC
Cards. WE is alsousedformemoryPCCardsthatemployprogrammablememory
technologies.
WE
C1
A19
E4
B18
O
DMAterminalcount.WEisusedasTCduringDMAoperationstoa16-bitPCCard
that supports DMA. The PCI4450 asserts WE to indicate TC for a DMA read
operation.
Writeprotect.WPappliesto16-bitmemoryPCCards.WPreflectsthestatusofthe
write-protectswitch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used
for the 16-bit port (IOIS16) function.
I/Ois16bits.IOIS16appliesto16-bitI/OPCCards.IOIS16isassertedbythe16-bit
PC Card when the address on the bus corresponds to an address to which the
16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit
accesses.
WP
(IOIS16)
M3
A10
L2
B10
I
DMArequest. WP can be used as the DMA request signal during DMA operations
toa16-bitPCCardthatsupportsDMA. Ifused, thePCCardassertsWPtoindicate
a request for a DMA operation.
VS1
VS2
L1
G1
B12
C15
K1
H6
B11
A14
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction
with each other, determine the operating voltage of the 16-bit PC Card.
I/O
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal C1 is A_WE.
Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_WE.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 14. CardBus PC Card Interface System (slots A and B)
TERMINAL
GFN NO.
GJG NO.
I/O
TYPE
FUNCTION
NAME
SLOT SLOT SLOT SLOT
†
A
‡
B
†
A
‡
B
CardBusPC Card clock. CCLK provides synchronous timing for all transactions on
the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG,
CAUDIO, CCD2, CCD1, andCVS2–CVS1aresampledontherisingedgeofCCLK,
and all timing parameters are defined with the rising edge of this signal. CCLK
operates at the PCI bus clock frequency, but it can be stopped in the low state or
slowed down for power savings.
CCLK
E3
B17
E2
A17
O
CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request
an increase in the CCLK frequency, and by the PCI4450 to indicate that the CCLK
frequency is decreased. CardBus clock run (CCLKRUN) follows the PCI clock run
(CLKRUN).
M3
H2
A10
B15
L2
B10
F13
O
CCLKRUN
CRST
CardBusPCCardreset. CRSTisusedtobringCardBusPCCard-specificregisters,
sequencers, andsignalstoaknownstate. WhenCRST is asserted, all CardBus PC
Card signals must be placed in a high-impedance state, and the PCI4450 drives
these signals to a valid logic level. Assertion can be asynchronous to CCLK, but
deassertionmust be synchronous to CCLK.
H2
I/O
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal E3 is A_CCLK.
Terminal name for slot B is preceded with B_. For example, the full name for terminal B17 is B_CCLK.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 15. CardBus PC Card Address and Data (slots A and B)
TERMINAL
GFN NO.
GJG NO.
I/O
TYPE
FUNCTION
NAME
SLOT SLOT SLOT SLOT
†
A
‡
B
†
A
‡
B
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
R1
P1
N3
N2
N1
K1
K3
K2
J2
D9
B9
A9
N7
M4
M1
M6
L5
K6
J6
J5
E9
B9
A9
F9
D10
C10
C12
D12
A13
A14
C14
A15
D14
A16
B16
C16
E17
D19
C20
D20
E18
F18
G17
E20
G18
F20
H18
G20
H20
H19
J18
J17
J19
E10
D11
E12
D12
D13
B13
E13
B14
E14
B15
A15
E16
F14
E18
F16
F15
F19
G14
G15
G18
G13
H18
H16
H14
H19
J16
J15
J18
J1
J4
H5
H4
H1
G4
G2
G5
B3
B4
D4
D5
A4
B5
A5
F6
A6
F7
B7
D7
G7
A7
B8
E8
A8
H1
H3
G2
G3
F1
A2
B3
B2
D5
C4
A3
B4
C5
C6
D7
C7
B6
B7
A6
C8
A7
B8
PC Card address and data. These signals make up the multiplexed CardBus address
anddata bus on the CardBus interface. During the address phase of a CardBus cycle,
CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,
CAD31–CAD0contain data. CAD31 is the most significant bit.
I/O
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the
same CardBus terminals. During the address phase of
a CardBus cycle,
J1
F2
C3
A4
C13
A17
D18
F19
J2
G6
A2
D6
A12
E15
D19
G16
CC/BE3
CC/BE2
CC/BE1
CC/BE0
CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is
used as byte enables. The byte enables determine which byte paths of the full 32-bit
data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1
applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and
CC/BE3 applies to byte 3 (CAD31–CAD24).
I/O
I/O
CardBusparity.InallCardBusreadandwritecycles,thePCI4450calculatesevenparity
across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI4450
outputsCPARwithaone-CCLKdelay.AsatargetduringCardBuscycles,thecalculated
parity is compared to the initiator’s parity indicator; a compare error results in a parity
errorassertion.
CPAR
C2
B20
B1
C19
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal C2 is A_CPAR.
Terminal name for slot B is preceded with B_. For example, the full name for terminal B20 is B_CPAR.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 16. CardBus PC Card Interface Control (slots A and B)
TERMINAL
GFN NO.
GJG NO.
I/O
TYPE
FUNCTION
NAME
SLOT SLOT SLOT SLOT
†
A
‡
B
†
A
‡
B
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system
speaker. The PCI4450 supports the binary audio mode and outputs a binary signal
from the card to SPKROUT.
CAUDIO
CBLOCK
M1
D2
C11
C18
L6
F10
D16
I
C2
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction
withCVS1andCVS2toidentifycardinsertionandinterrogatecardstodeterminethe
operatingvoltage and card type.
A8
M4
J20
B10
F8
L4
J19
D10
CCD1
CCD2
I
CardBus device select. The PCI4450 asserts CDEVSEL to claim a CardBus cycle
as the target device. As a CardBus initiator on the bus, the PCI4450 monitors
CDEVSELuntil a target responds. If no target responds before timeout occurs, then
the PCI4450 terminates the cycle with an initiator abort.
CDEVSEL
CFRAME
D1
G4
B18
A18
E5
F2
A18
D15
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle.
CFRAME is asserted to indicate that a bus transaction is beginning, and data
transfers continue while this signal is asserted. When CFRAME is deasserted, the
CardBus bus transaction is in the final data phase.
I/O
CardBus bus grant. CGNT is driven by the PCI4450 to grant a CardBus PC Card
access to the CardBus bus after the current data transaction has been completed.
C1
L2
A19
A12
E4
K2
B18
E11
I
I
CGNT
CINT
CardBusinterrupt. CINT is asserted low by a CardBus PC Card to requestinterrupt
servicing from the host.
CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete
thecurrentdataphaseofthetransaction.Adataphaseiscompletedonarisingedge
ofCCLKwhenboth CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are
bothsampled asserted, wait states are inserted.
CIRDY
E1
D16
F4
B16
I/O
CardBus parity error. CPERR is used to report parity errors during CardBus
transactions, except during special cycles. It is driven low by a target two clocks
followingthat data when a parity error is detected.
CPERR
CREQ
D3
J3
B19
B14
D1
J4
C18
A13
I/O
I
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires
use of the CardBus bus as an initiator.
CardBussystemerror.CSERRreportsaddressparityerrorsandothersystemerrors
thatcould lead to catastrophic results. CSERR is driven by the card synchronous to
CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The
PCI4450canreportCSERRtothesystembyassertionofSERRonthePCIinterface.
CSERR
L3
B11
K4
F11
I
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop
the current CardBus transaction. CSTOP is used for target disconnects, and is
commonlyasserted by target devices that do not support burst data transfers.
CSTOP
E4
A20
A11
D2
L1
B19
A10
I/O
I
CardBus status change. CSTSCHG is used to alert the system to a change in the
card’s status and is used as a wake-up mechanism.
M2
CSTSCHG
CardBustargetready. CTRDYindicatestheCardBustarget’s ability to complete the
current data phase of the transaction. A data phase is completed on a rising edge of
CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are
inserted.
CTRDY
E2
C17
F5
B17
I/O
CardBusvoltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used
in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards
to determine the operating voltage and card type.
CVS1
CVS2
L1
G1
B12
C15
K1
H6
B11
A14
I/O
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal M1 is A_CAUDIO.
Terminal name for slot B is preceded with B_. For example, the full name for terminal C11 is B_CAUDIO.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
terminal functions (continued)
Table 17. IEEE1394 PHY/Link Interface Terminals
TERMINAL
GFN NO.
I/O
TYPE
FUNCTION
NAME
GJG NO.
Phy–link interface control. These bi-direction signals control passage of
informationbetween the PHY and link. The link can only drive these terminals
after the PHY has granted permission following a link request (LREQ).
PHY_CTL1
PHY_CTL0
W6
U7
V6
W6
I/O
I/O
V9
U9
Y8
W8
V8
Y7
W7
V7
R8
T8
PHY_DATA7
PHY_DATA6
PHY_DATA5
PHY_DATA4
PHY_DATA3
PHY_DATA2
PHY_DATA1
PHY_DATA0
Phy–linkinterfacedata.Thesebi-directionalsignalspassdatabetweenthePHY
andlink. These terminals are driven by the link on transmissions and are driven
by the PHY on receptions. Only DATA1–DATA0 are valid for 100 Mbit speed.
DATA4–DATA0 are valid for 200 Mbit speed and DATA7–DATA0 are valid for
400Mbit speed.
V8
W8
P8
W7
V7
R7
System clock. This input provides a 49.152 MHz clock signal for data
synchronization.
PHY_CLK
V6
Y5
T6
R6
I
Link request. This signal is driven by the link to initiate a request for the PHY to
perform some service.
PHY_LREQ
O
LINKON
LPS
Y6
P7
V5
I
1394 link on. This input from the PHY indicates that the link should turn on.
Link power status. LPS indicates that link is powered and fully functional.
W5
O
I/O characteristics
Figure 3 shows a 3-state bidirectional buffer illustration for reference. The table, recommended operating
conditions provides the electrical characteristics of the inputs and outputs. The PCI4450 meets the ac
specifications of the PC Card 95 Standard and the PCI Bus 2.1 specifications.
V
CCP
Tied for Open Drain
OE
Pad
Figure 3. 3-State Bidirectional Buffer
clamping voltages
The I/O sites can be pulled through a clamping diode to a voltage rail for protection. The 3.3-V core power supply
is independent of the clamping voltages. The clamping (protection) diodes are required if the signaling
environment on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5.0 Vdc, and
the PCI4450 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V buffer with
a clamping diode to V
. If a system design requires a 5.0-V PCI bus, then the V
would be connected to
CCP
CCP
the 5.0-V power supply.
A standard die has only one clamping voltage for the sites as shown in Figure 3. After the terminal assignments
are fixed, the fabrication facility will support a design by splitting the clamping voltage for customization. The
PCI4450 requires five separate clamping voltages since it supports a wide range of features. The five voltages
are listed and defined in the table, recommended operating conditions.
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PCI4450GFN/GJG
PC Card and OHCI Controller
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PCI interface
This section describes the PCI interface of the PCI4450, and how the device responds to and participates in
PCI bus cycles. The PCI4450 provides all required signals for PCI master/slave devices and may operate in
either 5-V or 3.3-V PCI signaling environments by connecting the V
terminals to the desired signaling level.
CCP
PCI bus lock (LOCK)
The bus locking protocol defined in the PCI Specification is not highly recommended, but is provided on the
PCI4450 as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the
terminal function defaults to a general-purpose input (GPI). The use of LOCK is only supported by
PCI-to-CardBus bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is
asserted, nonexclusive transactions may proceed to an address that is not currently locked. A grant to start
a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own
protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK.
To avoid confusion with the PCI bus clock, the CardBus signal for this protocol is CBLOCK.
An agent may need to do an exclusive operation because a critical memory access to memory might be broken
into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the
lock is defined by PCI to be 16 bytes aligned. The lock protocol defined by PCI allows a resource lock without
interfering with nonexclusive, real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this
scenario the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is
asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that
supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified
line when a locked operation is in progress.
The PCI4450 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which
can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can
occur if a CardBus target supports delayed transactions and blocks access as the target until it completes a
delayed read. This target characteristic is prohibited by the 2.1 PCI Specification, and the issue is resolved by
the PCI master using LOCK.
loading the subsystem identification (EEPROM interface)
The subsystem vendor ID register and subsystem ID register make up a double word of PCI configuration space
located at offset 40h for functions 0 and 1. This doubleword register, used for system and option card (mobile
dock) identification purposes, is required by some operating systems. Implementation of this unique identifier
register is a PC ‘97 requirement.
The PCI4450 offers two mechanisms to load a read-only value into the subsystem registers. The first
mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but the access mode may be made read/write by clearing the SUBSYSRW
bit in the system control register (bit 5 of the system control register, offset 80h). Once this bit is cleared (0),
the BIOS may write a subsystem identification value into the registers at offset 40h. The BIOS must set the
SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register are limited to read-only
access. This approach saves the added cost of implementing the serial EEPROM.
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID
register must be loaded with a unique identifier through a serial EEPROM interface. The PCI4450 loads the
double-word of data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PRST and G_RST from the entire PCI4450 core, including the serial EEPROM state machine. Refer tosuspend
mode for details on using SUSPEND. The PCI4450 provides a two-line serial bus interface to the serial
EEPROM.
The system designer must implement a pulldown resistor on the PCI4450 LATCH terminal to indicate the serial
EEPROM mode. Only when this pulldown resistor is present will the PCI4450 attempt to load data through the
serial EEPROM interface. The serial EEPROM interface is a two-pin interface with one data signal (SDA) and
one clock signal (SCL). Figure 4 illustrates a typical PCI4450 application using the serial EEPROM interface.
V
CC
Serial
EEPROM
Latch
A0
SCL
SDA
A1 SCL
A2 SDA
PCI4450
Figure 4. Serial EEPROM Application
As stated above, when the PCI4450 is reset by G_RST, the subsystem data is read automatically from the
EEPROM. The PCI4450 masters the serial EEPROM bus and reads four bytes as described in Figure 5.
SlaveAddress
Word Address
SlaveAddress
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
b6 b5 b4 b3 b2 b1 b0
1
A
R/W#
Restart
Data Byte 3
R/W#
Data Byte 0
M
Data Byte 1
M
Data Byte 2
M
M
P
S/P – Start/Stop Condition
A – Slave Acknowledgment
M – Master Acknowledgment
Figure 5. EEPROM Interface Subsystem Data Collection
The EEPROM is addressed at slave address A0h (1010 0000b), as indicated in Figure 5, and the EEPROM
word address auto-increments after each byte transfers according to the protocol. All hardware address bits
for the EEPROM should be tied to the appropriate level to achieve this slave address. Thus, to provide the
subsystem register with data AABBCCDDh the EEPROM should be programmed with address 0 = AAh, 1 =
BBh, 2 = CCh, and 3 = DDh.
The serial EEPROM chip in the sample application circuit, Figure 4, assumes the 1010b high address nibble.
The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal
inputs tied to GND.
The serial EEPROM interface signals require pullup resistors. The serial EEPROM protocol allows bidirectional
transfers. Both the SCL and SDA signals are placed in a high-impedance state and pulled high when the bus
is not active. A high-to-low transition of the SDA line defines a start condition (S). A low-to-high transition of SDA
while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this
time will be interpreted as a control signal. Data is valid and stable during the clock high period. Figure 6
illustrates this protocol.
SDA
SCL
Start
Stop
Change of
Condition
Condition
Data Allowed
Data Line Stable,
Data Valid
Figure 6. Serial EEPROM Start/Stop Conditions and BIt Transfers
Each address byte and data transfer is followed by an acknowledge bit, as indicated in Figure 5. When the
PCI4450 transmits the addresses, it returns the SDA signal to the high state and places the line in a
high-impedancestate. The PCI4450 then generates an SCL clock cycle and expects the EEPROM to pull down
the SDA line during the acknowledge pulse. This procedure is referred to as a slave acknowledge with the
PCI4450 transmitter and the EEPROM receiver. Figure 7 illustrates general acknowledges.
During the data byte transfers from the serial EEPROM to the PCI4450, the EEPROM clocks the SCL signal.
After the EEPROM transmits the data to the PCI4450, it returns the SDA signal to the high state and places
the line in a high-impedance state. The EEPROM then generates an SCL clock cycle and expects the PCI4450
to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a masteracknowledge
with the EEPROM transmitter and the PCI4450 receiver. Figure 7 illustrates general acknowledges.
SCL From
1
2
3
7
8
9
Master
SDA Output
By Transmitter
SDA Output
ByReceiver
Figure 7. Serial EEPROM Protocol – Acknowledge
EEPROM interface status information is communicated through the general status register located at PCI offset
85h. The EEDETECT bit in this register indicates whether or not the PCI4450 serial EEPROM circuitry detects
the pulldown resistor on LATCH. An error condition, such as a missing acknowledge, results in the DATAERR
bit being set. The EEBUSY bit is set while the subsystem ID register is loading (serial EEPROM interface is
busy).
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PC Card and OHCI Controller
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serial ROM implementation
A serial ROM interface exists in both the Open HCI function and the PC Card controller functions. The PCI4450
implementation adds a busy indication between the interfaces to allow the function 2 loading to follow the
functions 0 and 1 load. All serial ROM addressing uses slave address 8’hA0. The functions 0 and 1 serial
EEPROM state machine is modified to provide a busy indication to function 2 and to start loading registers at
word address 8’h20 to allow for some serial ROM format flexibility in function 2.
Primarily, the serial ROM is used to preload the PCI4450 registers with data, and only write accessible bits in
these registers may be preloaded. Figure 8 illustrates the PCI4450 serial ROM data format, which is an
expanded version of both the OHCI-Lynx and PCI1450 serial ROM formats.
SlaveAddress8’b10100000
Flag byte
Word address 32 (20h)
Word address 33
SubSys byte 3
MaxLat / MinGnt
SubSys byte 0
SubSys byte 2
SubSys byte 1
Word address 34
Word address 35
Word address 0
Word address 1
Word address 2
Word address 3
Word address 4
Word address 5
Word address 6
Word address 7
SubSys byte 1
SubSys byte 2
SubSys byte 3
SubSys byte 0
SysCtrl byte 0
SysCtrl byte 1
Word address 36
Word address 37
Word address 38
Link_Enh byte 0
MiniROM_Addr
GUIDHi byte 0
SysCtrl byte 2
SysCtrl byte 3
Generalcontrol
Word address 39
Word address 40
Word address 41
GUIDHi byte 1
GUIDHi byte 2
GP event enable
GP output
Word address 42
Word address 43
Word address 8
Word address 9
GUIDHi byte 3
GUIDLo byte 0
GUIDLo byte 1
Word address 10
Word address 11
Word address 12
Word address 13
Word address 14
MF route byte 0
MF route byte 1
MF route byte 2
Word address 44
Word address 45
Word address 46
GUIDLo byte 2
GUIDLo byte 3
CheckSum
MF route byte 3
CardControl
Word address 47
Word address 48
Word address 49
Device control
Word address 15
Word address 16
Word address 17
Word address 18
Link_Enh byte 1
PCI misc byte 0
PCI misc byte 1
Diagnostic
PMC byte 1
Word address 50
Word address 51
Word address 52
ExCA ID and rev
...
RSVD
AVAIL
Figure 8. Serial ROM Data Format
The flag byte at word address 32 indicates to the PCI4450 whether or not the PC Card controller functions loads
the data from word address range 33–52. A flag byte set to 8’hFF indicates to stop loading the serial ROM data
for functions 0 and 1, but is independent of the function 2 1394 Open HCI controller load from word address
range 0–18.
An additional change in the serial ROM behavior with respect to Open HCI GUIDROM register access is the
MiniROM_Addr. The MiniROM_Addr field in the ROM data is loaded from byte location 6 (EEPROM word
address 6) and indicates to function 2 where to begin accessing the serial ROM via the GUID ROM register.
The GUIDROM.addrReset bit function changes slightly to reset serial ROM access to the byte location
indicated by MiniROM_Addr. A MiniROM_Addr value of zero provides identical operation as the OHCI-Lynx.
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PC Card and OHCI Controller
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PC Card applications overview
This section describes the PC Card interfaces of the PCI4450. A discussion on PC Card recognition details the
card interrogation procedure. This section discusses the card powering procedure, including the protocol of the
2
P C power switch interface. The internal ZV buffering provided by the PCI4450 and programming model is
detailed in this section. Also, standard PC Card register models are described, as well as a brief discussion of
the PC Card software protocol layers.
PC Card insertion/removal and recognition
The 1995 PC Card Standard addresses the card detection and recognition process through an interrogation
procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this
interrogation, card voltage requirements and interface (16-bit vs. CardBus) are determined.
The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card
designer connects these four pins in a certain configuration depending on the type of card and the supply
voltage. The encoding scheme for this, defined in the 1997 PC Card Standard, is shown in Table 18.
Table 18. PC Card – Card Detect and Voltage Sense Connections
CD2//CCD2
Ground
CD1//CCD1
Ground
VS2//CVS2
Open
VS1//CVS1
Open
Key
5 V
5 V
Interface
Voltage
5 V
16-bit PC Card
16-bit PC Card
Ground
Ground
Open
Ground
5 V and 3.3 V
5 V, 3.3 V, and
X.X V
Ground
Ground
Ground
Ground
5 V
16-bit PC Card
Ground
Ground
Ground
Connect to CVS1
Ground
Open
Open
Ground
Connect to CCD1
Ground
LV
LV
LV
LV
16-bit PC Card
CardBus PC Card
16-bit PC Card
3.3 V
3.3 V
Ground
Ground
3.3 V and X.X V
3.3 V and X.X V
Connect to CVS2
Ground
Connect to CCD2
Ground
CardBus PC Card
3.3 V, X.X V, and
Y.Y V
Connect to CVS1
Ground
Ground
Connect to CCD2
LV
CardBus PC Card
Ground
Connect to CVS2
Ground
Ground
Ground
Ground
Connect to CCD2
Connect to CCD1
Open
Open
Open
LV
LV
LV
LV
16-bit PC Card
CardBus PC Card
CardBus PC Card
CardBus PC Card
Reserved
Y.Y V
Y.Y V
Connect to CVS2
Ground
Open
X.X V and Y.Y V
Y.Y V
Connect to CVS1
Ground
Connect to CCD2
Connect to CCD1
Ground
Connect to CVS1
Connect to CVS2
Ground
Ground
Connect to CCD1
Reserved
2
P C power switch interface (TPS2202A/2206)
2
A power switch with a PCMCIA-to-peripheral control (P C) interface is required for the PC Card powering
2
interface. The TI TPS2206 (or TPS2202A) Dual-Slot PC Card Power-Interface Switch provides the P C
interface to the CLOCK, DATA, and LATCH terminals of the PCI4450. Figure 9 shows the terminal assignments
of the TPS2206. Figure 10 illustrates a typical application where the PCI4450 represents the PCMCIA
controller.
There are two ways to provide a clock source to the power switch interface. The first method is to provide an
external clock source such as a 32 kHz real time clock to the CLOCK terminal. The second method is to use
the internal ring oscillator. If the internal ring oscillator is used, then the PCI4450 provides its own clock source
for the PC Card interrogation logic and the power switch interface. The mode of operation is determined by the
setting of bit 27 of the system control register (PCI offset 80h). This bit is encoded as follows:
0 = CLOCK terminal (terminal U12) is an input (default).
1 = CLOCK terminal is an output that utilizes the internal oscillator.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
A 43 kW pulldown resistor should be tied to the CLOCK pin.
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
5V
5V
NC
NC
NC
NC
NC
12V
BVPP
BVCC
BVCC
BVCC
NC
OC
3.3V
3.3V
2
3
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
4
5
6
7
8
9
10
11
12
13
14
15
NC
RESET
3.3V
NC – No internal connection
Figure 9. TPS2206 Terminal Assignments
Power Supply
PC Card A
TPS2206
V
12 V
5 V
12 V
5 V
AVPP
PP1
V
V
V
PP2
3.3 V
3.3 V
AVCC
AVCC
AVCC
CC
CC
Supervisor
RESET
PC Card B
V
PP1
BVPP
V
V
V
PP2
BVCC
BVCC
BVCC
CC
3
CC
PCI4450
Serial I/F
PC Card Interface (68 pins/socket)
Figure 10. TPS2206 Typical Application
zoomed video support
The zoomed video (ZV) port on the PCI4450 provides an internally buffered 16-bit ZV PC Card data path. This
internal routing is programmed through the multimedia control register. Figure 10 summarizes the zoomed
video subsystem implemented in the PCI4450, and details the bit functions found in the multimedia control
register.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
An output port (PORTSEL) is always selected. The PCI4450 defaults to socket 0 (see the multimedia control
register). When ZVOUTEN is enabled, the zoomed video output terminals are enabled and allow the PCI4450
to route the zoomed video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is enabled
in the multimedia control register. If the PORTSEL maps to a card port that is disabled (ZVEN =0 or ZVEN1
= 0), then the zoomed video port is driven low (i.e., no data is transmitted).
Zoomed VideoSubsystem
Card Output
EnableLogic
ZVEN0
ZVOUTEN
PC Card
I/F
PC Card
Socket 0
ZVSTAT†
23
VGA
19 VideoSignals
PORTSEL
PC Card
Socket 1
PC Card
I/F
Audio
Codec
4 Audio Signals
ZVEN1
Card Output
EnableLogic
†
ZVSTAT must be enabled through the GPIO Control Register.
Figure 11. Zoomed Video Subsystem
zoomed video auto detect
Zoomed video auto detect, when enabled, allows the PCI4450 to automatically detect zoomed video data by
sensing the pixel clock from each socket and/or from a third zoomed video source that may exist on the
motherboard. The PCI4450 automatically switches the internal zoomed video MUX to route the zoomed video
stream to the PCI4450’s zoomed video output port. This eliminates the need for software to switch the internal
MUX using the multimedia control register (PCI offset 84h, bits 6 and 7).
The PCI4450 can be programmed to switch a third zoomed video source by programming MFUNC2 or
MFUNC3 as a zoomed video pixel clock sense pin and connecting this pin to the pixel clock of the third zoomed
video source. ZVSTAT may then be programmed onto MFUNC4, MFUNC1, or MFUNC0 and this signal may
switch the zoomed video buffers from the third zoomed video source. To account for the possibility of several
zoomed video sources being enabled at the same time, a programmable priority scheme may be enabled.
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Zoomed VideoSubsystem
Card Output
EnableLogic
3rd Zoomed VideoSource
ZVEN0
Pixel Clock Sense
Programmedon
23
MFUNC2 or MFUNC3
PC Card
I/F
PC Card
Socket 0
Buffers
Enable
23
ZVSTAT
Pixel Clock Sense
23
23
23
23
Auto Z/V Arbiter
and Buffer
VGA
19 VideoSignals
ZV Data
Pixel Clock Sense
23
PC Card
Socket 1
Audio
Codec
PC Card
I/F
4 Audio Signals
ZVEN1
Card Output
EnableLogic
Figure 12. Zoomed Video with Auto Detect Enabled
The PCI4450 defaults with zoomed video auto-detect disabled so that it will function exactly like the PCI1250A
and PCI1450. To enable zoomed video auto-detect and the programmable priority scheme, the following bits
must be set:
D
D
Multimedia control register (PCI offset 84h) bit 5: Writing a 1b enables zoomed video auto-detect
Multimedia control register (PCI offset 84h) bits 4–2: Set the programmable priority scheme
000 = Slot A, Slot B, External Source
001 = Slot A, External Source, Slot B
010 = Slot B, Slot A, External Source
011 = Slot B, External Source, Slot A
100 = External Source, Slot A, Slot B
101 = External Source, Slot B, Slot A
110 = External Source, Slot B, Slot A
111 = Reserved
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PC Card and OHCI Controller
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If it is desired to switch a third zoomed video source, then the following bits must also be set:
D
D
MFUNC routing register (PCI offset 8Ch), bits 14–12 or 10–8: Write 111b to program MFUNC3 or MFUNC2
as a pixel clock input pin.
MFUNC routing register (PCI ofset 8Ch), bits 18–16, 6–4, or 2–0: Write 111b to program MFUNC4,
MFUNC1, or MFUNC0 pin.
ultra zoomed video
Ultra zoomed video is an enhancement to the PCI4450’s DMA engine and is intended to improve the 16-bit
bandwidth for MPEG I and MPEG II decoder PC Cards. This enhancement allows the 4450 to fetch 32 bits of
data from memory versus the 11XX/12XX 16-bit fetch capability. This enhancement allows a higher sustained
throughput to the 16-bit PC Card, because the 4450 prefetches an extra 16 bits (32 bits total) during each PCI
read transaction. If the PCI Bus becomes busy, then the 4450 has an extra 16 bits of data to perform
back-to-back 16-bit transactions to the PC Card before having to fetch more data. This feature is built into the
DMA engine and software is not required to enable this enhancement.
NOTE:The 11XX and 12XX series CardBus controllers have enough 16-bit bandwidth to support
MPEG II PC Card decoders. But it was decided to improve the bandwidth even more in the 14XX
series CardBus controllers.
D3_STAT pin
Additional functionality added for the 4450 versus the 1250A/1251 series is the D3_STAT (D3 status) pin. This
pin is asserted under the following two conditions (both conditions must be true before D3_STAT is asserted):
D
D
Function 0 and Function 1 are placed in D3
PME is enabled on either function
The intent of including this feature in the PCI4450 is to use this pin to switch an external V /V
switch. This
CC AUX
feature can be programmed on MFUNC7, MFUNC6, MFUNC2, or MFUNC1 by writing 100b to the appropriate
multifunction routing status register bits (PCI offset 8Ch).
internal ring oscillator
The internal ring oscillator provides an internal clock source for the PCI4450 so that neither the PCI clock nor
an external clock is required in order for the PCI4450 to power down a socket or interrogate a PC Card. This
internal oscillator operates nominally at 16 kHz and can be enabled by setting bit 27 of the system control
register (PCI offset 80h) to a 1b. This function is disabled by default.
SPKROUT usage
The SPKROUT signal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card
is configured for I/O mode, the BVD2 pin becomes SPKR. This terminal, also used in CardBus applications,
is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI4450. The CardBus CAUDIO
signal also can pass a single amplitude, binary waveform. The binary audio signals from the two PC Card
sockets are XOR’ed in the PCI4450 to produce SPKROUT. Figure 13 illustrates the SPKROUT connection.
Bit 1, Card Control Register (offset 91h)
Card A SPKROUT Enable
Card A SPKR
SPKROUT
Speaker
Driver
Bit 1, Card Control Register (offset 91h)
Card B SPKROUT Enable
Card B SPKR
Card A SPKROUT Enable
Card B SPKROUT Enable
Figure 13. SPKROUT Connection to Speaker Driver
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
The SPKROUT signal is typically driven only by PC modem cards. To verify the SPKROUT on the PCI4450,
a sample circuit was constructed, and this simplified schematic is provided below. The PCI1130/1131 required
a pullup resistor on the SUSPEND/SPKROUT terminal. Since the PCI4450 does not multiplex any other
function on SPKROUT, this terminal does not require a pullup resistor.
V
CC
V
CC
SPKROUT
6
3
7
2
Speaker
1
8
+
–
4
LM386
Figure 14. Simplified Test Schematic
LED socket activity indicators
The socket activity LEDs indicate when an access is occurring to a PC Card. The LED signals are
programmablevia the MFUNC register. When configured for LED outputs, these terminals output an active high
signal to indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1
(card B) activity.
The active-high LED signal is driven for 64 ms durations. When the LED is not being driven high, then it is driven
to a low state. Either of the two circuits illustrated in Figure 15 can be implemented to provide the LED signaling,
and it is left for the board designer to implement the circuit to best fit the application.
CurrentLimiting
R ≈ 500 Ω
PCI4450
LED
CurrentLimiting
R ≈ 500 Ω
Application-
SpecificDelay
PCI4450
LED
Figure 15. Two Sample LED Circuits
As indicated, the LED signals are driven for 64 ms, and this is accomplished by a counter circuit. To avoid the
possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when
either the SUSPEND signal is asserted or when the PCI clock is to be stopped per the CLKRUN protocol.
Furthermore, if any additional socket activity occurs during this counter cycle, then the counter is reset and the
LED signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signals will
remain driven.
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PC Card and OHCI Controller
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PC Card 16 DMA support
The PCI4450 supports both PC/PCI (centralized) DMA and a distributed DMA slave engine for 16-bit PC Card
DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the
slave DDMA engine. Table 19 provides the DDMA register configuration.
Table 19. Distributed DMA Registers
DMA BASE
ADDRESS OFFSET
TYPE
REGISTER NAME
R
W
R
Currentaddress
Base address
Currentcount
Base count
00h
Reserved
Reserved
Page
04h
08h
0Ch
Reserved
Reserved
Reserved
W
R
N/A
Mode
N/A
Request
N/A
Status
W
R
Command
Multichannel
Mask
Reserved
W
MasterClear
CardBus socket register
The PCI4450 contains all registers for compatibility with the latest PCI to PCMCIA CardBus Bridge
Specification. These registers exist as the CardBus socket registers, and are listed in Table 20.
Table 20. CardBus Socket Registers
REGISTER NAME
Socket event
OFFSET
00h
Socket mask
04h
Socket present state
Socket force event
Socket control
08h
0Ch
10h
Reserved
14h
Reserved
18h
Reserved
1Ch
20h
Socketpowermanagement
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
programmable interrupt subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from
the PCI4450. The PCI4450 provides several interrupt signaling schemes to accommodate the needs of a
variety of platforms. The different mechanisms for dealing with interrupts in this device are based upon various
specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card
functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions.
The PCI4450 is therefore backward compatible with existing interrupt control register definitions, and new
registers have been defined where required.
The PCI4450 detects PC Card interrupts and events at the PC Card interface and notifies the host controller
via one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI4450, PC Card
interrupts are classified as either card status change (CSC) or as functional interrupts.
The method by which any type of PCI4450 interrupt is communicated to the host interrupt controller varies from
system to system. The PCI4450 offers system designers the choice of using parallel PCI interrupt signaling or
the serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination
with serialized IRQs via the multifunction routing register at offset 8Ch.
PC Card functional and card status change interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service. They
are indicated by asserting specially defined signals on the PC Card interface. Functional interrupts are
generated by 16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC) type interrupts, defined as events at the PC Card interface which are detected by
the PCI4450, may warrant notification of host card and socket services softwareforservice. CSCeventsinclude
both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.
Table 21 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functionalinterrupt sources are dependent upon the type of card inserted in the PC Card socket. The threetypes
of cards that may be inserted into any PC Card socket are: 16-bit memory card, 16-bit I/O card, and CardBus
cards. Functional interrupt events are valid only for 16-bit I/O and CardBus cards, that is, the functional
interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal type CSC interrupts
are independent of the card type.
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Table 21. PC Card Interrupt Events and Description
Card Type
Event
Type
Signal
Description
BVD1 (STSCHG) //
CSTSCHG
A transition on the BVD1 signal indicates a change
in the PC Card battery conditions.
CSC
Batteryconditions
(BVD1, BVD2)
A transition on the BVD2 signal indicates a change
in the PC Card battery conditions.
CSC
CSC
BVD2 (SPKR) // CAUDIO
READY (IREQ) // CINT
16-bitMemory
AtransitionontheREADYsignalindicatesachange
in the ability of the memory PC Card to accept or
providedata.
Wait states
(READY)
Change in card status
(STSCHG)
BVD1 (STSCHG) //
CSTSCHG
The assertion of the STSCHG signal indicates a
status change on the PC Card.
CSC
Functional
CSC
16-bit I/O
CardBus
Interruptrequest
(IREQ)
The assertion of the IREQ signal indicates an
interruptrequest from the PC Card.
READY (IREQ) // CINT
Change in card status
(CSTSCHG)
BVD1 (STSCHG) //
CSTSCHG
The assertion of the CSTSCHG signal indicates a
status change on the PC Card.
Interruptrequest
(CINT)
The assertion of the CINT signal indicates an
interruptrequest from the PC Card.
Functional
CSC
READY (IREQ) // CINT
N/A
AninterruptisgeneratedwhenaPCCardpower-up
cycle has completed.
Power cycle complete
A transition on either the CD1//CCD1 signal or the
CD2//CCD2signalindicatesaninsertionorremoval
of a 16-bit // CardBus PC Card.
Card insertion or
removal
CD1 // CCD1,
CD2 // CCD2
CSC
CSC
All PC Cards
AninterruptisgeneratedwhenaPCCardpower-up
cycle has completed.
Power cycle complete
N/A
The signal naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as
well as CardBus. For example, the READY(IREQ)//CINT signal includes the READY signal for 16-bit memory
cards, the IREQ signal for 16-bit I/O cards, and the CINT signal for CardBus cards. The 16-bit memory card
signal name is first, with the I/O card signal name second enclosed in parentheses. The CardBus signal name
follows after a forward double slash (//).
The PC Card standard describes the power-up sequence that must be followed by the PCI4450 when an
insertion event occurs and the host requests that the socket V and V be powered. Upon completion of this
CC
PP
power-up sequence, the PCI4450 interrupt scheme may be used to notify the host system, as in indicated in
Table 21, denoted by the power cycle complete event. This interrupt source is considered a PCI4450 internal
event because it does not depend on a signal change at the PC Card interface, but rather the completion of
applying power to the socket.
interrupt masks and flags
Host software may individually mask, or disable, most of the potential interrupt sources listed in Table 22 by
setting the appropriate bits in the PCI4450. By individually masking the interrupt sources listed in these tables,
software can control which events will cause a PCI4450 interrupt. Host software has some control over which
system interrupt the PCI4450 will assert by programming the appropriate routing registers. The PCI4450 allows
host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt
routing is somewhat specific to the interrupt signaling method used. This will be discussed in more detail in the
following sections.
When an interrupt is signaled by the PCI4450, the interrupt service routine must be able to discern which of
the events in Table 22 caused the interrupt. Internal registers in the PCI4450 provide flags which report which
of the interrupt sources was the cause of an interrupt. By reading these status bits, the interrupt service routine
can determine which action is to be taken.
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Table 22 details the registers and bits associated with masking and reporting potential interrupts. All interrupts
may be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types
of interrupts.
Table 22. PCI4450 Interrupt Masks and Flags Registers
Card Type
Event
Mask
Flag
Batteryconditions
(BVD1, BVD2)
ExCA Offset05h/45h/805h
Bits 1 & 0
ExCA Offset04h/44h/804h
Bits 1 & 0
16-bitMemory
Wait states
(READY)
ExCA Offset05h/45h/805h
Bit 2
ExCA Offset04h/44h/804h
Bit 2
Change in card status
(STSCHG)
ExCA Offset 05h/45h/805h
Bit 0
ExCA Offset04h/44h/804h
Bit 0
16-bit I/O
Interruptrequest
(IREQ)
PCI Configuration Offset 91h
Bit 0
Alwaysenabled
ExCA Offset 05h/45h/805h
Bit 3
ExCA Offset04h/44h/804h
Bit 3
All 16-bit PC Cards
Power cycle complete
Change in card status
(CSTSCHG)
Socket mask register
Bit 0
Socket event register
Bit 0
Interruptrequest
(CINT)
PCI Configuration Offset 91h
Bit 0
Alwaysenabled
CardBus
Socket mask register
Bit 3
Socket event register
Bit 3
Power cycle complete
Socket mask register
Bits 2 & 1
Socket event register
Bits 2 & 1
Card insertion or removal
There is no mask bit to stop the PCI4450 from passing PC Card functional interrupts through to the appropriate
interrupt scheme. Functional interrupts should not be fired until the PC Card is initialized and powered.
There are various methods of clearing the interrupt flag bits listed in Table 22. The flag bits in the ExCA registers
(16-bit PC Card related interrupt flags) may be cleared by two different methods. One method is an explicit write
of 1 to the flag bit to clear, and the other is a reading of the flag bit register. The selection of flag bit clearing
is made by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the flag cleared on
read method.
The CardBus related interrupt flags can only be cleared by an explicit write of 1 to the interrupt flag in the socket
event register. Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software should not program the chip through both register sets when a CardBus card is functioning.
using parallel PCI interrupts
Parallel PCI interrupts are available when in pure parallel PCI interrupt mode and are routed on
MFUNC0–MFUNC2. The PCI interrupt signaling is dependent upon the interrupt mode and is summarized in
Table 23. The interrupt mode is selected in the device control register (92h).
Table 23. Interrupt Pin Register Cross Reference
INTPIN
Function 0
INTPIN
Function 1
InterruptSignaling Mode
Parallel PCI interrupts only
Reserved
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x02 (INTB)
0x02 (INTB)
0x01 (INTA)
0x02 (INTB)
IRQ serialized (IRQSER) & parallel PCI interrupts
IRQ & PCI serialized (IRQSER) interrupts (default)
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power management overview
In addition to the low-power CMOS technology process used for the PCI4450, various features are designed
into the device to allow implementation of popular power saving techniques. These features and techniques
are discussed in this section.
CLKRUN protocol
CLKRUN is the primary method of power management on the PCI bus side of the PCI4450. Since some
chipsets do not implement CLKRUN, this is not always available to the system designer, and alternate power
savings features are provided.
If CLKRUN is not implemented, then the CLKRUN pin should be tied low. CLKRUN is enabled by default via
bit 1 (KEEPCLK) in the system control register (80h).
CardBus PC Card power management
The PCI4450 implements its own card power management engine that can turn off the CCLK to a socket when
there is no activity to the CardBus PC Card. The CCLK can also be configured as divide by 16 instead of
stopped. The CLKRUN protocol is followed on the CardBus interface to control this clock management.
PCI bus power management
The PCI Bus Power Management Interface Specification (PCIPM) establishes the infrastructure required to let
the operating system control the power of PCI functions. This is done by defining a standard PCI interface and
operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be
assignedone of four software visible power management states, which result in varying levels of power savings.
The four power management states of PCI functions are: D0 - Fully On state, D1 and D2 - intermediate states,
and D3 - Off state. Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are
derived from the device power state of the upstream bridge device.
For the operating system to manage the device power states on the PCI bus, the PCI function should support
four power management operations. The four operations are: capabilities reporting; power status reporting;
setting the power state; and system wake-up. The operating system identifies the capabilities of the PCI
function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1b in bit 4 of
the PCI status register (PCI offset 06h). When software determines that the device has a capabilities list by
seeing that bit 4 of the PCI status register is set, it will read the capability pointer register at PCI offset 14h. This
value in the register points the location in PCI configuration space of the capabilities linked list.
The first byte of each capability register block is required to be a unique ID of that capability. PCI power
management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of
capabilities. If there are no more items in the list, then the next item pointer should be set to 0. The registers
following the next item pointer are specific to the function’s capability. The PCIPM capability implements the
following register block:
Power Management Register Block
Powermanagementcapabilities(PMC)
Next item pointer
CapabilityID
Offset = 0
Offset = 4
PMCSRbridge
Data
Power management control status (CSR)
supportextensions
The power management capabilities (PMC) register is a static read-only register that provides information on
the capabilities of the function, related to power management. The PMCSR register enables control of power
management states and enables/monitors power management events. The data register is an optional register
that provides a mechanism for state-dependent power measurements such as power consumed or heat
dissipation.
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CardBus device class power management
The PCI Bus Interface Specification for PCI-to-CardBus Bridges was approved by PCMCIA in December of
1997. This specification follows the device and bus state definitions provided in the PCI Bus Power
Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue
addressed in the PCI Bus Interface Specification for PCI-to-CardBus Bridges is wake-up from D3 or D3
hot
cold
without losing wake-up context (also called PME context).
The specific issues addressed by the PCI Bus Interface Specification for PCI-to-CardBus Bridges for D3 wake
up are as follows:
D
D
Preservation of device context: The PCI Power Management Specification version 1.0 states that PRST
must be asserted when transitioning from D3 to D0. Some method to preserve wake-up context must
cold
be implemented so that PRST does not clear the PME context registers.
Power source in D3 if wake-up support is required from this state.
cold
The Texas Instruments PCI4450 addresses these D3 wake-up issues in the following manner:
D
Preservation of device context: When PRST is asserted, bits required to preserve PME context are not
cleared. To clear all bits in the PCI4450, another reset pin is defined: G_RST (global reset). G_RST is
normally only asserted during the initial power-on sequence. After the initial boot, PRSTshould be asserted
so that PME context is retained for D3-to-D0 transitions. Bits cleared by G_RST, but not cleared by PRST
(if the PME enable bit is set), are referred to as PME context bits. Please refer to the master list of PME
context bits in the next section.
D
Power source in D3
auxiliary power source must be switched to the PCI4450 V
break type of switch, so that V
if wake-up support is required from this state. Since V
is removed in D3
, an
cold
CC
cold
pins. This switch should be a make before
CC
to the PCI4450 is not interrupted.
CC
master list of PME context bits and global reset only bits
PME context bit means that the bit is cleared only by the assertion of G_RST when the PME enable bit is set
(PCI offset A4h, bit 8). If PME is not enabled, then these bits are cleared when either PRST or G_RST is
asserted.
Global reset only bits, as the name implies, are only cleared by G_RST. These bits are never cleared by PRST
regardless of the setting of the PME enable bit. (PCI offset A4h, bit 8). The G_RST signal is gated only by the
SUSPEND signal. This means that assertion of SUSPEND blocks the G_RST signal internally, thus preserving
all register contents.
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Global reset only bits:
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Subsystem ID/subsystem vendor ID (PCI offset 40h): bits 31–0
PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31–1
System control register (PCI offset 80h): bits 31–29, 27–24, 22–14, 6–3, 1, 0
Multimedia control register (PCI offset 84h): bits 7–0
General status register (PCI offset 85h): bits 2–0
General-purpose event status register (PCI offset 88h): bits 7, 6, 3–0
General-purpose event enable register (PCI offset 89h): bits 7, 6, 3–0
General-purpose input register (PCI offset 8Ah): bits 3–0
General-purpose output register (PCI offset 8Bh): bits 3–0
MFUNC routing register (PCI offset 8Ch): bits 31–0
Retry status register (PCI offset 90h): bits 7–1
Card control register (PCI offset 91h): bits 7, 6, 2, 1, 0
Device control register (PCI offset 92h): bits 7–0
Diagnostic register (PCI offset 93h): bits 7–0
Socket DMA register 0 (PCI offset 94h): bits 1–0
Socket DMA register 1 (PCI offset 98h): bits 15–0
GPE control/status register (PCI offset A8h): bits 10, 9, 8, 2, 1, 0
PME context bits
D
D
D
D
D
D
D
D
D
D
Bridge control register (PCI offset 3Eh): bit 6
Power management capabilities register (PCI offset A2h): bit 15
Power management control/status register (PCI offset A4h): bits 15, 8
ExCA power control register (ExCA 802h/842h): bits 7, 4, 3, 1, 0
ExCA interrupt and general control (ExCA 803h/843h): bit 6, 5
ExCA card status change register (ExCA 804h/844h): bits 3–0
ExCA card status change interrupt register (ExCA 805h/845h): bits 3–0
CardBus socket event register (CardBus offset 00h): bits 3–0
CardBus socket mask register (CardBus offset 04h): bits 3–0
CardBus socket control register (CardBus offset 10h): bits 6, 5, 4, 2, 1, 0
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system diagram implementing CardBus device class power management
PCI Bus
Real Time
Clock‡
South Bridge
PRST
G_RST†
Clock
CLKRUN
TPS2206
PCI4450
2
Power
Switch
Embedded
Controller
PME
Vcc
SystemVcc
PC Card
Socket A
68
68
D3
Status
V
aux
PC Card
Socket B
Makebefore
breakswitch
†
‡
The system connection to G_RST is implementation specific. G_RST should be applied whenever V is applied to the PCI4450. PRST should
cc
be applied for subsequent warm resets.
Not required if internal oscillator is used.
Figure 16. System Diagram Implementing CardBus Device Class Power Management
suspend mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the G_RST
(global reset) signal from the PCI4450. Besides gating PRST and G_RST, SUSPEND also gates PCLK inside
the PCI4450 in order to minimize power consumption.
Gating PCLK does not create any issues with respect to the power switch interface in the PCI4450. This is
because the PCI4450 does not depend on the PCI clock to clock the power switch interface. There are two
methods to clock the power switch interface in the PCI4450:
D
D
Use an external clock to the PCI4450 CLOCK pin
Use the internal oscillator
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be
passed to the host system without a PCI clock. However, if card status change interrupts are routed over the
serial interrupt stream, then the PCI clock will have to be restarted in order to pass the interrupt, because neither
the internal oscillator nor an external clock is routed to the serial interrupt state machine.
PRST
G_RST
PCI4450
Core
SUSPEND
GNT
PCLK
Figure 17. SUSPEND Functional Illustration
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requirements for SUSPEND
A requirement for implementing suspend mode is that the PCI bus must not be parked on the PCI4450 when
SUSPEND is asserted. The PCI4450 responds to SUSPEND being asserted by placing the REQ pin in a high
impedance state. The PCI4450 will also gate the internal clock and reset.
The GPIOs, MFUNC signals, and RI_OUT signals are all active during SUSPEND, unless they are disabled
in the appropriate PCI4450 registers.
ring indicate
The RI_OUT output is an important feature used in legacy power management. It is used so that a system can
go into a suspended mode and wake up on modem rings and other card events. The RI_OUT signal on the
PCI4450 may be asserted under any of the following conditions:
D
D
D
A 16-bit PC Card modem in a powered socket asserts RI to indicate an incoming call to the system.
A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.
A card status change (CSC) event, such as insertion/removal of cards, battery voltage levels, occurs.
A CSTSCHG signal from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These
two RI_OUT events are enabled separately. The following figure details various enable bits for the PCI4450
RI_OUT function; however, it does not illustrate the masking of CSC events. See interrupt masks and flags for
a detailed description of CSC interrupt masks and flags.
RI_OUT is multiplexed on the same pin with PME. The default is for RI_OUT to be signaled on this pin. In PCI
power managed systems, the PME signal should be enabled by setting bit 0 (RI_OUT/PME) in the system
control register (80h) and clearing bit 7 (RIENB) in the card control register (91h).
RI_OUTFunction
PC Card
Socket 0
Card
I/F
16-bit
Card
Bus
CSC
RI
CBWAKE
RIENB
RICSC(A)
RICSC(B)
RI_OUT
CSC
CBWAKE
RI
PC Card
Socket 1
Card
I/F
16-bIt
Card
Bus
Figure 18. RI_OUT Functional Illustration
Routing of CSC events to the RI_OUT signal, enabled on a per socket basis, is programmed by the RICSC bit
in the card control register. This bit is socket dependent (not shared), as illustrated in Figure 18.
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The RI signal from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the ExCA interrupt
and general control register. This is programmed on a per socket basis, and is only applicable when a 16-bit
card is powered in the socket.
The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The
mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers.
PC CARD CONTROLLER PROGRAMMING MODEL
This section describes the PCI4450 PCI configuration registers that make up the 256-byte PCI configuration
header for each PCI4450 function. As noted below, some bits are global in nature and should be accessed only
through function 0.
Registers containing one or more global bits are denoted by a “§.”
Any bit followed by a “†” is not cleared by the assertion of PRST (refer to CardBus device class power
management for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are only cleared
by G_RST. If PME is not enabled, then these bits are cleared by G_RST or PRST. These bits are sometimes
referred to as PME context bits and are implemented to allow PME context to be preserved when transitioning
from D3
or D3
to D0. If the PME context PRST functionality is not desired, then the PRST and G_RST
hot
cold
signals should be tied together.
If a bit is followed by a “‡”, then this bit is only cleared by G_RST in all cases (not conditional on PME being
enabled). These bits are intended to maintain device context such as interrupt routing and MFUNC
programming during “warm” resets.
PCI configuration registers (functions 0 and 1)
The PCI4450 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1.
The configuration header, compliant with the PCI Specification as a CardBus bridge header, is PC97/PC98
compliant as well. Table 24 illustrates the PCI configuration header, which includes both the predefined portion
of the configuration space and the user definable registers.
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Table 24. Functions 0 and 1 PCI Configuration Register Map
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
Command
04h
Class code
Header type
CardBus socket registers/ExCA base address
Secondary status Reserved
CardBus latency timer Subordinatebusnumber CardBus bus number
CardBus memory base register 0
Revision ID
08h
BIST
Latencytimer
Cache line size
0Ch
10h
Capabilitypointer
PCI bus number
14h
18h
1Ch
20h
CardBus memory limit register 0
CardBus memory base register 1
CardBus memory limit register 1
CardBus I/O base register 0
CardBus I/O limit register 0
CardBus I/O base register 1
CardBus I/O limit register 1
24h
28h
2Ch
30h
34h
38h
Bridge control †
Subsystem ID ‡
Interruptpin
Interruptline
3Ch
40h
Subsystem vendor ID ‡
PC Card 16-bit I/F legacy mode base address ‡
44h
Reserved
48h–7Fh
80h
System control ‡
Reserved
Reserved
General status †
Multimediacontrol‡
GPE status ‡
84h
GP0 control ‡
GP1 control ‡
GPE enable ‡
88h
Multifunctionrouting†
8Ch
90h
Diagnostic ‡
Device control ‡
Card control ‡
Retry status ‡
Socket DMA register 0 ‡
94h
Socket DMA register 1 ‡
Reserved
98h
9Ch
A0h
Powermanagementcapabilities†
PMCSR bridge support
extensions
Next pointer item
CapabilityID
Data (Reserved)
Powermanagementcontrol/status†
GPE control/status ‡
A4h
A8h
Reserved
†
‡
OneormorebitsintheregisterarePMEcontextbitsandcanonlybeclearedbytheassertionofG_RSTwhenPMEisenabled.IfPMEisnotenabled,
then these bits are cleared by the assertion of PRST or G_RST.
One or more bits in this register are only cleared by the assertion G_RST.
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vendor ID register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Type:
Vendor ID
Read-only
Offset:
Default:
00h (Functions 0, 1)
104Ch
Description: This 16-bit register contains a value allocated by the PCI SIG that identifies the manufacturer
of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch.
device ID register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID
R
1
R
0
R
1
R
0
R
1
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Device ID
Read-only
Offset:
Default:
02h (Functions 0, 1)
AC40h
Description: This 16-bit register contains a value assigned to the PCI4450 by Texas Instruments. The
device identification for the PCI4450 is AC40.
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command register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Command
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
0
Register:
Type:
Command
Read-only, Read/Write
Offset:
Default:
04h
0000h
Description: The command register provides control over the PCI4450 interface to the PCI bus. All bit
functions adhere to the definitions in the PCI Local Bus Specification, see Table 25. None of
the bit functions in this register are shared between the two PCI4450 PCI functions. Two
command registers exist in the PCI4450, one for each function. Software manipulates the two
PCI4450 functions as separate entities when enabling functionality through the command
register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR
between the two functions, and these control bits appear separate per function to software.
Table 25. PCI Command Register Description
BIT
TYPE
FUNCTION
15–10
R
Reserved. These bits return 0s when read. Writes have no effect.
Fast back-to-back enable. The PCI4450 will not generate fast back-to-back transactions; therefore, this bit is read-only.
This bit returns a 0 when read.
9
8
R
Systemerror (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR can be asserted
after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set for the PCI4450 to report address
parity errors.
R/W
0 = Disables the SERR output driver (default).
1 = Enables the SERR output driver.
Address/datasteppingcontrol. The PCI4450 does not support address/data stepping, and this bit is hardwired to 0. Writes
to this bit have no effect.
7
6
R
Parityerrorresponseenable.ThisbitcontrolsthePCI4450’sresponsetoparityerrorsthroughthePERRsignal.Dataparity
errors are indicated by asserting PERR, while address parity errors are indicated by asserting SERR.
0 = PCI4450 ignores detected parity error (default).
R/W
1 = PCI4450 responds to detected parity errors.
VGApalettesnoop.Whensetto1,palettesnoopingisenabled(i.e.,thePCI4450doesnotrespondtopaletteregisterwrites
and snoops the data). When the bit is 0, the PCI4450 will treat all palette accesses like all other accesses.
5
4
3
R/W
R
Memory write and invalidate enable. This bit controls whether a PCI initiator device can generate memory write and
invalidatecommands. The PCI4450 controller does not support memory write and invalidate commands, it uses memory
write commands instead; therefore, this bit is hardwired to 0. This bit returns 0 when read. Writes to this bit have no effect.
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI4450 does not respond
tospecialcycleoperations;therefore, thisbitishardwiredto0. Thisbitreturns0whenread. Writestothisbithavenoeffect.
R
Bus master control. This bit controls whether or not the PCI4450 can act as a PCI bus initiator (master). The PCI4450 can
take control of the PCI bus only when this bit is set.
2
R/W
0 = Disables the PCI4450’s ability to generate PCI bus accesses (default).
1 = Enables the PCI4450’s ability to generate PCI bus accesses.
Memory space enable. This bit controls whether or not the PCI4450 may claim cycles in PCI memory space.
0 = Disables the PCI4450’s response to memory space accesses (default).
1
0
R/W
R/W
1 = Enables the PCI4450’s response to memory space accesses.
I/O space control. This bit controls whether or not the PCI4450 may claim cycles in PCI I/O space.
0 = Disables the PCI4450 from responding to I/O space accesses (default).
1 = Enables the PCI4450 to respond to I/O space accesses.
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
status register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Status
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
1
R/W
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Status
Read-only, Read/Write
06h (Functions 0, 1)
0210h
Description: The status register provides device information to the host system. Bits in this register may be
read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0
written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Bus
Specification, as seen in the bit descriptions. PCI bus status is shown through each function.
Table 26. Status Register Description
BIT
TYPE
FUNCTION
PAR_ERR. Detected parity error. This bit is set when a parity error is detected, either address or data parity errors. Write
a 1 to clear this bit.
15
R/W
SYS_ERR. Signaled system error. This bit is set when SERR is enabled and the PCI4450 signaled a system error to the
host. Write a 1 to clear this bit.
14
13
R/W
R/W
R/W
R/W
R
MABORT. Received master abort. This bit is set when a cycle initiated by the PCI4450 on the PCI bus has beenterminated
by a master abort. Write a 1 to clear this bit.
TABT_REC.Received target abort. This bit is set when a cycle initiated by the PCI4450 on the PCI bus was terminated by
a target abort. Write a 1 to clear this bit.
12
TABT_SIG.Signaledtargetabort.ThisbitissetbythePCI4450whenitterminatesatransactiononthePCIbuswithatarget
abort. Write a 1 to clear this bit.
11
PCI_SPEED. DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the
PCI4450asserts this signal at a medium speed on nonconfiguration cycle accesses.
10–9
DATAPAR. Data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. PERR was asserted by any PCI device including the PCI4450.
b. The PCI4450 was the bus master during the data parity error.
c. The parity error response bit is set in the command register.
8
R/W
FBB_CAP. Fast back-to-back capable. The PCI4450 cannot accept fast back-to-back transactions; thus, this bit is
hardwiredto 0.
7
R
6
5
R
R
UDF. UDF supported. The PCI4450 does not support the user definable features; therefore, this bit is hardwired to 0.
66 MHz capable. The PCI4450 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is hardwired to 0.
Capabilitieslist. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are
implemented. The linked list of PCI power management capabilities is implemented in this function.
4
R
R
3–0
Reserved. These bits return 0s when read.
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
class code and revision ID register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Class code and revision ID
R
0
R
0
R
0
R
0
R
0
R
1
R
1
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
1
2
R
1
1
R
1
0
15
14
13
12
11
10
Name
Type
Default
Class code and revision ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Class code and revision ID
Read-only
Offset:
Default:
08h (Functions 0, 1)
0607 0000h
Description: This register recognizes the PCI4450 functions 0 and 1 as a bridge device (06h) and CardBus
bridge device (07h) with a 00h programming interface. Furthermore, the TI chip revision is
indicated in the lower byte (00h).
cache line size register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Cache line size
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Cache line size
Read/Write
Offset:
Default:
0Ch (Functions 0, 1)
00h
Description: This register is programmed by host software to indicate the system cache line size.
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
latency timer register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Latencytimer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Latency timer
Read/Write
0Dh
00h
Description: This register specifies the latency timer for the PCI4450, in units of PCI clock cycles. When
the PCI4450 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from
zero. If the latency timer expires before the PCI4450 transaction has terminated, then the
PCI4450 terminates the transaction when its GNT is deasserted.
header type register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Header type
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Header type
Read-only
Offset:
Default:
0Eh (Functions 0, 1)
82h
Description: This register returns 82h when read, indicating that the PCI4450 functions 0 and 1
configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI
header ranges from PCI register 0 to 7Fh, and 80h–FFh is user definable extension registers.
BIST register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
BIST
Read-only
Offset:
Default:
0Fh (Functions 0, 1)
00h
Description: Since the PCI4450 does not support a built-in self-test (BIST), this register returnsthevalueof
00h when read. This register returns 0s for the two PCI4450 functions.
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
CardBus socket registers / ExCA registers base address register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CardBus socket registers/ExCA base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus socket registers/ExCA base address
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
CardBus socket registers/ExCA base address
Read-only, Read/Write
10h
0000 0000h
Description: This register is programmed with a base address referencing the CardBus socket registers
and the memory mapped ExCA register set. Bits 31–12 are read/write, and allow the base
address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte
boundary. Bits 11–0 are read-only, returning 0s when read. When software writes all ones to
this register, the value read back will be FFFF F000h, indicating that at least 4K bytes of
memory address space are required. The CardBus registers start at offset 000h, and the
memory mapped ExCA registers begin at offset 800h. This register is not shared by functions
0 and 1, mapping each socket control register separately.
capability pointer register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capabilitypointer
R
1
R
0
R
1
R
0
R
R
0
R
0
R
0
0
Register:
Type:
Offset:
Default:
Capability pointer
Read-only
14h
A0h
Description: This register provides a pointer into the PCI configuration header where the PCI power
management register block resides. PCI header doublewords at A0h and A4h provide the
power management (PM) registers. Each socket has its own capability pointer register. This
register is read-only and returns A0h when read.
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
secondary status register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary status
R/WC R/WC R/WC R/WC R/WC
R
0
R
1
R/WC
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
0
0
0
0
Register:
Type:
Secondary status
Read-only, Read/Write to Clear
Offset:
Default:
16h
0200h
Description: This register is compatible with the PCI-PCI bridge secondary status register. It indicates
CardBus related device information to the host system. This register is very similar to the PCI
status register (offset 06h), and status bits are cleared by a writing a 1. This register is not
shared by the two socket functions, but is accessed on a per socket basis.
Table 27. Secondary Status Register Description
BIT
TYPE
FUNCTION
CBPARITY.Detectedparityerror.ThisbitissetwhenaCardBusparityerrorisdetected,eitheraddressordataparityerrors.
Write a 1 to clear this bit.
15
R/WC
CBSERR.Signaledsystemerror. This bit is set when CSERRissignaledbyaCardBuscard. ThePCI4450doesnotassert
the CSERR signal. Write a 1 to clear this bit.
14
13
R/WC
R/WC
R/WC
R/WC
R
CBMABORT. Received master abort. This bit is set when a cycle initiated by the PCI4450 on the CardBus bus has been
terminated by a master abort. Write a 1 to clear this bit.
REC_CBTA.Receivedtargetabort.ThisbitissetwhenacycleinitiatedbythePCI4450ontheCardBusbuswasterminated
by a target abort. Write a 1 to clear this bit.
12
SIG_CBTA. Signaled target abort. This bit is set by the PCI4450 when it terminates a transaction on the CardBus bus with
a target abort. Write a 1 to clear this bit.
11
CB_SPEED. CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the
PCI4450asserts this signal at a medium speed.
10–9
CB_DPAR. CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
8
R/WC
b. The PCI4450 was the bus master during the data parity error.
c. The parity error response bit is set in the bridge control register.
CBFBB_CAP. Fast back-to-back capable. The PCI4450 cannot accept fast back-to-back transactions; therefore, this bit
is hardwired to 0.
7
6
R
R
CB_UDF. User definable feature support. The PCI4450 does not support the user definable features; therefore, this bit is
hardwired to 0.
CB66MHZ. 66 MHz capable. The PCI4450 CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore,this bit is hardwired to 0.
5
R
R
4–0
Reserved. These bits return 0s when read.
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PCI bus number register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PCI bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
PCI bus number
Read/Write
Offset:
Default:
18h (Functions 0, 1)
00h
Description: This register is programmed by the host system to indicate the bus number of the PCI bus to
which the PCI4450 is connected. The PCI4450 uses this register, in conjunction with the
CardBus bus number and subordinate bus number registers, to determine when to forward
PCI configuration cycles to its secondary buses.
CardBus bus number register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBusbus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
CardBus bus number
Read/Write
19h
00h
Description: This register is programmed by the host system to indicate the bus number of the CardBus
bus to which the PCI4450 is connected. The PCI4450 uses this register, in conjunction with
the PCI bus number and subordinate bus number registers, to determine when to forward PCI
configuration cycles to its secondary buses. This register is separate for each PCI4450
controller function.
subordinate bus number register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Subordinate bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Subordinate bus number
Read/Write
1Ah
00h
Description: This register is programmed by the host system to indicate the highest numbered bus below
the CardBus bus. The PCI4450 uses this register, in conjunction with the PCI bus number and
CardBus bus number registers, to determine when to forward PCI configuration cycles to its
secondary buses. This register is separate for each CardBus controller function.
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
CardBus latency timer register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBuslatency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
CardBus latency timer
Read/Write
Offset:
Default:
1Bh (Functions 0, 1)
00h
Description: This register is programmed by the host system to specify the latency timer for the PCI4450
CardBus interface, in units of CCLK cycles. When the PCI4450 is a CardBus initiator and
asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires
before the PCI4450 transaction has terminated, then the PCI4450 terminates the transaction
at the end of the next data phase. A recommended minimum value for this register of 20h
allows most transactions to be completed.
memory base registers 0, 1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Memorybase registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Memory base registers 0, 1
Read-only, Read/Write
1Ch, 24h
0000 0000h
Description: These registers indicate the lower address of a PCI memory address range. They are used by
the PCI4450 to determine when to forward a memory transaction to the CardBus bus, and
likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write
and allow the memory base to be located anywhere in the 32-bit PCI memory space on
4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Writes to these bits have
no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1
are prefetchable or nonprefetchable. The memory base register or the memory limit register
must be nonzero in order for the PCI4450 to claim any memory transactions through CardBus
memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of
memory to CardBus).
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
memory limit registers 0, 1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Memorylimit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Memory limit registers 0, 1
Read-only, Read/Write
20h, 28h
0000 0000h
Description: These registers indicate the upper address of a PCI memory address range. Theyareusedby
the PCI4450 to determine when to forward a memory transaction to the CardBus bus, and
likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write
and allow the memory base to be located anywhere in the 32-bit PCI memory space on
4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Writes to these bits have
no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1
are prefetchable or nonprefetchable. The memory base register or the memory limit register
must be nonzero in order for the PCI4450 to claim any memory transactions through CardBus
memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of
memory to CardBus).
I/O base registers 0, 1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
I/O base registers 0, 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
I/O base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
I/O base registers 0, 1
Read-only, Read/Write
2Ch, 34h
0000 0000h
Description: These registers indicate the lower address of a PCI I/O address range. They are used by the
PCI4450 to determine when to forward an I/O transaction to the CardBus bus, and likewise,
when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the
bottom of the I/O window within a 64-Kbyte page, and the upper 16 bits (31–16) are all 0s
which locate this 64-Kbyte page in the first page of the 32-bit PCI I/O address space. Bits
31–16and bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a
natural doubleword boundary in the first 64-Kbyte page of PCI I/O address space. These I/O
windows are enabled when either the I/O base register or the I/O limit register are nonzero.
The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus.
Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
I/O limit registers 0, 1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
I/O limit registers 0, 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
I/O limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
I/O limit registers 0, 1
Read-only, Read/Write
30h, 38h
0000 0000h
Description: These registers indicate the upper address of a PCI I/O address range. They are used by the
PCI4450 to determine when to forward an I/O transaction to the CardBus bus, and likewise,
when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the
I/O window within a 64-Kbyte page, and the upper 16 bits are a page register which locates
this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O
limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16 of the
appropriate I/O base register) on doubleword boundaries.
Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base
register. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a
naturaldoubleword boundary. Writes to read-only bits have no effect. The PCI4450 assumes
that the lower two bits of the limit address are ones.
These I/O windows are enabled when either the I/O base register or the I/O limit register are
nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to
CardBus.
Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.
interrupt line register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interruptline
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Register:
Type:
Offset:
Default:
Interrupt line
Read/Write
3Ch
FFh
Description: This register communicates interrupt line routing information to the host system. This register
is not used by the PCI4450, since there are many programmable interrupt signaling options.
This register is considered reserved; however, host software may read and write to this
register. Each PCI4450 function has an interrupt line register.
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
interrupt pin register
PCI function 0
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interruptpin – PCI function 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
PCI function 1
Bit
7
6
5
4
3
2
1
0
Name
Type
Interruptpin – PCI function 1
R
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Default
0
Register:
Type:
Offset:
Default:
Interrupt pin
Read-only
3Dh
The default depends on the interrupt signaling mode.
Description: The value read from this register is function dependent. The value depends on two interrupt
tie bits (INTRTIE and TIEALL) in the system control register. INTRTIE is compatible withother
TI CardBus controllers and ties INTA to INTB internally. The TIEALL bit ties INTA, INTB, and
INTC together internally. The internal interrupt connections set by INTRTIE and TIEALL are
communicated to host software through this standard register interface. Refer to Table 28 for
a complete description of the register contents.
Table 28. Interrupt Pin Register Cross Reference
INTRTIE
Bit
TIEALL
Bit
INTPIN
Function 0
INTPIN
Function 1
INTPIN
Function 2
0
1
x
0
0
1
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
0x02 (INTB)
0x01 (INTA)
0x01 (INTA)
0x03 (INTC)
0x03 (INTC)
0x01 (INTA)
bridge control register
Bit
15
14
13
12
11
10
9
8
7
6†
5
4
3
2
1
0
Name
Type
Default
Bridgecontrol
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Bridge control
Read-only, Read/Write
3Eh (Function 0, 1)
0340h
Description: This register provides control over various PCI4450 bridging functions. Some bits in this
register are global in nature and should be accessed only through function 0.
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 29. Bridge Control Register Description
BIT
TYPE
FUNCTION
15–11
R
Reserved. These bits return 0s when read.
POSTEN. Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables posting of
write data on burst cycles. Operating with writepostingdisabledwillinhibitperformanceonburstcycles. Notethatbursted
write data can be posted, but various write transactions may not. This bit is socket dependent and is not shared between
functions 0 and 1.
10
9
R/W
R/W
R/W
R/W
PREFETCH1.Memorywindow1type. Thisbitspecifieswhetherornotmemorywindow1isprefetchable. Thisbitissocket
dependent.This bit is encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
PREFETCH0. Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
8
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
PCI Interrupt – IREQ routing enable. This bit is used to select whether PC Card functional interrupts are routed to PCI
interruptsor to the IRQ specified in the ExCA registers.
7
0 = Functional interrupts are routed to PCI interrupts (default).
1 = Functional interrupts are routed by ExCA registers.
CRST. CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST signal may
also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted.
1 = CRST is asserted (default).
This bit will not be cleared by the assertion of PRST. It will only be cleared by the assertion of G_RST.
6†
5§
R/W
R/W
MABTMODE. Master abort mode. This bit controls how the PCI4450 responds to a master abort when the PCI4450 is an
initiator on the CardBus interface. This bit is common between each socket.
0 = Master aborts not reported (default).
1 = Signal target abort on PCI and signal SERR, if enabled.
4
3
R
Reserved. This bit returns 0 when read.
VGAEN.VGAenable. ThisbitaffectshowthePCI4450respondstoVGAaddresses. Whenthisbitisset, accessestoVGA
addresseswill be forwarded.
R/W
ISAEN.ISAmodeenable. Thisbitaffects how the PCI4450 passes I/O cycles within the 64-Kbyte ISA range. This bit is not
common between sockets. When this bit is set, the PCI4450 will not forward the last 768 bytes of each 1K I/O range to
CardBus.
2
1
R/W
R/W
CSERREN. CSERRenable. Thisbit controlstheresponseof thePCI4450toCSERR signals on the CardBus bus. This bit
is separate for each socket.
0 = CSERR is not forwarded to PCI SERR.
1 = CSERR is forwarded to PCI SERR.
CPERREN.CardBus parity error response enable. This bit controls the response of the PCI4450 to CardBus parity errors.
This bit is separate for each socket.
0
R/W
0 = CardBus parity errors are ignored.
1 = CardBus parity errors are reported using CPERR.
†
§
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
These bits are global in nature and should be accessed only through function 0.
57
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
subsystem vendor ID register
Bit
15‡
14‡
13‡
12‡
11‡
10‡
9‡
8‡
7‡
6‡
5‡
4‡
3‡
2‡
1‡
0‡
Name
Type
Default
Subsystem vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
‡
This bit is cleared only by the assertion of G_RST.
Register:
Type:
Subsystem vendor ID
Read-only, Read/Write (when bit 5 in the system control register is 0.)
Offset:
Default:
40h (Functions 0, 1)
0000h
Description: This register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of
bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write;
when bit 5 is 1, this register is read-only. The default mode is read-only.
subsystem ID register
Bit
15‡
14‡
13‡
12‡
11‡
10‡
9‡
8‡
7‡
6‡
5‡
4‡
3‡
2‡
1‡
0‡
Name
Type
Default
Subsystem ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
‡
This bit is cleared only by the assertion of G_RST.
Register:
Type:
Subsystem ID
Read-only, Read/Write (when bit 5 in the system control register is 0.)
Offset:
Default:
42h (Functions 0, 1)
0000h
Description: This register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of
bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write;
when bit 5 is 1, this register is read-only. The default mode is read-only.
If an EEPROM is present, then the subsystem ID and subsystem vendor ID will be loaded
from EEPROM after a reset.
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PC Card 16-bit I/F legacy mode base address register
Bit
31‡
30‡
29‡
28‡
27‡
26‡
25‡
24‡
23‡
22‡
21‡
20‡
19‡
18‡
17‡
16‡
Name
Type
Default
Bit
PC Card 16-bit I/F legacy mode base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15‡
14‡
13‡
12‡
11‡
10‡
9‡
8‡
7‡
6‡
5‡
4‡
3‡
2‡
1‡
0
Name
Type
Default
PC Card 16-bit I/F legacy mode base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
1
‡
This bit is cleared only by the assertion of G_RST.
Register:
Type:
PC Card 16-bit I/F legacy mode base address
Read-only, Read/Write
Offset:
Default:
44h (Functions 0, 1)
0000 0001h
Description: The PCI4450 supports the index/data scheme of accessing the ExCA registers, which is
mappedby this register. An address written to this register is the address for the index register
and the address+1 is the data address. Using this access method, applications requiring
index/data ExCA access can be supported. The base address can be mapped anywhere in
32-bit I/O space on a word boundary; hence, bit 0 is read-only returning 1 when read. As
specified in the Yenta specification, this register is shared by functions 0 and 1. Refer to the
ExCA register set description for register offsets.
system control register
Bit
31‡
30‡
29‡
28
27‡
26‡
25‡
24‡
23
22‡
21‡
20‡
19‡
18‡
17‡
16‡
Name
Type
Default
Bit
System control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
7
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15‡
14‡
13
12
11
10
9
8
6‡
5‡
4‡
3‡
2
1‡
0‡
Name
Type
Default
System control
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
1
R/W
0
R/W
0
R
0
R/W
0
R/W
0
‡
This bit is cleared only by the assertion of G_RST.
Register:
Type:
Offset:
Default:
System control
Read-only, Read/Write
80h (Functions 0, 1)
0000 0020h
Description: System level initializations are performed through programming this doubleword register.
Some of the bits are global in nature and should be accessed only through function 0.
59
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 30. System Control Register Description
BIT
TYPE
FUNCTION
SER_STEP. Serialized PCI interrupt routing step. These bits are used to configure the serialized PCI interrupt stream
signalingand accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. These bits are global
to both PCI4450 functions.
00 = INTA/INTB/INTC signal in INTA/INTB/INTC slots (default)
31–30‡§
R/W
01 = INTA/INTB/INTC signal in INTB/INTC/INTD slots
10 = INTA/INTB/INTC signal in INTC/INTD/INTA slots
11 = INTA/INTB/INTC signal in INTD/INTA/INTB slots
INTRTIE. Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally and are
signaled as INTA. INTA may then be shifted by using the SER_STEP bits. This bit is global to both PCI4450 functions.
This bit has no effect on INTC.
29‡§
28
R/W
R/W
R/W
0 = INTA and INTB are not tied together internally (default).
1 = INTA and INTB are tied together internally.
TIEALL. This bit ties INTA, INTB, and INTC internally (to INTA) and reports this through the interrupt pin register.
P2CCLK. P2C power switch CLOCK. This bit determines whether the CLOCK terminal (terminal U12) is an input that
requiresan external clock source or if this terminal is an output that uses the internal oscillator.
0 = CLOCK terminal (terminal U12) is an input (default) (disabled).
27‡§
1 = CLOCK terminal is an output, the PCI4450 generated CLOCK.
A 43kW pulldown resistor should be tied to this terminal.
SMIROUTE. SMI interrupt routing. This bit is shared between functions 0 and 1, and selects whether IRQ2 or CSC is
signaledwhen a write occurs to power a PC Card socket.
26‡§
25‡
R/W
R/W
0 = PC Card power change interrupts routed to IRQ2 (default).
1 = A CSC interrupt is generated on PC Card power changes.
SMISTATUS. SMI interrupt status. This socket dependent bit is set when a write occurs to set the socket power, and the
SMIENB bit is set. Writing a 1 to this bit clears the status.
0 = SMI interrupt is signaled.
1 = SMI interrupt is not signaled.
SMIENB.SMI interrupt mode enable. When this bit isset, theSMIinterruptsignalinggeneratesaninterruptwhenawrite
to the socket power control occurs. This bit is shared and defaults to 0 (disabled).
0 = SMI interrupt mode is disabled (default).
24‡§
23
R/W
R
1 = SMI interrupt mode is enabled.
Reserved
CBRSVD. CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals will be driven low
when a CardBus card is inserted. When this bit is low, as default, these signals are placed in a high-impedance state.
0 = Place the CardBus RSVD terminals in a high-impedance state
22‡
R/W
1 = Drive the Cardbus RSVD terminals low (default).
VCCPROT. V
CC
protection enable. This bit is socket dependent.
21‡
20‡
R/W
R/W
0 = V
1 = V
protection is enabled for 16-bit cards (default).
protection is disabled for 16-bit cards.
CC
CC
Reducedzoomed video enable. When this bit is enabled, A25–22 of the card interface for PC Card 16 cards is placed in
the high impedance state. This bit is encoded as:
0 = Reduced zoomed video is disabled (default).
1 = Reduced zoomed video is enabled.
CDREQEN.PC/PCI DMA card enable. When this bit is set, the PCI4450 allows 16-bit PC Cards to request PC/PCI DMA
using the DREQ signaling. DREQ is selected through the socket DMA register 0.
0 = Ignore DREQ signaling from PC Cards (default).
19‡
R/W
R/W
1 = Signal DMA request on DREQ.
CDMACHAN. PC/PCI DMA channel assignment. These bits are encoded as:
0–3 = 8-bit DMA channels
18–16‡
4 = PCI master; not used (default)
5–7 = 16-bit DMA channels
§
‡
These bits are global in nature and should be accessed only through function 0.
This bit is cleared only by the assertion of G_RST.
60
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 30. System Control Register Description (continued)
BIT
TYPE
FUNCTION
MRBURSTDN. Memory read burst enable downstream. When this bit is set, memory read transactions are allowed to
burst downstream.
15‡§
R/W
0 = MRBURSTDN downstream is disabled.
1 = MRBURSTDN downstream is enabled (default).
MRBURSTUP. Memory read burst enable upstream. When this bit is set, thePCI4450allowsmemoryreadtransactions
to burst upstream.
14‡§
R/W
0 = MRBURSTUP upstream is disabled (default).
1 = MRBURSTUP upstream is enabled.
SOCACTIVE. Socket activity status. When set, this bit indicates access has been performed to or from a PC Card, and
is cleared upon read of this status bit. This bit is socket dependent.
0 = No socket activity (default)
13
12
R
R
1 = Socket activity
Reserved. This bit returns 1 when read. This is the power rail bit in functions 0 and 1.
PWRSTREAM.Power stream in progress status bit. When set, this bit indicates that a power stream to the power switch
is in progress and a powering change has been requested. When this bit is clear, it indicates that the power stream is
complete.
11
10
9
R
R
R
0 = Power stream is complete, delay has expired.
1 = Power stream is in progress.
DELAYUP. Power-up delay in progress status bit. When set, this bit indicates that a power-up stream has been sent to
the power switch, and proper power may not yet be stable. This bit is cleared when the power-up delay has expired.
0 = Power-up delay has expired.
1 = Power-up stream sent to switch. Power might not be stable.
DELAYDOWN.Power-downdelayinprogressstatusbit. Whenset, thisbitindicatesthatapower-downstreamhasbeen
sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-down delay has
expired.
0 = Power-down delay has expired.
1 = Power-down stream sent to switch. Power might not be stable.
INTERROGATE. Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when
the interrogation completes. This bit is socket dependent.
0 = Interrogation not in progress (default)
8
7
R
R
1 = Interrogation in progress
Reserved. This bit returns 0 when read.
PWRSAVINGS. Power savings mode enable. When this bit is set, the PCI4450 will consume less power with no
performanceloss. This bit is shared between the two PCI4450 functions.
0 = Power savings mode disabled
6‡§
R/W
1 = Power savings mode enabled (default)
SUBSYSRW. Subsystem ID (SS ID), subsystem vendor ID (SS VID), and the ExCA identification and revision registers
read/write enable. This bit is shared by functions 0 and 1. This bit does not control read/write of function 2, subsystem ID
register.
5‡§
4‡§
R/W
R/W
0 = SubsystemID, subsystemvendorID, and theExCA identification and revisionregisters areread/write.
1 = Subsystem ID, subsystem vendor ID, and the ExCA identification and revision registers are read-only
(default).
CB_DPAR. CardBus data parity SERR signaling enable.
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
CDMA_EN.PC/PCIDMAenable. EnablesPC/PCIDMAwhenset. WhenPC/PCIDMAisenabled, PCREQ and PCGNT
shouldbe routed to a multifunction routing terminal. See multifunction routing status register for options.
0 = Centralized DMA disabled (default)
3‡§
R/W
R
1 = Centralized DMA enabled
2
Reserved. This bit returns 0 when read.
§
‡
These bits are global in nature and should be accessed only through function 0.
This bit is cleared only by the assertion of G_RST.
61
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 30. System Control Register Description (continued)
BIT
TYPE
FUNCTION
KEEPCLK. Keep clock. When this bit is set, the PCI4450 will always follow CLKRUN protocol to maintain the system
PCLK and the CCLK (CardBus clock). This bit is global to the PCI4450 functions.
0 = Allow system PCLK and CCLK to stop (default)
1 = Never allow system PCLK or CCLK clock to stop
1‡§
R/W
NotethatthefunctionalityofthisbithaschangedversusthePCI12XXseriesofTICardBuscontrollers. IntheseCardBus
controllers,setting this bit would only maintain the PCI clock, not the CCLK. In the PCI4450, setting this bit will maintain
both the PCI clock and the CCLK.
PME/RI_OUT select bit. When this bit is 1, the PME signal is routed on to pin Y13 (PME/RI_OUT pin). When this bit is
0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal is routed on to pin Y13 (GFN) or pin R11 (GJG).
If this bit is 0 and bit 7 (RIENB) of the card control register is 0, then the output (Y13 or R11) will be placed in a
high-impedancestate. This pin is encoded as:
0‡§
R/W
0 = RI_OUT signal is routed to pin Y13 (GFN) or pin R11 (GJG) if bit 7 of the card control register is 1*.
(default)
1 = PME signal is routed on pin Y13 (GFN) or pin R11 (GJG) of the PCI4450 controller.
NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register is 0, then the output on pin Y13 (GFN) or pin R11 (GJG)
is placed in a high-impedance state.
§
‡
These bits are global in nature and should be accessed only through function 0.
This bit is cleared only by the assertion of G_RST.
62
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
multimedia control register
Bit
7‡
6‡
5‡
4‡
3‡
2‡
1‡
0‡
Name
Type
Default
Multimedia control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
0
Register:
Type:
Multimedia control
Read/Write
Offset:
Default:
84h (Functions 0, 1)
00h
Description: This register provides port mapping for the PCI4450 zoomed video/data ports. See zoomed
video support for details on the PCI4450 zoomed video support. Access this register only
through function 0.
Table 31. Multimedia Control Register Description
BIT
TYPE
FUNCTION
ZVOUTEN.ZV output enable. This bit enables the output for the PCI4450 outsourcing ZV terminals. When this bit is reset,
‘0’, these terminals are in a high impedance state.
7‡
R/W
0 = PCI4450 ZV output terminals disabled (default)
1 = PCI4450 ZV output terminals enabled
PORTSEL. ZV port select. This bit controls the multiplexing control over which PC Card ZV port data will be driven to the
outsourcing PCI4450 ZV port.
6‡
5‡
R/W
R/W
0 = Output card 0 ZV if enabled (default)
1 = Output card 1 ZV if enabled
Zoomed video auto-detect. This bit enables the zoomed video auto-detect feature. This bit is encoded as:
0 = Zoomed video auto detect disabled (default)
1 = Zoomed video auto detect enabled
Auto-detect priority encoding. These bits have meaning only if zoomed video auto-detect is enabled in bit 5 of this register.
If auto-detect is enabled, then bits 4–2 are encoded as follows:
000 = Slot A, Slot B, External Source
001 = Slot A, External Source, Slot B
010 = Slot B, Slot A, External Source
011 = Slot B, External Source, Slot A
4–2‡
R/W
100 = External Source, Slot A, Slot B
101 = External Source, Slot B, Slot A
110 = Reserved
111 = Reserved
ZVEN1.PC Card 1 ZV mode enable. Enables the zoomed video mode for socket 1. When set, the PCI4450 inputs ZV data
from the PC Card interface, and disables output drivers on ZV terminals.
0 = PC Card 1 ZV disabled (default)
1‡
0‡
R/W
R/W
1 = PC Card 1 ZV enabled
ZVEN0.PC Card 0 ZV mode enable. Enables the zoomed video mode for socket 0. When set, the PCI4450 inputs ZV data
from the PC Card interface, and disables output drivers on ZV terminals.
0 = PC Card 0 ZV disabled (default)
1 = PC Card 0 ZV enabled
‡
This bit is cleared only by the assertion of G_RST.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
general status register
Bit
7
6
5
4
3
2‡
1‡
0‡
Name
Type
Default
Generalstatus
R/U
0
R
0
R
0
R
0
R
0
R/U
X
R
0
R
0
Register:
Type:
General status
Read/Update
Offset:
Default:
85h (Functions 0)
00h
Description: This register provides the general device status information. The status of the serial
EEPROM interface is provided through this register.
Table 32. General Status Register Description
BIT
7
TYPE
R/U
R
FUNCTION
IDSEL_DET. When this bit is set, the IDSEL/MFUNC7 terminal functions as an IDSEL input.
Reserved. These bits return 0s when read.
6–3
EEDETECT. Serial EEPROM detect. Serial EEPROM is detected by sampling a logic high on SCL on PRST. When this bit
is set, the serial ROM is detected. This status bit is encoded as:
0 = EEPROM not detected (default)
2‡§
1‡§
0‡§
R/U
R
1 = EEPROM detected
DATAERR.Serial EEPROM data error status. This bit indicateswhena data erroroccurson theserial EEPROMinterface.
This bit may be set due to a missing acknowledge. This bit is cleared by a writing a 1.
0 = No error detected. (default)
1 = Data error detected.
EEBUSY. Serial EEPROM busy status. This bit indicates the status of the PCI4450 serial EEPROM circuitry. This bit is set
duringthe loading of the subsystem ID value.
R
0 = Serial EEPROM circuitry is not busy (default).
1 = Serial EEPROM circuitry is busy.
§
‡
This bit is global in nature and should only be accessed through function 0.
This bit is cleared only by the assertion of G_RST.
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PC Card and OHCI Controller
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general control register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Generalcontrol
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General control
Read-Only, Read/Write
Offset:
Default:
86h
00h
Description: This register provides top level PCI arbitration control.
Table 33. General Control Register Description
BIT
7–4
3
TYPE
R
FUNCTION
Reserved. These bits return 0s when read.
R/W
R/W
DISABLE_OHCI.Whenthisbitisset,theopenHCI1394controllerfunctioniscompletelynonaccessibleandnonfunctional.
GP2IIC. When this bit is set, the GPO0 and GPO1 signals are routed to SDA and SCL, respectively.
2
ARB_CTRL. Controls top level PCI arbitration.
00 = 1394 open HCI priority
01 = CardBus priority
1–0
R/W
10 = Fair round robin
11 = Reserved (fair round robin)
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
general-purpose event status register
Bit
7‡
6‡
5
4
3‡
2‡
1‡
0‡
Name
Type
Default
General-purpose event status
RCU
0
RCU
0
R
0
R
0
RCU
0
RCU
0
RCU
0
RCU
0
Register:
Type:
General-purpose event status
Read/Clear/Update
Offset:
Default:
88h
00h
Description: This register contains status bits that are set when general events occur and may be
programmed to generate general-purpose event signalling through GPE.
Table 34. General-Purpose Event Status Register Description
BIT
TYPE
FUNCTION
7‡
RCU
PWR_STS. Power change status. This bit is set when software changes the V
or V
power state of either socket.
PP
CC
VPP12_STS.12V V
for either socket.
request status. This bit is set when software has changed the requested V level to or from 12 V
PP
PP
6‡
5–4
3‡
RCU
R
Reserved. This bit returns 0 when read. A write has no effect.
GP3_STS. GPI3 status. This bit is set on a change in status of the MFUNC3 terminal input level if configured as a
general-purpose input, GPI3.
RCU
GP2_STS. GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a
general-purpose input, GPI2.
2‡
1‡
0‡
RCU
RCU
RCU
GP1_STS. GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a
general-purpose input, GPI1.
GP0_STS. GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a
general-purpose input, GPI0.
‡
This bit is cleared only by the assertion of G_RST.
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
general-purpose event enable register
Bit
7‡
6‡
5
4
3‡
2‡
1‡
0‡
Name
Type
Default
General-purpose event enable
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General-purpose event enable
Read-only, Read/Write
Offset:
Default:
89h
00h
Description: This register contains bits that are set to enable GPE signals.
Table 35. General-Purpose Event Enable Register Description
BIT
7‡
TYPE
R/W
R/W
R
FUNCTION
PWR_EN. Power change GPE enable. When this bit is set, GPE is signaled on PWR_STS events.
VPP12_EN.12-Volt V GPE enable. When this bit is set, GPE is signaled on VPP12_STS events.
6‡
PP
5–4
3‡
Reserved. This bit returns 0 when read. A write has no effect.
R/W
R/W
R/W
R/W
GP3_EN. GPI3 GPE enable. When this bit is set, GPE is signaled on GP3_STS events.
GP2_EN. GPI2 GPE enable. When this bit is set, GPE is signaled on GP2_STS events.
GP1_EN. GPI1 GPE enable. When this bit is set, GPE is signaled on GP1_STS events.
GP0_EN. GPI0 GPE enable. When this bit is set, GPE is signaled on GP0_STS events.
2‡
1‡
0‡
‡
This bit is cleared only by the assertion of G_RST.
general-purpose input register
Bit
7
6
5
4
3‡
2‡
1‡
0‡
Name
Type
Default
General-purpose input
R
0
R
0
R
0
R
0
RU
x
RU
x
RU
x
RU
x
Register:
Type:
Offset:
Default:
General-purpose input
Read/Update
8Ah
00h
Description: This register contains GPI terminal status.
Table 36. General-Purpose Input Register Description
BIT
7–4
3‡
TYPE
R
FUNCTION
Reserved. These bits return 0s when read. Writes have no effect.
RU
RU
RU
RU
GPI3_DATA. GPI3 data input. This bit represents the logical value of the data input from GPI3.
GPI2_DATA. GPI2 data input. This bit represents the logical value of the data input from GPI2.
GPI1_DATA. GPI1 data input. This bit represents the logical value of the data input from GPI1.
GPI0_DATA. GPI0 data input. This bit represents the logical value of the data input from GPI0.
2‡
1‡
0‡
‡
This bit is cleared only by the assertion of G_RST.
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
general-purpose output register
Bit
7
6
5
4
3‡
2‡
1‡
0‡
Name
Type
Default
General-purpose output
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General-purpose output
Read-only, Read/Write
Offset:
Default:
8Bh
00h
Description: This register is used to drive the GPO3–GPO0 outputs.
Table 37. General-Purpose Output Register Description
BIT
7–4
3‡
TYPE
R
FUNCTION
Reserved. These bits return 0s when read. Writes have no effect.
R/W
R/W
R/W
R/W
GPO3_DATA. This bit represents the logical value of the data driven to GPO3.
GPO2_DATA. This bit represents the logical value of the data driven to GPO2.
GPO1_DATA. This bit represents the logical value of the data driven to GPO1.
GPO0_DATA. This bit represents the logical value of the data driven to GPO0.
2‡
1‡
0‡
‡
This bit is cleared only by the assertion of G_RST.
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
multifunction routing status register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Multifunction routing status
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Multifunction routing status
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Multifunction routing status
Read/Write
8Ch
0000 0000h
Description: This register is used to configure MFUNC7–MFUNC0 terminals. These terminals may be
configured for various functions. This register is intended to be programmed once at
power-on initialization. The default value for this register may also be loaded through a serial
ROM.
Table 38. Multifunction Routing Status Register Description
BIT
TYPE
FUNCTION
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC7_SEL. MFUNC7 select. These bits control the mapping of MFUNC7 as follows:
31
R
000 = IDSEL
100 = D3_STAT
101 = LOCK
110 = RSVD
111 = RSVD
001 = RI_OUT
010 = OHCI_LED
011 = PCREQ
30–28
27
R/W
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC6_SEL. MFUNC6 select. These bits control the mapping of MFUNC6 as follows:
000 = RSVD
001 = RSVD
010 = OHCI_LED
011 = RSVD
100 = D3_STAT
101 = RSVD
110 = CAUDPWM
111 = RSVD
26–24
23
R/W
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC5_SEL. MFUNC5 select. These bits control the mapping of MFUNC5 as follows:
000 = RSVD
001 = RSVD
010 = OHCI_LED
011 = RSVD
100 = RSVD
101 = GPE
110 = CAUDPWM
111 = RSVD
22–20
19
R/W
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC4_SEL. MFUNC4 select. These bits control the mapping of MFUNC4 as follows:
000 = RSVD
001 = RSVD
010 = LEDA1
011 = PCREQ
100 = RSVD
101 = GPE
110 = RSVD
111 = ZV_STAT
18–16
15
R/W
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC3_SEL. MFUNC3 select. These bits control the mapping of MFUNC3 as follows:
000 = GPI3
100 = RSVD
101 = LOCK
110 = RSVD
111 = C_ZVCLK
001 = GPO3
010 = LEDA2
011 = PCGNT
14–12
R/W
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 38. Multifunction Routing Status Register Description (continued)
BIT
TYPE
FUNCTION
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC2_SEL. MFUNC2 select. These bits control the mapping of MFUNC2 as follows:
11
R
000 = GPI2
001 = GPO2
010 = INTC
011 = PCGNT
100 = D3_STAT
101 = RSVD
110 = RSVD
10–8
7
R/W
R
111 = C_ZVCLK
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC1_SEL. MFUNC1 select. These bits control the mapping of MFUNC1 as follows:
000 = GPI1
001 = GPO1
010 = INTB
100 = D3_STAT
101 = LOCK
110 = CAUDPWM
111 = ZV_STAT
6–4
3
R/W
R
011 = TEST_MUX
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC0_SEL. MFUNC0 select. These bits control the mapping of MFUNC0 as follows:
000 = GPI0
001 = GPO0
010 = INTA
011 = PCREQ
100 = RSVD
101 = GPE
110 = RSVD
111 = ZV_STAT
2–0
R/W
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
retry status register
Bit
7‡
6‡
5‡
4
3‡
2
1‡
0
Name
Type
Default
Retry status
R/W
1
R/W
1
R/WC
0
R
0
R/WC
0
R
0
R/WC
0
R
0
Register:
Type:
Offset:
Default:
Retry status
Read-only, Read/Write
90h (Functions 0, 1)
C0h
Description: The contents of this register enable the retry time-out counters and display the retry expiration
status. The flags are set when the PCI4450 retries a PCI or CardBus master request, and the
15
master does not return within 2 PCI clock cycles. The flags are cleared by writing a 1 to the
bit. These bits are expected to be incorporated into the PCI command register, PCI status
register, and bridge control register by the PCI SIG. Access this register only through function
0.
Table 39. Retry Status Register Description
BIT
TYPE
FUNCTION
PCIRETRY. PCI retry time-out counter enable. This bit is encoded as:
0 = PCI retry counter disabled
7‡
R/W
1 = PCI retry counter enabled (default)
CBRETRY. CardBus retry time-out counter enable. This bit is encoded as:
0 = CardBus retry counter disabled
6‡§
R/W
1 = CardBus retry counter enabled (default)
TEXP_CBB. CardBus target B retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
5‡
4
R/WC
R
1 = Retry has expired.
Reserved. This bit returns 0 when read.
TEXP_CBA. CardBus target A retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
3‡§
2
R/WC
R
1 = Retry has expired.
Reserved. This bit returns 0 when read.
TEXP_PCI. PCI target retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
1‡
0
R/WC
R
1 = Retry has expired.
Reserved. This bit returns 0 when read.
§
‡
These bits are global in nature and should be accessed only through function 0.
This bit is cleared only by the assertion of G_RST.
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
card control register
Bit
7‡
6‡
5
4
3
2‡
1‡
0‡
Name
Type
Default
Card control
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Card control
Read-only, Read/Write
Offset:
Default:
91h
00h
Description: This register is provided for PCI1130 compatibility. The contents provide the PC Card function
interrupt flag (IFG) and an alias for the ZVEN0 and ZVEN1 bits found in the PCI4450
multimedia control register. When this register is accessed by function 0, the ZVEN0 bit will
alias with ZVENABLE. When this register is accessed by function 1, the ZVEN1 bit will alias
with ZVENABLE. Setting ZVENABLE only places the PC Card socket interface ZV terminals
in a high impedance state, but does not enable the PCI4450 to drive ZV data onto the ZV
terminals.
The RI_OUT signal is enabled through this register, and the enable bit is shared between
functions 0 and 1.
Table 40. Card Control Register Description
BIT
TYPE
FUNCTION
RIENB. Ring indicate enable. When this bit is 1, the RI_OUT output is enabled. This bit is global in nature and should be
accessed only through function 0. This bit defaults to 0.
7‡§
R/W
ZVENABLE. Compatibility ZV mode enable. When this bit is 1, the corresponding PC Card socket interface ZV terminals
will enter a high impedance state. This bit defaults to 0.
6‡
R/W
5
R/W
R
Reserved.
4–3
Reserved. These bits default to 0.
AUD2MUX. CardBus Audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal must be routed through an
MFUNC terminal. If this bit is set for both functions, then function 0 gets routed.
0 = CAUDIO set to CAUDPWM on MFUNC pin (default)
2‡
1‡
0‡
R/W
R/W
R/W
1 = CAUDIO is not routed.
SPKROUTEN.Speaker output enable. When this bit is 1, it enables SPKR on the PC Card and routes it to SPKROUT on
the PCI bus. The SPKR signal from socket 0 is XOR’ed with the SPKR signal from socket 1 and sent to SPKROUT. The
SPKROUT terminal only drives data then either functions SPKROUTEN bit is set. This bit is encoded as:
0 = SPKR to SPKROUT not enabled (default)
1 = SPKR to SPKROUT enabled
IFG.Interruptflag.Thisbitistheinterruptflagfor16-bitI/OPCCardsandforCardBuscards.Thisbitissetwhenafunctional
interruptis signaled from a PC Card interface, and is socket dependent (i.e., not global). Write back a ‘1’ to clear this bit.
0 = No PC Card functional interrupt detected (default)
1 = PC Card functional interrupt detected
§
‡
These bits are global in nature and should be accessed only through function 0.
This bit is cleared only by the assertion of G_RST.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
device control register
Bit
7‡
6‡
5‡
4
3‡
Device control
2‡
1‡
0‡
Name
Type
Default
R/W
0
R/W
1
R/W
1
R
0
R/W
0
R/W
1
R/W
1
R/W
0
Register:
Type:
Offset:
Default:
Device control
Read-only, Read/Write
92h (Functions 0, 1)
66h
Description: This register is provided for PCI1130 compatibility. It contains bits which are shared between
functions 0 and 1. The interrupt mode select is programmed through this register. The socket
capable force bits are also programmed through this register.
Table 41. Device Control Register Description
BIT
TYPE
FUNCTION
Socket power lock bit. When this bit is set to 1, software will not be able to power down the PC Card socket while in D3.
This may be necessary to support Wake on LAN or RING if the operating system is programmed to power down a socket
when the CardBus controller is placed in the D3 state.
7‡
R/W
3VCAPABLE. 3-V socket capable force bit.
0 = Not 3-V capable
6‡§
R/W
1 = 3-V capable (default)
5‡
4
R/W
R
IO16R2. Diagnostic bit. This bit defaults to 1.
Reserved. This bit returns 0 when read. A write has no effect.
TEST. TI test bit. Write only 0 to this bit. This bit can be set to shorten the interrogation counter.
3‡§
R/W
INTMODE. Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Reserved
2–1‡§
R/W
10 = IRQ serialized interrupts & parallel PCI interrupts INTA and INTB
11 = IRQ & PCI serialized interrupts (default)
Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI4450, and it tests only the pins that
are inputs or I/Os. Any output only terminal on the PCI4450 is excluded from the NAND tree test.
0‡§
R/W
§
‡
These bits are global in nature and should be accessed only through function 0.
This bit is cleared only by the assertion of G_RST.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
diagnostic register
Bit
7‡
6‡
5‡
4‡
3‡
2‡
1‡
0‡
Name
Type
Default
Diagnostic
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
Register:
Type:
Diagnostic
Read/Write
Offset:
Default:
93h (Functions 0, 1)
61h
Description: This register is provided for internal Texas Instruments test purposes.
Table 42. Diagnostic Register Description
BIT
7‡§
6‡
TYPE
R/W
FUNCTION
This bit defaults to 0. This bit is encoded as:
0 = Reads true values in PCI vendor ID and PCI device ID registers (default).
1 = Reads all ones in reads to the PCI vendor ID and PCI device ID registers.
R/W
Reserved.
CSC interrupt routing control
0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1.
5‡
R/W
1 = CSC Interrupts routed to PCI if ExCA 805 bits 7–4 = 0000b. (Default)
In this case, the setting of ExCA 803 bit 4 is a “don’t care.”
4‡§
3‡§
2‡§
1‡§
R/W
R/W
R/W
R/W
DIAG. Diagnostic RETRY_DIS. Delayed transaction disable.
DIAG. Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
10
15
15
DIAG. Diagnostic DISCARD_TIM_SEL_CB. Set = 2 , Reset = 2
10
DIAG. Diagnostic DISCARD_TIM_SEL_PCI. Set = 2 , Reset = 2
ASYNC_CSC.Asynchronousinterruptgeneration.
0 = CSC interrupt not generated asynchronously
0‡§
R/W
1 = CSC interrupt is generated asynchronously (default)
§
‡
These bits are global in nature and should be accessed only through function 0.
This bit is cleared only by the assertion of G_RST.
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PCI4450GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
socket DMA register 0
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket DMA register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
R
0
15
14
13
12
11
10
1‡
0‡
Name
Type
Default
Socket DMA register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
DMA socket register 0
Read-only, Read/Write
94h (Functions 0, 1)
0000 0000h
Description: This register provides control over the PC Card DREQ (DMA request) signaling.
Table 43. Socket DMA Register 0 Description
BIT
TYPE
FUNCTION
31–2
R
Reserved. These bits return 0s when read.
DREQPIN.DMArequest(DREQ)pin. Thesebitsindicatewhichpinonthe16-bitPCCardinterfacewillastheDREQsignal
duringDMA transfers. This field is encoded as:
00 = Socket not configured for DMA (default)
01 = DREQ uses SPKR
1–0‡
R/W
10 = DREQ uses IOIS16
11 = DREQ uses INPACK
‡
This bit is cleared only by the assertion of G_RST.
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socket DMA register 1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket DMA register 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15‡
14‡
13‡
12‡
11‡
10‡
9‡
8‡
7‡
6‡
5‡
4‡
3‡
2‡
1‡
0‡
Name
Type
Default
Socket DMA register 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
DMA socket register 1
Read-only, Read/Write
98h (Functions 0, 1)
0000 0000h
Description: The contents of this register provide control over the distributed DMA (DDMA) registers and
the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a
16-byte region within the first 64K bytes of PCI I/O address space. Note that 32-bit transfers to
the 16-bit PC Card interface are not supported; the maximum transfer possible to the PC Card
interface is 16-bits. However, 32 bits of data are prefetched from the PCI bus, thus allowing
back-to-back 16-bit transfers to the PC Card interface.
Table 44. Socket DMA Register 1 Description
BIT
TYPE
FUNCTION
31–16
R
Reserved. These bits return 0s when read.
DMABASE. DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI
I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K bytes of I/O
addressspace. Thelowerfourbitsarehardwiredto0, andareincludedintheaddressdecode.Thus,thewindowisaligned
to a natural 16-byte boundary
15–4‡
3‡
R/W
R
EXTMODE. Extended addressing. This feature is not supported by the PCI4450, and always returns a 0.
XFERSIZE.Transfer size. These bits specify the width of the DMA transfer on the PC Card interface, and are encoded as:
00 = Transfers are 8 bits (default).
01 = Transfers are 16 bits.
10 = Reserved
2–1‡
0‡
R/W
R/W
11 = Reserved
DDMAEN. DDMA registers decode enable. Enables the decoding of the distributed DMA registers based upon the value
of DMABASE.
0 = Disabled (default)
1 = Enabled
‡
This bit is cleared only by the assertion of G_RST.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
capability ID register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CapabilityID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Capability ID
Read-only
A0h
01h
Description: This register identifies the linked list item as the register for PCI power management. The
register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI
location of the capabilities pointer and the value.
next item pointer register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Next item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Next item pointer
Read-only
A1h
00h
Description: The contents of this register indicate the next item in the linked list of the PCI power
managementcapabilities. SincethePCI4450functionsonlyincludeonecapabilitiesitem, this
register returns 0s when read.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
power management capabilities register
Bit
15†
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
R/W
1
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Power management capabilities
Read-only, Read/Write
A2h (Functions 0, 1)
FE11h
Description: This register contains information on the capabilities of the PC Card function related to power
management. Both PCI4450 CardBus bridge functions support D0, D1, D2, and D3 power
states.
Table 45. Power Management Capabilities Register Description
BIT
TYPE
FUNCTION
PME support. This 5-bit field indicates the power states from which the PCI4450 device functions may assert PME. A 0b
(zero) for any bit indicates that the function cannot assert the PME signal while in that power state. These five bits return
0Fh when read. Each of these bits is described below:
Bit 15 – defaults to a 1 indicating the PME signal can be asserted from the D3
state. This bit is read/write because
terminals. If the
terminals for D3 wake-upsupport, then
cold
cold
15†
R/W
R
wake-upsupport from D3
cold
is contingent on the system providing an auxiliary power source to the V
CC
system designer chooses not to provide an auxiliary power source to the V
BIOS should write a 0 to this bit.
CC
Bit 14 – contains the value 1 to indicate that the PME signal can be asserted from the D3
state.
hot
14–11
Bit 13 – contains the value 1 to indicate that the PME signal can be asserted from the D2 state.
Bit 12 – contains the value 1 to indicate that the PME signal can be asserted from the D1 state.
Bit 11 – contains the value 1 to indicate that the PME signal can be asserted from the D0 state.
10
9
R
R
R
R
D2_Support. This bit returns a 1 when read, indicating that the function supports the D2 device power state.
D1_Support. This bit returns a 1 when read, indicating that the function supports the D1 device power state.
Reserved. These bits return 000b when read.
8–6
5
DSI. Device specific initialization. This bit returns 0 when read.
AUX_PWR. Auxiliary power source. This bit is meaningful only if bit 15 (D3
supporting PME) is set. When this bit is
requires auxiliary power supplied by the system by way of a proprietary
cold
set, it indicates that support for PME in D3
deliveryvehicle.
cold
4
R
A 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source.
If the function does not support PME while in the D3 state (bit 15=0), then this field must always return 0.
cold
PMECLK.When this bit is 1, it indicates that the function relies on the presence of the PCI clock for PMEoperation.When
this bit is 0, it indicates that no PCI clock is required for the function to generate PME.
3
R
R
Functions that do not support PME generation in any state must return 0 for this field.
Version. These3bitsreturn001bwhenread,indicatingthatthereare4bytesofgeneral-purposepowermanagement(PM)
registers as described in the draft revision 1.0 PCI Bus Power Management Interface Specification.
2–0
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
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SCPS046 – JANUARY 1999
power management control/status register
Bit
15†
14
13
12
11
10
9
8†
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status
R/WC
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Power management control/status
Read-only, Read/Write, Read/Write to Clear
A4h (Functions 0, 1)
000000h
Description: This register determines and changes the current power state of the PCI4450 CardBus
function. The contents of this register are not affected by the internally generated reset
caused by the transition from the D3
to D0 state.
hot
All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3 -to-D0
hot
state transition, with the exception of the PME context bits (if PME is enabled) and the G_RST
only bits.
Table 46. Power Management Control/Status Register Description
BIT
TYPE
FUNCTION
PMESTAT. PME status. This bit is set when the CardBus function would normally assert the PME signal, independent of
thestateofthePME_ENbit. Thisbitisclearedbyawritebackof1, andthisalsoclearsthePMEsignalifPMEwasasserted
by this function. Writing a 0 to this bit has no effect.
15†
R/WC
DATASCALE.This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data, as indicated
by the DYN_DATA bit.
14–13
12–9
R
R
DATASEL. Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data, as
indicated by the DYN_DATA bit.
PME enable. This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This bit
will not be cleared by the assertion of PRST. It will only be cleared by the assertion of G_RST.
8†
R/W
R
7–2
Reserved. These bits return 0s when read.
PWRSTATE. Power state. This 2-bit field is used both to determine the current power state of a function and to set the
functioninto a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
1–0
R/W
11 = D3
hot
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
79
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power management control/status register bridge support extensions
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Powermanagement control/status register bridge support extensions
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Power management control/status register bridge support extensions
Read-only
Offset:
Default:
A6h (Functions 0, 1)
C0h
Description: This register supports PCI bridge specific functionality. It is required for all PCI-to-PCI
bridges.
Table 47. PMCSR_BSE Bridge Support Extensions
BIT
TYPE
FUNCTION
BPCC_Enable.Bus power/clock control enable. This bit returns 1 when read.
This bit is encoded as:
0 = Bus power/clock control is disabled.
1 = Bus power/clock control is enabled (default).
7
R
A 0 indicates that the bus power/clock control policies defined in the PCI Power Management specification are disabled.
Whenthebuspower/clockcontrolenablemechanismisdisabled,thebridge’s PMCSR powerstate field cannot be used by
the system software to control the power or the clock of the bridge’s secondary bus. A 1 indicates that the bus power/clock
control mechanism is enabled. When bus power/clock control is disabled, the bridge’s PMCSR power state field cannot
be used by the system software to control power or the clock of the bridge’s secondary bus.
B2_B3. B2/B3 support for D3 . The state ofthisbitdeterminestheactionthatistooccurasadirectresultofprogramming
hot
the function to D3 . This bit is only meaningful if bit 7 (BPCC_Enable) is a 1. This bit is encoded as:
hot
0 = when the bridge is programmed to D3 , its secondary bus will have its power removed (B3).
6
R
R
hot
1 = when the bridge function is programmed to D3 , its secondary bus’s PCI clock will be stopped (B2).
hot
(Default)
5–0
Reserved. These bits return 0s when read.
80
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
GPE control/status register
Bit
15
14
13
12
11
10‡
9‡
8‡
7
6
5
4
3
2‡
1‡
0‡
Name
Type
Default
GPEcontrol/status
R
0
R
0
R
0
R
0
R
0
R/WC R/WC R/WC
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
0
0
0
Register:
Type:
GPE control/status
Read-only, Read/Write, Read/Write to Clear
Offset:
Default:
A8h
0001h
Description: If the GPE (general-purpose event) function is programmed onto the MFUNC5 pin by writing
101b to bits 22–20 of the multifunction routing register (PCI offset 8Ch), then this register may
be used to program which events will cause GPE to be asserted and report the status.
Table 48. GPE Control/Status Register Description
BIT
15–11
10‡
TYPE
R
FUNCTION
Reserved. These bits return 0s when read.
R/WC
R/WC
ZV1_STS. PC Card socket 1 status. This bit is set on a change in status of the ZVENABLE bit in function 1.
ZV0_STS. PC Card socket 0 status. This bit is set on a change in status of the ZVENABLE bit in function 0.
9‡
VPP12_STS.12-volt V
from 12 volts from either socket.
request status. This bit is set when software has changed the requested V level to or
PP
PP
8‡
7–3
2‡
R/WC
R
Reserved. These bits return 0s when read.
ZV1_EN.PC Card socket 1 zoomed video event enable. When this bit is set, GPE is signaled on a change in status
of the ZVENABLE bit in function 1 of the PC Card controller.
R/W
ZV0_EN.PC Card socket 0 zoomed video event enable. When this bit is set, GPE is signaled on a change in status
of the ZVENABLE bit in function 0 of the PC Card controller.
1‡
0‡
R/W
R/W
VPP12_EN.12 Volt V
request event enable. When this bit is set, a GPE issignaledwhensoftwarehaschanged
level to or from 12 Volts for either socket.
PP
the requested V
PP
‡
This bit is cleared only by the assertion of G_RST.
81
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SCPS046 – JANUARY 1999
ExCA compatibility registers (functions 0 and 1)
The ExCA (exchangeable card architecture) registers implemented in the PCI4450 are register-compatible with
the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible
with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed
through this scheme by writing the register offset value into the index register (I/O base), and reading or writing
the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the
PC Card 16-bit I/F legacy mode base address register, which is shared by both card sockets. The offsets from
this base address run contiguous from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. Refer to
Figure 19 for an ExCA I/O mapping illustration. Table 49 identifies each ExCA register and its respective ExCA
offset.
The TI PCI4450 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI
memory space. They are located through the CardBus socket registers/ExCA registers base address register
(PCI register 10h) at memory offset 800h. Each socket has a separate base address programmable by function.
Refer to Figure 20 for an ExCA memory mapping illustration. Note that memory offsets are 800h–844h for both
functions 0 and 1. This illustration also identifies the CardBus socket register mapping, which is mapped into
the same 4K window at memory offset 0h.
The interrupt registers, as defined by the 82365SL Specification, in the ExCA register set control such card
functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt
routing registers and the host interrupt signaling method selected for the PCI4450 to ensure that all possible
PCI4450 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that
are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h.
Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are
regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte
granularity.
Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows.
These are regions of host memory space into which the card memory space is mapped. These windows are
defined by start, end, and offset addresses programmed in the ExCA registers described in this section.
Memory windows have 4K byte granularity.
A bit location followed by a ‡ means that this bit is not cleared by the assertion of PRST. This bit will only be
cleared by the assertion of G_RST. This is necessary to retain device context when transitioning from D3 to
D0.
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Offset
Host I/O Space
PCI4450Configuration Registers
00h
PC Card A
ExCA
Registers
Card Bus Socket / ExCA Base Address 10h
Index
Data
3Fh
40h
16–bit Legacy Mode Base Address
44h
PC Card B
ExCA
Registers
7Fh
Note: The 16–bit legacy mode base address
register is shared by function 0 and 1 as
indicated by the shading.
Offset of desired register is placed in the Index register and
the data from that location is returned in the data register.
Figure 19. ExCA Register Access Through I/O
Host
Host
MemorySpace
MemorySpace
PCI1450 Configuration Registers
Offset
Offset
00h
Offset
00h
.
.
.
CardBus
Socket A
Registers
10h
44h
CardBus Socket/ExCA Base Address
20h
.
.
CardBus
Socket B
Registers
800h
ExCA
Registers
Card A
16-bit Legacy-Mode Base Address
20h
.
.
.
844h
800h
ExCA
Registers
Card B
Note: The CardBus Socket/ExCA Base
Address Mode Register is separate for
functions 0 and 1.
844h
Offsets are from the CardBus socket/ExCA base
Address register’s base address
Figure 20. ExCA Register Access Through Memory
83
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 49. ExCA Registers and Offsets
PCI
ExCA
OFFSET
(CARD A)
ExCA
OFFSET
(CARD B)
MEMORY
ADDRESS
OFFSET
REGISTER NAME
Identificationandrevision
800
801
802†
803†
804†
805†
806
807
808
809
80A
80B
80C
80D
80E
80F
810
811
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
Interfacestatus
Power control †
Interrupt and general control †
Card status change †
Card status change interrupt configuration †
Address window enable
I / O window control
I / O window 0 start-address low-byte
I / O window 0 start-address high-byte
I / O window 0 end-address low-byte
I / O window 0 end-address high-byte
I / O window 1 start-address low-byte
I / O window 1 start-address high-byte
I / O window 1 end-address low-byte
I / O window 1 end-address high-byte
Memory window 0 start-address low-byte
Memory window 0 start-address high-byte
Memory window 0 end-address low-byte
Memory window 0 end-address high-byte
Memory window 0 offset-addresslow-byte
Memory window 0 offset-addresshigh-byte
Card detect and general control
Reserved
812
813
814
815
816
817
818
819
81A
81B
81C
81D
81E
81F
820
821
822
823
824
825
826
827
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
Memory window 1 start-address low-byte
Memory window 1 start-address high-byte
Memory window 1 end-address low-byte
Memory window 1 end-address high-byte
Memory window 1 offset-addresslow-byte
Memory window 1 offset-addresshigh-byte
Globalcontrol
Reserved
Memory window 2 start-address low-byte
Memory window 2 start-address high-byte
Memory window 2 end-address low-byte
Memory window 2 end-address high-byte
Memory window 2 offset-addresslow-byte
Memory window 2 offset-addresshigh-byte
Reserved
Reserved
†
One or more bits in this register are cleared only by the assertion of G_RST when PME is enabled. If PME is NOT enabled, then this bit is cleared
by the assertion of PRST or G_RST.
84
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 49. ExCA Registers and Offsets (continued)
PCI
ExCA
OFFSET
(CARD A)
ExCA
OFFSET
(CARD B)
MEMORY
ADDRESS
OFFSET
REGISTER NAME
Memory window 3 start-address low-byte
828
829
82A
82B
82C
82D
82E
82F
830
831
832
833
834
835
836
837
838
839
83A
83B
83C
83D
83E
83F
840
841
842
843
844
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
-
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
-
Memory window 3 start-address high-byte
Memory window 3 end-address low-byte
Memory window 3 end-address high-byte
Memory window 3 offset-addresslow-byte
Memory window 3 offset-addresshigh-byte
Reserved
Reserved
Memory window 4 start-address low-byte
Memory window 4 start-address high-byte
Memory window 4 end-address low-byte
Memory window 4 end-address high-byte
Memory window 4 offset-addresslow-byte
Memory window 4 offset-addresshigh-byte
I/O window 0 offset-addresslow-byte
I/O window 0 offset-addresshigh-byte
I/O window 1 offset-addresslow-byte
I/O window 1 offset-addresshigh-byte
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory window page register 0
Memory window page register 1
Memory window page register 2
Memory window page register 3
Memory window page register 4
-
-
-
-
-
-
-
-
85
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ExCA identification and revision register (Index 00h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA identification and revision
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
Register:
Type:
ExCA identification and revision
Read/Write
Offset:
CardBus Socket Address + 800h:
Card A ExCA Offset 00h
Card B ExCA Offset 40h
Default:
84h
Description: This register provides host software with information on 16-bit PC Card support and
82365SL-DF compatibility.
NOTE:
If bit 5 (SUBSYRW) in the system control register is 1, then this register is read-only.
Table 50. ExCA Identification and Revision Register Description
BIT
7–6
5–4
3–0
TYPE
R/W
R/W
R/W
FUNCTION
IFTYPE. Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
PCI4450.The PCI4450 supports both I/O and memory 16-bit PC Cards.
Reserved. These bits can be used for 82365SL emulation.
365REV. 82365SL revision. This field stores the 82365SL revision supported by the PCI4450. Host software may read
this field to determine compatibility to the 82365SL register set. This field defaults to 0100b upon reset.
86
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ExCA interface status register (Index 01h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA interface status
R
0
R
0
R
x
R
x
R
x
R
x
R
x
R
x
Register:
Type:
ExCA interface status
Read-only
Offset:
CardBus Socket Address + 801h:
Card A ExCA Offset 01h
Card B ExCA Offset 41h
Default:
00XX XXXXb
Description: This register provides information on current status of the PC Card interface. An x in the
default bit values indicates that the value of the bit after reset depends on the state of the PC
Card interface.
Table 51. ExCA Interface Status Register Description
BIT
TYPE
FUNCTION
Reserved. This bit returns 0 when read. A write has no effect.
7
R
CARDPWR.Card power. This bit indicates the current power status of the PC Card socket. This bit reflects how the ExCA
powercontrol register has been programmed. The bit is encoded as:
6
5
R
R
0 = V
1 = V
and V
and V
to the socket is turned off(default).
to the socket is turned on.
CC
CC
PP
PP
READY. This bit indicates the current status of the READY signal at the PC Card interface.
0 = PC Card is not ready for a data transfer.
1 = PC Card is ready for a data transfer.
CARDWP. Card write protect. This bit indicates the current status of the WP signal at the PC Card interface. This signal
reports to the PCI4450 whether or not the memory card is write protected. Further, write protection for an entire PCI4450
16-bit memory window is available by setting the appropriate bit in the ExCA memory window offset-address high byte
register.
4
R
0 = WP signal is 0. PC Card is R/W.
1 = WP signal is 1. PC Card is read-only.
CDETECT2.Card detect 2. This bit indicates the status of the CD2 signal at the PC Card interface. Software may use this
and CDETECT1 to determine if a PC Card is fully seated in the socket.
0 = CD2 signal is 1. No PC Card inserted.
3
2
R
R
1 = CD2 signal is 0. PC Card at least partially inserted.
CDETECT1.Card detect 1. This bit indicates the status of the CD1 signal at the PC Card interface. Software may use this
and CDETECT2 to determine if a PC Card is fully seated in the socket.
0 = CD1 signal is 1. No PC Card inserted.
1 = CD1 signal is 0. PC Card at least partially inserted.
BVDSTAT.Batteryvoltagedetect.Whena16-bitmemorycardisinserted,thefieldindicatesthestatusofthebatteryvoltage
detect signals (BVD1, BVD2) at the PC Card interface, where bit 0 reflects the BVD1 status, and bit 1 reflects BVD2.
00 = Battery is dead.
01 = Battery is dead.
10 = Battery is low; warning.
1–0
R
11 = Battery is good.
When a 16-bit I/O card is inserted, this field indicates the status of the SPKR (bit 1) signal and the STSCHG (bit 0) at the
PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.
87
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ExCA power control register (Index 02h)
Bit
7
6
5
4†
3†
2
1†
0†
Name
Type
Default
ExCA power control
R/W
0
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
Register:
Type:
ExCA power control
Read-only, Read/Write
Offset:
CardBus Socket Address + 802h:
Card A ExCA Offset 02h
Card B ExCA Offset 42h
Default:
00h
Description: This register provides PC Card power control. Bit 7 of this register controls the 16-bit output
enables on the socket interface, and can be used for power management in 16-bit PC Card
applications.
Table 52. ExCA Power Control Register Description
BIT
7†
TYPE
R/W
R
FUNCTION
COE. Card output enable. This bit controls the state of all of the 16-bit outputs on the PCI4450. This bit is encoded as:
0 = 16-bit PC Card outputs are disabled (default).
1 = 16-bit PC Card outputs are enabled.
6–5
Reserved. These bits return 0s when read. Writes have no effect.
EXCAVCC. V . These bits are used to request changes to card V . This field is encoded as:
CC
CC
00 = 0 V (default)
01 = 0 V Reserved
10 = 5 V
11 = 3 V
4–3†
2
R/W
R
Reserved. This bit returns 0 when read. A write has no effect.
EXCAVPP.V .ThesebitsareusedtorequestchangestocardV .ThePCI4450ignoresthisfieldunlessV tothesocket
CC
PP
PP
is enabled (i.e., 5 Vdc or 3.3 Vdc). This field is encoded as:
00 = 0 V (default)
1–0†
R/W
01 = V
CC
10 = 12 V
11 = 0 V Reserved
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
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ExCA interrupt and general control register (Index 03h)
Bit
7
6†
5†
4
3
2
1
0
Name
Type
Default
ExCA interrupt and general control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA interrupt and general control
Read/Write
Offset:
CardBus Socket Address + 803h:
Card A ExCA Offset 03h
Card B ExCA Offset 43h
Default:
00h
Description: This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card
functions.
Table 53. ExCA Interrupt and General Control Register Description
BIT
TYPE
FUNCTION
RINGEN. Card ring indicate enable. Enables the ring indicate function of the BVD1/RI pins. This bit is encoded as:
7
R/W
0 = Ring indicate disabled (default)
1 = Ring indicate enabled
Cardreset.Thisbitcontrolsthe16-bitPCCardRESETsignal,andallowshostsoftwaretoforceacardreset.Thisbitaffects
16-bit cards only. This bit is encoded as:
6†
5†
R/W
R/W
0 = RESET signal asserted (default)
1 = RESET signal deasserted.
CARDTYPE. Card type. This bit indicates the PC Card type. This bit is encoded as:
0 = Memory PC Card is installed (default)
1 = I/O PC Card is installed
CSCROUTE.PCI interrupt – CSC routing enable bit. This bit has meaning only if the CSC interrupt routing control bit (PCI
offset 93h, bit 5) is 0b. In this case, when this bit is set (high), the card status change interrupts are routed to PCI interrupts.
Whenlowthecardstatuschangeinterruptsarerouted,usingbits7–4intheExCAcardstatuschangeinterruptconfiguration
register. This bit is encoded as:
4
R/W
0 = CSC interrupts routed by ExCA registers (default)
1 = CSC interrupts routed to PCI interrupts
If the CSC interrupt routing control bit (PCI offset 93h, bit 5) is set to 1b, this bit has no meaning which is the default case.
INTSELECT. Card interrupt select for I/O PC Card functional interrupts. These bits select the interrupt routing for I/O PC
Card functional interrupts. This field is encoded as:
0000 = No ISA interrupt routing (default). CSC interrupts routed to PCI Interrupts.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
3–0
R/W
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
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ExCA card status-change register (Index 04h)
Bit
7
6
5
4
3†
2†
1†
0†
Name
Type
Default
ExCA card status-change
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
ExCA card status-change
Read-only
Offset:
CardBus Socket Address + 804h:
Card A ExCA Offset 04h
Card B ExCA Offset 44h
Default:
00h
Description: This register reflects the status of PC Card CSC interrupt sources. The ExCA card status
change interrupt configuration register enables these interrupt sources to generate an
interrupt to the host. When the interrupt source is disabled, the corresponding bit in this
register always reads as 0. When an interrupt source is enabled and that particular event
occurs, the corresponding bit in this register is set to indicate the interrupt source. After
generating the interrupt to the host, the interrupt service routine must read this register to
determine the source of the interrupt. The interrupt service routine is responsible for resetting
the bits in this register, as well. Resetting a bit is accomplished by one of two methods: a read
of this register, or an explicit write back of 1 to the status bit. The choice of these two methods
is based on the interrupt flag clear mode select, bit 2, in the ExCA global control register.
Table 54. ExCA Card Status-Change Register Description
BIT
TYPE
FUNCTION
7–4
R
Reserved. These bits return 0s when read. Writes have no effect.
CDCHANGE.Carddetectchange. ThisbitindicateswhetherachangeontheCD1orCD2signalsoccurredatthePCCard
interface.A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:
0 = No change detected on either CD1 or CD2
3†
2†
R
R
1 = A change was detected on either CD1 or CD2
READYCHANGE. Ready change. When a 16-bit memory is installed in the socket, this bit includes whether the source
of a PCI4450 interrupt was due to a change on the READY signal at the PC Card interface indicating that PC Card is now
ready to accept new data. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:
0 = No low-to-high transition detected on READY (default)
1 = Detected a low-to-high transition on READY
When a 16-bit I/O card is installed, this bit is always 0.
BATWARN. Battery warning change. When a 16-bit memory card is installed in the socket, this bit indicates whether the
source of a PCI4450 interrupt was due to a battery low warning condition. A read of this bit or writing a 1 to this bit clears
it. This bit is encoded as:
0 = No battery warning condition (default)
1 = Detected a battery warning condition
When a 16-bit I/O card is installed, this bit is always 0.
1†
0†
R
R
BATDEAD. Battery dead or status change. When a 16-bit memory card is installed in the socket, this bit indicates whether
the source of a PCI4450 interrupt was due to a battery dead condition. A read of this bit or writing a 1 tothisbitclearsit. This
bit is encoded as:
0 = STSCHG deasserted (default)
1 = STSCHG asserted
Ring indicate. When the PCI4450 is configured for ring indicate operation this bit indicates the status of the RI pin.
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
90
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ExCA card status-change interrupt configuration register (Index 05h)
Bit
7
6
5
4
3†
2†
1†
0†
Name
Type
Default
ExCA card status-change interrupt configuration
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA card status-change interrupt configuration
Read/Write
Offset:
CardBus Socket Address + 805h:
Card A ExCA Offset 05h
Card B ExCA Offset 45h
Default:
00h
Description: This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC
interrupt sources.
Table 55. ExCA Card Status-Change Interrupt Register Description
BIT
TYPE
FUNCTION
CSCSELECT. Interrupt select for card status change. These bits select the interrupt routing for card status change
interrupts.This field is encoded as:
0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) is set to 1b.
In this case bit 4 of ExCA 803 is a “don’t care.” This is the default setting.
0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI offset 93h) is set to 0b. In this case,
CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h to 1b
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
7–4
R/W
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
CDEN. Card detect enable. Enables interrupts on CD1 or CD2 changes. This bit is encoded as:
0 = Disables interrupts on CD1 or CD2 line changes (default)
3†
2†
R/W
R/W
1 = Enable interrupts on CD1 or CD2 line changes
READYEN. Ready enable. This bit enables/disables a low-to-high transition on the PC Card READY signal to generate a
host interrupt. This interrupt source is considered a card status change. This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
BATWARNEN. Battery warning enable. This bit enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
1†
0†
R/W
R/W
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
BATDEADEN. Battery dead enable. This bit enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
91
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ExCA address window enable register (Index 06h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA address window enable
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA address window enable
Read-only, Read/Write
Offset:
CardBus Socket Address + 806h:
Card A ExCA Offset 06h
Card B ExCA Offset 46h
Default:
00h
Description: This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default,
all windows to the card are disabled. The PCI4450 will not acknowledge PCI memory or I/O
cycles to the card if the corresponding enable bit in this register is 0, regardless of the
programming of the ExCA memory and I/O window start/end/offset address registers.
Table 56. ExCA Address Window Enable Register Description
BIT
TYPE
FUNCTION
IOWIN1EN. I/O window 1 enable. This bit enables/disables I/O window 1 for the card. This bit is encoded as:
7
R/W
0 = I/O window 1 disabled (default)
1 = I/O window 1 enabled
IOWIN0EN. I/O window 0 enable. This bit enables/disables I/O window 0 for the card. This bit is encoded as:
6
5
4
R/W
R
0 = I/O window 0 disabled (default)
1 = I/O window 0 enabled
Reserved. This bit returns 0 when read. A write has no effect.
MEMWIN4EN.Memory window 4 enable. This bit enables/disables memory window 4 for the card. This bit is encoded as:
0 = memory window 4 disabled (default)
R/W
1 = memory window 4 enabled
MEMWIN3EN.Memory window 3 enable. This bit enables/disables memory window 3 for the card. This bit is encoded as:
0 = memory window 3 disabled (default)
3
2
R/W
R/W
1 = memory window 3 enabled
MEMWIN2EN.Memory window 2 enable. This bit enables/disables memory window 2 for the card. This bit is encoded as:
0 = memory window 2 disabled (default)
1 = memory window 2 enable
MEMWIN1EN. Memory window 1 enable. This bit enables/disables memory window 1 for the PC Card.
This bit is encoded as:
1
0
R/W
R/W
0 = memory window 1 disabled (default)
1 = memory window 1 enabled
MEMWIN0EN. Memory window 0 enable. This bit enables/disables memory window 0 for the PC Card.
This bit is encoded as:
0 = memory window 0 disabled (default)
1 = memory window 0 enabled
92
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ExCA I/O window control register (Index 07h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA I/O window control
Read/Write
Offset:
CardBus Socket Address + 807h:
Card A ExCA Offset 07h
Card B ExCA Offset 47h
Default:
00h
Description: This register contains parameters related to I/O window sizing and cycle timing.
Table 57. ExCA I/O Window Control Register Description
BIT
TYPE
FUNCTION
WAITSTATE1. I/O window 1 wait-state. This bit controls the I/O window 1 wait-state for 16-bit I/O accesses. This bit has
no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.
This bit is encoded as:
7
R/W
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles extended by one equivalent ISA wait state
ZEROWS1. I/O window 1 zero wait-state. This bit controls the I/O window 1 wait-state for 8-bit I/O accesses.
NOTE:Thisbithasnoeffecton16-bitaccesses.Thiswait-statetimingemulatestheISAwait-stateusedbythe82365SL-DF.
0 = 8-bit cycles have standard length (default)
6
5
4
R/W
R/W
R/W
1 = 8-bit cycles reduced to equivalent of three ISA cycles
IOSIS16W1. I/O window 1 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used the
IOIS16 signal from the PC Card to determine the data width of the I/O data transfer.
0 = Data width determined by DATASIZE1, bit 4 (default)
1 = Window data width determined by IOIS16
DATASIZE1.I/Owindow1datasize.ThisbitcontrolstheI/Owindow1datasize.ThisbitisignorediftheI/Owindow1IOIS16
source bit (bit 5) is set. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
WAITSTATE0. I/O window 0 wait-state. This bit controls the I/O window 0 wait-state for 16-bit I/O accesses. This bit has
no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.
This bit is encoded as:
3
R/W
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles extended by one equivalent ISA wait state
ZEROWS0. I/O window 0 zero wait-state. This bit controls the I/O window 0 wait-state for 8-bit I/O accesses.
NOTE:Thisbithasnoeffecton16-bitaccesses.Thiswait-statetimingemulatestheISAwait-stateusedbythe82365SL-DF.
0 = 8-bit cycles have standard length (default)
2
1
0
R/W
R/W
R/W
1 = 8-bit cycles reduced to equivalent of three ISA cycles
IOIS16W0. I/O window 0 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used the
IOIS16 signal from the PC Card to determine the data width of the I/O data transfer.
0 = Data width determined by DATASIZE0, bit 0 (default)
1 = Window data width determined by IOIS16
DATASIZE0.I/Owindow0datasize.ThisbitcontrolstheI/Owindow1datasize.ThisbitisignorediftheI/Owindow1IOIS16
Source bit (bit 1) is set. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
93
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ExCA I/O window 0 & 1 start-address low-byte register (Index 08h, 0Ch)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window 0 & 1 start-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 start-address low-byte
CardBus Socket Address + 808h:
Card A ExCA Offset 08h
Card B ExCA Offset 48h
Register:
Offset:
ExCA I/O window 1 start-address low-byte
CardBus Socket Address + 80Ch:
Card A ExCA Offset 0Ch
Card B ExCA Offset 4Ch
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the low-byte of the 16-bit I/O window start address for I/O windows 0
and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address.
ExCA I/O window 0 & 1 start-address high-byte register (Index 09h, ODh)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window 0 & 1 start-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 start-address high-byte
CardBus Socket Address + 809h:
Card A ExCA Offset 09h
Card B ExCA Offset 49h
Register:
Offset:
ExCA I/O window 1 start-address high-byte
CardBus Socket Address + 80Dh:
Card A ExCA Offset 0Dh
Card B ExCA Offset 4Dh
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the high-byte of the 16-bit I/O window start address for I/O windows 0
and 1. The 8 bits of these registers correspond to the upper 8 bits of the start address.
94
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ExCA I/O window 0 & 1 end-address low-byte register (Index 0Ah, 0Eh)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window 0 & 1 end-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 end-address low-byte
CardBus Socket Address + 80Ah:
Card A ExCA Offset 0Ah
Card B ExCA Offset 4Ah
Register:
Offset:
ExCA I/O window 1 end-address low-byte
CardBus Socket Address + 80Eh:
Card A ExCA Offset 0Eh
Card B ExCA Offset 4Eh
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the low-byte of the 16-bit I/O window end address for I/O windows 0
and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address.
ExCA I/O window 0 & 1 end-address high-byte register (Index 0Bh, 0Fh)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window 0 & 1 end-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 end-address high-byte
CardBus Socket Address + 80Bh:
Card A ExCA Offset 0Bh
Card B ExCA Offset 4Bh
Register:
Offset:
ExCA I/O window 1 end-address high-byte
CardBus Socket Address + 80Fh:
Card A ExCA Offset 0Fh
Card B ExCA Offset 4Fh
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the high-byte of the 16-bit I/O window end address for I/O windows 0
and 1. The eight bits of these registers correspond to the upper eight bits of the end address.
95
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ExCA memory window 0–4 start-address low-byte register (Index 10h/18h/20h/28h/30h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0–4 start-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 start-address low-byte
CardBus Socket Address + 810h:
Card A ExCA Offset 10h
Card B ExCA Offset 50h
Register:
Offset:
ExCA memory window 1 start-address low-byte
CardBus Socket Address + 818h: Card A ExCA Offset 18h
Card B ExCA Offset 58h
ExCA memory window 2 start-address low-byte
CardBus Socket Address + 820h: Card A ExCA Offset 20h
Card B ExCA Offset 60h
ExCA memory window 3 start-address low-byte
CardBus Socket Address + 828h: Card A ExCA Offset 28h
Card B ExCA Offset 68h
ExCA memory window 4 start-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 830h:
Card A ExCA Offset 30h
Card B ExCA Offset 70h
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the low-byte of the 16-bit memory window start address for memory
windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of the start
address.
96
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ExCA memory window 0–4 start-address high-byte register (Index 11h/19h/21h/29h/31h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0–4 start-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 start-address high-byte
CardBus Socket Address + 811h:
Card A ExCA Offset 11h
Card B ExCA Offset 51h
Register:
Offset:
ExCA memory window 1 start-address high-byte
CardBus Socket Address + 819h: Card A ExCA Offset 19h
Card B ExCA Offset 59h
ExCA memory window 2 start-address high-byte
CardBus Socket Address + 821h: Card A ExCA Offset 21h
Card B ExCA Offset 61h
ExCA memory window 3 start-address high-byte
CardBus Socket Address + 829h: Card A ExCA Offset 29h
Card B ExCA Offset 69h
ExCA memory window 4 start-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 831h:
Card A ExCA Offset 31h
Card B ExCA Offset 71h
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the high-nibble of the 16-bit memory window start address for
memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits
A23–A20 of the start address. In addition, the memory window data width and wait states are
set in this register.
Table 58. ExCA Memory Window 0–4 Start-Address High-Byte Register Description
BIT
TYPE
FUNCTION
DATASIZE. This bit controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default)
7
R/W
1 = Window data width is 16 bits
ZEROWAIT.Zerowait-state.Thisbitcontrolsthememorywindowwaitstatefor8-and16-bitaccesses.Thiswaitstatetiming
emulatesthe ISA wait-state used by the 82365SL-DF. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default)
6
R/W
1 = 8-bit cycles reduced to equivalent of three ISA cycles
16-bit cycles reduce to the equivalent of two ISA cycles.
5–4
3–0
R/W
R/W
SCRATCH. Scratch pad bits. These bits have no effect on memory window operation.
STAHN. Start address high-nibble. These bits represent the upper address bits A23–A20 of the memory window start
address.
97
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ExCA memory window 0–4 end-address low-byte register (Index 12h/1Ah/22h/2Ah/32h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0–4 end-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 end-address low-byte
CardBus Socket Address + 812h:
Card A ExCA Offset 12h
Card B ExCA Offset 52h
Register:
Offset:
ExCA memory window 1 end-address low-byte
CardBus Socket Address + 81Ah: Card A ExCA Offset 1Ah
Card B ExCA Offset 5Ah
ExCA memory window 2 end-address low-byte
CardBus Socket Address + 822h: Card A ExCA Offset 22h
Card B ExCA Offset 62h
ExCA memory window 3 end-address low-byte
CardBus Socket Address + 82Ah: Card A ExCA Offset 2Ah
Card B ExCA Offset 68h
ExCA memory window 4 end-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 832h:
Card A ExCA Offset 32h
Card B ExCA Offset 72h
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the low-byte of the 16-bit memory window end address for memory
windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of the end
address.
98
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ExCA memory window 0–4 end-address high-byte register (Index 13h/1Bh/23h/2Bh/33h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0–4 end-address high-byte
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 end-address high-byte
CardBus Socket Address + 813h:
Card A ExCA Offset 13h
Card B ExCA Offset 53h
Register:
Offset:
ExCA memory window 1 end-address high-byte
CardBus Socket Address + 81Bh: Card A ExCA Offset 1Bh
Card B ExCA Offset 5Bh
ExCA memory window 2 end-address high-byte
CardBus Socket Address + 823h: Card A ExCA Offset 23h
Card B ExCA Offset 63h
ExCA memory window 3 end-address high-byte
CardBus Socket Address + 82Bh: Card A ExCA Offset 2Bh
Card B ExCA Offset 6Bh
ExCA Memory window 4 end-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 833h:
Card A ExCA Offset 33h
Card B ExCA Offset 73h
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the high-nibble of the 16-bit memory window end address for memory
windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the
end address. In addition, the memory window wait states are set in this register.
Table 59. ExCA Memory Window 0–4 End-Address High-Byte Register Description
BIT
7–6
5–4
3–0
TYPE
R/W
R
FUNCTION
MEMWS.Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory accesses.
The number of wait states added is equal to the binary value of these two bits.
Reserved. These bits return 0s when read. Writes have no effect.
ENDHN. End address high-nibble. These bits represent the upper address bits A23–A20 of the memory window and
address.
R/W
99
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SCPS046 – JANUARY 1999
ExCA memory window 0–4 offset-address low-byte register (Index 14h/1Ch/24h/2Ch/34h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0–4 offset-addresslow-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 offset-address low-byte
CardBus Socket Address + 814h:
Card A ExCA Offset 14h
Card B ExCA Offset 54h
Register:
Offset:
ExCA memory window 1 offset-address low-byte
CardBus Socket Address + 81Ch: Card A ExCA Offset 1Ch
Card B ExCA Offset 5Ch
ExCA memory window 2 offset-address low-byte
CardBus Socket Address + 824h: Card A ExCA Offset 24h
Card B ExCA Offset 64h
ExCA memory window 3 offset-address low-byte
CardBus Socket Address + 82Ch: Card A ExCA Offset 2Ch
Card B ExCA Offset 6Ch
ExCA memory window 4 offset-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 834h:
Card A ExCA Offset 34h
Card B ExCA Offset 74h
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the low-byte of the 16-bit memory window offset address for memory
windows0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of theoffset
address.
100
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SCPS046 – JANUARY 1999
ExCA memory window 0–4 offset-address high-byte register (15h/1Dh/25h/2Dh/35h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0–4 offset-addresshigh-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 offset-address high-byte
CardBus Socket Address + 815h:
Card A ExCA Offset 15h
Card B ExCA Offset 55h
Register:
Offset:
ExCA memory window 1 offset-address high-byte
CardBus Socket Address + 81Dh: Card A ExCA Offset 1Dh
Card B ExCA Offset 5Dh
ExCA memory window 2 offset-address high-byte
CardBus Socket Address + 825h: Card A ExCA Offset 25h
Card B ExCA Offset 65h
ExCA memory window 3 offset-address high-byte
CardBus Socket Address + 82Dh: Card A ExCA Offset 2Dh
Card B ExCA Offset 6Dh
ExCA memory window 4 offset-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 835h:
Card A ExCA Offset 35h
Card B ExCA Offset 75h
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the high 6 bits of the 16-bit memory window offset address for
memory windows 0, 1, 2, 3, and 4. The lower 6 bits of these registers correspond to bits
A25–A20 of the offset address. In addition, the write protection and common/attribute
memory configurations are set in this register.
Table 60. ExCA Memory Window 0–4 Offset-Address High-Byte Register Description
BIT
TYPE
FUNCTION
WINWP. Write protect. This bit specifies whether write operations to this memory window are enabled.
This bit is encoded as:
7
R/W
0 = Write operations are allowed (default)
1 = Write operations are not allowed
REG. This bit specifies whether this memory window is mapped to card attribute or common memory.
This bit is encoded as:
6
R/W
R/W
0 = Memory window is mapped to common memory (default)
1 = Memory window is mapped to attribute memory
OFFHB. Offset address high-byte. These bits represent the upper address bits A25–A20 of the memory window offset
address.
5–0
101
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
ExCA I/O window 0 & 1 offset-address low-byte register (Index 36h, 38h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window 0 & 1 offset-addresslow-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 offset-address low-byte
CardBus Socket Address + 836h:
Card A ExCA Offset 36h
Card B ExCA Offset 76h
Register:
Offset:
ExCA memory window 1 offset-address low-byte
CardBus Socket Address + 838h:
Card A ExCA Offset 38h
Card B ExCA Offset 78h
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the low-byte of the 16-bit I/O window offset address for I/O windows 0
and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit
0 is always 0.
ExCA I/O window 0 & 1 offset-address high-byte register (Index 37h, 39h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window 0 & 1 offset-addresshigh-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 offset-address high-byte
CardBus Socket Address + 837h:
Card A ExCA Offset 37h
Card B ExCA Offset 77h
Register:
Offset:
ExCA memory window 1 offset-address high-byte
CardBus Socket Address + 839h:
Card A ExCA Offset 39h
Card B ExCA Offset 79h
Type:
Default:
Size:
Read/Write
00h
One byte
Description: These registers contain the high-byte of the 16-bit I/O window offset address for I/O windows
0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the offset address.
102
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SCPS046 – JANUARY 1999
ExCA card detect and general control register (Index 16h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card detect and general control
R
X
R
X
W
0
R/W
0
R
0
R
0
R/W
0
R
0
Register:
Type:
Offset:
ExCA card detect and general control
Read-only, Write-only, Read/Write
CardBus Socket Address + 816h:
Card A ExCA Offset 16h
Card B ExCA Offset 56h
Default:
XX00 0000b
Description: This register controls how the ExCA registers for the socket respond to card removal. It also
reports the status of the VS1 and VS2 signals at the PC Card interface. Table 61 describes
each bit in the ExCA card detect and general control register.
Table 61. ExCA Card Detect and General Control Register Description
BIT
TYPE
FUNCTION
VS2STAT. VS2. This bit reports the current state of the VS2 signal at the PC Card interface, and, therefore, does not have
a default value.
0 = VS2 is low
1 = VS2 is high
7
R
VS1STAT. VS1. This bit reports the current state of the VS1 signal at the PC Card interface, and, therefore, does not have
a default value.
0 = VS1 is low
1 = VS1 is high
6
5
R
SWCSC. Software card detect interrupt. If the card detect enable bit in the ExCA card status change interrupt
configurationregister is set, then writing a 1 to this bit causes a card detect card status change interrupt for the associated
card socket.
If the card detect enable bit is cleared to 0 in the ExCA card status change interrupt configuration register, then writing a
1 to the software card detect interrupt bit has no effect. This bit is write-only.
W
A read operation of this bit always returns 0. Writing a 1 to this bit also clears it. If bit 2 of the ExCA global control register
is set and a 1 is written to clear bit 3 of the ExCA card status change interrupt register, then this bit also gets cleared.
CDRESUME. Card detect resume enable. If this bit is set to 1 and once a card detect change has been detected on the
CD1 and CD2 inputs, then the RI_OUT output will go from high to low. The RI_OUT remains low until the card status
changebit in the ExCA card status change register is cleared. If this bit is a 0, then the card detect resume functionality
isdisabled.
4
R/W
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
3–2
1
R
R/W
R
Reserved. These bits return 0s when read. Writes have no effect.
REGCONFIG. Register configuration upon card removal. This bit controls how the ExCA registers for the socket react to
a card removal event. This bit is encoded as:
0 = No change to ExCA registers upon card removal (default)
1 = Reset ExCA registers upon card removal
0
Reserved. This bit returns 0 when read. A write has no effect.
103
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ExCA global control register (Index 1Eh)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA global control
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA global control
Read-only, Read/Write
Offset:
CardBus Socket Address + 81Eh:
Card A ExCA Offset 1Eh
Card B ExCA Offset 5Eh
Default:
00h
Description: This register controls both PC Card sockets, and is not duplicated for each socket. The host
interrupt mode bits in this register are retained for 82365SL compatibility.
Table 62. ExCA Global Control Register Description
BIT
TYPE
FUNCTION
7–5
R
Reserved. These bits return 0s when read. Writes have no effect.
INTMODEB.Level/edge interrupt mode select – card B. This bit selects the signaling mode for the PCI4450 host interrupt
for Card B interrupts. This bit is encoded as:
4
3
2
1
R/W
R/W
R/W
R/W
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
INTMODEA. Level/edge interrupt mode select – card A. This bit selects the signaling mode for the PCI4450 host interrupt
for card A interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
IFCMODE. Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register. This bit is encoded as:
0 = Interrupt flags cleared by read of CSC register (default)
1 = Interrupt flags cleared by explicit write back of 1
CSCMODE. Card status change level/edge mode select. This bit selects the signaling mode for the PCI4450 host
interrupt for card status changes. This bit is encoded as:
0 = Host interrupt is edge mode (default)
1 = Host interrupt is level mode
PWRDWN. PWRDWN mode select. When the bit is set to 1, the PCI4450 is in power-down mode. In power-down mode
the PCI4450 card outputs are placed in a high-impedance state until an active cycle is executed on the card interface.
Followinganactivecycletheoutputsareagainplacedinahigh-impedancestate. ThePCI4450stillreceivesDMArequests,
functionalinterrupts and/or card status change interrupts; however, an actual card access is required to “wake up” the
interface.This bit is encoded as:
0
R/W
0 = Power-down mode disabled (default)
1 = Power-down mode enabled
104
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
ExCA memory window 0–4 page register (Index 40h, 41h, 42h, 43h, 44h)
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0–4 page
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA memory window 0–4 page
Read/Write
Offset:
Default:
CardBus Socket Address + 840h, 841h, 842h, 843h, 844h
00h
Description: The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register
when decoding addresses for 16-bit memory windows. Each window has its own page
register, all of which default to 00h. By programming this register to a nonzero value, host
software may locate 16-bit memory windows in any one of 256 16M-byte regions in the 4
Gigabyte PCI address space. These registers are only accessible when the ExCA registers
are memory mapped, that is, these registers may not be accessed using the index/data I/O
scheme.
105
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PC Card and OHCI Controller
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CardBus socket registers (functions 0 and 1)
The PCMCIA CardBus Specification requires a CardBus socket controller to provide five 32-bit registers which
report and control the socket-specific functions. The PCI4450 provides the CardBus socket/ExCA base
address register (PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each
socket has a separate base address register for accessing the CardBus socket registers, see Figure 21 below.
Table 63 illustrates the location of the socket registers in relation to the CardBus socket/ExCA base address.
Table 63. CardBus Socket Registers
REGISTER NAME
Socket event †
OFFSET
00h
Socket mask †
04h
Socket present state †
Socket force event
Socket control †
Reserved
08h
0Ch
10h
14h
Reserved
18h
Reserved
1Ch
20h
Socketpowermanagement
†
One or more bits in this register are cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared
by the assertion of PRST or G_RST.
Host
Host
MemorySpace
MemorySpace
PCI1450 Configuration Registers
Offset
00h
Offset
00h
.
.
.
CardBus
Socket A
Registers
10h
44h
CardBus Socket/ExCA Base Address
20h
.
.
CardBus
Socket B
Registers
800h
ExCA
Registers
Card A
16-bit Legacy-Mode Base Address
20h
.
.
.
844h
800h
ExCA
Registers
Card B
Note: The CardBus Socket/ExCA Base
Address Mode Register is separate for
functions 0 and 1.
844h
Figure 21. Accessing CardBus Socket Registers Through PCI Memory
106
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
socket event register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
R
0
R
0
R
0
15
14
13
12
11
10
3†
2†
1†
0†
Name
Type
Default
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/WC R/WC R/WC R/WC
0
0
0
0
Register:
Type:
Offset:
Default:
Socket event
Read-only, Read/Write to Clear
CardBus Socket Address + 00h
0000 0000h
Description: This register indicates a change in socket status has occurred. These bits donotindicatewhat
the change is, only that one has occurred. Software must read the socket present state
register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The
bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in
the socket force event register. All bits in this register are cleared by PCI reset. They may be
immediately set again, if, when coming out of PC Card reset, the bridge finds the status
unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software needs to clear
this register before enabling interrupts. If it is not cleared and interrupts are enabled, then an
interrupt is generated based on any bit set and not masked.
Table 64. Socket Event Register Description
BIT
TYPE
FUNCTION
31–4
R
Reserved. These bits return 0s when read.
PWREVENT. Power cycle. This bit is set when the PCI4450 detects that the PWRCYCLE bit in the socket present state
register has changed. This bit is cleared by writing a 1.
3†
2†
1†
R/WC
R/WC
R/WC
CD2EVENT. CCD2. This bit is set when the PCI4450 detects that the CDETECT2 field in the socket present state
register has changed. This bit is cleared by writing a 1.
CD1EVENT. CCD1. This bit is set when the PCI4450 detects that the CDETECT1 field in the socket present state
register has changed. This bit is cleared by writing a 1.
CSTSEVENT. CSTSCHG. This bit is set when the CARDSTS field in the socket present state register has changed
state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG signal. For 16-bit PC Cards, this bit is set on
both transitions of the CSTSCHG signal. This bit is reset by writing a 1.
0†
R/WC
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
107
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
socket mask register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
R
0
R
0
R
0
15
14
13
12
11
10
3†
2†
1†
0†
Name
Type
Default
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Socket mask
Read-only, Read/Write
Offset:
Default:
CardBus Socket Address + 04h
0000 0000h
Description: This register allows software to control the CardBus card events which generate a status
change interrupt. Table 65 below describes each bit in this register. The state of these mask
bits does not prevent the corresponding bits from reacting in the socket event register.
Table 65. Socket Mask Register Description
BIT
TYPE
FUNCTION
31–4
R
Reserved. These bits return 0s when read.
PWRMASK. Power cycle. This bit masks the PWRCYCLE bit in the socket present state register from causing a status
changeinterrupt.
3†
2–1†
0†
R/W
R/W
R/W
0 = PWRCYCLE event will not cause a CSC interrupt (default)
1 = PWRCYCLE event will cause a CSC interrupt
CDMASK. Card detect mask. These bits mask the CDETECT1 and CDETECT2 bits in the socket present state register
from causing a CSC interrupt.
00 = Insertion/removal will not cause CSC interrupt (default)
01 = Reserved (undefined)
10 = Reserved (undefined)
11 = Insertion/removal will cause CSC interrupt
CSTSMASK. CSTSCHG mask. This bit masks the CARDSTS field in the socket present state register from causing a
CSCinterrupt.
0 = CARDSTS event will not cause CSC interrupt (default)
1 = CARDSTS event will cause CSC interrupt
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
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socket present state register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket present state
R
0
R
0
R
1
R
1
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket present state
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
0
R
0
R
0
R
X
R
X
R
X
Register:
Type:
Socket present state
Read-only
Offset:
Default:
CardBus Socket Address + 08h
3000 00XXh
Description: This register reports information about the socket interface. Writes to the socket force event
register are reflected here as well as general socket interface status. Information about PC
Card V support and card type is only updated at each insertion. Also note that the PCI4450
CC
uses the CCD1 and CCD2 signals during card identification, and changes on these signals
during this operation are not reflected in this register.
Table 66. Socket Present State Register Description
BIT
TYPE
FUNCTION
YVSOCKET.YVsocket.ThisbitindicateswhetherornotthesocketcansupplyV
CC
=Y.YVtoPCCards.ThePCI4450does
not support Y.YV V ; therefore, this bit is always reset unless overridden by the socket force event register. This bit is
CC
31
R
hardwired to 0.
XVSOCKET.XVsocket.ThisbitindicateswhetherornotthesocketcansupplyV
CC
=X.XVtoPCCards.ThePCI4450does
not support X.XV V ; therefore, this bit is always reset unless overridden by the socket force event register. This bit is
CC
30
29
R
R
hardwired to 0.
3VSOCKET. 3-V socket. This bit indicates whether or not the socket can supply V
PCI4450does support 3.3 V V ; therefore, this bit is always set unless overridden by the socket force event register.
CC
= 3.3 Vdc to PC Cards. The
CC
5VSOCKET. 5-V socket. This bit indicates whether or not the socket can supply V
PCI4450does support 5.0 V V ; therefore, this bit is always 1 unless overridden by the device control register (bit 6).
CC
= 5.0 Vdc to PC Cards. The
CC
28
27–14
13
R
R
R
Reserved. These bits return 0s when read.
YVCARD. YV card. This bit indicates whether or not the PC Card inserted in the socket supports V
can be set by writing to the corresponding bit in the socket force event register.
= Y.Y Vdc. This bit
= X.X Vdc. This bit
= 3.3 Vdc. This bit
CC
XVCARD. XV card. This bit indicates whether or not the PC Card inserted in the socket supports V
can be set by writing to the corresponding bit in the socket force event register.
CC
12
R
3VCARD. 3-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
can be set by writing to the corresponding bit in the socket force event register.
CC
11
10
R
R
5VCARD. 5-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
= 5.0 Vdc.
request. This bit indicates that the host software has requested that the socket be powered at an
CC
BADVCCREQ. Bad V
invalidvoltage.
CC
9
R
0 = Normal operation (default)
1 = Invalid V request by host software
CC
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 66. Socket Present State Register Description (continued)
BIT
TYPE
FUNCTION
DATALOST. Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle did
not terminate properly or because write data still resides in the PCI4450.
0 = Normal operation (default)
8
R
1 = Potential data loss due to card removal
NOTACARD. Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is
notupdated until a valid PC Card is inserted into the socket.
0 = Normal operation (default)
7
6
R
R
1 = Unrecognizable PC Card detected
IREQCINT. READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC Card
interface.
0 = READY(IREQ)//CINT is low
1 = READY(IREQ)//CINT is high
CBCARD. CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not
updateduntil another card interrogation sequence occurs (card insertion).
5
4
R
R
16BITCARD. 16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not
updateduntil another card interrogation sequence occurs (card insertion).
PWRCYCLE. Power cycle. This bit indicates that the status of each card powering request. This bit is encoded as:
3
2
R
R
0 = Socket is powered down (default)
1 = Socket is powered up
CDETECT2. CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this signal
duringcard interrogation are not reflected here.
0 = CCD2 is low (PC Card may be present)
1 = CCD2 is high (PC Card not present)
CDETECT1. CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this signal
duringcard interrogation are not reflected here.
1
0
R
R
0 = CCD1 is low (PC Card may be present)
1 = CCD1 is high (PC Card not present)
CARDSTS. CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface.
0 = CSTSCHG is low
1 = CSTSCHG is high
110
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socket force event register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket force event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket force event
R
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
R
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
Socket force event
Read-only, Write-only
Offset:
Default:
CardBus Socket Address + 0Ch
0000 XXXXh
Description: This register is used to force changes to the socket event register and thesocketpresentstate
register. The CVSTEST bit in this register must be written when forcing changes that require
card interrogation.
Table 67. Socket Force Event Register Description
BIT
TYPE
FUNCTION
31–15
R
Reserved. These bits return 0s when read.
CVSTEST. Card VS test. When this bit is set, the PCI4450 reinterrogates the PC Card, updates the socket present state
register, and re-enables the socket power control.
14
13
12
11
10
9
W
W
W
W
W
W
W
W
FYVCARD.Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register to be written. When
set, this bit disables the socket power control.
FXVCARD.Force XV card. Writes to this bit cause the XVCARD bit in the socket present state register to be written. When
set, this bit disables the socket power control.
F3VCARD.Force 3-V card. Writes to this bit cause the 3VCARD bit in the socket present state register to be written. When
set, this bit disables the socket power control.
F5VCARD.Force 5-V card. Writes to this bit cause the 5VCARD bit in the socket present state register to be written. When
set, this bit disables the socket power control.
FBADVCCREQ.Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register can be made by
writingthis bit.
FDATALOST. Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register to be
written.
8
FNOTACARD. Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register to be
written.
7
6
5
4
R
W
W
Reserved. This bit returns 0 when read.
FCBCARD.Force CardBus card. Writes to this bit cause the CBCARD bit in the socket present state register to be written.
F16BITCARD.Force16-bitcard.Writestothisbitcausethe16BITCARDbitinthesocketpresentstateregistertobewritten.
FPWRCYCLE. Force power cycle. Writes to this bit cause the PWREVENT bit in the socket event register to be written,
and the PWRCYCLE bit in the socket present state register is unaffected.
3
2
1
0
W
W
W
W
FCDETECT2. Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register to be written, and the
CDETECT2 bit in the socket present state register is unaffected.
FCDETECT1. Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register to be written, and the
CDETECT1 bit in the socket present state register is unaffected.
FCARDSTS. Force CSTSCHG. Writes to this bit cause the CSTSEVENT bit in the socket event register to be written. The
CARDSTS bit in the socket present state register is unaffected.
111
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
socket control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
R
0
R
0
R
0
3
R
0
R
0
R
0
15
14
13
12
11
10
6†
5†
4†
2†
1†
0†
Name
Type
Default
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Socket control
Read-only, Read/Write
Offset:
Default:
CardBus Socket Address + 10h
0000 0000h
Description: This register provides control of the voltages applied to the socket’s V
and V . The
CC
PP
PCI4450 ensures that the socket is powered up only at acceptable voltages when a CardBus
card is inserted.
Table 68. Socket Control Register Description
BIT
TYPE
FUNCTION
31–8
R
Reserved. These bits return 0s when read.
STOPCLK. This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock to the
CardBus Card:
0 = The PCI4450 Clock run master will try to stop the clock to the CardBus Card under the following two
conditions:
The CardBus interface is idle for 8 clocks and
7
R/W
There is a request from the PCI master to stop the PCI clock.
1= The PCI4450 clock run master will try to stop the clock to the CardBus card under the following condition:
The CardBus interface is idle for 8 clocks.
In summary, if this bit is set to1, then the CardBus controller will try to stop the clock to the CardBus card independent of
the PCI clock run signal. The only condition that has to be satisfied in this case is the CardBus interface sampled idle for
8 clocks.
VCCCTRL. V
CC
control. These bits are used to request card V changes.
CC
000 = Request power off(default)
001 = Reserved
010 = Request V
011 = Request V
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= 5.0 V
= 3.3 V
= X.XV
= Y.YV
CC
CC
CC
CC
6–4†
R/W
3
R
Reserved. This bit returns 0 when read.
VPPCTRL. V control. These bits are used to request card VPP changes.
PP
000 = Request power off(default)
001 = Request V
010 = Request V
011 = Request V
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= 12.0 V
= 5.0 V
= 3.3 V
= X.XV
= Y.YV
PP
PP
PP
PP
PP
2–0†
R/W
†
This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or G_RST.
112
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SCPS046 – JANUARY 1999
socket power management register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R/W
0
15
14
13
12
11
10
0
Name
Type
Default
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
Register:
Type:
Offset:
Default:
Socket power management
Read-only, Read/Write
CardBus Socket Address + 20h
0000 0000h
Description: This register provides power management control over the socket through a mechanism for
slowing or stopping the clock on the card interface when the card is idle.
Table 69. Socket Power Management Register Description
BIT
TYPE
FUNCTION
31–26
R
Reserved. These bits return 0s when read.
SKTACCES. Socket access status. This bitprovidesinformationonwhenasocketaccesshasoccurred. Thisbitiscleared
by a read access.
25
R
0 = No PC Card access has occurred (default)
1 = PC Card has been accessed
SKTMODE. Socket mode status. This bit provides clock mode information.
0 = Normal clock operation
24
23–17
16
R
R
1 = Clock frequency has changed
Reserved. These bits return 0s when read.
CLKCTRLEN. CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL).
R/W
R
0 = Clock control disabled (default)
1 = Clock control enabled
15–1
Reserved. These bits return 0s when read.
This bit determines whether the CardBus clock run master stops the CCLK or slows the clock when it detects idle
activity on the CardBus interface.
0
R/W
0= Stop the CardBus clock using the clock run protocol when there is no activity on the CardBus interface (default).
1 = Divide PCI clock by 16 using the clock run protocol when there is no activity on the CardBus interface.
113
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
distributed DMA (DDMA) registers
The DMA base address, programmable in PCI configuration space at offset 98h, points to a 16-byte region in
PCI I/O space where the DDMA registers reside. Table 70 summarizes the names and locations of these
registers. These registers are identical in function, but different in location from the Intel 8237 DMA controller.
The similarity between the register models retains some level of compatibility with legacy DMA and simplifies
the translation required by the master DMA device when forwarding legacy DMA writes to DMA channels.
These PCI4450 DMA register definitions are identical to those registers of the same name in the 8237 DMA
controller;however, someregisterbitsdefinedinthe8237donotapplytodistributedDMAinaPCIenvironment.
In such cases, the PCI4450 will implement these obsolete register bits as nonfunctional, read-only bits. The
reserved registers shown in Table 70 are implemented as read-only, and return 0s when read. Writes to
reserved registers have no effect.
Table 70. Distributed DMA Registers
DMA BASE
TYPE
REGISTER NAME
ADDRESS
OFFSET
R
W
R
Currentaddress
Base address
Currentcount
Base count
00h
04h
08h
0Ch
Reserved
Reserved
Page
Reserved
Reserved
Reserved
W
R
N/A
Mode
N/A
Request
N/A
Status
W
R
Command
Multichannel
Mask
Reserved
W
Master clear
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SCPS046 – JANUARY 1999
DMA current address / base address register
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
Bit
DMA current address/base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Name
Type
Default
DMA current address/base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA current address/base address
Read/Write
Offset:
Default:
Size:
DMA Base Address + 00h
00 0000h
Two bytes
Description: This register is used to set the starting (base) memory address of a DMA transfer. Reads from
this register indicate the current memory address of a direct memory transfer.
For the 8-bit DMA transfer mode, the DMA current address register contentsarepresentedon
AD15–0 of the PCI bus during the address phase. Bits 7–0 of the DMA page register are
presented on AD23–AD16 of the PCI bus during the address phase.
For the 16-bit DMA transfer mode, the DMA current address register contents are presented
onAD16–AD1 of the PCI bus during the address phase, and AD0 is driven to logic ‘0’. Bits 7–1
of the DMA page register are presented on AD23–AD17 of the PCI bus during the address
phase, and bit 0 is ignored.
DMA page register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA page
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA page
Read/Write
Offset:
Default:
Size:
DMA Base Address + 02h
0000h
One byte
Description: This register is used to set the upper byte of the address of a DMA transfer. Details of the
address represented by this register are explained in the DMA current address/base address
register, above.
115
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
DMA current count / base count register
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
Bit
DMA current count/base count
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Name
Type
Default
DMA current count/base count
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA current count/base count
Read/Write
Offset:
Default:
Size:
DMA Base Address + 04h
0000h
Two bytes
Description: This register is used to set the total transfer count, in bytes, of a direct memory transfer.Reads
from this register indicate the current count of a direct memory transfer. In the 8-bit transfer
mode, the count is decremented by 1 after each transfer. Likewise, the count is decremented
by 2 in 16-bit transfer mode.
DMA command register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMAcommand
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
Size:
DMA command
Read-only, Read/Write
DMA Base Address + 08h
0000h
One byte
Description: This register is used to enable and disable the controller; all other bits are reserved.
Table 71. DDMA Command Register Description
BIT
TYPE
FUNCTION
7–3
R
Reserved. These bits return 0s when read.
DMA controller enable. This bit enables and disables the distributed DMA slave controller in the PCI4450, and defaults to
the enabled state.
2
R/W
R
0 = DMA controller enabled (default)
1 = DMA controller disabled
1–0
Reserved. These bits return 0s when read.
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SCPS046 – JANUARY 1999
DMA status register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA status
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
DMA status
Read-only
Offset:
Default:
Size:
DMA Base Address + 08h
0000h
One byte
Description: This register indicates the terminal count and DMA request (DREQ) status.
Table 72. DMA Status Register Description
BIT
TYPE
FUNCTION
DREQSTAT. Channel request. In the 8237, these bits indicate the status of the DREQ signal of each DMA channel. In
thePCI4450, these bits indicate the DREQ status of the single socket being serviced by this register. All four bits are set
when the PC Card asserts its DREQ signal, and are reset when DREQ is deasserted. The status of the mask bit in the
DMAmultichannel mask register has no effect on these bits.
7–4
R
TC. Channel terminal count. The 8327 uses these bits to indicate the TC status of each of its four DMA channels. In
thePCI4450, thesebitsreportinformationaboutjustasingleDMAchannel;therefore, allfouroftheseregisterbitsindicate
the TC status of the single socket being serviced by this register. All four bits are set when the terminal count (TC) is
reached by the DMA channel. These bits are reset when read or when the DMA channel is reset
3–0
R
DMA request register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA request
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
DMA request
Write-only
Offset:
Default:
Size:
DMA Base Address + 09h
0000h
One byte
Description: This register is used to request a DDMA transfer through software. Any write to this register
enables software requests. This register is to be used in block mode only.
117
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SCPS046 – JANUARY 1999
DMA mode register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA mode
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
Register:
Type:
Offset:
Default:
Size:
DMA mode
Read-only, Read/Write
DMA Base Address + 0Bh
0000h
One byte
Description: This register is used to set the DMA transfer mode.
Table 73. DDMA Mode Register Description
BIT
TYPE
FUNCTION
DMAMODE.Mode select bits. The PCI4450 uses these bits to determine the transfer mode.
00 = Demand mode select (default)
01 = Single mode select
10 = Block mode select
11 = Reserved
7–6
R/W
INCDEC. Address increment/decrement. The PCI4450 uses this register bit to select the memory address in the DMA
currentaddress/base address register to increment or decrement after each data transfer. This is in accordance with the
8237 use of this register bit, and is encoded as follows:
5
4
R/W
R/W
0 = Addresses increment (default)
1 = Addresses decrement
AUTOINIT.Auto-initializationbit.
0=Auto-initializationdisabled(default)
1=Auto-initializationenabled
XFERTYPE. Transfer type. These bits select the type of direct memory transfer to be performed. A memory write transfer
moves data from the PCI4450 PC Card interface to memory, and a memory read transfer moves data from memory to
thePCI4450 PC Card interface. The field is encoded as:
00 = No transfer selected (default)
01 = Write transfer
3–2
1–0
R/W
R
10 = Read transfer
11 = Reserved
Reserved. These bits return 0s when read.
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DMA master clear register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA master clear
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
DMA master clear
Write-only
Offset:
Default:
Size:
DMA Base Address + 0Dh
0000h
One byte
Description: This register is used to reset the DDMA controller, and resets all DDMA registers.
DMA multichannel mask register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMAmultichannel mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
1
Register:
Type:
Offset:
Default:
Size:
DMA multichannel mask
Read-only, Read/Write
DMA Base Address + 0Fh
0000h
One byte
Description: The PCI4450 uses only the least significant bit of this register to mask the PC Card DMA
channel. The PCI4450 sets the mask bit when the PC Card is removed. Host software is
responsible for either resetting the socket’s DMA controller or re-enabling the mask bit.
Table 74. DDMA MultiChannel Mask Register Description
BIT
TYPE
FUNCTION
7–1
R
Reserved. These bits return 0s when read.
MASKBIT. Mask select bit. This bit masks incoming DREQ signals from the PC Card. When set, the socket ignores DMA
requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced normally.
0 = DDMA service provided on card DREQ
0
R/W
1 = Socket DREQ signalignored(default)
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PCI4450GFN/GJG
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SCPS046 – JANUARY 1999
OHCI-Lynx controller programming model
This section describes the internal registers used to program the link function, including both PCI configuration
registers and Open HCI registers. All registers are detailed in the same format. A brief description is provided
for each register, followed by the register offset and a bit-table describing the reset state for each register.
A bit description table is typically included that indicates bit field names, a detailed field description, and field
access tags. Table 75 describes the field access tags.
Table 75. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
Read
Write
Set
MEANING
R
W
S
Field may be read by software.
Field may be written by software to any value.
Field may be set by a write of 1. Writes of 0 have no effect.
Field may be cleared by a write of 1. Writes of 0 have no effect.
Field may be autonomously updated by the PCI4450.
C
U
Clear
Update
PCI configuration registers
The PCI4450 link function configuration header is compliant with the PCI Specification as a standard header.
Table 76 illustrates the PCI configuration header which includes both the predefined portion of the configuration
space and the user definable registers. The registers that are labeled Reserved are read-only returning 0 when
read and are not applicable to the link function or have been reserved by the PCI specification for future use.
Table 76. PCI Configuration Register Map
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
Command
04h
Class code
Header type
Open HCI registers base address
Revision ID
08h
BIST
Latencytimer
Cache line size
0Ch
10h
TI extension registers base address
14h
Reserved
Reserved
Reserved
Reserved
Reserved
18h
1Ch
20h
24h
28h
Subsystem ID
Subsystem vendor ID
2Ch
30h
Reserved
Reserved
Capabilitespointer
34h
Reserved
38h
Max latency
Mingrant
Interruptpin
Interruptline
CapabilityID
3Ch
40h
PCI OHCI control
Next item pointer
Powermanagementcapabilities
44h
PM data
PMCSR_BSE
PowermanagementCSR
48h
Reserved
4C–ECh
F0h
F4h
F8h
FCh
PCImiscellaneousconfiguration
Link_enhancements
Subsystem ID alias
Subsystem vendor ID alias
GPIO1 GPIO0
GPIO3
GPIO2
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
vendor ID register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
Vender ID
Read-only
00h
104Ch
Description: This 16-bit read-only register contains a value allocated by the PCI SIG and identifies the
manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch.
device ID register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Device ID register
Read-only
02h
8011h
Description: This16-bitread-onlyregistercontainsavalueassignedtothePCI4450byTexasInstruments.
The device identification for the PCI4450 OHCI controller function is 8011h.
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SCPS046 – JANUARY 1999
PCI command register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI command
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R
0
Register:
Type:
PCI command
Read-only, Read/Write
Offset:
Default:
04h
0000h
Description: The command register provides control over the PCI4450 link interface to the PCI bus. All bit
functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following
bit descriptions.
Table 77. PCI Command Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–10 RSVD
R
R
Reserved. These bits return 0s when read.
9
8
7
6
5
4
3
FBB_ENB
Fast back-to-back enable. The PCI4450 will not generate fast back to back transactions, thus this bit
returns 0 when read.
SERR_ENB
STEP_ENB
PERR_ENB
VGA_ENB
MWI_ENB
SPECIAL
R/W
R
SERR enable. When set, the PCI4450 SERR driver is enabled. SERR can be asserted after detecting an
address parity error on the PCI bus.
Address/data stepping control. The PCI4450 does not support address/data stepping, and this bit is
hardwired to 0.
R/W
R
Parityerrorenable. Whenset, thePCI4450isenabledtodrivePERRresponsetoparityerrorsthroughthe
PERR signal.
VGA palette snoop enable. The PCI4450 does not feature VGA palette snooping. This bit returns 0 when
read.
R/W
R
Memory write and invalidate enable. When set, the PCI4450 is enabled to generate MWI PCI bus
commands. If reset, the PCI4450 will generate memory write commands instead.
Special cycle enable. The PCI4450 function does not respond to special cycle transactions. This bit
returns 0 when read.
2
1
MASTER_ENB
MEMORY_ENB
R/W
R/W
Bus master enable. When set, the PCI4450 is enabled to initiate cycles on the PCI bus.
Memory response enable. Setting this bit enables the PCI4450 to respond to memory cycles on the PCI
bus. This bit must be set to access OHCI registers.
0
IO_ENB
R
I/O space enable. The PCI4450 link does not implement any I/O mapped functionality; thus, this bit
returns 0 when read.
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SCPS046 – JANUARY 1999
PCI status register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI status
RCU RCU RCU RCU RCU
R
0
R
1
RCU
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
0
0
0
0
0
0
Register:
Type:
PCI status
Read-only, Read/Clear/Update
Offset:
Default:
06h
0210h
Description: PCI Bus Specification, as seen in the bit descriptions.
Table 78. PCI Status Register Description
BIT
15
FIELD NAME
PAR_ERR
TYPE
RCU
RCU
DESCRIPTION
Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.
14
SYS_ERR
Signaledsystem error. This bit is set when SERR is enabled and the PCI4450 signaled a system error to
the host.
13
12
MABORT
RCU
RCU
RCU
R
Received master abort. This bit is set when a cycle initiated by the PCI4450 on the PCI bus has been
terminated by a master abort.
TABORT_REC
TABORT_SIG
PCI_SPEED
DATAPAR
Received target abort. This bit is set when a cycle initiated by the PCI4450 on the PCI bus was
terminated by a target abort.
11
Signaledtarget abort. This bit is set by the PCI4450 when it terminates a transaction on the PCI bus with
a target abort.
10–9
8
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b indicating that the
PCI4450 asserts this signal at a medium speed on non-configuration cycle accesses.
RCU
Data parity error detected. This bit is set when the following conditions have been met:
a. PERR was asserted by any PCI device including the PCI4450
b. The PCI4450 was the bus master during the data parity error
c. The parity error response bit is set in the command register
7
6
5
4
FBB_CAP
UDF
R
R
R
R
Fast back-to-back capable. The PCI4450 cannot accept fast back-to-back transactions; thus, this bit is
hardwired to 0.
UDF supported. The PCI4450 does not support the user definable features; thus, this bit is hardwired to
0.
66MHZ
CAPLIST
66 MHz capable. The PCI4450 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is
hardwired to 0.
Capabilities list. This bit returns 1 when read, and indicates that capabilities additional to standard
PCI are implemented. The linked list of PCI power management capabilities is implemented in this
function.
3–0
RSVD
R
Reserved. These bits return 0s when read.
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SCPS046 – JANUARY 1999
class code and revision ID register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Class code and revision ID
R
0
R
0
R
0
R
0
R
1
R
1
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Class code and revision ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
Register:
Type:
Offset:
Default:
Class code and revision ID
Read-only
08h
0C00 100Xh
Description: Thisread-onlyregistercategorizesthePCI4450asaserialbuscontroller(0Ch), controllingan
IEEE1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip
revision is indicated in the lower byte.
Table 79. Class Code and Revision ID Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–24 BASECLASS
R
Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus
controller.
23–16 SUBCLASS
R
R
R
Sub class. This field returns 00h when read, which specifically classifies the function as controlling a
IEEE1394 serial bus.
15–8
7–0
PGMIF
Programminginterface. Thisfieldreturns10hwhenread, whichindicatesthattheprogrammingmodelis
compliant with the 1394 OHCI specification.
CHIPREV
Silicon revision. This field returns the silicon revision of the PCI4450.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
latency timer and class cache line size register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer and class cache line size
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Latency timer and class cache line size
Read/Write
0Ch
0000h
Description: This register is programmed by host BIOS to indicate system cache line size and the latency
timer associated with the PCI4450.
Table 80. Latency Timer and Class Cache Line Size Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
LATENCY_TIMER
R/W
PCIlatencytimer. ThevalueinthisregisterspecifiesthelatencytimerforthePCI4450, inunitsofPCI
clock cycles. When the PCI4450 is a PCI bus initiator and asserts FRAME, the latency timer will
begin counting from zero. If the latency timer expires before the PCI4450 transaction has
terminated, then the PCI4450 will terminate the transaction when its GNT is deasserted.
7–0
CACHELINE_SZ
R/W
Cache line size. This value is used by the PCI4450 during memory write and invalidate, memory
read line, and memory read multiple transactions.
header type and BIST register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Header type and BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Header type and BIST
Read-only
0Eh
0000h
Description: This register indicates that this function is part of a multifunction device and has a standard
PCI header type and indicates no built-in self-test.
Table 81. Header Type and BIST Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
BIST
R
Built-in self-test. The PCI4450 does not include a built-in self-test, and this field returns 00h when
read.
7–0
HEADER_TYPE
R
PCI header type. The PCI4450 includes the standard PCI header, and this is communicated by
returning 00h when this field is read.
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
open HCI registers base address register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Open HCI registers base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Open HCI registers base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Open HCI registers base address
Read-only, Read/Write
10h
0000 0000h
Description: This register is programmed with a base address referencing the memory mapped OHCI
control. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating
that at least 2 Kbytes of memory address space are required for the OHCI registers.
Table 82. Open HCI Registers Base Address Register Description
BIT
31–11
10–4
FIELD NAME
OHCIREG_PTR
OHCI_SZ
TYPE
R/W
R
DESCRIPTION
Open HCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI register base address.
Open HCI register size. This field returns 0s when read, and indicates that the OHCI registers
require a 2-Kbyte region of memory.
3
OHCI_PF
R
R
OHCI register prefetch. This bit returns 0, indicating the OHCI registers are nonprefetchable.
2–1
OHCI_MEMTYPE
Open HCI memory type. This field returns 0s when read, and indicates that the base register is
32 bits wide and mapping can be done anywhere in the 32-bit memory space.
0
OHCI_MEM
R
OHCI memory indicator. This bit returns 0, indicating the OHCI registers are mapped into system
memory space.
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TI extension base address register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
TI extension base address
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
TI extension base address
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
TI extension base address
Read-only
14h
0000 0000h
Description: This register is programmed with a base address referencing the memory mapped TI
extension registers.
Table 83. TI Extension Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–11
TI_EXTREG_PTR
R/W
TI extension register pointer. Specifies the upper 20 bits of the 32-bit TI extension register base
address.
10–4
3
TI_SZ
TI_PF
R
R
R
R
TI extension register size. This field returns 0s when read, and indicates that the TI extension
registers require a 2-Kbyte region of memory.
TI extension register prefetch. This bit returns 0, indicating the TI extension registers are
nonprefetchable.
2–1
0
TI_MEMTYPE
TI_MEM
TI memory type. This field returns 0s when read, and indicates that the base register is 32 bits wide
and mapping can be done anywhere in the 32-bit memory space.
TImemoryindicator. Thisbitreturns0, indicatingtheTIextensionregistersaremappedintosystem
memory space.
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SCPS046 – JANUARY 1999
PCI subsystem identification register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PCI subsystem identification
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI subsystem identification
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
Register:
Type:
PCI subsystem identification
Read/Update
Offset:
Default:
2Ch
0000 0000h
Description: This register is used for subsystem and option card identification purposes. This register can
be initialized from the serial EEPROM or can be written using the subsystem access register.
Table 84. PCI Subsystem Identification Register Description
BIT
31–16
15–0
FIELD NAME
OHCI_SSID
OHCI_SSVID
TYPE
RU
DESCRIPTION
Subsystem device ID. This field indicates the subsystem device ID.
Subsystem vendor ID. This field indicates the subsystem vendor ID.
RU
PCI power management capabilities pointer register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PCI power management capabilities pointer
R
0
R
1
R
0
R
0
R
0
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
PCI power management capabilities pointer
Read-only
34h
44h
Description: This register provides a pointer into the PCI configuration header where the PCI power
management register block resides. PCI4450 configuration header double-words at 44h and
48h provide the power management registers. This register is read-only and returns 44h
when read.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
interrupt line and pin registers
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt line and pin
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Interrupt line and pin
Read-only, Read/Write
3Ch
0000h
Description: This register is used to communicate interrupt line routing information.
Table 85. Interrupt Line and Pin Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
INTR_PIN
R
Interrupt pin register. This register returns 01h, 02h, or 03h when read, indicating that the PCI4450
link function signals interrupts on INTA, INTB, or INTC pin.
7–0
INTR_LINE
R/W
Interrupt line register. This register is programmed by the system and indicates to the software
which interrupt line the PCI4450 INTA is connected.
MIN_GNT and MAX_LAT registers
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
MIN_GNT and MAX_LAT
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
1
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
1
RU
0
Register:
Type:
Offset:
Default:
MIN_GNT and MAX_LAT
Read/Update
3Eh
0202h
Description: This register is used to communicate to the system the desired setting of the latency timer
register. If a serial ROM is detected, then the contents of this register are loaded through the
serial ROM interface after a PCI reset. If no serial ROM is detected, then this register returns a
default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4.
Table 86. MIN_GNT and MAX_LAT Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
MAX_LAT
RU
Maximum latency. The contents of this register may be used by host BIOS to assign an
arbitration priority-level to the PCI4450. The default for this register indicates that the
PCI4450 may need to access the PCI bus as often as every 1/4 µs; thus, an extremely high
priority level is requested. The contents of this field may also be loaded through the serial
ROM.
7–0
MIN_GNT
RU
Minimum grant. The contents of this register may be used by host BIOS to assign a latency
timer register value to the PCI4450. The default for this register indicates that the PCI4450
may need to sustain burst transfers for nearly 64 µs; thus, requesting a large value be
programmed in the PCI4450 latency timer register.
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PCI OHCI control register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI OHCI control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
PCI OHCI control
Read-only
40h
0000h
Description: This register contains IEEE1394 Open HCI specific control bits. All bits in this register are
read-only and return 0s, since no OHCI specific control bits have been implemented.
capability ID and next item pointer registers
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Capability ID and next item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Capability ID and next item pointer
Read-only
44h
0001h
Description: This register identifies the linked list capability item, and provides a pointer to the next
capability item.
Table 87. Capability ID and Next Item Pointer Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
NEXT_ITEM
R
Next item pointer. The PCI4450 supports only one additional capability that is communicated to
the system through the extended capabilities list; thus, this field returns 00h when read.
7–0
CAPABILITY_ID
R
Capability identification. This field returns 01h when read, which is the unique ID assigned by
the PCI SIG for PCI power management capability.
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power management capabilities register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
RU
0
RU
1
RU
0
RU
0
RU
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Power management capabilities
Read/Update
46h
4001h
Description: This register indicates the capabilities of the PCI4450 related to PCI power management. In
summary, the D0, D2, and D3 device states are supported.
hot
Table 88. Power Management Capabilities Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_D3COLD
RU
PMEsupportfromD3
is dependent upon PCI4450 V
PCI miscellaneous configuration register.
.Whenset,PCI4450generatesaPMEwakeeventfromD3
.Thisbitstate
cold
cold
implementation and may be configured by host software using the
aux
14–11
PME_SUPPORT
RU
PME support. This four-bit field indicates the power states from which the PCI4450 may assert
PME. These four bits return a value of 4’b1100 by default, indicating that PME may be asserted
from the D3
miscellaneous configuration register.
and D2 power states. Bit 13 may be modified by host software using the PCI
hot
10
9
D2_SUPPORT
D1_SUPPORT
R
R
D2 support. This bit returns a 1 when read, indicating that the PCI4450 supports the D2 power state.
D1 support. This bit returns a 0 when read, indicating that the PCI4450 does not support the D1 power
state.
8
DYN_DATA
R
Dynamic data support. This bit returns a 0 when read, indicating that the PCI4450 does not report
dynamic power consumption data.
7–6
5
RSVD
DSI
R
R
Reserved. These bits return 0s when read.
Device specific initialization. This bit returns 0 when read, indicating that the PCI4450 does not
require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
4
3
AUX_PWR
PME_CLK
R
R
R
Auxiliary power source. Since the PCI4450 supports PME generation in the D3 device state and
cold
requires V
aux
, this bit returns 1 when read.
PMEclock. Thisbitreturns0whenreadindicatingthatnohostbusclockisrequiredforthePCI4450to
generate PME.
2–0
PM_VERSION
Power management version. This field returns 001b when read, indicating that the PCI4450
is compatible with the registers described in the revision 1.0 PCI Bus Power Management
Specification.
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power management control and status register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control and status
RC
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Power management control and status
Read-only, Read/Write, Read/Clear
Offset:
Default:
48h
0000h
Description: This register implements the control and status of the PCI power management function. This
register is not affected by the internally generated reset caused by the transition from the
D3
to D0 state.
hot
Table 89. Power Management Control and Status Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_STS
RC
This bit is set when the PCI4450 would normally be asserting the PME signal, independentofthestateofthe
PME_ENB bit. This bit is cleared by a write back of 0, and this also clears the PME signal driven by the
PCI4450. Writing a 0 to this bit has no effect.
14–9
8
DYN_CTRL
PME_ENB
RSVD
R
R/W
R
Dynamic data control. This bit field returns 0s when read since the PCI4450 does not report dynamic data.
PME enable. This bit enables the function to assert PME. If the bit is cleared assertion of PME is disabled.
Reserved. These bits return 0s when read.
7–5
4
DYN_DATA
RSVD
R
Dynamic data. This bit returns 0 when read since the PCI4450 does not report dynamic data.
Reserved. These bits return 0s when read.
3–2
1–0
R
PWR_STATE
R/W
Power state. This two-bit field is used to set the PCI4450 device power state, and is encoded as follows:
00 = Current power state is D0
01 = Current power state is D1
10 = Current power state is D2
11 = Current power state is D3
hot
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SCPS046 – JANUARY 1999
power management extension register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management extension
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Power management extension
Read-only
4Ah
0000h
Description: This register provides extended power management features not applicable to the PCI4450,
thus it is read-only and returns 0 when read.
Table 90. Power Management Extension Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
PM_DATA
R
Power management data. This bit field returns 0s when read since the PCI4450 does not report
dynamic data.
7–0
PMCSR_BSE
R
Power management CSR – bridge support extensions. This field returns 0s since the PCI4450 does
not provide P2P bridging.
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PCI miscellaneous configuration register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PCI miscellaneous configuration
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
PCI miscellaneous configuration
R/W
0
R
0
R/W
1
R
0
R
0
R/W
1
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
PCI miscellaneous configuration
Read-only, Read/Write
F0h
0000 2400h
Description: This register provides miscellaneous PCI-related configuration.
Table 91. PCI Miscellaneous Configuration Register Description
BIT
31–16
15
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. These bits return 0s when read.
PME support from D3 . This bit is used to program the corresponding read-only value read
from power management capabilities. This bit retains state through PCI reset and D3 – D0
transitions.
PME_D3COLD
R/W
cold
14
13
RSVD
R
Reserved. This bit returns 0 when read.
PME_SUPPORT_D2
R/W
PME support. This bit is used to program the corresponding read-only value read from power
management capabilities. If wake from the D2 power state implemented in PCI4450 is not
desired, then this bit may be cleared to indicate to power management software that wake–up
from D2 is not supported. This bit retains state through PCI reset and D3 – D0 transitions.
12–11
10
RSVD
R
Reserved. These bits return 0s when read.
D2_SUPPORT
R/W
D2 support. This bit is used to program the corresponding read-only value read from power
management capabilities. If the D2 power state implemented in PCI4450 is not desired, then
this bit may be cleared to indicate to power management software that D2 is not supported.
This bit retains state through PCI reset and D3 – D0 transitions.
9–4
3
RSVD
RSVD
R
Reserved. These bits return 0s when read.
R/W
R/W
R/W
R/W
Reserved. This bit defaults to 0.
2
DISABLE_SCLKGATE
DISABLE_PCIGATE
KEEP_PCLK
When set, the internal SCLK runs identically with the chip input.
When set, the internal PCI clock runs identically with the chip input.
1
0
Whenset, thePCIclockisalwayskeptrunningthroughtheCLKRUNprotocol. Whencleared,the
PCI clock may be stopped using CLKRUN.
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link enhancement control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Link enhancement control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Link enhancement control
R
0
R
0
R/W
0
R/W
1
R
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
Register:
Type:
Offset:
Default:
Link enhancement control
Read-only, Read/Write
F4h
0000 1000h
Description: This register implements TI proprietary bits that are initialized by software or by a serial
EEPROM if present. After these bits are set, their functionality is enabled only if the
aPhyEnhanceEnable bit in the HCControl register is set.
Table 92. Link Enhancement Control Register Description
BIT
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. These bits return 0s when read.
31–14
13–12
atx_thresh
R/W
This bit field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When
PCI4450 retries the packet, it uses a 2K-byte threshold resulting in store-and-forward operation.
00 = Threshold ~ 2 Kbytes resulting in store-and-forward operation
01 = Threshold ~ 1.7 Kbytes (default)
10 = Threshold ~ 1 K
11 = Threshold ~ 512 bytes
11–10
9
RSVD
R
Reserved. This bit returns 0 when read.
enab_audio_ts
R/W
Enable audio/music CIP timestamp enhancement. When this bit is set, the enhancement is
enabled for audio/music CIP transmit streams (FMT = 6’h10).
8
enab_dv_ts
R/W
Enable DV CIP timestamp enhancement. When this bit is set, the enhancement is enabled for DV
CIP transmit streams (FMT = 6’h00).
7
6
enab_unfair
RSVD
R/W
R
Enable asynchronous priority requests. OHCILynx (TSB12LV22) compatible.
This reserved field will not be assigned in PCI4450 follow–on products since this bit location loaded
by the serial ROM from the enhancements field corresponds to HCControl.programPhyEnable in
Open HCI register space.
5–3
2
RSVD
enab_insert_idle
enab_accel
RSVD
R
Reserved. These bits return 0s when read.
R/W
R/W
R
Enable insert idle. OHCILynx (TSB12LV22) compatible.
Enable acceleration enhancements. OHCILynx (TSB12LV22) compatible.
Reserved. This bit returns 0 when read.
1
0
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
subsystem access register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Subsystem access identification
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem access identification
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Subsystem access identification
Read/Write
F8h
0000 0000h
Description: This register is used for system and option card identification purposes. The contents of this
register are aliased to subsystem identification register at address 2Ch.
Table 93. Subsystem Access Identification Register Description
BIT
31–16
15–0
FIELD NAME
SUBDEV_ID
SUBVEN_ID
TYPE
R/W
DESCRIPTION
Subsystem device ID. This field indicates the subsystem device ID.
Subsystem vendor ID. This field indicates the subsystem vendor ID.
R/W
136
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
GPIO control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GPIO control
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R
0
9
R/W
0
R
0
7
R
0
6
R/W
0
R/W
0
R
0
3
R
0
2
R
0
1
R/W
0
15
14
13
12
11
10
8
5
4
0
Name
Type
Default
GPIO control
R/W
0
R
0
R/W
0
R/W
1
R
0
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
1
R
0
R
0
R
0
R/W
0
Register:
Type:
Offset:
Default:
GPIO control
Read-only, Read/Write
FCh
0000 1010h
Description: ThisregisterhasthecontrolandstatusbitsforGPIO0, GPIO1, GPIO2andGPIO3ports. Upon
reset, GPIO0 and GPIO1 default to bus manager contender (BMC) and link power status
terminals, respectively. The BMC terminal can be configured as GPIO0 by setting the
disable_BMC bit to 1. The LPS terminal can be configured as GPIO1 by setting the
disable_LPS bit to 1.
Table 94. General-Purpose Input/Output Control Register Description
BIT
31–30
29
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. These bits return 0s when read.
GPIO_INV3
R/W
GPIO3 polarity invert. This bit controls the input/output polarity control of GPIO3.
0 = noninverted (default)
1 = inverted
28
GPIO_ENB3
R/W
GPIO3 enable control. This bit controls the output enable for GPIO3
0 = high-impedance output (default)
1 = output enabled
27–25
24
RSVD
R
Reserved. These bits return 0s when read.
GPIO_DATA3
R/W
GPIO3 data. When GPIO3 output is enabled, the value written to this bit represents the logical data
driven to the GPIO3 terminal.
23–22
21
RSVD
R
Reserved. These bits return 0s when read.
GPIO_INV2
R/W
GPIO2 polarity invert. This bit controls the input/output polarity control of GPIO2.
0 = noninverted (default)
1 = inverted
20
GPIO_ENB2
R/W
GPIO2 enable control. This bit controls the output enable for GPIO2.
0 = high-impedance output (default)
1 = output enabled
19–17
16
RSVD
R
Reserved. These bits return 0s when read.
GPIO_DATA2
R/W
GPIO2 data. When GPIO2 output is enabled, the value written to this bit represents the logical data
driven to the GPIO2 terminal.
15
14
DISABLE_LPS
RSVD
R/W
R
Disable link power status (LPS). This bit configures this terminal as
0 = LPS (default)
1 = GPIO1
Reserved. This bit returns 0 when read.
137
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SCPS046 – JANUARY 1999
Table 94. General-Purpose Input/Output Control Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
13
GPIO_INV1
R/W
GPIO1polarityinvert.WhenDISABLE_LPSbitissetto1,thisbitcontrolstheinputoutputpolaritycontrol
of GPIO1
0 = noninverted (default)
1 = inverted
12
GPIO_ENB1
R/W
GPIO1 enable control. When DISABLE_LPS bit is set to 1, this bit controls the output enable for GPIO1
0 = high-impedance output
1 = output enabled (default)
11–9
8
RSVD
R
Reserved. These bits return 0s when read.
GPIO_DATA1
R/W
GPIO1data. WhenDISABLE_LPSbitissetto1andGPIO1outputisenabled, thevaluewrittentothisbit
represents the logical data driven to the GPIO1 terminal.
7
DISABLE_BMC
R/W
Disable bus manager contender (BMC). This bit configures this terminals as bus master contender or
GPIO.
0 = BMC (default)
1 = GPIO0
6
5
RSVD
R
Reserved. This bit returns 0 when read.
GPIO_INV0
R/W
GPIO0 polarity invert. When DISABLE_BMC bit is set to 1, this bit controls the input output polarity
control of for GPIO0
0 = non-inverted (default)
1 = inverted
4
GPIO_ENB0
R/W
GPIO0 enable control. When DISABLE_BMC bit is set to 1, this bit controls the output enable for GPIO0
0 = high-impedance output
1 = output enabled (default)
3–1
0
RSVD
R
Reserved. These bits return 0s when read.
GPIO_DATA0
R/W
GPIO0 data. When DISABLE_BMC bit is set to 1 and GPIO0 output is enabled, the value written to
this bit represents the logical data driven to the GPIO0 terminal.
138
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
link timer adjustment register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Link timer adjustment
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Link timer adjustment
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Link timer adjustment
Read-only, Read/Write
C10h
0000 0000h
Description: This register is used to control the link rollover value, and should be programmed with a
non–zero value only when PCI4450 is the 1394 cycle master.
Table 95. Link Timer Adjustment Register Description
BIT
31–8
7
FIELD NAME
RSVD
TYPE
DESCRIPTION
Reserved. These bits return 0s when read.
R
R
TIMER_ADJ_REQ
This bit indicates that the timer adjust request is active, but not completed. This bit is set
whenever the timer adjust field is written, and is cleared when the actual adjustment is made.
6–4
3–0
RSVD
R
Reserved. These bits return 0s when read.
TIMER_ADJ_VAL
R/W
Cycletimeradjustmentvalue. ThisfourbitsignedvalueisusedtoadjustthePCI4450cycleTimer.
The cycle timer offset field may be adjusted from +7 to –8 using this register.
139
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
open HCI registers
The open HCI registers defined by the IEEE1394 Open HCI Specification are memory mapped into a 2-Kbyte
region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space. These
registers are the primary interface for controlling the PCI4450 IEEE1394 link function.
This section provides the register interface and bit descriptions. There are several set and clear register pairs
inthisprogrammingmodel, whichareimplementedtosolvevariousissueswithtypicalread-modify-writecontrol
registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 96
for an illustration. A 1 written to RegisterSet causes the corresponding bit in the set/clear register to be set, while
a 0 leaves the corresponding bit unaffected. A 1 written to RegisterClear causes the corresponding bit in the
set/clear register to be reset, while a 0 leaves the corresponding bit in the set/clear register unaffected.
Typically, a read from either RegisterSet or RegisterClear returns the value of the set/clear register. However,
sometimes reading the RegisterClear will provide a masked version of the set/clear register. The interrupt event
register is an example of this behavior.
Table 96. Open HCI Register Map
DMA CONTEXT
REGISTER NAME
ABBREVIATION
OFFSET
00h
—
OHCI version
Version
Global unique ID ROM
Asynchronous transmit retries
CSR data
GUID_ROM
ATRetries
04h
08h
CSRData
0Ch
10h
CSR compare data
CSR control
CSRCompareData
CSRControl
ConfigROMhdr
BusID
14h
Configuration ROM header
Bus identification
Bus options
18h
1Ch
20h
BusOptions
GUIDHi
Global unique ID high
Global unique ID low
Reserved
24h
GUIDLo
28h
—
2Ch
30h
Reserved
—
Configuration ROM map
Posted write address low
Posted write address high
Vendor identification
Reserved
ConfigROMmap
PostedWriteAddressLo
PostedWriteAddressHi
VendorID
34h
38h
3Ch
40h
—
44h – 4Ch
140
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 96. Open HCI Register Map (Continued)
DMA CONTEXT
REGISTER NAME
Host controller control
ABBREVIATION
HCControlSet
OFFSET
50h
—
HCControlClr
54h
Reserved
—
58h
Reserved
—
5Ch
Self ID
Reserved
—
60h
Self ID buffer
Self ID count
Reserved
SelfIDBuffer
64h
SelfIDCount
68h
—
6Ch
—
IRChannelMaskHiSet
IRChannelMaskHiClear
IRChannelMaskLoSet
IRChannelMaskLoClear
IntEventSet
70h
Isochronous receive channel mask high
Isochronous receive channel mask low
Interrupt event
74h
78h
7Ch
80h
IntEventClear
84h
IntMaskSet
88h
Interrupt mask
IntMaskClear
8Ch
IsoXmitIntEventSet
IsoXmitIntEventClear
IsoXmitIntMaskSet
IsoXmitIntMaskClear
IsoRecvIntEventSet
IsoRecvIntEventClear
IsoRecvIntMaskSet
IsoRecvIntMaskClear
90h
Isochronous transmit interrupt event
Isochronous transmit interrupt mask
Isochronous receive interrupt event
Isochronous receive interrupt mask
94h
98h
9Ch
—
A0h
A4h
A8h
ACh
B0–D8h
DCh
E0h
Reserved
Fairness control
FairnessControl
LinkControlSet
Link control
LinkControlClear
E4h
Node identification
Phy layer control
Isochronous cycle timer
Reserved
NodeID
E8h
PhyControl
ECh
F0h
IsoCycleTimer
—
F4h – FCh
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h – 17Ch
AsyncRequestFilterHiSet
AsyncRequestFilterHiClear
AsyncRequestFilterLoSet
AsyncRequestFilterloClear
PhysicalRequestFilterHiSet
PhysicalRequestFilterHiClear
PhysicalRequestFilterLoSet
PhysicalRequestFilterloClear
PhysicalUpperBound
—
Asynchronous request filter high
Asynchronous request filter low
Physical request filter high
Physical request filter low
Physical upper bound
Reserved
141
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 96. Open HCI Register Map (Continued)
DMA CONTEXT
REGISTER NAME
ABBREVIATION
ContextControlSet
OFFSET
180h
Context control
Asychronous
request transmit
[ ATRQ ]
ContextControlClear
—
184h
Reserved
188h
Command pointer
Reserved
CommandPtr
—
18Ch
190h – 19Ch
1A0h
ContextControlSet
ContextControlClear
—
Asychronous
response transmit
[ ATRS ]
Context control
1A4h
Reserved
1A8h
Command pointer
Reserved
CommandPtr
—
1ACh
1B0h – 1BCh
1C0h
ContextControlSet
ContextControlClear
—
Asychronous
request receive
[ ARRQ ]
Context control
1C4h
Reserved
1C8h
Command pointer
Reserved
CommandPtr
—
1CCh
1D0h – 1DCh
1E0h
ContextControlSet
ContextControlClear
—
Asychronous
response receive
[ ARRS ]
Context control
1E4h
Reserved
1E8h
Command pointer
Reserved
CommandPtr
—
1ECh
1F0h – 1FCh
200h + 16*n
204h + 16*n
208h + 16*n
20Ch + 16*n
400h + 32*n
404h + 32*n
408h + 32*n
40Ch + 32*n
410h + 32*n
Isochronous
transmit context n
n = 0, 1, 2, 3, … 7
ContextControlSet
ContextControlClear
—
Context control
Reserved
Command pointer
CommandPtr
ContextControlSet
ContextControlClear
—
Isochronous
receive context n
n = 0, 1, 2, 3, 4
Context control
Reserved
Command pointer
Context match
CommandPtr
ContextMatch
142
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
OHCI version register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
OHCI version
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
OHCI version
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
OHCI version
Read-only
00h
0X01 0000h
Description: This register indicates the OHCI version support, and whether or not the serial ROM is
present.
Table 97. OHCI Version Register Description
BIT
31–25
24
FIELD NAME
RSVD
TYPE
DESCRIPTION
R
R
Reserved. These bits return 0s when read.
GUID_ROM
The PCI4450 sets this bit if the serial ROM is detected. If the serial ROM is present, then the
Bus_Info_Block will be automatically loaded on hardware reset.
23–16
version
R
Major version of the Open HCI. The PCI4450 is compliant with the OHCI specification version 1.00; thus,
this field reads 8’h01.
15–8
7–0
RSVD
R
R
Reserved. These bits return 0s when read.
revision
Minor version of the Open HCI. The PCI4450 is compliant with the OHCI specification version 1.00; thus,
this field reads 8’h00.
143
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
GUID ROM register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GUID ROM
RSU
0
R
0
R
0
R
0
R
0
R
0
RSU
R
0
8
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
0
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
Name
Type
Default
GUID ROM
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
GUID ROM
Read-only, Read/Set/Update, Read/Update
Offset:
Default:
04h
00XX 0000h
Description: This register is used to access the serial ROM, and is only applicable if the
Version.GUID_ROM bit is set.
Table 98. GUID ROM Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
addrReset
RSU
Software sets this bit to reset the GUID ROM address to 0. When the PCI4450 completes the reset, it
clears this bit. The PCI4450 does not automatically fill rdData with the 0 byte.
th
30–26
25
RSVD
rdStart
R
Reserved. These bits return 0s when read.
RSU
A read of the currently addressed byte is started when this bit is set. This bit is automatically cleared
when the PCI4450 completes the read of the currently addressed GUID ROM byte.
24
RSVD
rdData
RSVD
R
RU
R
Reserved. ThIs bit returns 0 when read.
23–16
15–0
This field represents the data read from the GUID ROM.
Reserved. These bits return 0s when read.
144
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
asynchronous transmit retries register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous transmit retries
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Asynchronous transmit retries
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Asynchronous transmit retries
Read-only, Read/Write
08h
0000 0000h
Description: This register indicates the number of times the PCI4450 will attempt a retry for asynchronous
DMA request transmit and for asynchronous physical and DMA response transmit.
Table 99. Asynchronous Transmit Retries Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–29
secondLimit
R
The second limit field returns 0s when read, since outbound dual-phase retry is not
implemented.
28–16
15–12
11–8
cycleLimit
RSVD
R
R
The cycle limit field returns 0s when read, since outbound dual-phase retry is not implemeted.
Reserved. These bits return 0s when read.
maxPhysRespRetries
R/W
The maxPhysRespRetries field tells the physical response unit how many times to attempt to
retry the transmit operation for the response packet when a busy acknowledge or
ack_data_error is received from the target node.
7–4
3–0
maxATRespRetries
maxATReqRetries
R/W
R/W
The maxATRespRetries field tells the asynchronous transmit response unit how many times
to attempt to retry the transmit operation for the response packet when a busy acknowledge
or ack_data_error is received from the target node.
The maxATReqRetries field tells the asynchronous transmit DMA request unit how many
times to attempt to retry the transmit operation for the response packet when a busy
acknowledge or ack_data_error is received from the target node.
145
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
CSR data register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR data
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
CSR data
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
CSR data
Read-only
0Ch
XXXX XXXXh
Description: This register is used to access the bus management CSR registers from the host through
compare-swap operations. This register contains the data to be stored in a CSR if the
compare is successful.
CSR compare register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR compare
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
CSR compare
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
CSR compare
Read-only
10h
XXXX XXXXh
Description: This register is used to access the bus management CSR registers from the host through
compare-swap operations. This register contains the data to be compared with the existing
value of the CSR resource.
146
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
CSR control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR control
RU
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
CSR control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
X
R/W
X
Register:
Type:
CSR control
Read-only, Read/Update, Read/Write
Offset:
Default:
14h
0000 0000h
Description: This register is used to access the bus management CSR registers from the host through
compare-swap operations. This register is used to control the compare-swap operation and
select the CSR resource.
Table 100. CSR Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
csrDone
RU
This bit is set by the PCI4450 when a compare-swap operation is complete. It is reset whenever this
register is written.
30–2
1–0
RSVD
csrSel
R
Reserved. These bits return 0s when read.
R/W
This field selects the CSR resource as follows:
00 = BUS_MANAGER_ID
01 = BANDWIDTH_AVAILABLE
10 = CHANNELS_AVAILABLE_HI
11 = CHANNELS_AVAILABLE_LO
147
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
configuration ROM header register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Configuration ROM header
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Configuration ROM header
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Register:
Type:
Configuration ROM header
Read/Write
Offset:
Default:
18h
0000 XXXXh
Description: This register externally maps to the first quadlet of the 1394 configuration ROM, offset
48’hFFFF_F000_0400.
Table 101. Configuration ROM Header Register Description
BIT
FIELD NAME
info_length
TYPE
R/W
R/W
R/W
DESCRIPTION
31–24
23–16
15–0
IEEE1394 bus mgmt field. Must be valid when HCControl.linkEnable bit is set.
IEEE1394 bus mgmt field. Must be valid when HCControl.linkEnable bit is set.
crc_length
rom_crc_value
IEEE1394 bus management field. Must be valid at any time the HCControl.linkEnable bit is set. The
reset value is undefined if no serial ROM is present. If a serial ROM is present, then this field is loaded
from the serial ROM.
bus identification register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Bus identification
R
0
R
0
R
1
R
1
R
0
R
0
R
0
9
R
1
8
R
0
7
R
0
6
R
1
5
R
1
4
R
0
3
R
0
2
R
1
1
R
1
0
15
14
13
12
11
10
Name
Type
Default
Bus identification
R
0
R
0
R
1
R
1
R
1
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
1
R
0
R
0
Register:
Type:
Bus identification
Read-only
Offset:
Default:
1Ch
3133 3934h
Description: This register externally maps to the first quadlet in the Bus_Info_Block, and contains the
constant 32’h31333934, which is the ASCII value of 1394.
148
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
bus options register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Bus options
R/W
X
R/W
X
R/W
X
R/W
X
R/W
0
R
0
R
0
9
R
0
8
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
7
6
5
4
3
2
1
0
Name
Type
Default
Bus options
R/W
1
R/W
0
R/W
1
R/W
0
R
0
R
0
R
0
R
0
R/W
X
R/W
X
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Offset:
Default:
Bus options
Read-only, Read/Write
20h
X0XX A0X2h
Description: This register externally maps to the second quadlet of the Bus_Info_Block.
Table 102. Bus Options Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
irmc
R/W
Isochronous resource manager capable. IEEE1394 bus management field. Must be valid when
HCControl.linkEnable bit is set.
30
29
28
cmc
isc
R/W
R/W
R/W
Cycle master capable. IEEE1394 bus management field. Must be valid when HCControl.linkEnable bit is
set.
Isochronous support capable. IEEE1394 bus management field. Must be valid when
HCControl.linkEnable bit is set.
bmc
Bus manager capable. IEEE1394 bus management field. Must be valid when HCControl.linkEnable bit is
set.
27
pmc
RSVD
R/W
R
IEEE1394 bus management field. Must be valid when HCControl.linkEnable bit is set.
Reserved. These bits return 0s when read.
26–24
23–16
cyc_clk_acc
R/W
Cycle master clock accuracy. (accuracy in parts per million) IEEE1394 bus management field. Must be
valid when HCControl.linkEnable bit is set.
15–12
max_rec
R/W
IEEE 1394 bus management field. Hardware shall initialize max_rec to indicate the maximum number
of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes
must be 512 greater, and is calculated by 2^(max_rec + 1). Software may change max_rec, however
this field must be valid at any time the HCControl.linkEnable bit is set. A received block write request
packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not
affected by a soft reset, and defaults to value indicating 2048 bytes on hard reset.
11–8
7–6
RSVD
g
R
Reserved. These bits return 0s when read.
R/W
Generationcounter. This field shall be incremented is any portion the configuration ROM hasincremented
since the prior bus reset.
5–3
2–0
RSVD
R
R
Reserved. These bits return 0s when read.
Lnk_spd
Link speed. This field returns 010, indicating that the link speeds of 100, 200 and 400 Mbits/s are
supported.
149
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
GUID high register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GUID high
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
GUID high
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
GUID high
Read-only
24h
0000 0000h
Description: This register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to
the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and
chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID
value. If a serial ROM is detected, then the contents of this register are loaded through the
serial ROM interface after a PCI reset. At that point, the contents of this register cannot be
changed. IfnoserialROMisdetected, thenthisregistermaybewrittenoncetosetthevalueof
this register. At that point, the contents of this register cannot be changed.
GUID low register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GUID low
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
GUID low
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
GUID low
Read-only
28h
0000 0000h
Description: This register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to
chip_ID_lo in the Bus_Info_Block. This register initializes to 0s on a hardware reset, and
behaves identical to the GUID high register.
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PC Card and OHCI Controller
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configuration ROM mapping register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Configuration ROM mapping
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Configuration ROM mapping
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Configuration ROM mapping
Read-only, Read/Write
34h
0000 0000h
Description: This register contains the start address within system memory that will map to the start
address of 1394 configuration ROM for this node.
Table 103. Configuration ROM Mapping Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–10
configROMaddr
R/W
If a quadlet read request to 1394 offset 48’hFFFF_F000_0400 through offset 48’hFFFF_F000_07FF
is received, then the low order 10 bits of the offset are added to this register to determine the host
memory address of the read request.
9–0
RSVD
R
Reserved. These bits return 0s when read.
posted write address low register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Posted write address low
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Posted write address low
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Offset:
Default:
Posted write address low
Read/Update
38h
XXXX XXXXh
Description: This register is used to communicate error information if a write request is posted and an error
occurs while writing the posted data packet.
Table 104. Posted Write Address Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–0
offsetLo
RU
The lower 32 bits of the 1394 destination offset of the write request that failed.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
posted write address high register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Posted write address high
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Posted write address high
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Posted write address high
Read/Update
Offset:
Default:
3Ch
XXXX XXXXh
Description: This register is used to communicate error information if a write request is posted and an error
occurs while writing the posted data packet.
Table 105. Posted Write Address High Register Description
BIT
31–16
15–0
FIELD NAME
sourceID
TYPE
RU
DESCRIPTION
This bus and node number of the node that issued the write request that failed.
The upper 16 bits of the 1394 destination offset of the write request that failed.
offsetHi
RU
vendor ID register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Vendor ID
Read-only
40h
0000 0000h
Description: The vendor ID register holds the company ID of an organization that specifies any
vendor-unique registers. The PCI4450 does not implement Texas Instruments unique
behavior with regards to Open HCI. Thus this register is read-only and returns 0s when read.
152
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
host controller control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Host controller control
RSC
0
R
X
R
0
R
0
R
0
R
0
R
0
9
R
0
8
RC
0
RSC
R
0
5
R
0
4
RSC
RSC
X
RSC RSCU
0
0
0
0
15
14
13
12
11
10
7
6
3
2
1
0
Name
Type
Default
Host controller control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Host controller control
Read/Set/Clear/Update
Offset:
50h
54h
set register
clear register
Default:
X00X 0000h
Description: This set/clear register pair provides flags for controlling the PCI4450 link function.
Table 106. Host Controller Control Register Description
BIT
31
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. These bits return 0s when read.
30
noByteSwapData
RSC
This bit is used to control whether physical accesses to locations outside the PCI4450 itself as
well as any other DMA data accesses should be swapped.
29–24
23
RSVD
R
Reserved. These bits return 0s when read.
programPhyEnable
RC
This bit informs upper level software that lower level software has consistently configured the
p1394a enhancements in the Link and PHY. When 1 generic software such as the OHCI driver
is responsible for configuring p1394a enhancements in the PHY and the aPhyEnhanceEnable
bit in the PCI4450. When 0, the generic software may not modify the p1394a enhancements in
the PCI4450 or PHY and cannot interpret the setting of aPhyEnhanceEnable. This bit can
be initialized from serial EEPROM.
22
aPhyEnhanceEnable
RSC
When the programPhyenable is 1 and link enable is 1, the OHCI driver can set this bit to use all
p1394a enhancements. When programPhyEnable is set 0, the software shall not change PHY
enhancements or the aPhyEnhanceEnable bit.
21–20
19
RSVD
LPS
R
Reserved. These bits return 0s when read.
RSC
This bit is used to control the link power status. Software must set LPS to 1 to permit the link-PHY
communication. A 0 prevents link-PHY communication.
18
17
postedWriteEnable
linkEnable
RSC
RSC
This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only
when linkEnable is 0.
This bit is cleared to 0 by a hardware reset or software reset. Software must set this bit to 1 when
the system is ready to begin operation and then force a bus reset. This bit is necessary to keep
other nodes from sending transactions before the local system is ready. When this bit is clear
the PCI4450 is logically and immediately disconnected from the 1394 bus, no packets will
be received or processed nor will packets be transmitted.
16
SoftReset
RSVD
RSCU When set to 1, all PCI4450 state is reset, all FIFO’s are flushed, and all OHCI registers are set to
their hardware reset values unless otherwise specified. PCI registers are not affected by this bit.
This bit remains set to 1 while the softReset is in progress and reverts back to 0 when the reset
has completed.
15–0
R
Reserved. These bits return 0s when read.
153
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
self ID buffer pointer register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Self ID buffer pointer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Self ID buffer pointer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Self ID buffer pointer
Read-only, Read/Write
64h
XXXX XX00h
Description: This register points to the 2-Kbyte aligned base address of the buffer in host memory where
the self ID packets will be stored during bus initialization. Bits 31–11 are read/writeaccessible.
self ID count register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Self ID count
RU
X
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
7
6
5
4
3
2
1
0
Name
Type
Default
Self ID count
R
0
R
0
R
0
R
0
R
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
R
0
R
0
Register:
Type:
Offset:
Default:
Self ID count
Read/Update
68h
X0XX 0000h
Description: This register keeps a count of the number of times the bus self ID process has occurred, flags
self ID packet errors, and keeps a count of the amount of self ID data in the self ID buffer.
Table 107. Self ID Count Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
selfIDError
RU
Whenthisbitis1,anerrorwasdetectedduringthemostrecentselfIDpacketreception.Thecontents
of the self ID buffer are undefined. This bit is cleared after a self ID reception in which no errors are
detected. Note that an error can be a hardware error or a host bus write error.
30–24
23–16
RSVD
R
Reserved. These bits return 0s when read.
selfIDGeneration
RU
The value in this field increments each time a bus reset is detected. This field rolls over to 0 after
reaching 255.
15–11
10–2
RSVD
R
Reserved. These bits return 0s when read.
selfIDSize
RU
This field indicates the number of quadlets that have been written into the self ID buffer for the current
selfIDGeneration. This includes the header quadlet and the self ID data. This field is cleared to 0
when the self ID reception begins.
1–0
RSVD
R
Reserved. These bits return 0s when read.
154
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
ISO receive channel mask high register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
ISO receive channel mask high
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
ISO receive channel mask high
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
ISO receive channel mask high
Read/Set/Clear
Offset:
70h
74h
set register
clear register
Default:
XXXX XXXXh
Description: This set/clear register is used to enable packet receives from the upper 32 isochronous data
channels. A read from either the set register or clear register returns the value of the
IRChannelMaskHi register.
Table 108. ISO Receive Channel Mask High Register Description
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
FIELD NAME
isoChannel63
isoChannel62
isoChannel61
isoChannel60
isoChannel59
isoChannel58
isoChannel57
isoChannel56
isoChannel55
isoChannel54
isoChannel53
isoChannel52
isoChannel51
isoChannel50
isoChannel49
isoChannel48
isoChannel47
isoChannel46
isoChannel45
isoChannel44
isoChannel43
isoChannel42
isoChannel41
isoChannel40
TYPE
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
DESCRIPTION
When set, the PCI4450 is enabled to receive from iso channel number 63.
When set, the PCI4450 is enabled to receive from iso channel number 62.
When set, the PCI4450 is enabled to receive from iso channel number 61.
When set, the PCI4450 is enabled to receive from iso channel number 60.
When set, the PCI4450 is enabled to receive from iso channel number 59.
When set, the PCI4450 is enabled to receive from iso channel number 58.
When set, the PCI4450 is enabled to receive from iso channel number 57.
When set, the PCI4450 is enabled to receive from iso channel number 56.
When set, the PCI4450 is enabled to receive from iso channel number 55.
When set, the PCI4450 is enabled to receive from iso channel number 54.
When set, the PCI4450 is enabled to receive from iso channel number 53.
When set, the PCI4450 is enabled to receive from iso channel number 52.
When set, the PCI4450 is enabled to receive from iso channel number 51.
When set, the PCI4450 is enabled to receive from iso channel number 50.
When set, the PCI4450 is enabled to receive from iso channel number 49.
When set, the PCI4450 is enabled to receive from iso channel number 48.
When set, the PCI4450 is enabled to receive from iso channel number 47.
When set, the PCI4450 is enabled to receive from iso channel number 46.
When set, the PCI4450 is enabled to receive from iso channel number 45.
When set, the PCI4450 is enabled to receive from iso channel number 44.
When set, the PCI4450 is enabled to receive from iso channel number 43.
When set, the PCI4450 is enabled to receive from iso channel number 42.
When set, the PCI4450 is enabled to receive from iso channel number 41.
When set, the PCI4450 is enabled to receive from iso channel number 40.
8
155
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 108. ISO Receive Channel Mask High Register Description (Continued)
BIT
7
FIELD NAME
isoChannel39
isoChannel38
isoChannel37
isoChannel36
isoChannel35
isoChannel34
isoChannel33
isoChannel32
TYPE
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
DESCRIPTION
When set, the PCI4450 is enabled to receive from iso channel number 39.
When set, the PCI4450 is enabled to receive from iso channel number 38.
When set, the PCI4450 is enabled to receive from iso channel number 37.
When set, the PCI4450 is enabled to receive from iso channel number 36.
When set, the PCI4450 is enabled to receive from iso channel number 35.
When set, the PCI4450 is enabled to receive from iso channel number 34.
When set, the PCI4450 is enabled to receive from iso channel number 33.
When set, the PCI4450 is enabled to receive from iso channel number 32.
6
5
4
3
2
1
0
ISO receive channel mask low register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
ISO receive channel mask low
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
ISO receive channel mask low
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
ISO receive channel mask low
Read/Set/Clear
Offset:
78h
7Ch
set register
clear register
Default:
XXXX XXXXh
Description: This set/clear register is used to enable packet receives from the lower 32 isochronous data
channels.
Table 109. ISO Receive Channel Mask Low Register Descriptions
BIT
31
30
L
FIELD NAME
isoChannel31
isoChannel30
L
TYPE
RSC
RSC
L
DESCRIPTION
When set, the PCI4450 is enabled to receive from iso channel number 31.
When set, the PCI4450 is enabled to receive from iso channel number 30.
Bits 29 through 2 follow the same pattern
1
isoChannel1
isoChannel0
RSC
RSC
When set, the PCI4450 is enabled to receive from iso channel number 1.
When set, the PCI4450 is enabled to receive from iso channel number 0.
0
156
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
interrupt event register
Bit
31
30
29
28
27
26
25
24
Interrupt event
RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
R
0
R
X
R
0
R
0
R
0
R
0
2
RSCU RSCU
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Name
Type
Default
Interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
RSCU RSCU
RU
X
RU
X
RSCU RSCU RSCU RSCU RSCU RSCU
X
X
X
X
X
X
X
X
Register:
Type:
Interrupt event
Read/Set/Clear/Update
Offset:
80h
84h
set register
clear register [returns IntEvent and IntMask when read]
Default:
XXXX 0XXXh
Description: This set/clear register reflects the state of the various PCI4450 interrupt sources. The
interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a
1 in the corresponding bit in the set register. The only mechanism to clear the bits in this
register is to write a 1 to the corresponding bit in the clear register.
Table 110. Interrupt Event Register Description
BIT
31
FIELD NAME
RSVD
TYPE
DESCRIPTION
R
R
R
Reserved. This bit returns 0 when read.
Vendor defined.
30
vendorSpecific
RSVD
29–27
26
Reserved. These bits return 0s when read.
phyRegRcvd
cycleTooLong
RSCU The PCI4450 has received a PHY register data byte which can be read from the PHY control register.
25
RSCU If LinkControl.cycleMaster is set, this indicated that over 125 µs elapsed between the start of sending
a cycle start packet and the end of a subaction gap. LinkControl.cycleMaster is cleared by this event.
24
unrecoverableError RSCU This event occurs when the PCI4450 encounters any error that forces it to stop operations on any or
all of its subunits. For example, when a DMA context sets its dead bit. While unrecoverableError is
set, all normal interrupts for the context(s) that caused this interrupt will be blocked from being set.
23
22
cycleInconsistent
cycleLost
RSCU A cycle start was received that had an isochronous cycleTimer.seconds and isochronous
cycleTimer.count different from the value in the CycleTimer register.
RSCU A lost cycle is indicated when no cycle_start packet is sent/received between two successive
cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately
follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after
a cycleSynch event without an intervening cycle start. CycleLost may be set either when it occurs
or when logic predicts that it will occur.
th
21
20
cycle64Seconds
cycleSynch
RSCU Indicates that the 7 bit of the cycle second counter has changed.
RSCU Indicates that a new isochronous cycle has started and is set when the low order bit of the cycle count
toggles.
19
18
17
phy
RSCU Indicates the PHY requests an interrupt through a status transfer.
RSVD
R
Reserved. These bits return 0s when read.
busReset
RSCU Indicates that the PHY chip has entered bus reset mode.
157
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 110. Interrupt Event Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
16
selfDcomplete
RSCU A selfID packet stream has been received. It will be generated at the end of the bus initialization
process. This bit is turned off simultaneously when IntEvent.busReset is turned on.
15–10
9
RSVD
R
Reserved. These bits return 0s when read.
lockRespErr
RSCU Indicates that the PCI4450 sent a lock response for a lock request to a serial bus register, but did not
receive an ack_complete.
8
7
postedWriteErr
isochRx
RSCU Indicates that a host bus error occurred while the PCI4450 was trying to write a 1394 write request,
which had already been given an ack_complete, into system memory.
RU
Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have
generated and interrupt. This is not a latched event, it is the OR’ing of all bits in (isoRecvIntEvent
and isoRecvIntMask). The isoRecvIntEvent register indicates which contexts have interrupted.
6
iscohTx
RU
Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have
generated and interrupt. This is not a latched event, it is the OR’ing of all bits in (isoXmitIntEvent
and isoXmitIntMask). The isoXmitIntEvent register indicates which contexts have interrupted.
5
4
3
2
1
0
RSPkt
RQPkt
RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the
descriptor’s xferStatus and resCount fields have been updated.
RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the
descriptor’s xferStatus and resCount fields have been updated.
ARRS
RSCU Async receive response DMA interrupt. This bit is conditionally set upon completion of an ARRS
context command descriptor.
ARRQ
RSCU Async receive request DMA interrupt. This bit is conditionally set upon completion of an ARRQ DMA
context command descriptor.
respTxComplete
reqTxComplete
RSCU Asynchronous response transmit DMA interrupt. This bit is conditionally set upon completion of an
ATRS DMA command.
RSCU Asynchronous request transmit DMA interrupt. This bit is conditionally set upon completion of an
ATRQ DMA command.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
interrupt mask register
Bit
31
30
29
28
27
26
25
24
Interrupt mask
RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
RSC
0
R
X
R
0
R
0
R
0
R
0
2
RSCU RSCU
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Name
Type
Default
Interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
RSCU RSCU
RU
X
RU
X
RSCU RSCU RSCU RSCU RSCU RSCU
X
X
X
X
X
X
X
X
Register:
Type:
Interrupt mask
Read/Set/Clear
Offset:
88h
8Ch
set register
clear register
Default:
XXXX 0XXXh
Description: This set/clear register is used to enable the various PCI4450 interrupt sources. Reads from
either the set register or the clear register always return IntMask. In all cases except
masterIntEnable (bit 31), the enables for each interrupt event align with the event register bits
detailed in Table 110.
Table 111. Interrupt Mask Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
masterIntEnable
RSC
When set, external interrupts will be generated in accordance with the IntMask register. If clear, no
external interrupts will be generated.
30–0
See Table 110
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
isochronous transmit interrupt event register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous transmit interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Isochronous transmit interrupt event
Read/Set/Clear
Offset:
90h
84h
set register
clear register [returns IsoXmitEvent and IsoXmitMask when read]
Default:
0000 00XXh
Description: This set/clear register reflects the interrupt state of the isochronous transmit contexts. An
interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST
command completes and its interrupt bits are set. Upon determining that the IntEvent.isochTx
interrupt has occurred, software can check this register to determine which context(s) caused
the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt
signal, orbywritinga1inthecorrespondingbitinthesetregister. Theonlymechanismtoclear
the bits in this register is to write a 1 to the corresponding bit in the clear register.
Table 112. Isochronous Transmit Interrupt Event Register Description
BIT
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. These bits return 0s when read.
31–8
7
6
5
4
3
2
1
0
isoXmit7
isoXmit6
isoXmit5
isoXmit4
isoXmit3
isoXmit2
isoXmit1
isoXmit0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Isochronous transmit channel 7 caused the isochTx interrupt.
Isochronous transmit channel 6 caused the isochTx interrupt.
Isochronous transmit channel 5 caused the isochTx interrupt.
Isochronous transmit channel 4 caused the isochTx interrupt.
Isochronous transmit channel 3 caused the isochTx interrupt.
Isochronous transmit channel 2 caused the isochTx interrupt.
Isochronous transmit channel 1 caused the isochTx interrupt.
Isochronous transmit channel 0 caused the isochTx interrupt.
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
isochronous transmit interrupt mask register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous transmit interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Isochronous transmit interrupt mask
Read/Set/Clear
Offset:
98h
9Ch
set register
clear register
Default:
0000 00XXh
Description: This set/clear register is used to enable the isochTx interrupt source on a per channel basis.
Reads from either the set register or the clear register always return IsoXmitIntMask. In all
cases the enables for each interrupt event align with the event register bits detailed in
Table 112.
161
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
isochronous receive interrupt event register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Isochronous receive interrupt event
Read/Set/Clear
Offset:
A0h
A4h
set register
clear register [returns IsoRecvEvent and IsoRecvMask when read]
Default:
0000 000Xh
Description: This set/clear register reflects the interrupt state of the isochronous receive contexts. An
interrupt is generated on behalf of an isochronous receive context if an INPUT_* command
completes and its interrupt bits are set. Upon determining that the IntEvent.isochRx interrupt
has occurred, software can check this register to determine which context(s) caused the
interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal,
or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the
bits in this register is to write a 1 to the corresponding bit in the clear register.
Table 113. Isochronous Receive Interrupt Event Register Description
BIT
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. These bits return 0s when read.
31–4
3
2
1
0
isoRecv3
isoRecv2
isoRecv1
isoRecv0
RSC
RSC
RSC
RSC
Isochronous receive channel 3 caused the isochRx interrupt.
Isochronous receive channel 2 caused the isochRx interrupt.
Isochronous receive channel 1 caused the isochRx interrupt.
Isochronous receive channel 0 caused the isochRx interrupt.
162
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
isochronous receive interrupt mask register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
X
R
X
R
X
Register:
Type:
Isochronous receive interrupt mask
Read/Set/Clear
Offset:
A8h
ACh
set register
clear register
Default:
0000 000Xh
Description: This set/clear register is used to enable the isochRx interrupt source on a per channel basis.
Reads from either the set register or the clear register always return IsoRecvIntMask. In all
cases the enables for each interrupt event align with the event register bits detailed in
Table 113.
fairness control register (optional register)
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Fairness control
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Fairness control
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Fairness control
Read-only
Offset:
Default:
DCh
XXXX XX00h
Description: This register provides a mechanism by which software can direct the host controller to
transmit multiple asynchronous requests during a fairness interval.
Table 114. Link Control Register Description
BIT
31–8
7–0
FIELD NAME
RSVD
TYPE
DESCRIPTION
R
R
Reserved.
pri_req
This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY during fairness interval.
163
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
link control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Link control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
R
0
7
RSC RSCU RSC
R
0
3
R
0
2
R
0
1
R
0
0
0
X
X
X
15
14
13
12
11
10
8
6
5
4
Name
Type
Default
Link control
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
R
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
Register:
Type:
Link control
Read/Set/Clear/Update
Offset:
E0h
E4h
set register
clear register
Default:
00X0 0X00h
Description: This set/clear register provides the control flags that enable and configure the link core
protocol portions of the PCI4450. It contains controls for the receiver and cycle timer.
Table 115. Link Control Register Description
BIT
31–23
22
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. These bits return 0s when read.
cycleSource
RSC
When 1, the cycle timer will use an external source (CYCLEIN) to determine when to roll over the
cycle timer. When 0, the cycle timer rolls over when the timer reaches 3072 cycles of the
24.576 MHz clock (125 µs).
21
20
cycleMaster
RSCU When set, and the PHY has notified the PCI4450 that it is root, the PCI4450 will generate a cycle
start packet every time the cycle timer rolls over, based on the setting of the cycleSource bit.
When 0, the OHICLynx will accept received cycle start packets to maintain synchronization with
the node which is sending them. This bit is automatically reset when the cycleTooLong event
occurs and cannot be set until the IntEvent.cycleTooLong bit is cleared.
CycleTimerEnable
RSC
When 1, the cycle timer offset will count cycles of the 24.576 MHz clock and roll over at the
appropriate time based on the settings of the above bits. When 0, the cycle timer offset will not
count.
19–11
10
RSVD
R
Reserved. These bits return 0s when read.
RcvPhyPkt
RSC
When 1, the receiver will accept incoming PHY packets into the AR request context if the
AR request context is enabled. This does not control receipt of self-identification packets.
9
RcvSelfID
RSVD
RSC
R
When 1, the receiver will accept incoming self-identification packets. Before setting this bit to 1,
software must ensure that the self ID buffer pointer register contains a valid address.
8–0
Reserved. These bits return 0s when read.
164
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
node identification register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Node identification
RU
0
RU
0
R
0
R
0
RU
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Node identification
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
1
1
1
1
1
1
1
1
1
1
Register:
Type:
Offset:
Default:
Node identification
Read/Write/Update
E8h
0000 11XXh
Description: This register contains the address of the node on which the OHICLynx chip resides, and
indicates the valid node number status. The 16-bit combination of busNumber and
NodeNumber is referred to as the node ID.
Table 116. Node Identification Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
iDValid
RU
This bit indicates whether or not the PCI4450 has a valid node number. It is cleared when a 1394 bus
reset is detected and set when the PCI4450 receives a new node number from the PHY.
30
root
RSVD
RU
R
This bit is set during the bus reset process if the attached PHY is root.
Reserved. These bits return 0s when read.
29–28
27
CPS
RU
R
Set if the PHY is reporting that cable power status is OK (VP 8V).
Reserved. These bits return 0s when read.
26–16
15–6
RSVD
busNumber
RWU
This number is used to identify the specific 1394 bus the PCI4450 belongs to when multiple
1394-compatiable buses are connected via a bridge.
5–0
NodeNumber
RU
This number is the physical node number established by the PHY during self-identification. It is
automatically set to the value received from the PHY after the self-identification phase. If the PHY
sets the nodeNumber to 63, software should not set ContextControl.run for either of the AT DMA
contexts.
165
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PHY control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PHY control
RU
X
R
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PHY control
RWU RWU
R
0
R
0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
0
0
Register:
Type:
Offset:
Default:
PHY control
Read/Write/Update
ECh
XXXX 0XXXh
Description: This register is used to read or write a PHY register.
Table 117. PHY Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
rdDone
RU
This bit is cleared to 0 by the PCI4450 when either rdReg or wrReg is set to 1. This bit is set to 1 when a
register transfer is received from the PHY.
30–28
27–24
23–16
15
RSVD
rdAddr
rdData
rdReg
R
Reserved. These bits return 0s when read.
RU
This is the address of the register most recently received from the PHY.
This field is the contents of a PHY register which has been read.
RU
RWU
This bit is set by software to initiate a read request to a PHY register, and is cleared by hardware
when the request has been sent. The wrReg and rdReg bits must be used exclusively.
14
wrReg
RWU
This bit is set by software to initiate a write request to a PHY register, and is cleared by hardware
when the request has been sent. The wrReg and rdReg bits must be used exclusively.
13–12
11–8
7–0
RSVD
regAddr
wrData
R
Reserved. These bits return 0s when read.
R/W
R/W
This field is the address of the PHY register to be written or read.
This field is the data to be written to a PHY register, and is ignored for reads.
166
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
isochronous cycle timer register
Bit
31
30
29
28
27
26
25
Isochronous cycle timer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous cycle timer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
Isochronous cycle timer
Read/Write/Update
F0h
XXXX XXXXh
Description: This read/write register indicates the current cycle number and offset. When the PCI4450 is
cycle master, this register is transmitted with the cycle start message. When the PCI4450 is
not cycle master, this register is loaded with the data field in an incoming cycle start. In the
event that the cycle start message is not received, the fields can continue incrementing on
their own (if programmed) to maintain a local time reference.
Table 118. Isochronous Cycle Timer Register Description
BIT
FIELD NAME
cycleSeconds
cycleCount
TYPE
RWU
RWU
RWU
DESCRIPTION
This field counts seconds (cycleCount rollovers) modulo 128.
This field counts cycles (cycleOffset rollovers) modulo 8000.
31–25
24–12
11–0
cycleOffset
This field counts 24.576 MHz clocks modulo 3072, i.e., 125 µs. If an external 8 kHz clock configuration
is being used, then cycleOffset must be set to 0 at each tick of the external clock.
167
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
asynchronous request filter high register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Asynchronous request filter high
Read/Set/Clear
Offset:
100h set register
104h clear register
0000 0000h
Default:
Description: This set/clear register is used to enable asynchronous receive requests on a per node basis,
and handles the upper node IDs. When a packet is destined for either the physical request
context or the ARRQ context, the source node ID is examined. If the bit corresponding to the
node ID is not set in this register, then the packet is not acknowledged and the request is not
queued. The node ID comparison is done if the source node is on the same bus as the
PCI4450. All nonlocal bus sourced packets are not acknowledged unless bit 31 in this register
is set.
Table 119. Asynchronous Request Filter High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
asynReqAllBuses
RSC
If set to 1, all asynchronous requests received by the PCI4450 from nonlocal bus nodes will be
accepted.
30
29
28
27
26
25
24
23
22
21
20
asynReqResource62
asynReqResource61
asynReqResource60
asynReqResource59
asynReqResource58
asynReqResource57
asynReqResource56
asynReqResource55
asynReqResource54
asynReqResource53
asynReqResource52
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If set to 1 for local bus node number 62, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 61, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 60, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 59, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 58, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 57, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 56, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 55, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 54, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 53, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 52, asynchronous requests received by the PCI4450 from that
node will be accepted.
168
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 119. Asynchronous Request Filter High Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
19
asynReqResource51
RSC
If set to 1 for local bus node number 51, asynchronous requests received by the PCI4450 from that
node will be accepted.
18
17
16
15
14
13
12
11
10
9
asynReqResource50
asynReqResource49
asynReqResource48
asynReqResource47
asynReqResource46
asynReqResource45
asynReqResource44
asynReqResource43
asynReqResource42
asynReqResource41
asynReqResource40
asynReqResource39
asynReqResource38
asynReqResource37
asynReqResource36
asynReqResource35
asynReqResource34
asynReqResource33
asynReqResource32
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If set to 1 for local bus node number 50, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 49, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 48, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 47, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 46, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 45, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 44, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 43, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 42, asynchronous requests received by the PCI4450 from that
node will be accepted.
If set to 1 for local bus node number 41, asynchronous requests received by the PCI4450 from that
node will be accepted.
8
If set to 1 for local bus node number 40, asynchronous requests received by the PCI4450 from that
node will be accepted.
7
If set to 1 for local bus node number 39, asynchronous requests received by the PCI4450 from that
node will be accepted.
6
If set to 1 for local bus node number 38, asynchronous requests received by the PCI4450 from that
node will be accepted.
5
If set to 1 for local bus node number 37, asynchronous requests received by the PCI4450 from that
node will be accepted.
4
If set to 1 for local bus node number 36, asynchronous requests received by the PCI4450 from that
node will be accepted.
3
If set to 1 for local bus node number 35, asynchronous requests received by the PCI4450 from that
node will be accepted.
2
If set to 1 for local bus node number 34, asynchronous requests received by the PCI4450 from that
node will be accepted.
1
If set to 1 for local bus node number 33, asynchronous requests received by the PCI4450 from that
node will be accepted.
0
If set to 1 for local bus node number 32, asynchronous requests received by the PCI4450 from that
node will be accepted.
169
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
asynchronous request filter low register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Asynchronous request filter low
Read/Set/Clear
Offset:
108h set register
10Ch clear register
0000 0000h
Default:
Description: This set/clear register is used to enable asynchronous receive requests on a per node basis,
and handles the lower node IDs. Other than filtering different node IDs, this register behaves
identical to the asynchronous request filter high register.
Table 120. Asynchronous Request Filter Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
asynReqResource31
RSC
If set to 1 for local bus node number 31, asynchronous requests received by the PCI4450 from that
node will be accepted.
30
asynReqResource30
RSC
If set to 1 for local bus node number 30, asynchronous requests received by the PCI4450 from that
node will be accepted.
L
L
L
Bits 29 through 2 follow the same pattern.
1
asynReqResource1
RSC
If set to 1 for local bus node number 1, asynchronous requests received by the PCI4450 from that
node will be accepted.
0
asynReqResource0
RSC
If set to 1 for local bus node number 0, asynchronous requests received by the PCI4450 from that
node will be accepted.
170
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
physical request filter high register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Physical request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Physical request filter high
Read/Set/Clear
Offset:
110h set register
114h clear register
0000 0000h
Default:
Description: This set/clear register is used to enable physical receive requests on a per node basis, and
handles the upper node IDs. When a packet is destined for the physical request context, and
the node ID has been compared against the ARRQ registers, then the comparison is done
again with this register. If the bit corresponding to the node ID is not set in this register, then the
request will be handled by the ARRQ context instead of the physical request context.
Table 121. Physical Request Filter High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
physReqAllBusses
RSC
If set to 1, then all asynchronous requests received by the PCI4450 from nonlocal bus nodes will be
accepted.
30
29
28
27
26
25
24
23
22
21
20
19
physReqResource62
physReqResource61
physReqResource60
physReqResource59
physReqResource58
physReqResource57
physReqResource56
physReqResource55
physReqResource54
physReqResource53
physReqResource52
physReqResource51
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If set to 1 for local bus node number 62, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 61, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 60, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 59, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 58, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 57, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 56, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 55, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 54, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 53, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 52, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 51, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
171
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 121. Physical Request Filter High Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
18
physReqResource50
RSC
If set to 1 for local bus node number 50, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
17
16
15
14
13
12
11
10
9
physReqResource49
physReqResource48
physReqResource47
physReqResource46
physReqResource45
physReqResource44
physReqResource43
physReqResource42
physReqResource41
physReqResource40
physReqResource39
physReqResource38
physReqResource37
physReqResource36
physReqResource35
physReqResource34
physReqResource33
physReqResource32
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If set to 1 for local bus node number 49, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 48, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 47, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 46, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 45, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 44, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 43, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 42, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 41, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
8
If set to 1 for local bus node number 40, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
7
If set to 1 for local bus node number 39, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
6
If set to 1 for local bus node number 38, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
5
If set to 1 for local bus node number 37, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
4
If set to 1 for local bus node number 36, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
3
If set to 1 for local bus node number 35, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
2
If set to 1 for local bus node number 34, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
1
If set to 1 for local bus node number 33, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
0
If set to 1 for local bus node number 32, then physical requests received by the PCI4450 from that
node will be handled through the physical request context.
172
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
physical request filter low register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Physical request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Physical request filter low
Read/Set/Clear
Offset:
118h set register
11Ch clear register
0000 0000h
Default:
Description: This set/clear register is used to enable physical receive requests on a per node basis, and
handles the lower node IDs. When a packet is destined for the physical request context, and
the node ID has been compared against the asynchronous request filter registers, then the
node ID comparison is done again with this register. If the bit corresponding to the node ID is
not set in this register, then the request will be handled by the asynchronous request context
instead of the physical request context.
Table 122. Physical Request Filter Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
physReqResource31
RSC
If set to 1 for local bus node number 31, then physical requests received by the PCI4450 from
that node will be handled through the physical request context.
30
physReqResource30
RSC
If set to 1 for local bus node number 30, then physical requests received by the PCI4450 from
that node will be handled through the physical request context.
L
L
L
Bits 29 through 2 follow the same pattern.
1
physReqResource1
RSC
Ifsetto1forlocalbusnodenumber1, thenphysicalrequestsreceivedbythePCI4450fromthat
node will be handled through the physical request context.
0
physReqResource0
RSC
Ifsetto1forlocalbusnodenumber0, thenphysicalrequestsreceivedbythePCI4450fromthat
node will be handled through the physical request context.
173
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
physical upper bound register (optional register)
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical upper bound
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Physical upper bound
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Physical upper bound
Read-only
Offset:
Default:
120h
0000 0000h
Description: This register is an optional register and is not implemented. This register is read-only and
returns all 0s.
174
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
asynchronous context control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous context control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Asynchronous context control
RSCU
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Asynchronous context control
Read/Set/Clear/Update
Offset:
180h set register
184h clear register [ATRQ]
1A0h set register [ATRS]
1A4h clear register [ATRS]
1C0h set register [ARRQ]
1C4h clear register [ARRQ]
1E0h set register [ATRS]
[ATRQ]
1E4h clear register [ATRS]
0000 X0XXh
Default:
Description: This set/clear register controls the state and indicates status of the DMA context.
Table 123. Asynchronous Context Control Register Description
BIT
31–16
15
FIELD NAME
RSVD
TYPE
DESCRIPTION
R
Reserved. These bits return 0s when read.
run
RSCU This bit is set by software to enable descriptor processing for the context and cleared by software to stop
descriptor processing. The PCI4450 will only change this bit on a hardware or software reset.
14–13
12
RSVD
wake
R
Reserved. These bits return 0s when read.
RSU
Software sets this bit to cause the PCI4450 to continue or resume descriptor processing. The PCI4450 will
clear this bit on every descriptor fetch.
11
10
dead
active
RSVD
spd
RU
RU
R
ThePCI4450 sets thisbitwhenitencountersafatalerrorandclearsthebitwhensoftwareresetstherunbit.
The PCI4450 sets this bit to 1 when it is processing descriptors.
Reserved. These bits return 0s when read.
9–8
7–5
RU
This field indicates the speed at which a packet was received or transmitted, and only contains meaningful
information for receive contexts. This field is encoded as:
000b = 100 Mbits/sec,
001b = 200 Mbits/sec,
010b = 400 Mbits/sec, and all other values are reserved.
4–0
eventcode
RU
This field holds the acknowledge sent by the link core for this packet or an internally generated error code if
the packet was not transferred successfully.
175
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
asynchronous context command pointer register
Bit
31
30
29
28
27
26
Asynchronous context command pointer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous context command pointer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Asynchronous context command pointer
Read/Write/Update
19Ch [ATRQ]
1ACh [ATRS]
1CCh [ATRQ]
1ECh [ATRS]
Default:
XXXX XXXXh
Description: This register contains a pointer to the address of the first descriptor block that the PCI4450 will
access when software enables the context by setting the ContextControl.run bit.
Table 124. Asynchronous Context Command Pointer Register Description
BIT
31–4
3–0
FIELD NAME
descriptorAddress
Z
TYPE
RWU
RWU
DESCRIPTION
Contains the upper 28 bits of the address of a 16-byte aligned descriptor block.
Indicates the number of contiguous descriptors at the address pointed to by the descriptor
address. If Z is 0, it indicates that the descriptorAddress is not valid.
176
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
isochronous transmit context control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit context control
RSCU RSC
RSC
X
RSC
X
RSC
X
RSC RSC
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous transmit context control
RSC
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Isochronous transmit context control
Read/Set/Clear/Update
Offset:
200h + (16 * n)
204h + (16 * n)
XXXX X0XXh
set register
clear register
Default:
Description: This set/clear register controls options, state, and status for the isochronous transmit DMA
contexts. The n value in the following register addresses indicates the context number (n = 0,
1, 2, 3, …).
Table 125. Isochronous Transmit Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
cycleMatchEnable
RSCU When set to 1, processing will occur such that the packet described by the context’s first descriptor
block will be transmitted in the cycle whose number is specified in the cycleMatch field of this
register. The 13-bit cycleMatch field must match the 13-bit cycleCount field in the cycle start
packet that is sent or received immediately before isochronous transmission begins.
30–16
15
cycleMatch
run
RSC
Contains a 15-bit value, corresponding to the lower order 2 bits of cycleSeconds and 13-bit
cycleCount field. If cycleMatchEnable is set, then this IT DMA context will become enabled for
transmits when the bus cycleCount value equals the cycleMatch value.
RSC
This bit is set by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The PCI4450 will only change this bit on a hardware or software
reset.
14–13
12
RSVD
wake
R
Reserved. These bits return 0s when read.
RSU
Software sets this bit to cause the PCI4450 to continue or resume descriptor processing. The
PCI4450 will clear this bit on every descriptor fetch.
11
dead
RU
The PCI4450 sets this bit when it encounters a fatal error, and clears the bit when software resets
the run bit.
10
active
RSVD
RU
R
The PCI4450 sets this bit to 1 when it is processing descriptors.
Reserved. These bits return 0s when read.
9–8
7–5
4–0
spd
RU
RU
This field in not meaningful for isochronous transmit contexts.
event code
Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values
are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
177
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
isochronous transmit context command pointer register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Isochronous transmit context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Isochronous transmit context command pointer
Read-only
Offset:
Default:
20Ch + (16 * n)
XXXX XXXXh
Description: This register contains a pointer to the address of the first descriptor block that the PCI4450 will
access when software enables an ISO transmit context by setting the ContextControl.run bit.
Thenvalueinthefollowingregisteraddressesindicatesthecontextnumber(n=0, 1, 2, 3, …).
178
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
ischronous receive context control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Ischronous receive context control
RSC
X
RSC
X
RSCU
X
RSC
X
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Ischronous receive context control
RSCU
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Ischronous receive context control
Read/Set/Clear/Update
Offset:
400h + (32 * n)
404h + (32 * n)
X000 X0XXh
set register
clear register
Default:
Description: This set/clear register controls options, state, and status for the isochronous receive DMA
contexts. The n value in the following register addresses indicates the context number (n = 0,
1, 2, 3, …).
Table 126. Isochronous Receive Context Control
BIT
FIELD NAME
TYPE
DESCRIPTION
31
bufferFill
RSC
When set, received packets are placed back-to-back to completely fill each receive buffer.
When clear, each received packet is placed in a single buffer. If the multiChanMode bit is set
to 1, thisbitmustalsobesetto1. ThevalueofbufferFillmustnotbechangedwhileactiveorrunare
set.
30
isochHeader
RSC
When set to 1, received isochronous packets will include the complete 4-byte isochronous packet
header seen by the link layer. The end of the packet will be marked with a xferStatus in the first
doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent)
cycleStart packet. When clear, the packet header is stripped off of received isochronous packets.
The packet header, if received, immediately precedes the packet payload. The value of
isochHeader must not be changed while active or run are set.
29
28
cycleMatchEnable
multiChanMode
RSCU When set, the context will begin running only when the 13-bit cycleMatch field in the contextMatch
register matches the 13-bit cycleCount in the cycleStart packet. The effects of this bit, however,
are impacted by the values of other bits in this register. Once the context has become
active, hardware clears the cycleMatchEnable bit. The value of cycleMatchEnable must not be
changed while active or run are set.
RSC
When set, the corresponding isochronous receive DMA context will receive packets for all
isochronous channels enabled in the IRChannelMaskHi and IRChannelMaskLo registers. The
isochronous channel number specified in the IRDMA context match register is ignored. When 0,
the IRDMA context will receive packets for that single channel. Only one IRDMA context may
use the IRChannelMask registers. If more that one IRDMA context control register has the
multiChanMode bit set, results are undefined. The value of multiChanMode must not be
changed while active or run are set.
27–16
15
RSVD
run
R
Reserved. These bits return 0s when read.
RSCU This bit is set by software toenabledescriptorprocessingforthecontextandclearedbysoftwareto
stop descriptor processing. The PCI4450 will only change this bit on a hardware or software reset.
14–13
12
RSVD
wake
R
Reserved. These bits return 0s when read.
RSU
Software sets this bit to cause the PCI4450 to continue or resume descriptor processing. The
PCI4450 will clear this bit on every descriptor fetch.
11
10
dead
RU
RU
The PCI4450 sets this bit when it encounters a fatal error, and clears the bit when software resets
the run bit.
active
The PCI4450 sets this bit to 1 when it is processing descriptors.
179
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 126. Isochronous Receive Context Control (Continued)
9–8
7–5
RSVD
spd
R
Reserved. These bits return 0s when read.
RU
This field indicates the speed at which the packet was received.
3’b000 = 100 Mbits/sec,
3’b001 = 200 Mbits/sec, and
3’b010 = 400 Mbits/sec. All other values are reserved.
4–0
event code
RU
Following and INPUT* command, the error code is indicated in this field.
isochronous receive context command pointer register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Isochronous receive context command pointer
Read-only
Offset:
Default:
40Ch + (32 * n)
XXXX XXXXh
Description: This register contains a pointer to the address of the first descriptor block that the PCI4450 will
access when software enables an ISO receive context by setting the ContextControl.run bit.
Thenvalueinthefollowingregisteraddressesindicatesthecontextnumber(n=0, 1, 2, 3, …).
180
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
isochronous receive context match register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive context match
R
X
R
X
R
X
R
X
R
0
R
0
R
0
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive context match
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
0
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Isochronous receive context match
Read/Write
Offset:
Default:
410Ch + (32 * n)
XXXX XXXXh
Description: This register is used to start an isochronous receive context running on a specified cycle
number, to filter incoming isochronous packets based on tag values, and to wait for packets
with a specified sync value. The n value in the following register addresses indicates the
context number (n = 0, 1, 2, 3, …).
Table 127. Isochronous Receive Context Match Register Description
BIT
31
FIELD NAME
tag3
TYPE
R/W
R/W
R/W
R/W
R
DESCRIPTION
If set, this context will match on iso receive packets with a tag field of 2’b11.
If set, this context will match on iso receive packets with a tag field of 2’b10.
If set, this context will match on iso receive packets with a tag field of 2’b01.
If set, this context will match on iso receive packets with a tag field of 2’b00.
Reserved. These bits return 0s when read.
30
tag2
29
tag1
28
tag0
27–25
24–12
RSVD
cycleMatch
R/W
Contains a 13-bit value, corresponding to the 13-bit cycleCount field in the cycleStart packet. If
cycleMatchEnable is set, then this context is enabled for receives when the bus cycleCount value
equals the cycleMatch value.
11–8
sync
R/W
This field contains the 4-bit field which is compared to the sync field of each iso packet for this channel
when the command descriptor’s w field is set to 2’b11.
7
6
RSVD
R
Reserved. These bits return 0s when read.
tag1SyncFilter
R/W
If set and the tag1 bit is set , then packets with tag2b01 shall be accepted into the context if the two
most significant bits of the packets sync field are 2’b00. Packets with tag values other than 2’b01 are
filtered according to tag0, tag2 and tag3 without any additional restrictions.
If clear, this context will match on isochronous receive packets as specified in the tag0–3 bits with no
additional restrictions.
5–0
channelNumber
R/W
This 6-bit field indicates the isochronous channel number for which this IR DMA context will accept
packets.
181
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PC Card and OHCI Controller
SCPS046 – JANUARY 1999
GPIO interface
The GPIO interface consists of four general-purpose input output ports. On power reset, GPIO0 and GPIO1 are
enabled and are configured as bus manager contender (BMC) and link power status (LPS) , respectively. BMC
and LPS outputs can be configured via the GPIO control register in PCI Configuration space, as GPIO0 and
GPIO1. Figure 3 shows the schematic for GPIO0 and GPIO implementation.
GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register.
Figure 4 shows the schematic for GPIO2 and GPIO3 implementation.
GPIO Read Data
GPIO Port
GPIO Write Data
D
Q
BMC
GPIO_Invert
GPIO Enable
Disable BMC
Figure 22. BMC/LINKON/GPIO0
GPIO Read Data
GPIO Write Data
GPIO Port
D
Q
LPS
GPIO_Invert
GPIO Enable
Disable LPS
Figure 23. LPS/GPIO1
182
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
GPIO Read Data
GPIO Write Data
GPIO Port
D
Q
GPIO_Invert
GPIO Enable
Figure 24. GPIO2 and GPIO3
serial EEPROM
serial bus interface
The PCI4450 provides a serial bus interface to initiallize the 1394 Global Unique ID register and a few PCI
configuration registers through a serial EEPROM. The PCI4450 communicates with the serial EEPROM via the
2-wire serial interface.
After power-up the serial interface initializes the locations listed in Table 128. While the PCI4450 is accessing
the serial ROM , all incoming PCI Slave accesses are terminated with retry status. Table 129 shows the serial
ROM memory map required for initializing the PCI4450 registers.
Table 128. Registers and Bits Loadable through Serial EEPROM
BITS LOADED
OFFSET
REGISTER
1394 GlobalUniqueIDHi
FROM EEPROM
OHCI Register (24h)
OHCI Register(28h)
OHCI Register (50h)
PCI Register (2Ch)
PCI Register (2Dh)
PCI Register (3Eh)
PCI Register (F4h)
31–0
31–0
23
1394 GlobalUniqueIDLo
Host Control Register
PCI Subsytem ID
15–0
15–0
15–0
7, 2, 1
PCI Vendor ID
PCI Maximum Latency, PCI Minimum Grant
Link Enhancements Control Register
183
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 129. Serial EEPROM Map
BYTE
ADDRESS
BYTE DESCRIPTION
00
01
02
03
04
05
PCI maximum latency (4’h0)
PCI_Minimum grant (4’h0)
PCI vendor ID
PCI vendor ID (ms byte)
PCI subsytem ID (ls byte)
PCI subsytem ID
[7]
[6]
[5]
RSVD
[4]
[3]
[2]
[1]
[0]
Link_enhancement-
Control.enab_unfair
HCControl.
ProgramPhy
Enable
RSVD
RSVD Link_enhancement- Link_enhancement- RSVD
Control.enab_
insert_idle
Control.enab_accel
06
07
08
09
0A
0B
0C
0D
0E
Reserved
1394 GlobalUniqueIDHi (ls byte 0)
1394 GlobalUniqueIDHi (byte 1)
1394 GlobalUniqueIDHi (byte 2)
1394 GlobalUniqueIDHi (ms byte 3)
1394 GlobalUniqueIDLo (ls byte 0)
1394 GlobalUniqueIDLo (byte 1)
1394 GlobalUniqueIDLo (byte 2)
1394 GlobalUniqueIDLo (ms byte 3)
184
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
†
absolute maximum ratings over operating temperature ranges (unless otherwise noted)
Supply voltage range, V
Clamping voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CCP, CCA, CCB
Input voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCP
CCA
CCB
Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
ZV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Miscellaneous and Phy I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
CC
CC
CC
CC
Output voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
CC
CCA
CCB
Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
ZV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Miscellaneous and Phy I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
CC
CC
CC
CC
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
OK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
O O CC
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals are measured with
I
CC
respect to V
instead of V . PCCardterminalsaremeasuredwithrespecttoV
or V
. ZVterminalsandTTLsignalsare
CCB
CCP
CC
CCA
measured with respect to V . The limit specified applies for a dc condition.
CC
2. Applies for external output and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals are measured
O
CC
withrespecttoV
insteadofV . PCCardterminalsaremeasuredwithrespecttoV
orV
CCA
.ZVterminalsandTTLsignals
CCB
CCP
CC
are measured with respect to V . The limit specified applies for a dc condition.
CC
185
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
recommended operating conditions (see Note 3)
OPERATION
MIN
3
NOM
3.3
3.3
5
MAX
3.6
UNIT
V
V
Core voltage
Commercial
Commercial
3.3 V
3.3 V
5 V
V
CC
3
3.6
PCI I/O voltage, ZV Port I/O voltage
V
V
V
V
CCP
4.5
3
5.5
3.3 V
5 V
3.3
5
3.6
V
PC Card I/O voltage
Commercial
PCI
CCA/B
4.75
5.25
3.3 V
5 V
0.5 V
V
CCP
CCP
2
V
CCP
3.3 V
5 V
0.475 V
V
CCA/B
CCA/B
CCA/B
†
PC Card
PHY I/F
V
IH
High-level Input voltage
2.4
V
2
V
V
V
V
V
V
CC
CC
CC
‡
TTL
2
2.4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
§
Fail safe
3.3 V
5 V
0.3 V
CCP
PCI
V
V
0.8
3.3 V
5 V
0.325 V
CCA/B
†
V
IL
PC Card
PHY I/F
Low-level input voltage
0.8
0.8
0.8
0.8
V
V
V
‡
TTL
§
Fail safe
PCI
3.3 V
5 V
V
CCP
PC Card
PHY I/F
V
CCA/B
V
CC
V
V
Input voltage
V
V
I
‡
TTL
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
§
Fail safe
PCI
3.3 V
5 V
PC Card
PHY I/F
¶
Output voltage
O
‡
TTL
Fail safe
§
V
CC
4
PCI and PC Card
TTL and fail safe
t
t
Input transition times (t and t )
ns
r
f
6
T
Operating ambient temperature range
Virtual junction temperature
25
25
70
_C
_C
A
#
T
J
115
†
‡
Applies to external inputs and bidirectional buffers without hysteresis
TTL 4 mA pins are A_CVS1//A_VS1, A_CVS2//A_VS2, B_CVS1//B_VS1, B_CVS2//B_VS2, CLOCK, DATA, LATCH, SPKROUT,
MFUNC4–MFUNC0, SCL, SDA, ZV_UVx, ZV_PCLK, ZV_SDATA, ZV_LRCLK, ZV_MCLK, ZV_VSYNC, ZV_HREF, ZV_SCLK, ZV_Yx,
SUSPEND, LPS, PHY_LREQ.
TTL 8 mA pins are MFUNC6, MFUNC5, PHY_CTL0, PHY_CTL1, PHY_DATAx, and LINKON.
Fail-safe pin is RI_OUT (open drain).
Applies to external output buffers
§
¶
#
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
186
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
PINS
OPERATION TEST CONDITIONS
MIN
MAX UNIT
3.3 V
5 V
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= –0.5 mA
= –2 mA
= –0.15 mA
= –0.15 mA
= –4 mA
= –8 mA
= –4 mA
= –8 mA
= 1.5 mA
= 6 mA
0.9 V
OH
OH
OH
OH
OH
OL
OH
OH
OL
OL
OL
OL
OL
OL
OL
OL
OL
CC
2.4
PCI
3.3 V
5 V
0.9 V
CC
2.4
PC Card
PHY I/F
TTL
V
OH
V
High-level output voltage (see Note 4)
3.3 V
3.3 V
2.8
V
CC
V
CC
V
CC
–0.6
–0.6
–0.6
3.3 V
5 V
0.1 V
CC
PCI
0.55
V
V
3.3 V
5 V
= 0.7 mA
= 0.7 mA
= 4 mA
0.1 V
CC
PC Card
PHY I/F
0.55
3.3 V
3.3 V
0.5
0.5
0.5
0.5
Low-level output voltage
V
OL
= 8 mA
= 4 mA
TTL
V
V
= 8 mA
SERR
= 8 mA
0.5
–1
–1
10
3.6 V
5.25 V
3.6 V
V = V
I
CC
CC
CC
3-state output, high-impedance state
current (see Note 4)
I
I
Output pins
µA
OZL
V = V
I
†
†
V = V
I
3-state output, high-impedance state
current
Output pins
µA
µA
OZH
5.25 V
25
–1
V = V
I
CC
Input pins
I/O pins
Latch
V = GND
I
I
IL
V = GND
I
–10
–2
Low-level input current
V = GND
I
‡
3.6 V
10
V = V
I
CC
Input pins
‡
‡
‡
5.25 V
3.6 V
20
10
25
10
V = V
I
CC
CC
CC
CC
I
IH
µA
High-level input current (see Note 5)
V = V
I
I/O pins
5.25 V
3.6 V
V = V
I
Fail-safe pins
V = V
I
†
‡
For PCI pins, V = V
. For PC Card pins, V = V
CCP
. For ZV pins, V = V . For miscellaneous pins, V = V
CC
.
CC
I
I
CC(A/B)
For I/O pins, input leakage (I and I ) includes I leakage of the disabled output.
OZ
I
I
IL
IH
NOTES: 4. V
and I
are not tested on SERR (GFN pin Y20, GJG pin W18)and RI_OUT (GFN pin Y13, GJG pin R11) because they are
OH
OL
open-drain outputs.
5.
I
IH
is not tested on LATCH (GFN pin W12, GJG pin W11) because it is pulled up with an internal resistor.
187
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PCI clock/reset timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Figure 26 and Figure 27)
ALTERNATE
SYMBOL
TEST
CONDITIONS
PARAMETER
MIN
MAX
UNIT
t
t
t
Cycle time, PCLK
t
30
11
11
1
ns
ns
c
cyc
Pulse duration, PCLK high
Pulse duration, PCLK low
Slew rate, PCLK
t
high
wH
wL
t
ns
low
t , t
∆v/∆t
4
V/ns
ms
ms
r f
t
t
Pulse duration, RSTIN
t
1
w
rst
Setup time, PCLK active at end of RSTIN
t
100
su
rst-clk
PCI timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 7, Figure 25, and Figure 28)
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
PCLK-to-shared signal
valid delay time
t
11
val
inv
Propagation delay time,
See Note 6
C = 50 pF,
L
See Note 7
t
ns
pd
PCLK-to-shared signal
invalid delay time
t
2
2
t
t
t
t
Enable time, high impedance-to-active delay time from PCLK
Disable time, active-to-high impedance delay time from PCLK
Setup time before PCLK valid
t
ns
ns
ns
ns
en
dis
su
h
on
t
28
off
t
7
0
su
Hold time after PCLK high
t
h
NOTES: 6. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
7. This data sheet uses the following conventions to describe time ( t ) intervals. The format is t , where subscript A indicates the type
A
ofdynamicparameterbeingrepresented. Oneofthefollowingisused:t =propagationdelaytime, t = delay time, t =setuptime,
pd
d
su
and t = hold time.
h
Switching characteristics for PHY-Link interface
PARAMETER
MEASURED
–50% to 50%
–50% to 50%
–50% to 50%
MIN
6
TYP
MAX
UNIT
t
t
t
Setup time, Dn, CTLn, LREQ to PHY_CLK
Hold time, Dn, CTLn, LREQ before PHY_CLK
Delay time, PHY_CLK to Dn, CTLn
su
1
ns
h
2
11
d
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT PARAMETERS
†
I
‡
OL
TIMING
C
I
I
V
LOAD
(pF)
OL
OH
LOAD
(V)
PARAMETER
(mA)
(mA)
t
0
3
PZH
Test
Point
t
50
8
–8
en
t
t
t
PZL
PHZ
PLZ
From Output
Under Test
V
LOAD
t
t
50
50
8
8
–8
–8
1.5
‡
dis
pd
C
LOAD
†
‡
C
V
includes the typical load-circuit distributed capacitance.
LOAD
LOAD
I
OH
– V
OL
= 50 Ω, where V
= 0.6 V, I
= 8 mA
OL
OL
I
OL
LOAD CIRCUIT
V
Timing
Input
(see Note A)
CC
V
CC
50% V
High-Level
Input
CC
50% V
50% V
CC
CC
0 V
0 V
t
h
t
su
t
w
V
CC
90% V
Data
CC
V
CC
50% V
Input
50% V
CC
10% V
CC
CC
t
Low-Level
Input
0 V
50% V
50% V
CC
CC
0 V
t
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
Output
Control
(low-level
enabling)
V
CC
50% V
50% V
CC
CC
V
0 V
CC
Input
(see Note A)
t
50% V
50% V
CC
PZL
CC
t
PLZ
0 V
t
pd
V
t
CC
50% V
pd
V
Waveform 1
(see Notes B
and C)
CC
CC
OH
50% V
CC
In-Phase
Output
V
+ 0.3 V
OL
50% V
50% V
CC
CC
V
OL
V
OL
t
PHZ
t
pd
t
PZH
t
pd
V
OH
V
OH
Waveform 2
(see Notes B
and C)
V
– 0.3 V
OH
Out-of-Phase
Output
50% V
CC
50% V
50% V
CC
CC
50% V
V
OL
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, Z = 50 Ω, t = 6 ns.
O
r
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For t
and t
, V
PHZ OL
and V
are measured values.
OH
PLZ
Figure 25. Load Circuit and Voltage Waveforms
189
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PCI BUS PARAMETER MEASUREMENT INFORMATION
t
high
t
low
2 V
0.8 V
2 V MIN Peak-to-Peak
t
f
t
r
t
cyc
Figure 26. PCLK Timing Waveform
PCLK
t
rst
RSTIN
t
srst-clk
Figure 27. RSTIN Timing Waveforms
PCLK
1.5 V
t
t
inv
val
1.5 V
Valid
PCI Output
PCI Input
t
t
on
off
Valid
t
su
t
h
Figure 28. Shared Signals Timing Waveforms
190
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PC Card cycle timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and
I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address
setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output
PC Card cycles that are as close to the Intel 82365SL-DF timing as possible, while always slightly exceeding
the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput.
The PC Card address setup and hold times are a function of the wait-state bits. Table 130 shows address setup
time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 131 and Table 132 show command
active time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 133 shows address hold time
in PCLK cycles and nanoseconds for I/O and memory cycles.
Table 130. PC Card Address Setup Time, t
, 8-Bit and 16-Bit PCI Cycles
su(A)
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
3/90
Memory
Memory
WS1
WS1
0
1
2/60
4/120
Table 131. PC Card Command Active Time, t
, 8-Bit PCI Cycles
c(A)
WAIT-STATE BITS
TS1 – 0 = 01
(PCLK/ns)
WS
0
ZWS
0
X
1
19/570
23/690
7/210
1
I/O
0
00
01
10
11
00
0
19/570
23/690
23/690
23/690
7/210
X
X
X
1
Memory
Table 132. PC Card Command Active Time, t
, 16-Bit PCI Cycles
c(A)
WAIT-STATE BITS
TS1 – 0 = 01
(PCLK/ns)
WS
0
ZWS
0
X
1
7/210
11/330
N/A
1
I/O
0
00
01
10
11
00
0
9/270
13/390
17/510
23/630
5/150
X
X
X
1
Memory
191
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
Table 133. PC Card Address Hold Time, t
, 8-Bit and 16-Bit PCI Cycles
h(A)
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
2/60
2/60
3/90
Memory
Memory
WS1
WS1
0
1
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, memory cycles (for 100-ns common memory) (see Note 8 and Figure 29)
ALTERNATE
SYMBOL
MIN
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, CE1 and CE2 before WE/OE low
Setup time, CA25–CA0 before WE/OE low
T1
60
+2PCLK
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su
su
su
pd
w
T2
t
su(A)
Setup time, REG before WE/OE low
T3
Propagation delay time, WE/OE low to WAIT low
Pulse duration, WE/OE low
T4
T5
200
120
Hold time, WE/OE low after WAIT high
T6
h
Hold time, CE1 and CE2 after WE/OE high
Setup time (read), CDATA15–CDATA0 valid before OE high
Hold time (read), CDATA15–CDATA0 valid after OE high
Hold time, CA25–CA0 and REG after WE/OE high
Setup time (write), CDATA15–CDATA0 valid before WE low
Hold time (write), CDATA15–CDATA0 valid after WE low
T7
h
T8
su
h
T9
0
+1PCLK
60
T10
T11
T12
t
h(A)
h
su
h
240
NOTE 8: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle
type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be
observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, I/O cycles (see Figure 30)
ALTERNATE
MIN
MAX
UNIT
SYMBOL
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, REG before IORD/IOWR low
60
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su
su
su
pd
pd
w
Setup time, CE1 and CE2 before IORD/IOWR low
Setup time, CA25–CA0 valid before IORD/IOWR low
Propagation delay time, IOIS16 low after CA25–CA0 valid
Propagation delay time, IORD low to WAIT low
Pulse duration, IORD/IOWR low
t
+2PCLK
su(A)
35
35
T
cA
Hold time, IORD low after WAIT high
h
Hold time, REG low after IORD high
0
h
Hold time, CE1 and CE2 after IORD/IOWR high
Hold time, CA25–CA0 after IORD/IOWR high
Setup time (read), CDATA15–CDATA0 valid before IORD high
Hold time (read), CDATA15–CDATA0 valid after IORD high
Setup time (write), CDATA15–CDATA0 valid before IOWR low
Hold time (write), CDATA15–CDATA0 valid after IOWR high
120
h
t
+1PCLK
h
h(A)
10
0
su
h
90
90
su
h
192
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, miscellaneous (see Figure 31)
ALTERNATE
SYMBOL
PARAMETER
MIN
MAX
UNIT
BVD2 low to SPKROUT low
BVD2 high to SPKROUT high
IREQ to IRQ15–IRQ3
30
30
30
30
T27
t
pd
Propagation delay time
ns
T28
STSCHG to IRQ15–IRQ3
PC Card PARAMETER MEASUREMENT INFORMATION
CA25–CA0
REG
T10
CE1, CE2
T1
T5
T7
WE, OE
WAIT
T3
T6
T2
T4
T12
T9
T11
CDATA15–CDATA0
(write)
T8
CDATA15–CDATA0
(read)
With no wait state
With wait state
Figure 29. PC Card Memory Cycle
193
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
PC Card PARAMETER MEASUREMENT INFORMATION
CA25–CA0
IOIS16
T16
T22
REG
T20
T21
CE1, CE2
T14
T18
IORD, IOWR
WAIT
T13
T15
T19
T17
T26
T24
T25
CDATA15–CDATA0
(write)
T23
CDATA15–CDATA0
(read)
With no wait state
With wait state
Figure 30. PC Card I/O Cycle
BVD2
SPKROUT
IREQ
T27
T28
IRQ15–IRQ3
Figure 31. Miscellaneous PC Card Delay Times
194
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
MECHANICAL DATA
GFN (S-PBGA-N256)
PLASTIC BALL GRID ARRAY
27,20
26,80
24,70
24,00
SQ
SQ
24,13 TYP
0,635
1,27
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18 20
2
4
6
8
2,32
1,92
0,40
0,30
Seating Plane
0,15
0,80
0,60
M
0,10
0,70
0,50
4040185-2/B 11/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
195
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PCI4450 GFN/GJG
PC Card and OHCI Controller
SCPS046 – JANUARY 1999
MECHANICAL DATA
GJG (S-PBGA-N257)
PLASTIC BALL GRID ARRAY
16,10
SQ
14,40 TYP
15,90
0,80
W
V
U
T
R
P
N
M
L
K
J
H
G
F
0,80
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,12
0,08
M
0,08
0,45
0,35
0,45
4173511/A 08/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Micro Star is a trademark of Texas Instruments Incorporated.
196
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IMPORTANT NOTICE
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