PCM1608KY/2K [TI]
24-Bit, 192kHz Sampling, 8-Channel, Enhanced Multilevel, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER; 24位192kHz采样， 8通道，增强型多级Δ-Σ数位类比转换器
| 型号： | PCM1608KY/2K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-Bit, 192kHz Sampling, 8-Channel, Enhanced Multilevel, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总31页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM1608
PCM1608
SBAS164A – MARCH 2001
24-Bit, 192kHz Sampling, 8-Channel,
Enhanced Multilevel, Delta-Sigma
DIGITAL-TO-ANALOG CONVERTER
APPLICATIONS
FEATURES
● INTEGRATED A/V RECEIVERS
● DVD MOVIE AND AUDIO PLAYERS
● HDTV RECEIVERS
●
24-BIT RESOLUTION
●
ANALOG PERFORMANCE:
Dynamic Range: 100dB typ (PCM1608Y)
105dB typ (PCM1608KY)
SNR: 100dB typ (PCM1608Y)
105dB typ (PCM1608KY)
● CAR AUDIO SYSTEMS
● DVD ADD-ON CARDS FOR HIGH-END PCs
● DIGITAL AUDIO WORKSTATIONS
● OTHER MULTICHANNEL AUDIO SYSTEMS
THD+N: 0.003% typ (PCM1608Y)
0.002% typ (PCM1608KY)
Full-Scale Output: 3.1Vp-p typ
●
4x/8x OVERSAMPLING INTERPOLATION FILTER:
Stopband Attenuation: –55dB
Passband Ripple: ±0.03dB
DESCRIPTION
The PCM1608 is a CMOS monolithic integrated circuit that
features eight 24-bit audio Digital-to-Analog Converters
(DACs) and support circuitry in a small LQFP-48 package. The
DACs utilize Texas Instrument’s enhanced multi-level, delta-
sigma architecture that employs fourth-order noise shaping and
8-level amplitude quantization to achieve excellent signal-to-
noise performance and a high tolerance to clock jitter.
● SAMPLING FREQUENCY:
5kHz to 200kHz (Channels 1, 2, 7, and 8)
5kHz to 100kHz (Channels 3, 4, 5, and 6)
● ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO DATA
● DATA FORMATS: Standard, I2S, and Left-Justified
● SYSTEM CLOCK: 128, 192, 256, 384, 512, or 768fS
The PCM1608 accepts industry-standard audio data formats
with 16- to 24-bit audio data. Sampling rates up to 200kHz
(channels 1, 2, 7, and 8) or 100kHz (channels 3, 4, 5, and 6)
are supported. A full set of user-programmable functions are
accessible through a 4-wire serial control port that supports
register write and read functions.
●
USER-PROGRAMMABLE FUNCTIONS:
Digital Attenuation: 0dB to –63dB, 0.5dB/Step
Soft Mute
Zero Flags May Be Used As General-
Purpose Logic Output
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
●
DUAL-SUPPLY OPERATION:
+5V Analog, +3.3V Digital
●
●
+5V TOLERANT DIGITAL LOGIC INPUTS
PACKAGE: LQFP-48
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
PCM1608Y
LQFP-48
340
"
–25°C to +85°C
PCM1608Y
PCM1608Y
PCM1608Y/2K
PCM1608KY
250-Piece Tray
Tape and Reel
250-Piece Tray
Tape and Reel
"
"
"
"
PCM1608KY
LQFP-48
340
–25°C to +85°C
PCM1608KY
"
"
"
"
"
PCM1608KY/2K
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM1608Y/2K” will get a single 2000-piece Tape and Reel.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
Power Supply Voltage, VDD .............................................................. +4.0V
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
VCC .............................................................. +6.5V
Ground Voltage Differences.............................................................. ±0.1V
Digital Input Voltage ................................................ –0.3V to (6.5V + 0.3V)
mentsrecommendsthatallintegratedcircuitsbehandledwith
Input Current (except power supply) ............................................... ±10mA
Operating Temperature Under Bias ................................ –40°C to +125°C
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Storage Temperature ...................................................... –55°C to +150°C
Junction Temperature .................................................................... +150°C
ESD damage can range from subtle performance degradation
Lead Temperature (soldering, 5s)................................................. +260°C
Package Temperature (IR reflow, 10s) .......................................... +235°C
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit data, unless otherwise noted.
PCM1608Y
PCM1608KY
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
UNITS
24
Bits
DATA FORMAT
Audio Data Interface Formats
Audio Data Bit Length
Audio Data Format
Standard, I2S, Left-Justified
16, 18, 20, 24-Bits Selectable
MSB-First, Binary Two’s Complement
Sampling Frequency (fS)
VOUT 1, 2, 7, 8
VOUT 3, 4, 5, 6
5
5
200
100
kHz
kHz
System Clock Frequency
128, 192, 256, 384, 512, 768fS
TTL-Compatible
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level
VIH
2.0
VDC
VDC
VIL
0.8
Input Logic Current
(1)
IIH
IIL
IIH
IIL
VIN = VDD
VIN = 0V
VIN = VDD
VIN = 0V
10
µA
µA
µA
µA
(1)
–10
100
–10
(2)
65
(2)
Output Logic Level
VOH
VOL
IOH = –4mA
IOL = +4mA
2.4
VDC
VDC
1.0
DYNAMIC PERFORMANCE(3) (4)
PCM1608Y
THD+N at VOUT = 0dB
fS = 44.1kHz
fS = 96kHz
fS = 192Hz
fS = 44.1kHz
fS = 96kHz
0.003
0.005
0.006
1.25
1.40
1.65
100
99
98
100
99
98
98
0.01
%
%
%
%
%
THD+N at VOUT = –60dB
fS = 192kHz
%
Dynamic Range
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
fS = 44.1kHz
94
94
91
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise Ratio
Channel Separation
Level Linearity Error
fS = 96kHz
fS = 192kHz
VOUT = –90dB
97
96
±0.5
PCM1608
SBAS164A
2
ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit data, unless otherwise noted.
PCM1608Y
PCM1608KY
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PCM1608KY
THD+N at VOUT = 0dB
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
0.002
0.004
0.005
0.7
0.008
%
%
%
THD+N at VOUT = –60dB
fS = 44.1kHz
%
fS = 96kHz
0.9
%
fS = 192kHz
1.0
%
Dynamic Range
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
fS = 44.1kHz
98
98
94
105
103
102
105
103
102
103
101
100
±0.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise Ratio
Channel Separation
Level Linearity Error
fS = 96kHz
fS = 192kHz
VOUT = –90dB
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
±1.0
±1.0
±30
±6
±3
±60
% of FSR
% of FSR
mV
VOUT = 0.5VCC at Bipolar Zero
ANALOG OUTPUT
Output Voltage
Center Voltage
Full Scale (–0dB)
AC Load
62% of VCC
50% VCC
Vp-p
VDC
kΩ
Load Impedance
5
DIGITAL FILTER PERFORMANCE
Filter Characteristics 1, Sharp Roll-Off
Passband
±0.03dB
–3dB
0.454fS
0.487fS
Passband
Stopband
Passband Ripple
Stopband Attenuation
Stopband Attenuation
0.546fS
dB
dB
dB
±0.03
Stopband = 0.546fS
Stopband = 0.567fS
–50
–55
Filter Characteristics 2, Slow Roll-Off
Passband
Passband
±0.5dB
–3dB
0.198fS
0.390fS
Stopband
0.884fS
–40
Passband Ripple
Stopband Attenuation
Delay Time
±0.5
dB
dB
Stopband = 0.884fS
20/fS
±0.1
sec
dB
De-Emphasis Error
ANALOG FILTER PERFORMANCE
Frequency Response
f = 20kHz
f = 44kHz
–0.03
–0.20
dB
dB
POWER-SUPPLY REQUIREMENTS(4)
Voltage Range, VDD
VCC
Supply Current, IDD
+3.0
+4.5
+3.3
+5.0
18
40
40
+3.6
+5.5
25
VDC
VDC
mA
mA
mA
(5)
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
ICC
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
33
36
36
224
312
312
46
mA
mA
mA
mW
mW
mW
Power Dissipation
313
TEMPERATURE RANGE
Operation Temperature
Thermal Resistance
–25
+85
°C
θJA
LQFP-48
100
°C/W
NOTES: (1) Pins 31, 38, 40, 41, 45-47 (DATA4, SCKI, BCK, LRCK, DATA1, DATA2, DATA3). (2) Pins 34-37 (MDI, MC, ML, RST). (3) Analog performance
specifications are tested with a Shibasoku #725 THD Meter with 400Hz HPF on, 30kHz LPF on, average mode with 20kHz bandwidth limiting. The load
connected to the analog output is 5kΩ, or larger, via capacitive loading. (4) Conditions in 192kHz operation are: system clock = 128fS, DAC3 through DAC6
disabled in Register 8, and oversampling rate = 64fS in Register 12. (5) CLKO is disabled.
PCM1608
SBAS164A
3
BLOCK DIAGRAM
Output Amp and
Low-Pass Filter
VOUT
1
2
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
BCK
LRCK
Output Amp and
Low-Pass Filter
VOUT
Serial
Input
I/F
DATA1 (1,2)
DATA2 (3,4)
DATA3 (5,6)
DATA4 (7,8)
Output Amp and
Low-Pass Filter
VOUT3
4x/8x
Oversampling
Digital Filter
with
Function
Controller
VOUT4
Output Amp and
Low-Pass Filter
Enhanced
Multi-Level
Delta-Sigma
Modulator
VCOM
VOUT
5
Output Amp and
Low-Pass Filter
TEST
RST
ML
Output Amp and
Low-Pass Filter
VOUT6
Function
Control
I/F
MC
Output Amp and
Low-Pass Filter
VOUT
7
8
MDI
MDO
VOUT
Output Amp and
Low-Pass Filter
System Clock
System Clock
Manager
Power Supply
Zero Detect
SCKI
PIN CONFIGURATION
Top View
LQFP
36 35 34 33 32 31 30 29 28 27 26 25
RST
SCKI
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
V
CC3
AGND3
CC4
AGND4
OUT8
AGND6
CC5
AGND5
OUT7
VCOM
VOUT
OUT2
SCKO
BCK
V
LRCK
TEST
VDD
V
PCM1608
V
DGND
DATA1
DATA2
DATA3
ZEROA
V
1
V
1
2
3
4
5
6
7
8
9
10 11 12
PCM1608
SBAS164A
4
PIN ASSIGNMENTS
PIN
NAME
I/O
DESCRIPTION
1
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
I
Zero Data Flag for VOUT1. Can also be used as GPO pin.
Zero Data Flag for VOUT2. Can also be used as GPO pin.
Zero Data Flag for VOUT3. Can also be used as GPO pin.
Zero Data Flag for VOUT4. Can also be used as GPO pin.
Zero Data Flag for VOUT5. Can also be used as GPO pin.
Zero Data Flag for VOUT6. Can also be used as GPO pin.
No Connection
2
3
4
5
6
7
8
NC
No Connection
9
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
6
5
4
3
2
1
Voltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DATA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA1. Up to 192kHz.
Common Voltage Output. This pin should be bypassed with a 10µF capacitor to AGND.
Voltage Output for Audio Signal Corresponding to Lch on DATA4. Up to 192kHz.
Analog Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VCOM
VOUT7
AGND5
VCC
AGND6
VOUT
AGND4
VCC
AGND3
VCC
AGND2
VCC
AGND1
VCC
5
Analog Power Supply, +5V
Analog Ground
8
Voltage Output for Audio Signal Corresponding to Rch on DATA4. Up to 192kHz.
Analog Ground
4
Analog Power Supply, +5V
Analog Ground
3
Analog Power Supply, +5V
Analog Ground
2
Analog Power Supply, +5V
Analog Ground
1
Analog Power Supply, +5V
NC
ZERO7
DATA4
ZERO8
MDO
No Connection
Zero Data Flag for VOUT
Serial Audio Data Input for VOUT7 and VOUT8(2)
Zero Data Flag for VOUT
7
8
Serial Data Output for Serial Control Port(3)
Serial Data Input for Serial Control Port(1)
Shift Clock for Serial Control Port(1)
Latch Enable for Serial Control Port(1)
MDI
MC
I
ML
I
RST
I
System Reset, Active LOW(1)
SCKI
I
System Clock Input. Input frequency is 128, 192, 256, 384, 512, or 768fS.(2)
Buffered Clock Output. Output frequency is 128, 192, 256, 384, 512, or 768fS, or one-half of 128, 192, 256, 384, 512, or 768fS.
Shift Clock Input for Serial Audio Data. Clock must be 32, 48, or 64fS.(2)
Left and Right Clock Input. This clock is equal to the sampling rate, fS.(2)
Test Pin. This pin should be connected to DGND.(1)
Digital Power Supply, +3.3V
SCKO
BCK
O
I
LRCK
TEST
VDD
I
—
—
—
I
DGND
DATA1
DATA2
DATA3
ZEROA
Digital Ground
Serial Audio Data Input for VOUT1 and VOUT2(2)
Serial Audio Data Input for VOUT3 and VOUT4(2)
Serial Audio Data Input for VOUT5 and VOUT6(2)
Zero Data Flag. Logical “AND” of ZERO1 through ZERO6.
I
I
O
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.
PCM1608
SBAS164A
5
TYPICAL CHARACTERISTICS
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, fS = 44.1kHz)
FREQUENCY RESPONSE PASSBAND
FREQUENCY RESPONSE (Sharp Roll-Off)
(Sharp Roll-Off)
0
–20
0.05
0.04
0.03
0.02
0.01
0
–40
–60
–80
–0.01
–0.02
–0.03
–0.04
–0.05
–100
–120
–140
0
1
2
3
4
0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
FREQUENCY RESPONSE (Slow Roll-Off)
TRANSITION CHARACTERISTICS (Slow Roll-Off)
0
–20
5
4
3
–40
2
1
–60
0
–80
–1
–2
–3
–4
–5
–100
–120
–140
0
1
2
3
4
0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
De-Emphasis and De-Emphasis Error
DE-EMPHASIS (fS = 32kHz)
0.0
DE-EMPHASIS ERROR (fS = 32kHz)
0.5
0.4
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
–7.0
–8.0
–9.0
–10.0
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
Frequency (kHz)
Frequency (kHz)
PCM1608
SBAS164A
6
TYPICAL CHARACTERISTICS (Cont.)
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
De-Emphasis and De-Emphasis Error (Cont.)
DE-EMPHASIS (fS = 44.1kHz)
DE-EMPHASIS ERROR (fS = 44.1kHz)
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
–7.0
–8.0
–9.0
–10.0
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
18
18
0
2
4
6
8
10
12
14
16
20
0
2
4
6
8
10
12
14
16
20
Frequency (kHz)
Frequency (kHz)
DE-EMPHASIS (fS = 48kHz)
DE-EMPHASIS ERROR (fS = 48kHz)
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
–7.0
–8.0
–9.0
–10.0
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
18
0
2
4
6
8
10 12 14
20 22
18
0
2
4
6
8
10 12 14
20 22
16
16
Frequency (kHz)
Frequency (kHz)
ANALOG DYNAMIC PERFORMANCE
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, and 24-bit input data, unless otherwise noted. Conditions in 192kHz operation are: system clock = 128fS,
DAC3 through DAC6 = disable of Register 8, and oversampling rate = 64fS of Redister 12.
Supply-Voltage Characteristics
THD+N vs VCC (VDD = 3.3V)
DYNAMIC RANGE vs VCC (VDD = 3.3V)
10
1
110
108
106
104
102
100
98
–60dB/192kHz, 384fS
–60dB/96kHz, 384fS
44.1kHz, 384fS
–60dB/44.1kHz, 384fS
0.1
96kHz, 384fS
0dB/192kHz, 384fS
0dB/96kHz, 384fS
0.01
0.001
0.0001
192kHz, 384fS
0dB/44.1kHz, 384fS
96
4
4.5
5
5.5
6
4
4.5
5
5.5
6
VCC (V)
VCC (V)
PCM1608
SBAS164A
7
TYPICAL CHARACTERISTICS (Cont.)
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, and 24-bit input data, unless otherwise noted. Conditions in 192kHz operation are: system clock = 128fS,
DAC3 through DAC6 = disable of Register 8, and oversampling rate = 64fS of Redister 12.
Supply-Voltage Characteristics (Cont.)
SNR vs VCC (VDD = 3.3V)
CHANNEL SEPARATION vs VCC (VDD = 3.3V)
110
108
106
104
102
100
98
110
108
106
104
102
100
98
44.1kHz, 384fS
96kHz, 384fS
44.1kHz, 384fS
96kHz, 384fS
192kHz, 384fS
192kHz, 384fS
96
96
4
4.5
5
5.5
6
4
4.5
5
5.5
6
VCC (V)
V
CC (V)
Temperature Characteristics
THD+N vs TA
DYNAMIC RANGE vs TA
110
108
106
104
102
100
98
10
1
–60dB/192kHz, 384fS
–60dB/96kHz, 384fS
44.1kHz, 384fS
96kHz, 384fS
–60dB/44.1kHz, 384fS
0.1
0dB/192kHz, 384fS
0dB/96kHz, 384fS
0.01
0.001
0.0001
192kHz, 384fS
0dB/44.1kHz, 384fS
96
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
SNR vs TA
CHANNEL SEPARATION vs TA
110
108
106
104
102
100
98
110
108
106
104
102
100
98
44.1kHz, 384fS
96kHz, 384fS
44.1kHz, 384fS
96kHz, 384fS
192kHz, 384fS
192kHz, 384fS
96
96
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
PCM1608
SBAS164A
8
SYSTEM CLOCK OUTPUT
SYSTEM CLOCK AND RESET
FUNCTIONS
A buffered version of the system clock input is available at
the SCKO output (pin 39). SCKO can operate at either full
(fSCKI) or half (fSCKI/2) rate. The SCKO output frequency
may be programmed using the CLKE bit of Register 9. If the
SCKO output is not required, it is recommended to disable
it using the CLKE bit. The default is SCKO enabled.
SYSTEM CLOCK INPUT
The PCM1608 requires a system clock for operating the
digital interpolation filters and multilevel delta-sigma modu-
lators. The system clock is applied at the SCKI input (pin 38).
Table I shows examples of system clock frequencies for
common audio sampling rates.
POWER-ON AND EXTERNAL RESET FUNCTIONS
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. The PLL1700 multi-
clock generator from Texas Instruments is an excellent
choice for providing the PCM1608 system clock.
The PCM1608 includes a power-on reset function, as shown
in Figure 2. With the system clock active, and VDD > 2.0V
(typical, 1.6V to 2.4V), the power-on reset function will be
enabled. The initialization sequence requires 1024 system
clocks from the time VDD > 2.0V. After the initialization
period, the PCM1608 will be set to its reset default state, as
described in the Mode Control Register section of this data
sheet.
The 192kHz sampling frequency operation is available on
DATA1 for VOUT1 and VOUT2, and DATA4 for VOUT7 and
VOUT8. It is recommended that VOUT3, VOUT4, VOUT5, and
VOUT6 be disabled when operating with fS = 192kHz. This
is done by setting the DAC3, DAC4, DAC5, and DAC6 bits
of Register 9 to a “1” state.
The PCM1608 also includes an external reset capability
using the RST input (pin 37). This allows an external
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
SAMPLING
FREQUENCY
128fS
192fS
256fS
384fS
512fS
768fS
8kHz
16kHz
32kHz
44.1kHz
48kHz
96kHz
192kHz
—
—
—
—
—
—
—
—
—
—
2.0480
4.0960
8.1920
11.2896
12.2880
24.5760
(2)
3.0720
6.1440
12.2880
16.9344
18.4320
36.8640
(2)
4.0960
8.1920
16.3840
22.5792
24.5760
49.1520
(2)
6.1440
12.2880
24.5760
33.8688
36.8640
(1)
—
24.5760
—
36.8640
(2)
NOTES: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock is not supported for the given sampling frequency.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
tSCKH
2.0V
System Clock
0.8V
tSCKL
System Clock
Pulse Cycle Time(1)
System Clock Pulse Width HIGH tSCKH: 7ns (min)
System Clock Pulse Width LOW tSCKL: 7ns (min)
NOTE: (1) 1/128fS, 1/256fS, 1/384fS, 1/512fS, and 1/768fS.
FIGURE 1. System Clock Timing.
2.4V
VDD
2.0V
1.6V
0V
Reset
Reset Removal
Internal Reset
1024 System Clocks
Don’t Care
System Clock
FIGURE 2. Power-On Reset Timing.
PCM1608
SBAS164A
9
controller or master reset circuit to force the PCM1608 to
initialize to its reset default state. For normal operation,
RST should be set to a logic “1”.
Internal operation of the PCM1608 is synchronized with
LRCK. Accordingly, it is held when the sampling rate clock
of LRCK is changed, or SCKI and/or BCK is broken at least
for one clock cycle. If SCKI, BCK, and LRCK are provided
continuously after this hold condition, the internal operation
will be resynchronized automatically, less than 3/fS period. In
this resynchronize period, and following 3/fS, the analog
outputs are forced to the bipolar zone level (or VCC/2).
External resettling is not required.
The external reset operation and timing is shown in Figure 3.
The RST pin is set to logic “0” for a minimum of 20ns.
After the initialization sequence is completed, the PCM1608
will be set to its reset default state, as described in the
Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog
outputs are forced to the bipolar zero level (or VCC/2).
After the reset period, the internal registers are initialized
in the next 1/fS period and, if SCKI, BCK, and LRCK are
provided continuously, the PCM1608 provides proper ana-
log output with unit-group delay, as specified in this data
sheet.
AUDIO DATA FORMATS AND TIMING
The PCM1608 supports industry-standard audio data formats,
including Standard, I2S, and Left-Justified (see Figure 4).
Data formats are selected using the format bits, FMT[2:0], in
Register 9. The default data format is 24-bit Standard. All
formats require Binary Two’s Complement, MSB-first audio
data. See Figure 5 for a detailed timing diagram of the serial
audio interface.
The external reset is especially useful in applications
where there is a delay between PCM1608 power-up and
system clock activation. In this case, the RST pin should
be held at a logic “0” level until the system clock has been
activated.
DATA1, DATA2, DATA3, and DATA4 each carry two audio
channels, designated as the Left and Right channels. The Left
channel data always precedes the Right channel data in the
serial data stream for all data formats. Table II shows the
mapping of the digital input data to the analog output pins.
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1608 is comprised of
a 5-wire synchronous serial port. It includes LRCK (pin 41),
BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), DATA3
(pin 47), and DATA4 (pin 31). BCK is the serial audio bit
clock, and is used to clock the serial data present on
DATA1, DATA2, DATA3, and DATA4 into the audio
interface’s serial shift register. Serial data is clocked into
the PCM1608 on the rising edge of BCK. LRCK is the
serial audio left/right word clock. It is used to latch serial
data into the serial audio interface’s internal registers.
DATA INPUT
CHANNEL
ANALOG OUTPUT
DATA1
DATA1
DATA2
DATA2
DATA3
DATA3
DATA4
DATA4
Left
Right
Left
VOUT1(1)
VOUT2(1)
VOUT3(2)
VOUT4(2)
VOUT5(2)
VOUT6(2)
VOUT7(1)
VOUT8(1)
Right
Left
Right
Left
Right
Both LRCK and BCK must be synchronous to the system
clock. Ideally, it is recommended that LRCK and BCK be
derived from the system clock input, SCKI. LRCK is
operated at the sampling frequency (fS). BCK may be
operated at 32, 48, or 64 times the sampling frequency (I2S
format does not support BCK = 32fS).
NOTES: (1) Up to 192kHz. (2) Up to 96kHz, forced to bipolar zero when
fS = 96kHz.
TABLE II. Audio Input Data to Analog Output Mapping.
RST
Reset Removal
Reset
Internal Reset
1024 System Clocks
System Clock
FIGURE 3. External Reset Timing.
PCM1608
SBAS164A
10
SERIAL CONTROL INTERFACE
(pin 36). MDO is the serial data output, used to read back the
values of the mode registers; MDI is the serial data input,
used to program the mode registers; MC is the serial bit
clock, used to shift data in and out of the control port; and
ML is the control port latch clock.
The serial control interface is a 4-wire synchronous serial
port that operates asynchronously to the serial audio inter-
face. The serial control interface is utilized to program and
read the on-chip mode registers. The control interface in-
cludes MDO (pin 33), MDI (pin 34), MC (pin 35), and ML
(1) Standard Data Format: L-Channel = HIGH, R-Channel = LOW
1/fS
R-Channel
LRCK
L-Channel
BCK
(= 32fS, 48fS or 64fS)
16-Bit Right-Justified, BCK = 48fS or 64fS
DATA
14 15 16
1
2
3
14 15 16
1
2
3
14 15 16
MSB
LSB
MSB
LSB
16-Bit Right-Justified, BCK = 32fS
DATA
14 15 16
16 17 18
1
2
3
14 15 16
1
2
3
14 15 16
MSB
LSB MSB
LSB
17 18
LSB
18-Bit Right-Justified
DATA
1
2
3
16 17 18
1
2
MSB
LSB
MSB
20-Bit Right-Justified
DATA 18 19 20
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
MSB
MSB
24-Bit Right-Justified
DATA
22 23 24
1
2
3
22 23 24
1
2
3
22 23 24
LSB
MSB
LSB MSB
(2) I2S Data Format: L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 48fS or 64fS)
DATA
1
2
3
N-2 N-1
N
1
2
3
N-2 N-1
N
1
2
MSB
LSB
MSB
LSB
(3) Left-Justified Data Format: L-Channel = HIGH, R-Channel = LOW
1/fS
L-Channel
LRCK
R-Channel
BCK
(= 32fS, 48fS or 64fS)
DATA
1
2
3
N-2 N-1
N
1
2
3
N-2 N-1
N
1
2
MSB
LSB
MSB
LSB
FIGURE 4. Audio Data Input Formats.
PCM1608
SBAS164A
11
LRCK
BCK
50% of VDD
50% of VDD
tBCH
tBCL
tLB
tBCY
tBL
DATA1,DATA2,
DATA3, DATA4
50% of VDD
tDS
tDH
SYMBOL
PARAMETER
MIN
MAX
UNITS
(1)
tBCY
tBCH
tBCL
tBL
BCK Pulse Cycle Time
BCK High Level Time
BCK Low Level Time
32, 48, or 64fS
35
35
10
10
10
10
ns
ns
ns
ns
ns
ns
BCK Rising Edge to LRCK Edge
tLB
LRCK Falling Edge to BCK Rising Edge
DATA Set Up Time
tDS
tDH
DATA Hold Time
NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
FIGURE 5. Audio Interface Timing.
REGISTER WRITE OPERATION
MC, corresponding to the 16-bits of the control data word on
MDI. After the sixteenth clock cycle has completed, ML is
set to logic “1” to latch the data into the indexed mode
control register.
All Write operations for the serial control port use 16-bit
data words. Figure 6 shows the control data word format.
The most significant bit is the Read/Write (R/W) bit. When
set to “0”, this bit indicates a Write operation. There are
seven bits, labeled IDX[6:0], that set the register index (or
address) for the Write operation. The least significant eight
bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
SINGLE REGISTER READ OPERATION
Read operations utilize the 16-bit control word format shown
in Figure 6. For Read operations, the R/W bit is set to “1”.
Read operations ignore the index bits, IDX[6:0], of the
control data word. Instead, the REG[6:0] bits in Control
Register 11 are used to set the index of the register that is to
be read during the Read operation. Bits IDX[6:0] should be
set to 00H for Read operations.
Figure 7 shows the functional timing diagram for writing the
serial control port. ML is held at a logic “1” state until a
register needs to be written. To start the register write cycle,
ML is set to logic “0”. Sixteen clocks are then provided on
MSB
LSB
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
D5
D4
D3
D2
D1
D0
Register Index (or Address)
Register Data
Read/Write Operation
0 = Write Operation
1 = Read Operation (register index is ignored)
FIGURE 6. Control Data Word Format for MDI.
ML
MC
MDI
X
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5
D4 D3 D2 D1 D0
X
X
RW IDX6
FIGURE 7. Write Operation Timing.
PCM1608
SBAS164A
12
The details of the Read operation are shown in Figure 8. First,
Control Register 11 must be written with the index of the
register to be read back. Additionally, the INC bit must be set
to logic “0” in order to disable the Auto-Increment Read
function. The Read cycle is then initiated by setting ML to
logic “0” and setting the R/W bit of the control data word to
logic “1”, indicating a Read operation. MDO remains at a
high-impedance state until the last eight bits of the 16-bit read
cycle, which corresponds to the eight data bits of the register
indexed by the REG[6:0] bits of Control Register 11. The
Read cycle is completed when ML is set to “1”, immediately
after the MC clock cycle for the least significant bit of
indexed control register has completed.
AUTO-INCREMENT READ OPERATION
The Auto-Increment Read function allows for multiple regis-
ters to be read sequentially. The Auto-Increment Read func-
tion is enabled by setting the INC bit of Control Register 11
to “1”. The sequence always starts with Register 1, and ends
with the register indexed by the REG[6:0] bits in Control
Register 11.
Figure 8 shows the timing of the Auto-Increment Read
operation. The operation begins by writing Control Regis-
ter 11, setting INC to “1”, and setting REG[6:0] to the last
register to be read in the sequence. The actual Read opera-
tion starts on the next HIGH to LOW transition of the ML
pin.
INC = 1 (Auto-Increment Read)
ML
MC
MDI
1
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
MDO
High Impedance
D7 D6 D5 D4 D3 D2 D1 D0
INDEX “1”
ML
MC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MDI
MDO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
INDEX “N – 1” INDEX “N”
INC = 0 (Single Register Read)
High Impedance
ML
MC
1
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
MDI
MDO
High Impedance
D7 D6 D5 D4 D3 D2 D1 D0
INDEX “N”
NOTES: (1) X = Don’t care. (2) Index which it begins to read in the read mode can set by REG[6:0] in Register 11, data from Register 1 to Register 12 can
be read by setting it as “INC = 1” in Register 11. For example, set REG[6:0] = “0001001” to read from Register 9. (INC = “0” or “1”.)
FIGURE 8. Read Operation Timing.
PCM1608
SBAS164A
13
The Read cycle starts by setting the R/W bit of the control
word to “1”, and setting all of the IDX[6:0] bits to “0”.
All subsequent bits input on the MDI are ignored while ML
is set to “0”. For the first eight clocks of the Read cycle,
MDO is set to a high-impedance state. This is followed by
a sequence of 8-bit words, each corresponding the data
contained in Control Registers 1 through N, where N is
defined by the REG[6:0] bits in Control Register 11. The
Read cycle is completed when ML is set to “1”, immediately
after the MC clock cycle for the least significant bit of
Control Register N has completed.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 9 shows a detailed timing diagram for the Serial
Control interface. Pay special attention to the setup and hold
times, as well as tMLS and tMLH, which define minimum delays
between edges of the ML and MC clocks. These timing
parameters are critical for proper control port operation.
tMHH
50% of VDD
ML
tMCH
tMCL
tMLS
tMLH
50% of VDD
MC
tMCY
LSB
MDI
50% of VDD
tMDS
tMCH
tMOS
LSB
50% of VDD
MDO
SYMBOL
PARAMETER
MIN
MAX
UNITS
tMCY
tMCL
tMCH
tMHH
tMLS
tMLH
tMDH
tMDS
tMOS
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
ML High Level Time
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
300
20
ML Falling Edge to MC Rising Edge
ML Hold Time(1)
20
MDI Hold Time
15
MDL Set Up Time
20
MC Falling Edge to MDSO Stable
30
NOTE: (1) MC rising edge for LSB to ML rising edge.
FIGURE 9. Control Interface Timing.
PCM1608
SBAS164A
14
MODE CONTROL REGISTERS
Register Map
User-Programmable Mode Controls
The mode control register map is shown in Table IV. Each
register includes a R/W bit that determines whether a regis-
ter read (R/W = 1) or write (R/W = 0) operation is per-
formed. Each register also includes an index (or address)
indicated by the IDX[6:0] bits.
The PCM1608 includes a number of user-programmable
functions that are accessed via control registers. The regis-
ters are programmed using the Serial Control Interface that
was previously discussed in this data sheet. Table III lists the
available mode control functions, along with their reset
default conditions and associated register index.
FUNCTION
RESET DEFAULT
CONTROL REGISTER
INDEX, IDX[6:0]
Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps
0dB, No Attenuation
1 through 6, 16, 17
AT1[7:0], AT2[7:0]
AT3[7:0], AT4[7:0]
AT5[7:0], AT6[7:0]
AT7[7:0], AT8[7:0]
MUT[8:1]
DAC[8:1]
FMT[2:0]
FLT
Soft Mute Control
DAC 1-8 Operation Control
Audio Data Format Control
Digital Filter Roll-Off Control
SCKO Frequency Selection
Mute Disabled
DAC 1-6 Enabled
24-Bit Standard Format
Sharp Roll-Off
7, 18
8, 19
9
9
9
Full Rate (= fSCKI
)
CLKD
SCKO Output Enable
SCKO Enabled
9
CLKE
De-Emphasis All Channel Function Control
De-Emphasis All Channel Sample Rate Selection
Output Phase Select
De-Emphasis All Channel Disabled
44.1kHz
10
10
10
10
11
11
12
12
12
DMC
DMF[1:0]
DREV
ZREV
REG[6:0]
INC
GPOE
GPO[6:1]
OVER
Normal Phase
High
REG[6:0] = 01H
Auto-Increment Disabled
Zero Flag Enabled
Disabled
Zero Flag Polarity Select
Read Register Index Control
Read Auto-Increment Control
General-Purpose Output Enable
General-Purpose Output Bits (GPO1-GPO6)
Oversampling Rate Control
64x
TABLE III. User-Programmable Mode Controls.
IDX
(B8-B14) REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
Register0
Register1
Register2
Register3
Register4
Register5
Register6
Register7
Register8
Register9
Register10
Register11
Register12
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX1 IDX0 N/A(1) N/A(1) N/A(1) N/A(1) N/A(1) N/A(1) N/A(1) N/A(1)
IDX1 IDX0
IDX1 IDX0
IDX1 IDX0
IDX1 IDX0
IDX1 IDX0
IDX1 IDX0
AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30
AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40
AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50
AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60
IDX1 IDX0 RSV(2) RSV(2) MUT6 MUT5 MUT4 MUT3 MUT2 MUT1
IDX1 IDX0 RSV(2) RSV(2) DAC6 DAC5 DAC4 DAC3 DAC2 DAC1
IDX1 IDX0 RSV(2) RSV(2) FLT
IDX1 IDX0 RSV(2) ZREV DREV DMF1 DMF0 DMC
IDX1 IDX0 INC REG6 REG5 REG4 REG3 REG2 REG1 REG0
IDX1 IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1
CLKD CLKE FMT2 FMT1 FMT0
DMC DMC
10H
11H
12H
13H
Register 16
Register 17
Register 18
Register 19
R/W IDX6
R/W IDX6
R/W IDX6
R/W IDX6
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX5 IDX4
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX3 IDX2
IDX1 IDX0
IDX1 IDX0
AT77 AT76 AT75 AT74 AT73 AT72 AT71 AT70
AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80
IDX1 IDX0 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) MUT8 MUT7
IDX1 IDX0 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) DAC8 DAC7
NOTES: (1) N/A = not assigned. No operation even if setting any data. (2) RSV = reserved for test operation. It should be set “0” during regular operation.
TABLE IV. Mode Control Register Map.
PCM1608
SBAS164A
15
REGISTER DEFINITIONS
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17 AT16
AT27 AT26
AT37 AT36
AT47 AT46
AT57 AT56
AT67 AT66
AT77 AT76
AT87 AT86
AT15
AT14
AT13
AT12 AT11 AT10
AT22 AT21 AT20
AT32 AT31 AT30
AT42 AT41 AT40
AT52 AT51 AT50
AT62 AT61 AT60
AT72 AT71 AT70
AT82 AT81 AT80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
AT25
AT35
AT45
AT55
AT65
AT75
AT85
AT24
AT34
AT44
AT54
AT64
AT74
AT84
AT23
AT33
AT43
AT53
AT63
AT73
AT83
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
ATx[7:0]
Digital Attenuation Level Setting
where x = 1 through 8, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 1111 1111B
Each DAC output, VOUT1 through VOUT8, has a digital attenuator associated with it. The attenuator may be
set from 0dB to –63dB, in 0.5dB steps. Changes in attenuator levels are made by incrementing or
decrementing, by one step (0.5dB), for every 8/fS time interval until the programmed attenuator setting is
reached. Alternatively, the attenuator may be set to infinite attenuation (or mute).
The attenuation level may be set using the formula below.
Attenuation Level (dB) = 0.5 (ATx[7:0]DEC – 255)
where: ATx[7:0]DEC = 0 through 255
for: ATx[7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings.
ATx[7:0]
Decimal Value
Attenuator Level Setting
1111 1111B
1111 1110B
1111 1101B
255
254
253
•
0dB, No Attenuation (default)
–0.5dB
–1.0dB
•
•
•
•
•
•
•
•
1000 0010B
1000 0001B
1000 0000B
130
129
128
•
–62.5dB
–63.0dB
Mute
•
•
•
•
•
•
•
•
0000 0000B
0
Mute
PCM1608
SBAS164A
16
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 7
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
MUT6 MUT5 MUT4 MUT3 MUT2 MUT1
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
MUTx
Soft Mute Control
Where x = 1 through 6, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 0
MUTx = 0
MUTx = 1
Mute Disabled (default)
Mute Enabled
The mute bits, MUT1 through MUT6, are used to enable or disable the Soft Mute function for the
corresponding DAC outputs, VOUT1 through VOUT6. The Soft Mute function is incorporated into the digital
attenuators. When Mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When Mute
is enabled by setting MUTx = 1, the digital attenuator for the corresponding output will be decreased from
the current setting to the infinite attenuation setting one attenuator step (0.5dB) at a time. This provides a
quiet, pop-free muting of the DAC output. Upon returning from Soft Mute, by setting
MUTx = 0, the attenuator will be increased one step at a time to the previously programmed attenuator
level.
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 8
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
DAC6 DAC5 DAC4 DAC3 DAC2 DAC1
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
DACx
DAC Operation Control
where x = 1 through 6, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 0
DACx = 0
DACx = 1
DAC Operation Enabled (default)
DAC Operation Disabled
The DAC operation controls are used to enable and disable the DAC outputs, VOUT1 through VOUT6. When
DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier
input is switched to the DC common-mode voltage (VCOM), equal to VCC/2
.
PCM1608
SBAS164A
17
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 9
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
FLT
CLKD CLKE FMT2 FMT1 FMT0
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
FLT
Digital Filter Roll-Off Control
These bits are Read/Write.
Default Value: 0
FLT = 0
FLT = 1
Sharp Roll-Off (default)
Slow Roll-Off
The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Two
filter roll-off sections are available: Sharp or Slow. The filter responses for these selections are shown in
the Typical Performance Curves section of this data sheet.
CLKD
SCKO Frequency Selection
This bit is Read/Write.
Default Value: 0
CLKD = 0
CLKD = 1
Full Rate, fSCKO = fSCKI (default)
Half Rate, fSCKO = fSCKL/2
The CLKD bit is used to determine the clock frequency at the system clock output pin, SCKO.
CLKE
SCKO Output Enable
This bit is Read/Write.
Default Value: 0
CLKE = 0
CLKE = 1
SCKO Enabled (default)
SCKO Disabled
The CLKE bit is used to enable or disable the system clock output pin, SCKO. When SCKO is enabled, it will
output either a full or half rate clock, based upon the setting of the CLKD bit. When SCKO is disabled, it is set
to a LOW level.
FMT[2:0] Audio Interface Data Format
These bits are Read/Write.
Default Value: 000B
FMT[2:0]
Audio Data Format Selection
000
001
010
011
100
101
110
111
24-Bit Standard Format, Right-Justified Data (default)
20-Bit Standard Format, Right-Justified Data
18-Bit Standard Format, Right-Justified Data
16-Bit Standard Format, Right-Justified Data
I2S Format, 16- to 24-bits
Left-Justified Format, 16- to 24-Bits
Reserved
Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
PCM1608
SBAS164A
18
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 10
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV ZREV DREV DMF1 DMF0 DMC
DMC DMC
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
DMF[1:0]
Sampling Frequency Selection for the De-Emphasis Function
These bits are Read/Write.
Default Value: 00B
DMF[1:0]
De-Emphasis Same Rate Selection
00
01
10
11
44.1kHz (default)
48kHz
32kHz
Reserved
The DMF[1:0] bits are used to select the sampling frequency used for the Digital De-Emphasis function when
it is enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet.
The table below shows the available sampling frequencies.
DMC
Digital De-Emphasis, All Channels Function Control
This bit is Read/Write.
Default Value: 0
DMC = 0
DMC = 1
De-Emphasis Disabled for All Channels (default)
De-Emphasis Enabled for All Channels 1 and 2
The DMC bit is used to enable or disable the De-Emphasis function for all channels. To select more than one
of three DMC bits, enable or disable the De-Emphasis function.
DREV
Output Phase Select
Default Value: 0
DREV = 0
DREV = 1
Normal Output (default)
Inverted Output
The DREV bit is the output analog signal phase control.
ZREV
Zero Flag Polarity Select
Default Value: 0
ZREV = 0
ZREV = 1
Zero Flag Pins HIGH at a Zero Detect (default)
Zero Flag Pins LOW at a Zero Detect
The ZREV bit allows the user to select the polarity of the Zero Flag pins.
PCM1608
SBAS164A
19
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 11
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
INC
REG6 REG5 REG4 REG3 REG2 REG1 REG0
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
INC
Auto-Increment Read Control
This bit is Read/Write.
Default Value: 0
INC = 0
INC = 1
Auto-Increment Read Disabled (default)
Auto-Increment Read Enabled
The INC bit is used to enable or disable the Auto-Increment Read feature of the Serial Control Interface. Refer
to the Serial Control Interface section of this data sheet for details regarding Auto-Increment Read operation.
REG[6:0]
Read Register Index
These bits are Read/Write.
Default Value: 01H
The REG[6:0] bits are used to set the index of the register to be read when performing the Single Register Read
operation. In the case of an Auto-Increment Read operation, the REG[6:0] bits indicate the index of the last
register to be read in the Auto-Increment Read sequence. For example, if Registers 1 through 6 are to be read
during an Auto-Increment Read operation, the REG[6:0] bits would be set to 06H. Refer to the Serial Control
Interface section of this data sheet for details regarding the Single Register and Auto-Increment Read operations.
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 12
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1
GPOx
General-Purpose Logic Output
Where: x = 1 through 6, corresponding pins GPO1 through GPO6.
These bits are Read/Write.
Default Value: 0
GPOx = 0
GPOx = 1
Set GPOx to “0”
Set GPOx to “1”
The general-purpose output pins, GPO1 through GPO6, are enabled by setting GPOE = 1. These pins are used
as general-purpose outputs for controlling user-defined logic functions. When general-purpose outputs are
disabled (GPOE = 0), they default to the zero-flag function, ZERO1 through ZERO6.
GPOE
General-Purpose Output Enable
This bit is Read/Write.
Default Value: 0
GPOE = 0
GPOE = 1
General-Purpose Outputs Disabled
Pins default to zero-flag function (ZERO1 through ZERO6).
General-Purpose Outputs Enabled
Data written to GPO1 through GPO6 will appear at the corresponding pins.
PCM1608
SBAS164A
20
Register 12 (Cont.)
OVER
Oversampling Rate Control
This bit is Read/Write.
Default Value: 0
System Clock Rate = 256, 384, 512, or 768fS:
OVER = 0
OVER = 1
64x Oversampling (default)
128x Oversampling
System Clock Rate = 128 or 192fS:
OVER = 0
OVER = 1
32x Oversampling (default)
64x Oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma DACs. The OVER = 1 setting is
reccomended when the oversampling rate is 192kHz (system clock rate is 128 or 192fS).
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 18
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
RSV
RSV
RSV
RSV MUT8 MUT7
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
MUTx
Soft Mute Control
Where x = 7-8, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 0
MUTx = 0
MUTx = 1
Mute Disabled (default)
Mute Enabled
The mute bits, MUT7 through MUT8, are used to enable or disable the Soft Mute function for the
corresponding DAC outputs, VOUT7 and VOUT8. The Soft Mute function is incorporated into the digital
attenuators. When Mute is disabled (MUTx = 0), the attenuator and the DAC operate normally. When Mute
is enabled by setting MUTx = 1, the digital attenuator for the corresponding output will be decremented
from the current setting to the infinite attenuation setting one attenuator step (0.5dB) at a time. This
provides a quiet, “pop”-free muting of the DAC output. Upon returning from Soft Mute, by setting
MUTx = 0, the attenuator will be incremented one step at a time to the previously programmed attenuator
level.
PCM1608
SBAS164A
21
B15
R/W
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 19
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
RSV
RSV
RSV
RSV DAC8 DAC7
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
DACx
DAC Operation Control
Where x = 7-8, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 0
DACx = 0
DACx = 1
DAC Operation Disabled (default)
DAC Operation Enabled
The DAC operation controls are used to enable and disable the DAC outputs, VOUT7 and VOUT8. When
DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier
input is switched to the DC common-mode voltage (VCOM), equal to VCC/2.
filter is not enough to attenuate the out-of-band noise to an
ANALOG OUTPUTS
acceptable level for most applications. An external low-pass
filter is required to provide sufficient out-of-band noise
rejection. Further discussion of DAC post-filter circuits is
provided in the Applications Information section of this data
sheet.
The PCM1608 includes eight independent output channels,
VOUT1 through VOUT8. These are unbalanced outputs, each
capable of driving 3.1Vp-p typical into a 5kΩ AC load with
VCC = +5V. The internal output amplifiers for VOUT1 through
VOUT8 are DC biased to the common-mode (or bipolar zero)
voltage, equal to VCC/2.
VCOM OUTPUT
The output amplifiers include an RC continuous-time filter,
which helps to reduce the out-of-band noise energy present
at the DAC outputs due to the noise-shaping characteristics
of the PCM1608’s delta-sigma DACs. The frequency re-
sponse of this filter is shown in Figure 10. By itself, this
One unbuffered, common-mode voltage output pin, VCOM
(pin 15), is brought out for decoupling purposes. This pin is
nominally biased to a DC voltage level equal to VCC/2. If
this pin is to be used to bias external circuitry, a voltage
follower is required for buffering purposes. Figure 11 shows
an example of using the VCOM pin for external biasing
applications.
20
0
–20
–40
–60
–80
–100
PCM1608
4
VCC
2
1
VBIAS
≈
OPA337
3
15
VCOM
+
10µF
1
10
100
1k
10k
100k
1M
10M
FIGURE 11. Biasing External Circuits Using the VCOM Pin.
Log Frequency (Hz)
FIGURE 10. Output Filter Frequency Response.
PCM1608
SBAS164A
22
ZERO FLAG
can be used to operate external mute circuits. ZERO1 through
ZERO6 can be used as status indicators for a microcontroller,
audio signal processor, or other digitally controlled functions.
Zero Detect Condition
Zero Detection for each output channel is independent from
the others. If the data for a given channel remains at a “0”
level for 1024 sample periods (or LRCK clock periods), a
Zero Detect condition exists for that channel.
The active polarity of zero flag output can be inverted by
setting the ZREV bit of Control Register 10 to “1”. The reset
default is active high output, or ZREV = 0.
Zero Output Flags
Given that a Zero Detect condition exists for one or more
channels, the Zero Flag pins for those channels will be set to
a logic “1” state. There are Zero Flag pins for each channel,
ZERO1 through ZERO6 (pins 1 through 6), ZERO7 (pin 30),
and ZERO8 (pin 32). In addition, all eight Zero Flags are
logically “AND”ed together, and the result provided at the
ZEROA pin (pin 48), which is set to a logic “1” state when all
channels indicate a Zero Detect condition. The Zero Flag pins
APPLICATIONS INFORMATION
CONNECTION DIAGRAMS
A basic connection diagram with the necessary power-
supply bypassing and decoupling components is shown in
Figure 12. Texas Instruments recommends using the compo-
nent values shown in Figure 12 for all designs.
ML
MC
MD
PLL1700
Micro Controller
SCKO3
ZERO7, 8
DATA4
+5V
Power Supply
10µF
Regulator
36 35 34 33 32 31 30 29 28 27 26 25
VCC3
37
38
39
40
41
42
24
RST
RST
23
AGND3
SCKI
SCKO
BCK
V
CC4 22
AGND4
21
20
19
18
17
16
15
14
13
BCK
LPF
LPF
LRCK
V
OUT8
AGND6
CC5
AGND5
OUT7
VCOM
VOUT
VOUT
8
LRCK
TEST
PCM1608
43 VDD
V
10µF
44 DGND
V
DATA1
DATA1
DATA2
45
46
47
48
VOUT7
10µF
DATA2
DATA3
1
LPF
LPF
VOUT1
DATA3
ZEROA
V
OUT2
V
OUT2
ZEROA
1
2
3
4
5
6
7
8
9
10 11 12
LPF
VOUT
VOUT
VOUT
3
4
5
LPF
LPF
LPF
V
OUT6
ZERO1–6
FIGURE 12. Basic Connection Diagram.
PCM1608
SBAS164A
23
A typical application diagram is shown in Figure 13. The
REG1117-3.3 from Texas Instruments is used to generate
+3.3V for VDD from the +5V analog power supply. The
PLL1700E from Texas Instruments is used to generate the
system clock input at SCKI, as well as generating the clock
for the audio signal processor.
Series resistors (22Ω to 100Ω) are recommended for SCKI,
LRCK, BCK, DATA1, DATA2, DATA3, and DATA4.
The series resistor combines with the stray PCB and device
input capacitance to form a low-pass filter which removes
high-frequency noise from the digital signal, thus reducing
high-frequency emission.
O U T
A G N D 2
3
4
5
6
V
C C
O U T
2
1
V
V
O U T
A G N D 1
V
C C
O U T
V
V
N C
N C
Z e r o - F l a g
Z e r o - F l a g
Z E R O 7
D A T A 4
Z E R O 8
N C
Z E R O 6 / G P O 6
Z E R O 5 / G P O 5
Z E R O 4 / G P O 4
Z E R O 3 / G P O 3
Z E R O 2 / G P O 2
Z E R O 1 / G P O 1
M D O
M D I
M C
M L
FIGURE 13. Typical Application Diagram.
24
PCM1608
SBAS164A
POWER SUPPLIES AND GROUNDING
Multiple FeedBack (MFB) circuit arrangement, which re-
duces sensitivity to passive component variations over fre-
quency and temperature. For more information regarding
MFB active filter design, please refer to the Texas Instru-
ments Applications Bulletin AB-034, available from our
web site (www.ti.com), or your local Texas Instruments
sales office.
The PCM1608 requires a +5V analog supply and a +3.3V
digital supply. The +5V supply is used to power the DAC
analog and output filter circuitry, while the +3.3V supply is
used to power the digital filter and serial interface circuitry.
For best performance, the +3.3V supply should be derived
from the +5V supply using a linear regulator (see Figure 13).
Since the overall system performance is defined by the quality
of the DACs and their associated analog output circuitry,
high-quality audio op amps are recommended for the active
filters. The OPA2134 and OPA2353 dual op amps from
Texas Instruments are shown in Figures 14 and 15, and are
recommended for use with the PCM1608.
Two capacitors are required for supply bypassing (see Fig-
ure 12). These capacitors should be located as close as
possible to the PCM1608 package. The 10µF capacitors
should be tantalum or aluminum electrolytic, while the
0.1µF capacitors are ceramic (X7R type is recommended
for surface-mount applications).
DAC OUTPUT FILTER CIRCUITS
Delta-sigma DACs utilize noise-shaping techniques to im-
prove in-band Signal-to-Noise Ratio (SNR) performance at
the expense of generating increased out-of-band noise above
the Nyquist Frequency, or fS/2. The out-of-band noise must
be low-pass filtered in order to provide the optimal converter
performance. This is accomplished by a combination of on-
chip and external low-pass filtering.
R2
C1
2
R1
R3
VIN
R4
1
VOUT
OPA2134
3
C2
R2
R1
A
V ≈ –
Figures 14 and 15 show the recommended external low-pass
active filter circuits for dual- and single-supply applications.
These circuits are second-order Butterworth filters using the
FIGURE 14. Dual Supply Filter Circuit.
R2
AV ≈ –
R1
R2
C1
R1
R3
2
VIN
R4
1
VOUT
OPA2134
C2
3
PCM1608
VCOM
To Additional
Low-Pass Filter
Circuits
OPA337
C2
10µF
+
FIGURE 15. Single-Supply Filter Circuit.
PCM1608
SBAS164A
25
Separate power supplies are recommended for the digital and
analog sections of the board. This prevents the switching noise
present on the digital supply from contaminating the analog
power supply and degrading the dynamic performance of the
DACs. In cases where a common +5V supply must be used for
the analog and digital sections, an inductance (RF choke, ferrite
bead) should be placed between the analog and digital +5V
supply connections to avoid coupling of the digital switching
noise into the analog circuitry. Figure 17 shows the recom-
mended approach for single-supply applications.
PCB LAYOUT GUIDELINES
A typical PCB floor plan for the PCM1608 is shown in
Figure 16. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a
split or cut in the circuit board. The PCM1608 should be
oriented with the digital I/O pins facing the ground plane
split/cut to allow for short, direct connections to the digital
audio interface and control signals originating from the
digital section of the board.
Digital Power
Analog Power
+VD
DGND
AGND +5VA
+VS –VS
REG
VCC
VDD
DGND
Digital Logic
and
Audio
Processor
Output
Circuits
PCM1608
Digital
Ground
AGND
Analog
Ground
DIGITAL SECTION
ANALOG SECTION
Return Path for Digital Signals
FIGURE 16. Recommended PCB Layout.
Power Supplies
RF Choke or Ferrite Bead
+5V
GND +VS –VS
REG
VCC
VDD
VDD
DGND
Digital Logic
and
Output
Circuits
Audio
Processor
PCM1608
AGND
Common
Ground
DIGITAL SECTION
ANALOG SECTION
FIGURE 17. Single-Supply PCB Layout.
26
PCM1608
SBAS164A
Figure 18 illustrates the simulated jitter sensitivity of the
PCM1608. To achieve best performance, the system clock
jitter should be less than 300 picoseconds. This is easily
achieved using a quality clock generation IC, like the PLL1700
from Texas Instruments.
THEORY OF OPERATION
The DAC section of the PCM1608 is based on a multi-bit
delta-sigma architecture. This architecture utilizes a fourth-
order noise-shaper and an 8-level amplitude quantizer, fol-
lowed by an analog low-pass filter. A block diagram of the
delta-sigma modulator is shown in Figure 19. This architec-
ture has the advantage of stability and improved jitter toler-
ance, when compared to traditional 1-bit (2-level) delta-
sigma designs.
JITTER DEPENDENCE (x 64 Over Sampling)
125
120
115
110
105
100
95
The combined oversampling rate of the digital interpolation
filter and the delta-sigma modulator is 32, 64, or 128fS. The
total oversampling rate is determined by the desired sam-
pling frequency. If fS ≤ 96kHz, then the OVER bit in
Register 12 may be set to an oversampling rate of 64 or
128fS. If fS > 96kHz, then the OVER bit may be used to set
the oversampling rate to 32 or 64fS. Figure 20 shows the
out-of-band quantization noise plots for both the 64x and
128x oversampling scenarios. Notice that the 128x
oversampling plot shows significantly improved out-of-band
noise performance, allowing for a simplified low-pass filter
to be used at the output of the DAC.
90
0
100
200
300
400
500
600
Jitter (ps)
FIGURE 18. Jitter Sensitivity.
–
+
Z–1
Z–1
Z–1
Z–1
8fS
+
+
+
+
+
8-Level Quantizer
64fS
FIGURE 19. Eight-Level Delta-Sigma Modulator.
QUANTIZATION NOISE SPECTRUM
(64x Oversampling)
0
QUANTIZATION NOISE SPECTRUM
(128x Oversampling)
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Frequency (fS)
Frequency (fS)
FIGURE 20. Quantization Noise Spectrum.
PCM1608
SBAS164A
27
For the PCM1608 DACs, THD+N is measured with a full-
scale, 1kHz digital sine wave as the test stimulus at the input
of the DAC. The digital generator is set to a 24-bit audio
word length and a sampling frequency of 44.1kHz, or 96kHz.
The digital generator output is taken from the unbalanced
S/PDIF connector of the measurement system. The
S/PDIF data is transmitted via coaxial cable to the digital
audio receiver on the DEM-DAI1602 demo board. The
receiver is then configured to output 24-bit data in either I2S
or left-justified data format. The DAC audio interface format
is programmed to match the receiver output format. The
analog output is then taken from the DAC post filter and
connected to the analog analyzer input of the measurement
system. The analog input is band-limited, using filters resi-
dent in the analyzer. The resulting THD+N is measured by
the analyzer and displayed by the measurement system.
KEY PERFORMANCE PARAMETERS
AND MEASUREMENT
This section provides information on how to measure key
dynamic performance parameters for the PCM1608. In all
cases, an Audio Precision System Two Cascade or equiva-
lent audio measurement system is utilized to perform the
testing.
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion + Noise (THD+N) is a significant
figure of merit for audio DACs, since it takes into account
both harmonic distortion and all noise sources within a
specified measurement bandwidth. The true rms value of the
distortion and noise is referred to as THD+N. The test setup
for THD+N testing is shown in Figure 21.
Evaluation Board
DEM-DAI1608
2nd-Order
Low-Pass
Filter
S/PDIF
Receiver
PCM1608
f–3dB = 54kHz
Analyzer
Digital
and
Display
Generator
S/PDIF
Band Limit
Notch Filter
fC = 1kHz
Output
100% Full-Scale
24-Bit, 1kHz
Sine Wave
rms Mode
HPF = 22Hz(1)
LPF = 30kHz(1)
Option = 20kHz Apogee Filter(2)
NOTES: (1) There is little difference in measured THD+N when using the
various settings for these filters. (2) Required for THD+N test.
FIGURE 21. Test Setup for THD+N Measurements.
PCM1608
SBAS164A
28
DYNAMIC RANGE
IDLE CHANNEL SIGNAL-TO-NOISE RATIO
Dynamic range is specified as A-Weighted, THD+N mea-
sured with a –60dBFS, 1kHz digital sine wave stimulus at
the input of the DAC. This measurement is designed to give
a good indication of how the DAC will perform, given a
low-level input signal.
The SNR test provides a measure of the noise of the DAC.
The input to the DAC is in all “0”s data, and the DAC’s
Infinite Zero Detect Mute function must be disabled (de-
fault condition at power-up for the PCM1608). This en-
sures that the delta-sigma modulator output is connected to
the output amplifier circuit so that idle tones (if present)
may be observed at the output. The dither function of the
digital signal generator must also be disabled to ensure an
all “0”s data stream at the input of the DAC.
The measurement setup for the dynamic range measurement
is shown in Figure 22, and is similar to the THD+N test
setup discussed previously. The differences include the
band-limit filter selection, the additional A-Weighting filter,
and the –60dBFS input level.
The measurement setup for SNR is identical to that used for
dynamic range, with the exception of the input signal level.
(see the notes provided in Figure 22.)
Evaluation Board
DEM-DAI1608
2nd-Order
Low-Pass
Filter
S/PDIF
Receiver
PCM1608(1)
f
–3dB = 54kHz
Analyzer
and
Display
Digital
Generator
A-Weight
Filter(1)
S/PDIF
Output
Band Limit
Notch Filter
fC = 1kHz
0% Full-Scale,
Dither Off (SNR)
–60dBFS,
rms Mode
HPF = 22Hz
LPF = 22kHz
Option = A-Weighting(2)
1kHz Sine Wave
(Dynamic Range)
NOTES: (1) Infinite Zero Detect Mute disabled.
(2) Results without A-Weighting will be approxi-
mately 3dB worse.
FIGURE 22. Test Set-Up for Dynamic Range and SNR Meeasurements.
PCM1608
SBAS164A
29
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
PCM1608KY
PCM1608KY/2K
PCM1608Y
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
PT
PT
PT
PT
48
48
48
48
250
2000
250
PCM1608Y/2K
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
相关型号：
PCM1608Y
24-Bit, 192kHz Sampling, 8-Channel, Enhanced Multilevel, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
TI
PCM1608Y/2K
24-Bit, 192kHz Sampling, 8-Channel, Enhanced Multilevel, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
TI
PCM1609A
24-BIT, 192-kHz SAMPLING, 8-CHANNEL, ENHANCED MULTILEVEL, DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
TI
PCM1609APT
24-BIT, 192-kHz SAMPLING, 8-CHANNEL, ENHANCED MULTILEVEL, DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
TI
PCM1609APTG4
24-BIT, 192-kHz SAMPLING, 8-CHANNEL, ENHANCED MULTILEVEL, DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
TI
PCM1609APTR
24-BIT, 192-kHz SAMPLING, 8-CHANNEL, ENHANCED MULTILEVEL, DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
TI
PCM1609APTRG4
24-BIT, 192-kHz SAMPLING, 8-CHANNEL, ENHANCED MULTILEVEL, DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
TI
PCM1680
24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma, Audio Digital-to-Analog Converter
TI
©2020 ICPDF网 联系我们和版权申明