PCM1754 [TI]
106dB SNR 立体声音频数模转换器 (DAC)（硬件控制）;
| 型号： | PCM1754 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 106dB SNR 立体声音频数模转换器 (DAC)（硬件控制） 转换器 数模转换器 |
| 文件： | 总41页 (文件大小：2025K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
PCM175x 24 位、192kHz 采样、增强型多级、Δ-Σ、音频
数模转换器
1 特性
2 应用
1
•
•
24 位分辨率
模拟性能 (VCC = 5V)
•
•
•
•
A/V 接收器
HDTV 接收器
车载音频系统
–
–
–
–
动态范围：106dB
需要 24 位音频的应用
SNR：106dB（典型值）
THD+N：0.002%（典型值）
满量程输出：4VPP（典型值）
3 说明
PCM1753、PCM1754 和 PCM1755 (PCM175x) 器件
是基于 TI 增强型 Δ-Σ 架构的立体声数模转换器
•
4× 或 8× 过采样数字滤波器
–
–
阻带衰减：–50dB
(DAC)。这一增强型架构使用四阶噪声整形和 8 阶振幅
量化，可实现出色的动态性能并提升时钟抖动耐受度。
得益于具有符合行业标准的音频数据格式以及 16 位和
24 位数据的器件支持，PCM175x 器件可轻松与音频
DSP 和解码器芯片连接。可在硬件模式下或通过全套
用户可编程的功能（可通过支持寄存器写入功能的三线
串行控制接口访问）控制 PCM175x 器件。
通带纹波：±0.04dB
•
•
采样频率：5kHz 至 200kHz
系统时钟：128 fS、192 fS、256 fS、384 fS、512
fS、768 fS、1152 fS，且具有自动检测功能
•
硬件控制 (PCM1754)
–
–
–
–
I2S 和 16 位字，右平衡
44.1kHz 数字去加重功能
软静音
PCM1753 与 PCM1748、PCM1742 和 PCM1741 引
脚兼容，引脚 5 除外。
适用于 L/R 通道共模输出的零标志
•
•
电源：5V 单电源
器件信息(1)
小型 16 引线 SSOP 封装，无铅
器件型号
PCM1753
封装
封装尺寸（标称值）
PCM1754
PCM1755
SSOP (16)
3.90mm x 4.90mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
功能方框图
BCK
Audio
LRCK
Serial
V
L
OUT
Output Amp
And
Low-Pass Filter
DAC
DATA
Port
4x/8x
Enhanced
Multilevel
Delta-Sigma
Modulator
Oversampling
Digital Filter
and Function
Control
FMT
V
V
COM
Serial
Control
Port
MUTE
Output Amp
And
Low-Pass Filter
DAC
DEMP
TEST
R
OUT
System C lock
SCK
System
Clock Manager
Zero Detect
Power Supply
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLES092
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 18
8.6 Register Maps......................................................... 19
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions...................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 System Clock Input Timing ....................................... 6
7.7 Audio Interface Timing.............................................. 6
7.8 Control Interface Timing Requirements .................... 7
7.9 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
9
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 31
12.1 相关文档ꢀ ........................................................... 31
12.2 相关链接................................................................ 31
12.3 接收文档更新通知 ................................................. 31
12.4 社区资源................................................................ 31
12.5 商标....................................................................... 31
12.6 静电放电警告......................................................... 31
12.7 Glossary................................................................ 31
13 机械、封装和可订购信息....................................... 31
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (August 2015) to Revision E
Page
•
•
•
•
Added text to pin 11 description to clarify operation for PCM1755 ........................................................................................ 3
Added text to pin 12 description to clarify operation for PCM1755 ....................................................................................... 3
Added new row for PCM1755 temperature range to Absolute Maximum Ratings table ....................................................... 4
Changed location of operating temperature from Electrical Characteristics table to Recommended Operating
Conditions table...................................................................................................................................................................... 4
•
Changed operating temperature MAX value for PCM1753 and PCM1754 from 105°C to 85°C in the Recommended
Operating Conditions table ..................................................................................................................................................... 4
•
•
•
Added new row for PCM1755 temperature range to the Recommended Operating Conditions table ................................. 4
Changed output voltage value from MIN to TYP in the Electrical Characteristics table ....................................................... 6
Changed center voltage value from MIN to TYP in the Electrical Characteristics table ........................................................ 6
Changes from Revision C (February 2009) to Revision D
Page
•
已添加 添加了 ESD 额定值 表、建议运行条件 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部
分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 ............................................................................. 1
2
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
5 Device Comparison Table
FEATURE
PCM1753, PCM1755
I2S, standard, left-justified
PCM1754
I2S, standard
16-bit and 24-bit I2S, 16-bit standard
Audio data interface format
Audio data bit length
Audio data format
16-bit, 18-bit, 20-bit, and 24-bit selectable
MSB first, 2's complement
6 Pin Configuration and Functions
PCM1753, PCM1755 DBQ Package
16-Pin SSOP
PCM1754 DBQ Package
16-Pin SSOP
Top View
Top View
BCK
DATA
LRCK
DGND
NC
BCK
DATA
LRCK
DGND
NC
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
SCK
SCK
ML
FMT
MC
MUTE
DEMP
TEST
ZEROA
VCOM
MD
ZEROL/NA
ZEROR/ZEROA
VCOM
VCC
VCC
VOUTL
VOUTL
VOUTR
VOUTR
AGND
AGND
Pin Functions
PIN
I/O
DESCRIPTION
PCM1753,
PCM1755
NAME
PCM1754
AGND
BCK
9
1
9
1
—
I
Analog ground
Audio-data bit-clock input
Audio-data digital input
De-emphasis control
Digital ground
DATA
DEMP
DGND
FMT
2
2
I
-
13
4
I
4
—
I
-
15
3
Data format select
LRCK
MC
3
I
L-channel and R-channel audio data latch enable input
Mode control clock input
Mode control data input
14
13
15
-
-
I
MD
-
I
ML
-
I
Mode control latch input
Analog mixing control
MUTE
NC
14
5
I
5
—
I
No connection
SCK
16
-
16
12
6
System clock input
TEST
VCC
VCOM
I
Test pin, ground or open
Analog power supply, 5 V
Common voltage decoupling
Analog output for L-channel
Analog output for R-channel
6
—
—
O
O
10
7
10
7
VOUTL
VOUTR
8
8
Zero flag output for R-channel / Zero flag output for L-/R-channel.
Open-drain output for PCM1755.
ZEROR/ZEROA
ZEROL/NA
11
12
11
-
O
O
Zero flag output for L-channel / Not assigned.
Open-drain output for PCM1755.
Copyright © 2003–2019, Texas Instruments Incorporated
3
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
Supply voltage
VCC
–0.3
6.5
±0.1
6.5
Ground voltage differences
Input voltage
AGND, DGND
V
–0.3
V
Input current (any pins except supplies)
±10
85
mA
PCM1753, PCM1754
PCM1755
–40
–25
Ambient temperature under bias
°C
85
Junction temperature
150
150
°C
°C
Storage temperature, Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
VCC
TA
Supply voltage
4.5
–40
–25
5
5.5
85
85
V
PCM1753, PCM1754
PCM1755
Operating temperature
°C
7.4 Thermal Information
PCM175x
DBQ (SSOP)
16 PINS
104.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
53
46.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.3
ψJB
46.4
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
7.5 Electrical Characteristics
all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted)
PARAMETER
Resolution
DATA FORMAT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
24
Bits
fS
Sampling frequency
5
200
kHz
kHz
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1152 fS
System clock frequency
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
VIH
VIL
Input logic level, high
2
VDC
VDC
Input logic level, low
0.8
10
Input logic current, high (SCK, BCK, DATA,
and LRCK pins)
IIH
IIL
IIH
IIL
VIN = VCC
µA
µA
µA
µA
Input logic current, low (SCK, BCK, DATA,
and LRCK pins)
VIN = 0 V
VIN = VCC
VIN = 0 V
-10
100
-10
Input logic current, high (TEST, DEMP,
MUTE, and FMT pins)
65
Input logic current, low (TEST, DEMP,
MUTE, and FMT pins)
VOH
VOL
Output logic level, high (ZEROA pin)
IOH = –1 mA
IOL = 1 mA
2.4
VDC
VDC
Output logic level, low (ZEROA pin)
0.4
DYNAMIC PERFORMANCE(1)(2)
fS = 44.1 kHz
0%
0%
0.01%
THD+N at VOUT = 0 dB
fS = 96 kHz
fS = 192 kHz
0%
fS = 44.1 kHz
0.65%
0.80%
0.95%
106
THD+N at VOUT = -60 dB
Dynamic range
fS = 96 kHz
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
A-weighted, fS = 96 kHz
A-weighted, fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
A-weighted, fS = 96 kHz
A-weighted, fS = 192 kHz
fS = 44.1 kHz
100
100
97
104
dB
dB
102
106
Signal-to-noise ratio
Channel separation
104
102
103
fS = 96 kHz
101
dB
dB
fS = 192 kHz
100
Level linearity error
VOUT = -90 dB
±0.5
DC ACCURACY
% of
FSR
Gain error
±1
±6
% of
FSR
Gain mismatch, channel-to-channel
Bipolar zero error
±1
±3
VOUT = 0.5 VCC at BPZ
±30
±60
mV
(1) Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in
the averaging mode.
(2) Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS of register 18.
Copyright © 2003–2019, Texas Instruments Incorporated
5
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
Electrical Characteristics (continued)
all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
80% of
VCC
Output voltage
Full scale (0 dB)
VPP
50% of
VCC
Center voltage
VDC
Load impedance
AC-coupled load
±0.04 dB
5
kΩ
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS (SHARP ROLLOFF)
Pass band
Stop band
0.454 fS
±0.04
0.546 fs
–50
Pass-band ripple
dB
dB
Stop-band attenuation
ANALOG FILTER PERFORMANCE
Stop band = 0.546 fS
At 20 kHz
At 44 kHz
–0.03
–0.2
Frequency response
dB
POWER SUPPLY REQUIREMENTS(2)
fS = 44.1 kHz
fS = 96 kHz
fS = 192 kHz
fS = 44.1 kHz
fS = 96 kHz
fS = 192 kHz
16
25
21
ICC
Supply current
mA
mW
30
80
105
Power dissipation
125
150
TEMPERATURE
RθJA
Thermal Resistance
16-pin DBQ
104.1
°C/W
7.6 System Clock Input Timing
for more information, see the System Clock Input section
MIN
NOM
MAX UNIT
t(SCKH)
t(SCKL)
t(SCY)
System clock pulse duration, high
System clock pulse duration, low
System clock pulse cycle time
7
7
ns
ns
ns
See Figure 20.
(1)
See
(1) 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS.
7.7 Audio Interface Timing
for more information, see the Audio Data Formats and Timing section
MIN
MAX
UNIT
1/(32 fS)
1/(48 fS)
t(BCY)
BCK pulse cycle time
1/(64 fS)(1)
t(BCH)
t(BCL)
t(BL)
BCK high–level time
35
35
10
ns
ns
ns
BCK low–level time
See Figure 22.
BCK rising edge to LRCK edge
LRCK falling edge to BCK rising
edge
t(LB)
10
ns
t(DS)
t(DH)
DATA setup time
DATA hold time
10
10
ns
ns
(1) fS is the sampling frequency (for example, 44.1 kHz, 48 kHz, 96 kHz, and so on).
6
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
7.8 Control Interface Timing Requirements
these timing parameters are critical for proper control port operation
MIN
100
50
NOM
MAX
UNIT
ns
t(MCY)
t(MCL)
t(MCH)
t(MCH)
t(MLS)
t(MLH)
t(MDH)
t(MCS)
MC pulse cycle time
MC low-level time
MC high-level time
ML high-level time
ML falling edge to MC rising edge
ML hold time(2)
ns
50
ns
(1)
See
ns
See Figure 1.
20
20
15
20
ns
ns
MD hold time
ns
MD setup time
ns
3
256 ´ f
(1)
S seconds (min); fS: sampling rate.
(2) MC rising edge for LSB to ML rising edge.
t(MHH)
ML
t(MCL)
t(MLS)
t(MCH)
t(MLH)
MC
MD
t(MCY)
LSB
t(MDS)
t(MDH)
Figure 1. Control Interface Timing
Copyright © 2003–2019, Texas Instruments Incorporated
7
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
7.9 Typical Characteristics
7.9.1 Digital Filter (De-Emphasis Off)
all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
0
–20
0.05
0.04
0.03
–40
0.02
0.01
–60
0.00
–80
–0.01
–0.02
–0.03
–0.04
–0.05
–100
–120
–140
0
1
2
3
4
0.0
0.1
0.2
Frequency[×f ]
S
0.3
0.4
0.5
Frequency[× f
]
S
Figure 2. Frequency Response, Sharp Rolloff
Figure 3. Pass-Band Ripple, Sharp Rolloff
0
5
4
–20
–40
3
2
1
–60
0
–80
–1
–2
–3
–4
–5
–100
–120
–140
0
1
2
3
4
0.0
0.1
0.2
Frequency [×f ]
S
0.3
0.4
0.5
Frequency[×f
]
S
Figure 4. Frequency Response, Slow Rolloff
Figure 5. Transition Characteristics, Slow Rolloff
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
Frequency (kHz)
Frequency (kHz)
Figure 6. De-Emphasis Level vs Frequency
Figure 7. De-Emphasis Error vs Frequency
8
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
Digital Filter (De-Emphasis Off) (continued)
all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
Frequency (kHz)
Frequency (kHz)
Figure 8. De-Emphasis Level vs Frequency
Figure 9. De-Emphasis Error vs Frequency
0
–1
–2
–3
–4
–5
–6
–7
–8
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–
9
–10
16 18 20 22
0
2
4
6
8
10 12 14
16 18 20 22
0
2
4
6
8
10 12 14
Frequency (kHz)
Frequency (kHz)
Figure 10. De-Emphasis Level vs Frequency
Figure 11. De-Emphasis Error vs Frequency
Copyright © 2003–2019, Texas Instruments Incorporated
9
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
7.9.2 Analog Dynamic Performance (Supply Voltage Characteristics)
All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
110
108
106
104
102
100
98
10
44.1 kHz, 384 f
S
96 kHz, 384 f
S
192 kHz, 128 f
S
1
0.1
–60 dB
0.01
0 dB
0.001
44.1 kHz, 384 f
S
96 kHz, 384 f
S
192 kHz, 128 f
S
96
0.0001
4.0
4.5
5.0
5.5 6.0
4.0
4.5
5.0
5.5
6.0
Supply Voltage (V)
Supply Voltage (V)
Figure 12. Total Harmonic Distortion + Noise vs Supply
Voltage
Figure 13. Dynamic Range vs Supply Voltage
110
110
44.1 kHz, 384 f
44.1 kHz, 384 f
S
S
96 kHz, 384 f
96 kHz, 384 f
S
S
108
106
104
102
100
98
108
106
104
102
100
98
192 kHz, 128 f
192 kHz, 128 f
S
S
96
96
4.0
4.5
5.0
5.5
6.0
4.0
4.5
5.0
5.5
6.0
Supply Voltage (V)
Supply Voltage (V)
Figure 14. Signal-to-Noise Ratio vs Supply Voltage
Figure 15. Channel Separation vs Supply Voltage
10
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
7.9.3 Analog Dynamic Performance (Temperature Characteristics)
All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, (unless otherwise noted)
110
108
106
104
102
100
98
10
44.1 kHz, 384 f
S
96 kHz, 384 f
S
–60 dB
192 kHz, 128 f
S
1
0.1
0.01
0 dB
0.001
44.1 kHz, 384 f
S
96 kHz, 384 f
S
192 kHz, 128 f
S
96
0.0001
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Free-Air Temperature (°C)
Free-Air Temperature (°C)
Figure 16. Total Harmonic Distortion + Noise vs Free-Air
Temperature
Figure 17. Dynamic Range vs Free-Air Temperature
110
110
44.1 kHz, 384 f
S
44.1 kHz, 384 f
S
96 kHz, 384 f
S
96 kHz, 384 f
S
108
108
192 kHz, 128 f
S
192 kHz, 128 f
S
106
104
102
100
98
106
104
102
100
98
96
96
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Free-Air Temperature (°C)
Free-Air Temperature (°C)
Figure 18. Signal-to-Noise Ratio vs Free-Air Temperature
Figure 19. Channel Separation vs Free-Air Temperature
Copyright © 2003–2019, Texas Instruments Incorporated
11
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
8 Detailed Description
8.1 Overview
The PCM175x devices are stereo digital-to-analog converters (DACs) based on TI's enhanced delta-sigma
architecture which employ 4th-order noise shaping and 8-level amplitude quantization to achieve excellent
dynamic performance and improved clock jitter tolerance. The PCM175x devices easily interface with audio DSP
and decoder chips because of the devices' support of industry-standard audio data formats with 16- and 24-bit
data. The PCM175x devices can be controlled in a hardware mode, or a full set of user-programmable functions
is accessible through a three-wire serial control port, which supports register-write functions.
8.2 Functional Block Diagram
BCK
Audio
LRCK
Serial
V
V
V
L
Output Amp
and
OUT
DATA
Port
DAC
Low-Pass Filter
4x/8x
Oversampling
Digital
Enhanced
Multilevel
Delta-Sigma
Modulator
Filter
and
FMT
COM
Function
Control
Serial
Control
Port
MUTE
DEMP
Output Amp
and
Low-Pass Filter
DAC
R
OUT
TEST
SCK
System Clock
System
Clock
Manager
Zero Detect
Power Supply
8.3 Feature Description
8.3.1 System Clock and Reset Functions
8.3.1.1 System Clock Input
The PCM175x devices require a system clock for operating the digital interpolation filters and multilevel delta-
sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 lists examples of system clock
frequencies for common audio sampling rates.
Figure 20 shows and the System Clock Input Timing table lists he timing requirements for the system clock input.
For optimal performance, use a clock source with low phase-jitter and noise. TI's PLL170x family of multiclock
generators is an excellent choice for providing the PCM175x system clock.
12
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
Feature Description (continued)
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
SAMPLING
FREQUENCY
128 fS
1.024
192 fS
1.536
256 fS
2.048
384 fS
3.072
512 fS
4.096
768 fS
6.144
1152 fS
9.216
8 kHz
16 kHz
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
192 kHz
2.048
3.072
4.096
6.144
8.192
12.288
24.576
33.8688
18.432
4.096
6.144
8.192
12.288
16.9344
18.432
33.8688
16.384
22.5792
24.576
45.1584
36.864
(1)
5.6448
6.144
8.4672
9.216
11.2896
12.288
22.5792
(1)
(1)
(1)
(1)
36.864
(1)
11.2896
12.288
24.576
16.9344
18.432
36.864
(1)
(1)
24.576
36.864
49.152
(1)
(1)
(1)
(1) This system clock rate is not supported for the given sampling frequency.
t
(SCKH)
H
L
2.0 V
0.8 V
System Clock (SCK)
t
(SCKL)
t
(SCY)
Figure 20. System Clock Input Timing
8.3.1.2 Power-On Reset Functions
The PCM175x devices include a power-on reset function. Figure 21 shows the operation of this function. With the
system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The
initialization sequence requires 1024 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V).
During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or VCC/2. After
the reset period, an internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCK are provided
continuously, the PCM175x devices provide proper analog output with unit group delay against the input data.
V
CC
3.7 V (Max)
3.0 V (Typ)
2.2 V (Min)
Reset
Reset Removal
Internal Reset
System Clock
Don’t Care
1024 System Clocks
Figure 21. Power-On Reset Timing
Copyright © 2003–2019, Texas Instruments Incorporated
13
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
8.3.2 Audio Serial Interface
The audio serial interface for the PCM175x devices consists of a 3-wire synchronous serial port. The interface
includes LRCK (pin 3), BCK (pin 1), and DATA (pin 2). The BCK pin is the serial audio bit clock, and it is used to
clock the serial data present on the DATA pin into the serial shift register of the audio interface. Serial data is
clocked into the PCM175x on the rising edge of the BCK pin. The LRCK pin is the serial audio left and right word
clock. This pin is used to latch serial data into the internal registers of the serial audio interface.
Both the LRCK and BCK pins should be synchronous to the system clock. Ideally, TI recommendeds that the
LRCK and BCK pins be derived from the system clock input, SCK. The LRCK pin is operated at the sampling
frequency, fS. The BCK pin can be operated at 32, 48, or 64 times the sampling frequency for standard (right-
justified) format, and 32 times the sampling frequency of the BCK pin is limited to 16-bit right-justified format only.
The BCK pin can be operated at 48 or 64 times the sampling frequency for the I2S and left-justified formats. 48
times the sampling frequency of BCK is limited to 192/384/768 fS SCKI.
Internal operation of the PCM175x devices is synchronized with the LRCK pin. Accordingly, internal operation is
held when the sampling rate clock of the LRCK pin is changed or when the SCK pin and/or BCK pin is
interrupted for a 3-bit clock cycle or longer. If th SCK, BCK, and LRCK pins are provided continuously after this
held condition, the internal operation is re-synchronized automatically in a period of less than 3/fS. External
resetting is not required.
8.3.2.1 Audio Data Formats and Timing
The PCM1753 device supports industry-standard audio data formats, including right-justified, I2S, and left-
justified. The PCM1754 device supports I2S and 16-bit-word right-justified audio data formats. Figure 23 shows
the data formats. Data formats are selected using the format bits, FMT[2:0], located in control register 20 of the
PCM1753 device, and are selected using the FMT pin on the PCM1754 device. The default data format is 24-bit
left-justified. All formats require binary 2s-complement MSB-first audio data. The Audio Interface Timing table
shows a detailed timing diagram for the serial audio interface.
1.4 V
1.4 V
1.4 V
LRCK
t
t
(BCL)
t
(BCH)
(LB)
BCK
t
t
(BCY)
(BL)
DATA
t
t
(DS)
(DH)
Figure 22. Audio Interface Timing
14
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
BCK
L-Channel
R-Channel
(= 32 f , 48 f or 64 f )
S
S
S,
16-Bit Right-Justified, BCK = 48 f or 64 f
S
S
DATA 14 15 16
1
2
3
14 15 16
1
2
3
14 15 16
LSB
MSB
LSB
MSB
16-Bit Right-Justified, BCK = 32 f
S
DATA 14 15 16
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
18-Bit Right-Justified, BCK = 48 f or 64 f
S
S
DATA 16 17 18
1
3
2
3
16 17 18
LSB
1
3
2
3
16 17 18
LSB
MSB
MSB
20-Bit Right-Justified, BCK = 48 f or 64 f
S
S
18 19 20
1
2
18 19 20
LSB
1
2
18 19 20
LSB
DATA
MSB
MSB
24-Bit Right-Justified, BCK = 48 f or 64 f
S
S
DATA 22 23 24
1
2
3
22 23 24
LSB
1
2
3
22 23 24
LSB
MSB
MSB
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/f
S
LRCK
BCK
L-Channel
R-Channel
(= 48 f or 64 f )
S
S
N–2 N–1
N–2 N–1
1
2
3
N
1
2
3
N
12
DATA
MSB
LSB
MSB
LSB
(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
BCK
L-Channel
R-Channel
(= 48 f or 64 f )
S
S,
N–2 N–1
N–2 N–1
DATA
1
2
3
N
1
2
3
N
1
2
MSB
LSB
MSB
LSB
Figure 23. Audio Data Input Formats
Copyright © 2003–2019, Texas Instruments Incorporated
15
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
8.3.3 Zero Flag (PCM1754)
The PCM1754 device has a ZERO flag pin, ZEROA (pin 11). ZEROA is the L-channel and R-channel common
zero flag pin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK
clock periods), ZEROA is set to a logic 1 state.
8.3.4 Zero Flag (PCM1753)
Zero-Detect Condition
Zero detection for either output channel is independent from the other channel. If the data for a given channel
remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that
channel.
8.3.5 Zero Flag Outputs
If a zero-detect condition exists for one or more channels, the zero flag pins for those channels are set to a logic
1 state. There are zero flag pins for each channel, ZEROL (pin 12) and ZEROR (pin 11). These pins can be used
to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or
other digitally controlled function. The active polarity of zero flag outputs can be inverted by setting the ZREV bit
of control register 22 to 1. The reset default is active-high output, or ZREV = 0. The L-channel and R-channel
common zero flag can be selected by setting the AZRO bit of control register 22 to 1. The reset default is
independent zero flags for L-channel and R-channel, or AZRO = 0.
8.3.6 Analog Outputs
The PCM1753 device includes two independent output channels, VOUTL and VOUTR. These are unbalanced
outputs, each capable of driving 4 VPP typical into a 5-kΩ ac-coupled load. The internal output amplifiers for
VOUTL and VOUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to 0.5 VCC
.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the PCM1754 delta-sigma D/A converters.
The frequency response of this filter is shown in Figure 24. By itself, this filter is not enough to attenuate the out-
of-band noise to an acceptable level for many applications. An external low-pass filter is required to provide
sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Applications
Information section of this data sheet.
10
0
–10
–20
–30
–40
–50
–60
0.1
1
10
100
1
10
k
k
Frequency (kHz)
Figure 24. Output Filter Frequency Response
16
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
8.3.6.1 VCOM Output
One unbuffered common-mode voltage output pin, VCOM (pin 10) is brought out for decoupling purposes. This pin
is nominally biased to a dc voltage level equal to 0.5 VCC. This pin can be used to bias external circuits.
Figure 25 shows an example of using the VCOM pin for external biasing applications.
R2
AV = –1, where AV = –
R1
PCM1754
V
CC
C
R
1
2
R
R
3
1
2
3
10 µF
(1)
–
V X
OUT
1/2
1
Filtered
Output
OPA2353
C
2
+
V
COM
+
10 µF
(1)
X = L or R
(a) Using V
to Bias a Single-Supply Filter Stage
COM
V
CC
PCM1754
–
Buffered V
OPA337
+
COM
V
COM
+
10 µF
(b) Using a Voltage Follower to Buffer V
When Biasing Multiple Nodes
COM
Figure 25. Biasing External Circuits Using the VCOM Pin
8.4 Device Functional Modes
8.4.1 Hardware Control (PCM1754)
The digital functions of the PCM1754 are capable of hardware control. Table 2 lists selectable formats, Table 3
shows de-emphasis control, and Table 4 lists mute control.
Table 2. Data Format Select
FMT (PIN 15)
LOW
DATA FORMAT
16– to 24–bit, I2S format
16–bit right–justified
HIGH
Copyright © 2003–2019, Texas Instruments Incorporated
17
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
Table 3. De-Emphasis Control
DEMP (PIN 13)
DE–EMPHASIS FUNCTION
44.1 kHz de–emphasis OFF
LOW
HIGH
44.1 kHz de–emphasis ON
Table 4. Mute Control
MUTE (PIN 14)
LOW
MUTE
Mute OFF
HIGH
Mute ON
8.4.2 Oversampling Rate Control (PCM1754)
The PCM1754 automatically controls the oversampling rate of the delta-sigma DACs with the system clock rate.
The oversampling rate is set to 64× oversampling with every system clock and sampling frequency.
8.5 Programming
8.5.1 Software Control (PCM1753/55)
The PCM1753 and PCM1755 devices have many programmable functions which can be controlled in the
software control mode. The functions are controlled by programming the internal registers using the ML, MC, and
MD pins.
The serial control interface is a 3-wire serial port, which operates asynchronously to the audio serial interface.
The serial control interface is used to program the on-chip mode registers. The control interface includes MD (pin
13), MC (pin 14), and ML (pin 15). The MD pin is the serial data input, used to program the mode registers. The
MC pin is the serial bit clock, used to shift data into the control port. The ML pin is the control port latch clock.
8.5.1.1 Register Write Operation
All write operations for the serial control port use 16-bit data words. Figure 26 lists the control data word format.
The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index (or
address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the
register specified by IDX[6:0].
Figure 27 lists the functional timing diagram for writing to the serial control port. ML is held at a logic 1 state until
a register needs to be written. To start the register write cycle, ML is set to logic 0. Sixteen clocks are then
provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has
completed, ML is set to logic 1 to latch the data into the indexed mode control register.
Figure 26. Control Data Word Format for MD
Figure 27. Register Write Operation
18
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
8.6 Register Maps
8.6.1 Mode Control Registers (PCM1753/55)
8.6.1.1 User-Programmable Mode Controls
The PCM1753/55 devices include a number of user-programmable functions, which are accessed via control
registers. The registers are programmed using the serial control interface, which was previously discussed in this
data sheet. Table 5 lists the available mode control functions, along with their reset default conditions and
associated register index.
Table 5. User-Programmable Mode Controls
FUNCTION
Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps
Soft mute control
RESET DEFAULT
0 dB, no attenuation
Mute disabled
REGISTER
BIT(s)
AT1[7:0], AT2[7:0]
MUT[2:0]
OVER
16 and 17
18
18
18
19
19
19
20
20
22
22
22
Oversampling rate control (64 fS or 128 fS)
Soft reset control
64 fS oversampling
Reset disabled
SRST
DAC operation control
DAC1 and DAC2 enabled
De-emphasis disabled
44.1 kHz
DAC[2:1]
DM12
De-emphasis function control
De-emphasis sample rate selection
Audio data format control
DMF[1:0]
FMT[2:0]
FLT
24-bit left-justified
Sharp rolloff
Digital filter rolloff control
Zero flag function select
L-, R-channel independent
Normal phase
AZRO
Output phase select
DREV
Zero flag polarity select
High
ZREV
The mode control register map is shown in Table 6. Each register includes an index (or address) indicated by the
IDX[6:0] bits.
Table 6. Mode Control Register Map(1)
IDX
(B8–B REGISTER
14)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
10h
11h
12h
13h
14h
16h
Register 16
Register 17
Register 18
Register 19
Register 20
Register 22
0
0
0
0
0
0
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
AT17
AT27
SRST
RSV
AT16
AT26
OVER
DMF1
RSV
AT15
AT25
RSV
DMF0
FLT
AT14
AT24
RSV
AT13
AT23
RSV
RSV
RSV
RSV
AT12
AT22
RSV
AT11
AT21
MUT2
DAC2
FMT1
ZREV
AT10
AT20
MUT1
DAC1
FMT0
DREV
DM12
RSV
RSV
RSV
FMT2
AZRO
RSV
RSV
RSV
RSV
(1) RSV: Reserved for test operation. It should be set to 0 for regular operation.
Copyright © 2003–2019, Texas Instruments Incorporated
19
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
8.6.1.2 Register Definitions
8.6.1.2.1 ATx[7:0]: Digital Attenuation Level Setting
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default value: 1111 1111b
Each DAC channel (VOUTL and VOUTR) includes a digital attenuation function. The attenuation level can be set
from 0 dB to –63 dB in 0.5-dB steps. Changes in attenuator levels are made by incrementing or decrementing
one step (0.5 dB) for every 8/fS time internal until the programmed attenuator setting is reached. Alternatively,
the attenuation level can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. The attenuation level is set using the following
formula:
Attenuation level (dB) = 0.5 × (ATx[7:0]DEC – 255)
where ATx[7:0]DEC = 0 through 255.
For ATx[7:0]DEC = 0 through 128, attenuation is set to infinite attenuation.
The table in Figure 28 shows the attenuation levels for various settings:
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Figure 28. ATx[7:0]: Digital Attenuation Level Setting Table
20
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
8.6.1.2.2 MUTx: Soft Mute Control
where x = 1 or 2, corresponding to the DAC outputs VOUTL (x = 1) and VOUTR (x = 2).
Default value: 0
The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC
outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is
disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the
digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one
attenuator step (0.5 dB) for every 8/fS seconds. This provides pop-free muting of the DAC output.
By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmed
attenuation level.
8.6.1.2.3 OVER: Oversampling Rate Control
Default value: 0
System clock rate = 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS:
System clock rate = 128 fS or 192 fS:
The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters. The OVER = 1 setting
is recommended when the sampling rate is 192 kHz (system clock rate is 128 fS or 192 fS).
8.6.1.2.4 SRST: Reset
Default value: 0
The SRST bit is used to enable or disable the soft reset function. The operation is the same as power-on reset.
All registers are initialized.
8.6.1.2.5 DACx: DAC Operation Control
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2).
Default value: 0
The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR. When DACx =
0, the corresponding output generates the audio waveform dictated by the data present on the DATA pin. When
DACx = 1, the corresponding output is set to the bipolar zero level, or 0.5 VCC
.
Copyright © 2003–2019, Texas Instruments Incorporated
21
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
8.6.1.2.6 DM12: Digital De-Emphasis Function Control
Default value: 0
The DM12 bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical
Characteristics section of this data sheet.
8.6.1.2.7 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
Default value: 00
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is
enabled.
8.6.1.2.8 FMT[2:0]: Audio Interface Data Format
Default value: 101
The FMT[2:0] bits are used to select the data format for the serial audio interface. The table in Figure 29 shows
the available format options.
Figure 29. FMT[2:0]: Audio Interface Data Format Table
22
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
8.6.1.2.9 FLT: Digital Filter Rolloff Control
Default value: 0
The FLT bit allows the user to select the digital filter rolloff that is best suited to the application. Two filter rolloff
selections are available, sharp and slow. The filter responses for these selections are shown in the Typical
Characteristics section of this data sheet.
8.6.1.2.10 DREV: Output Phase Select
Default value: 0
The DREV bit is the output analog signal phase control.
8.6.1.2.11 ZREV: Zero Flag Polarity Select
Default value: 01h
The ZREV bit allows the user to select the polarity of zero flag pins.
8.6.1.2.12 AZRO: Zero Flag Function Select
Default value: 0
The AZRO bit allows the user to select the function of zero flag pins.
Copyright © 2003–2019, Texas Instruments Incorporated
23
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The delta-sigma section of the PCM175x device is based on an 8-level amplitude quantizer and a 4th-order noise
shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8-
level delta-sigma modulator is shown in Figure 32. This 8-level delta-sigma modulator has the advantage of
stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64 fS.
The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 35 and
Figure 36. The enhanced multilevel delta-sigma architecture also has advantages for input clock jitter sensitivity
due to the multilevel quantizer, with the simulated jitter sensitivity shown in Figure 37.
The PCM175X devices are suitable for a wide variety of cost-sensitive consumer applications requiring good
performance and operation with a single 5-V supply.
9.2 Typical Application
A basic connection diagram is shown in Figure 30, with the necessary power supply bypassing and decoupling
components. TI recommends using the component values shown in Figure 30 for all designs.
The use of series resistors (22 Ω to 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs. The
series resistor combines with the stray PCB and device input capacitance to form a low-pass filter, which reduces
high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines.
For this design example, use the parameters listed in Table 7.
PCM1754
System Clock
Format
BCK
SCK
FMT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCM Audio Data
DATA
LRCK
DGND
NC
MUTE On/Off
DEMP On/Off
MUTE
DEMP
TEST
Zero Mute Control
V
CC
ZEROA
+5 V
10 µF
V
OUT
V
OUT
L
V
COM
+
10 µF
10 µF
R
AGND
10 µF
Post LPF
L-Ch Out
Post LPF
R-Ch Out
Figure 30. Basic Connection Diagram
24
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Design Parameters
Table 7 lists the design parameters and example values for the PCM175x devices.
Table 7. Design Parameters
DESIGN PARAMETER
Audio input
EXAMPLE VALUE
PCM audio data
0 VPP - 4 VPP
Hardware
Analog output
Part configuration
9.2.1.2 Power Supplies and Grounding
The PCM1754 device requires 5 V for VCC
.
Proper power supply bypassing is shown in Figure 30. The 10-μF capacitors should be tantalum or aluminum
electrolytic.
9.2.1.3 D/A Output Filter Circuits
Delta-sigma D/A converters use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR)
performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The
out-of-band noise must be low-pass filtered in order to provide the optimal converter performance. This is
accomplished by a combination of on-chip and external low-pass filtering.
Figure 25(a) and Figure 31 show the recommended external low-pass active filter circuits for single- and dual-
supply applications. These circuits are 2nd-order Butterworth filters using the multiple feedback (MFB) circuit
arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For
more information regarding MFB active filter design, see Burr-Brown applications bulletin (SBAA055), available
from the TI Web site at http://www.ti.com.
Because the overall system performance is defined by the quality of the D/A converters and their associated
analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters. TI's
OPA2353 and OPA2134 dual operational amplifiers are shown in Figure 25(a) and Figure 31, and are
recommended for use with the PCM1754 device.
R
C
2
1
R
R
3
1
2
R
–
4
V
IN
1
OPA2134
V
OUT
3
C
+
2
R2
R1
AV = –
Figure 31. Dual-Supply Filter Circuit
Copyright © 2003–2019, Texas Instruments Incorporated
25
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
9.2.2 Detailed Design Procedure
9.2.2.1 Total Harmonic Distortion + Noise
Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio D/A converters because it
takes into account both harmonic distortion and all noise sources within a specified measurement bandwidth.
The average value of the distortion and noise is referred to as THD+N.
For the PCM175x, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at the input
of the DAC (see Figure 33). The digital generator is set to 24-bit audio word length and a sampling frequency of
44.1 kHz or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the
measurement system. The S/PDIF data is transmitted via a coaxial cable to the digital audio receiver on the
DEM-DAI1753 demonstration board. The receiver is then configured to output 24-bit data in either I2S or left-
justified data format. The DAC audio interface format is programmed to match the receiver output format. The
analog output is then taken from the DAC post filter and connected to the analog analyzer input of the
measurement system. The analog input is band limited using filters resident in the analyzer. The resulting
THD+N is measured by the analyzer and displayed by the measurement system.
+
+
+
+
+
IN
+
+
+
+
–1
–1
–1
–1
Z
Z
Z
Z
8 f
S
+ +
+
+
8-Level Quantizer
OUT
64 f
S
Figure 32. Eight-Level Delta-Sigma Modulator
26
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
9.2.2.2 Dynamic Range
Dynamic range is specified as A-weighted THD+N measured with a –60-dB full-scale, 1-kHz digital sine wave
stimulus at the input of the D/A converter. This measurement is designed to give a good indicator of how the
DAC performs given a low-level input signal.
The measurement setup for the dynamic range measurement is shown in Figure 34, and is similar to the THD+N
test setup discussed previously. The differences include the band limit filter selection, the additional A-weighting
filter, and the –60-dB full-scale input level.
Evaluation Board
DEM-DAI1753
2nd-Order
S/PDIF
PCM1754
Low-Pass
Filter
Receiver
f
= 54 kHz or 108 kHz
–3 dB
Audio Precision System Two
Analyzer
and
Display
Digital
AES17 Filter
Generator
Band Limit
S/PDIF
Output
0 dB FS
(100% Full-Scale),
24-Bit,
Averaging
Mode
HPF = 400 Hz
LPF = 30 kHz
f
= 20.9 kHz
–3 dB
1-kHz Sine Wave
Figure 33. Test Setup for THD+N Measurement
9.2.2.3 Idle Channel Signal-to-Noise Ratio (SNR)
The SNR test provides a measure of the noise floor of the D/A converter. The input to the D/A is all-0s data, and
the dither function of the digital generator must be disabled to ensure an all-0s data stream at the input of the
D/A converter.
The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input
signal level.
(See the note provided in Figure 34).
Evaluation Board
DEM-DAI1753
2nd-Order
S/PDIF
PCM1754
Low-Pass
Filter
Receiver
f
= 54 kHz or 108 kHz
–3 dB
Audio Precision System Two
Analyzer
Digital
A-Weighting
(1)
and
Display
AES17 Filter
Generator
Filter
S/PDIF
Output
Band Limit
0% Full-Scale,
Dither Off (SNR)
or –60 dB FS,
Averaging
Mode
HPF = 400 Hz
LPF = 30 kHz
f
= 20.9 kHz
–3 dB
1 kHz Sine Wave
(Dynamic Range)
(1)
Results without A-Weighting are approximately 3 dB worse.
Figure 34. Test Setup for Dynamic Range and SNR Measurement
Copyright © 2003–2019, Texas Instruments Incorporated
27
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
9.2.3 Application Curves
0
20
0
20
40
40
60
60
80
80
100
120
140
160
180
100
120
140
160
180
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Frequency [×f ]
S
Frequency[×f ]
S
Figure 35. Quantization Noise Spectrum (×64
Oversampling)
Figure 36. Quantization Noise Spectrum (×128
Oversampling)
125
120
115
110
105
100
95
90
0
100
200
300
400
500
600
Jitter (psp-p
)
Figure 37. Jitter Dependence (×64 Oversampling)
28
Copyright © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
10 Power Supply Recommendations
The PCM175x devices are designed to operate from a 4.5-V to 5.5-V power supply. Ensure that the power
supply is clean and use high-quality decoupling capacitors to reduce noise. The bulk capacitances can be from
either tantalum or aluminum capacitors.
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the PCM175x devices. In cases where a common 5-V supply must be used for the
analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and
digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 39
shows the recommended approach for single-supply applications.
11 Layout
11.1 Layout Guidelines
Figure 38 shows a typical PCB floor plan for the PCM175x devices. A ground plane is recommended, with the
analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM175x
should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections
to the digital audio interface and control signals originating from the digital section of the board.
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the PCM175x. In cases where a common 5-V supply must be used for the analog and
digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V
supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 39 shows the
recommended approach for single-supply applications.
11.2 Layout Example
Digital Power
+V DGND
Analog Power
AGND +5VA +V –V
S
D
S
V
CC
Digital Logic
and
Audio
Output
DGND
PCM1754
Circuits
Processor
Digital
Ground
AGND
Analog
Ground
Digital Section
Analog Section
Return Path for Digital Signals
Figure 38. Recommended PCB Layout
Copyright © 2003–2019, Texas Instruments Incorporated
29
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
Layout Example (continued)
Power Supplies
AGND +V
RF Choke or Ferrite Bead
+5V
–V
S
S
V
CC
V
DD
Output
DGND
Circuits
PCM1754
AGND
Common
Ground
Digital Section
Analog Section
Figure 39. Single-Supply PCB Layout
30
版权 © 2003–2019, Texas Instruments Incorporated
PCM1753, PCM1754, PCM1755
www.ti.com.cn
ZHCSK28E –APRIL 2003–REVISED JULY 2019
12 器件和文档支持
12.1 相关文档ꢀ
请参阅如下相关文档：
•
•
•
•
•
德州仪器 (TI)，《数字音频数模转换器的动态性能测试》 应用简报
德州仪器 (TI)，《OPA2353 高速单电源轨至轨运算放大器 MicroAmplifier™ 系列》数据表
德州仪器 (TI)，《OPA2134 SoundPlus™ 高性能音频运算放大器》数据表
德州仪器 (TI)，《PLL170x 3.3V 双路 PLL 多时钟发生器》数据表
德州仪器 (TI)，《PCM175x-Q1 24 位 192kHz 采样增强型多级 Δ-Σ 音频数模转换器》数据表
12.2 相关链接
表 8 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品的快速链
接。
表 8. 相关链接
产品文件夹
单击此处
单击此处
单击此处
单击此处
样片与购买
单击此处
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
单击此处
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 商标
E2E is a trademark of Texas Instruments.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2003–2019, Texas Instruments Incorporated
31
PCM1753, PCM1754, PCM1755
ZHCSK28E –APRIL 2003–REVISED JULY 2019
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
32
版权 © 2003–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM1753DBQ
PCM1753DBQR
PCM1754DBQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
DBQ
DBQ
DBQ
DBQ
DBQ
DBQ
DBQ
DBQ
16
16
16
16
16
16
16
16
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PCM1753
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
PCM1753
PCM1754
PCM1754
PCM1754
PCM1754
PCM1755
PCM1755
75
75
RoHS & Green
RoHS & Green
PCM1754DBQG4
PCM1754DBQR
PCM1754DBQRG4
PCM1755DBQ
2000 RoHS & Green
2000 RoHS & Green
75
RoHS & Green
PCM1755DBQR
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1753DBQR
PCM1754DBQR
PCM1755DBQR
SSOP
SSOP
SSOP
DBQ
DBQ
DBQ
16
16
16
2000
2000
2000
330.0
330.0
330.0
12.4
12.4
12.4
6.4
6.4
6.4
5.2
5.2
5.2
2.1
2.1
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM1753DBQR
PCM1754DBQR
PCM1755DBQR
SSOP
SSOP
SSOP
DBQ
DBQ
DBQ
16
16
16
2000
2000
2000
356.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PCM1753DBQ
PCM1754DBQ
PCM1754DBQG4
PCM1755DBQ
DBQ
DBQ
DBQ
DBQ
SSOP
SSOP
SSOP
SSOP
16
16
16
16
75
75
75
75
506.6
506.6
506.6
506.6
8
8
8
8
3940
3940
3940
3940
4.32
4.32
4.32
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明