PCM1770RGAR [TI]
LOW VOLTAGE AND POWER STEREO AUDIO DIGITAL TO ANALOG CONVER WITH HEADPHONE AMPLIFER; 低电压和功耗立体声音频数模转换器CONVER ,带有耳机放大器型号: | PCM1770RGAR |
厂家: | TEXAS INSTRUMENTS |
描述: | LOW VOLTAGE AND POWER STEREO AUDIO DIGITAL TO ANALOG CONVER WITH HEADPHONE AMPLIFER |
文件: | 总29页 (文件大小:308K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
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D
Pop-Noise-Free Circuit
3.3-V Tolerant
FEATURES
D
D
D
D
Multilevel DAC Including Headphone
Amplifier
Packages: TSSOP-16 and VQFN-20, Lead Free
Analog Performance (V , V
= 2.4 V):
CC HP
APPLICATIONS
− Dynamic Range: 98 dB Typ
− THD+N at 0 dB: 0.1% Typ
− THD+N at −20 dB: 0.04% Typ
D
D
D
D
Portable Audio Player
Cellular Phone
PDA
− Output Power at R = 16 Ω: 13 mW
L
(Stereo), 26 mW (Monaural)
1.6-V to 3.6-V Single Power Supply
Low Power Dissipation: 6.5 mW at V
Other Applications Requiring Low-Voltage
Operation
D
D
,
CC
V
= 2.4 V
HP
DESCRIPTION
D
D
D
System Clock: 128 f , 192 f , 256 f , 384 f
S S S S
Sampling Frequency: 5 kHz to 50 kHz
The PCM1770 and PCM1771 devices are CMOS,
monolithic, integrated circuits which include stereo
digital-to-analog converters, headphone circuitry, and
support circuitry in small TSSOP-16 and VQFN-20
packages.
Software Control (PCM1770):
− 16-, 20-, 24-Bit Word Available
− Left-, Right-Justified, and I S
2
− Slave/Master Selectable
− Digital Attenuation: 0 dB to –62 dB,
1 dB/Step
− 44.1-kHz Digital De-Emphasis
− Zero Cross Attenuation
− Digital Soft Mute
The data converters use TI’s enhanced multilevel ∆-Σ
architecture, which employs noise shaping and
multilevel amplitude quantization to achieve excellent
dynamic performance and improved tolerance to clock
jitter. The PCM1770 and PCM1771 devices accept
several industry standard audio data formats with 16- to
− Monaural Analog-In With Mixing
− Monaural Speaker Mode
2
24-bit data, left-justified, I S, etc., providing easy
interfacing to audio DSP and decoder devices.
Sampling rates up to 50 kHz are supported. A full set of
user-programmable functions are accessible through a
3-wire serial control port, which supports register write
functions.
D
Hardware Control (PCM1771):
− Left-Justified and I S
− 44.1-kHz Digital De-Emphasis
− Monaural Analog-In With Mixing
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢀꢑ ꢇ ꢐꢓ ꢁ ꢋꢔ ꢇꢏ ꢐ ꢌꢋꢌ ꢗꢘ ꢙꢚ ꢛ ꢜꢝ ꢞꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞꢗ ꢚꢘ ꢦꢝ ꢞꢢꢧ ꢀꢛ ꢚꢦꢡ ꢠꢞꢟ
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ꢀꢛ ꢚ ꢦꢡꢠ ꢞ ꢗꢚ ꢘ ꢣꢛ ꢚ ꢠ ꢢ ꢟ ꢟ ꢗꢘ ꢬ ꢦꢚ ꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢫ ꢗꢘꢠ ꢥꢡꢦ ꢢ ꢞꢢ ꢟꢞꢗ ꢘꢬ ꢚꢙ ꢝꢥ ꢥ ꢣꢝ ꢛ ꢝꢜ ꢢꢞꢢ ꢛ ꢟꢧ
Copyright 2004, Texas Instruments Incorporated
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www.ti.com
SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
OPERATION
TEMPERATURE
RANGE
PRODUCT
PACKGE
PACKAGE
CODE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PACKAGE
PCM1770PW
PCM1770PWR
PCM1770RGA
PCM1770RGAR
PCM1771PW
Tube
Tape and reel
Tray
PCM1770PW
PCM1770RGA
PCM1771PW
PCM1771RGA
16-lead TSSOP
20-lead VQFN
16-lead TSSOP
20-lead VQFN
16PW
20RGA
16PW
−25°C to 85°C
−25°C to 85°C
−25°C to 85°C
−25°C to 85°C
PCM1770
PCM1770
PCM1771
PCM1771
Tape and reel
Tube
PCM1771PWR
PCM1771RGA
PCM1771RGAR
Tape and reel
Tray
20RGA
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
PCM1770
PCM1771
Supply voltage: V , V
CC HP
4 V
0.1 V
Supply voltage differences: V , V
CC HP
Ground voltage differences
Digital input voltage
0.1 V
–0.3 V to 4.0 V
10 mA
Input current (any terminals except supplies)
Operating temperature
–40°C to 125°C
–55°C to 150°C
150°C
Storage temperature
Junction temperature
Lead temperature (soldering)
Package temperature (IR reflow, peak)
260°C, 5 s
260°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
all specifications at T = 25°C, V
= V
HP
= 2.4 V, f = 44.1 kHz, system clock = 256 f and 24-bit data, R = 16 Ω, unless otherwise noted
A
CC
S
S
L
PCM1770PW, PCM1771PW,
PCM1770RGA, PCM1771RGA
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Resolution
24
Bits
OPERATING FREQUENCY
Sampling frequency (f )
S
5
50
kHz
System clock frequency
128f , 192 f , 256 f , 384 f
S
S
S
S
(1)(2)
DIGITAL INPUT/OUTPUT
V
V
0.7 V
Vdc
Vdc
µA
IH
IL
CC
Input logic level
0.3 V
CC
10
I
I
V
IN
V
IN
= V
CC
= 0 V
IH
Input logic current
–10
µA
IL
V
V
I
I
= –2 mA
= 2 mA
0.7 V
Vdc
Vdc
OH
OH
CC
(3)
Output logic level
0.3 V
OL
OL
CC
DYNAMIC PERFORMANCE (HEADPHONE OUTPUT)
Full scale output voltage
Dynamic range
0 dB
0.55 V
V
P-P
dB
HP
98
EIAJ, A-weighted
EIAJ, A-weighted
0 dB (13 mW)
−20 dB (0.1 mW)
Stereo
90
90
Signal-to-noise ratio
98
dB
0.1%
0.04%
13
THD+N
0.1%
10
20
64
14
mWrms
mWrms
dB
Output power
Monaural
26
Channel separation
Load resistance
72
16
Ω
DC ACCURACY
Gain error
2
2
8
8
% of FSR
% of FSR
mV
Gain mismatch,
channel-to-channel
Bipolar zero error
V
OUT
= 0.5 V
CC
at BPZ
30
75
ANALOG LINE INPUT (MIXING CIRCUIT)
Analog input voltage range
0.584 V
HP
V
P-P
Gain (analog input to headphone
output)
0.67
Analog input impedance
THD+N
10
kΩ
AIN = 0.56 V
HP
(peak-to-peak)
0.1%
DIGITAL FILTER PERFORMANCE
Pass band
0.454 f
S
Stop band
0.546 f
S
Pass-band ripple
0.04
dB
dB
Stop-band attenuation
Group delay
–50
20/f
S
44.1-kHz de-emphasis error
0.1
dB
(1)
(2)
(3)
Digital inputs and outputs are CMOS compatible.
All logic inputs are 3.3-V tolerant and not terminated internally.
LRCK and BCK terminals
3
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
ELECTRICAL CHARACTERISTICS(continued)
all specifications at T = 25°C, V
= V
= 2.4 V, f = 44.1 kHz, system clock = 256 f and 24-bit data, R = 16 Ω, unless otherwise noted
A
CC
HP
S
S
L
PCM1770PW, PCM1771PW,
PCM1770RGA, PCM1771RGA
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
ANALOG FILTER PERFORMANCE
Frequency response
at 20 kHz
0.2
dB
POWER SUPPLY REQUIREMENTS
Voltage range, V , V
CC HP
1.6
2.4
1.5
1.2
3.6
2.5
2.5
Vdc
mA
I
I
BPZ input
BPZ input
CC
HP
Supply current
I
I
+
CC
HP
(1)
Power down
5
15
µA
BPZ input
6.5
12
12
36
mW
Power dissipation
(1)
Power down
µW
TEMPERATURE RANGE
Operation temperature
–25
85
°C
PCM1770PW, −71PW: 16-terminal TSSOP
150
130
θ
Thermal resistance
All input signals are held static.
PCM1770RGA, −71RGA: 20-terminal
VQFN
°C/W
JA
(1)
PIN ASSIGNMENTS
PCM1770
PCM1771
PW PACKAGE
(TOP VIEW)
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LRCK
DATA
BCK
PD
AGND
HGND
SCKI
MS
MC
LRCK
DATA
BCK
PD
AGND
HGND
SCKI
FMT
AMIX
MD
DEMP
V
V
V
V
CC
CC
HP
HP
V
AIN
V
AIN
COM
COM
H
R
H
L
H
R
H
L
OUT
OUT
OUT
OUT
PCM1770
RGA PACKAGE
(TOP VIEW)
PCM1771
RGA PACKAGE
(TOP VIEW)
20 19 18 17 16
15
20 19 18 17 16
1 15
1
FMT
DATA
BCK
MS
MC
MD
V
DATA
BCK
2
3
4
5
14
13
12
11
2
3
4
5
14
13
12
11
AMIX
DEMP
PD
PD
V
CC
AGND
HGND
AGND
HGND
CC
V
V
HP
HP
6
7
8
9
10
6
7
8
9 10
NC − No internal connection
4
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
Terminal Functions
PCM1770PW
TERMINAL
I/O
DESCRIPTIONS
NAME
AGND
AIN
NO.
5
–
I
Analog ground. This is a return for V .
CC
10
3
Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs.
BCK
I/O
Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input
from external device. In the master interface mode, the PCM1770 device generates the BCK output to external device.
DATA
2
6
9
8
1
I
–
Serial audio data input
HGND
Analog ground. This is a return for V .
HP
H
OUT
L
O
O
I/O
L-channel analog signal output of the headphone amplifiers
R-channel analog signal output of the headphone amplifiers
H
OUT
R
LRCK
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device.
In the master interface mode, the PCM1770 device generates the LRCK output to an external device.
MC
MD
MS
PD
14
13
15
4
I
I
I
I
Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
Mode control port serial data input. Controls the operation mode on the PCM1770 device.
Mode control port select. The control port is active when this terminal is low.
Reset input. When low, the PCM1770 device is powered down, and all mode control registers are reset to default
settings.
SCKI
16
12
7
I
System clock input
V
CC
–
–
Power supply for all analog circuits except the headphone amplifier.
V
COM
Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5V
HP
nominal.
V
HP
11
–
Analog power supply for the headphone amplifier circuits. The voltage level must be the same as V
.
CC
PCM1770RGA
TERMINAL
I/O
DESCRIPTIONS
NAME
AGND
AIN
NO.
4
–
I
Analog ground. This is a return for V .
CC
10
2
Monaural analog signal mixer input. The signal can be mixed with output of L- and R-channel DACs.
BCK
I/O
Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input
from external device. In the master interface mode, the PCM1770 device generates the BCK output to external
device.
DATA
1
5
I
–
Serial audio data input
HGND
Analog ground. This is a return for V .
HP
H
L
9
O
O
I/O
L-channel analog signal output of the headphone amplifiers
R-channel analog signal output of the headphone amplifiers
OUT
H
OUT
R
7
LRCK
20
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device.
In the master interface mode, the PCM1770 device generates the LRCK output to an external device.
MC
MD
MS
NC
14
13
15
I
I
Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
Mode control port serial data input. Controls the operation mode on the PCM1770 device.
Mode control port select. The control port is active when this terminal is low.
No connect
I
8, 17,
–
18, 19
PD
3
I
Reset input. When low, the PCM1770 device is powered down, and all mode control registers are reset to default
settings.
SCKI
16
12
6
I
System clock input
V
V
–
–
Power supply for all analog circuits except the headphone amplifier.
Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is
CC
COM
required for noise filtering. Voltage level of this terminal is 0.5V
nominal.
HP
V
HP
11
–
Analog power supply for the headphone amplifier circuits. The voltage level must be the same as V .
CC
5
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
Terminal Functions
PCM1771PW
TERMINAL
I/O
DESCRIPTIONS
NAME
AGND
AIN
NO.
5
–
–
I
Analog ground. This is a return for V .
CC
10
14
3
Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs.
AMIX
BCK
Analog mixing control
I
Serial bit clock. Clocks the individual bits of the audio data input, DATA.
DATA
DEMP
FMT
2
I
Serial audio data input
De-emphasis control
Data format select
13
15
6
I
I
HGND
–
O
O
I
Analog ground. This is a return for V .
HP
H
H
L
9
L-channel analog signal output of the headphone amplifiers
R-channel analog signal output of the headphone amplifiers
OUT
R
OUT
8
LRCK
1
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate.
PD
4
I
Reset input. When low, the PCM1771 device is powered down, and all mode control registers are reset to default
settings.
SCKI
16
12
7
I
System clock input
V
CC
–
–
Power supply for all analog circuits except the headphone amplifier.
V
COM
Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5V
HP
nominal.
V
HP
11
–
Analog power supply for the headphone amplifier circuits. The voltage level must be the same as V
.
CC
PCM1771RGA
TERMINAL
I/O
DESCRIPTIONS
NAME
AGND
AIN
NO.
4
–
–
I
Analog ground. This is a return for V .
CC
10
14
2
Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs.
AMIX
BCK
Analog mixing control
I
Serial bit clock. Clocks the individual bits of the audio data input, DATA.
DATA
DEMP
FMT
1
I
Serial audio data input
De-emphasis control
Data format select
13
15
5
I
I
HGND
–
O
O
I
Analog ground. This is a return for V .
HP
H
OUT
L
9
L-channel analog signal output of the headphone amplifiers
R-channel analog signal output of the headphone amplifiers
H R
OUT
7
LRCK
NC
20
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate.
8, 17,
18, 19
–
I
No connect
PD
3
Reset input. When low, the PCM1771 device is powered down, and all mode control registers are reset to default
settings.
SCKI
16
12
6
I
System clock input
V
V
–
–
Power supply for all analog circuits except the headphone amplifier
Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is
CC
COM
required for noise filtering. Voltage level of this terminal is 0.5V
nominal.
HP
V
HP
11
–
Analog power supply for the headphone amplifier circuits. The voltage level must be the same as V .
CC
6
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
FUNCTIONAL BLOCK DIAGRAM
AIN
Digital
Attenuator
Headphone
Amplifier
LRCK
DATA
× 8
Digital
Filter
Audio
Interface
∆Σ
H
V
R
OUT
DAC
+
BCK
V
COM
COM
(FMT) MS
(AMIX) MC
(DEMP) MD
× 8
Digital
Filter
SPI
Port
∆Σ
H
OUT
L
DAC
+
Clock Manager
Power Supply
SCKI
PD
V
CC
V
HP
AGND
HGND
( ) : PCM1771
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
Digital Filter (De-Emphasis Off)
AMPLITUDE
AMPLITUDE
vs
vs
FREQUENCY
0
FREQUENCY
0.05
0.04
−20
−40
0.03
0.02
0.01
−60
0.00
−80
−0.01
−0.02
−0.03
−0.04
−0.05
−100
−120
−140
0
1
2
3
4
0.0
0.1
0.2
0.3
0.4
0.5
f – Frequency [ꢀ f ]
f – Frequency [ꢀ f ]
S
S
Figure 1
Figure 2
All specifications at T = 25°C, V
CC
= V = 2.4 V, f = 44.1 kHz, system clock = 256 f and 24-bit data, R = 16 Ω, unless otherwise noted.
HP S S L
A
7
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
TYPICAL PERFORMANCE CURVES
De-Emphasis Curves
DE-EMPHASIS ERROR
DE-EMPHASIS LEVEL
vs
vs
FREQUENCY
FREQUENCY
0.5
0.4
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10 12 14 16 18 20
0.0
0.1
0.2
0.3
0.4
0.5
0.6
f – Frequency – kHz
f – Frequency – kHz
Figure 3
Figure 4
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
104
102
100
98
1
0 dB
0.1
–20 dB
96
94
92
1.2
0.01
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
1.6
2.0
2.4
2.8
3.2
3.6
4.0
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 5
Figure 6
All specifications at T = 25°C, V
= V = 2.4 V, f = 44.1 kHz, system clock = 256 f and 24-bit data, R = 16 Ω, unless otherwise noted.
HP S S L
A
CC
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
TYPICAL PERFORMANCE CURVES
SNR
vs
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
104
102
100
98
78
76
74
72
70
68
66
96
94
92
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 7
Figure 8
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
102
101
100
99
0 dB
0.1
98
97
–20 dB
96
95
94
−40
0.01
−40
−20
0
20
40
60
80
100
−20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 9
Figure 10
All specifications at T = 25°C, V
CC
= V = 2.4 V, f = 44.1 kHz, system clock = 256 f and 24-bit data, R = 16 Ω, unless otherwise noted.
HP S S L
A
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
TYPICAL PERFORMANCE CURVES
SNR
vs
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
102
101
100
99
76
75
74
73
72
71
70
69
68
98
97
96
95
94
−40
−20
0
20
40
60
80
100
−40
−20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 11
Figure 12
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
20
18
16
14
12
10
8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Operational
6
Power Down
4
2
0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
V
CC
– Supply Current – V
Figure 13
All specifications at T = 25°C, V
= V = 2.4 V, f = 44.1 kHz, system clock = 256 f and 24-bit data, R = 16 Ω, unless otherwise noted.
HP S S L
A
CC
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
TYPICAL PERFORMANCE CURVES
SUPPLY CURRENT
vs
SAMPLING FREQUENCY
20
18
16
14
12
10
8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Operational
Power Down
6
4
2
0
0
10
20
30
40
50
f
S
– Sampling Frequency – kHz
Figure 14
DYNAMIC RANGE
vs
JITTER
100
99
98
97
96
95
94
0
100
200
300
400
500
600
700
Jitter – ps
Figure 15
All specifications at T = 25°C, V
CC
= V = 2.4 V, f = 44.1 kHz, system clock = 256 f and 24-bit data, R = 16 Ω, unless otherwise noted.
HP S S L
A
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
TYPICAL PERFORMANCE CURVES
OUTPUT SPECTRUM (–60 dB, N = 8192)
OUTPUT SPECTRUM (–60 dB, N = 8192)
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
20
40
60
80
100
120
0
5
10
15
20
f – Frequency – kHz
f – Frequency – kHz
Figure 16
Figure 17
All specifications at T = 25°C, V
= V = 2.4 V, f = 44.1 kHz, system clock = 256 f and 24-bit data, R = 16 Ω, unless otherwise noted.
HP S S L
A
CC
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
DETAILED DESCRIPTION
SYSTEM CLOCK, RESET, AND FUNCTIONS
System Clock Input
The PCM1770 and PCM1771 devices require a system clock for operating the digital interpolation filters and multilevel ∆-Σ
modulators. The system clock is applied at terminal 16 (SCKI). Table 1 shows examples of system clock frequencies for
common audio sampling rates.
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock
source with low phase jitter and noise.
Table 1. System Clock Frequency for Common Audio Sampling Frequencies
SAMPLING FREQUENCY, LRCK
SYSTEM CLOCK FREQUENCY, SCKI (MHz)
128 f 192 f 256 f 384 f
S
S
S
S
48 kHz
44.1 kHz
32 kHz
6.144
5.6448
4.096
3.072
2.8224
2.048
1.536
1.4112
1.024
9.216
8.4672
6.144
4.608
4.2336
3.072
2.304
2.1168
1.536
12.288
11.2896
8.192
18.432
16.9344
12.288
9.216
24 kHz
6.144
22.05 kHz
16 kHz
5.6448
4.096
8.4672
6.144
12 kHz
3.072
4.608
11.025 kHz
8 kHz
2.8224
2.048
4.2336
3.072
t
(SCKH)
0.7 V
0.3 V
CC
SCKI
CC
t
(SCKL)
System Clock
Pulse Cycle Time
†
†
1/(128f ), 1/(192f ), 1/(256f ), and 1/(384f )
S
S
S
S
PARAMETERS
SYMBOL
MIN
7
UNIT
ns
System clock pulse width high
System clock pulse width low
t
(SCKH)
t
7
ns
(SCKL)
Figure 18. System Clock Timing
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
POWER ON/OFF AND RESET
The PCM1770/71 always must have the PD pin set from LOW to HIGH once after power-supply voltages V and V
CC
HP
have reached the specified voltage range and stable clocks SCKI, BCK, and LRCK are being supplied for the power-on
sequence. A minimum time of 1 ms after both the clock and power-supply requirements are met is required before the PD
pin changes from LOW to HIGH, as shown in Figure 19. Subsequent to the PD LOW-to-HIGH transition, the internal logic
state is held in reset for 1024 system clock cycles prior to the start of the power-on sequence. During the power-on
sequence, H
L and H
R increase gradually from ground leved, reaching an output level that corresponds to the input
OUT
OUT
data after a period of 9334/f . When powering off, the PD pin is set from HIGH to LOW first. Then H
L and H
R
S
OUT
OUT
decrease gradually to ground level over a period of 9334/f , as shown in Figure 20, after which power can be removed
S
without creating pop noise. When powering on or off, adhering to the timing requirements of Figure 19 and Figure 20
ensures that pop noise does not occur. If the timing requirements are not met, pop noise might occur.
V , V
CC HP
0 V
1 ms (Min)
1 ms (Min)
1024 Internal System Clocks
LRCK, BCK, SCKI
PD
Internal Reset
9334/f
S
0 V
H L, H R
OUT OUT
Figure 19. Power-On Sequence
V , V
CC HP
0 V
LRCK, BCK, SCKI
9334/f
S
PD
H L, H R
OUT OUT
0 V
Figure 20. Power-Off Sequence
14
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
POWER-UP/-DOWN SEQUENCE AND RESET
The PCM1770 device has two kinds of power-up/-down methods: the PD terminal through hardware control and PWRD
(register 4, B0) through software control. The PCM1771 device has only the PD terminal through hardware control for the
power-up/-down sequence. The power-up or power-down sequence operates the same as the power-on or power-off
sequence. When powering up or down using the PD terminal, all digital circuits are reset. When powering up or down using
PWRD, all digital circuits are reset except for maintaining the logic states of the registers. Figure 21 shows the
power-up/power-down sequence.
2.4 V
V , V
CC HP
9334/f
9334/f
S
S
LRCK, BCK, SCKI
PD
H L, H R
OUT OUT
0 V
Figure 21. Power-Down and Power-Up Sequences
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1770 and PCM1771 devices consists of a 3-wire synchronous serial port. It includes
terminals 1 (LRCK), 2 (DATA), and 3 (BCK). BCK is the serial audio bit clock, and it clocks the serial data present on DATA
into the audio interface serial shift register. Serial data is clocked into the PCM1770 and PCM1771 devices on the rising
edge of BCK. LRCK is the serial audio left/right word clock. It latches serial data into the serial audio interface internal
registers.
Both LRCK and BCK of the PCM1770 device support the slave and master modes which are set by FMT (register 3). LRCK
and BCK are outputs during the master mode and inputs during the slave mode.
In slave mode, BCK and LRCK are synchronous to the audio system clock, SCKI. Ideally, it is recommended that LRCK
and BCK be derived from SCKI. LRCK is operated at the sampling frequency, f . BCK can be operated at 32, 48, and 64
S
times the sampling frequency.
In master mode, BCK and LRCK are derived from the system clock and these terminals are outputs. The BCK and LRCK
are synchronous to SCKI. LRCK is operated at the sampling frequency, f . BCK can be operated at 64 times the sampling
S
frequency.
The PCM1770 and PCM1771 devices operate under LRCK synchronized with the system clock. The PCM1770 and
PCM1771 devices do not need a specific phase relationship between LRCK and the system clock, but do require the
synchronization of LRCK and the system clock. If the relationship between the system clock and LRCK changes more than
3BCK during one sample period, internal operation of the PCM1770 and PCM1771 devices halt within 1/f , and the analog
S
output is kept in last data until resynchronization between system clock and LRCK is completed.
AUDIO DATA FORMATS AND TIMING
2
The PCM1770 device supports industry-standard audio data formats, including standard, I S, and left justified. The
2
PCM1771 device supports the I S and left-justified data formats. Table 2 lists the main features of the audio data interface.
Figure 22 shows the data formats. Data formats are selected using the format bits, FMT[2:0] of control register 3 in case
of the PCM1770 device, and are selected using the FMT terminal in case of the PCM1771 device. The default data format
is 24-bit, left-justified, slave mode. All formats require binary 2s complement, MSB-first audio data. Figure 23 shows a
detailed timing diagram for the serial audio interface in slave mode. Figure 24 shows a detailed timing diagram for the serial
audio interface in master mode.
Table 2. Audio Data Interface
AUDIO-DATA INTERFACE FEATURE
CHARACTERISTIC
2
Standard, I S, left justified
(PCM1770)
Audio data interface format
(PCM1771)
2
I S, left justified
Audio data bit length
Audio data format
16-, 20-, 24-bits selectable
MSB first, 2s complement
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(1) Standard Data Format; L-Channel = High, R-Channel = Low (Slave Mode)
1/f
S
LRCK
R-Channel
L-Channel
BCK
(= 32 f , 48 f or 64 f )
S
S
S
16-Bit Right-Justified, BCK = 32 f
S
DATA 14 15 16
1
2
3
14 15 16
1
2
3
14 15 16
LSB
MSB
MSB
LSB
16-Bit Right-Justified, BCK = 48 f or 64 f
S
S
1
2
3
DATA 14 15 16
1
2
3
14 15 16
LSB
14 15 16
LSB
MSB
MSB
20-Bit Right-Justified
DATA 18 19 20
1
2
3
18 19 20
LSB
1
2
3
18 19 20
LSB
MSB
MSB
24-Bit Right-Justified
DATA 22 23 24
1
2
3
22 23 24
LSB
1
2
3
22 23 24
LSB
MSB
MSB
2
(2) I S Data Format; L-Channel = Low, R-Channel = High (Slave Mode)
1/f
S
LRCK
BCK
L-Channel
R-Channel
(= 32 f , 48 f or 64 f
)
S
S
S
DATA
1
2
3
N−2 N−1
N
1
2
3
N−2 N−1
N
1
2
MSB
LSB
MSB
LSB
(3) Left-Justified Data Format; L-Channel = High, R-Channel = Low (Slave Mode)
1/f
S
LRCK
BCK
L-Channel
R-Channel
(= 32 f , 48 f or 64 f
)
S
S
S
DATA
1
2
3
N−2 N−1
N
1
2
3
N−2 N−1
N
1
2
MSB
LSB
MSB
LSB
(4) Left-Justified Data Format; L-Channel = High, R-Channel = Low (Master Mode)
(The frequency of BCK is 64f and SCKI is 256f only)
S
S
1/f
S
LRCK
BCK
L-Channel
R-Channel
(= 64 f
)
S
DATA
1
2
3
N−2 N−1
N
1
2
3
N−2 N−1
N
1
2
MSB
LSB
MSB
LSB
Figure 22. Audio Data Input Formats
17
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50% of V
SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
LRCK (Input)
CC
t
(BCL)
t
t
(BCH)
(LB)
50% of V
BCK (Input)
CC
CC
t
t
t
(BCY)
(BL)
50% of V
DATA
t
(DS)
(DH)
PARAMETERS
SYMBOL
MIN
MAX
UNIT
(1)
BCK pulse cycle time
BCK high-level time
BCK low-level time
t
1/(64f )
S
(BCY)
t
35
35
10
10
10
10
ns
ns
ns
ns
ns
ns
(BCH)
t
(BCL)
BCK rising edge to LRCK edge
LRCK edge to BCK rising edge
DATA set-up time
t
t
(BL)
(LB)
t
(DS)
(DH)
DATA hold time
t
(1)
f
S
is the sampling frequency.
Figure 23. Audio Interface Timing (Slave Mode)
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
t
(SCY)
50% of V
CC
SCKI
t
(DL)
50% of V
CC
LRCK (Output)
BCK (Output)
DATA
t
(BCL)
t
t
t
(BCH)
(DB)
(DB)
50% of V
CC
t
(BCY)
50% of V
CC
t
(DS)
t
(DH)
PARAMETERS
SYMBOL
MIN
MAX
UNIT
(1)
1/(256f )
S
SCKI pulse cycle time
t
(SCY)
LRCK edge from SCKI rising edge
BCK edge from SCKI rising edge
BCK pulse cycle time
BCK high-level time
t
0
0
40
40
ns
ns
(DL)
(DB)
t
(1)
t
1/(64 f )
S
(BCY)
(BCH)
t
146
146
10
ns
ns
ns
ns
BCK low-level time
t
(BCL)
DATA set-up time
t
(DS)
DATA hold time
t
10
(DH)
(1) f is up to 48 kHz. f is the sampling frequency.
S
S
Figure 24. Audio Interface Timing (Master Mode)
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
HARDWARE CONTROL (PCM1771)
The digital functions of the PCM1771 device are capable of hardware control. Table 3 shows selectable formats, Table 4
shows de-emphasis control, and Table 5 shows analog mixing control.
Table 3. Data Format Select
FMT
Low
High
DATA FORMAT
16- to 24-bit, left-justified format
2
16- to 24-bit, I S format
Table 4. De-Emphasis Control
DEMP
Low
DE-EMPHASIS FUNCTION
44.1-kHz de-emphasis OFF
44.1-kHz de-emphasis ON
High
Table 5. Analog Mixing Control
AMIX
Low
ANALOG MIXING
Analog mixing OFF
Analog mixing ON
High
SOFTWARE CONTROL (PCM1770)
The PCM1770 device has many programmable functions that can be controlled in the software control mode. The functions
are controlled by programming the internal registers using MS, MC, and MD.
The software control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. The serial
control interface is used to program the on-chip mode registers. MD is the serial data input, used to program the mode
registers. MC is the serial bit clock, used to shift data into the control port. MS is the mode control port select signal.
REGISTER WRITE OPERATION (PCM1770)
All write operations for the serial control port use 16-bit data words. Figure 25 shows the control data word format. The most
significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register index (or address) for the write
operation. The eight least significant bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].
Figure 26 shows the functional timing diagram for writing to the serial control port. To write data into the mode register, data
is clocked into an internal shift register on the rising edge of the MC clock. Serial data can change on the falling edge of
the MC clock and must be stable on the rising edge of the MC clock. The MS signal must be low during the write mode
and the rising edge of the MS signal must be aligned with the falling edge of the last MC clock pulse in the 16-bit frame.
The MC clock can run continuously between transactions while the MS signal is low.
LSB
D0
MSB
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
Register Index (or Address)
D7
D6
D5
D4
D3
D2
D1
Register Data
Figure 25. Control Data Word Format for MD
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
(1) Single Write Operation
16-Bits
MS
MC
MD
MSB
LSB
MSB
(2) Continuous Write Operation
16-Bits x N Frames
MS
MC
MD
MSB
LSB
MSB
LSB
MSB
LSB
N Frames
Figure 26. Register Write Operation
CONTROL INTERFACE TIMING REQUIREMENTS (PCM1770)
Figure 27 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper
control port operation.
t
(MHH)
MS
50% of V
CC
t
t
(MCL)
(MLS)
t
t
(MLH)
(MCH)
MC
MD
50% of V
50% of V
CC
t
(MCY)
LSB
CC
t
(MDS)
t
(MDH)
PARAMETERS
SYMBOL
MIN
(1)
TYP
MAX UNITS
MC pulse cycle time
MC low-level time
MC high-level time
MS high-level time
t
100
50
ns
ns
ns
ns
ns
ns
ns
ns
(MCY)
t
(MCL)
t
t
50
(2)
20
20
15
20
(MCH)
(MHH)
MS falling edge to MC rising edge
MS hold time
t
(MLS)
(MLH)
(MDH)
t
MD hold time
t
MD set-up time
t
(MDS)
(1) When MC runs continuously between transactions, MC pulse cycle time is specified as 3/(128f ), where f is sampling rate.
S
S
(2) 3/(128f ) s (min), where f is sampling rate.
S
S
Figure 27. Control Interface Timing
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
MODE CONTROL REGISTERS (PCM1770)
User-Programmable Mode Controls
The PCM1770 device has a number of user- programmable functions that can be accessed via mode control registers.
The registers are programmed using the serial control interface, as discussed in the SOFTWARE CONTROL (PCM1770)
section. Table 6 lists the available mode control functions, along with their reset default conditions and associated register
index.
Register Map
Table 7 shows the mode control register map. Each register includes an index (or address) indicated by the IDX[6:0] bits.
Table 6. User-Programmable Mode Controls
FUNCTION
Soft mute control, L/R independently
RESET DEFAULT
Disabled
REGISTER NO.
BIT(S)
01
MUTL, MUTR
ATL[5:0], ATR[5:0]
Digital attenuation level setting, 0 dB to –63 dB in 1-dB steps, L/R
independently
0 dB
01, 02
Oversampling rate control (128 f , 192 f , 256 f , 384 f )
128 f oversampling
S
03
03
03
03
03
04
04
OVER
RINV
S
S
S
S
Polarity control for analog output for R-channel DAC
Analog mixing control for analog in, AIN (terminal 14)
44.1-kHz de-emphasis control
Not inverted
Disabled
AMIX
Disabled
DEM
Audio data format select
24-bit, left-justified format
Disabled
FMT[2:0]
ZCAT
Zero cross attenuation
Power down control
Disabled
PWRD
Table 7. Mode Control Register Map
REGISTER
IDX [6:0]
B15 B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(B14–B8)
Register 01
Register 02
Register 03
Register 04
01h
02h
03h
04h
0
0
0
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUTR MUTL ATL5 ATL4 ATL3 ATL2
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV
ATL1
ATL0
ATR0
RSV ATR5 ATR4 ATR3 ATR2 ATR1
RINV AMIX DEM FMT2 FMT1 FMT0
RSV ZCAT RSV
RSV
RSV PWRD
NOTE: RSV: Reserved for test operation. It must be set to 0 during regular operation.
Register Definitions
B15 B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 01
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUTR MUTL ATL5 ATL4 ATL3 ATL2 ATL1 ATL0
IDX[6:0]: 000 0001b
MUTx: Soft Mute Control
Where, x = L or R, corresponding to the headphone output H
Default Value: 0
L and H
R.
OUT
OUT
MUTL, MUTR = 0
MUTL, MUTR = 1
Mute disabled (default)
Mute enabled
The mute bits, MUTL and MUTR, enable or disable the soft mute function for the corresponding headphone
outputs, H L and H R. The soft mute function is incorporated into the digital attenuators. When mute is
OUT
OUT
disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the
digital attenuator for the corresponding output are decreased from the current setting to the infinite attenuation,
one attenuator step (1 dB) at a time. This provides pop-free muting of the headphone output.
By setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuation
level.
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
ATL[5:0]: Digital Attenuation Level Setting for Headphone Output, H
L
OUT
Default value: 11 1111b
Headphone output, H
L includes a digital attenuation function. The attenuation level can be set from 0 dB to
OUT
–62 dB, in 1.0-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step
(1.0 dB) for every 8/f time internal until the programmed attenuator setting is reached. Alternatively, the
S
attenuation level may be set to infinite attenuation (or mute).
The following table shows the attenuation levels for various settings:
ATL[5:0]
11 1111b
11 1110b
11 1101b
ꢀ
ATTENUATION LEVEL SETTING
0 dB, no attenuation (default)
–1.0 dB
–2.0 dB
ꢀ
00 0010b
00 0001b
00 0000b
–61.0 dB
–62.0 dB
Mute
B15 B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 02
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
RSV ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
IDX[6:0]: 000 0010b
ATR[5:0]: Digital Attenuation Level Setting for Headphone Output, H
R
OUT
Default Value: 11 1111b
Headphone output, H
R includes a digital attenuation function. The attenuation level can be set from 0 dB to
OUT
–62 dB, in 1-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1.0
dB) for every 8/f time internal until the programmed attenuator setting in reached. Alternatively, the attenuation
S
level can be set to infinite attenuation (or mute).
To set the attenuation levels for ATR[5:0], see the table for ATL[5:0], register 01.
B15 B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 03
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV
RINV AMIX DEM FMT2 FMT1 FMT0
IDX[6:0]: 000 0011b
OVER: Over Sampling Control
Default Value: 0
OVER = 0
OVER = 1
128 f oversampling
S
192 f , 256 f , 384 f oversampling
S
S
S
The OVER bit controls the oversampling rate of the ∆-Σ D/A converters. When it operates at a low sampling rate,
less than 24 kHz, this function is recommended.
RINV: Polarity Control for Headphone Output, H
R
OUT
Default Value: 0
RINV = 0
RINV = 1
Not inverted
Inverted output
The RINV bits allow the user to control the polarity of the headphone output, H
R. This function can be used to
OUT
connect the monaural speaker with BTL connection method. This bit is recommended to be 0 during the
power-up/-down sequence for minimizing audible pop noise.
23
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
AMIX: Analog Mixing Control for External Analog Signal, AIN
Default Value: 0
AMIX = 0
AMIX = 1
Disabled (not mixed)
Enabled (mixing to the DAC output)
AMIX bit allows the user to mix analog input (AIN) with headphone outputs (H
DEM: 44.1-kHz De-emphasis Control
L/H
R) internally.
OUT
OUT
Default Value: 0
DEM = 0
DEM = 1
Disabled
Enabled
The DEM bit enables or disables the digital de-emphasis filter for 44.1-kHz sampling rate.
FMT[2:0]: Audio Interface Data Format
Default Value: 000
The FMT[2:0] bits select the data format for the serial audio interface. The following table shows the available
format options.
FMT[2:0]
Audio Data Format Selection
000
001
010
011
100
101
110
111
16- to 24-bit, left-justified format (default)
2
16- to 24-bit, I S format
24-bit right-justified data
20-bit right-justified data
16-bit right-justified data
16- to 24-bit, left-justified format, master mode
Reserved
Reserved
B15 B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 04
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
RSV
RSV ZCAT RSV
RSV RSV PWRD
IDX[6:0]: 000 0100b
ZCAT: Zero Cross Attenuation
Default Value: 0
ZCAT = 0
ZCAT = 1
Normal attenuation (default)
Zero cross attenuation
This bit enables the change signal level on zero crossing during attenuation control or muting. If the signal does
not cross BPZ beyond 512/f (11.6 ms at 44.1-kHz sampling rate), the signal level is changed similar to normal
S
attenuation control. This function is independently monitored for each channel; moreover, change of signal level
is alternated between both channels. Figure 28 shows an example of zero cross attenuation.
24
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
ATT CTRL START
L-Channel
(1.5 kHz)
R-Channel
(1 kHz)
Level Change Point
Figure 28. Example of Zero Cross Attenuation
PWRD: Power Down Control
Default Value: 0
PWRD = 0
PWRD = 1
Normal operation (default)
Power-down state
This bit is used to enter into low-power mode. Note that PWRD has no reset function.
When this bit is set to 1, the PCM1770 device enters low-power mode and all digital circuits are reset except the
register states which remain unchanged.
ANALOG IN/OUT
HEADPHONE OUTPUT (STEREO)
The PCM1770 and PCM1771 devices have two independent headphone amplifiers, and each amplifier output is provided
at the H
L and H
R terminals. Because the capability of the headphone output is designed for driving a 16-Ω
OUT
OUT
impedance headphone, less than a 16-Ω impedance headphone is not recommended. A resistor and a capacitor must be
connected to H L and H R to ensure proper output loading.
OUT
OUT
Monaural Output (BTL Mode/Monaural Speaker)
The monaural output can be created by summing left and right headphone outputs. When in the BTL mode, the user must
set each headphone output levels to −3 dB using ATL[5:0] bits on register 01 and ATR[5:0] bits on register 02. Moreover,
invert the polarity of the right headphone output by using the RINV bit on control register 03. The RINV bit is recommended
to be 0 during power-up/-down sequence for minimizing audible pop noise.
Analog Input
The PCM1770 and PCM1771 devices have an analog input, AIN (terminal 10). The AMIX bit (PCM1770) or the AMIX
terminal (PCM1771) allows the user to mix AIN with the headphone outputs (H
L and H
R) internally. When in the
OUT
OUT
MIXING mode, an ac-coupling capacitor is needed for AIN. But if AIN is not used, AIN must be open and the AMIX bit
(PCM1770) must be disabled or the AMIX terminal (PCM1771) must be low.
Because AIN does not have an internal low-pass filter, it is recommended that the bandwidth of the input signal into AIN
is limited to less than 100 kHz. The source of signals connected to AIN must be connected by low impedance.
Although the maximum input voltage on AIN is designed to be as large as 0.584 V [peak-to-peak], the user must attenuate
HP
the input voltage on AIN and control digital input data so that each headphone output (H
L and H
R) does not exceed
OUT
OUT
0.55 V [peak-to-peak] during mixing mode.
HP
V
Output
COM
One unbuffered common-mode voltage output terminal, V
is brought out for decoupling purposes. This terminal is
COM,
nominally biased to a dc voltage level equal to 0.5V and connected to a 10-µF capacitor. In the case of a capacitor smaller
HP
than 10 µF, pop noise can be generated during the power-on/-off or power-up/-down sequences.
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SLES011C – SEPTEMBER 2001 – REVISED MAY 2004
APPLICATION INFORMATION
CONNECTION DIAGRAMS
Figure 29 shows the basic connection diagram with the necessary power supply bypassing and decoupling components.
It is recommended that the component values shown in Figure 29 be used for all designs.
The use of series resistors (22 Ω to 100 Ω) are recommended for the MCKI, LRCK, BCK, and DATA inputs. The series
resistor combines with the stray PCB and device input capacitance to form a low-pass filter that reduces high frequency
noise emissions and helps to dampen glitches and ringing present on the clock and data lines.
POWER SUPPLIES AND GROUNDING
The PCM1770 and PCM1771 devices require a 2.4-V typical analog supply for V and V . These 2.4-V supplies power
CC
HP
the DAC, analog output filter, and other circuits. For best performance, these 2.4-V supplies must be derived from the
analog supply using a linear regulator, as shown in Figure 29.
Figure 29 shows the proper power supply bypassing. The 10-µF capacitors must be tantalum or aluminum electrolytic,
while the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount applications).
1.6 V to 3.6 V
LRCK
DATA
BCK
SCKI
MS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Audio DSP
Controller
MC
PD
MD
PCM1770
AGND
HGND
V
CC
10 µF
10 µF
V
HP
10 µF
V
COM
AIN
Analog In
H
OUT
R
H
L
OUT
10 µF
220 µF
0.022 µF
16 Ω
220 µF
Headphone
= 16 Ω
R
L
0.022 µF
16 Ω
Figure 29. Basic Connection Diagram
26
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MPQF110 − SEPTEMBER 2001
RGA (S-PQFP-N20)
PLASTIC QUAD FLATPACK
4,30
4,10
4,05
3,95
0,50 NOM/2
A
“A”
B
4,30
4,10
DETAIL “A”
4,05
3,95
0,50 NOM
1,00 NOM
20
“C”
0,25
0,09
0,95
0,50
1,00
MAX
1
S
C0,70
0,50 NOM
Index
1,00 NOM
0,75
0,45
0,05
0,00
S
S
0,05
DETAIL “B”
“B”
0,27
0,17
M
S AB
0,05
0,21
0,09
0,05
0,00
0,25
0,09
0,35 0,11
0,23
0,17
0,27
0,17
0,69 0,11
DETAIL “C”
0,22 0,05
4202802/B 08/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. These dimensions include package bend.
D. Falls within EIAJ: EDR-7324.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dsp.ti.com
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Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
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www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
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Wireless
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
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