PCM1771RGARG4_技术文档

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PCM1770, PCM1771

SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

LOW-VOLTAGE AND LOW-POWER STEREO AUDIO DIGITAL-TO-ANALOG CONVERTER

WITH HEADPHONE AMPLIFIER

FEATURES

APPLICATIONS

•

Portable Audio Player

Cellular Phone

PDA

Other Applications Requiring Low-Voltage

Operation

•

Multilevel DAC Including Headphone Amplifier

•

Analog Performance (V_CC, V_HP= 2.4 V):

–

Dynamic Range: 98 dB Typ

THD+N at 0 dB: 0.1% Typ

THD+N at –20 dB: 0.04% Typ

Output Power at R_L= 16 Ω: 13 mW

DESCRIPTION

(Stereo), 26 mW (Monaural)

The PCM1770 and PCM1771 devices are CMOS,

monolithic, integrated circuits which include stereo

digital-to-analog converters, headphone circuitry, and

support circuitry in small TSSOP-16 and VQFN-20

packages.

•

1.6-V to 3.6-V Single Power Supply

Low Power Dissipation: 6.5 mW at V_CC, V_HP

2.4 V

=

•

System Clock: 128 f_S, 192 f_S, 256 f_S, 384 f_S

Sampling Frequency: 5 kHz to 50 kHz

Software Control (PCM1770):

The data converters use TI's enhanced multilevel ∆-Σ

architecture, which employs noise shaping and

multilevel amplitude quantization to achieve excellent

dynamic performance and improved tolerance to

clock jitter. The PCM1770 and PCM1771 devices

accept several industry standard audio data formats

with 16- to 24-bit data, left-justified, I²S, etc.,

providing easy interfacing to audio DSP and decoder

devices. Sampling rates up to 50 kHz are supported.

–

16-, 20-, 24-Bit Word Available

Left-, Right-Justified, and I²S

Slave/Master Selectable

Digital Attenuation: 0 dB to –62 dB, 1

dB/Step

A

full set of user-programmable functions is

–

44.1-kHz Digital De-Emphasis

Zero Cross Attenuation

Digital Soft Mute

accessible through a 3-wire serial control port, which

supports register write functions.

Monaural Analog-In With Mixing

Monaural Speaker Mode

•

Hardware Control (PCM1771):

–

Left-Justified and I²S

44.1-kHz Digital De-Emphasis

Monaural Analog-In With Mixing

•

Pop-Noise-Free Circuit

3.3-V Tolerant

Packages: TSSOP-16 and VQFN-20

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PCM1770, PCM1771

www.ti.com

SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

PCM1770

PCM1771

Supply voltage: V_CC, V_HP

–0.3 V to 4 V

±0.1 V

Supply voltage differences: V_CC, V_HP

Ground voltage differences

Digital input voltage

±0.1 V

–0.3 V to 4 V

±10 mA

Input current (any terminals except supplies)

Operating temperature

–40°C to 125°C

–55°C to 150°C

150°C

Storage temperature

Junction temperature

Lead temperature (soldering)

Package temperature (IR reflow, peak)

260°C, 5 s

260°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range

MIN

NOM

2.4

MAX

UNIT

Supply voltage: V_CC, V_HP

Digital input logic family

1.6

3.6

V

CMOS

System clock

0.64

5

19.2

50

MHz

kHz

Ω

Digital input clock frequency

Sampling clock

Analog output load resistance

Analog input level (V_HP= 2.4 V)

Operating free-air temperature, T_A

16

1.4

85

Vp-p

°C

–25

2

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SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

ELECTRICAL CHARACTERISTICS

all specifications at T_A= 25°C, V_CC= V_HP= 2.4 V, f_S= 44.1 kHz, system clock = 256 f_Sand 24-bit data, R_L= 16 Ω, unless

otherwise noted

PCM1770PW, PCM1771PW,

PCM1770RGA, PCM1771RGA

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

Resolution

24

Bits

OPERATING FREQUENCY

Sampling frequency (f_S)

System clock frequency

DIGITAL INPUT/OUTPUT⁽¹⁾⁽²⁾

5

50

kHz

128f _S, 192 f_S, 256 f_S, 384 f_S

Logic family

CMOS compatible

V_IH

V_IL

I_IH

0.7 V_CC

0.3 V_CC

10

VDC

µA

Input logic level

V_IN= V_CC

V_IN= 0 V

Input logic current

Output logic level⁽³⁾

I_IL

–10

µA

V_OH

V_OL

I_OH= –2 mA

I_OL= 2 mA

0.7 V_CC

VDC

0.3 V_CC

DYNAMIC PERFORMANCE (HEADPHONE OUTPUT)

Full-scale output voltage

Dynamic range

0 dB

0.55 V_HP

Vp-p

dB

EIAJ, A-weighted

0 dB (13 mW)

–20 dB (0.1 mW)

Stereo

90

98

Signal-to-noise ratio

dB

0.1%

0.04%

13

THD+N

Total harmonic distortion + noise

Output power

0.1%

10

20

64

14

mWrms

dB

Monaural

26

Channel separation

Load resistance

72

16

Ω

DC ACCURACY

Gain error

±2

±8

%FSR

mV

Gain mismatch,

channel-to-channel

Bipolar zero error

ANALOG LINE INPUT (MIXING CIRCUIT)

Analog input voltage range

V_OUT= 0.5 V_CCat BPZ

±30

±75

0.584 V_HP

Vp-p

Gain (analog input to headphone

output)

0.67

Analog input impedance

10

kΩ

THD+N

Total harmonic distortion + noise AIN = 0.56 V_HP(peak-to-peak)

0.1%

DIGITAL FILTER PERFORMANCE

Pass band

0.454 f_S

±0.04

Stop band

0.546 f_S

–50

Pass-band ripple

dB

Stop-band attenuation

Group

delay

20/f_S

±0.1

44.1-kHz de-emphasis error

dB

ANALOG FILTER PERFORMANCE

(1) Digital inputs and outputs are CMOS compatible.

(2) All logic inputs are 3.3-V tolerant and not terminated internally.

(3) LRCK and BCK terminals

3

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SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

ELECTRICAL CHARACTERISTICS (continued)

all specifications at T_A= 25°C, V_CC= V_HP= 2.4 V, f_S= 44.1 kHz, system clock = 256 f_Sand 24-bit data, R_L= 16 Ω, unless

otherwise noted

PCM1770PW, PCM1771PW,

PCM1770RGA, PCM1771RGA

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

Frequency response

POWER SUPPLY REQUIREMENTS

Voltage range, V_CC, V_HP

I_CC

at 20 kHz

±0.2

dB

1.6

2.4

1.5

1.2

5

3.6

2.5

15

VDC

mA

BPZ input

Power down⁽⁴⁾

I_HP

Supply current

I_CC+ I_HP

µA

mW

µW

BPZ input

Power down⁽⁴⁾

6.5

12

Power dissipation

36

TEMPERATURE RANGE

Operation temperature

–25

85

°C

PCM1770PW, -71PW: 16-terminal TSSOP

PCM1770RGA, -71RGA: 20-terminal VQFN

150

130

θ_JA

Thermal resistance

°C/W

(4) All input signals are held static.

4

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SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

PIN ASSIGNMENTS

PCM1770

PW PACKAGE

(TOP VIEW)

PCM1771

PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LRCK

DATA

BCK

PD

AGND

HGND

SCKI

LRCK

DATA

BCK

PD

AGND

HGND

SCKI

FMT

AMIX

DEMP

MS

MC

MD

V

CC

HP

V

COM

AIN

V

COM

AIN

H R

OUT

H

OUT

L

H R

OUT

H

OUT

L

P0001-02

PCM1770

RGA PACKAGE

(TOP VIEW)

PCM1771

RGA PACKAGE

(TOP VIEW)

20 19 18 17 16

15

20 19 18 17 16

1

2

3

4

5

15

FMT

DATA

BCK

MS

MC

MD

DATA

BCK

2

3

4

5

14

13

12

11

14

13

12

11

AMIX

DEMP

PD

V

CC

V

CC

AGND

HGND

AGND

HGND

V

HP

V

HP

6

7

8

9

10

6

7

8

9 10

NC − No internal connection

P0002-02

5

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SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

TERMINAL FUNCTIONS

PCM1770PW

TERMINAL

I/O

DESCRIPTION

NAME

AGND

AIN

NO.

5

–

I

Analog ground. This is a return for V_CC

.

10

3

Monaural analog signal mixer input. The signal can be mixed with the outputs of the L- and R-channel DACs.

BCK

I/O Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock

is input from an external device. In the master interface mode, the PCM1770 device generates the BCK output

to an external device.

DATA

2

6

9

8

1

I

Serial audio data input

HGND

–

Analog ground. This is a return for V_HP.

H_OUT

L

O

L-channel analog signal output of the headphone amplifiers

R-channel analog signal output of the headphone amplifiers

R

LRCK

I/O Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of

LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an

external device. In the master interface mode, the PCM1770 device generates the LRCK output to an external

device.

MC

MD

MS

PD

14

13

15

4

I

Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.

Mode control port serial data input. Controls the operation mode on the PCM1770 device.

Mode control port select. The control port is active when this terminal is low.

Reset input. When low, the PCM1770 device is powered down, and all mode control registers are reset to

default settings.

SCKI

V_CC

16

12

7

I

System clock input

–

Power supply for all analog circuits except the headphone amplifier.

V_COM

Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is

required for noise filtering. Voltage level of this terminal is 0.5 V_HPnominal.

V_HP

11

–

Analog power supply for the headphone amplifier circuits. The voltage level must be the same as V_CC.

6

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SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

TERMINAL FUNCTIONS (CONTINUED)

PCM1770RGA

TERMINAL

I/O

DESCRIPTION

NAME

AGND

AIN

NO.

4

–

I

Analog ground. This is a return for V_CC

.

10

2

Monaural analog signal mixer input. The signal can be mixed with the outputs of the L- and R-channel DACs.

BCK

I/O Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock

is input from an external device. In the master interface mode, the PCM1770 device generates the BCK output

to an external device.

DATA

1

5

I

Serial audio data input

HGND

–

Analog ground. This is a return for V_HP.

H_OUT

L

9

O

L-channel analog signal output of the headphone amplifiers

R-channel analog signal output of the headphone amplifiers

R

7

LRCK

20

I/O Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of

LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an

external device. In the master interface mode, the PCM1770 device generates the LRCK output to an external

device.

MC

MD

MS

NC

14

13

15

I

Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.

Mode control port serial data input. Controls the operation mode on the PCM1770 device.

Mode control port select. The control port is active when this terminal is low.

No connect

I

8, 17,

–

18, 19

PD

3

I

Reset input. When low, the PCM1770 device is powered down, and all mode control registers are reset to

default settings.

SCKI

V_CC

16

12

6

I

System clock input

–

Power supply for all analog circuits except the headphone amplifier.

V_COM

Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is

required for noise filtering. Voltage level of this terminal is 0.5 V_HPnominal.

V_HP

11

–

Analog power supply for the headphone amplifier circuits. The voltage level must be the same as V_CC.

7

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SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

TERMINAL FUNCTIONS (CONTINUED)

PCM1771PW

TERMINAL

I/O

DESCRIPTION

NAME

AGND

AIN

NO.

5

–

I

Analog ground. This is a return for V_CC.

10

14

3

Monaural analog signal mixer input. The signal can be mixed with the outputs of the L- and R-channel DACs.

AMIX

BCK

Analog mixing control

I

Serial bit clock. Clocks the individual bits of the audio data input, DATA.

DATA

DEMP

FMT

2

I

Serial audio data input

De-emphasis control

Data format select

13

15

6

I

HGND

–

O

I

Analog ground. This is a return for V_HP.

H_OUT

L

9

L-channel analog signal output of the headphone amplifiers

R-channel analog signal output of the headphone amplifiers

R

8

LRCK

1

Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of

LRCK must be the same as the audio sampling rate.

PD

4

I

Reset input. When low, the PCM1771 device is powered down, and all mode control registers are reset to

default settings.

SCKI

V_CC

16

12

7

I

System clock input

–

Power supply for all analog circuits except the headphone amplifier.

V_COM

Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is

required for noise filtering. Voltage level of this terminal is 0.5 V_HPnominal.

V_HP

11

–

Analog power supply for the headphone amplifier circuits. The voltage level must be the same as V_CC.

PCM1771RGA

TERMINAL

I/O

DESCRIPTION

NAME

AGND

AIN

NO.

4

–

I

Analog ground. This is a return for V_CC.

10

14

2

Monaural analog signal mixer input. The signal can be mixed with the outputs of the L- and R-channel DACs.

AMIX

BCK

Analog mixing control

I

Serial bit clock. Clocks the individual bits of the audio data input, DATA.

DATA

DEMP

FMT

1

I

Serial audio data input

De-emphasis control

Data format select

13

15

5

I

HGND

–

O

I

Analog ground. This is a return for V_HP.

H_OUT

L

9

L-channel analog signal output of the headphone amplifiers

R-channel analog signal output of the headphone amplifiers

R

7

LRCK

20

Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of

LRCK must be the same as the audio sampling rate.

NC

8, 17,

18, 19

–

I

No connect

PD

3

Reset input. When low, the PCM1771 device is powered down, and all mode control registers are reset to

default settings.

SCKI

V_CC

16

12

6

I

System clock input

–

Power supply for all analog circuits except the headphone amplifier

V_COM

Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is

required for noise filtering. Voltage level of this terminal is 0.5 V_HPnominal.

V_HP

11

–

Analog power supply for the headphone amplifier circuits. The voltage level must be the same as V_CC.

8

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SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

FUNCTIONAL BLOCK DIAGRAM

AIN

Digital

Attenuator

Headphone

Amplifier

LRCK

DATA

× 8

Digital

Filter

Audio

Interface

∆Σ

+

H

R

OUT

DAC

BCK

V

COM

V

COM

(FMT) MS

(AMIX) MC

(DEMP) MD

× 8

Digital

Filter

SPI

Port

∆Σ

DAC

H

OUT

L

Clock Manager

Power Supply

SCKI

PD

V

CC

V

HP

AGND

HGND

( ) : PCM1771

B0001-02

TYPICAL PERFORMANCE CURVES

All specifications at T_A= 25°C, V_CC= V_HP2.4 V, f_S= 44.1 kHz, system clock = 256 f_S, 24-bit data, and R_L= 16 Ω, unless

otherwise noted.

Digital Filter

Digital Filter (De-Emphasis Off)

AMPLITUDE

vs

FREQUENCY

AMPLITUDE

vs

FREQUENCY

0

−20

0.05

0.04

0.03

−40

0.02

0.01

−60

0.00

−80

−0.01

−0.02

−0.03

−0.04

−0.05

−100

−120

−140

0

1

2

3

4

0.0

0.1

0.2

0.3

0.4

0.5

f – Frequency [ꢀ f ]

S

G001

G002

Figure 1.

Figure 2.

9

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SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

TYPICAL PERFORMANCE CURVES (continued)

All specifications at T_A= 25°C, V_CC= V_HP2.4 V, f_S= 44.1 kHz, system clock = 256 f_S, 24-bit data, and R_L= 16 Ω, unless

otherwise noted.

De-Emphasis Curves

DE-EMPHASIS LEVEL

vs

DE-EMPHASIS ERROR

vs

FREQUENCY

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

0.5

0.4

0.3

0.2

0.1

0.0

−0.1

−0.2

−0.3

−0.4

−0.5

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0

2

4

6

8

10 12 14 16 18 20

f – Frequency [ꢀ f ]

f – Frequency – kHz

S

G003

G004

Figure 3.

Figure 4.

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE

vs

SUPPLY VOLTAGE

vs

SUPPLY VOLTAGE

1.00

104

102

100

98

1

0 dB

0.10

0.1

–20 dB

96

94

0.01

92

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

V

CC

– Supply Voltage – V

V

CC

– Supply Voltage – V

G005

G006

Figure 5.

Figure 6.

10

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TYPICAL PERFORMANCE CURVES (continued)

All specifications at T_A= 25°C, V_CC= V_HP2.4 V, f_S= 44.1 kHz, system clock = 256 f_S, 24-bit data, and R_L= 16 Ω, unless

otherwise noted.

SIGNAL-TO-NOISE RATIO

vs

CHANNEL SEPARATION

vs

SUPPLY VOLTAGE

104

102

100

98

78

76

74

72

70

68

66

96

94

92

1.2

1.6

2.0

V

2.4

2.8

3.2

3.6

4.0

1.6

2.0

V

2.4

2.8

3.2

3.6

4.0

– Supply Voltage – V

CC

G008

G007

Figure 7.

Figure 8.

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE

vs

FREE-AIR TEMPERATURE

vs

FREE-AIR TEMPERATURE

1.00

1

102

101

100

99

0 dB

0.10

0.1

98

97

–20 dB

96

95

94

−40

0.01

−40

−20

0

20

40

60

80

100

−20

0

20

40

60

80

100

T – Free-Air Temperature – °C

A

T – Free-Air Temperature – °C

A

G009

G010

Figure 9.

Figure 10.

11

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TYPICAL PERFORMANCE CURVES (continued)

All specifications at T_A= 25°C, V_CC= V_HP2.4 V, f_S= 44.1 kHz, system clock = 256 f_S, 24-bit data, and R_L= 16 Ω, unless

otherwise noted.

SIGNAL-TO-NOISE RATIO

vs

FREE-AIR TEMPERATURE

CHANNEL SEPARATION

vs

FREE-AIR TEMPERATURE

102

101

100

99

76

75

74

73

72

71

70

69

68

98

97

96

95

94

−40

−20

0

20

40

60

80

100

−40

−20

0

20

40

60

80

100

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

G011

G012

Figure 11.

Figure 12.

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

SUPPLY CURRENT

vs

SAMPLING FREQUENCY

20

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

18

16

14

12

10

8

18

16

14

12

10

8

Operational

Power Down

6

Power Down

4

2

4

2

0

10

20

30

40

50

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

f

S

– Sampling Frequency – kHz

V

CC

– Supply Current – V

G014

G013

Figure 13.

Figure 14.

12

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TYPICAL PERFORMANCE CURVES (continued)

All specifications at T_A= 25°C, V_CC= V_HP2.4 V, f_S= 44.1 kHz, system clock = 256 f_S, 24-bit data, and R_L= 16 Ω, unless

otherwise noted.

DYNAMIC RANGE

vs

JITTER

100

99

98

97

96

95

94

0

100

200

300

400

500

600

700

Jitter – ps

G015

Figure 15.

OUTPUT SPECTRUM (-60 dB, N = 8192)

0

−20

0

−20

−40

−60

−80

−100

−120

−140

−100

−120

−140

0

5

10

15

20

0

20

40

60

80

100

120

f – Frequency – kHz

G016

G017

Figure 16.

Figure 17.

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DETAILED DESCRIPTION

System Clock, Reset, and Functions

System Clock Input

The PCM1770 and PCM1771 devices require a system clock for operating the digital interpolation filters and

multilevel ∆-Σ modulators. The system clock is applied at terminal 16 (SCKI). Table 1 shows examples of system

clock frequencies for common audio sampling rates.

Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to

use a clock source with low phase jitter and noise.

Table 1. System Clock Frequency for Common Audio Sampling Frequencies

SYSTEM CLOCK FREQUENCY, SCKI (MHz)

SAMPLING FREQUENCY, LRCK

128 f_S

6.144

5.6448

4.096

3.072

2.8224

2.048

1.536

1.4112

1.024

192 f_S

9.216

8.4672

6.144

4.608

4.2336

3.072

2.304

2.1168

1.536

256 f_S

12.288

11.2896

8.192

384 f_S

18.432

16.9344

12.288

9.216

48 kHz

44.1 kHz

32 kHz

24 kHz

6.144

22.05 kHz

16 kHz

5.6448

4.096

8.4672

6.144

12 kHz

3.072

4.608

11.025 kHz

8 kHz

2.8224

2.048

4.2336

3.072

t

(SCKH)

0.7 V

CC

SCKI

0.3 V

CC

t

(SCKL)

t

(SCKY)

T0005-02

PARAMETER

MIN

7

UNIT

t_(SCKH)

t_(SCKL)

t_(SCKY)

System clock pulse duration, HIGH

System clock pulse duration, LOW

System clock pulse cycle time⁽¹⁾

ns

7

52

(1) 1/(128 f_S), 1/(192 f_S), 1/(256 f_S) or 1/(384 f_S)

Figure 18. System Clock Timing

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Power On/Off Reset

The PCM1770/71 always must have the PD pin set from LOW to HIGH once after power-supply voltages V_CC

and V_HPhave reached the specified voltage range and stable clocks SCKI, BCK, and LRCK are being supplied

for the power-on sequence. A minimum time of 1 ms after both the clock and power-supply requirements are

met is required before the PD pin changes from LOW to HIGH, as shown in Figure 19. Subsequent to the PD

LOW-to-HIGH transition, the internal logic state is held in reset for 1024 system clock cycles prior to the start of

the power-on sequence. During the power-on sequence, H_OUTL and H_OUTR increase gradually from ground

leved, reaching an output level that corresponds to the input data after a period of 9334/f_S. When powering off,

the PD pin is set from HIGH to LOW first. Then H_OUTL and H_OUTR decrease gradually to ground level over a

period of 9334/f_S, as shown in Figure 20, after which power can be removed without creating pop noise. When

powering on or off, adhering to the timing requirements of Figure 19 and Figure 20 ensures that pop noise does

not occur. If the timing requirements are not met, pop noise might occur.

V , V

CC HP

0 V

1 ms (Min)

1024 Internal System Clocks

LRCK, BCK, SCKI

1 ms (Min)

PD

Internal Reset

9334/f

S

0 V

H L, H R

OUT OUT

T0006-02

Figure 19. Power-On Sequence

V , V

CC HP

0 V

LRCK, BCK, SCKI

9334/f

S

PD

H L, H R

OUT OUT

0 V

T0007-02

Figure 20. Power-Off Sequence

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Power-Up/-Down Sequence and Reset

The PCM1770 device has two kinds of power-up/-down methods: the PD terminal through hardware control and

PWRD (register 4, B0) through software control. The PCM1771 device has only the PD terminal through

hardware control for the power-up/-down sequence. The power-up or power-down sequence operates the same

as the power-on or power-off sequence. When powering up or down using the PD terminal, all digital circuits are

reset. When powering up or down using PWRD, all digital circuits are reset except for maintaining the logic

states of the registers. Figure 21 shows the power-up/power-down sequence.

2.4 V

V , V

CC HP

9334/f

S

LRCK, BCK, SCKI

PD

H L, H R

OUT OUT

0 V

T0008-02

Figure 21. Power-Down and Power-Up Sequences

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Audio Serial Interface

The audio serial interface for the PCM1770 and PCM1771 devices consists of a 3-wire synchronous serial port.

It includes terminals 1 (LRCK), 2 (DATA), and 3 (BCK). BCK is the serial audio bit clock, and it clocks the serial

data present on DATA into the audio interface serial shift register. Serial data is clocked into the PCM1770 and

PCM1771 devices on the rising edge of BCK. LRCK is the serial audio left/right word clock. It latches serial data

into the serial audio interface internal registers.

Both LRCK and BCK of the PCM1770 device support the slave and master modes, which are set by FMT

(register 3). LRCK and BCK are outputs during the master mode and inputs during the slave mode.

In slave mode, BCK and LRCK are synchronous to the audio system clock, SCKI. Ideally, it is recommended

that LRCK and BCK be derived from SCKI. LRCK is operated at the sampling frequency, f_S. BCK can be

operated at 32, 48, or 64 times the sampling frequency.

In master mode, BCK and LRCK are derived from the system clock and these terminals are outputs. BCK and

LRCK are synchronous to SCKI. LRCK is operated at the sampling frequency, f_S. BCK can be operated at 64

times the sampling frequency.

The PCM1770 and PCM1771 devices operate under LRCK synchronized with the system clock. The PCM1770

and PCM1771 devices do not need a specific phase relationship between LRCK and the system clock, but do

require the synchronization of LRCK and the system clock. If the relationship between the system clock and

LRCK changes more than ±3 BCK during one sample period, internal operation of the PCM1770 and PCM1771

devices halts within 1/f_S, and the analog output is kept in last data until resynchronization between system clock

and LRCK is completed.

Audio Data Formats and Timing

The PCM1770 device supports industry-standard audio data formats, including standard, I²S, and left-justified.

The PCM1771 device supports the I²S and left-justified data formats. Table 2 lists the main features of the audio

data interface. Figure 22 shows the data formats. Data formats are selected using the format bits, FMT[2:0] of

control register 3 in the case of the PCM1770 device, and are selected using the FMT terminal in the case of the

PCM1771 device. The default data format is 24-bit, left-justified, slave mode. All formats require binary 2s

complement, MSB-first audio data. Figure 23 shows a detailed timing diagram for the serial audio interface in

slave mode. Figure 24 shows a detailed timing diagram for the serial audio interface in master mode.

Table 2. Audio Data Interface

AUDIO-DATA INTERFACE FEATURE

CHARACTERISTIC

Audio data interface format (PCM1770) Standard, I²S, left-justified

(PCM1771) I²S, left-justified

Audio data bit length

Audio data format

16-, 20-, 24-bit selectable

MSB-first, 2s-complement

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(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW (Slave Mode)

1/f

S

LRCK

R-Channel

L-Channel

BCK

(= 32 f , 48 f or 64 f )

S

16-Bit Right-Justified, BCK = 32 f

S

DATA 14 15 16

1

2

3

14 15 16

1

2

3

14 15 16

LSB

MSB

LSB

MSB

16-Bit Right-Justified, BCK = 48 f or 64 f

S

DATA 14 15 16

1

2

3

14 15 16

LSB

1

2

3

14 15 16

LSB

MSB

20-Bit Right-Justified

DATA 18 19 20

1

2

3

18 19 20

LSB

1

2

3

18 19 20

LSB

MSB

24-Bit Right-Justified

DATA 22 23 24

1

2

3

22 23 24

LSB

1

2

3

22 23 24

LSB

MSB

2

(2) I S Data Format; L-Channel = LOW, R-Channel = HIGH (Slave Mode)

1/f

S

LRCK

R-Channel

L-Channel

BCK

(= 32 f , 48 f or 64 f

)

S

DATA

1

2

3

N−2 N−1

N

1

2

3

N−2 N−1

N

1

2

MSB

LSB

MSB

LSB

(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW (Slave Mode)

1/f

S

LRCK

BCK

L-Channel

R-Channel

(= 32 f , 48 f or 64 f

)

S

DATA

1

2

3

N−2 N−1

N

1

2

3

N−2 N−1

N

1

2

MSB

LSB

MSB

LSB

(4) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW (Master Mode)

(The frequency of BCK is 64 f and SCKI is 256 f only)

S

1/f

S

LRCK

BCK

L-Channel

R-Channel

(= 64 f

)

S

DATA

1

2

3

N−2 N−1

N

1

2

3

N−2 N−1

N

1

2

MSB

LSB

MSB

LSB

T0009-01

Figure 22. Audio Data Input Formats

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50% of V

CC

LRCK (Input)

t

(BCL)

t

(BCH)

(LB)

50% of V

CC

BCK (Input)

t

(BCY)

(BL)

50% of V

CC

DATA

t

(DS)

(DH)

T0010-02

PARAMETER

MIN

MAX

UNIT

t_(BCY)

t_(BCH)

t_(BCL)

t_(BL)

BCK pulse cycle time

BCK high-level time

BCK low-level time

1/(64 f_S)⁽¹⁾

35

10

ns

BCK rising edge to LRCK edge

LRCK edge to BCK rising edge

DATA set-up time

t_(LB)

t_(DS)

t_(DH)

DATA hold time

(1) f_Sis the sampling frequency.

Figure 23. Audio Interface Timing (Slave Mode)

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t

(SCY)

50% of V

SCKI

LRCK (Output)

BCK (Output)

DATA

CC

t

(DL)

50% of V

CC

t

(BCL)

t

(DB)

(BCH)

(DB)

t

(BCY)

t

(DS)

t

(DH)

T0011-02

PARAMETER

MIN

MAX

UNIT

t_(SCY)

t_(DL)

SCKI pulse cycle time

1/(256 f_S)⁽¹⁾

LRCK edge from SCKI rising edge

BCK edge from SCKI rising edge

BCK pulse cycle time

BCK high-level time

0

40

ns

t_(DB)

0

1/(64 f_S)⁽¹⁾

146

t_(BCY)

t_(BCH)

t_(BCL)

t_(DS)

ns

BCK low-level time

146

DATA setup time

10

t_(DH)

DATA hold time

10

(1) f_Sis up to 48 kHz. f_Sis the sampling frequency.

Figure 24. Audio Interface Timing (Master Mode)

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Hardware Control (PCM1771)

The digital functions of the PCM1771 device are capable of hardware control. Table 3 shows selectable formats,

Table 4 shows de-emphasis control, and Table 5 shows analog mixing control.

Table 3. Data Format Select

FMT

Low

High

DATA FORMAT

16- to 24-bit, left-justified format

16- to 24-bit, I²S format

Table 4. De-Emphasis Control

DEMP

Low

DE-EMPHASIS FUNCTION

44.1-kHz de-emphasis OFF

High

44.1-kHz de-emphasis ON

Table 5. Analog Mixing Control

AMIX

Low

ANALOG MIXING

Analog mixing OFF

High

Analog mixing ON

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Software Control (PCM1770)

The PCM1770 device has many programmable functions that can be controlled in the software-control mode.

The functions are controlled by programming the internal registers using MS, MC, and MD.

The software-control interface is a 3-wire serial port that operates asynchronously to the serial audio interface.

The serial control interface is used to program the on-chip mode registers. MD is the serial data input, used to

program the mode registers. MC is the serial bit clock, used to shift data into the control port. MS is the mode

control port select signal.

Register Write Operation (PCM1770)

All write operations for the serial control port use 16-bit data words. Figure 25 shows the control data word

format. The most significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register index (or

address) for the write operation. The eight least significant bits, D[7:0], contain the data to be written to the

register specified by IDX[6:0].

Figure 26 shows the functional timing diagram for writing to the serial control port. To write data into the mode

register, the data is clocked into an internal shift register on the rising edge of the MC clock. Serial data can

change on the falling edge of the MC clock and must be stable on the rising edge of the MC clock. The MS

signal must be low during the write mode and the rising edge of the MS signal must be aligned with the falling

edge of the last MC clock pulse in the 16-bit frame. The MC clock can run continuously between transactions

while the MS signal is low.

LSB

D0

MSB

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0

Register Index (or Address)

D7

D6

D5

D4

D3

D2

D1

Register Data

R0001-01

Figure 25. Control Data Word Format for MD

(1) Single Write Operation

16 Bits

MS

MC

MD

MSB

LSB

MSB

(2) Continuous Write Operation

16 Bits x N Frames

MS

MC

MD

MSB

LSB

MSB

LSB

MSB

LSB

N Frames

T0012-01

Figure 26. Register Write Operation

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Control Interface Timing Requirements (PCM1770)

Figure 27 shows a detailed timing diagram for the serial control interface. These timing parameters are critical

for proper control port operation.

t

(MHH)

MS

50% of V

CC

t

(MCL)

(MLS)

t

(MLH)

(MCH)

MC

MD

50% of V

CC

t

(MCY)

LSB

CC

t

(MDS)

t

(MDH)

T0013-02

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

MC pulse cycle time

MC low-level time

MC high-level time

MS high-level time

t_(MCY)

t_(MCL)

t_(MCH)

t_(MHH)

t_(MLS)

t_(MLH)

t_(MDH)

t_(MDS)

100⁽¹⁾

ns

50

(2)

MS falling edge to MC rising edge

MS hold time

20

15

20

MD hold time

MD setup time

(1) When MC runs continuously between transactions, MC pulse cycle time is specified as 3/(128 f_S), where f_Sis

sampling rate.

(2) 3/(128 f_S) s (min), where f_Sis sampling rate.

Figure 27. Control Interface Timing

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Mode Control Registers (PCM1770)

User-Programmable Mode Controls

The PCM1770 device has a number of user-programmable functions that can be accessed via mode control

registers. The registers are programmed using the serial control interface, as discussed in the Software Control

(PCM1770) section. Table 6 lists the available mode control functions, along with their reset default conditions

and associated register index.

Register Map

Table 7 shows the mode control register map. Each register includes an index (or address) indicated by the

IDX[6:0] bits.

Table 6. User-Programmable Mode Controls

FUNCTION

Soft mute control, L/R independently

RESET DEFAULT

Disabled

REGISTER NO.

BIT(S)

01

MUTL, MUTR

ATL[5:0], ATR[5:0]

Digital attenuation level setting, 0 dB to –63 dB in 1-dB steps, L/R

independently

0 dB

01, 02

Oversampling rate control (128 f_S, 192 f_S, 256 f_S, 384 f_S)

Polarity control for analog output for R-channel DAC

Analog mixing control for analog in, AIN (terminal 14)

44.1-kHz de-emphasis control

128 f_Soversampling

Not inverted

03

04

OVER

RINV

Disabled

AMIX

Disabled

DEM

Audio data format select

24-bit, left-justified format

Disabled

FMT[2:0]

ZCAT

Zero cross attenuation

Power-down control

Disabled

PWRD

Table 7. Mode Control Register Map

REGIS IDX [6:0] B15 B14 B13 B12 B11 B10 B9

TER (B14-B8)

B8

B7

B6

B5

B4

B3

B2

B1

B0

01

02

01h

02h

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUTR MUTL ATL5 ATL4 ATL3 ATL2 ATL1 ATL0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

(1)

03

04

03h

04h

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV RINV AMIX DEM FMT2 FMT1 FMT0

(1)

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV

RSV

RSV ZCAT RSV

RSV

RSV PWR

(1)

(1) RSV is reserved for test operation. It must be set to 0 during regular operation.

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Register Definitions

Register 01

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

0

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0 MUTR MUTL ATL5

ATL4

ATL3

ATL2

ATL1

ATL0

IDX[6:0]: 000 0001b

MUTx: Soft Mute Control

Where, x = L or R, corresponding to the headphone output H_OUTL or H_OUTR.

Default value: 0

MUTL, MUTR = 0 Mute disabled (default)

MUTL, MUTR = 1 Mute enabled

The mute bits, MUTL and MUTR, enable or disable the soft mute function for the corresponding headphone

outputs, H_OUTL and H_OUTR. The soft mute function is incorporated into the digital attenuators. When mute is

disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the

digital attenuator for the corresponding output is decreased from the current setting to the infinite attenuation,

one attenuator step (1 dB) at a time. This provides pop-free muting of the headphone output.

By setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuation

level.

ATL[5:0]: Digital Attenuation Level Setting for Headphone Output, H_OUT

L

Default value: 11 1111b

Headphone output H_OUTL includes a digital attenuation function. The attenuation level can be set from 0 dB to

–62 dB, in 1-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1

dB) for every 8/f_Stime internal until the programmed attenuator setting is reached. Alternatively, the attenuation

level may be set to infinite attenuation (or mute).

The following table shows the attenuation levels for various settings:

ATL[5:0]

11 1111b

11 1110b

11 1101b

:

ATTENUATION LEVEL SETTING

0 dB, no attenuation (default)

–1 dB

–2 dB

:

00 0010b

00 0001b

00 0000b

–61 dB

–62 dB

Mute

Register 02

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

0

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

RSV

ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

IDX[6:0]: 000 0010b

ATR[5:0]: Digital Attenuation Level Setting for Headphone Output, H_OUT

R

Default value: 11 1111b

Headphone output H_OUTR includes a digital attenuation function. The attenuation level can be set from 0 dB to

–62 dB, in 1-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1

dB) for every 8/f_Stime internal until the programmed attenuator setting in reached. Alternatively, the attenuation

level can be set to infinite attenuation (or mute).

To set the attenuation levels for ATR[5:0], see the table for ATL[5:0], register 01.

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Register 03

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

0

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0 OVER RSV

RINV AMIX

DEM

FMT2 FMT1 FMT0

IDX[6:0]: 000 0011b

OVER: Oversampling Control

Default value: 0

OVER = 0

OVER = 1

128f_Soversampling

192f_S, 256f_S, 384f_Soversampling

The OVER bit controls the oversampling rate of the ∆-Σ D/A converters. When it operates at a low sampling

rate, less than 24 kHz, this function is recommended.

RINV: Polarity Control for Headphone Output, H_OUT

R

Default value: 0

RINV = 0

RINV = 1

Not inverted

Inverted output

The RINV bits allow the user to control the polarity of the headphone output, H_OUTR. This function can be used

to connect the monaural speaker using the BTL connection method. This bit is recommended to be 0 during the

power-up/-down sequence for minimizing audible pop noise.

AMIX: Analog Mixing Control for External Analog Signal, AIN

Default value: 0

AMIX = 0

AMIX = 1

Disabled (not mixed)

Enabled (mixing to the DAC output)

The AMIX bit allows the user to mix analog input (AIN) with headphone outputs (H_OUTL/H_OUTR) internally.

DEM: 44.1-kHz De-Emphasis Control

Default value: 0

DEM = 0

DEM = 1

Disabled

Enabled

The DEM bit enables or disables the digital de-emphasis filter for the 44.1-kHz sampling rate.

FMT[2:0]: Audio Interface Data Format

Default value: 000

The FMT[2:0] bits select the data format for the serial audio interface. The following table shows the available

format options.

FMT[2:0]

000

Audio Data Format Selection

16- to 24-bit, left-justified format (default)

16- to 24-bit, I²S format

001

010

24-bit right-justified data

20-bit right-justified data

16-bit right-justified data

16- to 24-bit, left-justified format, master mode

Reserved

011

100

101

110

111

Reserved

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Register 04

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

0

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

RSV

ZCAT

RSV

RSV PWRD

IDX[6:0]: 0000 0100b

ZCAT: Zero Cross Attenuation

Default value: 0

ZCAT = 0

ZCAT = 1

Normal attenuation (default)

Zero cross attenuation

This bit enables changing the signal level on zero crossing during attenuation control or muting. If the signal

does not cross BPZ beyond 512/f_S(11.6 ms at 44.1-kHz sampling rate), the signal level is changed similarly to

normal attenuation control. This function is independently monitored for each channel; moreover, change of

signal level is alternated between both channels. Figure 28 shows an example of zero cross attenuation.

ATT CTRL START

L-Channel

(1.5 kHz)

R-Channel

(1 kHz)

Level Change Point

W0001-01

Figure 28. Example of Zero Cross Attenuation

PWRD: Power Down Control

Default value: 0

PWRD = 0

PWRD = 1

Normal operation (default)

Power-down state

This bit is used to enter into low-power mode. Note that PWRD has no reset function.

When this bit is set to 1, the PCM1770 device enters low-power mode and all digital circuits are reset except the

register states, which remain unchanged.

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Analog In/Out

Headphone Output (Stereo)

The PCM1770 and PCM1771 devices have two independent headphone amplifiers, and the amplifier outputs

are provided at the H_OUTL and H_OUTR terminals. Because the capability of the headphone output is designed for

driving a 16-Ω impedance headphone, less than a 16-Ω impedance headphone is not recommended. A resistor

and a capacitor must be connected to H_OUTL and H_OUTR to ensure proper output loading.

Monaural Output (BTL Mode/Monaural Speaker)

The monaural output can be created by summing the left and right headphone outputs. When in the BTL mode,

the user must set the headphone output levels to –3 dB using the ATL[5:0] bits in register 01 and the ATR[5:0]

bits in register 02. Moreover, invert the polarity of the right headphone output by using the RINV bit on control

register 03. The RINV bit is recommended to be 0 during the power-up/-down sequence for minimizing audible

pop noise.

Analog Input

The PCM1770 and PCM1771 devices have an analog input, AIN (terminal 10). The AMIX bit (PCM1770) or the

AMIX terminal (PCM1771) allows the user to mix AIN with the headphone outputs (H_OUTL and H_OUTR) internally.

When in the mixing mode, an ac-coupling capacitor is needed for AIN. But if AIN is not used, AIN must be open

and the AMIX bit (PCM1770) must be disabled or the AMIX terminal (PCM1771) must be low.

Because AIN does not have an internal low-pass filter, it is recommended that the bandwidth of the input signal

into AIN is limited to less than 100 kHz. The source of signals connected to AIN must be connected by low

impedance.

Although the maximum input voltage on AIN is designed to be as large as 0.584 V_HP(peak-to-peak), the user

must attenuate the input voltage on AIN and control the digital input data so that each line output (H_OUTL and

H_OUTR) does not exceed 0.55 V_HP(peak-to-peak) in the mixing mode.

V_COMOutput

One unbuffered common-mode voltage output terminal, V_COM,is brought out for decoupling purposes. This

terminal is nominally biased to a dc voltage level equal to 0.5 V_HPand connected to a 10-µF capacitor. In the

case of a capacitor smaller than 10 µF, pop noise can be generated during the power-on/-off or power-up/-down

sequences.

28

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PCM1770, PCM1771

www.ti.com

SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

APPLICATION INFORMATION

Connection Diagrams

Figure 29 shows the basic connection diagram with the necessary power supply bypassing and decoupling

components. It is recommended that the component values shown in Figure 29 be used for all designs.

The use of series resistors (22 Ω to 100 Ω) is recommended for the SCKI, LRCK, BCK, and DATA inputs. The

series resistor combines with the stray PCB and device input capacitance to form a low-pass filter that reduces

high-frequency noise emissions and helps to dampen glitches and ringing present on the clock and data lines.

Power Supplies and Grounding

The PCM1770 and PCM1771 devices require a 2.4-V typical analog supply for V_CCand V_HP. These 2.4-V

supplies power the DAC, analog output filter, and other circuits. For best performance, these 2.4-V supplies

must be derived from the analog supply using a linear regulator, as shown in Figure 29.

Figure 29 shows the proper power supply bypassing. The 10-µF capacitors must be tantalum or aluminum

electrolytic, while the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount applications).

Short-Circuit Protection

Continuous shorting of H_OUTL and H_OUTR to GND, to a power supply, or to each other is not permitted, as

protection circuitry for an output short is not implemented in the device. If the possibility of shorting cannot be

eliminated in an application, an 8-Ω or higher series resistor must be added between the phase compensation

circuits of the H_OUTx pins and the application circuitry (headphone jack in Figure 29).

29

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PCM1770, PCM1771

www.ti.com

SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

APPLICATION INFORMATION (continued)

1.6 V to 3.6 V

LRCK

SCKI

MS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Audio DSP

Controller

DATA

BCK

MC

PD

MD

PCM1770

0.1 µF

10 µF

AGND

HGND

V

CC

V

HP

10 µF

V

COM

AIN

Analog In

H R

OUT

H L

OUT

10 µF

220 µF

0.022 µF

16 Ω

220 µF

Headphone

R

L

= 16 Ω

0.022 µF

16 Ω

S0008-01

Figure 29. Basic Connection Diagram

30

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PCM1770, PCM1771

www.ti.com

SLES011E–SEPTEMBER 2001–REVISED MARCH 2007

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from D Revision (April 2005) to E Revision .................................................................................................... Page

•

Changed MCKI to SCKI...................................................................................................................................................... 29

Corrected errors, added recommended parts, and changed incorrect symbols ................................................................ 30

Changes from C Revision (May 2004) to D Revision ..................................................................................................... Page

•

Changed data sheet to new format ...................................................................................................................................... 1

Changed value for power-supply voltage ............................................................................................................................. 2

Removed package/ordering information, reformatted, and appended at end of data sheet ................................................ 2

Added new Recommended Operating Conditions table to data sheet................................................................................. 2

Changed page layout for Terminal Function tables.............................................................................................................. 6

Changed page layout of Figure 13 and Figure 14.............................................................................................................. 12

In Figure 22, added arrows to all rising edges of BCK for data formats (2), (3), and (4)................................................... 18

Added new subsection, Short-Circuit Protection, with information concerning protection of output pins........................... 29

31

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

22-Aug-2007

PACKAGING INFORMATION

Orderable Device

PCM1770PW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

16

20

16

20

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCM1770PWG4

PCM1770PWR

PCM1770PWRG4

PCM1770RGA

TSSOP

QFN

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

RGA

PW

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCM1770RGAG4

PCM1770RGAR

PCM1770RGARG4

PCM1771PW

QFN

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

QFN

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

QFN

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

QFN

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCM1771PWG4

PCM1771PWR

PCM1771PWRG4

PCM1771RGA

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

RGA

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCM1771RGAG4

PCM1771RGAR

PCM1771RGARG4

QFN

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

QFN

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

QFN

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-Aug-2007

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

13

PCM1770RGAR

PCM1771PWR

PCM1771RGAR

RGA

PW

20

16

20

SITE 49

4.4

6.8

4.4

5.4

4.4

1.3

1.6

1.3

8

12

16

12

Q1

330

17

RGA

330

13

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

PCM1770RGAR

PCM1771PWR

PCM1771RGAR

RGA

PW

20

16

20

SITE 49

342.9

336.6

20.64

28.58

20.64

RGA

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,

improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	PCM1771RGARG4
厂家：	TEXAS INSTRUMENTS
描述：	LOW-VOLTAGE AND LOW-POWER STEREO AUDIO DIGITAL-TO-ANALOG CONVERTER WITH HEADPHONE AMPLIFIER 低电压和低功耗立体声音频数位类比转换器，带有耳机放大器转换器放大器
文件：	总38页 (文件大小：570K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCM1771RGARG4 [TI]

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