PCM1794ADBR [TI]
132dB SNR 最高性能立体声 DAC（硬件控制） | DB | 28 | -25 to 85;
| 型号： | PCM1794ADBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 132dB SNR 最高性能立体声 DAC（硬件控制） | DB | 28 | -25 to 85 光电二极管 转换器 |
| 文件： | 总37页 (文件大小：900K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM1794A
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
PCM1794A 24 位、192kHz 采样、高级分段、音频立体声
数模转换器
1 特性
2 应用
1
•
•
24 位分辨率
模拟性能：
•
•
•
•
•
A/V 接收器
DVD 播放器
乐器
–
动态范围：
车载音频系统
其他需要 24 位音频的应用
–
–
–
132dB（9V RMS，单声道）
129dB（4.5V RMS，立体声）
127dB（2V RMS，立体声）
3 说明
–
总谐波失真 + 噪声 (THD+N)：0.0004%
PCM1794A 器件是一款单片 CMOS 集成电路，由立
体声数模转换器 (DAC) 和采用小型 28 引脚 SSOP 封
装的支持电路组成。数据转换器采用德州仪器 (TI) 的
高级分段 DAC 架构，拥有出色的动态性能和增强的时
钟抖动耐受性。PCM1794A 器件提供均衡电流输出，
允许用户从外部优化模拟性能。最高支持 200kHz 的采
样速率。
•
•
差分电流输出：7.8mA p-p
8× 过采样数字滤波器：
–
–
阻带衰减：–130dB
通带纹波：±0.00001dB
•
•
采样频率：10kHz 至 200kHz
系统时钟：128、192、256、384、512 或 768
fS，带自动检测功能
•
•
接受 16 位和 24 位音频数据
脉冲编码调制 (PCM) 数据格式：标准、I2S 和左对
齐
器件信息(1)
器件型号
PCM1794A
封装
封装尺寸（标称值）
SSOP (28)
10.20mm x 5.30mm
•
可供外部数字滤波器或数字信号处理器 (DSP) 选用
的接口
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
•
•
•
•
数字去加重功能
数字滤波器衰减：急剧或缓慢
软静音
零标记
双电源支持：5V 模拟、3.3V 数字
5V 耐压数字输入
小型 28 引脚紧缩小外形 (SSOP) 封装
简化的应用示意图
I/V Stage
Data
LRCK
BCK
L Analog Out
R Analog Out
Differential Output or
Differential to SE
Stage
PCM1794A
DSP
MCLK
I/V Stage
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLES117
PCM1794A
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 25
Power Supply Recommendations...................... 26
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 7
6.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 27
11 器件和文档支持 ..................................................... 28
11.1 文档支持................................................................ 28
11.2 社区资源................................................................ 28
11.3 商标....................................................................... 28
11.4 静电放电警告......................................................... 28
11.5 Glossary................................................................ 28
12 机械、封装和可订购信息....................................... 28
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (November 2006) to Revision B
Page
•
已添加 ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档
支持部分以及机械、封装和可订购信息部分。 ....................................................................................................................... 1
2
Copyright © 2004–2015, Texas Instruments Incorporated
PCM1794A
www.ti.com.cn
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
5 Pin Configuration and Functions
DB Package
28-Pin SSOP
Top View
MONO
CHSL
DEM
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC2L
2
AGND3L
3
I
I
OUTL–
LRCK
DATA
BCK
4
OUTL+
5
AGND2
6
V
V
V
CC1
SCK
7
COML
COMR
REF
DGND
8
V
9
I
DD
MUTE
FMT0
FMT1
ZERO
RST
10
11
12
13
14
AGND1
I
I
OUTR–
OUTR+
AGND3R
V
CC2R
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
1
MONO
CHSL
DEM
I
I
Monaural mode enable(1)
L-channel, R-channel select(1)
De-emphasis enable(1)
2
3
I
4
LRCK
DATA
BCK
I
Left and right clock (fS) input(1)
Serial audio data input(1)
Bit clock input(1)
5
I
6
I
7
SCK
I
System clock input(1)
8
DGND
VDD
—
—
I
Digital ground
9
Digital power supply, 3.3 V
Mute control(1)
Audio data format select(1)
Audio data format select(1)
Zero flag
10
11
12
13
14
15
16
17
18
19
20
21
22
MUTE
FMT0
FMT1
ZERO
RST
I
I
O
I
Reset(1)
VCC2R
AGND3R
IOUTR+
IOUTR–
AGND1
IREF
—
—
O
O
—
—
—
—
Analog power supply (R-channel DAC), 5 V
Analog ground (R-channel DAC)
R-channel analog current output +
R-channel analog current output –
Analog ground (internal bias)
Output current reference bias pin
R-channel internal bias decoupling pin
L-channel internal bias decoupling pin
VCOMR
VCOM
L
(1) Schmitt-trigger input, 5-V tolerant.
Copyright © 2004–2015, Texas Instruments Incorporated
3
PCM1794A
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
23
24
25
26
27
28
NAME
VCC
1
—
—
O
Analog power supply, 5 V
AGND2
IOUTL+
Analog ground (internal bias)
L-channel analog current output +
L-channel analog current output –
Analog ground (L-channel DAC)
Analog power supply (L-channel DAC), 5 V
IOUTL–
O
AGND3L
VCC2L
—
—
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
MAX
6.5
UNIT
VCC1, VCC2L, VCC2R
Supply Voltage
V
VDD
4
Supply voltage differences: VCC1, VCC2L, VCC2R
±0.1
±0.1
V
V
Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND
LRCK, DATA, BCK, SCK, FMT1,
FMT0, MONO, CHSL, DEM, MUTE,
RST
–0.3
6.5
Digital input voltage
V
ZERO
–0.3
–0.3
(VDD + 0.3 V) < 4
Analog input voltage
(VCC + 0.3 V) < 6.5
V
mA
°C
°C
°C
°C
°C
Input current (any pins except supplies)
Ambient temperature under bias
Junction temperature
±10
125
150
260
250
150
–40
Lead temperature (soldering, 5 s)
Package temperature (IR reflow, peak)
Storage temperature, Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2004–2015, Texas Instruments Incorporated
PCM1794A
www.ti.com.cn
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
3
3.3
3.6
VDC
VCC
VCC2L
VCC2R
1
Supply voltage
4.75
—25
5
5.25
85
VDC
°C
TJ
Operation temperature
6.4 Thermal Information
PCM1794A
DB (SSOP)
28 PINS
66.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
25.4
27.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.3
ψJB
27.1
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit
data, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DATA FORMAT
fS
Sampling frequency
10
200
kHz
fS
System clock frequency
128, 192, 256, 384, 512, 768
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
2
VIH
VIL
IIH
Input logic level high
VDC
VDC
µA
Input logic level low
0.8
10
Input logic current high
Input logic current low
Output logic level high
Output logic level low
VIN = VDD
IIL
VIN = 0 V
–10
µA
VOH
VOL
IOH = –2 mA
IOL = 2 mA
2.4
VDC
VDC
0.4
DYNAMIC PERFORMANCE (2-V RMS OUTPUT)(1)(2)
fS = 44.1 kHz
0.0004%
0.0008%
0.0015%
0.0008%
THD+N at VOUT = 0 dB
fS = 96 kHz
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 192 kHz
123
127
127
127
Dynamic range
dB
(1) Filter condition:
(a) THD+N: 20-Hz HPF, 20-kHz apogee LPF
(b) Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
(c) Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
(d) Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
(e) Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision™
in the averaging mode.
(2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 25.
Copyright © 2004–2015, Texas Instruments Incorporated
5
PCM1794A
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
www.ti.com.cn
Electrical Characteristics (continued)
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit
data, unless otherwise noted
PARAMETER
TEST CONDITIONS
EIAJ, A-weighted, fS = 44.1 kHz
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 192 kHz
fS = 44.1 kHz
MIN
TYP
127
127
127
123
122
120
±1
MAX
UNIT
123
Signal-to-noise ratio
dB
120
Channel separation
fS = 96 kHz
dB
dB
fS = 192 kHz
Level linearity error
VOUT = –120 dB
DYNAMIC PERFORMANCE (4.5-V RMS Output)(1)(3)
fS = 44.1 kHz
0.0004%
0.0008%
0.0015%
129
THD+N at VOUT = 0 dB
Dynamic range
fS = 96 kHz
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 192 kHz
fS = 44.1 kHz
129
dB
dB
dB
129
129
Signal-to-noise ratio
129
129
124
Channel separation
fS = 96 kHz
123
fS = 192 kHz
121
DYNAMIC PERFORMANCE (MONO MODE)(1)(3)
THD+N at VOUT = 0 dB
fS = 44.1 kHz
0.0004%
0.0008%
0.0015%
132
fS = 96 kHz
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 192 kHz
Dynamic range
132
dB
dB
132
132
Signal-to-noise ratio
132
132
ANALOG OUTPUT
Gain error
–6
–3
–2
±2
±0.5
±0.5
7.8
6
3
2
% of FSR
% of FSR
% of FSR
mA p-p
mA
Gain mismatch, channel-to-channel
Bipolar zero error
At BPZ
Output current
Full scale (0 dB)
At BPZ
Center current
–6.2
DIGITAL FILTER PERFORMANCE
De-emphasis error
±0.004
dB
FILTER CHARACTERISTICS-1: SHARP ROLLOFF
±0.00001 dB
–3 dB
0.454 fS
0.49 fS
Pass band
Stop band
0.546 fS
–130
Pass-band ripple
±0.00001
dB
dB
s
Stop-band attenuation
Stop band = 0.546 fS
Delay time
55/fS
FILTER CHARACTERISTICS-2: SLOW ROLLOFF
±0.04 dB
–3 dB
0.254 fS
0.46 fS
Pass band
(3) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 26.
6
Copyright © 2004–2015, Texas Instruments Incorporated
PCM1794A
www.ti.com.cn
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
Electrical Characteristics (continued)
all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit
data, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Stop band
0.732 fS
Pass-band ripple
Stop-band attenuation
±0.001
dB
dB
s
Stop band = 0.732 fS
–100
Delay time
18 / fS
POWER SUPPLY REQUIREMENTS
fS = 44.1 kHz
fS = 96 kHz
fS = 192 kHz
fS = 44.1 kHz
fS = 96 kHz
fS = 192 kHz
fS = 44.1 kHz
fS = 96 kHz
fS = 192 kHz
12
23
15
40
IDD
Digital supply current(4)
Analog supply current(4)
Power dissipation(4)
mA
mA
mW
45
33
ICC
35
37
205
250
335
250
(4) Input is BPZ data.
6.6 Timing Requirements
MIN
MAX
UNIT
SYSTEM CLOCK INPUT TIMING (see Figure 1)
t(SCY)
System-clock pulse-cycle time
13
0.4 × t(SCY)
0.4 × t(SCY)
ns
ns
ns
t(SCKH)
t(SCKL)
System-clock pulse duration, HIGH
System-clock pulse duration, LOW
EXTERNAL RESET TIMING (see Figure 2)
t(RST) Reset pulse duration, LOW
AUDIO INTERFACE TIMING (see Figure 3)
20
ns
t(BCY)
t(BCL)
t(BCH)
t(BL)
BCK pulse-cycle time
BCK pulse duration, LOW
BCK pulse duration, HIGH
BCK rising edge to LRCK edge
LRCK edge to BCK rising edge
DATA setup time
70
30
30
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
t(LB)
t(DS)
t(DH)
DATA hold time
LRCK clock duty
50% ± 2-bit clocks
Copyright © 2004–2015, Texas Instruments Incorporated
7
PCM1794A
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
www.ti.com.cn
t(SCKH)
H
2 V
System Clock (SCK)
0.8 V
L
t(SCKL)
t(SCY)
Figure 1. System Clock Input Timing
RST (Pin 14)
50 % of V
DD
t
(RST)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
Figure 2. External Reset Timing
50% of V
50% of V
50% of V
LRCK
BCK
DD
DD
DD
t
t
(BCL)
t
(BCH)
(LB)
t
t
t
(BCY)
(BL)
DATA
t
(DS)
(DH)
Figure 3. Timing of Audio Interface
8
Copyright © 2004–2015, Texas Instruments Incorporated
PCM1794A
www.ti.com.cn
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
6.7 Typical Characteristics
0
0.00002
−50
−100
−150
−200
0.00001
0
–0.00001
–0.00002
0.0
0
1
2
3
4
0.1
0.2
0.3
0.4
0.5
Frequency [× f
]
S
Frequency [× f
]
S
Figure 4. Amplitude vs Frequency
Frequency Response, Sharp Rolloff
Figure 5. Amplitude vs Frequency
Pass-Band Ripple, Sharp Rolloff
0
0
−2
−4
−50
−100
−150
−200
−6
−8
−10
−12
−14
−16
−18
−20
0
1
2
3
4
0.0
0.1
0.2
0.3
0.4
]
0.5
0.6
Frequency [× f
]
S
Frequency [× f
S
Figure 6. Amplitude vs Frequency
Frequency Response, Slow Rolloff
Figure 7. Amplitude vs Frequency
Transition Characteristics, Slow Rolloff
0
−2
0.020
0.015
0.010
0.005
−4
0
−6
–0.005
–0.010
−8
–0.015
–0.020
−10
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
f – Frequency – kHz
f – Frequency – kHz
fS = 44.1 kHz
fS = 44.1 kHz
Figure 9. De-Emphasis Error vs Frequency
Figure 8. De-Emphasis Level vs Frequency
Copyright © 2004–2015, Texas Instruments Incorporated
9
PCM1794A
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
www.ti.com.cn
Typical Characteristics (continued)
132
130
128
126
124
122
0.01
f
S
= 96 kHz
f
S
= 48 kHz
f
S
= 192 kHz
f
= 192 kHz
S
0.001
f
S
= 96 kHz
f
= 48 kHz
5.00
S
0.0001
4.50
4.75
V
5.00
5.25
5.50
4.50
4.75
V
5.25
5.50
– Supply Voltage – V
CC
– Supply Voltage – V
CC
Figure 11. Dynamic Range vs Supply Voltage
Figure 10. Total Harmonic Distortion + Noise vs Supply
Voltage
132
130
130
128
f
S
= 96 kHz
f
128
126
124
122
126
124
122
120
f
= 96 kHz
S
= 192 kHz
S
f
S
= 48 kHz
f
= 48 kHz
S
f
S
= 192 kHz
4.50
4.75
V
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
– Supply Voltage – V
V
CC
– Supply Voltage – V
CC
TA = 25°C
VOUT = 4.5 VRMS
VDD = 3.3 V
Measurement circuit is Figure 26
Figure 12. Signal-to-Noise Ratio vs Supply Voltage
Figure 13. Channel Separation vs Supply Voltage
132
0.01
130
f
S
= 96 kHz
f
S
= 48 kHz
128
126
124
122
f
S
= 192 kHz
f
S
= 192 kHz
0.001
f
= 96 kHz
= 48 kHz
S
f
S
0.0001
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
– Free-Air Temperature – °C
A
T
– Free-Air Temperature – °C
A
Figure 15. Dynamic Range vs Free-Air Temperature
Figure 14. Total Harmonic Distortion + Noise
vs Free-Air Temperature
10
Copyright © 2004–2015, Texas Instruments Incorporated
PCM1794A
www.ti.com.cn
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
Typical Characteristics (continued)
132
130
130
128
126
124
122
120
f
= 96 kHz
S
128
126
124
122
f
S
= 192 kHz
f = 48 kHz
S
f
S
= 48 kHz
f
S
= 192 kHz
f
S
= 96 kHz
−50
−25
0
25
50
75
100
−50
−25
0
T – Free-Air Temperature – °C
A
25
50
75
100
T
– Free-Air Temperature – °C
A
VCC = 5 V
VDD = 3.3 V
VOUT = 4.5 VRMS
Measurement circuit is Figure 26.
Figure 16. Signal-to-Noise Ratio vs Free-Air Temperature
Figure 17. Channel Separation vs Free-Air Temperature
0
0
−20
−40
−20
−40
−60
−60
−80
−80
−100
−120
−140
−160
−180
−100
−120
−140
−160
0
2
4
6
8
10 12 14 16 18 20
0
10 20 30 40 50 60 70 80 90 100
f – Frequency – kHz
f – Frequency – kHz
VCC = 5 V
TA = 25°C
Measurement circuit is Figure 26
VCC = 5 V
TA = 25°C
Measurement circuit is Figure 26
VDD = 3.3 V
fS = 48 kHz, 32768 point 8
average
VDD = 3.3 V
fS = 48 kHz, 32768 point 8
average
Figure 18. Amplitude vs Frequency
Figure 19. Amplitude vs Frequency
–60-db Output Spectrum, BW = 20 kHz
–60-db Output Spectrum, BW = 100 kHz
10
1
0.1
0.01
0.001
0.0001
−100
−80
−60
−40
−20
0
Input Level – dBFS
VCC = 5 V
Measurement circuit is Figure 26
fS = 48 kHz, TA = 25°C
VDD = 3.3 V
Figure 20. Total Harmonic Distortion + Noise vs Input Level
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7 Detailed Description
7.1 Overview
The PCM1794A device is a 24-bit, 192-kHz, differential-current, output digital-to-analog converter (DAC) that
comes in a 28-pin SSOP package. The PCM1794AA device is hardware controlled and uses the advanced-
segment DAC architecture from TI to perform with a Stereo Dynamic Range of 129 dB (132 dB Mono) and with a
THD of 0.0004% at 44.1 kHz. The PCM1794AA device uses the SCK input as the system clock and
automatically detects the sampling rate of the Digital Audio input when valid BCK and LRCK clocks are supplied.
To bypass the internal filter, use an external digital filter.
Table 1. Device Features
FEATURE
DESCRIPTION
Resolution
24 bits
Audio data interface format
Audio data bit length
Audio data format
Standard, I2S, left justified
16-bit, 24-bit selectable
MSB first, two's complement
7.2 Functional Block Diagram
I
I
L–
OUT
LRCK
Audio
BCK
Data Input
DATA
Current
Segment
DAC
V
L
OUT
I/F
L+
L
OUT
I/V and Filter
8
Oversampling
Digital
V
I
COM
MUTE
FMT1
FMT0
MONO
CHSL
Advanced
Segment
DAC
Bias
and
Vref
REF
Filter
and
V
R
COM
Modulator
Function
Control
Function
Control
I/F
I
R–
OUT
OUT
Current
Segment
DAC
V
OUT
R
DEM
RST
I
R+
I/V and Filter
System
Clock
Manager
ZERO
Zero
Power Supply
Detect
12
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7.3 Feature Description
7.3.1 System Clock Input
The PCM1794A device requires a system clock for operating the digital interpolation filters and advanced
segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1794A device has a
system clock detection circuit that automatically senses the frequency at which the system clock is operating.
Table 2 shows examples of system clock frequencies for common audio-sampling rates.
The Timing Requirements table lists and Figure 1 shows the timing requirements for the system clock input. For
optimal performance, use a clock source with low-phase jitter and noise. One of the Texas Instruments PLL1700
family of multiclock generators is an excellent selection for providing the PCM1794A system clock.
Table 2. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
SAMPLING
FREQUENCY
128 fS
4.096
192 fS
6.144
256 fS
8.192
384 fS
12.288
16.9344
18.432
36.864
73.728
512 fS
16.384
22.5792
24.576
49.152
768 fS
24.576
33.8688
36.864
73.728
32 kHz
44.1 kHz
48 kHz
5.6488
6.144
8.4672
9.216
11.2896
12.288
24.576
49.152
96 kHz
12.288
24.576
18.432
36.864
(1)
(1)
192 kHz
See
See
(1) This system clock rate is not supported for the given sampling frequency.
7.3.2 Power-On and External Reset Functions
The PCM1794A device includes a power-on reset function. Figure 21 shows the operation of this function. With
VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from
the time VDD > 2 V.
The PCM1794A device also includes an external reset capability using the RST input (pin 14), which allows an
external controller or master reset circuit to force the PCM1794A device to initialize to its default reset state.
The Timing Requirements table lists and Figure 2 shows the external reset operation and timing. The RST pin is
set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state to start the initialization
sequence, which requires 1024 system clock periods. The external reset is useful in applications with a delay
between the PCM1794A power-up and system clock activation.
V
DD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
Figure 21. Power-On Reset Timing
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7.3.3 Audio Data Interface
7.3.3.1 Audio Serial Interface
The audio interface port is a 3-wire serial port that includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is
the serial audio bit clock, and used to clock the serial data present on DATA into the serial shift register of the
audio interface. Serial data is clocked into the PCM1794A device on the rising edge of BCK. LRCK is the serial
audio left/right word clock.
The PCM1794A device requires the synchronization of LRCK and the system clock, but does not require a
specific phase relation between LRCK and the system clock.
If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is
initialized within 1/fS, and the analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and the system clock is completed.
7.3.3.2 PCM Audio Data Formats and Timing
The PCM1794A device supports industry-standard audio data formats, including standard right-justified, I2S, and
left-justified. The data formats are shown in Figure 22. Data formats are selected using the format bits, FMT1
(pin 12), and FMT0 (pin 11) as shown in Table 3. All formats require binary twos-complement, MSB-first audio
data. The Timing Requirements table lists and Figure 3 shows a detailed timing diagram for the serial audio
interface.
14
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(1) Standard Data Format (Right Justified); L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 16-Bit
14 15 16
1
2
15 16
LSB
1
2
15 16
DATA
MSB
Audio Data Word = 24-Bit
22 23 24
1
2
23 24
LSB
1
2
23 24
DATA
MSB
(2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 24-Bit
DATA
1
2
23 24
LSB
1
2
23 24
1
2
MSB
2
(3) I S Data Format; L-Channel = LOW, R-Channel = HIGH
1/f
S
LRCK
L-Channel
R-Channel
BCK
Audio Data Word = 24-Bit
DATA
1
2
23 24
LSB
1
2
23 24
1
2
MSB
Figure 22. Audio Data Input Formats
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7.3.4 Audio Data Format
Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1794A device also supports monaural
mode and DF bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1794A device can select the DF
rolloff characteristics.
Table 3. Audio Data Format Select
MONO
CHSL
FMT1
GMT0
FORMAT
I2S
STEREO/MONO
Stereo
DF ROLLOFF
Sharp
Sharp
Sharp
Sharp
Slow
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Left-justified format
Standard, 16-bit
Standard, 24-bit
I2S
Stereo
Stereo
Stereo
Stereo
Left-justified format
Standard, 16-bit
Digital filter bypass
I2S
Stereo
Slow
Stereo
Slow
Mono
—
Mono, L-channel
Mono, L-channel
Mono, L-channel
Mono, L-channel
Mono, R-channel
Mono, R-channel
Mono, R-channel
Mono, R-channel
Sharp
Sharp
Sharp
Sharp
Sharp
Sharp
Sharp
Sharp
Left-justified format
Standard, 16-bit
Standard, 24-bit
I2S
Left-justified format
Standard, 16-bit
Standard, 24-bit
7.3.5 Soft Mute
The PCM1794A device supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs
transition to the bipolar zero level in –0.5-dB steps with a transition speed of 1/fS per step. The mute operation
system provides pop-free muting of the DAC output.
7.3.6 De-Emphasis
The PCM1794A device has a de-emphasis filter for the sampling frequency of 44.1 kHz. The de-emphasis filter is
controlled using DEM (pin 3).
7.3.7 Zero Detect
When the PCM1794A device detects that the audio input data in the L-channel and the R-channel is
continuously zero for 1024 LRCKs in the PCM mode, or that the audio input data is continuously zero for 1024
WDCKs in the external filter mode, the PCM1794A device sets ZERO (pin 13) to HIGH.
7.3.8 Advanced Segment DAC
Upper
0–62
6 Bits
Level
ICOB
Decoder
0–66
Current
Segment
DAC
Advanced
DWA
Digital Input
Analog Output
24 Bits
rd
3
-Order
5-Level
Sigma-Delta
8 f
S
0–4
MSB
and
Lower 18 Bits
Level
Figure 23. Advanced Segment DAC
16
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The PCM1794A device uses TI’s advanced segment DAC architecture to achieve excellent dynamic
performance and improved tolerance to clock jitter. The PCM1794A device provides balanced current outputs.
Digital input data using the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are
converted to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are
processed by a five-level, third-order delta-sigma modulator operated at 64 fS by default. The 1 level of the
modulator is equivalent to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB
converter and third-order delta-sigma modulator are summed together to create an up-to-66-level digital code,
and then processed by data-weighted averaging (DWA) to reduce the noise produced by element mismatch. The
data of up to 66 levels from the DWA is converted to an analog output in the differential-current segment section.
This architecture has overcome the various drawbacks of conventional multibit processing, and also achieves
excellent dynamic performance.
7.3.9 Analog Output
Table 4 and Figure 24 show the relationship between the digital input code and analog output.
Table 4. Digital Input Code and Analog Output
800000 (–FS)
–2.3
000000 (BPZ)
7FFFFF (+FS)
–10.1
IOUTN [mA]
IOUTP [mA]
VOUTN [V](1)
VOUTP [V](1)
VOUT [V](1)
–6.2
–6.2
–4.65
–4.65
0
–10.1
–2.3
–1.725
–7.575
–2.821
–7.575
–1.725
2.821
(1) VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the measurement circuit of Figure 25.
0
−2
I N
OUT
−4
−6
−8
I P
OUT
−10
−12
800000(–FS)
000000(BPZ)
7FFFFF(+FS)
Input Code – Hex
Figure 24. Relationship Between Digital Input and Analog Output
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7.4 Device Functional Modes
7.4.1 Device Control
The PCM1794A device is a hardware controlled by external pins. These pins can be tied high or low directly to
GND or to VDD. These pins can also be controlled by the GPIO of a host controller.
7.4.2 Audio Input Modes
The PCM1794A device accepts PCM audio in I2S, Right justified (standard), or Left justified formats. The
PCM1794 device has an internal digital filter that has the option of a slow or sharp roll off. Use an external digital
filter to bypass the internal digital filter. External filter mode is explained more in the Interfacing With an External
Digital Filter section.
7.4.3 Audio Output Modes
With the use of the MONO pin, the PCM1794A can output either differential stereo audio, or differential mono
audio. Figure 25 shows an example of stereo output. Figure 27 shows an example of mono mode.
18
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The design of the application circuit lets the user realize the high signal-to-noise (S/N) ratio of the PCM1794A
device, as noise and distortion generated in an application circuit are not negligible.
In the circuit of Figure 25, the output level is 2-VRMS, and 127-dB S/N is achieved. The circuit of Figure 26 should
result in the highest performance. In this case the output level is set to 4.5-VRMS, and 129-dB S/N is achieved
(stereo mode). In monaural mode, if the output of the L-channel and R-channel is used as a balanced output,
132-dB S/N is achieved (see Figure 27).
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Application Information (continued)
C
1
2200 pF
R
1
750 Ω
V
CC
V
CC
C
3
2700 pF
C
11
0.1 µF
R
5
270 Ω
C
15
0.1 µF
C
17
22 pF
C
19
33 pF
7
5
R
3
560 Ω
7
2
3
8
–
+
I –
OUT
5
R
7
100 Ω
2
3
6
–
+
6
U
1
NE5534
U
4
3
LT1028
4
R
4
560 Ω
C
12
0.1 µF
R
6
270 Ω
C
16
0.1 µF
C
4
2700 pF
V
EE
V
EE
C
2
2200 pF
R
2
750 Ω
V
CC
C
13
0.1 µF
V
= 15 V
CC
EE
V
f
= –15 V
C
18
22 pF
= 217 kHz
C
7
5
2
3
8
6
–
+
I +
OUT
U
2
NE5534
4
C
14
0.1 µF
V
EE
Figure 25. Measurement Circuit, VOUT = 2-VRMS
20
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Application Information (continued)
C
1
2200 pF
R
1
820 Ω
V
CC
V
CC
C
3
2700 pF
C
11
0.1 µF
R
5
360 Ω
C
15
0.1 µF
C
17
22 pF
C
19
33 pF
7
5
R
3
360 Ω
7
2
3
8
–
+
I –
OUT
5
R
7
100 Ω
2
3
6
–
+
6
U
1
NE5534
U
4
3
LT1028
4
R
4
360 Ω
C
12
0.1 µF
R
6
360 Ω
C
16
0.1 µF
C
4
2700 pF
V
EE
V
EE
C
2
2200 pF
R
2
820 Ω
V
CC
V
V
f
= 15 V
CC
EE
C
13
0.1 µF
= –15 V
= 162 kHz
C
C
18
22 pF
7
5
2
3
8
6
–
+
I +
OUT
U
2
NE5534
4
C
14
0.1 µF
V
EE
Figure 26. Measurement Circuit, VOUT = 4.5-VRMS
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Application Information (continued)
I
L– (Pin 26)
I
I
–
+
OUT
OUT
OUT+
Figure 25
Circuit
I
L+ (Pin 25)
OUT
OUT
3
2
1
I
I
R– (Pin 18)
I
I
–
+
OUT
OUT
OUT–
Figure 25
Circuit
Balanced Out
R+ (Pin 17)
OUT
OUT
Figure 27. Measurement Circuit for Monaural Mode
8.1.1 I/V Section
The current of the PCM1794A device on each of the output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is 7.8 mA p-p
at 0 dB (full scale). Use Equation 1 to calculate the voltage output level of the I/V converter (Vi).
Vi = 7.8 mA p–p × Rf
where
•
Rf is the feedback resistance of I/V converter
(1)
An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic
performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the
audio dynamic performance of the I/V section.
8.1.2 Differential Section
The PCM1794A voltage outputs are followed by differential amplifier stages, which sum the differential signals for
each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-
pass filter function.
The operational amplifier recommended for the differential circuit is the Linear Technology LT1028, because the
input noise is low.
8.1.3 Interfacing With an External Digital Filter
For some applications, using a programmable digital signal processor as an external digital filter to perform the
interpolation function may be necessary. The following pin settings enable the external digital filter application
mode:
•
•
•
•
MONO (pin 1) = LOW
CHSL (pin 2) = HIGH
FMT0 (pin 11) = HIGH
FMT1 (pin 12) = HIGH
The pins that provide the serial interface for the external digital filter are shown in the connection diagram of
Figure 28. The word clock (WDCK) must be operated at 8× or 4× the desired sampling frequency, fS.
22
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Application Information (continued)
V
DD
MONO
CHSL
DEM
V
2L
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
External
Filter
Device
AGND3L
I
I
L–
L+
3
OUT
WDCK
DATA
BCK
LRCK
DATA
BCK
4
OUT
AGND2
5
V
1
CC
6
Analog
SCK
SCK
V L
COM
7
Output Stage
(See Figure 23)
PCM1794A
DGND
V
COM
R
8
V
DD
I
REF
9
MUTE
FMT0
FMT1
ZERO
RST
AGND1
10
11
12
13
14
I
R–
R+
OUT
I
OUT
AGND3R
V
CC
2R
Figure 28. Connection Diagram for External Digital Filter (Internal DF Bypass Mode) Application
8.1.3.1 System Clock (SCK) and Interface Timing
In an application using an external digital filter, the PCM1794A device requires the synchronization of WDCK and
the system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK,
and DATA is shown in Figure 29.
WDCK
50% of V
50% of V
50% of V
DD
DD
DD
t
t
t
(LB)
(BCH)
(BCL)
BCK
t
t
t
(BCY)
(BL)
DATA
t
(DS)
(DH)
Figure 29. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
Table 5 shows the timing requirements for an application using an external digital filter in internal DF bypass
mode.
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Application Information (continued)
Table 5. External Digital Filter Application Timing Requirements
MIN
20
7
MAX
UNIT
ns
t(BCY)
t(BCL)
t(BCH)
t(BL)
BCK pulse-cycle time
BCK pulse duration, LOW
BCK pulse duration, HIGH
BCK rising edge to WDCK falling edge
WDCK falling edge to BCK rising edge
DATA setup time
ns
7
ns
5
ns
t(LB)
5
ns
t(DS)
t(DH)
5
ns
DATA hold time
5
ns
8.1.3.2 Audio Format
The PCM1794A device in the external digital filter interface mode supports right-justified audio formats, including
24-bit audio data, as shown in Figure 30.
1/4 f or 1/8 f
S
S
WDCK
BCK
Audio Data Word = 24-Bit
23 24
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DATA
MSB
LSB
Figure 30. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
24
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8.2 Typical Application
This application is using the GPIO of a host controller to manipulate the hardware control pins. A PCM audio
source is supplying digital audio and the output is single-ended stereo audio.
C
f
5 V
R
f
0.1 µF
MONO
CHSL
DEM
V
2L
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10 µF
CC
+
–
+
Controller
AGND3L
Differential
to
Single
I L–
OUT
3
C
f
V
OUT
L-Channel
Converter
With
LRCK
DATA
BCK
I
L+
4
OUT
R
f
5 V
PCM
AGND2
Low-Pass
Filter
5
–
+
Audio Data
Source
V
1
CC
6
47 µF
+
+
SCK
V L
COM
7
C
f
+
10 µF
PCM1794A
DGND
V
COM
R
8
R
0.1 µF
f
47 µF
10 kΩ
V
DD
I
REF
9
–
+
MUTE
FMT0
FMT1
ZERO
RST
AGND1
10
11
12
13
14
Differential
to
Single
I
R–
R+
C
f
OUT
V
OUT
R-Channel
Converter
With
Controller
I
OUT
R
f
0.1 µF
5 V
AGND3R
Low-Pass
Filter
–
+
V
CC
2R
10 µF
+
3.3 V
+
10 µF
Figure 31. Typical Application Circuit
8.2.1 Design Requirements
For the typical application example, use the parameters listed in Table 6.
Table 6. Design Parameters
DESIGN PARAMETER
Audio Input
Audio Output
Control
EXAMPLE
Digital PCM
Single-Ended Stereo Analog
Host GPIO
Filter
Internal Filter
8.2.2 Detailed Design Procedure
8.2.2.1 Audio Input or Output
In this application, a PCM audio source is supplied to the device. A current output is produced and then
converted to a voltage output in the I/V stage. The next stage in the output is a differential to single-ended
amplifier stage with a low pass filter to reduce out of band noise. The fc of the example circuits (Figure 26 and
Figure 27) are shown in the example figures. Use Equation 2 to calculate the value of fc.
fc = 1 / (2 × π × Rf × Cf)
(2)
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Typical Application (continued)
8.2.3 Application Curves
0
−20
10
1
−40
−60
0.1
0.01
−80
−100
−120
−140
−160
0.001
0.0001
0
10 20 30 40 50 60 70 80 90 100
f – Frequency – kHz
−100
−80
−60
−40
−20
0
Input Level – dBFS
VCC = 5 V
TA = 25°C
Measurement circuit is Figure 26
VCC = 5 V
Measurement circuit is Figure 26
fS = 48 kHz, TA = 25°C
fS = 48 kHz, 32768 point 8 average
VDD = 3.3 V
VDD = 3.3 V
–60-db Output Spectrum, BW = 100 kHz
Figure 32. Amplitude vs Frequency
Figure 33. Total Harmonic Distortion + Noise vs Input
Level
9 Power Supply Recommendations
The PCM1794A device requires 5-V (nominal) supplies. A 5-V supply is required for the analog circuitry powered
by the VCC1, VCC2L, and VCC2R pins. A second 5-V supply is for the digital circuitry powered by the VDD pin.
These pins can be powered by the same 5-V rail but separating the supplies can assist with getting the target
SNR and THD in some cases. Place the decoupling capacitors for the power supplies close to the device
terminals.
10 Layout
10.1 Layout Guidelines
TI recommends using the same ground between AGND and DGND to avoid any potential voltage difference
between them. Ensure the return currents for digital signals avoid the AGND pin or the input signals to the I/V
stage. Avoid running high frequency clock and control signals near AGND, or any of the IOUT pins where
possible. The pin layout of the PCM1794A partitions into two parts: an analog section and a digital section. If the
system is partitioned in such a way that digital signals are routed away from the analog sections, then no digital
return currents (for example, clocks) should be generated in the analog circuitry.
Place the decoupling capacitors as close to the Vcc1, VCC2L, VCC2R, VCOML, VCOMR, and VDD pins as possible.
See Figure 34 for additional guidelines.
26
Copyright © 2004–2015, Texas Instruments Incorporated
PCM1794A
www.ti.com.cn
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
10.2 Layout Example
5 V
+
1
2
28
MONO
CHSL
DEM
V
2L
CC
Hardware select
pins or Host
control
0.1 ꢀF
10 ꢀF
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND3L
Left I/V
Output
circuit
3
I
Lœ
OUT
4
LRCK
DATA
BCK
I
L+
OUTL+
5
AGND2
(2)
See
6
5V
V
1
L
CC
+
+
47 ꢀF
7
SCK
V
COM
10 ꢀF
PCM1794A
3.3 V
+
8
DGND
V
R
COM
10 Kꢁ
9
V
I
REF
0.1 ꢀF
10 ꢀF
DD
10
11
12
13
14
MUTE
FMT0
FMT1
ZERO
RST
AGND1
I
R-
OUT
Right I/V
Output
circuit
Hardware select
or host control
I
R+
OUT
AGND3R
5 V
V
2R
CC
+
0.1 ꢀF
10 ꢀF
(1)
Via to bottom Ground Plane
Pad to top layer ground pour
Top Layer Ground Pour
Top Layer Signal Traces
(1) TI recommends to place a top layer ground pour for shielding around device and connect it to the lower main PCB
ground plane with multiple vias.
(2) These resistors help prevent overshoot and reduce coupling. Begin with a value of 10 Ω for the MCLK resistor and
27 Ω for the other resistors.
Figure 34. PCM1794A Layout Example
版权 © 2004–2015, Texas Instruments Incorporated
27
PCM1794A
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
《适用于抗混叠和抗成像滤波器的低噪声、低失真设计》，SBAA001
《PCM1717/18/19/20/23/27 的 HD+N 与频率特性及频谱》，SBAA020
《DEM-PCM1792、DEM-DSD1792、DEM-PCM1794 和 DEM-DSD1794 EVM 板》，SLEU037
《NE5534x、SA5534x 低噪声运算放大器》，SLOS070
PLL1700《多时钟发生器》，SBOS096
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
Audio Precision is a trademark of Audio Precision.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
28
版权 © 2004–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM1794ADB
ACTIVE
SSOP
SSOP
DB
28
28
47
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-25 to 85
-25 to 85
PCM1794
A
PCM1794ADBR
ACTIVE
DB
2000 RoHS & Green
NIPDAU
PCM1794
A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1794ADBR
PCM1794ADBR
SSOP
SSOP
DB
DB
28
28
2000
2000
330.0
330.0
16.4
17.4
8.2
8.5
10.5
10.8
2.5
2.4
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM1794ADBR
PCM1794ADBR
SSOP
SSOP
DB
DB
28
28
2000
2000
356.0
336.6
356.0
336.6
35.0
28.6
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DB SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PCM1794ADB
28
47
500
10.6
500
9.6
Pack Materials-Page 3
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1
2X
10.5
9.9
8.45
NOTE 3
14
15
0.38
0.22
28X
0.15
C A B
5.6
5.0
B
NOTE 4
2 MAX
0.25
GAGE PLANE
(0.15) TYP
SEE DETAIL A
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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