PCM1801U [TI]
具有单端输入的 93dB SNR 立体声 ADC | D | 14 | -25 to 85;
| 型号： | PCM1801U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有单端输入的 93dB SNR 立体声 ADC | D | 14 | -25 to 85 光电二极管 转换器 |
| 文件： | 总25页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM1801
SBAS131C–OCTOBER 2000–REVISED JULY 2007
SINGLE-ENDED ANALOG-INPUT 16-BIT STEREO ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
•
•
•
•
DVD Recorders
DVD Receivers
AV Amplifier Receivers
Electric Musical Instruments
•
•
•
•
Dual 16-Bit Monolithic ΔΣ ADC
Single-Ended Voltage Input
Antialiasing Filter Included
64× Oversampling Decimation Filter:
Pass-Band Ripple: ±0.05 dB
DESCRIPTION
Stop-Band Attenuation: –65 dB
The PCM1801 is a low-cost, single-chip stereo
analog-to-digital converter (ADC) with single-ended
•
Analog Performance:
THD+N: –88 dB (typical)
SNR: 93 dB (typical)
Dynamic Range: 93 dB (typical)
Internal High-Pass Filter
PCM Audio Interface: Left-Justified, I2S
Sampling Rate: 4 kHz to 48 kHz
System Clock: 256 fS, 384 fS, or 512 fS
Single 5-V Power Supply
analog voltage inputs. The PCM1801 uses
a
delta-sigma modulator with 64 times oversampling, a
digital decimation filter, and a serial interface that
supports slave mode operation and two data formats.
The PCM1801 is suitable for a wide variety of
cost-sensitive consumer applications where good
performance is required.
•
•
•
•
•
Small SO-14 Package
PCM1801
(+)
th
Single-End/
Differential
Converter
5
Order
V L
IN
Delta-Sigma
Modulator
(−)
BCK
Serial Data
Interface
×1/64
Decimation
and
High-Pass
Filter
LRCK
DOUT
FMT
V
V
1
2
REF
Reference
REF
Format
Control
(−)
(+)
th
Single-End/
Differential
Converter
5
Order
V R
IN
Delta-Sigma
Modulator
BYPAS
SCKI
Clock/Timing Control
Power Supply
V
CC
AGND DGND
V
DD
B0004-02
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2007, Texas Instruments Incorporated
PCM1801
www.ti.com
SBAS131C–OCTOBER 2000–REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
TYPE
PACKAGE
CODE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
QUANTITY
PCM1801U
Rails
56
PCM1801U
14-pin SOIC
D
PCM1801U
PCM1801U/2K
Tape and reel
2000
ABSOLUTE MAXIMUM RATINGS
Supply voltage: VDD, VCC
–0.3 V to 6.5 V
±0.1 V
Supply voltage differences: VDD, VCC
GND voltage differences: AGND, DGND
Digital input voltage
±0.1 V
–0.3 V to (VDD + 0.3 V), < 6.5 V
–0.3 V to (VCC + 0.3 V), < 6.5 V
±10 mA
Analog input voltage
Input current (any pin except supplies)
Power dissipation
300 mW
Operating temperature range
Storage temperature
–25°C to 85°C
–55°C to 125°C
260°C, 5 s
Lead temperature, soldering
Package temperature (IR reflow, peak)
235°C
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range
MIN
NOM
5
MAX
5.5
UNIT
V
Analog supply voltage, VCC
Digital supply voltage, VDD
Analog input voltage, full-scale (–0 dB)
Digital input logic family
4.5
4.5
5
5.5
V
2.828
TTL
Vp-p
System clock
Digital input clock frequency
8.192
32
24.576
48
MHz
kHz
pF
Sampling clock
Digital output load capacitance
10
Operating free-air temperature, TA
–25
85
°C
2
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
PIN CONFIGURATION
PCM1801
(TOP VIEW)
1
14
13
12
11
10
9
V L
V
V
1
2
IN
REF
2
3
4
5
6
7
V R
IN
REF
DGND
AGND
V
DD
V
CC
SCKI
BCK
FMT
BYPAS
DOUT
8
LRCK
P0005-01
Table 1. PIN ASSIGNMENTS
NAME
AGND
BCK
PIN
12
6
I/O
DESCRIPTION
–
I
Analog ground
Bit clock input
BYPAS
9
I
HPF bypass control(1) L: HPF enabled
H: HPF disabled
DGND
DOUT
FMT
3
8
–
O
I
Digital ground
Audio data output
Audio data format(1)
10
L: MSB-first, left-justified
H: MSB-first, I2S
LRCK
SCKI
VCC
7
5
I
I
Sampling clock input
System clock input; 256 fS, 384 fS, or 512 fS
Analog power supply
11
4
–
–
I
VDD
Digital power supply
VINL
1
Analog input, Lch
VINR
2
I
Analog input, Rch
VREF
VREF
1
2
14
13
–
–
Reference 1 decoupling capacitor
Reference 2 decoupling capacitor
(1) With 100-kΩ typical pulldown resistor
3
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, 16-bit data, and SYSCLK = 384 fS, unless otherwise noted.
PCM1801U
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
16
Bits
DIGITAL INPUT/OUTPUT
(1)
VIH
2
Input logic level
VDC
(1)
VIL
0.8
±10
100
(2)
IIN
Input logic current
μA
(3)
IIN
(4)
VOH
IOH = –1.6 mA
IOL = 3.2 mA
4.5
Output logic level
VDC
kHz
(4)
VOL
0.5
fS
Sampling frequency
4
44.1
48
256 fS
384 fS
512 fS
1.024
1.536
2.048
11.2896
16.9344
22.5792
12.288
18.432
24.576
System clock frequency
MHz
DC ACCURACY
Gain mismatch, channel-to-channel
±1
±2
±2.5
±5
% of FSR
% of FSR
Gain error
Gain drift
±20
±2
ppm of FSR/°C
% of FSR
Bipolar zero error
High-pass filter bypassed
High-pass filter bypassed
Bipolar zero drift
±20
ppm of FSR/°C
DYNAMIC PERFORMANCE(5)
FS (–0.5 dB)
–60 dB
–88
–90
93
–80
THD+N
dB
Dynamic range
Signal-to-noise ratio
Channel separation
ANALOG INPUT
Input range
A-weighted
A-weighted
90
90
87
dB
dB
dB
93
90
FS (VIN = 0 dB)
2.828
2.1
Vp-p
V
Center voltage
Input impedance
30
kΩ
Antialiasing filter frequency response
–3 dB
150
kHz
DIGITAL FILTER PERFORMANCE
Pass band
0.454 fS
Hz
Hz
dB
dB
s
Stop band
0.583 fS
–65
Pass-band ripple
±0.05
Stop-band attenuation
Delay time (latency)
High-pass frequency response
17.4/fS
–3 dB
0.019 fS
mHz
(1) Pins 5, 6, 7, 9, and 10 (SCKI, BCK, LRCK, BYPAS, and FMT)
(2) Pins 5, 6, 7 (SCKI, BCK, LRCK) Schmitt-trigger input
(3) Pins 9, 10 (BYPAS, FMT) Schmitt-trigger input with 100-kΩ typical pulldown resistor
(4) Pin 8 (DOUT)
(5) fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™ in rms mode with 20-kHz LPF and 400-Hz HPF
in the performance calculation.
4
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, 16-bit data, and SYSCLK = 384 fS, unless otherwise noted.
PCM1801U
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY REQUIREMENTS
VCC
4.5
4.5
5
5
5.5
5.5
24
Voltage range
VDD
VDC
Supply current(6)
VCC = VDD = 5 V
VCC = VDD = 5 V
18
90
mA
Power dissipation
120
mW
TEMPERATURE RANGE
TA
Operation
–25
–55
85
°C
°C
Tstg
θJA
Storage
125
Thermal resistance
100
°C/W
(6) No load on DOUT (pin 8)
BLOCK DIAGRAM
PCM1801
(+)
(−)
th
Single-End/
Differential
Converter
5
Order
Delta-Sigma
Modulator
V L
IN
BCK
Serial Data
Interface
×1/64
Decimation
and
High-Pass
Filter
LRCK
DOUT
FMT
V
V
1
2
REF
Reference
REF
Format
Control
(−)
(+)
th
Single-End/
Differential
Converter
5
Order
V R
IN
Delta-Sigma
Modulator
BYPAS
SCKI
Clock/Timing Control
Power Supply
V
CC
AGND DGND
V
DD
B0004-02
5
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
ANALOG FRONT-END (Single Channel)
1 µF
30 kΩ
V
V
V
L
IN
−
+
1
+
−
+
1 kΩ
1 kΩ
(+)
(−)
Delta-Sigma
Modulator
1
2
REF
14
13
+
+
4.7 µF
4.7 µF
V
REF
REF
S0011-02
TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, and SYSCLK = 384 fS, unless otherwise noted
ANALOG DYNAMIC PERFORMANCE
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs
vs
TEMPERATURE
TEMPERATURE
0.006
0.005
0.004
0.003
0.002
96
95
94
93
92
3.0
2.8
96
95
−60 dB
2.6
2.4
2.2
94
93
92
Dynamic Range
−0.5 dB
SNR
−25
0
25
50
75
100
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
G001
G002
Figure 1.
Figure 2.
6
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, and SYSCLK = 384 fS, unless otherwise noted
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0.006
0.005
0.004
0.003
0.002
96
95
94
93
92
3.0
2.8
96
95
−60 dB
Dynamic Range
94
2.6
2.4
2.2
SNR
93
−0.5 dB
92
5.75
4.25
4.50
4.75
5.00
5.25
5.50
5.75
4.25
4.50
4.75
5.00
5.25
5.50
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
G003
G004
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs
vs
SAMPLING RATE
SAMPLING RATE
0.006
0.005
0.004
0.003
0.002
3.0
2.8
96
95
94
93
92
96
95
−60 dB
2.6
2.4
2.2
94
Dynamic Range
93
SNR
−0.5 dB
92
32
44.1
48
32
44.1
48
Sampling Rate − kHz
Sampling Rate − kHz
G005
G006
Figure 5.
Figure 6.
7
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, and SYSCLK = 384 fS, unless otherwise noted
SUPPLY CURRENT
SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
20
16
12
8
20
16
12
8
I
+ I
DD
CC
I
+ I
DD
CC
I
CC
I
CC
I
DD
I
DD
4
4
0
−25
0
4.25
0
25
50
75
100
4.50
4.75
5.00
5.25
5.50
5.75
T
A
− Free-Air Temperature − °C
V
CC
− Supply Voltage − V
G007
G008
Figure 7.
Figure 8.
SUPPLY CURRENT
vs
SAMPLING RATE
20
16
12
8
I
+ I
DD
CC
I
CC
I
DD
4
0
0
10
20
30
40
50
Sampling Rate − kHz
G009
Figure 9.
8
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, and SYSCLK = 384 fS, unless otherwise noted
OUTPUT SPECTRUM
FULL-SCALE FFT
–60 dBFS FFT
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
5
10
15
20
0
5
10
15
20
f − Frequency − kHz
f − Frequency − kHz
G010
G011
Figure 10.
Figure 11.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
AMPLITUDE
FREQUENCY
100
10
0.1
0.01
1
0.1
0.001
0.0001
0.01
0.001
−100
−80
−60
−40
−20
0
20
100
1k
10k 20k
Amplitude − dBV
f − Frequency − Hz
G012
G013
Figure 12.
Figure 13.
9
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, and SYSCLK = 384 fS, unless otherwise noted
DECIMATION FILTER
OVERALL CHARACTERISTICS
STOP-BAND ATTENUATION CHARACTERISTICS
0
−50
0
−20
−40
−100
−150
−200
−60
−80
−100
0
8
16
24
32
0.00
0.25
0.50
0.75
1.00
Normalized Frequency [× f Hz]
Normalized Frequency [× f Hz]
S
S
G014
G015
Figure 14.
Figure 15.
PASS-BAND RIPPLE CHARACTERISTICS
TRANSITION BAND CHARACTERISTICS
0.2
0.0
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−0.2
−0.4
−0.6
−0.8
−1.0
−4.13 dB at 0.5 f
S
0.0
0.1
0.2
0.3
0.4
0.5
0.45
0.47
0.49
0.51
0.53
0.55
Normalized Frequency [× f Hz]
Normalized Frequency [× f Hz]
S
S
G016
G017
Figure 16.
Figure 17.
10
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, and SYSCLK = 384 fS, unless otherwise noted
HIGH-PASS FILTER
HIGH-PASS FILTER RESPONSE
HIGH-PASS FILTER RESPONSE
0.2
0.0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−0.2
−0.4
−0.6
−0.8
−1.0
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Normalized Frequency [× f /1000 Hz]
Normalized Frequency [× f /1000 Hz]
S
S
G018
G019
Figure 18.
Figure 19.
ANTIALIASING FILTER
ANTIALIASING FILTER
STOP-BAND CHARACTERISTICS
ANTIALIASING FILTER
PASS-BAND CHARACTERISTICS
0.2
0.0
0
−10
−20
−30
−40
−50
−0.2
−0.4
−0.6
−0.8
−1.0
1
10
100
1k
10k 100k
1M
10M
1
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
G020
G021
Figure 20.
Figure 21.
11
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
THEORY OF OPERATION
The PCM1801 consists of a band-gap reference, two channels of a single-to-differential converter, a fully
differential 5th-order delta-sigma modulator, a decimation filter (including digital high-pass), and a serial interface
circuit. The block diagram illustrates the total architecture of the PCM1801, and the analog front-end diagram
illustrates the architecture of the single-to-differential converter and the antialiasing filter. Figure 22 illustrates the
architecture of the 5th-order delta-sigma modulator and transfer functions.
An internal high-precision reference with two external capacitors provides all reference voltages which are
required by the converter, and defines the full-scale voltage range of both channels. The internal single-ended to
differential voltage converter saves the design, space, and extra parts needed for external circuitry required by
many delta-sigma converters. The internal full-differential architecture provides a wide dynamic range and
excellent power-supply rejection performance.
The input signal is sampled at a 64× oversampling rate, eliminating the need for a sample-and-hold circuit and
simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators
which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a 1-bit
digital-to-analog converter (DAC). The delta-sigma modulator shapes the quantization noise, shifting it out of the
audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator
outputs, reducing idle tone levels.
The 64-fS, 1-bit stream from the modulator is converted to 1-fS, 16-bit digital data by the decimation filter, which
also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a
digital high-pass filter, and the filtered output is converted to time-multiplexed serial signals through a serial
interface which provides flexible serial formats.
Analog
In
−
−
st
nd
rd
th
th
1
2
3
4
5
X(z)
+
+
+
SW-CAP
SW-CAP
SW-CAP
SW-CAP
SW-CAP
Qn(z)
Integrator
Integrator
Integrator
Integrator
Integrator
−
Digital
Out
Y(z)
+
+
+
+
+
+
+
+
H(z)
Comparator
1-Bit
DAC
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
B0005-01
Figure 22. Simplified Diagram of the PCM1801 5th-Order Delta-Sigma Modulator
SYSTEM CLOCK
The system clock for the PCM1801 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling
frequency. The system clock must be supplied on SCKI (pin 5).
The PCM1801 also has a system clock detection circuit that automatically senses if the system clock is
operating at 256 fS, 384 fS, or 512 fS.
When a 384-fS or 512-fS system clock is used, the PCM1801 automatically divides the clock down to 256 fS
internally. This 256-fS clock is used to operate the digital filter and the modulator. Table 2 lists the relationship of
typical sampling frequencies and system clock frequencies. Figure 23 illustrates the system clock timing.
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Table 2. System Clock Frequencies
SAMPLING RATE FREQUENCY
SYSTEM CLOCK FREQUENCY
(kHz)
256 fs
8.1920
11.2896
12.2880
384 fs
512 fs
32
44.1
48
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
t
t
CLKIL
CLKIH
2 V
SCKI
0.8 V
T0005-04
System clock pulse duration, HIGH
System clock pulse duration, LOW
t(CLKIH)
t(CLKIL)
12 ns (min)
12 ns (min)
Figure 23. System Clock Timing
POWER-ON RESET
The PCM1801 has an internal power-on reset circuit, which initializes (resets) when the supply voltage
(VCC/VDD) exceeds 4 V (typical). Because the system clock is used as the clock signal for the reset circuit, the
system clock must be supplied as soon as power is applied; more specifically, the device must receive at least
three system clock cycles before VDD > 4 V. While VCC/VDD < 4 V (typical) and for 1024 system clock cycles after
VCC/VDD > 4 V, the PCM1801 stays in the reset state and the digital output is forced to zero. The digital output is
valid 18,436 fS periods after release from the reset state. Figure 24 illustrates the internal power-on reset timing
and the digital output for power-on reset.
4.4 V
V
CC
/ V
DD
4 V
3.6 V
Reset
Reset Removal
Internal Reset
3 Clocks Minimum
1024 System Clocks
18436 / f
S
System Clock
DOUT
(1)
Zero Data
Normal Data
T0014-02
(1) The transient response (exponentially attenuated signal from ±0.2% dc of FSR with a 200-ms time constant) appears
initially.
Figure 24. Internal Power-On Reset Timing
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
SERIAL AUDIO DATA INTERFACE
The PCM1801 interfaces the audio system through BCK (pin 6), LRCK (pin 7), and DOUT (pin 8).
The PCM1801 accepts 64-BCK/LRCK, 48-BCK/LRCK (only for a 384-fS system clock) or 32-BCK/LRCK format
for the left-justified format. And the PCM1801 accepts the 64-BCK/LRCK or 48-BCK/LRCK format (only for a
384-fS system clock) for I2S format.
DATA FORMAT
The PCM1801 supports two audio data formats in slave mode, which are selected by the FMT control input
(pin 10) as shown in Table 3. Figure 25 illustrates the data format. If the application system cannot ensure an
effective system clock prior to power up of the PCM1801, the FMT pin must be held LOW until the power-on
reset sequence is completed. In this case, if the I2S format (FMT = HIGH) is required in the application, FMT can
be set HIGH after the power-on reset sequence is completed.
Table 3. Data Format
FMT
0 (L)
1 (H)
DATA FORMAT
16-bit, left-justified
16-bit, I2S
FMT = L
16-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCK
BCK
DOUT
1
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
FMT = H
2
16-Bit, MSB-First, I S
LRCK
BCK
Left-Channel
Right-Channel
DOUT
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
T0016-03
Figure 25. Audio Data Format
14
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
INTERFACE TIMING
Figure 26 illustrates the interface timing.
t
(LRCP)
1.4 V
LRCK
t
t
(BCKL)
(LRSU)
t
(LRHD)
t
(BCKH)
1.4 V
BCK
t
t
t
(CKDO)
(LRDO)
(BCKP)
0.5 V
DD
DOUT
T0017-02
DESCRIPTION
SYMBOL
t(BCKP)
t(BCKH)
t(BCKL)
t(LRSU)
t(LRHD)
t(LRCP)
t(CKDO)
t(LRDO)
t(RISE)
MIN
300
120
120
80
TYP
MAX
UNITS
ns
BCK period
BCK pulse duration, HIGH
BCK pulse duration, LOW
ns
ns
LRCK setup time to BCK rising edge
LRCK hold time to BCK rising edge
LRCK period
ns
40
ns
20
μs
Delay time, BCK falling edge to DOUT valid
Delay time, LRCK edge to DOUT valid
Rising time of all signals
–20
–20
40
40
20
20
ns
ns
ns
Falling time of all signals
t(FALL)
ns
NOTE: Timing measurement reference level is (VIH + VIL)/2. Rising and falling time is
measured from 10% to 90% of the I/O signal swing. Load capacitance of the DOUT
signal is 20 pF.
Figure 26. Audio Data Interface Timing
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
The PCM1801 operates with LRCK synchronized to the system clock (SCKI). The PCM1801 does not require a
specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If
the relationship between LRCK and SCKI changes more than 6 bit clocks (BCK) during one sample period due
to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and the digital output is forced to BPZ until
resynchronization between LRCK and SCKI is completed. In case of changes less than 5 bit clocks (BCK),
resynchronization does not occur and the previously described digital output control and discontinuity do not
occur. Figure 27 illustrates the ADC digital output for lost synchronization and resynchronization. During
undefined data, some noise may be generated in the audio signal. Also, the transition of normal to undefined
data and undefined or zero data to normal makes a discontinuity of data on the digital output and may generate
some noise in the audio signal.
15
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
Resynchronization
Synchronization Lost
Synchronous
Asynchronous
Synchronous
State of Synchronization
1/f
S
32/f
S
Undefined
Data
(1)
DOUT
Normal Data
Zero Data
Normal Data
T0020-02
(1) The transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appears
initially.
Figure 27. ADC Digital Output for Loss of Synchronization and Re-Synchronization
HPF Bypass Control
The built-in function for dc component rejection can be bypassed by BYPAS (pin 9) control (see Table 4). In
bypass mode, the dc component of the input analog signal, the internal dc offset, etc., are also converted and
output in the digital output data.
Table 4. HPF Bypass Control
BYPAS
HIGH-PASS FILTER (HPF) MODE
Normal (dc cut) mode
Bypass (through) mode
Low
High
APPLICATION INFORMATION
BOARD DESIGN AND LAYOUT CONSIDERATIONS
VCC, VDD PINS
The digital and analog power supply lines to the PCM1801 should be bypassed to the corresponding ground
pins with both 0.1-μF ceramic and 10-μF tantalum capacitors as close to the pins as possible to maximize the
dynamic performance of the ADC. Although the PCM1801 has two power lines to maximize the potential of
dynamic performance, using one common power supply is recommended to avoid unexpected power supply
problems, such as latch-up due to power supply sequencing.
AGND, DGND PINS
To maximize the dynamic performance of the PCM1801, the analog and digital grounds are not internally
connected. These points should have low impedance to avoid digital noise feedback into the analog ground.
They should be connected directly to each other under the PCM1801 package to reduce potential noise
problems.
VIN PINS
A 1.0-μF tantalum capacitor is recommended as an ac-coupling capacitor, which establishes a 5.3-Hz cutoff
frequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding a
series resistor to the VIN pins.
VREF PINS
To ensure low source impedance, 4.7-μF tantalum capacitors are recommended from VREF1 to AGND and from
VREF2 to AGND. These capacitors should be located as close as possible to the VREF1 and VREF2 pins to reduce
dynamic errors on the ADC references.
16
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SBAS131C–OCTOBER 2000–REVISED JULY 2007
APPLICATION INFORMATION (continued)
DOUT PIN
The DOUT pin has a large load-drive capability, but locating a buffer near the PCM1801 and minimizing load
capacitance is recommended in order to minimize the digital-analog crosstalk and maximize the dynamic
performance of the ADC.
FMT PIN
In general, the FMT pin is used for audio data format selection by tying up DGND or VDD in accordance with
interface requirements. If the application system cannot ensure an effective system clock prior to power up of
the PCM1801 when I2S format is required, then the FMT pin must be set HIGH after the power-on reset
sequence. This input control can be accomplished easily by connecting a C-R delay circuit with a delay time
greater than 1 ms to the FMT pin.
SYSTEM CLOCK
The quality of the system clock can influence dynamic performance in the PCM1801. The duty cycle, jitter, and
threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part,
the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure to
supply the audio clocks results in a power dissipation increase of up to three times normal dissipation and may
degrade long-term reliability if the maximum power dissipation limit is exceeded.
TYPICAL CIRCUIT CONNECTION DIAGRAM
Figure 28 is a typical connection diagram illustrating a circuit for which the input HPF cutoff frequency is about
5 Hz.
(3)
(3)
(1)
(1)
C
C
C
C
+
+
+
+
6
1
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
L
V
V
1
2
Lch In
Rch In
IN
REF
5
2
R
IN
REF
0 V
DGND
AGND
(2)
C
3
(2)
C
4
V
DD
V
+5 V
CC
System Clock
Data Clock
SCKI
BCK
FMT
BYPAS
DOUT
Format
Bypass
Pin Program
or Control
Audio
Data
Latch Enable
8
LRCK
Processor
Data Out
S0013-01
(1) C1 and C2: A 1-μF capacitor gives a 5.3-Hz (τ = 1 μF * 30 kΩ) cutoff frequency for the input HPF in normal operation
and requires a power-on setting time of 30 ms at power up.
(2) C3 and C4: Bypass capacitors, 0.1-μF ceramic and 10-μF tantalum or aluminum electrolytic, depending on layout
and power supply
(3) C5 and C6: 4.7-μF tantalum or aluminum electrolytic capacitors
Figure 28. Typical Circuit Connection
17
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM1801U
PCM1801U/2K
PCM1801U/2KG4
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
14
14
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-25 to 85
-25 to 85
PCM1801U
Samples
Samples
Samples
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
PCM1801U
PCM1801U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1801U/2K
SOIC
D
14
2000
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 14
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
PCM1801U/2K
D
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PCM1801U
D
14
50
506.6
8
3940
4.32
Pack Materials-Page 3
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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