PCM2706PJT [TI]
STEREO AUDIO DAC WITH USB INTERFACE, SINGLE-ENDED HEADPHONE OUTPUT AND S/PDF OUTPUT; 立体声音频， USB接口，单端耳机输出和S / PDF输出DAC
| 型号： | PCM2706PJT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | STEREO AUDIO DAC WITH USB INTERFACE, SINGLE-ENDED HEADPHONE OUTPUT AND S/PDF OUTPUT |
| 文件： | 总33页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLES081A − JUNE 2003 – REVISED MAY 2004
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D
Multiple Functions:
FEATURES
− Up to Eight Human Interface Device (HID)
Interfaces (Depending on Model and
Settings)
− Suspend Flag
− S/PDIF Out With SCMS
D
On-Chip USB Interface:
− With Full-Speed Transceivers
− Fully Compliant With USB 1.1
Specification
− Certified by USB-IF
− External ROM Interface (PCM2704/6)
− Serial Programming Interface (PCM2705/7)
− I S Interface (Selectable on PCM2706/7)
− Partially Programmable Descriptors
− Adaptive Isochronous Transfer for
Playback
2
D
Package:
− Bus-Powered or Self-Powered Operation
− Lead-Free Product
− 28-Pin SSOP (PCM2704/5)
− 32-Pin TQFP (PCM2706/7)
D
D
Sampling Rate: 32, 44.1, 48 kHz
On-Chip Clock Generator:
Single 12-MHz Clock Source
APPLICATIONS
D
Single Power Supply:
− Bus-Powered: 5 V, Typical (V
− Self-Powered: 3.3 V, Typical
D
D
D
D
D
USB Headphones
)
BUS
USB Audio Speaker
USB CRT/LCD Monitor
D
16-Bit Delta-Sigma Stereo DAC
− Analog Performance at 5 V (Bus),
3.3 V (Self):
USB Audio Interface Box
USB-Featured Consumer Audio Product
− THD+N: 0.006% (R > 10 kΩ,
L
DESCRIPTION
Self-Powered)
− THD+N: 0.025% (R = 32 Ω)
L
The PCM2704/5/6/7 is TI’s single-chip USB stereo audio
DAC with USB 1.1 compliant full-speed protocol controller
and S/PDIF. The USB-protocol controller works with no
software code, but USB descriptors can be modified in
some parts (for example, vendor ID/product ID) through
the use of an external ROM (PCM2704/6) SPI
− SNR: 98 dB
− Dynamic Range: 98 dB
− P : 12 mW (R = 32 Ω)
O
L
− Oversampling Digital Filter
− Pass-Band Ripple: ±0.04 dB
− Stop-Band Attenuation: –50 dB
− Single-Ended Voltage Output
− Analog LPF Included
†
(PCM2705/7) or on request. The PCM2704/5/6/7
employs SpAct architecture, TI’s unique system that
recovers the audio clock from USB packet data. On-chip
analog PLLs with SpAct enable playback with low clock
jitter.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
The modification of the USB descriptor through external ROM or SPI must comply with USB-IF guidelines, and the vendor ID must be your own
ID as assigned by the USB-IF. The descriptor also can be modified by changing a mask; please contact your representative for details.
SpAct is a trademark of Texas Instruments.
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ꢀꢠ ꢟ ꢫꢦꢥ ꢣ ꢜꢟ ꢝ ꢨꢠ ꢟ ꢥ ꢧ ꢤ ꢤ ꢜꢝ ꢱ ꢫꢟ ꢧ ꢤ ꢝꢟꢣ ꢝꢧ ꢥꢧ ꢤꢤ ꢢꢠ ꢜꢪ ꢰ ꢜꢝꢥ ꢪꢦꢫ ꢧ ꢣꢧ ꢤꢣꢜ ꢝꢱ ꢟꢞ ꢢꢪ ꢪ ꢨꢢ ꢠ ꢢꢡ ꢧꢣꢧ ꢠ ꢤꢬ
Copyright 2004, Texas Instruments Incorporated
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www.ti.com
SLES081A − JUNE 2003 – REVISED MAY 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
(1)
PACKAGE ORDERING INFORMATION
OPERATING
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE-LEAD PACKAGE CODE
PCM2704DB
PCM2704DBR
PCM2705DB
Tube
Tape and reel
Tube
PCM2704DB
PCM2705DB
PCM2706PJT
PCM2707PJT
SSOP-28
SSOP-28
TQFP-32
TQFP-32
28DB
28DB
32PJT
32PJT
–25°C to 85°C
–25°C to 85°C
–25°C to 85°C
–25°C to 85°C
PCM2704
PCM2705
PCM2706
PCM2707
PCM2705DBR
PCM2706PJT
PCM2706PJTR
PCM2707PJT
PCM2707PJTR
Tape and reel
Tray
Tape and reel
Tray
Tape and reel
(1)
For the most current specification and package information, refer to our Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNITS
V
V
V
–0.3 V to 6.5 V
–0.3 V to 4 V
±0.1 V
BUS
Supply voltage
, V
, V
, V
CCP CCL CCR DD
, V , V , V
Supply voltage differences
Ground voltage differences
CCP CCL CCR DD
PGND, AGNDL, AGNDR, DGND, ZGND
HOST
±0.1 V
–0.3 V to 6.5 V
Digital input voltage
Analog input voltage
D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT, SSPND, CK, DT,
PSEL, FSEL, TEST, TEST0, TEST1, FUNC0, FUNC1, FUNC2, FUNC3
–0.3 V to (V
+ 0.3) V < 4 V
DD
V
V
V
–0.3 V to (V
+ 0.3) V < 4 V
+ 0.3) V < 4 V
+ 0.3) V < 4 V
COM
CCP
R
OUT
–0.3 V to (V
CCR
CCL
L
OUT
–0.3 V to (V
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
±10 mA
–40°C to 125°C
–55°C to 150°C
150°C
Junction temperature
Lead temperature (soldering)
Package temperature (IR reflow, peak)
260°C, 5 s
260°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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www.ti.com
SLES081A − JUNE 2003 – REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
all specifications at T = 25°C, V
= 5 V, f = 44.1 kHz, f = 1 kHz,16-bit data, unless otherwise noted
IN
A
BUS
S
PCM2704DB, PCM2705DB,
PCM2706PJT, PCM2707PJT
PARAMETER
DIGITAL INPUT/OUTPUT
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Apply USB revision 1.1,
full-speed
Host interface
Audio data format
USB isochronous data format
INPUT LOGIC
V
V
V
V
2
–0.3
2
3.3
0.8
IH
IL
Input logic level
VDC
(1)
5.5
IH
(1)
IL
–0.3
0.8
(2)
I
I
I
I
V
IN
V
IN
V
IN
V
IN
= 3.3 V
= 0 V
±10
±10
100
±10
IH
(2)
IL
Input logic current
µA
= 3.3 V
= 0 V
65
IH
IL
OUTPUT LOGIC
(3)
V
V
V
V
I
I
I
I
= –2 mA
= 2 mA
2.8
2.4
OH
OH
OL
OH
OL
(3)
OL
0.3
0.4
Output logic level
VDC
= –2 mA
= 2 mA
OH
OL
CLOCK FREQUENCY
Input clock frequency, XTI
Sampling frequency
11.994
12
12.006
MHz
kHz
f
s
32, 44.1, 48
DAC CHARACTERISTICS
Resolution
16
Bits
Audio data channel
DC ACCURACY
1, 2
Channel
Gain mismatch, channel-to-channel
Gain error
±2
±2
±3
±8 % of FSR
±8 % of FSR
±6 % of FSR
Bipolar zero error
(4)
DYNAMIC PERFORMANCE
R
R
R
> 10 kΩ, self-powered
> 10 kΩ, bus-powered
= 32 Ω,
0.006%
0.012%
0.01%
0.02%
L
L
L
(5)
Line
THD+N,
V
OUT
= 0 dB
Headphone
0.025%
self-/bus-powered
THD+N, V
OUT
Dynamic range
= –60 dB
2%
98
98
70
EIAJ, A-weighted
EIAJ, A-weighted
90
90
60
dB
dB
dB
S/N ratio
Channel separation
(1)
(2)
(3)
(4)
HOST
D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI
FUNC0, FUNC1, FUNC2
f
= 1 kHz, using the System Twot Cascade audio measurement system by Audio Precisiont in the RMS mode with a 20-kHz LPF and 400-Hz
IN
HPF.
(5)
THD+N performance varies slightly depending on the effective output load, including dummy load R7, R8 in Figure 31.
System Two and Audio Precision are trademarks of Audio Precision, Inc.
3
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SLES081A − JUNE 2003 – REVISED MAY 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
all specifications at T = 25°C, V
= 5 V, f = 44.1 kHz, f = 1 kHz,16-bit data, unless otherwise noted
S IN
A
BUS
PCM2704DB, PCM2705DB,
PCM2706PJT, PCM2707PJT
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
ANALOG OUTPUT
Output voltage
0.55 V
, 0.55 V
Vp-p
V
CCL
CCR
Center voltage
0.5 V
CCP
Line
Headphone
AC coupling
10
16
kΩ
Ω
Load impedance
AC coupling
–3 dB
32
140
kHz
dB
LPF frequency
response
f = 20 kHz
–0.1
DIGITAL FILTER PERFORMANCE
Pass band
0.454 f
Hz
Hz
dB
dB
s
s
Stop band
0.546 f
s
Pass-band ripple
±0.04
Stop-band attenuation
Delay time
–50
20/f
s
POWER SUPPLY REQUIREMENTS
V
V
Bus-powered
Self-powered
DAC operation
4.35
3
5
3.3
23
5.25
3.6
BUS
, V
Voltage range
VDC
, V
, V
CCP CCL CCR DD
Line
30
mA
µA
Headphone
Line/headphone
Line
DAC operation (R = 32 Ω)
35
46
Supply current
L
(1)
Suspend mode
150
76
190
108
166
684
158
242
998
DAC operation
mW
µW
Power dissipation
(self-powered)
Headphone
Line/headphone
Line
DAC operation (R = 32 Ω)
116
495
115
175
750
L
(1)
Suspend mode
DAC operation
mW
µW
Power dissipation
(bus-powered)
Headphone
Line/headphone
DAC operation (R = 32 Ω)
L
(1)
Suspend mode
Internal power
V
, V
, V
, V
Bus-powered
3.2
3.35
3.5
VDC
CCP CCL CCR DD
(2)
supply voltage
TEMPERATURE RANGE
Operating temperature
–25
85
°C
28-pin SSOP (PCM2704/5)
32-pin TQFP (PCM2706/7)
100
80
θ
Thermal resistance
Under USB suspend state.
°C/W
JA
(1)
(2)
V
, V . These pins work as output pins of internal power supply for bus-powered operation.
, V
, V
DD CCP CCL CCR
4
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www.ti.com
SLES081A − JUNE 2003 – REVISED MAY 2004
PIN ASSIGNMENTS
PCM2704/PCM2705
DB PACKAGE
(TOP VIEW)
PCM2706/PCM2707
PJT PACKAGE
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTO
CK
DT
PSEL
DOUT
DGND
XTI
2
SSPND
TEST0
TEST1
HID2/MD
HID1/MC
HID0/MS
HOST
3
24 23 22 21 20 19 18 17
4
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
ZGND
PSEL
DT
CK
5
AGNDL
6
V
7
V
CCL
DD
V
V
L
R
XTO
XTI
8
D–
D+
OUT
9
V
OUT
CCP
10
11
12
13
14
V
PGND
V
SSPND
TEST
FSEL
BUS
CCR
ZGND
AGNDL
V
AGNDR
COM
AGNDR
V
COM
V
V
V
CCL
CCR
1
2
3
4
5
6
7
8
V
L
R
OUT
OUT
5
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www.ti.com
SLES081A − JUNE 2003 – REVISED MAY 2004
Terminal Functions (PCM2704DB/PCM2705DB)
TERMINAL
NAME
I/O
DESCRIPTION
Analog ground for headphone amplifier of L-channel
NO.
12
17
2
AGNDL
—
AGNDR
CK
—
Analog ground for headphone amplifier of R-channel
O
Clock output for external ROM (PCM2704). Must be left open (PCM2705).
(1)
D+
9
I/O USB differential input/output plus
(1)
I/O USB differential input/output minus
D–
8
DGND
DOUT
DT
6
—
O
Digital ground
S/PDIF output
5
(1)
I/O Data input/output for external ROM(PCM 2704). Must be left open with pullup resistor (PCM2705).
3
(3)
HID0/MS
HID1/MC
HID2/MD
HOST
22
23
24
21
I
I
I
I
HID key state input (mute), active HIGH (PCM2704). MS input (PCM2705).
HID key state input (volume up), active HIGH (PCM2704). MC input (PCM2705).
HID key state input (volume down), active HIGH (PCM2704). MD input (PCM2705).
(3)
(3)
). Max power select during bus-powered
Host detection during self-powered operation (connect to V
BUS
(2)
operation (LOW: 100 mA, HIGH: 500 mA).
PGND
PSEL
19
4
—
I
Analog ground for DAC, OSC and PLL
(1)
Power source select. (LOW: self-power, HIGH: bus-power)
SSPND
TEST0
TEST1
27
26
25
10
13
20
16
18
7
O
I
Suspend flag, active LOW (LOW: suspend, HIGH: operational)
(1)
(1)
Test pin. Must be set HIGH
Test pin. Must be set HIGH
I
V
V
V
V
V
V
V
V
—
—
—
—
—
—
O
O
I
Connect to USB power (V ) for bus-powered operation. Connect to V for self-powered operation.
BUS DD
BUS
CCL
CCP
CCR
COM
DD
(4)
Analog power supply for headphone amplifier of L-channel
(4)
Analog power supply for DAC, OSC and PLL
Analog power supply for headphone amplifier of R-channel
Common voltage for DAC (V
(4)
/2). Connect decoupling capacitor to PGND.
CCP
(4)
Digital power supply
L
OUT
14
15
28
1
DAC analog output for L-channel
DAC analog output for R-channel
R
OUT
(1)
Crystal oscillator input
XTI
XTO
O
—
Crystal oscillator output
ZGND
(1)
11
Ground for internal regulator
LV-TTL level
(2)
(3)
(4)
LV-TTL level, 5-V tolerant
LV-TTL level with internal pulldown
Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
6
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SLES081A − JUNE 2003 – REVISED MAY 2004
Terminal Functions (PCM2706PJT/PCM2707PJT)
TERMINAL
NAME
I/O
DESCRIPTION
Analog ground for headphone amplifier of L-channel
NO.
26
31
14
23
22
20
17
15
9
AGNDL
—
AGNDR
CK
—
Analog ground for headphone amplifier of R-channel
O
Clock output for external ROM (PCM2706). Must be left open (PCM2707).
(1)
D+
I/O USB differential input/output plus
(1)
I/O USB differential input/output minus
D–
DGND
DOUT
DT
—
O
Digital ground
S/PDIF output / I S data output
2
(1)
I/O Data input/output for external ROM (PCM2706). Must be left open with pullup resistor (PCM2707).
(1)
2
Function select (LOW: I S DATA output, HIGH: S/PDIF output)
FSEL
I
2 (3)
I/O HID key state input (next track), active HIGH (FSEL = 1). I S LR clock output (FSEL = 0).
FUNC0
FUNC1
FUNC2
FUNC3
HID0/MS
HID1/MC
HID2/MD
HOST
5
2
(3)
19
18
4
I/O HID key state input (previous track), active HIGH (FSEL = 1). I S bit clock output(FSEL = 0).
(3)
2
I/O HID key state input (stop), active HIGH (FSEL = 1). I S system clock output (FSEL = 0).
2
(3)
I
I
I
I
I
HID key state input (play/pause), active HIGH (FSEL = 1). I S data input (FSEL = 0).
(3)
6
HID key state input (mute), active HIGH (PCM2706). MS input (PCM2707)
HID key state input (volume up), active HIGH (PCM2706). MC input (PCM2707)
(3)
(3)
7
8
HID key state input (volume down), active HIGH (PCM2706)/MD input (PCM2707)
3
Host detection during self-powered operation. (connect to V
). Max power select during bus-powered
BUS
(2)
operation. (LOW: 100 mA, HIGH: 500 mA).
PGND
PSEL
1
—
I
Analog ground for DAC, OSC and PLL
(1)
16
11
10
24
27
2
Power source select. (LOW: self-power, HIGH: bus-power)
SSPND
TEST
O
I
Suspend flag, active LOW (LOW: suspend, HIGH: operational)
(1)
Test pin. Must be set HIGH
V
V
V
V
V
V
V
V
—
—
—
—
—
—
O
O
I
Connect to USB power (V ) for bus-powered operation. Connect to V for self-powered operation.
BUS DD
BUS
CCL
CCP
CCR
COM
DD
(4)
Analog power supply for headphone amplifier of L-channel
(4)
Analog power supply for DAC, OSC and PLL
Analog power supply for headphone amplifier of R-channel
Common voltage for DAC (V
(4)
30
32
21
28
29
12
13
25
/2). Connect decoupling capacitor to PGND.
CCP
(4)
Digital power supply
L
DAC analog output for L-channel
DAC analog output for R-channel
OUT
OUT
R
(1)
Crystal oscillator input
XTI
XTO
O
—
Crystal oscillator output
ZGND
(1)
Ground for internal regulator
LV-TTL level
(2)
(3)
(4)
LV-TTL level, 5-V tolerant
LV-TTL level with internal pulldown
Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
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BLOCK DIAGRAM (PCM2704DB/PCM2705DB)
V
CCP
V
CCL
V
CCR
V
DD
PGND
AGNDL AGNDR DGND
ZGND
Power
Manager
SSPND
5-V to 3.3-V
Voltage Regulator
V
BUS
V
COM
USB
Protocol
Controller
Analog
PLL
V
OUT
L
DAC
D+
D–
Control
Endpoint
V R
OUT
S/PDIF Encoder
DOUT
EEPROM
Interface
CK
DT
†
ISO-Out
Endpoint
FIFO
HOST
HID0/MS
HID1/MC
HID2/MD
HID
Endpoint
SPI
Interface
PSEL
‡
TEST0
TEST1
96 MHz
Tracker
(SpAct)
PLL (×8)
XTI 12 MHz XTO
†
‡
Applies to PCM2704DB
Applies to PCM2705DB
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BLOCK DIAGRAM (PCM2706PJT/PCM2707PJT)
V
CCP
V
CCL
V
CCR
V
DD
PGND
AGNDL AGNDR DGND
ZGND
Power
Manager
SSPND
5-V to 3.3-V
Voltage Regulator
V
BUS
V
COM
USB
Protocol
Controller
Analog
PLL
V
OUT
L
DAC
D+
D–
Control
Endpoint
V R
OUT
S/PDIF
Encoder
DOUT
FSEL
DOUT
LRCK
BCK
FUNC0
FUNC1
FUNC2
FUNC3
2
I S I/F
EEPROM
Interface
CK
DT
SYSCK
DIN
†
ISO-Out
Endpoint
FIFO
HOST
†
HID3: Next Trackt
†
HID4: Previous Trackt
HID0/MS
HID1/MC
HID2/MD
†
HID
Endpoint
SPI
Interface
HID5: Stop
‡
†
HID6: Play/Pause
PSEL
TEST
96 MHz
Tracker
(SpAct)
PLL (×8)
XTI 12 MHz XTO
†
‡
Applies to PCM2706PJT
Applies to PCM2707PJT
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
DAC DIGITAL INTERPOLATION FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0.05
0.04
0
−20
0.03
−40
0.02
0.01
−60
0.00
−80
−0.01
−0.02
−0.03
−0.04
−0.05
−100
−120
−140
0.0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
f – Frequency [× f ]
f – Frequency [× f ]
S
S
Figure 1. Frequency Response
Figure 2. Pass-Band Ripple
DAC ANALOG LOW-PASS FILTER FREQUENCY RESPONSE
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0.0
−0.5
−1.0
−1.5
−2.0
0
−20
−40
−60
−80
0.01
0.1
1
10
100
1
10
100
1k
10k
f – Frequency – kHz
f – Frequency – kHz
Figure 3. Pass-Band Characteristics
Figure 4. Stop-Band Characteristics
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
S
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TYPICAL PERFORMANCE CURVES
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.05
0.04
0.03
0.02
0.01
0.00
0.05
0.04
0.03
0.02
0.01
0.00
Self-Powered
Bus-Powered
= 0 dB
V
OUT
= 0 dB
V
OUT
32 Ω
32 Ω
10 kΩ
10 kΩ
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 5
Figure 6
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0.05
0.04
0.03
0.02
0.01
0.00
0.05
0.04
0.03
0.02
0.01
0.00
Self-Powered
Bus-Powered
V
OUT
= 0 dB
V
OUT
= 0 dB
32 Ω
32 Ω
10 kΩ
10 kΩ
4.0
4.5
5.0
5.5
3.0
3.1
3.2
3.3
3.4
3.5
3.6
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 8
Figure 7
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
S
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ꢀ
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ꢂ
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ꢄ
ꢅ
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ꢀ
ꢁ
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TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
SAMPLING FREQUENCY
SAMPLING FREQUENCY
0.05
0.04
0.03
0.02
0.01
0.00
0.05
0.04
0.03
0.02
0.01
0.00
Self-Powered
Bus-Powered
= 0 dB
V
OUT
= 0 dB
V
OUT
32 Ω
32 Ω
10 kΩ
10 kΩ
30
35
40
45
50
30
35
40
45
50
f
S
– Sampling Frequency – kHz
f
S
– Sampling Frequency – kHz
Figure 9
Figure 10
DYNAMIC RANGE and SNR
vs
DYNAMIC RANGE and SNR
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
105
103
101
99
105
103
101
99
Bus-Powered
Self-Powered
Dynamic Range
Dynamic Range
SNR
97
97
SNR
95
−50
95
−50
−25
0
25
50
75
100
−25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 11
Figure 12
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
S
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DYNAMIC RANGE and SNR
vs
DYNAMIC RANGE and SNR
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
105
103
101
99
105
Self-Powered
Bus-Powered
103
101
99
Dynamic Range
SNR
Dynamic Range
SNR
97
97
95
3.0
95
4.0
3.1
3.2
3.3
3.4
3.5
3.6
4.5
5.0
5.5
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 13
Figure 14
DYNAMIC RANGE and SNR
vs
SAMPLING FREQUENCY
DYNAMIC RANGE and SNR
vs
SAMPLING FREQUENCY
105
103
101
99
105
103
101
99
Self-Powered
Bus-Powered
Dynamic Range
Dynamic Range
SNR
SNR
97
97
95
95
30
35
40
45
50
30
35
40
45
50
f
S
– Sampling Frequency – kHz
f
S
– Sampling Frequency – kHz
Figure 15
Figure 16
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
S
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ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
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ꢇ
ꢀ
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SUSPEND CURRENT
vs
FREE-AIR TEMPERATURE
SUSPEND CURRENT
vs
SUPPLY VOLTAGE
200
150
100
50
200
150
100
50
0
−50
0
4.0
−25
0
25
50
75
100
4.5
5.0
5.5
T
A
– Free-Air Temperature – °C
V
BUS
– Supply Voltage – V
Figure 17
Figure 18
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
20
40
60
80
100
120
0
5
10
15
20
f – Frequency – kHz
f – Frequency – kHz
Figure 19. Output Spectrum (–60 dB, N = 8192)
Figure 20. Output Spectrum (–60 dB, N = 8192)
All specifications at T = 25°C, V
BUS
= 5 V, f = 44.1 kHz, f = 1 kHz, 16-bit data, unless otherwise noted.
IN
A
S
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DETAILED DESCRIPTION
CLOCK AND RESET
For both USB function and audio function, the PCM2704/5/6/7 requires a 12-MHz (±500 ppm) clock, which can be
generated by the built-in oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be
connected to XTI (pin 28 for PCM2704/5, pin 12 for PCM2706/7) and XTO (pin 1 for PCM2704/5, pin 13 for
PCM2706/7) with one large (1-MΩ) resistor and two small capacitors, the capacitance of which depends on the
specified load capacitance of the crystal resonator. An external clock can be supplied from XTI (pin 28 for
PCM2704/5, pin 12 for PCM2706/7). If an external clock is supplied, XTO (pin 1 for PCM2704/5, pin 13 for
PCM2706/7) must be left open. Because no clock disabling pin is provided, it is not recommended to use the external
clock supply. SSPND (pin 27 for PCM2704/5, pin 11 for PCM2706/7) is unable to use clock disabling.
The PCM2704/5/6/7 has an internal power-on reset circuit, and it works automatically when V
(pin 7 for
(pin 10 for
DD
PCM2704/5, pin 21 for PCM2706/7) exceeds 2 V typical (1.6 V–2.4 V), which is equivalent to V
BUS
PCM2704/5, pin 24 for PCM2706/7) exceeding 3 V typical for bus-powered applications. About 700 µs is required
until internal reset release.
OPERATION MODE SELECTION
The PCM2704/5/6/7 has the following mode-select pins.
Power Configuration Select/Host Detection
PSEL (pin 4 for PCM2704/5, pin 16 for PCM2706/7) is dedicated to selecting the power source. This selection affects
the configuration descriptor. While in bus-powered operation, maximum power consumption from the V
is
BUS
determined by HOST (pin 21 for PCM2704/5, pin 3 for PCM2706/7). For self-powered operation, HOST must be
connected to V of the USB bus with a pulldown resistor to detect attach and detach. (To avoid excessive suspend
BUS
current, the pulldown should be a high-value resistor.)
Table 1. Power Configuration Select
PSEL
DESCRIPTION
Self-powered
Bus-powered
0
1
HOST
DESCRIPTION
0
1
Detached from USB (self-powered)/100 mA (bus-powered)
Attached to USB (self-powered)/500 mA (bus-powered)
Function Select (PCM2706/7)
2
FSEL (pin 9) determines the function of FUNC0–FUNC3 (pins 4, 5, 18, and 19) and DOUT (pin17). When the I S
interface is required, FSEL must be set to LOW. Otherwise, FSEL must be set to HIGH.
Table 2. Function Select
FSEL
DOUT
FUNC0
FUNC1
FUNC2
FUNC3
2
2
2
2
2
0
1
Data out (I S)
LRCK (I S)
BCK (I S)
SYSCK (I S)
(1)
Data in (I S)
(1)
(1)
(1)
Play/pause (HID)
S/PDIF data
Next track (HID)
Previous track (HID)
Stop (HID)
(1)
Valid on the PCM2706; no function assigned on the PCM2707.
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USB INTERFACE
Control data and audio data are transferred to the PCM2704/5/6/7 via D+ (pin 9 for PCM2704/5, pin 23 for
PCM2706/7) and D– (pin 8 for PCM2704/5, pin 22 for PCM2706/7). D+ should be pulled up with a 1.5-kΩ (±±5%
resistor. To avoid back voltage in self-powered operation, the device must not provide power to the pullup resistor
on D+ while V
of the USB port is inactive.
BUS
All data to/from the PCM2704/5/6/7 are transferred at full speed. The following information is provided in the device
descriptor. Some parts of the device descriptor can be modified through external ROM (PCM2704/6), SPI
(PCM2705/7), or internal mask ROM on request.
Table 3. Device Descriptor
USB revision
1.1 compliant
Device class
0x00 (device defined interface level)
0x00 (not specified)
Device subclass
Device protocol
Max packet size for endpoint 0
Vendor ID
0x00 (not specified)
8 bytes
0x08BB (default value, can be modified)
Product ID
0x2704/0x2705/0x2706/0x2707 (These values correspond to the model number, and the value can be
modified.)
Device release number
Number of configurations
Vendor strings
1.0 (0x0100)
1
“Burr-Brown from TI” (default value, can be modified)
“USB Audio DAC” (default value, can be modified)
Not supported
Product strings
Serial number
The following information is contained in the configuration descriptor. Some parts of the configuration descriptor can
be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or on request.
Table 4. Configuration Descriptor
Interface
Three interfaces
Power attribute
Max power
0x80 or 0xC0 (bus-powered or self-powered, depending on PSEL; no remote wake up. This value can be modified.)
0x0A, 0x32 or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending on PSEL and HOST. This
value can be modified.)
The following information is contained in the string descriptor. Some parts of the string descriptor can be modified
through external ROM (PCM2704/6), SPI (PCM2705/7), or on request.
Table 5. String Descriptor
#0
#1
#2
0x0409
Burr-Brown from TI (default value, can be modified)
USB Audio DAC (default value, can be modified)
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Device Configuration
Figure 21 illustrates the USB audio function topology. The PCM2704/5/6/7 has three interfaces. Each interface is
enabled by some alternative settings.
Endpoint #0
Default
Endpoint
FU
Endpoint #2
IT
TID1
OT
TID2
(IF #1)
Analog Out
Audio Streaming
Interface
UID3
Standard Audio Control Interface (IF #0)
Endpoint #5
(IF #2)
HID Interface
PCM2704/5/6/7
Figure 21. USB Audio Function Topology
Interface #0 (Default/Control Interface)
Interface #0 is the control interface. Setting #0 is the only possible setting for interface #0. Setting #0 describes the
standard audio control interface. Audio control interface consists of a terminal. The PCM2704/5/6/7 has three
terminals as follows.
D
D
D
Input terminal (IT #1) for isochronous-out stream
Output terminal (OT #2) for audio analog output
Feature unit (FU #3) for DAC digital attenuator
Input terminal #1 is defined as a USB stream (terminal type 0x0101). Input terminal #1 can accept two-channel audio
streams constructed of left and right channels. Output terminal #2 is defined as a speaker (terminal type 0x0301).
Feature unit #3 supports the following sound control features.
D
D
Volume control
Mute control
The built-in digital volume controller can be manipulated by an audio-class-specific request from 0 dB to –64 dB in
steps of 1 dB. Changes are made by incrementing or decrementing one step (1 dB) for every 1/f time interval until
S
the volume level reaches the requested value. Each channel can be set to a separate value. The master volume
control is not supported. A request to the master volume is stalled and ignored. The built-in digital mute controller
can be manipulated by an audio-class-specific request. A master mute control request is acceptable. A mute control
2
request to an individual channel is stalled and ignored. The digital volume control does not affect the S/PDIF and I S
outputs (PCM2706/7).
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Interface #1 (Isochronous-Out Interface)
Interface #1 is for the audio-streaming data-out interface. Interface #1 has the following three alternative settings.
Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operational settings.
ALTERNATIVE
SETTING
TRANSFER
MODE
SAMPLING RATE
(kHz)
DATA FORMAT
00
01
02
Zero bandwidth
2s complement (PCM)
2s complement (PCM)
16-bit
16-bit
stereo
mono
Adaptive
Adaptive
32, 44.1, 48
32, 44.1, 48
Interface #2 (HID Interface)
Interface #2 is the interrupt-data-in interface. Interface #2 comprises the HID consumer control device. Alternative
setting #0 is the only possible setting for interface #2.
On the HID device descriptor, eight HID items are reported as follows for any model, in any configuration.
Basic HID operation
Interface #2 can report the following three key statuses for any model. These statuses can be set by the HID0–HID2
pins (PCM2704/6) or the SPI port (PCM2705/7).
D
D
D
Mute (0xE2)
Volume up (0xE9)
Volume down (0xEA)
Extended HID operation (PCM2705/6/7)
By using the FUNC0–FUNC3 pins (PCM2706) or the SPI port (PCM2705/7), the following additional conditions can
be reported to the host.
D
D
D
D
Play/Pause (0xCD)
Stop (0xB7)
Previous (0xB6)
Next (0xB5)
Auxiliary HID status report (PCM2705/7)
One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI command
or external ROM. This definition must be described as on the report descriptor with a three-byte usage ID. AL A/V
Capture (0x0193) is assigned as the default for this status flag.
Endpoints
The PCM2704/5/6/7 has three endpoints as follows.
D
D
D
Control endpoint (EP #0)
Isochronous-out audio data-stream endpoint (EP #2)
HID endpoint (EP #5)
The control endpoint is a default endpoint. The control endpoint is used to control all functions of the PCM2704/5/6/7
by standard USB request and USB audio-class-specific request from the host. The isochronous-out audio data
stream endpoint is an audio sink endpoint, which receives the PCM audio data. The isochronous-out audio data
stream endpoint accepts the adaptive transfer mode. The HID endpoint is an interrupt-in endpoint. The HID endpoint
reports HID status every 10 ms.
The HID endpoint is defined as a consumer control device. The HID function is designed as an independent endpoint
from the isochronous-out endpoint. This means that the effect of HID operation depends on host software. Typically,
the HID function is used to control the primary audio-out device.
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DAC
The PCM2704/5/6/7 has a DAC that uses an oversampling technique with 128-f second-order multibit noise
S
shaping. This technique provides extremely low quantization noise in the audio band, and the built-in analog low-pass
filter removes the high-frequency components of the noise-shaping signal. DAC outputs are provided through the
headphone amplifier V
L and V
R can provide 12 mW at 32 Ω as well as 1.8 Vp-p into a 10-kΩ load.
OUT
OUT
DIGITAL AUDIO INTERFACE – S/PDIF OUTPUT
The PCM2704/5/6/7 employs S/PDIF output. Isochronous-out data from the host is encoded to S/PDIF output DOUT
as well as to DAC analog outputs V
Monaural data is converted to the stereo format at the same data rate. S/PDIF output is not supported in the I S I/F
enable mode.
L and V
R. Interface format and timing follows the IEC-60958 standard.
OUT
OUT
2
Channel Status Information
The channel status information is fixed as consumer application, PCM mode, copyright, digital/digital converter. All
other bits are fixed as 0s except for the sample frequency, which is set automatically according to the data received
through the USB.
Copyright Management
Digital audio data output is always encoded as original with SCMS control. Only one generation of digital duplication
is allowed. The implementation of this feature is optional. Note that it is your responsibility for determining whether
to implement this feature in your product or not.
2
DIGITAL AUDIO INTERFACE – I S INTERFACE OUTPUT (PCM2706/7)
2
2
The PCM2706 and PCM2707 can support the I S interface, which is enabled by FSEL (pin 9). In the I S interface
enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT, respectively. They
2
2
provide digital output/input data in the16-bit I S format, which is also accepted by the internal DAC. I S interface
format and timing are shown in Figure 22 and Figure 23.
1/f
S
LRCK
BCK
R−Channel
L−Channel
(64 f )
S
1
1
2
3
14 15 16
LSB
1
1
2
3
14 15 16
LSB
1
1
2
2
DOUT
DIN
MSB
MSB
2
3
14 15 16
LSB
2
3
14 15 16
LSB
MSB
MSB
Figure 22. Audio Data Input Format
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50% of V
SLES081A − JUNE 2003 – REVISED MAY 2004
LRCK (Output)
DD
DD
DD
t
(BCL)
t
t
t
(BCH)
(BL)
50% of V
BCK (Output)
t
(BCY)
t
(BD)
(LD)
DOUT (Output)
50% of V
t
(DS)
t
(DH)
DIN (Input)
SYMBOL
50% of V
DD
PARAMETER
MIN
300
MAX
UNIT
t
BCK pulse cycle time
ns
ns
ns
ns
ns
ns
ns
ns
(BCY)
t
BCK pulse duration, HIGH
BCK pulse duration, LOW
100
100
–20
–20
–20
20
(BCH)
t
(BCL)
t
LRCK delay time from BCK falling edge
DOUT delay time from BCK falling edge
DOUT delay time from LRCK edge
DIN setup time
40
40
40
(BL)
t
(BD)
t
(LD)
(DS)
(DH)
t
t
DIN hold time
20
NOTE: Load capacitance is 20 pF.
Figure 23. Audio Interface Timing
EXTERNAL ROM DESCRIPTOR (PCM2704/6)
The PCM2704/6 supports an external ROM interface to override internal descriptors. Pin 3 (for PCM2704)/pin 15
(for PCM2706) is assigned as DT (serial data) and pin 2 (for PCM2704)/pin 14 (for PCM2706) is assigned as CK
2
(serial clock) of the I C interface when using the external ROM descriptor. Descriptor data is transferred from the
2
external ROM to the PCM2704/6 through the I C interface the first time when the device activates after power-on
reset. Before completing a read of the external ROM, the PCM2704/6 replies with NACK for any USB command
request from the host to the device itself. The descriptor data, which can be in external ROM, are as follows. String
descriptors must be described in ANSI ASCII code (1 byte for each character). String descriptors are automatically
converted to unicode strings for transmission to the host. The device address of the external ROM is fixed as 0xA0.
The data must be stored from address 0x00 and must consist of 57 bytes as described in the following items. Read
operation is performed at a cycle of XTI/384 (approximately 30 kHz).
D
D
D
D
D
D
D
Vendor ID (2 bytes)
Product ID (2 bytes)
Device string (16 bytes in ANSI ASCII code)
Vendor string (32 bytes in ANSI ASCII code)
Maximum power (1 byte)
Power attribute (1 byte)
Auxiliary HID usage ID in report descriptor (3 bytes)
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DT
CK
S
1−7
8
9
1−8
9
1−8
9
9
P
Device Address R/W
ACK
DATA
ACK
DATA
ACK
NACK
Start Condition
Stop Condition
R/W: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgement of a Byte if 0
DATA: 8 Bits (Byte)
NACK: Not Acknowledgement if 1
M
M
M
S
S
M
S
M
S
M
M
S
Device address
R/W
ACK
DATA
ACK
DATA
ACK
...
NACK
P
Read Operation
Figure 24. External ROM Read Operation
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TIMING DIAGRAM
Start
Repeated Start
(D-HD)
Stop
t
t
(DT-F)
t
t
t
t
(P-SU)
(BUF)
(D-SU)
(DT-R)
DT
t
t
(RS-HD)
(CK-R)
t
(LOW)
CK
t
t
t
(RS-SU)
(S-HD)
(HI)
t
(CK-F)
SYMBOL
PARAMETER
MIN
MAX
UNIT
kHz
µs
f
CK clock frequency
100
(CK)
t
Bus free time between STOP and START condition
Low period of the CK clock
4.7
4.7
4
(BUF)
t
µs
(LOW)
t
High period of the CK clock
µs
(HI)
t
Setup time for START/repeated START condition
4.7
µs
(RS-SU)
t
(S-HD)
Hold time for START/repeated START condition
4
µs
t
(RS-HD)
t
Data setup time
250
0
ns
ns
ns
ns
ns
ns
µs
pF
V
(D-SU)
t
Data hold time
900
(D-HD)
t
Rise time of CK signal
Fall time of CK signal
Rise time of DT signal
Fall time of DT signal
Setup time for STOP condition
Capacitive load for DT and CK line
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
4
1000
1000
1000
1000
(CK-R)
B
B
B
B
t
t
(CK-F)
(DT-R)
t
(DT-F)
t
(P-SU)
C
B
400
V
NH
Noise margin at HIGH level for each connected device (including hysteresis)
0.2 V
DD
Figure 25. External ROM Read Interface Timing Requirements
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EXTERNAL ROM EXAMPLE
Here is an example of external ROM data, with an explanation of the example following the data.
0xBB, 0x08, 0x04, 0x27,
0x50, 0x72, 0x6F, 0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E,
0x56, 0x65, 0x6E, 0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61,
0x72, 0x65, 0x20, 0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20,
0x80,
0x7D,
0x0A, 0x93, 0x01
The data is stored beginning at address 0x00.
Vendor ID: 0x08BB
Device ID: 0x2704
Device string: Product strings. (16 bytes)
Vendor string: Vendor strings are placed here. (32 bytes, 31 visible characters are followed by 1 space)
bmAttribute: 0x80 (Bus-powered)
maxPower: 0x7D (250 mA)
Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture)
SERIAL PROGRAMMING INTERFACE (PCM2705/7)
The PCM2705/7 supports the serial programming interface (SPI) to program the descriptor and to set the HID state.
Descriptor data is described in the External ROM Descriptor section.
t
(MHH)
MS
50% of V
DD
t
t
(MCL)
(MLS)
t
t
(MLH)
(MCH)
MC
MD
50% of V
50% of V
DD
t
(MCY)
LSB
DD
t
(MDS)
t
(MDH)
SYMBOL
PARAMETERS
MIN
100
TYP
MAX UNITS
t
t
t
t
t
t
t
t
MC pulse cycle time
MC low-level time
MC high-level time
MS high-level time
ns
ns
ns
ns
ns
ns
ns
ns
(MCY)
(MCL)
(MCH)
(MHH)
(MLS)
(MLH)
(MDH)
(MDS)
50
50
100
20
MS falling edge to MC rising edge
MS hold time
20
MD hold time
15
MD setup time
20
Figure 26. SPI Timing Diagram
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(1) Single Write Operation
16-Bits
MS
MC
MD
MSB
LSB
MSB
(2) Continuous Write Operation
16-Bits x N Frames
MS
MC
MD
MSB
LSB
MSB
LSB
MSB
LSB
N Frames
Figure 27. SPI Write Operation
SPI REGISTER (PCM2705/7)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
D7
0
0
0
0
ST
0
ADDR
0
D0
D1
D2
D3
D4
D5
D6
D[7:0]
Function of the lower 8 bits depends on the value of the ST (B11) bit.
ST = 0 (HID status write)
D7
D6
D5
D4
D3
D2
D1
D0
Reports MUTE HID status to the host (active high)
Reports volume-up HID status to the host (active high)
Reports volume-down HID status to the host (active high)
Reports next-track HID status to the host (active high)
Reports previous-track HID status to the host (active high)
Reports stop HID status to the host (active high)
Reports play/pause HID status to the host (active high)
Reports extended command status to the host (active high)
ST = 1 (ROM data write)
D[7:0] Internal descriptor ROM data
ADDR
Starts write operation for internal descriptor reprogramming (active high)
456 bits of ROM data, (described in the External ROM Example section) must be provided when this bit is asserted.
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active when ST is set low.
ST
Determines the function of the lower 8-bit data as follows
0: HID status write
1: Descriptor ROM data write
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Functionality of ST and ADDR Bit Combinations
ST
0
ADDR
FUNCTION
0
1
0
1
HID status write
0
HID status write and descriptor ROM address read
Descriptor ROM data write
Reserved
1
1
USB HOST INTERFACE SEQUENCE
Power-On, Attach, and Playback Sequence
The PCM2704/5/6/7 is ready for setup when the reset sequence has finished and the USB bus is attached. After a
connection has been established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. While waiting for
the audio data (idle state), the analog output is set to bipolar zero (BPZ).
When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains 1 ms of audio data,
into the internal storage buffer. The PCM2704/5/6/7 starts playing the audio data after detecting the next subsequent
start-of-frame (SOF) packet.
3.3 V
(Typ.)
V
DD
2.0 V (Typ.)
0 V
st
1
nd
2 Audio Data
Bus Reset
Set Configuration
Audio Data
Bus Idle
D+/D−
SOF
SOF
SOF
SSPND
BPZ
V
L
R
OUT
V
OUT
Device Setup
1 ms
700 µs
Internal Reset
Ready for Setup
Ready for Playback
Figure 28. Initial Sequence
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Play, Stop, and Detach Sequence
When host finishes or aborts the playback, the PCM2704/5/6/7 stops the playing after last audio data has played.
Suspend and Resume Sequence
The PCM2704/5/6/7 enters the suspend state after the USB bus has been in a constant idle state for approximately
5 ms. While the PCM2704/5/6/7 is in the suspend state, SSPND flag (pin 27 for PCM2704/5, pin 11 for PCM2706/7)
is asserted. The PCM2704/5/6/7 wakes up immediately when detecting the non-idle state on the USB bus.
V
BUS
Audio Data
Audio Data
Last Audio Data
SOF
D+/D–
SOF
SOF
SOF
SOF
V
L
R
OUT
V
OUT
Detach
1 ms
Figure 29. Play, Stop, and Detach
Idle
D+/D−
SSPND
5 ms
Suspend
V
L
R
OUT
V
OUT
Active
Active
2.5 ms
Figure 30. Suspend and Resume
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TYPICAL CIRCUIT CONNECTION 1 (EXAMPLE OF USB SPEAKER)
Figure 31 illustrates a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application.
X
1
C
1
C
2
R
1
PCM2704DB
External ROM
(Optional)
XTO
CK
XTI
1
2
28
27
26
25
SUSPEND
SCL
SDA
SSPND
TEST0
TEST1
DT
3
R
9
PSEL
DOUT
DGND
4
S/PDIF OUT
5
HID2/MD 24
HID1/MC 23
HID0/MS 22
VOLUME–
VOLUME+
MUTE
6
USB ’B’
Connector
C
7
R
2
7
V
DD
R
R
3
D–
D+
D–
D+
HOST
8
21
20
C
4
4
V
CCP
9
V
10
V
PGND 19
BUS
BUS
C
3
C
8
+
GND
11 ZGND
V
COM
18
17
16
15
AGNDL
AGNDR
12
13
14
C
6
C
5
V
CCL
V
CCR
C
+
C
13
9
+
+
V
OUT
L
V R
OUT
+
C
11
C
12
C
10
C
14
TPA200X
Power
Amp
R
5
R
6
R
7
R
8
Notes:
X : 12-MHz crystal resonator
1
C , C : 10-pF to 33-pF (depending on load capacitance of crystal resonator)
1
2
C , C , C , C C : 1-µF ceramic
3
8
4
5
6,
7
C : 47-µF electrolytic
C , C : 100-µF electrolytic (depending on tradeoff between required frequency response and discharge time for resume)
9
10
C
C
, C : 0.022-µF ceramic
11 12
13 14
, C : 1-µF electrolytic
R : 1 MW
1
R , R : 1.5 kW
2
9
4
6
R , R : 22 W
3
R , R : 16 W
5
R , R : 330 W (depending on tradeoff between required THD performance and pop-noise level for suspend)
7
8
Output impedance of V
L and V
OUT
OUT
9
10
External ROM power can be supplied from V
Figure 31. Bus-Powered Application
Note that the circuit illustrated above is for information only. Whole-board design should be considered to meet the
USB specification as a USB-compliant product.
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TYPICAL CIRCUIT CONNECTION 2 (EXAMPLE OF REMOTE HEADPHONE)
Figure 32 illustrates a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs.
C
+
9
Headphone
+
C
11
C
12
C
10
R
5
R
6
R
7
R
8
R
9
R
10
C
6
+
C
3
C
4
32 31 30 29 28 27 26 25
USB ’B’
Connector
R
2
C
5
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PGND
V
V
BUS
D+
BUS
R
3
V
D+
CCP
HOST
D–
D–
PLAY/PAUSE
NEXT TRACK
R
4
FUNC3
V
GND
DD
PCM2706PJT
C
8
C
FUNC0
7
DGND
FUNC1
FUNC2
DOUT
MUTE
PREVIOUS TRACK
HID0/MS
HID1/MC
HID2/MD
VOLUME+
STOP
VOLUME–
External ROM
(Optional)
9
10 11 12 13 14 15 16
SDA
R
11
SUSPEND
SCL
R
1
X
1
C
1
C
2
Notes:
C
, C : 0.022-µF ceramic
11 12
X : 12-MHz crystal resonator
R : 1 MW
1
1
C , C : 10-pF to 33-pF (depending on load capacitance of crystal
R , R : 1.5 kW
1
2
2
11
resonator)
R , R : 22 W
3 4
C , C , C , C , C : 1-µF ceramic
R , R : 16 W
3
4
5
7
8
5
6
C : 47-µF electrolytic
R , R , R , R : 3.3 kW
6
7
8
9
10
C , C : 100-µF electrolytic (depending on required frequency
External ROM power can be supplied from V
, but any other active
, or V as a power source.
9
10
CCP
response)
componentmust not use V
, V
, V
CCP CCL CCR DD
Figure 32. Bus-Powered Application
Note that the circuit illustrated above is for information only. Whole board design should be considered to meet the
USB specification as a USB-compliant product.
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TYPICAL CIRCUIT CONNECTION 3 (EXAMPLE OF DSP SURROUND PROCESSING AMP)
2
Figure 33 illustrates a typical circuit connection for an I S- and SPI-enabled self-powered application.
C
8
Headphone
+
+
C
10
C
11
C
9
R
6
R
7
R
8
R
9
R
10
R
11
C
6
+
C
3
C
4
32 31 30 29 28 27 26 25
USB ’B’
Connector
R
2
C
5
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PGND
V
V
BUS
D+
BUS
R
R
3
TAS300X
I S I/F Audio Device
V
D+
CCP
2
HOST
D–
D–
DIN
4
R
12
FUNC3
V
GND
DD
+
PCM2707PJT
C
7
LRCK
MS
FUNC0
DGND
FUNC1
FUNC2
DOUT
BCK
HID0/MS
HID1/MC
HID2/MD
MC
SYSTEM CLOCK
DOUT
MD
9
10 11 12 13 14 15 16
R
5
SUSPEND
R
1
X
1
Power
3.3 V
C
C
2
1
GND
Notes:
X : 12-MHz crystal resonator
C , C : 100-µF electrolytic (depending on required frequency
8 9
response)
C , C : 0.022-µF ceramic
10 11
1
C , C : 10-pF to 33-pF (depending on load capacitance of crystal
1
2
resonator)
R , R : 1 MW
1
12
R , R : 1.5 kW
C , C : 1-µF ceramic
3
4
2
5
C : 0.1-µF ceramic and 10-µF electrolytic
R , R : 22 W
5
3 4
C , C : 47-µF electrolytic
R , R : 16 W
6 7
6
7
R , R , R , R : 3.3 kW
8
9
10 11
SPI host (DSP) must have responsibility to handle D+ pullup if descriptor is programmed by SPI. SPI host must not activate D+ pullup until all internal
registers have been set. D+ pullup must not be activated while detaching from host.
D+must not activate (HIGH: 3.3 V) before programming of the PCM2707 by SPI is completed.
D+must not activate (HIGH: 3.3 V) while the device is detached from the USB.
V
BUS
of the USB can be used to detect USB bus power status. (Note that V of the USB connector is 5 V.)
BUS
Figure 33. Self-Powered Application
Note that the circuit illustrated above is for information only. Whole board design should be considered to meet the
USB specification as a USB-compliant product.
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APPENDIX
OPERATING ENVIRONMENT
For appropriate operation, one of the following operating systems must be running on a host PC equipped with a USB
port certified by the manufacturer. If these conditions are met, the operation of the PCM2704/5/6/7 does not depend
on the operating speed of the CPU. Texas Instruments has tested and confirmed the following listed operating
environments. The PCM2704/5/6/7 may work with other PCs and operating systems also, but proper operation using
them has not been tested and cannot be assured by TI.
Operating System
D
Microsoftt Windowst 98SE/Windows Met Japanese/English edition (For Windows 98SE and Windows Me,
the HID function is not fully functional with the default class driver.)
D
Microsoft Windows 2000 Professional Japanese/English edition
D
Microsoft Windows XPt Home/Professional Japanese/English edition (For Windows XP, use the latest version
of the USB audio driver, which is available on the Windows update site, or apply Service Pack 1. See the Q310507
white paper available from Microsoft.)
D
D
D
Apple Computer Mac OSt 9.1 or later Japanese/English edition
Apple Computer Mac OS X 10.0 or later English edition
Apple Computer Mac OS X 10.1 or later Japanese edition SP (For the Mac OS X 10.0 Japanese edition, plug
and play does not work appropriately for USB audio devices.)
PC: One of These PC-AT Compatible Computers Running a Listed OS (OS Requirement Must Be Met)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Motherboard using Intel 440 BX or ZX chipset (using the USB controller in the chipset)
Motherboard using Intel i810 chipset (using the USB controller in the chipset)
Motherboard using Intel i815 chipset (using the USB controller in the chipset)
Motherboard using Intel i820 chipset (using the USB controller in the chipset)
Motherboard using Intel i845 chipset (using the ICH2 USB controller in the chipset)
Motherboard using Intel i845 chipset (using the ICH4 USB controller in the chipset)
Motherboard using Intel i850 chipset (using the USB controller in the chipset)
Motherboard using Intel i848 chipset (using the ICH5/R USB controller in the chipset)
Motherboard using Intel i865 chipset (using the ICH5/R USB controller in the chipset)
Motherboard using Intel i875 chipset (using the ICH5/R USB controller in the chipset)
Motherboard using Apollot KT133 chipset (using the USB controller in the chipset)
Motherboard using Apollo KT333 chipset (using the USB controller in the chipset)
Motherboard using Apollo Pro plus chipset (using the USB controller in the chipset)
Motherboard using MVP4 or MVP3 chipset (using the USB controller in the chipset)
Motherboard using Aladdin V chipset (using the USB controller in the chipset)
Motherboard using SiS530 or SiS559 chipset (using the USB controller in the chipset)
Motherboard using SiS735 chipset (using the USB controller in the chipset)
NOTE:
The PCM2704/5/6/7 has been acknowledged in a USB compliance test. However, the acknowledgement is for the PCM2704/5/6/7 device
only, and does not apply to the customer’s system using the PCM2704/5/6/7.
Intel is a trademark of Intel Corporation.
Mac OS is a trademark of Apple Computer, Inc.
Microsoft, Windows, Windows Me, and Windows XP are trademarks of Microsoft Corporation.
Other trademarks are the property of their respective owners.
30
MECHANICAL DATA
MPQF112 – NOVEMBER 2001
PJT (S-PQFP–N32)
PLASTIC QUAD FLATPACK
0,45
0,30
0,80
M
0,20
0,20
0,09
Gage Plane
32
0,15
0,05
0,25
1
0°– 7°
7,00
9,00
SQ
SQ
0,75
0,45
1,05
0,95
Seating Plane
0,10
1,20
1,00
4203540/A 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2004, Texas Instruments Incorporated
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