PCM3060PWR
更新时间：2024-10-30 05:40:56
品牌：TI
描述：具有 96/192kHz 采样速率的 24 位异步立体声音频编解码器 | PW | 28 | -25 to 85
概述
规格参数
数据手册
替代型号PCM3060PWR 概述
具有 96/192kHz 采样速率的 24 位异步立体声音频编解码器 | PW | 28 | -25 to 85 编解码器 其他电信集成电路
PCM3060PWR 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SSOP |
| 包装说明： | TSSOP-28 | 针数： | 28 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 1 week |
| 风险等级： | 0.6 | Is Samacsys： | N |
| JESD-30 代码： | R-PDSO-G28 | JESD-609代码： | e4 |
| 长度： | 9.7 mm | 湿度敏感等级： | 2 |
| 功能数量： | 1 | 端子数量： | 28 |
| 最高工作温度： | 85 °C | 最低工作温度： | -25 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | TSSOP |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| 峰值回流温度（摄氏度）： | 260 | 认证状态： | Not Qualified |
| 座面最大高度： | 1.2 mm | 标称供电电压： | 3.3 V |
| 表面贴装： | YES | 技术： | CMOS |
| 电信集成电路类型： | TELECOM CIRCUIT | 温度等级： | OTHER |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | GULL WING |
| 端子节距： | 0.65 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 4.4 mm |
| Base Number Matches： | 1 |
PCM3060PWR 数据手册
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PCM3060
SLAS533B–MARCH 2007–REVISED MARCH 2008
24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC
1
FEATURES
and DAC
•
•
•
24-Bit Delta-Sigma ADC and DAC
ADC, DAC Asynchronous Operation
Stereo ADC:
–
Digital De-Emphasis: 32, 44.1, 48 kHz for
DAC
–
–
Power Down: ADC/DAC Independently
Asynchronous/Synchronous Control for
ADC/DAC Operation
–
High Performance: (Typical, 48 kHz)
–
–
–
THD+N: –93 dB
SNR: 99 dB
•
•
•
External Reset and Power-Down Pin:
ADC/DAC Simultaneously
Audio Interface Mode:
ADC/DAC Independent Master/Slave
Audio Data Format:
–
Dynamic Range: 99 dB
–
–
–
–
–
Sampling Rate: 16–96 kHz
System Clock: 256, 384, 512, 768 fS
Full Scale Input: 3 Vp-p
–
–
–
ADC/DAC Independent
I2S, Left-Justified, Right-Justified
Antialiasing Filter Included
1/64 Decimation Filter:
•
•
Dual Power Supplies:
5-V for Analog and 3.3-V for Digital
Package: TSSOP-28
–
–
Pass-Band Ripple: ±0.05 dB
–
Stop-Band Attenuation: –65 dB
–
On-Chip High-Pass Filter: 0.91 Hz at
fS = 48 kHz
APPLICATIONS
•
Stereo DAC:
•
•
•
•
DVD-RW
Digital TV
Digital Set-Top Box
Audio-Visual Applications
–
High Performance: (Typical, Differential,
48 kHz)
–
–
–
THD+N: –94 dB
SNR: 105 dB
DESCRIPTION
Dynamic Range: 104 dB
–
–
Sampling Rate: 16–192 kHz
The PCM3060 is
a low-cost, high-performance,
single-chip, 24-bit stereo audio codec with
single-ended analog inputs and differential analog
outputs.
System Clock: 128, 192, 256, 384,
512, 768 fS
–
–
–
–
Differential Voltage Output: 8 Vp-p
Single-Ended Voltage Output: 4 Vp-p
Analog Low-Pass Filter Included
4×/8× Oversampling Digital Filter:
The stereo 24-bit ADC employs
a
64-times
delta-sigma modulator. It supports 16–96 kHz
sampling rates and a 16/24-bit digital audio output
word on the audio interface.
–
–
Pass-Band Ripple: ±0.04 dB
The stereo 24-bit DAC employs a 64- or 128-times
delta-sigma modulator. It supports 16–192 kHz
sampling rates and a 16/24-bit digital audio input
word on the audio interface.
Stop-Band Attenuation: –50 dB
–
Zero Flags
•
Flexible Mode Control
The PCM3060 supports fully independent operation
of the sampling rate and audio interface for the ADC
and DAC.
Each audio interface supports I2S, left-justified, and
right-justified formats with 16/24-bit words.
–
3-Wire SPI, 2-Wire I2C Compatible Serial
Control Interface
–
Hardware Control Mode
•
Multiple Functions via SPI or I2C Interface:
–
Digital Attenuation and Soft Mute for ADC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
PCM3060
www.ti.com
SLAS533B–MARCH 2007–REVISED MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The PCM3060 can be software-controlled through a 3-wire SPI-compatible or 2-wire I2C-compatible serial
interface, which provides access to all functions including digital attenuation, soft mute, de-emphasis etc.
The PCM3060 can be also used in hardware mode, which provides three basic functions.
The PCM3060 is fabricated using a highly advanced CMOS process and is available in a small 28-pin TSSOP
package.
The PCM3060 is suitable for various sound processing applications for DVD-RW, digital TV, STB, and other AV
equipment.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
VCC
VDD
–0.3 to 6.5
Supply voltage
V
–0.3 to 4
Ground voltage differences AGND1, AGND2, DGND, SGND
RST, MS, MC, MD, SCKI1, SCKI2, DIN
±0.1
–0.3 to 6.5
V
V
Digital input voltage
BCK1, BCK2, LRCK1, LRCK2, DOUT
ZEROL, ZEROR, MODE
–0.3 to (VDD + 0.3 V) < 4
–0.3 to (VDD + 0.3 V) < 4
–0.3 to (VCC + 0.3 V) < 6.5
±10
V
V
Analog input voltage
VINL, VINR, VCOM, VOUTL+, VOUTL–, VOUTR+, VOUTR–
V
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
mA
°C
°C
°C
°C
°C
TA
–40 to 125
Tstg
TJ
–55 to 150
Junction temperature
150
Lead temperature (soldering)
Package temperature (IR reflow, peak)
260, 5 s
260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
5
MAX UNIT
VCC Analog supply voltage
VDD Digital supply voltage
Digital input interface level
5.5
3.6
V
V
2.7
3.3
TTL compatible
Sampling frequency, LRCK1, LRCK2
System clock frequency, SCKI1, SCKI2
16
96/192
36.864
kHz
MHz
Vpp
kΩ
Digital input clock frequency
Analog input level
2.048
3
AC-coupled
DC-coupled
5
Analog output load resistance
10
kΩ
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature
50
20
85
pF
pF
–25
25
°C
2
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3060
PCM3060
www.ti.com
SLAS533B–MARCH 2007–REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data (unless otherwise
noted).
PCM3060PW
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
DIGITAL INPUT/OUTPUT
DATA FORMAT
Audio data interface format
I2S, LJ, RJ
16, 24
Audio data word length
Audio data format
Bits
MSB-first, 2s-complement
Sampling frequency, ADC
Sampling frequency, DAC
System clock frequency
16
16
48
48
96
192
fS
kHz
128, 192, 256, 384, 512, 768 fS
2.048
36.864
MHz
INPUT LOGIC
(1)
VIH
2
2
VDD
0.8
(1)
VIL
Input logic level
VDC
µA
(2) (3)
VIH
5.5
(2) (3)
VIL
0.8
(2)
IIH
VIN = VDD
VIN = 0 V
VIN = VDD
VIN = 0 V
±10
±10
100
±10
(2)
IIL
Input logic current
(1) (3)
IIH
65
(1) (3)
IIL
OUTPUT LOGIC
(4)
VOH
IOUT = –4 mA
IOUT = 4 mA
2.8
Output logic level
VDC
(4) (5)
VOL
REFERENCE OUTPUT
VCOM output voltage
0.5
0.5 VCC
12.5
V
VCOM output impedance
7
18
±1
kΩ
Allowable VCOM output
source/sink current
µA
ADC CHARACTERISTICS
Resolution
ANALOG INPUT
16
24
Bits
Full scale input voltage
Center voltage
VINL, VINR = 0 dB
0.6 VCC
0.5 VCC
10
Vp-p
V
Input impedance
kΩ
Antialiasing filter response
–3 dB
300
kHz
DC ACCURACY
Gain mismatch,
channel-to-channel
Full-scale input, VINL, VIN
R
R
±2
±8 % of FSR
Gain error
Full-scale input, VINL, VIN
±2
±8 % of FSR
±2 % of FSR
Bipolar zero error
HPF bypass, VINL, VIN
R
±0.5
(1) BCK1, BCK2, LRCK1, LRCK2 (in slave mode, Schmitt-trigger input with 50-kΩ typical internal pulldown resistor)
(2) SCKI1, SCKI2, DIN, MS/ADR/IFMD, MC/SCL/FMT, MD/SDA/IFMD (Schmitt-trigger input, 5-V tolerant).
(3) RST (Schmitt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant).
(4) BCK1, BCK2, LRCK1, LRCK2 (in master mode), DOUT, ZEROL, ZEROR
(5) MD/SDA/IFMD (in I2C mode, open drain LOW output)
Copyright © 2007–2008, Texas Instruments Incorporated
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3
Product Folder Link(s): PCM3060
PCM3060
www.ti.com
SLAS533B–MARCH 2007–REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data (unless otherwise
noted).
PCM3060PW
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
(6) (7)
DYNAMIC PERFORMANCE
VIN = –1 dB, fS = 48 kHz
–93
–93
99
–85
THD+N
Total harmonic distortion + noise
dB
dB
dB
dB
dB
VIN = –1 dB, fS = 96 kHz
fS = 48 kHz, A-weighted
fS = 96 kHz, A-weighted
fS = 48 kHz, A-weighted
fS = 96 kHz, A-weighted
fS = 48 kHz
95
95
92
92
Dynamic range
101
99
SNR
Signal-to-noise ratio
101
96
Channel separation
(between L-ch and R-ch)
fS = 96 kHz
98
fS1 = 48 kHz, fS2 = 44.1 kHz
fS1 = 96 kHz, fS2 = 44.1 kHz
96
Crosstalk from DAC
98
DIGITAL FILTER PERFORMANCE
0.454
fS
Pass band
Hz
Hz
0.583
fS
Stop band
Pass-band ripple
< 0.454 fS
> 0.583 fS
±0.05
dB
dB
s
Stop-band attenuation
Group delay time
–65
17.4/fS
0.019 fS
/1000
HPF frequency response
–3 dB
Hz
DAC CHARACTERISTICS
Resolution
16
24
Bits
ANALOG OUTPUT
Single-ended
Differential
Single-ended
Differential
AC-coupled
DC-coupled
f = 20 kHz
f = 44 kHz
–3 dB
0.8 VCC
1.6 VCC
0.5 VCC
0.48 VCC
Output voltage
Center voltage
Load impedance
Vp-p
V
5
kΩ
10
–0.02
–0.07
300
dB
LPF frequency response
kHz
DC ACCURACY
Gain mismatch,
channel-to-channel
±1
±4 % of FSR
±6 % of FSR
Gain error
±2
±1
±1
Single-ended
±2
Bipolar zero error
% of FSR
Differential (VOUTX+ – VOUTX–)
(6) fIN = 1 kHz, using System Two audio measurement system by Audio Precision, RMS mode with 20-kHz LPF and 400-Hz HPF.
(7) fS = 96 kHz: SCKI1 = SCKI2 = 256 fS, fS = 192 kHz: SCKI1 = 512 fS at fS = 48 kHz and SCKI2 = 128 fS at fS = 192 kHz.
4
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3060
PCM3060
www.ti.com
SLAS533B–MARCH 2007–REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data (unless otherwise
noted).
PCM3060PW
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
(8) (9) (10)
DYNAMIC PERFORMANCE (SINGLE-ENDED)
VOUT = 0 dB, fS = 48 kHz
–93
–94
–94
103
103
103
104
104
104
101
101
101
101
101
101
–85
THD+N
Total harmonic distortion + noise VOUT = 0 dB, fS = 96 kHz
VOUT = 0 dB, fS = 192 kHz
dB
dB
dB
dB
dB
fS = 48 kHz, EIAJ, A-weighted
99
100
97
Dynamic range
fS = 96 kHz, EIAJ, A-weighted
fS = 192 kHz, EIAJ, A-weighted
fS = 48 kHz, EIAJ, A-weighted
fS = 96 kHz, EIAJ, A-weighted
fS = 192 kHz, EIAJ, A-weighted
fS = 48 kHz
SNR
Signal-to-noise ratio
Channel separation
Crosstalk from ADC
fS = 96 kHz
fS = 192 kHz
fS1 = 48 kHz, fS2 = 44.1 kHz
fS1 = 48 kHz, fS2 = 88.2 kHz
97
fS1 = 48 kHz, fS2 = 176.4 kHz
(8) (9) (11)
DYNAMIC PERFORMANCE (DIFFERENTIAL)
VOUT = 0 dB, fS = 48 kHz
–94
–95
–95
104
104
104
105
105
105
103
103
103
103
103
103
THD+N
Total harmonic distortion + noise VOUT = 0 dB, fS = 96 kHz
VOUT = 0 dB, fS = 192 kHz
dB
dB
dB
dB
dB
fS = 48 kHz, EIAJ, A-weighted
Dynamic range
fS = 96 kHz, EIAJ, A-weighted
fS = 192 kHz, EIAJ, A-weighted
fS = 48 kHz, EIAJ, A-weighted
fS = 96 kHz, EIAJ, A-weighted
fS = 192 kHz, EIAJ, A-weighted
fS = 48 kHz
SNR
Signal-to-noise ratio
Channel separation
Crosstalk from ADC
fS = 96 kHz
fS = 192 kHz
fS1 = 48 kHz, fS2 = 44.1 kHz
fS1 = 48 kHz, fS2 = 88.2 kHz
fS1 = 48 kHz, fS2 = 176.4 kHz
SHARP ROLLOFF
DIGITAL FILTER PERFORMANCE
0.454
fS
Pass band
Hz
Hz
0.546
fS
Stop band
Pass-band ripple
< 0.454 fS
> 0.546 fS
±0.04
dB
dB
Stop-band attenuation
–50
(8) fS = 96 kHz: SCKI1 = SCKI2 = 256 fS, fS = 192 kHz: SCKI1 = 512 fS at fS = 48 kHz and SCKI2 = 128 fS at fS = 192 kHz.
(9) fOUT = 1 kHz, using System Two audio measurement system by Audio Precision, RMS mode with 20-kHz LPF and 400-Hz HPF.
(10) Assumed 5-kΩ AC-coupled second-order LPF and 115-dB or higher- performance buffer.
(11) Assumed 10-kΩ DC-coupled second-order LPF and 115- dB or higher-performance differential to single-ended converter.
Copyright © 2007–2008, Texas Instruments Incorporated
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5
Product Folder Link(s): PCM3060
PCM3060
www.ti.com
SLAS533B–MARCH 2007–REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data (unless otherwise
noted).
PCM3060PW
PARAMETER
TEST CONDITIONS
SLOW ROLLOFF
UNIT
MIN
TYP
MAX
DIGITAL FILTER PERFORMANCE
0.308
fS
Pass band
Hz
Stop band
Pass-band ripple
0.73 fS
–35
Hz
dB
dB
< 0.308 fS
> 0.73 fS
±0.5
Stop-band attenuation
DIGITAL FILTER PERFORMANCE
Group delay time
20/fS
±0.1
s
De-emphasis error
dB
POWER SUPPLY REQUIREMENTS
VCC
4.5
2.7
5
3.3
25
5.5
3.6
36
Voltage range
VDD
VDC
fS = 48 kHz/ADC, fS = 48 kHz/DAC
fS = 96 kHz/ADC, fS = 96 kHz/DAC
fS1 = 48 kHz/ADC, fS2 = 192 kHz/DAC
fS = 48 kHz/ADC, power down/DAC
Power down/ADC, fS = 48 kHz/DAC
mA
mA
mA
mA
mA
µA
25
25
ICC
12
13
(12) (13)
Full power down
780
9
Supply current
fS = 48 kHz/ADC, fS = 48 kHz/DAC
fS = 96 kHz/ADC, fS = 96 kHz/DAC
fS1 = 48 kHz/ADC, fS2 = 192 kHz/DAC
fS = 48 kHz/ADC, power down/DAC
Power down/ADC, fS = 48 kHz/DAC
Full power down (12)
12
mA
mA
mA
mA
mA
µA
16
13
IDD
5
5
150
160
180
170
77
fS = 48 kHz/ADC, fS = 48 kHz/DAC
fS = 96 kHz/ADC, fS = 96 kHz/DAC
fS1 = 48 kHz/ADC, fS2 = 192 kHz/DAC
fS = 48 kHz/ADC, power down/DAC
Power down/ADC, fS = 48 kHz/DAC
Full power down (12) (13)
220
Power dissipation
mW
82
4.4
TEMPERATURE RANGE
Operation temperature
–25
85
°C
θJA
Thermal resistance
105
°C/W
(12) Halt SCKI1, SCKI2, BCK1, BCK2, LRCK1, LRCK2
(13) AC-coupled configuration. If DC-coupled configuration is used, DC current flow to external load is added and it depends on external load
resistance.
6
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3060
PCM3060
www.ti.com
SLAS533B–MARCH 2007–REVISED MARCH 2008
PIN ASSIGNMENTS
PCM3060
PW (TSSOP) PACKAGE
(TOP VIEW)
1
MC/SCL/FMT
MD/SDA/DEMP
DOUT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MODE
2
MS/ADR/IFMD
VINR
3
4
LRCK1
BCK1
VINL
5
VCC
SCKI1
AGND1
6
7
VDD
AGND2
VCOM
DGND
8
SCKI2
9
VOUTL+
VOUTL–
BCK2
10
11
12
13
14
LRCK2
DIN
VOUTR+
VOUTR–
SGND
RST
ZEROR
ZEROL
P0043-03
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): PCM3060
PCM3060
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SLAS533B–MARCH 2007–REVISED MARCH 2008
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
PIN
23
22
5
AGND1
AGND2
BCK1
–
–
ADC analog ground
DAC analog ground
I/O(1) Audio data bit clock input/output for ADC
I/O(1) Audio data bit clock input/output for DAC
BCK2
10
8
DGND
–
I(2)
O
Digital ground
DIN
12
3
Audio data digital input for DAC
Audio data digital output for ADC
DOUT
LRCK1
LRCK2
MC/SCL/FMT
MD/SDA/DEMP
4
I/O(1) Audio data left/right clock input/output for ADC
I/O(1) Audio data left/right clock input/output for DAC
11
1
I (2)
Mode control, clock for SPI, clock for I2C, format for H/W mode(5)
2
I/O(3) Mode control, data for SPI, data for I2C, de-emphasis for H/W mode
This pin provides four operation modes according to its input connection. Connected directly to
VDD: SPI mode. Connected to VDD through 220-kΩ pullup resistor: H/W mode, single-ended
VOUTX. Connected to DGND through 220-kΩ pulldown resistor: H/W mode, differential VOUTX.
Connected directly to DGND : I2C mode.
(4)
MODE
28
I
MS/ADR/IFMD
RST
27
15
6
I (2)
Mode control, select for SPI with low active, address for I2C, I/F mode for H/W mode
Reset and power-down control input, active-low
System clock input for ADC
(5)
I
SCKI1
SCKI2
SGND
VCC
I(2)
I(2)
–
9
System clock input for DAC
16
24
21
7
Shield analog ground
–
ADC, DAC analog power supply, 5-V
VCOM
–
ADC, DAC voltage common decoupling
VDD
–
Digital power supply, 3.3-V
VIN
L
25
26
19
20
14
13
17
18
I
Analog input to ADC, L-channel
VINR
I
Analog input to ADC, R-channel
VOUTL–
VOUTL+
ZEROL
ZEROR
VOUTR–
VOUTR+
O
O
O
O
O
O
Analog output from DAC, L-channel – in differential mode, must be open in single-ended mode
Analog output from DAC, L-channel + in differential mode, L-channel in single-ended mode
Zero flag, L-channel
Zero flag, R-channel
Analog output from DAC, R-channel – in differential mode, must be open in single-ended mode
Analog output from DAC, R-channel + in differential mode, R-channel in single-ended mode
(1) Schmitt-trigger input/output with 50-kΩ typical internal pulldown resistor
(2) Schmitt-trigger input, 5-V tolerant
(3) Schmitt-trigger input, 5 V tolerant for SPI, H/W mode and Schmitt-trigger input/open drain LOW output, 5-V tolerant for I2C
(4) VDD/2 biased, quad-state input
(5) Schmitt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant
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BLOCK DIAGRAM
SE to Diff.
Converter
Delta-Sigma
Modulator
VINL
VDD
Decimation Filter
with HPF
DGND
SE to Diff.
Converter
Delta-Sigma
Modulator
VINR
DOUT
LRCK1
VCC
BCK1
Audio
AGND1
SGND
Common
and
Reference
Interface
and
Clock
SCK1
SCK2
BCK2
LRCK2
DIN
Voltage Common and Reference
AGND2
VCOM
Control
ZEROR
VOUTR–
Multi-Level
Delta-Sigma
Modulator
LPF and
Buffer
VOUTR+
RST
Interpolation Filter
with Digital Function
MODE
Mode
Control
MS/ADR/IFMD
MC/SCL/FMT
MD/SDA/DEMP
V
OUTL+
Multi-Level
Delta-Sigma
Modulator
LPF and
Buffer
VOUTL–
ZEROL
B0229-01
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TYPICAL PERFORMANCE CURVES OF ADC INTERNAL FILTER
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data,
unless otherwise noted.
DIGITAL FILTER
DECIMATION FILTER, STOP-BAND CHARACTERISTICS
DECIMATION FILTER, PASS-BAND CHARACTERISTICS
0.1
0
−20
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
−40
−60
−80
−100
−120
−140
−160
0
8
16
24
32
0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency [×f ]
Normalized Frequency [×f ]
S
S
G001
G002
Figure 1.
Figure 2.
ANALOG FILTER
HIGH-PASS FILTER CHARACTERISTICS
ANTIALIASING FILTER CHARACTERISTICS
0
−5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
−10
−15
−20
−25
−30
−35
−40
−45
−50
0.0
0.1
0.2
0.3
0.4
1
10
100
1k
10k
f − Frequency − kHz
Normalized Frequency [×f /1000]
S
G004
G003
Figure 3.
Figure 4.
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TYPICAL PERFORMANCE CURVES OF DAC INTERNAL FILTER
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data,
unless otherwise noted.
DIGITAL FILTER
INTERPOLATION FILTER, STOP BAND
INTERPOLATION FILTER, PASS BAND
(SHARP-ROLL OFF)
(SHARP-ROLL OFF)
0.1
0.0
0
−20
−40
−0.1
−0.2
−0.3
−0.4
−0.5
−60
−80
−100
−120
−140
−160
0
1
2
3
4
0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency [×f ]
Normalized Frequency [×f ]
S
S
G005
G006
Figure 5.
Figure 6.
ANALOG FILTER
DE-EMPHASIS FILTER CHARACTERISTICS
(fS = 44.1 kHz)
LOW-PASS FILTER CHARACTERISTICS
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0
−10
−20
−30
−40
−50
0
2
4
6
8
10 12 14 16 18 20
1
10
100
1k
10k
f − Frequency − kHz
f − Frequency − kHz
G007
G008
Figure 7.
Figure 8.
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SLAS533B–MARCH 2007–REVISED MARCH 2008
TYPICAL ADC PERFORMANCE CURVES
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data,
unless otherwise noted.
THD+N at –1 dB vs TEMPERATURE
DYNAMIC RANGE and SNR vs TEMPERATURE
−88
−90
−92
−94
−96
−98
−100
104
102
100
98
V
IN
= –0.5 dB
Dynamic Range
SNR
96
94
92
−25
−25
0
25
50
75
100
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
G009
G010
Figure 9.
Figure 10.
THD+N at –1 dB vs SUPPLY VOLTAGE
DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE
−88
−90
−92
−94
−96
−98
−100
104
102
100
98
V
IN
= –1 dB
Dynamic Range
SNR
96
94
92
4.50
4.50
4.75
V
5.00
5.25
5.50
4.75
V
5.00
5.25
5.50
− Supply Voltage − V
− Supply Voltage − V
CC
CC
G011
G012
Figure 11.
Figure 12.
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SLAS533B–MARCH 2007–REVISED MARCH 2008
TYPICAL DAC PERFORMANCE CURVES
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data,
unless otherwise noted.
THD+N vs TEMPERATURE
DYNAMIC RANGE and SNR vs TEMPERATURE
−90
−92
110
108
106
104
102
100
98
SNR
−94
−96
Dynamic Range
−98
−100
−102
−25
0
25
50
75
100
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
G013
G014
Figure 13.
Figure 14.
THD+N vs SUPPLY VOLTAGE
DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE
−90
−92
110
108
106
104
102
100
98
−94
SNR
−96
Dynamic Range
−98
−100
−102
4.50
4.75
V
5.00
5.25
5.50
4.50
4.75
V
5.00
5.25
5.50
− Supply Voltage − V
− Supply Voltage − V
CC
CC
G015
G016
Figure 15.
Figure 16.
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SLAS533B–MARCH 2007–REVISED MARCH 2008
TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data,
unless otherwise noted.
ADCs OUTPUT SPECTRUM
OUTPUT SPECTRUM (–1 dB, N=32768)
OUTPUT SPECTRUM (–60 dB, N=32768)
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
5
10
15
20
0
5
10
15
20
f − Frequency − kHz
f − Frequency − kHz
G017
G018
Figure 17.
Figure 18.
DAC OUTPUT SPECTRUM
OUTPUT SPECTRUM (0 dB, N=32768)
OUTPUT SPECTRUM (–60 dB, N=32768)
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
5
10
15
20
0
5
10
15
20
f − Frequency − kHz
f − Frequency − kHz
G019
G020
Figure 19.
Figure 20.
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SLAS533B–MARCH 2007–REVISED MARCH 2008
DEVICE DESCRIPTION
ASYNCHRONOUS OPERATION
The PCM3060 supports complete asynchronous operation between the ADC and DAC by receiving two
independent system clocks on SCKI1 and SCKI2.
Also, the PCM3060 supports synchronous operation between ADC and DAC by receiving one common system
clock on either SCKI1 or SCKI2 and controlling the system clock configuration through register 67 or 72 in serial
mode control.
SYSTEM CLOCK
The PCM3060 requires two system clocks for operating the ADC and DAC blocks independently, or it requires
one common clock for synchronous ADC and DAC operation.
The system clock for the ADC of the PCM3060 must be 256, 384, 512, or 768 fS, where fS is the audio sampling
rate for the ADC, 16 to 96 kHz.
The system clock for the DAC of the PCM3060 must be 128, 192, 256, 384, 512, or 768 fS, where fS is the audio
sampling rate for the DAC, 16 to 192 kHz.
Table 2 lists the typical system clock frequencies, fSCKI1 and fSCKI2 for common audio sampling rates, and
Figure 21 shows the timing requirements for the system clock inputs.
Table 2. System Clock Frequencies for Common Audio Sampling Clock Frequencies
SAMPLING
FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY, fSCKI1, fSCKI2 [MHz]
(1)
(1)
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
16
32
2.048
4.096
3.072
6.144
4.096
8.192
6.144
12.288
16.9344
18.432
33.8688
36.864
See (2)
See (2)
8.192
16.384
22.5792
24.576
See (2)
See (2)
See (2)
See (2)
12.288
24.576
33.8688
36.864
See (2)
See (2)
See (2)
See (2)
44.1
48
5.6488
6.144
8.4672
9.216
11.2896
12.288
22.5792
24.576
88.2
11.2896
12.288
22.5792
24.576
16.9344
18.432
33.8688
36.864
96
176.4 (1)
192 (1)
See
(2)
See (2)
(1) This combination of sampling clock frequency and system clock frequency is supported only for the DAC.
(2) This system clock frequency is not supported for the given sampling clock frequency.
tw(SCH)
H
2 V
System Clock
(SCK1, SCK2)
0.8 V
L
tw(SCL)
t(SCY)
T0005-14
SYMBOL
t(SCY)
PARAMETERS
MIN
25
MAX
UNIT
System clock cycle time
System clock high time
System clock low time
System clock duty cycle
ns
ns
ns
tw(SCH)
tw(SCL)
0.4 t(SCY)
0.4 t(SCY)
40%
60%
Figure 21. System Clock Input Timing
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SLAS533B–MARCH 2007–REVISED MARCH 2008
POWER-ON RESET AND EXTERNAL RESET SEQUENCE
The PCM3060 has both an internal power-on reset circuit and an external reset circuit. The sequences for both
resets are shown in the following.
Figure 22 illustrates the timing of the internal power-on reset. Initialization (reset) is done automatically at the
time when VDD exceeds 2.2 V typical.
Internal reset is released 1024 SCKIx (x = 1, 2) after power on if the H/W control mode is selected and RST is
kept HIGH; then the PCM3060 begins normal operation. If the S/W control mode is selected and RST is kept
HIGH, internal reset is released 1024 SCKIx after the reset of ADPSV and DAPSV through serial control port;
then the PCM3060 begins normal operation. If RST is kept LOW, internal reset is held and the reset sequence is
frozen until RST is changed from LOW to HIGH. VOUTL and VOUTR from the DAC are forced to the VCOM (= 0.5
VCC) level as VCC rises. If synchronization is maintained among SCKIx, BCKx, and LRCKx, VOUTL and VOUTR go
into the fade-in sequence after tDACDLY1 = 2048/fS from internal reset release. Then VOUTL and VOUTR provide
outputs corresponding to DIN after tDACDLY2 = 1616/fS from the start of fade-in. Similarly, DOUT from the ADC is
enabled and goes into the fade-in sequence after tADCDLY1 = 2048/fS from internal reset release, and then DOUT
provides an output corresponding to VINL and VINR after tADCDLY2 = 1936/fS from the start of fade-in. If
synchronization is not held, the internal reset is not released and operation mode is kept on reset and
power-down state. After resynchronization, the DAC begins its fade-in sequence, and the ADC also begins
fade-in operation after internal initialization and an initial delay.
Figure 23 is the timing chart of the external reset. The RST pin initiates external forced reset when RST is held
LOW for at least tRST = 2048/fS; it resets the device places it in the power-down state, which is the lowest-power
dissipation state in the PCM3060.
When RST transitions from HIGH to LOW while SCKIx, BCKx, and LRCKx are synchronized, VOUTL and VOUT
R
are forced to the VCOM (= 0.5 VCC) level after the fade-out sequence lasting tDACDLY2 = 1616/fS, and DOUT is
forced to ZERO after tADCDLY2 = 1936/fS fade-out sequence. After that, the internal reset becomes LOW, the
PCM3060 resets and enters into the power-down state, finally all registers and memory except mode control
registers are reset. To resume into normal operation, changing RST to HIGH again is required, and the sequence
shown in Figure 22 is performed. It is possible to halt SCKIx, BCKx and LRCKx during the power-down state, but
all clocks must be resumed prior to starting the power-up sequence. The same fade-in/-out sequence of VOUTL/R
and DOUT can be obtained by setting the ADPSV and DAPSV bits through serial mode control port.
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POWER-ON RESET AND EXTERNAL RESET SEQUENCE (Continued)
(VDD = 3.3 V typ.)
(VDD = 2.7 V min.)
VDD
(VDD = 2.2 V typ.)
0 V
SCKIx,
BCKx,
LRCKx
Synchronous Clocks
MODE
RST
ADPSV
DAPSV
(1)
1024 SCKIx
1024 SCKIx
Power Down
Internal
Reset
Normal Operation
t(DACDLY1)
2048/fS
t(DACDLY2)
1616/fS
VOUTL+/–
VOUTR+/–
0.5 VCC
VCOM (0.5 VCC
)
t(ADCDLY1)
2048/fS
t(ADCDLY2)
1936/fS
DOUT
ZERO
Fade-in
T0097-02
NOTE: Release from the power-save mode is required if the software control mode is selected.
Figure 22. DAC Output and ADC Output for Power-On Reset
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(VDD = 3.3 V typ.)
VDD
0 V
SCKIx,
BCKx,
LRCKx
Synchronous Clocks
Synchronous Clocks
MODE
RST
tRST
2048/fS min.
2048/fS min.
ADPSV
DAPSV
(1)
1024 SCKIx
Internal
Reset
Normal Operation
Normal Operation
Power Down
t(DACDLY1)
2048/fS
t(DACDLY2)
1616/fS
t(DACDLY2)
1616/fS
VOUTL+/–
VOUTR+/–
0.5 VCC
VCOM (0.5 VCC
)
t(ADCDLY2)
1936/fS
t(ADCDLY1)
2048/fS
t(ADCDLY2)
1936/fS
DOUT
Fade-out
ZERO
Fade-in
T0098-02
(1) ADPSV and DAPSV control VOUTL/R and DOUT, respectively, with fade-in/out the same as for RST.
Figure 23. DAC Output and ADC Output for External Reset
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SLAS533B–MARCH 2007–REVISED MARCH 2008
PCM AUDIO INTERFACE
Audio Interface Mode and Timing
The digital audio data can be interfaced in either slave or master mode, and this interface mode is selectable
using the serial mode control described in the Mode Control section.
The interface mode is also selectable independently for the ADC and the DAC. DIN is always input to the
PCM3060 and DOUT is always an output from the PCM3060. Slave mode is the default mode for both the ADC
and the DAC.
In slave mode, BCK1/2 and LRCK1/2 are inputs to the PCM3060, and BCK1/2 must be either 64 fS or 48 fS. DIN
is sampled on the rising edge of BCK2, and DOUT is changed on the falling edge of BCK1. The default timing
specification is shown in Figure 24.
In master mode, BCK1/2 and LRCK1/2 are outputs from the PCM3060. BCK1/2 and LRCK1/2 are generated by
the PCM3060 from SCKI1/2, and BCK1/2 is fixed at 64 fS. DIN is sampled on the rising edge of BCK2, and
DOUT is changed on the falling edge of BCK1. The detailed timing specification is shown in Figure 25.
t(BCH)
t(BCL)
BCK1/2
(Input)
1.4 V
t(BCY)
t(LRH)
t(LRS)
LRCK1/2
(Input)
1.4 V
t(DOD)
0.5 VDD
DOUT
t(DIS)
t(DIH)
DIN
1.4 V
T0247-01
SYMBOL
t(BCY)
DESCRIPTION
MIN
75
35
35
10
10
10
10
15
TYP
MAX
UNIT
ns
BCK1/2 cycle time
tw (BCH)
tw (BCL)
t(LRS)
BCK1/2 high time
BCK1/2 low time
ns
ns
LRCK1/2 set-up time to BCK1/2 rising edge
LRCK1/2 hold time to BCK1/2 rising edge
DIN setup time to BCK1/2 rising edge
DIN hold time to BCK1/2 rising edge
ns
t(LRH)
t(DIS)
ns
ns
t(DIH)
ns
t(DOD)
DOUT delay time from BCK1/2 falling edge
70
ns
NOTE: Load capacitance of output is 20 pF.
Figure 24. Audio Data Interface Timing (Slave Mode: BCK1/2 and LRCK1/2 Work as Inputs)
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SCKI1/2
(Input)
1.4 V
t(BCH)
t(BCD)
t(BCL)
t(BCD)
BCK1/2
(Output)
0.5 VDD
0.5 VDD
0.5 VDD
t(BCY)
t(LRD)
LRCK1/2
(Output)
t(DOD)
DOUT
t(DIS)
t(DIH)
DIN
1.4 V
T0248-01
SYMBOL
t(BCY)
PARAMETERS
MIN
TYP
MAX
UNIT
BCK1/2 cycle time
1/64 fS
tw(BCH)
tw(BCL)
t(LRD)
t(DIS)
BCK1/2 high time
BCK1/2 low time
0.4 t(BCY)
0.5 t(BCY) 0.6 t(BCY)
0.5 t(BCY) 0.6 t(BCY)
30
0.4 t(BCY)
LRCK1/2 delay time from BCK1/2 falling edge
DIN setup time to BCK1/2 rising edge
0
ns
ns
ns
ns
ns
10
10
0
t(DIH)
DIN hold time to BCK1/2 rising edge
t(DOD)
t(BCD)
DOUT delay time from BCK1/2 falling edge
BCK1/2 delay time from SCKI1/2 rising edge(1)
30
40
10
NOTE: Load capacitance of output is 20 pF.
(1) This specification applies for SCKI1/2 when the frequency is less than 25 MHz.
Figure 25. Audio Data Interface Timing (Master Mode: BCK1/2 and LRCK1/2 work as Outputs)
Audio Interface Format
The PCM3060 supports the following four interface formats in both slave and master modes, and they are
selectable independently for the ADC and DAC using serial mode control.
24-bit I2S format
24-bit left-justified format
24-bit right-justified format
16-bit right-justified format
All formats are provided in MSB-first, 2s complement data format.
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FMT1/2[1:0] = 00
24-Bit, MSB-First, I2S
LRCK1/2
Right-Channel
Left-Channel
Left-Channel
Left-Channel
Left-Channel
BCK1/2
DIN
1
2
3
3
22 23 24
LSB
1
2
3
3
22 23 24
LSB
MSB
MSB
DOUT
1
2
22 23 24
LSB
1
2
22 23 24
LSB
MSB
MSB
FMT1/2[1:0] = 01
24-Bit, MSB-First, Left-Justified
LRCK1/2
Right-Channel
BCK1/2
DIN
1
2
3
3
22 23 24
1
2
3
22 23 24
LSB
1
1
MSB
LSB
MSB
DOUT
1
2
22 23 24
LSB
1
2
3
22 23 24
LSB
MSB
MSB
FMT1/2[1:0] = 10
24-Bit, MSB-First, Right-Justified
LRCK1/2
Right-Channel
BCK1/2
DIN 24
DOUT 24
1
2
3
3
22 23 24
LSB
1
2
3
3
22 23 24
LSB
MSB
MSB
1
2
22 23 24
LSB
1
2
22 23 24
LSB
MSB
MSB
FMT1/2[1:0] = 11
16-Bit, MSB-First, Right-Justified
LRCK1/2
Right-Channel
BCK1/2
DIN 16
DOUT 16
1
2
3
3
14 15 16
LSB
1
2
3
3
14 15 16
LSB
MSB
MSB
1
2
14 15 16
LSB
1
2
14 15 16
LSB
MSB
MSB
T0016-18
Figure 26. Audio Data Input/Output Format
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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
As the PCM3060 operates under the system clock (SCKI1/2) and the audio sampling clock (LRCK1/2), SCKI1/2
and LRCK1/2 must have a specific relationship in slave mode. The PCM3060 does not need a specific phase
relationship between audio the interface clocks (LRCK1/2, BCK1/2) and system clock (SCKI1/2), but does
require a frequency synchronization of LRCK1/2, BCK1/2, and SCKI1/2.
If the relationship between SCKI2 and LRCK2 changes more than ±6 BCK2s (BCK2 = 64 fS) or ±5 BCK2s (BCK2
= 48 fS) due to jitter or frequency change, etc., internal operation of DAC halts within 2/fS, and analog output is
forced to VCOM (0.5VCC) until resynchronization of SCKI2 to LRCK2 and BCK2 is completed and then tDACDLY3
passes by.
If the relationship between SCKI1 and LRCK1 changes more than ±6 BCK1s (BCK1 = 64 fS) or ±5 BCK1s (BCK1
= 48 fS) due to jitter, frequency change, etc., internal operation of ADC halts within 2/fS, and digital output is
forced into ZERO code until resynchronization of SCKI1 to LRCK1 and BCK1 is completed and then tADCDLY3
passes by.
In case of changes less than ±5 BCK1/2s (BCK1/2 = 64) or ±4 BCK1/2s (BCK1/2 = 48), resynchronization does
not occur, and previously described analog/digital output control and discontinuity do not occur.
Figure 27 illustrates the DAC analog output and ADC digital output for loss of synchronization.
During undefined data, it may generate some noise in audio signal. Also, the transition of normal to undefined
data and undefined or zero data to normal creates a discontinuity in the data on the analog and digital outputs,
which may generate some noise in the audio signal.
The ADC output, DOUT and DAC outputs, and VOUTX hold the previous state if the system clock halts.
State of Synchronization
Synchronous
Asynchronous
Synchronous
t(DACDLY3)
(22/fS)
Within 2/fS
Normal
VCOM
(0.5 VCC
)
Undefined
Data
DAC VOUTX+/–
Normal
t(ADCDLY3)
(32/fS)
Undefined
Data
ADC DOUT
Normal
Zero
Normal
T0020-08
Figure 27. DAC Output and ADC Output for Loss of Synchronization
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ANALOG INPUTS TO ADC
The PCM3060 has two independent input channels, VINL and VINR. These are single-ended (unbalanced) inputs,
each capable of 0.6-VCC Vpp input with 10-kΩ input resistance, typically.
ANALOG OUTPUTS FROM DAC
The PCM3060 has two independent output channels, VOUTL and VOUTR. These are differential, (balanced)
outputs, each capable of driving 0.8-VCC Vpp (1.6-Vpp in differential) typical with a 10-kΩ dc-coupled load. The
internal output amplifiers for VOUTL+, VOUTL– and VOUTR+, VOUTR– are biased to VCOM, described as follows.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the PCM3060 delta-sigma modulators.
The frequency response of this filter is shown in the typical performance curves. This filter is not enough to
attenuate the out-of-band noise to an acceptable level for many applications in general. An external low-pass
filter is used if further out-of-band noise rejection in required.
VOUTX+, VOUTX– configuration can be changed to single-ended (unbalanced) output via a MODE pin setting or
serial mode control, and VOUTX+ is assigned as an output pin in single-ended mode.
VCOM OUTPUT
One unbuffered common voltage output pin, VCOM (pin 20) is brought out for decoupling purposes. This pin is
internally biased to a dc voltage level of 0.5 VCC nominal, and is used as an internal common voltage and
reference voltage for the ADC and DAC. This pin can be used to bias an external circuit, but the load impedance
must be high enough for operation with the output resistance of this pin, which is 12.5 kΩ, typically.
OVERSAMPLING RATE CONTROL
The oversampling rate of ADC of PCM3060 is fixed at 64 fS, but the oversampling rate of DAC of PCM3060 is
one of 64 fS, 32 fS or 16 fS, and this is automatically selected by the ratio of system clock frequency and sampling
frequency. And it can be also set to double rate, i.e., one of 128 fS, 64 fS or 32 fS, through serial control.
ZERO FLAGS
Zero-Detect Condition
For each DAC channel, the PCM3060 has a zero-detect circuit that recognizes zero detection when 1024
consecutive zeros have been sampled on DIN.
Zero-Flag Outputs
There are two zero-flag outputs, ZEROL and ZEROR. These pins can be used to operate external mute circuits,
or used as status indicators for a microcontroller, audio signal processor, etc. These pins can be programmed in
following two modes using the serial control port as described in the MODE CONTROL section.
DESCRIPTION
AZRO
ZEROL
ZEROR
0 (default)
1
L-ch zero detection
R-ch zero detection
L-ch and R-ch zero detection
L-ch and R-ch zero detection
For zero detection, these pins are set to HIGH (1) by default, but the polarity of the zero-flag outputs can be
inverted through the serial control port.
ZREV
0 (default)
1
DESCRIPTION
HIGH for zero detection
LOW for zero detection
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MODE CONTROL
The PCM3060 supports the following three types of mode control interface and four types of operation
configuration, according to the input state of MODE (pin 28) as follows. The pullup or pulldown resistor must be
220 kΩ ±5%.
MODE
Tie to DGND
MODE CONTROL INTERFACE
2-wire (I2C) serial control, selectable VOUTX configuration
Pulldown resistor to DGND
Pullup resistor to VDD
Tie to VDD
3-wire parallel control, differential VOUT
3-wire parallel control, single-ended VOUT
3-wire (SPI) serial control, selectable VOUTX configuration
X
X
The input state of the MODE pin is sampled during power-on reset or external reset; therefore, an input change
after reset is ignored until the next reset is performed.
The definitions (assignments) of the following three pins are changed by this control mode setting.
DEFINITION
PIN
SPI
MD
MC
MS
I2C
H/W
DEMP
FMT
2
1
SDA
SCL
ADR
27
IFMD
In serial mode control, the actual mode control is performed by register write (and read) through an SPI- or
I2C-compatible serial control port.
In parallel mode control, three specific functions are controlled directly through high/low settings of three specific
pins.
PARALLEL HARDWARE CONTROL
IFMD (Interface Mode)
DESCRIPTION
LOW
HIGH
Slave mode for ADC, slave mode for DAC
Master (256 fS) mode for ADC, slave mode for DAC
The audio interface of the ADC and DAC can be independent from each other, but mode selection is applied on
both.
FMT (Interface Format)
DESCRIPTION
LOW
HIGH
24-bit I2S for ADC and DAC
24-bit left-justified for ADC and DAC
The audio interface of the ADC and DAC can be independent from each other, but format selection is applied on
both.
DEMP (De-emphasis)
DESCRIPTION
LOW
HIGH
De-emphasis off
(1)
De-emphasis on
(1) The 44.1-kHz de-emphasis filter is always selected.
3-WIRE (SPI) SERIAL CONTROL
The PCM3060 supports SPI-compatible serial ports, which operate asynchronously to the audio serial interface.
The control interface consists of MD, MC, and MS. MD is the serial data input, used to program the mode control
registers. MC is the serial bit clock, used to shift the data into the control port. MS is the select input, used to
enable the mode control port.
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Register Write Operation
All single-write operations via the serial control port use 16-bit data words. Figure 28 shows the control data word
format. The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index
(address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the
register specified by IDX[6:0].
Figure 29 shows the functional timing diagram for single-write operations on the serial control port. MS is held in
the High state until a register is to be written. To start the register write cycle, MS is set to the Low state. Sixteen
clocks are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth
clock cycle has completed, MS is set to High to latch the data into the indexed mode control register.
The PCM3060 supports the multiple-write operation in addition to the single-write operation. Multiple write is
performed by sending N-sets of 8-bit register data after the first 16 bits of register address and register data,
while keeping the MC clock and MS in the Low state. Closing the multiple-write operation is done by setting MS
to the High state.
LSB
D0
MSB
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
Register Index (or Address)
D7
D6
D5
D4
D3
D2
D1
Register Data
R0001-01
Figure 28. Control Data Word Format for MD
MS
MC
MD
X
0
D7 D6 D5 D4 D3 D2
D1 D0
X
X
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6
T0048-01
Figure 29. Register Write Operation
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Timing Requirements
Figure 30 shows a detailed timing diagram for the 3-wire serial control interface. These timing parameters are
critical for proper control port operation.
t(MHH)
1.4 V
MS
MC
MD
t(MSS)
t(MCH)
t(MCL)
t(MSH)
1.4 V
t(MCY)
LSB
1.4 V
t(MDS)
t(MDH)
T0013-10
SYMBOL
t(MCY)
PARAMETER
MIN
MAX
UNIT
ns
MC cycle time
100
40
tw(MCL)
tw (MCH)
t(MHH)
t(MSS)
t(MSH)
t(MDH)
t(MDS)
MC low-level time
MC high-level time
MS high-level time
ns
40
ns
t(MCY)
15
ns
MS falling edge to MC rising edge
ns
MS rising edge from MC rising edge for LSB(1)
15
ns
MD hold time
15
ns
MD setup time
15
ns
(1) MC rise edge for LSB to MS rise edge.
Figure 30. Control Interface Timing for SPI
TWO-WIRE (I2C) SERIAL CONTROL
The PCM3060 supports the I2C-compatible serial bus and the data transmission protocol for standard-mode and
fast-mode (CB max = 100 pF) as a slave device. This protocol is explained in the well-known I2C 2.0
specification.
Slave Address
MSB
LSB
R/W
1
0
0
0
1
1
ADR
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The PCM3060 has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory
preset to 10 0011. The next bit of the address byte is the device select bit, which can be user-defined by the
ADR pin (pin 27). Two PCM3060s at maximum can be connected on the same bus at one time. Each PCM3060
responds when it receives its own slave address.
Packet Protocol
A master device must control packet protocol, which consists of a start condition, slave address with read/write
bit, data if write or acknowledgment if read, and stop condition. The PCM3060 supports the slave receiver
function.
SDA
Sp
SCL
St
1-7
8
9
1-8
9
1-8
9
9
Slave Address
ACK
DATA
ACK
DATA
ACK
ACK
R/W
Start
Condition
Stop
Condition
R/W: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgement of a Byte if 0, not Acknowledgement of a Byte if 1
DATA: 8 Bits (Byte)
T0049-06
Write Operation
The PCM3060 supports the receiver function. A master can write to any PCM3060 registers using single or
multiple accesses. The master sends a PCM3060 slave address with a write bit, a register address, and the
data. If multiple access is required, the address is that of the starting register, followed by the data to be
transferred. When the data are received properly, the index register is incremented by 1 automatically. When the
index register reaches 4Ah, the next value is 40h. When undefined registers are accessed, the PCM3060 does
not send an acknowledgment. Figure 31 is a diagram of the write operation. The register address and the write
data are 8-bit in MSB-first format.
Transmitter
Data Type
M
M
M
S
M
S
M
S
M
S
S
M
Reg Address
Sp
St Slave Address
ACK
ACK
Write Data 1 ACK
Write Data 2 ACK
ACK
W
M: Master Device S: Slave Device St: Start Condition W: Write ACK: Acknowledgement Sp: Stop Condition
R0002-04
Figure 31. Framework for Write Operation
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Timing Diagram
The detailed timing diagram for SCL and SDA is shown as follows.
Start
Repeated Start
Stop
t(D-HD)
t(SDA-F)
t(P-SU)
t(BUF)
t(D-SU)
t(SDA-R)
SDA
t(SCL-R)
t(S-HD)
t(GW)
t(LOW)
SCL
t(S-HD)
t(HI)
t(S-SU)
t(SCL-F)
T0050-04
Timing Characteristics
STANDARD MODE
FAST MODE
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
f(SCL)
SCL clock frequency
100
400
kHz
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
µs
ns
pF
V
t(BUF)
t(LOW)
t(HI)
Bus free time between STOP and START conditions
Low period of the SCL clock
High period of the SCL clock
Setup time for START/repeated START condition
Hold time for START/repeated START condition
Data setup time
4.7
4.7
4
1.3
1.3
0.6
t(S-SU)
t(S-HD)
t(D-SU)
t(D-HD)
t(SCL-R)
t(SCL-F)
t(SDA-R)
t(SDA-F)
t(P-SU)
t(GW)
4.7
4
0.6
0.6
250
0
100
Data hold time
3450
1000
1000
1000
1000
0
900
300
300
300
300
Rise time of SCL signal
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
0.6
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Allowable glitch width
4
N/A
400
50
CB
Capacitive load for SDA and SCL lines
100
Noise margin at high level for each connected device (including hysteresis)
Noise margin at low level for each connected device (including hysteresis)
Hysteresis of Schmitt-trigger input
0.2 VDD
0.1 VDD
N/A
0.2 VDD
0.1 VDD
0.05 VDD
V
V
Figure 32. Control Interface Timing for I2C
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MODE CONTROL REGISTERS
The PCM3060 has many user-programmable functions which are accessed via control registers, and they are
programmed through the SPI or I2C serial control port. Table 3 lists the available mode control functions along
with reset default conditions and associated register addresses. The register map is shown in Table 3.
Table 3. User-Programmable Mode Control Functions
FUNCTION RESET
Mode control register reset (ADC and DAC)
System reset (ADC and DAC)
DEFAULT
Normal operation
Normal operation
Power save
REGISTER
LABEL
MRST
SRST
ADPSV
DAPSV
S/E
64
64
64
64
64
ADC power-save control (ADC)
DAC power-save control (DAC)
Power save
VOUT configuration control (DAC)
Differential
Digital attenuation control, 0 dB to –100 dB in 0.5-dB steps
(DAC)
0 dB, no attenuation
65 and 66
AT21[7:0], AT22[7:0]
Clock select for DAC operation (DAC)
Master/slave mode for DAC audio interface (DAC)
Interface format for DAC audio interface (DAC)
Oversampling rate control (DAC)
Output phase select (DAC)
CLK2 enable
Slave
67
67
67
68
68
68
69
69
69
69
69
CSEL2
M/S 2[2:0]
FMT2[1:0]
OVER
I2S
Low (x64/x32/x16)
Normal
DREV2
Soft-mute control (DAC)
Mute disabled
Sharp rolloff
MUT22, MUT21
FLT
Digital filter rolloff control (DAC)
De-emphasis sampling rate selection (DAC)
De-emphasis function control (DAC)
Zero-flag polarity control (DAC)
44.1 kHz
DMF[1:0]
DMC
De-emphasis disabled
High for detection
L-ch, R-ch independent
ZREV
Zero-flag form select (DAC)
AZRO
Digital attenuation control, 20 dB to –100 dB in 0.5-dB steps
(ADC)
0 dB, no attenuation
70 and 71
AT11[7:0], AT12[7:0]
Clock select for ADC operation (ADC)
Master/slave mode for ADC audio interface (ADC)
Interface format for ADC audio interface (ADC)
Zero-cross detection disable for digital attenuation control (ADC)
HPF bypass control (ADC)
CLK1 enable
Slave
72
72
72
73
73
73
73
CSEL1
M/S1[2:0]
FMT1[1:0]
ZCDD
I2S
Zero-cross detection enabled
Bypass disabled
Normal
BYP
Input phase select (ADC)
DREV1
Soft-mute control (ADC)
Mute disabled
MUT12, MUT11
Table 4. Register Map
REGISTER ADDRESS
DATA
HEX
DEC
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
RSV(1)
AT212
AT222
RSV(1)
AT211
AT221
40h
Register 64
0
1
0
0
0
0
0
0
MRST
SRST
ADPSV DAPSV
RSV(1)
S/E
41h
42h
Register 65
Register 66
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
AT217
AT227
AT216
AT226
AT215
AT225
AT214
AT224
AT213
AT223
AT210
AT220
RSV(1)
RSV(1)
RSV(1)
43h
44h
45h
Register 67
Register 68
Register 69
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
CSEL2
M/S 22
OVER
DMF1
M/S 21
M/S 20
FMT21
FMT20
RSV(1)
FLT
RSV(1)
DMF0
RSV(1)
DMC
DREV2 MUT22 MUT21
RSV(1)
AT113
AT123
RSV(1)
AT112
AT122
ZREV
AZRO
46h
47h
Register 70
Register 71
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
AT117
AT127
AT116
AT126
AT115
AT125
AT114
AT124
AT111
AT121
AT110
AT120
RSV(1)
BYP
RSV(1)
48h
49h
Register 72
Register 73
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
CSEL1
RSV(1)
M/S 12
RSV(1)
M/S 11
RSV(1)
M/S 10
ZCDD
FMT11
FMT10
DREV1 MUT12 MUT11
(1) RSV means reserved for factory use or future extension, and these bits should be set to 0 during regular operation. Do not write any
values in addresses other than those listed.
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REGISTER DEFINITIONS
B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 64
0
1
0
0
0
0
MRST
SRST
ADPSV DAPSV
RSV
RSV
RSV
S/E
MRST: Mode Control Register Reset (ADC and DAC)
Default value: 1
MRST = 0
MRST = 1
Set default value
Normal operation (default)
The MRST bit controls reset of the mode control registers to their default values. Pop noise may be generated.
Returning the MRST bit to 1 is not required, as the MRST bit is automatically set to 1 after a mode control
register reset.
SRST: System Reset (ADC and DAC)
Default value: 1
SRST = 0
SRST = 1
Resynchronization
Normal operation (default)
The SRST bit controls system reset, the relation between system clock and sampling clock is re-synchronized,
and ADC operation and DAC operation is restarted. The mode control register is not reset and the PCM3060
does not go into power down state, but pop-noise may be generated. Returning the SRST bit to 1 is not required,
as the SRST bit is automatically set to 1 after triggering a system reset.
ADPSV: ADC Power-Save Control (ADC)
Default value: 1
ADPSV = 0
ADPSV = 1
Normal operation
Power-save mode (default)
The ADPSV bit controls the ADC power-save mode. In power-save mode, DOUT is forced to ZERO with a
fade-out sequence, the internal ADC data are reset, and the ADC goes into the power-down state. For
power-save mode release, a fade-in sequence is applied on DOUT during the resume process. The serial mode
control is enabled during this mode. A waiting time of more than 2048/fS is required for the proper status change
by this power save control on/off. As the default state after power on is the power-save mode and DOUT is
disabled (ZERO), release from the power-save mode is required for normal operation. The detailed sequence
and timing for ADPSV control is shown Figure 22 and Figure 23.
NOTE:
It is recommended that changing/stopping clocks or changing the audio interface
mode be performed in power-down mode in order to avoid unexpected pop/click noise
and performance degradation.
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DAPSV: DAC Power-Save Control (DAC)
Default value: 1
DAPSV = 0
DAPSV = 1
Normal operation
Power-save mode (default)
The DAPSV bit controls DAC power-save mode. In power-save mode, DAC outputs are forced to Vcom with a
fade-out sequence, the internal DAC data are reset and the DAC goes into the power-down state. For
power-save mode release, a fade-in sequence is applied on the DAC outputs in resume process. The serial
mode control is enabled during this mode. A waiting time of more than 2048/fS is required for the proper status
change by this power-save control on/off. As the default state after power on is the power-save mode and the
DAC outputs are disabled (VCOM), release from the power-save mode is required for normal operation. The
detailed sequence and timing for DAPSV control is shown Figure 22 and Figure 23.
NOTE:
It is recommended that changing/stopping clocks or changing the audio interface
mode be performed in power-down mode in order to avoid unexpected pop/click noise
and performance degradation.
S/E: DAC Output Configuration Control (DAC)
Default value: 0
S/E = 0
S/E = 1
Differential (default)
Single-ended
The S/E bit allows the user to select the configuration of the DAC output on the VOUTX pins according to
application circuit.
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B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 65
Register 66
0
1
0
0
0
0
0
1
AT217
B7
AT216
B6
AT215
B5
AT214
B4
AT213 AT212 AT211
AT210
B0
B15 B14 B13 B12 B11 B10
B9
B8
B3
B2
B1
0
1
0
0
0
0
1
0
AT227
AT226
AT225
AT224
AT223 AT222 AT221
AT220
AT2x[7:0]: Digital Attenuation Level Setting (DAC)
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default value: 1111 1111b
AT2x[7:0]
1111 1111b
1111 1110b
1111 1101b
:
DECIMAL VALUE
ATTENUATION LEVEL SETTING
255
254
253
:
0 dB, no attenuation (default)
–0.5 dB
–1 dB
:
1000 0001b
1000 0000b
0111 1111b
:
129
128
127
:
–63 dB
–63.5 dB
–64 dB
:
0011 1000b
0011 0111b
0011 0110b
:
56
55
54
:
–99.5 dB
–100 dB
Mute
:
0000 0000b
0
Mute
Each DAC channel (VOUTL and VOUTR) has a digital attenuator function. The attenuation level may be set from 0
dB to –100 dB in 0.5-dB steps, and also may be set to infinite attenuation (mute). The attenuation level change
from current value to target value is performed by incrementing or decrementing one 0.5-dB step for every 8/fS
time interval. While the attenuation level change sequence is in progress, new commands for attenuation level
change are not processed, but the new command overwrites the previous command in the command buffer. The
last command for attenuation level change is performed after the present attenuation level change sequence is
finished.
The attenuation level for each channel can be set individually using the following formula, and the foregoing table
shows attenuation levels for various settings:
Attenuation level (dB) = 0.5 × (AT2x[7:0]DEC – 255), where AT2x[7:0]DEC = 0 through 255 for AT2x[7:0]DEC = 0
through 54, the level is set to infinite attenuation (mute).
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B15 B14 B13 B12 B11 B10
B9
1
B8
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 67
0
1
0
0
0
0
CSEL2 M/S 22
M/S 21
M/S 20
RSV
RSV
FMT21 FMT20
CSEL2: Clock Select for DAC Operation
Default value: 0 (SCKI2, BCK2, LRCK2 enabled for DAC operation)
CSEL2 = 0
CSEL2 = 1
SCKI2, BCK2, LRCK2 enabled for DAC operation (default)
SCKI1, BCK1, LRCK1 enabled for DAC operation
The CSEL2 bit controls system clock and audio interface clocks for the DAC operation.
SCKI2, BCK2, LRCK2 are used for the DAC portion if CSEL2 = 0 (default), and SCKI1, BCK1, LRCK1 are used
for DAC operation if CSEL2 = 1.
M/S 2[2:0]: Audio Interface Mode for DAC
Default value: 000 (slave mode)
M/S 2[2:0]
0 0 0
Audio Interface Mode for DAC
Slave mode (default)
Master mode, 768 fS
Master mode, 512 fS
Master mode, 384 fS
Master mode, 256 fS
Master mode, 192 fS
Master mode, 128 fS
Reserved
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
The M/S 2[2:0] bits control the audio interface mode for the DAC.
FMT2[1:0]: Audio Interface Format for DAC
Default value: 00 (I2S Mode)
FMT2[1:0]
0 0
Audio Interface Format for DAC
24-bit I2S format (default)
24-bit left-justified format
0 1
1 0
24-bit right-justified format
16-bit right-justified format
1 1
The FMT2[1:0] bits control the audio interface format for the DAC.
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B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 68
0
1
0
0
0
1
RSV
OVER
RSV
RSV
RSV
DREV2
MUT22
MUT21
OVER: Oversampling Rate Control (DAC)
Default value: 0
OVER
System clock = 512 fS or 768 fS
×64 Oversampling (default)
×128 Oversampling
System clock = 256 fS or 384 fS
×32 Oversampling (default)
×64 Oversampling
System clock = 128 fS or 192 fS
×16 Oversampling (default)
×32 Oversampling
OVER = 0
OVER = 1
The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters.
Setting OVER = 1 might improve out-of-band noise characteristics in some application environments, but it might
also slightly affect baseband performance.
Writing over this bit during normal operation may generate pop noise.
DREV2: Output Phase Select (DAC)
Default value: 0
DREV2 = 0
DREV2 = 1
Normal output (default)
Inverted output
The DREV2 bit is used to control the phase of the analog signal outputs (VOUTL and VOUTR).
MUT2x: Soft Mute Control (DAC)
where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default value: 0
MUT2x = 0
MUT2x = 1
Mute disabled (default)
Mute enabled
The mute bits, MUT21 and MUT22, are used to enable or disable the soft mute function for the corresponding
DAC outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is
disabled (MUT2x = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUT2x = 1,
the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation at
the rate of one 0.5-dB step for every 8/fS time interval. By setting MUT2x = 0, the attenuator is increased to the
previously programmed attenuation level at the rate of one 0.5-dB step for every 8/fS time interval. This provides
pop-free muting of the DAC output.
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B15 B14 B13 B12 B11 B10
B9
0
B8
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 69
0
1
0
0
0
1
FLT
DMF1
DMF0
DMC
RSV
RSV
ZREV
AZRO
FLT: Digital Filter Rolloff Control (DAC)
Default value: 0
FLT = 0
FLT = 1
Sharp rolloff (Default)
Slow rolloff
The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Sharp and Slow
filter roll-off selections are available. The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function (DAC)
Default value: 00
DMF[1:0]
0 0
De-Emphasis Sampling Rate Selection
44.1 kHz (default)
48 kHz
0 1
1 0
32 kHz
1 1
Reserved
The DMF[1:0] bits are used to select the sampling frequency of the digital de-emphasis function when it is
enabled.
DMC: Digital De-Emphasis Function Control (DAC)
Default value: 0
DMC = 0
DMC = 1
De-emphasis disabled (default)
De-emphasis enabled
The DMC bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical
Performance Curves section of this data sheet for frequency characteristics.
ZREV: Zero-Flag Polarity Select (DAC)
Default value: 0
ZREV = 0
ZREV = 1
High for zero detect (default)
Low for zero detect
The ZREV bit is used to control the polarity of zero flag pins.
AZRO: Zero-Flag Function Select (DAC)
Default value: 0
AZRO = 0
AZRO = 1
ZEROL: L-ch ZERO detection (default)
ZEROL: L and R ZERO detection
ZEROR: R-ch ZERO detection (default)
ZEROR: L and R ZERO detection
The AZRO bit is used to select the function of zero flag pins.
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B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 70
Register 71
0
1
0
0
0
1
1
0
AT117
B7
AT116
B6
AT115
B5
AT114
B4
AT113 AT112 AT111
AT110
B0
B15 B14 B13 B12 B11 B10
B9
B8
B3
B2
B1
0
1
0
0
0
1
1
1
AT127
AT126
AT125
AT124
AT123 AT122 AT121
AT120
AT1x[7:0]: Digital Attenuation Level Setting (ADC)
where x = 1 or 2, corresponding to the ADC output L-ch part of DOUT (x = 1) or R-ch part of DOUT (x = 2).
Default value: 1101 0111b
AT1x[7:0]
1111 1111b
1111 1110b
1111 1101b
:
DECIMAL VALUE
ATTENUATION LEVEL SETTING
255
254
253
:
20 dB
19.5 dB
19 dB
:
1101 1000b
1101 0111b
1101 0110b
:
216
215
214
:
0.5 dB
0 dB, no attenuation (default)
–0.5 dB
:
0001 0000b
0000 1111b
0000 1110b
:
16
15
14
:
–99.5 dB
–100 dB
Mute
:
0000 0000b
0
Mute
Each ADC channel has a digital attenuator function with 20-dB gain. The attenuation level may be set from 20 dB
to –100 dB in 0.5-dB steps, and also may be set to infinite attenuation (mute). The attenuation level change from
the current value to the target value is performed by incrementing or decrementing one by 0.5-dB step at the
timing of zero-cross detection on the input signal which is sampled for every 1/fS time interval, or for every 8/fS
time interval if the zero-cross detection mode is disabled by ZCDD setting. If a zero-crossing is not detected for
512/fS, actual level change is done for every 1/fS time interval until a zero-crossing is detected again. While the
attenuation level change sequence is in progress, new commands for attenuation level change are not
processed, but the new command overwrites the previous command in the command buffer. The last command
for attenuation level change is performed after the present attenuation level change sequence is finished.
The attenuation level for each channel can be set individually using the following formula, and the above table
shows attenuation levels for various settings:
Attenuation level (dB) = 0.5 × (AT1x[7:0]DEC – 215), where AT1x[7:0]DEC = 0 through 255 for AT1x[7:0]DEC = 0
through 14, the level is set to infinite attenuation (mute).
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B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 72
0
1
0
0
1
0
CSEL1 M/S 12
M/S 11
M/S 10
RSV
RSV
FMT11 FMT10
CSEL1: Clock Select for ADC Operation
Default value: 0 (SCKI1, BCK1, LRCK1 enabled for ADC operation)
CSEL1 = 0
CSEL1 = 1
SCKI1, BCK1, LRCK1 enabled for ADC operation (default)
SCKI2, BCK2, LRCK2 enabled for ADC operation
The CSEL1 bit controls the system clock and audio interface clocks for the ADC operation.
SCKI1, BCK1, LRCK1 are used for ADC portion if CSEL1 = 0 (default), and SCKI2, BCK2, LRCK2 are used for
ADC portion if CSEL1 = 1.
M/S 1[2:0]: Audio Interface Mode for ADC
Default value: 000 (slave mode)
M/S 1[2:0]
0 0 0
Audio Interface Mode for ADC
Slave mode (default)
Master mode, 768 fS
Master mode, 512 fS
Master mode, 384 fS
Master mode, 256 fS
Reserved
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
Reserved
1 1 1
Reserved
The M/S 1[2:0] bits control the audio interface mode for the ADC.
FMT1[1:0]: Audio Interface Format for ADC
Default value: 00 (I2S mode)
FMT1[1:0]
0 0
Audio Interface Format for ADC
24-bit I2S format (default)
24-bit left-justified format
0 1
1 0
24-bit right-justified format
16-bit right-justified format
1 1
The FMT1[1:0] bits control the audio interface mode for ADC.
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B15 B14 B13 B12 B11 B10
B9
0
B8
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 73
0
1
0
0
1
0
RSV
RSV
RSV
ZCDD
BYP
DREV1 MUT12 MUT11
ZCDD: Zero-Cross Detection Disable for Digital Attenuation (ADC)
Default value: 0
ZCDD = 0
ZCDD = 1
Zero-cross detection enabled (default)
Zero-cross detection disabled
The ZCDD bit controls the zero-cross detect function for digital attenuation and mute. When zero-cross detection
is enabled, the actual level change for digital attenuation and mute is done at the timing of zero-cross detection
on the input signal which is sampled for every 1/fS time interval. If zero-crossing is not detected for 512/fS, the
actual level change is done for every 1/fS time interval until a zero-crossing is detected again as timeout control
for no zero-crossing input signal. When zero-cross detection is disabled, the actual level change is done at the
timing of 8/fS time interval.
BYP: HPF Bypass Control (ADC)
Default value: 0
BYP = 0
BYP = 1
Normal output, HPF enabled (default)
Bypassed output, HPF disabled
The BYP bit controls the HPF function; the dc component of the input signal and the internal dc offset are
converted in bypass mode.
DREV1: Input Phase Select (ADC)
Default value: 0
DREV1 = 0
DREV1 = 1
Normal input (default)
Inverted input
The DREV1 bit is used to control the phase of analog signal inputs (VINL and VINR).
MUT1x: Soft Mute Control (ADC)
where x = 1 or 2, corresponding to the ADC output L-ch part of DOUT (x = 1) and R-ch part of DOUT (x = 2).
Default value: 0
MUT1x = 0
MUT1x = 1
Mute disabled (default)
Mute enabled
The mute bits, MUT11 and MUT12, are used to enable or disable the soft mute function for the corresponding
ADC outputs, DOUT. The soft mute function is incorporated into the digital attenuators. When mute is disabled
(MUT1x = 0), the attenuator and ADC operate normally. When mute is enabled by setting MUT1x = 1, the digital
attenuator for the corresponding output is decreased from the current setting to infinite attenuation in 0.5 dB step
at the timing of zero-cross detection on the input signal which is sampled for every 1/fS time interval, or for every
8/fS time interval if zero-cross detection mode is disabled by ZCDD setting. If a zero-crossing is not detected for
512/fS, actual level change is done for every 1/fS time interval until zero-crossing is detected again. By setting
MUT1x = 0, the attenuator is increased to the previously programmed attenuation level in 0.5 dB step in the
same manner as for decreasing. This provides pop-free muting for the ADC input.
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TYPICAL CIRCUIT CONNECTION
Figure 33 illustrates typical circuit connection.
Control MCU
1
2
3
4
5
6
7
8
9
MC/FMT/SCL
MODE
28
27
Termination
MD/DEMP/SDA
MS/IFMD/ADR
C5
VIN
VIN
VCC
R
DOUT
LRCK1
BCK1
SCKI1
VDD
26
25
24
Analog Input
L
Audio
Receiver
/Encoder
C4
5 V
C1
AGND1 23
AGND2 22
0 V
C2
3.3 V
0 V
VCOM
VOUTL+
VOUTL–
VOUTR+
VOUTR–
DGND
SCKI2
21
20
19
18
17
C3
Analog Output
Post LPF
and
10 BCK2
11 LRCK2
12 DIN
Audio
Transmitter
/Decoder
Buffer
13 ZEROR
14 ZEROL
SGND 16
RST 15
Note: C1, C2: 0.1-mF ceramic capacitor and 10-mF electrolytic capacitor, depend on power supply.
C3: 0.1-mF ceramic capacitor and 10-mF electrolytic capacitor is recommended.
C4, C5: 4.7-mF electrolytic capacitor is recommended for 3-Hz cutoff frequency.
The termination for mode/configuration control.
Either one of following circuits has to be applied according to necessary mode/configuration.
Resistor value must be 220 kW, ±5 % tolerance.
28
28
3.3 V
3.3 V
28
28
0 V
0 V
(1)
(2)
(3)
(4)
S0257-01
Figure 33. Typical Application Diagram
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Application Examples for Analog Input and Output
a) Example of VCOM-biased buffering for 2-Vrms input with overvoltage protection.
R2
C2
Example of C, R values with
gain (G) and corner frequency (fC)
+V
C1
R1
R1: 20 kW
R2: 10 kW
R3: 1 kW
C1: 10 mF
C2: 330 pF
C3: 0.1 mF
G: 0.5
R3
Input
VIN
X
–V
VCOM
fC: 48 kHz
C3
b) Example of capless differential to single-ended converter with LPF and gain for 2-Vrms standard output.
R3
Example of C, R values with
gain (G) and corner frequency (fC)
C2
R1, R2: 10 kW
R3, R4: 7.5 kW
R5, R6: 820 W
R7: 100 W
+V
R1
C1
R2
R5
R6
R7
VOUTX+
VOUTX–
Output
–V
C1: 1500 pF
C2, C3: 470 pF
G: 0.75 (Differential to S/E)
fC: 54 kHz
R4
C3
c) Example of VCOM-biased single-supply single-ended application with LPF and MUTE control for 1-Vrms output.
R2
C2
Example of C, R values with
gain (G) and corner frequency (fC)
+V
R1
R3
R1: 10 kW
R2: 7.5 kW
R3: 750 W
C1: 3300 pF
C2: 470 pF
C3: 0.1 mF
C4: 10 mF
G: 0.75
C4
VOUTX+
VCOM
Output
Mute
C1
C3
fC: 54 kHz
ZEROx
Mute
OR
S0258-01
Figure 34. Application Examples for Analog Input and Output
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DESIGN AND LAYOUT CONSIDERATIONS IN APPLICATION
Power Supply Pins (VCC, VDD
)
The digital and analog power supply lines to the PCM3060 should be bypassed to the corresponding ground pins
with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic
performance of the ADC and DAC.
Although the PCM3060 has two power lines to maximize the potential of dynamic performance, using one
common source, 5-V power supply for VCC and a 3.3-V power supply for VDD which is generated from the 5-V
power supply for VCC, is recommended to avoid unexpected problems, such as latch-up, from incorrect power
supply sequencing.
Grounding (AGND1, AGND2, SGND, DGND)
To maximize the dynamic performance of the PCM3060, the analog and digital grounds are not connected
internally. These points should have very low impedance to avoid digital noise and signal components feeding
back into the analog ground. So, they should be connected directly to each other under the parts to reduce the
potential of noise problems.
VINL, VINR Pins
A 4.7-µF electrolytic capacitor is recommended as the ac coupling capacitor, which gives a 3-Hz cutoff
frequency. If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to
the VINX pins, although a small gain error is added due to variations of absolute input resistance of the
PCM3060. For example, adding 9.1 kΩ gives 2 Vrms full-scale with about 10% gain error.
VCOM Pin
Ceramic 0.1-µF and electrolytic 10-µF capacitors are recommended between VCOM and AGND to ensure low
source impedance of the ADC and DAC references. These capacitors should be located as close as possible to
the VCOM pins to reduce dynamic errors on ADC and DAC references.
VOUTL+, VOUTL–, VOUTR+, VOUTR– Pins
The differential to single-ended buffer with post LPF can be directly (without capacitor) connected to these output
pins, thereby minimizing the use of coupling capacitors for the 2-Vrms outputs. The output pins in single-ended
mode are assigned to VOUTL+ and VOUTR+ ; in single-ended mode, the VOUTL– and VOUTR– pins must be open.
MODE Pin
This pin is a logic input with quad-state input capability.
The pin is connected to VDD for High, to DGND for Low, and pulled up or pulled down through an external
resistor and for the two mid-states in order to distinguish the four input states. The pullup or pulldown resistor
must be 220 kΩ, ±5% tolerance.
System Clocks
The quality of SCKI1/2 may influence dynamic performance, as the PCM3060 (both ADC and DAC) operates
based on SCKI1/2. Therefore, it may be required to consider the jitter, duty, rise and fall time, etc. of the system
clocks.
The PCM3060 supports asynchronous operation between the ADC and DAC. Therefore, there is no restriction
on the relationship between SCKI1 and SCKI2 for digital operation, but it is strongly recommended to use a
common clock if the application does not require different base clock frequencies, like 44.1 kHz and 48 kHz.
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Audio Interface Clocks
In slave mode, PCM3060 does not require specific timing relationship between BCK1/LRCK1 and SCKI1,
BCK2/LRCK2 and SCKI2, but there is a possibility of performance degradation with a certain timing relationship
between them. In that case, specific timing-relationship control might solve this performance degradation.
In master mode, there is a possibility of performance degradation due to heavy loads on BCK1/LRCK1,
BCK2/LRCK2 and DOUT. It is recommended to load these pins as lightly as possible.
External Mute Control
For power-down ON/OFF control without the pop noise which is generated by a dc level change on the DAC
output, the external mute control is generally required. Use of the following control sequence is recommended:
external mute ON, codec power down ON, SCKI1/SCKI2 stop and resume if necessary, codec power down OFF,
and external mute OFF.
xxxxxx
xxxxxx
xxxxxx
xxxxxx
REVISION HISTORY
Changes from Original (March 2007) to Revision A ....................................................................................................... Page
•
Changed Figure 34(a), (b), and (c). Updated the Example of C, R values. ........................................................................ 40
Changes from Revision A (February 2008) to Revision B ............................................................................................. Page
•
•
Changed Supply Current - fS = 48 kHz/ADC, fS = 48 kHz/DAC max value From: 30 mA To: 36 mA ................................... 6
Changed Power dissipation - fS = 48 kHz/ADC, fS = 48 kHz/DAC max valueFrom: 190 mW To: 220 mW.......................... 6
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM3060PW
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
28
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-25 to 85
-25 to 85
PCM3060
PCM3060
Samples
Samples
PCM3060PWR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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14-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM3060PWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 28
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
PCM3060PWR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PCM3060PW
28
50
530
10.2
3600
3.5
Pack Materials-Page 3
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Copyright © 2022, Texas Instruments Incorporated
PCM3060PWR CAD模型
引脚图
封装焊盘图
PCM3060PWR 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| PCM3060PW | TI | 具有 96/192kHz 采样速率的 24 位异步立体声音频编解码器 | PW | 28 | 完全替代 |
|
| PCM3060PWG4 | TI | 24-bit Asynchronous Stereo Audio Codec with 96/192kHz sampling rate 28-TSSOP -25 to 85 | 类似代替 |
|
PCM3060PWR 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| PCM3070 | TI | Stereo Audio Codec With Embedded miniDSP | 获取价格 |
|
| PCM3070IRHBR | TI | Stereo Audio Codec With Embedded miniDSP | 获取价格 |
|
| PCM3070IRHBT | TI | Stereo Audio Codec With Embedded miniDSP | 获取价格 |
|
| PCM3070RHBT | TI | 暂无描述 | 获取价格 |
|
| PCM3070_14 | TI | Stereo Audio Codec | 获取价格 |
|
| PCM3120-Q1 | TI | 汽车类、立体声、106dB SNR、768kHz、低功耗、软件控制的音频 ADC | 获取价格 |
|
| PCM3120QRTERQ1 | TI | 汽车类、立体声、106dB SNR、768kHz、低功耗、软件控制的音频 ADC | RTE | 20 | -40 to 125 | 获取价格 |
|
| PCM3140-Q1 | TI | 具有 106dB SNR 的汽车类四通道、768kHz Burr-Brown? 音频模数转换器 (ADC) | 获取价格 |
|
| PCM3168A | TI | 24-Bit, 96-kHz/192-kHz, 6-In/8-Out Audio Codec with Differential Input/Output | 获取价格 |
|
| PCM3168A-Q1 | TI | 24-Bit, 96-kHz/192-kHz, 6-In/8-Out Audio Codec with Differential Input/Output | 获取价格 |
|
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