PCM3500EG4_技术文档

®

PCM3500

For most current data sheet and other product

information, visit www.burr-brown.com

Low Voltage, Low Power, 16-Bit, Mono

TM

VOICE/MODEM CODEC

FEATURES

● 16-BIT DELTA-SIGMA DAC AND ADC

● POWER SUPPLY: Single +2.7V to +3.6V

● SMALL PACKAGE: SSOP-24

● DESIGNED FOR MODEM ANALOG FRONT END:

Supports up to 56kbps Operation

● ANALOG PERFORMANCE:

APPLICATIONS

Sampling Frequency: 7.2kHz to 26kHz

Dynamic Range: 88dB (typ) at f_S= 8kHz, f = 1kHz

● SYSTEM CLOCK: 512f_S

● MASTER OR SLAVE OPERATION

● ON-CHIP CRYSTAL OSCILLATOR CIRCUIT

● ADC-TO-DAC LOOP-BACK MODE

● TIME SLOT MODE SUPPORTS UP TO

FOUR CODECs ON A SINGLE SERIAL

INTERFACE

IN

● SOFTWARE MODEMS FOR:

Personal Digital Assistant

Notebook and Hand-Held PCs

Set-Top Box

Digital Television

Embedded Systems

● PORTABLE VOICE RECORDER/PLAYER

● SPEECH RECOGNITION/SYNTHESIS

● TELECONFERENCING PRODUCTS

● POWER-DOWN MODE: 60µA (typ)

DESCRIPTION

digital-to-analog and analog-to-digital converters, in-

put anti-aliasing filter, digital high-pass filter for DC

blocking, and an output low-pass filter. The synchro-

nous serial interface provides for a simple, or glue-free

interface to popular DSP and RISC processors. The

serial interface also supports Time Division Multiplex-

ing (TDM), allowing up to four CODECs to share a

single 4-wire serial bus.

The PCM3500 is a low cost, 16-bit CODEC designed

for modem Analog Front End (AFE) and speech pro-

cessing applications. The PCM3500’s low power op-

eration from +2.7V to +3.6V power supplies, along

with an integrated power-down mode, make it ideal for

portable applications.

The PCM3500 integrates all of the functions needed for

a modem or voice CODEC, including delta-sigma

V_IN

∆Σ

Modulator

(ADC)

Decimation

Digital Filter

AAF

HPF

FS

AGND

BCK

DIN

Loop

V

_REF1

V_COM

V_REF

Reference

2

DOUT

V_OUT

∆Σ

Modulator

Interpolation

Digital Filter

Multi-Level

DAC

SMF

FSO

AGND

Clock

Gen/

OSC

SCKIO

Power

Mode Control

V_CC

AGND DGND

V_DDPDWN

LOOP

HPFD

M/S

TSC

XTO

XTI

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

•

Tel: (520) 746-1111

Twx: 910-952-1111 Internet: http://www.burr-brown.com/

•

Cable: BBRCORP Telex: 066-6491

•

FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

®

Printed in U.S.A. February, 2000

^PDS-1^1524B

PCM3500

SBAS117

SPECIFICATIONS

All specifications at +25°C, V_DD= V_CC= 3.3V, f_S= 8kHz, and nominal system clock (XTI) = 512f_S, unless otherwise noted. Measurement band is 100Hz to 0.425f_S.

PCM3500E

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

UNITS

16

Bits

DATA FORMAT

Serial Data Interface Format

DSP Format

16

Serial Data Bit Length

Serial Data Format

Bits

MSB-First, Binary Two’s Complement

Sampling Frequency, f_S

System Clock Frequency, 512f_S

ADC and DAC

7.2

8

26

kHz

3.686

4.096

13.312

MHz

DIGITAL INPUT/OUTPUT

Logic Family

CMOS

(1)

Input Logic Level: V_IH

0.7 • V_DD

VDC

µA

(1)

V_IL

0.3 • V_DD

±1

(2)

Input Logic Current: I_IN

(3)

I_IN

100

µA

(4)

Output Logic Level: V_OH

I_OUT= –1mA

I_OUT= +1mA

V_DD– 0.3

VDC

(4)

V_OL

0.3

ADC CHARACTERISTICS

DC ACCURACY

Input Voltage

Gain Error

0.6 V_CC

±2

Vp-p

% of FSR

kΩ

±5

Offset Error

High-Pass Filter Disabled

±2

Input Resistance

50

AC ACCURACY

THD+N

Dynamic Range

f_IN= 1kHz, V_IN= –0.5dB

Without A-Weighting

–85

88

–80

dB

82

80

Signal-to-Noise Ratio

Crosstalk

Without A-Weighting

DAC Channel Idle, 0dB Input

0.0002f_Sto 0.425f_S

88

85

dB

sec

Passband Ripple (internal HPF enabled)

Passband Ripple (internal HPF disabled)

Roll-Off at 0.00002f_S

Roll-Off at 0.56f_S

±0.05

–3

0f_Sto 0.425f_S

High-Pass Filter Enabled

0.58f_Sto f_S

–30

–65

18/f_S

Stopband Rejection

Group Delay

4m

DAC CHARACTERISTICS

DC ACCURACY

Output Voltage

Gain Error

0.6 V_CC

±1

Vp-p

% of FSR

kΩ

±5

Offset Error

High Pass Filter Disabled

±1

Load Resistance

10

AC ACCURACY

THD+N

Dynamic Range

Signal-to-Noise Ratio

Crosstalk

f_IN= 1kHz, V_OUT= 0dB

Without A-Weighted

ADC Channel Idle, 0dB Input

0f_Sto 0.425f_S

–90

92

–82

dB

sec

84

92

Passband Ripple

Group Delay

±0.4

12/f_S

4m

POWER SUPPLY REQUIREMENTS

Voltage Range

Supply Current, I_CC+ I_DD

V_CC, V_DD

V_CC= 3.3V

2.7

3.3

9

3.6

12

VDC

mA

Total Supply Current in Power-Down Mode

Total Power Dissipation

V_CC= V_DD= 3.3V, XTI Stopped

V_CC= V_DD= 3.3V

60

30

µA

mW

40

TEMPERATURE RANGE

Operating

Storage

–25

–55

+85

+125

°C

Thermal Resistance, Θ_JA

100

°C/W

NOTES: (1) Pins 6, 7, 8, 9, 10, 15, 17, 18, 19, 20 (M/S, TSC, BCK, FS, DIN, SCKIO, XTI, HPFD, LOOP, PDWN). (2) Pins 8, 9, 10, 15, 17 (BCK, FS, DIN, SCKIO

(Schmitt-Trigger input) XTI. (3) Pins 6, 7, 18, 19, 20 (M/S, TSC, HPFD, LOOP, PDWN; Schmitt-Trigger input with internal pull-down). (4) Pins 8, 9, 11, 12, 15,

16 (BCK, FS, DOUT, FSO, SCKIO, XTO).

®

PCM3500

2

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Supply Voltage, +V_DD, +V_CC............................................................. +6.5V

Supply Voltage Differences............................................................... ±0.1V

GND Voltage Differences.................................................................. ±0.1V

Digital Input Voltage ................................................... –0.3V to V_DD+ 0.3V

Input Current (any pins except supply) ........................................... ±10mA

Power Dissipation .......................................................................... 300mW

Operating Temperature Range ......................................... –25°C to +85°C

Storage Temperature ...................................................... –55°C to +125°C

Junction Temperature ...................................................................... 150°C

Lead Temperature (soldering, 5s).................................................. +260°C

(reflow, 10s) ................................................................................ +235°C

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE

DRAWING

NUMBER

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER⁽¹⁾

TRANSPORT

MEDIA

PRODUCT

PACKAGE

PCM3500E

"

24-Lead SSOP

"

338

"

–25°C to +85°C

PCM3500E

"

PCM3500E

PCM3500E/2K

Rails

Tape and Reel

"

NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2,000 pieces

of “PCM3500E/2K” will get a single 2000-piece Tape and Reel.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no

responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.

No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN

product for use in life support devices and/or systems.

®

3

PCM3500

PIN CONFIGURATION

Top View

SSOP

PCM3500

1

2

3

4

5

6

7

8

9

V_COM

V_REF

V_CC24

AGND 23

V_OUT22

AGND 21

PDWN 20

LOOP 19

HPFD 18

XTI 17

1

V_REF2

V_IN

AGND

M/S

TSC

BCK

FS

XTO 16

10 DIN

SCKIO 15

DGND 14

V_DD13

11 DOUT

12 FSO

PIN ASSIGNMENTS

NAME

I/O

DESCRIPTION

1

2

3

4

5

6

V_COM

OUT

—

Common-Mode Voltage (0.5V_CC). This pin should be connected to ground through a capacitor.

Decouple Pin for Reference Voltage 1 (0.99V_CC). This pin should be connected to ground through a capacitor.

Decouple Pin for Reference Voltage 2 (0.2V_CC). This pin should be connected to ground through a capacitor.

Analog Input for the ADC.

V_REF

1

V_REF2

—

V_IN

IN

AGND

M/S

—

Analog Ground for the ADC Input Signal.

IN

Master/Slave Select. This pin is used to determine the operating mode for the serial interface. A logic ‘0’ on this pin selects the Slave

Mode. A logic ‘1’ on this pin selects the Master Mode.⁽²⁾

7

8

9

TSC

BCK

FS

IN

I/O

Time Slot Mode Control. This pin is used to select the time slot operating mode. A logic ‘0’ on this pin disables Time Slot Mode. A

logic ‘1’ on this pin enables Time Slot Mode.⁽²⁾

Bit Clock. This pin serves as the bit (or shift) clock for the serial interface. This pin is an input in Slave Mode and an output in Master

Mode.⁽¹⁾

Frame Sync. This pin serves as the frame synchronization clock for the serial interface. This pin is an input in Slave Mode and an

output in Master Mode.⁽¹⁾

10

11

12

DIN

DOUT

FSO

IN

Serial Data Input. This pin is used to write 16-bit data to the DAC.⁽¹⁾

Serial Data Output. The ADC outputs 16-bit data on this pin.⁽³⁾

OUT

Frame Sync Output. Active only when Time Slot Mode is enabled. This pin is set to a high impedance state when Time Slot mode

is disabled (TSC = 0).

13

V_DD

—

Digital Power Supply. Used to power the digital section of the ADC and DAC, as well as the serial interface and mode control logic.

This pin is not internally connected to V_CC

.

14

15

DGND

SCKIO

—

Digital Ground. Internally connected through the substrate to analog ground.

I/O

System Clock Input/Output. This pin is a system clock output when using the crystal oscillator or XTI as the system clock input; when

XTI is connected to ground, this pin is a system clock input.⁽¹⁾

16

17

18

19

20

XTO

XTI

OUT

IN

Crystal Oscillator Output.

Crystal Oscillator Input or an External System Clock Input.

HPFD

LOOP

PDWN

IN

High-Pass Filter Disable. When this pin is set to a logic ‘1’, the HPF function in the ADC is disabled.⁽²⁾

ADC-to-DAC Loop-Back Control. When this pin is set to logic ‘1’, the ADC data is fed to the DAC input.⁽²⁾

IN

Power Down and Reset Control. When this pin is logic ‘0’, Power-Down Mode is enabled. The PCM3500 is reset on the rising edge

of this signal.⁽²⁾

21

22

23

24

AGND

V_OUT

—

OUT

—

Analog Ground for the DAC Output Signal.

Analog Output from the DAC Output Filter.

AGND

V_CC

Analog Ground. This is the ground for the internal analog circuitry.

Analog Power Supply. Used to power the analog circuitry of the ADC and DAC.

—

NOTES: (1) Schmitt-Trigger input. (2) Schmitt-Trigger input with an internal pull-down resistor. (3) Tri-state output in Time Slot Mode.

®

PCM3500

4

TYPICAL PERFORMANCE CURVES

DAC SECTION

DIGITAL FILTER

INTERPOLATION FILTER

PASSBAND RIPPLE CHARACTERISTICS

INTERPOLATION FILTER FREQUENCY RESPONSE

0

0.2

0.0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–0.2

–0.4

–0.6

–0.8

–1.0

0

1

2

3

4

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (• f_S)

Normalized Frequency (• f_SHz)

ANALOG FILTER

OUTPUT FILTER FREQUENCY RESPONSE

STOPBAND CHARACTERISTICS

OUTPUT FILTER FREQUENCY RESPONSE

PASSBAND CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

Frequency (Hz)

®

5

PCM3500

TYPICAL PERFORMANCE CURVES (Cont.)

T_A= +25°C, V_CC= V_DD= +3.3V, f_S= 8kHz, and f_SIGNAL= 1kHz, unless otherwise specified.

DAC SECTION

DAC OUTPUT SPECTRA

DAC OUTPUT SPECTRUM (–0dB, N = 8192)

DAC OUTPUT SPECTRUM (–60dB, N = 8192)

0

–20

0

–20

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

1

2

3

4

0

1

2

3

4

Frequency (kHz)

TOTAL HARMONIC DISTORTION + NOISE

vs SIGNAL NOISE

DAC OUT-OF-BAND NOISE SPECTRUM

(BPZ, N = 2048)

0

–20

0

–20

–40

–60

–80

–60

–100

–120

–140

THD+N fluctuates with signal level

as harmonics are limited to second

and third components.

–80

–100

–96

–84

–72

–60

–48

–36

–24

–12

0

8

16

24

32

40

48

56

64

Signal Level (dB)

Frequency (kHz)

®

PCM3500

6

TYPICAL PERFORMANCE CURVES (Cont.)

DAC SECTION

DAC CHARACTERISTICS vs TEMPERATURE, SUPPLY, AND SAMPLING FREQUENCY

TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs TEMPERATURE

(T_A= –25°C to +85°C)

–88

–90

–92

–94

–96

96

94

92

90

88

SNR

Dynamic Range

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

TOTAL HARMONIC DISTORTION + NOISE

vs SUPPLY VOLTAGE

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs SUPPLY VOLTAGE

(V_CC= V_DD= +2.7V to +3.6V)

–88

–90

–92

–94

–96

96

94

92

90

88

Dynamic Range

SNR

2.4

2.7

3.0

3.3

3.6

3.9

2.4

2.7

3.0

3.3

3.6

3.9

Supply Voltage (V)

TOTAL HARMONIC DISTORTION + NOISE

vs SAMPLING FREQUENCY

(f_S= 8kHz to 26kHz)

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs SAMPLING FREQUENCY

(f_S= 8kHz to 26kHz)

–88

–90

–92

–94

–96

96

94

92

90

88

BW = 3.4kHz

SNR

Dynamic Range

0

8

16

24

32

0

8

16

24

32

f

_S(kHz)

f

_S(kHz)

®

7

PCM3500

TYPICAL PERFORMANCE CURVES

ADC SECTION

DIGITAL FILTER

DECIMATION FILTER

STOPBAND ATTENUATION CHARACTERISTICS

DECIMATION FILTER FREQUENCY RESPONSE

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

0

0.2

0.4

0.6

0.8

1.0

0

8

16

24

32

Normalized Frequency (• f_SHz)

DECIMATION FILTER TRANSITION

BAND CHARACTERISTICS

DECIMATION FILTER

PASSBAND RIPPLE CHARACTERISTICS

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

0.2

0.0

–4.13dB at 0.5 • f_S

–0.2

–0.4

–0.6

–0.8

–1.0

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

Normalized Frequency (• f_SHz)

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (• f_SHz)

HIGH-PASS FILTER FREQUENCY RESPONSE

STOPBAND CHARACTERISTICS

HIGH-PASS FILTER FREQUENCY RESPONSE

PASSBAND CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–10

0

0.1

0.2

0.3

0.4

0.5

0

1

2

3

4

Normalized Frequency (• f_S/1000 Hz)

®

PCM3500

8

TYPICAL PERFORMANCE CURVES (Cont.)

T_A= +25°C, V_CC= V_DD= +3.3V, f_S= 8kHz, and f_SIGNAL= 1kHz, unless otherwise specified.

ADC SECTION

ANALOG FILTER

ANTI-ALIASING FILTER

STOPBAND CHARACTERISTICS

PASSBAND CHARACTERISTICS

0

–5

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

–10

–15

–20

–25

–30

–35

–40

–45

–50

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

Frequency (Hz)

ADC OUTPUT SPECTRA

ADC OUTPUT SPECTRUM (–60dB, N = 8192)

ADC OUTPUT SPECTRUM (–0.5dB, N = 8192)

0

–20

0

–20

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

1

2

3

4

0

1

2

3

4

Frequency (kHz)

TOTAL HARMONIC DISTORTION + NOISE

vs SIGNAL NOISE

0

–20

–40

–60

–80

THD+N fluctuates with signal level

as harmonics are limited to second

and third components.

–100

–96

–84

–72

–60

–48

–36

–24

–12

0

Signal Level (dB)

®

9

PCM3500

TYPICAL PERFORMANCE CURVES (Cont.)

T_A= +25°C, V_CC= V_DD= +3.3V, f_S= 8kHz, and f_SIGNAL= 1kHz, unless otherwise specified.

ADC SECTION

ADC CHARACTERISTICS vs TEMPERATURE, SUPPLY AND SAMPLING FREQUENCY

TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs TEMPERATURE

(T_A= –25°C to +85°C)

–84

–86

–88

–90

–92

92

90

88

86

84

SNR

Dynamic Range

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

TOTAL HARMONIC DISTORTION + NOISE

vs SUPPLY VOLTAGE

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs SUPPLY VOLTAGE

(V_CC= V_DD= +2.7V to +3.6V)

–84

–86

–88

–90

–92

92

90

88

86

84

Dynamic Range

SNR

2.4

2.7

3.0

3.3

3.6

3.9

2.4

2.7

3.0

3.3

3.6

3.9

Supply Voltage (V)

TOTAL HARMONIC DISTORTION + NOISE

vs SAMPLING FREQUENCY

(f_S= 8kHz to 26kHz)

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs SAMPLING FREQUENCY

(f_S= 8kHz to 26kHz)

–84

–86

–88

–90

–92

96

94

92

90

88

BW = 3.4kHz

SNR

Dynamic Range

0

8

16

24

32

0

8

16

24

32

f_S(kHz)

f

_S(kHz)

®

PCM3500

10

TYPICAL PERFORMANCE CURVES (Cont.)

T_A= +25°C, V_CC= V_DD= +3.3V, f_S= 8kHz, and f_SIGNAL= 1kHz, unless otherwise specified.

SUPPLY CURRENT vs SUPPLY VOLTAGE AND SAMPLING FREQUENCY

SUPPLY CURRENT vs SUPPLY VOLTAGE

12

10

8

12

10

8

I_CC+ I_DD

I_CC

6

4

I_DD

2

I_CC+ I_DDat Power Down

0

2.4

2.7

3.0

3.3

3.6

3.9

2.4

2.7

3.0

3.3

3.6

3.9

Supply Voltage (V)

®

11

PCM3500

SAMPLING FREQUENCY (kHz)

SYSTEM CLOCK FREQUENCY (MHz)

SYSTEM CLOCK AND RESET/

POWER DOWN

8

11.025

16

22.05

24

4.096

5.6448

8.192

11.2896

12.288

SYSTEM CLOCK INPUT AND OUTPUT

The PCM3500 requires a system clock for operating the

digital filters and delta-sigma data converters.

TABLE I. System Clock Frequencies for Common Sam-

pling Frequencies.

The system clock may be supplied from an external master

clock or generated using the on-chip crystal oscillator cir-

cuit. Figure 1 shows the required connections for external

and crystal clock operation. The system clock must operate

at 512 times the sampling frequency, f_S, with sampling

frequencies from 7.2kHz to 26kHz. This gives an effective

system clock frequency range of 3.6864MHz to 13.312MHz.

For either case, XTO (pin 16) should be left open. The system

clock source should be free of noise and exhibit low phase

jitter in order to obtain optimal dynamic performance from

the PCM3500. Figure 2 shows the system clock timing

requirements associated with an external master clock.

Table I shows system clock frequencies for common sam-

pling frequencies.

For crystal oscillator operation, a crystal is connected be-

tween XTI (pin 17) and XTO (pin 16), along with the

necessary load capacitors (10pF to 33pF per pin, as shown

in Figure 1). A fundamental-mode, parallel resonant crystal

is required.

For external clock operation, XTI (pin 17) or SCKIO (pin 15)

is driven by a master clock source. If SCKIO is used as the

system clock input, then XTI must be connected to ground.

SCKIO

External

Clock

C₁

Crystal

XTI

External

Clock

R

C₂

XTO

C₁, C₂= 10pF to 33pF

PCM3500

EXTERNAL CLOCK INPUT-XTI

(XTO must be open)

EXTERNAL CLOCK INPUT-SCKIO

(XTO must be open)

CRYSTAL RESONATOR

CONNECTION

FIGURE 1. System Clock Generation.

t_CLKIH

"H"

"L"

XTI

or

SCKIO

0.7V_DD

0.3V_DD

1/512f_S

t_CLKIL

System Clock Pulse Width HIGH t_CLKIH

System Clock Pulse Width LOW t_CLKIL

20ns (min)

FIGURE 2. External System Clock Timing Requirements.

®

PCM3500

12

PDWN causes the reset initialization sequence to start.

During the initialization sequence, the DAC output is forced

to AGND, and the ADC output is forced to a high impedance

state. After the initialization sequence has completed, the

DAC and ADC outputs experience a delay before they

output a valid signal or data. Refer to Figures 4 and 5 for

external reset and post-reset delay timing.

Reset and Power Down

The PCM3500 supports power-on reset, external reset, and

power-down operations. Power-on reset is performed by

internal circuitry automatically at power up, while the exter-

nal reset is initiated using the PDWN input (pin 20).

Power-on reset occurs when power and system clock are

initially applied to the PCM3500. The internal reset cir-

cuitry requires that the system clock be active at power up,

with at least three system clock cycles occurring prior to

V_DD= 2.2V. When V_DDexceeds 2.2V, the power-on reset

comparator enables the initialization sequence, which re-

quires 1024 system clock periods for completion. During

the initialization sequence, the DAC output is forced to

AGND, and the ADC output is forced to a high impedance

state. After the initialization sequence has completed, the

DAC and ADC outputs experience a delay before they

output a valid signal or data. Refer to Figures 3 and 5 for

power-on reset and post-reset delay timing.

Power-down mode is enabled by setting PDWN = ‘0’.

During power-down mode, minimum current is drawn when

the system clock is removed, resulting in 60µA (typical)

power supply current. The PDWN input includes an internal

pull-down resistor, which places the PCM3500 in power-

down mode at power-up if the PDWN pin is left uncon-

nected. Ideally, the PDWN input should be driven by active

logic in order to control reset and power-down operation. If

the PDWN pin is to be unused in the system application, it

should be connected to V_DDto enable normal operation. By

setting PDWN = ‘1’ when exiting power-down mode, the

PCM3500 will initiate an external reset as described earlier

in this section.

External reset is performed by first setting PDWN = ‘0’ and

then setting PDWN = ‘1’. The LOW to HIGH transition on

2.4V

2.2V

2.0V

V_DD

Reset

Reset Removal

Internal Reset

1024 System Clock Periods

System Clock

FIGURE 3. Power-On Reset Timing.

PWDN = LOW Pulse Width

_RST= 40ns minimum

t

PDWN

t_RST

Reset

Reset Removal

Internal Reset

1024 System Clock Periods

System Clock

FIGURE 4. External Reset Timing.

Reset Removal or Power Down OFF

Internal Reset

or Power Down

Ready/Operation

Reset

Power Down

t_DACDLY1(2048/f_S)

V_COM

DAC V_OUT

GND

(0.5V_CC

t_ADCDLY1(2304/f_S)

High Impedance

)

(1)

ADC DOUT

NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially.

FIGURE 5. DAC and ADC Output for Reset and Power Down.

®

13

PCM3500

SERIAL INTERFACE

anteed in Master Mode). Data for DIN is clocked into the

serial interface on the rising edge of BCK, while data for

DOUT is clocked out of the serial interface on the falling

edge of BCK.

The serial interface of the PCM3500 is a 4-wire synchronous

serial port. It includes FS (pin 9), BCK (pin 8), DIN (pin 10)

and DOUT (pin 11). FS is the frame synchronization clock,

BCK is the serial bit or shift clock, DIN is the serial data input

for the DAC, and DOUT is the serial data output for the ADC.

Figure 6 shows the serial interface format for the PCM3500.

The serial data for DIN and DOUT must be in Binary Two’s

Complement, MSB-first format. Figures 7 and 8 show the

timing specifications for the serial interface when used in

Slave and Master Modes.

The frame sync, FS, operates at the sampling frequency (f_S).

The bit clock, BCK, operates at 16f_Sfor normal operation.

DIN and DOUT also operate at the bit clock rate. Both FS

and BCK must be synchronous with the system clock (guar-

FS

BCK

DIN

15 14 13 12 11

MSB

5

4

3

2

1

0

15 14 13 12 11

5

4

3

2

1

0

LSB MSB

LSB

DOUT

15 14 13 12 11

MSB

0

15 14 13 12 11

0

LSB MSB

LSB

1/f_S

16-Bit/Frame

FIGURE 6. Serial Interface Format.

t_FSP

t_FSW

FS

(input)

0.5V_DD

t_FSSU

t_FSHD

t_BCKP

BCK

(input)

t_BCKH

t_BCKL

DIN

(input)

t_DIHD

t_DISU

DOUT

(output)

t_CKDO

NOTES: Timing measurement reference level is (V /V )/2. RIsing and falling time is measured

IH IL

from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT signal is 50pF.

SYMBOL DESCRIPTION

MIN

TYP

MAX

UNITS

t_BCKP

BCK Period

2400

800

ns

t_BCKH

t_BCKL

t_FSW

t_FSP

BCK Pulse Width HIGH

BCK Pulse Width LOW

800

FS Pulse Width HIGH

t_BCKP– 60

t_BCKP

1/f_S

t_BCKP+ 60

FS Period

t_FSSU

t_FSHD

t_DISU

t_DIHD

t_CKDO

t_R

FS Set Up Time to BCK Rising Edge

FS Hold Time to BCK Rising Edge

DIN Set Up Time to BCK Rising Edge

DIN Hold Time to BCK Rising Edge

Delay Time BCK Falling Edge to DOUT

Rising Time of All Signals

Falling Time of All Signals

60

0

ns

80

30

t_F

FIGURE 7. Serial Interface Timing for Slave Mode.

®

PCM3500

14

t_FSP

t_FSW

FS

(output)

0.5V_DD

t_CKFS

t_BCKP

BCK

(output)

t_BCKH

t_BCKL

DIN

(input)

t_DIHD

t_DISU

DOUT

(output)

t_CKDO

NOTES: Timing measurement reference level is (V /V )/2. Rising and falling time is measured from

IH IL

10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FS, BCK signal is 50pF.

SYMBOL DESCRIPTION

MIN

TYP

MAX

UNITS

t_BCKP

t_BCKH

t_BCKL

t_CKFS

t_FSW

t_FSP

BCK Period

2400

1200

16000

8000

ns

BCK Pulse Width HIGH

BCK Pulse Width LOW

1200

8000

Delay Time BCK Falling Edge to FS

FS Pulse Width HIGH

– 40

40

t_BCKP– 60

t_BCKP

1/f_S

t_BCKP+ 60

FS Period

t_DISU

t_DIHD

t_CKDO

t_R

DIN Set Up Time to BCK Rising Edge

DIN Hold Time to BCK Rising Edge

Delay Time BCK Falling Edge to DOUT

Rising Time of All Signals

Falling Time of All Signals

60

0

ns

80

30

t_F

FIGURE 8. Serial Interface Timing for Master Mode.

System

Clock

System

Clock

PCM3500

XTI

FS

XTI

FS

BCK

DIN

Controller

DIN

GND

V_DD

M/S

DOUT

M/S

TSC

DOUT

GND

TSC

Slave Mode

Master Mode

FIGURE 9. Slave and Master Mode Connections.

Slave Mode Operation

MASTER/SLAVE OPERATION

In Slave Mode, the FS and BCK pins are inputs to the

PCM3500. Both FS and BCK should be derived from the

system clock signal (XTI or SCKIO) to ensure proper

synchronization. Slave Mode is best suited for applications

where the DSP or controller is capable of generating the FS,

BCK, and system clocks using an on-chip serial port and/or

timing generator.

The serial interface supports both Slave and Master Mode

operation. The mode is selected by the M/S input (pin 6).

Table II shows mode and pin settings corresponding to the

M/S input selection. Figure 9 shows connections for Slave

and Master mode operation.

SERIAL

INTERFACE

Master Mode Operation

M/S (PIN 6)

MODE

FS (PIN)

BCK (PIN 8)

In Master Mode operation, both FS and BCK are clock

outputs generated by the PCM3500 from the system clock

input (XTI, SCKIO, or a crystal). In Master Mode, the timing

and phase relationships between system clock, FS, and BCK

are managed internally to provide optimal synchronization.

0

1

Slave

Input

Master

Output

TABLE II. Master/Slave Mode Selection.

®

15

PCM3500

interface bus. This is useful for system applications that

require multiple modem or voice channels. Figure 11 shows

examples of Time Slot Mode connections.

SYNCHRONIZATION REQUIREMENTS

The PCM3500 requires that FS and BCK be synchronous

with the system clock. Internal circuitry is included to detect

a loss of synchronization between FS and the system clock

input. If the phase relationship between FS and the system

clock varies more than ± 1.5 BCK periods, the PCM3500

will detect a loss of synchronization. Upon detection, the

DAC output is forced to 0.5V_CCand the DOUT pin is forced

to a high impedance state. This occurs within one sampling

clock (FS) period of initial detection. Figure 10 shows the

loss of synchronization operation and the DAC and ADC

output delays associated with it.

Time Slot Mode defines a 64-bit long frame, composed of

four time slots. Each slot is 16 bits long and corresponds to

one of four CODECs. The FS pin on the first PCM3500

(CODEC A, Slot 0) is used as the master frame sync, and

operates at the sampling frequency, f_S. The bit clock, BCK,

operates at 64f_S. DIN and DOUT of each CODEC also

operate at 64f_S. Figure 12 shows the operation of the Time

Slot Mode.

Time Slot operation is enabled or disabled using the TSC

input (pin 7). The state of the TSC pin is updated at power-

on reset, or on the rising edge of PWDN input (if using

external reset or power-down mode). A forced reset is

required when changing from Slave to Master Mode, or visa

versa, in real time.

TIME SLOT OPERATION

The PCM3500 serial interface supports Time Division

Multiplexing (TDM) using the Time Slot Mode. Up to four

PCM3500s may be connected on the same 4-wire serial

Synchronization

Lost

Resynchronization

State of

Synchronization

Synchronous

Asynchronous

Synchronous

within

1/f_S

t_DACDLY2(32/f_S)

V_COM

(0.5 V_CC

V_COM

(0.5 V_CC

Undefined Data

Normal

)

DAC V_OUT

Normal

t_ADCDLY2(32/f_S)

Undefined Data

Normal

High Impedance

Normal⁽¹⁾

ADC DOUT

NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR

with 200ms time constant) appears initially.

FIGURE 10. Loss of Synchronization Operation and Timing.

PCM3500

(CODEC A, Slot 0)

SCKIO

FS

XTI

Controller

XTO

BCK

DIN

V_DD

M/S

DOUT

FSO

TSC

PCM3500

(CODEC B, Slot 1)

SCKIO

FS

XTI

XTO

BCK

DIN

M/S

GND

V_DD

DOUT

FSO

TSC

To Two PCM3500s

FIGURE 11. Time Slot Mode Connections.

®

PCM3500

16

One Frame = 1/f_S, 64 Bits per Frame, 16 Bits per Slot

CODEC A

CODEC B

CODEC C

CODEC D

Slot 0, 16 Bits

Slot 1, 16 Bits

Slot 2, 16 Bits

Slot 3, 16 Bits

FS

BCK

FS (A)

FSO (A)

FS (B)

FSO (B)

FS (C)

FSO (C)

FS (D)

FSO (D)

DIN

DOUT (A)

DOUT (B)

DOUT (C)

DOUT (D)

MSB

LSB

High Impedance

FIGURE 12. Time Slot Mode Operation.

®

17

PCM3500

ate in Loop-Back Mode, allowing the host to read the ADC

data at the DOUT pin.

Table III shows the TSC pin settings and corresponding

mode selections. When Time Slot Mode is enabled, FSO

(pin 12) is used as a frame sync output, which is connected

to the FS input of the next PCM3500 in the Time Slot

sequence. Figures 13 and 14 provide detailed timing for

Time Slot Mode operation.

LOOP (PIN 19)

LOOP-BACK MODE

0

1

Loop-Back Mode Disabled, Normal Operation

Loop-Back Mode Enabled

TABLE IV. Loop-Back Mode Selection.

TSC (PIN 7)

TIME SLOT MODE

0

1

Time Slot Mode Disabled, Normal Operation

Time Slot Operation Enable

HIGH-PASS FILTER

The PCM3500 includes a digital high-pass filter in the ADC

which may be used to remove the DC offset created by the

analog front-end (AFE) section. The high-pass filter response

is shown in Figure 15. The high-pass filter may be enabled or

disabled using the HPFD input (pin 18). Table V shows the

HPFD pin settings and corresponding mode selections.

TABLE III. Time Slot Mode Selection.

ADC-TO-DAC LOOP BACK

The PCM3500 includes a Loop-Back Mode, which directly

feeds the ADC data to the DAC input. This mode is designed

for diagnostic testing and system adjustment. Loop-Back

Mode is enabled and disabled using the LOOP input (pin

19). Table IV shows the LOOP pin settings and correspond-

ing mode selections. The serial interface continues to oper-

HPFD (PIN 18)

HIGH-PASS FILTER MODE

0

1

High-Pass Filter On

High-Pass Filter Off

TABLE V. High-Pass Filter Mode Selection.

t_FSP

t_FSW

FS

(input)

0.5V_DD

t_FSSU

t_FSHD

t_BCKP

BCK

(input)

0.5V_DD

t_BCKL

t_BCKH

DIN

(input)

0.5V_DD

t_DIHD

High Impedance

t_DISU

High Impedance

0.5V_DD

DOUT

(output)

t_HZDO

t_CKDO

t_DOHZ

FSO

(output)

0.5V_DD

t_BFSO

t_FSOW

NOTES: Timing measurement reference level is (V /V )/2. Rising and falling time is measured from

IH IL

10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, and FSO signal is 50pF.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_BCKP

t_BCKH

t_BCKL

t_FSW

t_FSP

BCK Period

600

200

ns

BCK Pulse Width HIGH

BCK Pulse Width LOW

200

FS Pulse Width HIGH

t_BCKP– 60

t_BCKP

1/f_S

t_BCKP+ 60

FS Period

t_FSSU

t_FSHD

t_DISU

t_DIHD

t_CKDO

t_HZDO

t_DOHZ

t_FSOW

t_BFSO

t_R

FS Set Up TIme to BCK Rising Edge

FS Hold TIme to BCK RIsing Edge

DIN Set Up Time to BCK Rising Edge

DIN Hold Time to BCK Rising Edge

Delay Time BCK Falling Edge to DOUT

Delay Time BCK Falling Edge to DOUT Active

Delay Time BCK Falling Edge to DOUT Inactive

FSO Pulse Width HIGH

60

0

ns

80

20

19.5

t_BCKP

t_BCKP– 60

0

t_BCKP+ 60

Delay Time BCK Falling Edge to FSO

Rising Time of All Signals

80

30

t_F

Falling Time of All Signals

FIGURE 13. Serial Interface Timing for Time Slot Mode Operation (Slave Mode).

®

PCM3500

18

t_FSP

t_FSW

FS

(output)

0.5V_DD

t_BCKP

t_CKFS

BCK

(output)

t_BCKL

t_BCKH

DIN

(input)

t_DIHD

High Impedance

t_DISU

High Impedance

0.5V_DD

DOUT

(output)

t_HZDO

t_CKDO

t_DOHZ

FSO

(output)

0.5V_DD

t_BFSO

t_FSOW

NOTES: Timing measurement reference level is (V /V )/2. Rising and falling time is measured from

IH IL

10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FSO, FS, and BCK signal is 50pF.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_BCKP

t_BCKH

t_BCKL

t_CKFS

t_FSW

t_FSP

BCK Period

600

300

4000

2000

ns

BCK Pulse Width HIGH

BCK Pulse Width LOW

300

2000

Delay Time BCK Falling Edge to FS

FS Pulse Width HIGH

–40

40

t_BCKP– 60

t_BCKP

1/f_S

t_BCKP+ 60

FS Period

t_DISU

t_DIHD

t_CKDO

t_HZDO

t_DOHZ

t_FSOW

t_BFSO

t_R

DIN Set Up Time to BCK Rising Edge

DIN Hold Time to BCK Rising Edge

Delay Time BCK Falling Edge to DOUT

Delay Time BCK Falling Edge to DOUT Active

Delay Time BCK Falling Edge to DOUT Inactive

FSO Pulse Width HIGH

60

0

ns

80

20

19.5

t_BCKP

t_BCKP– 60

0

t_BCKP+ 60

Delay Time BCK Falling Edge to FSO

Rising Time of All Signals

80

30

t_F

Falling Time of All Signals

FIGURE 14. Serial Interface Timing for Time Slot Mode Operation (Master Mode).

HIGH-PASS FILTER FREQUENCY RESPONSE

STOPBAND CHARACTERISTICS

HIGH-PASS FILTER FREQUENCY RESPONSE

PASSBAND CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–10

0

0.1

0.2

0.3

0.4

0.5

0

1

2

3

4

Normalized Frequency (• f_S/1000 Hz)

FIGURE 15. High-Pass Filter Response.

®

19

PCM3500

unbuffered on pin 1 for decoupling. A 1µF to 10µF alumi-

num electrolytic or tantalum capacitor is recommended for

decoupling purposes. This capacitor should be located as

close as possible to pin 1.

APPLICATIONS INFORMATION

BASIC CIRCUIT CONNECTIONS

The basic connection diagram for the PCM3500 is shown in

Figure 16. Included are the required power supply bypass and

reference decoupling capacitors. The DAC output, V_OUT, and

the ADC input, V_IN, should be AC-coupled to external cir-

cuitry.

The V_COMvoltage is typically equal to V_CC/2, and may be

used to bias external input and output circuitry. However,

since the V_COMpin is not a buffered output, it must drive a

high impedance load to avoid excessive loading. Buffering

the V_COMpin with an external op amp configured as a

voltage follower is recommended when driving multiple bias

nodes. Figure 17 shows examples of using V_COMwith

external circuitry.

Reference Pin Connections

The V_COMvoltage is used internally to bias the input and

output amplifier stages of the PCM3500. It is brought out

PCM3500

C₃

C₄

C₅

+

+3.3V

1

2

3

4

5

6

7

8

9

V_COM

V_REF

V_CC24

AGND 23

V_OUT22

AGND 21

PDWN 20

LOOP 19

HPFD 18

XTI 17

+

C₁

1

V

_REF2

V_IN

External Reset

Power-Down Control

AGND

M/S

TSC

BCK

FS

XTO 16

Serial

Interface

External Clock System

10 DIN

SCKIO 15

DGND 14

V_DD13

C₂

11 DOUT

12 FSO

+

C₆

C₇

Analog Line Interface Circuit

Telecom Line

C₁, C₂: Power supply bypass capacitors. Parallel combination of a 1µF to 10µF aluminum electrolytic capacitor and 0.1µF ceramic capacitor.

C₃, C₄, C₅: V_REFand V_COMbypass capacitors. Use a 1µF to 10µF aluminum electrolytic capacitor.

C₆, C₇: Input/output AC-coupling capacitors. Use a 0.1µF to 10µF aluminum electrolytic capacitor.

FIGURE 16. Basic Connection Diagram.

(a) Biasing an External Active Filter Stage

V_CC

Non-Polarized

1µF

PCM3500

(b) Using a Buffer to Provide Bias for Multiple or

Low Input Impedance Nodes

V_OUT

OPA343

V_COM

Use voltage follower

to buffer V_COM

+

4.7µF

PCM3500

V_COM

To Bias

Nodes

+

OPA340

4.7µF

FIGURE 17. Using V_COMto Bias External Circuitry.

®

PCM3500

20

V_REF1 (pin 2) and V_REF2 (pin 3) are reference voltages used

by the delta-sigma modulators. They are brought out strictly

for decoupling purposes. V_REF1 and V_REF2 are not to be

used to bias external circuits. A 1µF to 10µF aluminum

electrolytic or tantalum capacitor is recommended for

decoupling on each pin. These capacitors should be located

as close as possible to pins 2 and 3.

by a split ground plane, with the PCM3500 positioned

entirely over the analog section of the board. The AGNDs

(pins 5, 20, and 23) and DGND (pin 14) are connected

directly to the analog ground plane. The power supply pins,

V_CC(pin 13) and V_DD(pin 24), are routed directly to the

+2.7V to +3.6V analog power supply using wide copper

traces (100 mils or wider recommended) or a power plane.

Power supply bypass and reference decoupling capacitors

are shown located as close as possible to the PCM3500.

Power Supplies and Grounding

V_CC(pin 24) and V_DD(pin 13) should be connected directly

to the +2.7V to +3.6V analog power supply, as shown in

Figure 16. The AGNDs (pins 5, 21, and 23) and DGND (pin

14) should be connected directly to the analog ground.

Power supply bypass capacitors should be located as close

to the power supply pins as possible in order to ensure a low

impedance connection. A combination of a 10µF aluminum

electrolytic or tantalum capacitor in parallel with a 0.1µF

The PCM3500 is oriented so that the digital pins are facing

the ground plane split. Digital connections should be made

as short and direct as possible to limit high frequency

radiation and coupling. Series resistors (from 20Ω to 100Ω)

may be put in series with the system clock, FS, BCK, and

FSO lines to reduce or eliminate overshoot on clock edges,

further reducing radiated emissions. The split ground plane

should be connected at one point by a trace, wire, or ferrite

bead. Often the board will be designed to have several

jumper points for the common ground connection, so that

the best performance can be derived through experimenta-

tion.

ceramic capacitor is recommended for both V_CCand V_DD

.

V_DDand V_CCshould not be connected to separate digital and

analog power supplies. This can lead to an SCR latch-up

condition, which can cause either degraded device perfor-

mance or catastrophic failures.

An alternative technique, using a single power supply or

battery, is shown in Figure 19. This technique is more

suitable for portable applications.

PCB LAYOUT GUIDELINES

The recommended PCB layout technique is shown in Figure

18. The analog and digital section of the board are separated

Digital Power

Supply

Analog Power

Supply

Common

Supply

Ferrite

Beads

Common

Connection

+3.3V

V_CC

V_DD

Host

and

V_CC

V_DD

PCM3500

Host

and

Logic

AGND DGND

PCM3500

Logic

AGND DGND

Digital I/Os

DIGITAL SECTION

Digital I/Os

DIGITAL SECTION

ANALOG SECTION

Split Grounds

Analog

Ground

Digital

Ground

Analog

Ground

Digital

Ground

FIGURE 18. Recommended PCB Layout Technique.

FIGURE 19. PCB Layout Using a Single-Supply or Battery.

®

21

PCM3500

OUTPUT FILTER CIRCUITS FOR THE DAC

noise requirements for a particular system. Generally, a 2nd-

order or better low-pass circuit will be required, with the

cut-off frequency set to f_S/2 or less.

The PCM3500’s DAC uses delta-sigma conversion tech-

niques. It uses oversampling and noise shaping to improve

in-band (f = f_S/2) signal-to-noise performance at the expense

of increased out-of-band noise. The DAC output must be

low-pass filtered to attenuate the out-of-band noise to a

reasonable level.

Burr-Brown Application Bulletin AB-034 provides infor-

mation for designing both Multiple Feedback and Sallen-

Key active filter circuits using software available from Burr-

Brown’s web site. Another excellent reference for both

passive and active filter design is the “Electronic Filter

Design Handbook, Third Edition” by Williams and Taylor,

published by McGraw-Hill.

The PCM3500 includes a low-pass filter in the on-chip

output amplifier circuit. The frequency response for this

filter is shown in Figure 20. Although this filter helps to

lower the out-of-band noise, it is not adequate for many

applications. This is especially true for applications where

the sampling frequency is below 16kHz, since the out-of-

band noise above f_S/2 is in the audio spectrum. An external

filter circuit, either passive or active, is required to provide

additional attenuation of the out-of-band noise. The low-

pass filter order will be dependent upon the out-of-band

ON-CHIP ANALOG FRONT END FOR THE ADC

The PCM3500 A/D converter includes a fully differential

input delta-sigma modulator. In order to simplify connection

for single-ended applications, an analog front end (AFE)

circuit has been included on the PCM3500 just prior to the

modulator. The AFE circuit is shown in Figure 21.

OUTPUT FILTER

STOPBAND FREQUENCY RESPONSE

0

PASSBAND FREQUENCY RESPONSE

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

Frequency (Hz)

FIGURE 20. DAC Output Amplifier Filter Response.

1.0µF

50kΩ

V_IN

4

+

(+)

(–)

Delta-Sigma

Modulator

V_COM

1

2

3

V_REF

1

2

+

Reference

+

FIGURE 21. On-Chip AFE Circuit for the ADC.

®

PCM3500

22

The AFE circuit consists of a single-ended-to-differential

converter, with the first stage of the circuit doubling as a

low-pass, anti-alias filter. The frequency response for the

filter is shown in Figure 22. Since the delta-sigma modulator

oversamples the input at 64f_S, the anti-alias filter require-

ments are relaxed, with only a single-pole filter being re-

quired. If an application requires further band limiting of the

input signal, a simple RC filter at the V_INinput (pin 4) can

be used, as shown in Figure 23.

provide the complete modem function. Figure 24 shows a

simplified block diagram of a software modem using the

PCM3500.

The DAA provides the interface between the CODEC and

two-wire telephone line. The DAA provides numerous

functions, including two-to-four wire conversion, modem-

side to line-side isolation, ring detection, hook switch con-

trol, line current compensation, and overvoltage protection.

The host CPU provides the data pump and supervisory

functions for the software modem application. The host

executes modem software code, which includes the neces-

sary routines for transmit and receive functions, error detec-

tion and correction, echo cancellation, and CODEC/DAA

control and supervision.

SOFTWARE MODEM

APPLICATIONS

The PCM3500 was designed to meet the requirements for

software-based analog modems, supporting up to 56kbps⁽¹⁾.

In a software modem application, the PCM3500 is paired

with a Data Access Arrangement (DAA) and a host CPU to

NOTE: (1) Data transmission is limited to 53kbps over standard telephone

lines. Actual transmission rates vary depending upon the quality of the

lines and switching equipment for a given connection.

ANTI-ALIASING FILTER

PASSBAND CHARACTERISTICS

0

STOPBAND CHARACTERISTICS

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

1

10

100

1k

10k

100k

100

1k

10k

100k

1M

10M

Frequency (Hz)

FIGURE 22. Anti-Alias Filter Frequency Response.

Modem

Software

PCM3500

R

Analog

Input

+

V_IN

Data

Access

Arrangement

(DAA)

Tip

Ring

Host

CPU

PCM3500

CODEC

C

Data

1

2π RC

f_–3dB

=

Controls (ring detect, off hook, etc.)

FIGURE 23. Optional External Low-Pass Filter for the

ADC.

FIGURE 24. Software Modem Block Diagram.

®

23

PCM3500

I S O L A T I O N B A R R I E R

I S O L A T I O N B A R R I E

®

PCM3500

24

Software Modem AFE Application Circuit

wide dynamic range and excellent power supply rejection

performance. The input signal is sampled at a 64x

oversampling rate, eliminating the need for a sample-and-

hold circuit, and simplifying anti-alias filtering require-

ments. The 5th-order delta-sigma noise shaper consists of

five integrators which use a switched-capacitor topology, a

comparator, and a feedback loop consisting of a one-bit

DAC. The delta-sigma modulator shapes the quantization

noise, shifting it out of the audio band in the frequency

domain. The high order of the modulator enables it to

randomize the modulator outputs, reducing idle tone levels.

Figure 25 shows an applications circuit which utilizes the

PCM3500 and the DAA2000 from Infineon Technologies

(Siemens) to implement a complete modem AFE. The

DAA2000 provides modem-side (DM207) and line-side

(DL207) interfaces, with optical isolation separating the

functions. The PCM3500 is connected to the modem-side of

the DAA2000. The PCM3500’s serial interface and hard-

ware mode controls are connected to the host CPU.

The 64f_Sone-bit data stream from the modulator is con-

verted to 1f_S, 16-bit data words by the decimation filter,

which also acts as a low-pass filter to remove the shaped

quantization noise. The DC components can be removed by

a high-pass filter function contained within the decimation

filter.

THEORY OF OPERATION

ADC SECTION

The PCM3500 A/D converter consists of two reference

circuits, a mono single-to-differential converter, a fully dif-

ferential 5th-order delta-sigma modulator, a decimation fil-

ter (including digital high pass), and a serial interface circuit.

The block diagram on the front page of this data sheet

illustrates the architecture of the ADC section, Figure 21

shows the single-to-differential converter, and Figure 26

illustrates the architecture of the 5th-order delta-sigma modu-

lator and transfer functions.

DAC SECTION

The delta-sigma DAC section of PCM3500 is based on a 5-

level amplitude quantizer and a 3rd-order noise shaper. This

section converts the oversampled input data to 5-level delta-

sigma format. A block diagram of the 5-level delta-sigma

modulator is shown in Figure 27. This 5-level delta-sigma

modulator has the advantage of stability and clock jitter

sensitivity over the typical one-bit (2 level) delta-sigma

modulator. The combined oversampling rate of the delta-

sigma modulator and the internal 8x interpolation filter is

64f_Sfor a 512f_Ssystem clock. The theoretical quantization

noise performance of the 5-level delta-sigma modulator is

An internal reference circuit with three external capacitors

provides all reference voltages which are required by the

ADC, which defines the full-scale range for the converter.

The internal single-to-differential voltage converter saves

the design, space and extra parts needed for external cir-

cuitry required by many delta-sigma converters. The internal

full-differential signal processing architecture provides a

shown in Figure 28.

Analog In

X(z)

–

+

–

1st SW-CAP

Integrator

+

2nd SW-CAP

Integrator

3rd SW-CAP

Integrator

+

4th SW-CAP

Integrator

5th SW-CAP

Integrator

Qn(z)

Digital Out

Y(z)

+

H(z)

Comparator

1-Bit

DAC

Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)

Signal Transfer Function

Noise Transfer Function

STF(z) = H(z)/[1 + H(z)]

NTF(z) = 1/[1 + H(z)]

FIGURE 26. Simplified 5th-Order Delta-Sigma Modulator.

®

25

PCM3500

+

–

+

–

+

Z^–1

In

8f_S

18-Bit

+

5-level Quantizer

4

3

2

1

0

Out

64f_S

FIGURE 27. 5-Level Delta-Sigma Modulator Block Digram.

3rd-ORDER ∆Σ MODULATOR

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

0

5

10

15

20

25

30

Frequency (kHz)

FIGURE 28. Quantization Noise Spectrum.

®

PCM3500

26

PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2003

PACKAGING INFORMATION

ORDERABLE DEVICE

STATUS(1)

PACKAGE TYPE

PACKAGE DRAWING

PINS

PACKAGE QTY

PCM3500E

ACTIVE

SSOP

DB

24

58

PCM3500E/2K

2000

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	PCM3500EG4
厂家：	TEXAS INSTRUMENTS
描述：	低电压、低功耗、16 位、单声道 SoundPlus™ 语音/调制解调器编解码器 \| DB \| 24 光电二极管消费电路商用集成电路编解码器调制解调器
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PCM3500EG4 [TI]

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