PCM3794A [TI]
Low-Power Stereo Audio CODEC;
| 型号： | PCM3794A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Power Stereo Audio CODEC |
| 文件： | 总68页 (文件大小：1690K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM3793 is Not Recommended for New Designs
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PCM3793
PCM3794
SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital
Speaker Amplifier
FEATURES
•
•
2 (I2C) or 3 (SPI) Wire Serial Control
•
Analog Front End:
Programmable Function by Register Control:
–
–
–
–
Stereo Single-Ended Input With Multiplexer
Mono Differential Input
–
–
–
–
–
Digital Attenuation of DAC: 0 dB to –62 dB
Power Up/Down Control for Each Module
6-dB to –70-dB Gain for Analog Outputs
30-dB to –12-dB Gain for Analog Inputs
Stereo Programmable Gain Amplifier
Microphone Boost Amplifier (20 dB) and
Bias
0/20 dB Boost Selectable for Microphone
Input
•
•
Analog BackEnd:
–
–
Stereo/Mono Line Output With Volume
–
–
–
–
0-dB to –21-dB Gain for Analog Mixing
Parameter Settings for ALC
Stereo/Mono Headphone Amplifier With
Volume and Capless Mode
Three-Band Tone Control and 3D Sound
–
Stereo/Mono Digital Speaker Amplifier
(BTL) With Volume (PCM3793)
High-Pass Filter and Two-Stage Notch
Filter
Analog Performance:
–
Analog Mixing
–
–
–
Dynamic Range: 93 dB (DAC)
Dynamic Range: 90 dB (ADC)
•
•
•
•
Pop-Noise Reduction Circuit
Short and Thermal Protection Circuit
Package: 5-mm × 5-mm QFN Pacakge
Operation Temperature Range: –40°C to 85°C
40-mW + 40-mW Headphone Output at
RL = 16 Ω
–
700-mW + 700-mW Speaker Output at
RL = 8 Ω
APPLICATIONS
•
•
Power Supply Voltage
•
•
•
Portable Audio Player, Cellular Phone
Video Camcorder, Digital Still Camera
PMP/DMB
–
–
–
–
1.71 V to 3.6 V for Digital I/O Section
1.71 V to 3.6 V for Digital Core Section
2.4 V to 3.6 V for Analog Section
DESCRIPTION
2.4 V to 3.6 V for Power Amplifier Section
The PCM3793/94 is a low-power stereo CODEC
designed for portable digital audio applications. The
device integrates stereo digital speaker amplifier,
headphone amplifier, line amplifier, line input, boost
amplifier, microphone bias, programmable gain
control, analog mixing, sound effects, and automatic
level control (ALC). It is available in a small-footprint,
5-mm × 5-mm QFN package. The PCM3793/94
accepts right-justified, left-justified, I2S, and DSP
formats, providing easy interfacing to audio DSP,
decoder, and encoder chips. Sampling rates up to 50
kHz are supported. The user-programmable
functions are accessible through a two- or three-wire
serial control port.
Low Power Dissipation:
–
–
–
7 mW in Playback, 1.8 V/2.4 V, 48 kHz
13 mW in Record, 1.8 V/2.4 V, 48 kHz
30 µW in Power Down
•
•
•
Sampling Frequency: 5 kHz to 50 kHz
Automatic Level Control for Recording
Operation From a Single Clock Input Without
PLL
•
•
System Clock:
–
Common-Audio Clock (256 fS/384 fS), 12/24,
13/26, 13.5/27, 19.2/38.4, 19.68/39.36 MHz
Headphone Plug Insert Detection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
PCM3793 is Not Recommended for New Designs
PCM3793
PCM3794
www.ti.com
SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION
OPERATION
TEMPERATURE
RANGE
PACKAGE
CODE
PACKAGE
MARKING
ORDERING
NUMBER(1)
PRODUCT
PACKAGE
TRANSPORT MEDIA
PCM3793RHBT
PCM3793RHBR
PCM3794RHBT
PCM3794RHBR
Small tape and reel
Large tape and reel
Small tape and reel
Large tape and reel
PCM3793RHB
PCM3794RHB
32 QFN
32 QFN
RHB
RHB
–40°C to 85°C
–40°C to 85°C
PCM3793
PCM3794
(1) For the most current specification and package information, see the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
PCM3793/94
UNIT
V
Supply voltage
VDD, VIO, VCC, VPA
–0.3 to 4
±0.1
Ground voltage differences: DGND, AGND, PGND
Input voltage
V
–0.3 to 4
±10
V
Input current (any pins except supplies and SPK out)
Ambient temperature under bias
Storage temperature
mA
°C
–40 to 110
–55 to 150
150
°C
Junction temperature
°C
Lead temperature (soldering)
Package temperature (reflow, peak)
260
°C, 5 s
°C
260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
2.4
NOM
3.3
MAX UNIT
VCC, VPA
VDD , VIO
Analog supply voltage
Digital supply voltage
Digital input logic family
3.6
3.6
V
V
1.71
3.3
CMOS
SCKI system clock
3.072
8
18.432
48
MHz
kHz
kΩ
Ω
Digital input clock frequency
LRCK sampling clock
LOL and LOR
10
16
8
Analog output load resistance
HPOL and HPOR
SPOLP, SPOLN, SPORP and SPORN
Ω
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature
30
10
85
pF
pF
°C
TA
–40
2
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless
otherwise noted).
PCM3793RHB, PCM3794RHB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Audio Data Characteristics
DATA FORMAT
Resolution
16
Bits
Bits
Audio data interface format
I2S, left-, right-justified, DSP
Audio data bit length
Audio data format
16
MSB first, 2s complement
5
Sampling frequency (fS)
50
27
40
kHz
VDD < 2 V
VDD > 2 V
System clock
MHz
Digital Input/Output
Logic family
CMOS compatible
0.7 VIO
VIH
VIL
IIH
VDC
VDC
Input logic level
0.3 VIO
10
VIN = 3.3 V
VIN = 0 V
Input logic current
Output logic level
µA
IIL
–10
VOH
VOL
IOH = –2 mA
IOL = 2 mA
0.75 VIO
VDC
VDC
0.25 VIO
Digital Input to Line Output Through DAC (LOL, LOR, and MONO)
RL = 10 kΩ, ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = disabled
DYNAMIC PERFORMANCE
0 dB
2.828
Vp-p
Vrms
dB
Full-scale output voltage
1
93
Dynamic range
EIAJ, A-weighted
EIAJ, A-weighted
SNR
Signal-to-noise ratio
Channel separation
86
10
93
dB
91
dB
THD+N Total harmonic distortion + noise 0 dB
Load resistance
0.008%
kΩ
Line Input to Line Output Through Mixing Path (LOL, LOR, and MONO)
RL = 10 kΩ, ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled
DYNAMIC PERFORMANCE
2.828
1
Vp-p
Vrms
dB
Full-scale input and output
voltage
0 dB
SNR
Signal-to-noise ratio
EIAJ, A-weighted
84
93
3
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless
otherwise noted).
PCM3793RHB, PCM3794RHB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Digital Input to Headphone Output Through DAC (HPOL and HPOR)
RL = 16 Ω or 32 Ω, ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = disabled, not capless mode
DYNAMIC PERFORMANCE
2.828
Vp-p
Vrms
dB
Full-scale output voltage
Signal-to-noise ratio
0 dB
1
93
SNR
EIAJ, A-weighted
84
16
30 mW, RL = 32 Ω, volume = 0 dB
40 mW, RL = 16 Ω, volume = –1 dB
0.1%
0.03%
THD+N Total harmonic distortion + noise
Load resistance
Ω
200 Hz, 140 mVp-p
1 kHz, 140 mVp-p
20 kHz, 140 mVp-p
–40
–45
–32
PSRR
Power-supply rejection ratio
dB
Line Input to Headphone Output Through Mixing Path (HPOL and HPOR)
RL = 16 Ω or 32 Ω, ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled, not capless mode
DYNAMIC PERFORMANCE
2.828
Vp-p
Vrms
dB
Full-scale output voltage
0 dB
1
SNR
Signal-to-noise ratio
Load resistance
EIAJ, A-weighted
84
16
93
Ω
Digital Input to Speaker Output Through DAC (SPOLP, SPOLN, SPORP, and SPORN): PCM3793
RL = 8 Ω, ALC = OFF, volume = 0 dB, headphone = powered down, analog mixing = disabled
DYNAMIC PERFORMANCE
2.52
0.9
Vp-p
Vrms
dB
Full-scale output voltage
Signal-to-noise ratio
0 dB
SNR
EIAJ, A-weighted
84
8
93
THD+N Total harmonic distortion + noise 400 mW, RL = 8Ω, volume = 0 dB
0.3%
Load resistance
Ω
200 Hz, 140 mVp-p
–50
–45
–25
PSRR
Power-supply rejection ratio
1 kHz, 140 mVp-p
20 kHz, 140 mVp-p
dB
Line Input to Speaker Output Through Mixing Path (SPOLP, SPOLN, SPORP, and SPORN): PCM3793
RL = 8Ω, ALC = OFF, volume = 0 dB, headphone = powered down, analog mixing = enabled
DYNAMIC PERFORMANCE
2.52
0.9
93
Vp-p
Vrms
dB
Full-scale output voltage
Signal-to-noise ratio
0 dB
SNR
EIAJ, A-Weighted
84
4
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless
otherwise noted).
PCM3793RHB, PCM3794RHB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Line Input to Digital Output Through ADC (AIN1L/R, AIN2L/R, AIN3L, and AIN3L/R)
ALC = OFF, microphone boost = 0 dB, PGA = 0 dB, speaker and headphone = powered down, analog mixing = disabled
DYNAMIC PERFORMANCE
2.828
Vp-p
Vrms
dB
Full-scale input voltage
0 dB
1
90
Dynamic range
EIAJ, A-weighted
EIAJ, A-weighted
SNR
Signal-to-noise ratio
Channel separation
83
90
dB
87
dB
THD+N Total harmonic distortion + noise –1 dB
ANALOG INPUT
0.009%
Center voltage
0.5 VCC
20
V
Input impedance
10
kΩ
Microphone Bias
ALC = OFF, microphone boost = 0 dB, PGA = 0 dB, speaker and headphone = powered down, analog mixing = disabled
Bias voltage
0.75 VCC
V
Bias source current
Output noise
2
mA
µV
14
Filter Characteristics
INTERPOLATION FILTER FOR DAC
Pass band
0.454 fS
Stop band
0.546 fS
–50
Pass-band ripple
±0.04
dB
dB
s
Stop-band attenuation
Group delay
19/fs
De-emphasis error
ANALOG FILTER FOR DAC
Frequency response
DECIMATION FILTER FOR ADC
Pass band
±0.1
dB
f = 20 kHz
±0.2
dB
0.408 fS
Stop band
0.591 fS
–60
Pass-band ripple
±0.02
dB
dB
s
Stop-band attenuation
Group delay
f < 3.268 fS
17/fS
HIGH-PASS FILTER FOR ADC
–3 dB, fc = 4 Hz
3.74
10.66
–0.5 dB, fc = 4 Hz
–0.1 dB, fc = 4 Hz
–3 dB, fc = 240 Hz
–0.5 dB, fc = 240 Hz
–0.1 dB, fc = 240 Hz
24.2
Frequency response
Hz
235.68
609.95
2601.2
5
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless
otherwise noted).
PCM3793RHB, PCM3794RHB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Power Supply and Supply Current
VIO
VIO
1.71
1.71
2.4
3.3
3.3
3.3
3.3
24.3
9
3.6
3.6
VDD
VDD
VCC
VPA
Voltage range
VCC
VDC
3.6
VPA
2.4
3.6
BPZ input, all active, no load
All inputs are held static
BPZ input
35
mA
µA
Supply current
50
80.2
30
115.5
165
mW
µW
Power dissipation
All inputs are held static
Temperature Condition
Operation temperature
–40
85
°C
θJA
Thermal resistance
30
°C/W
6
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
PIN ASSIGNMENTS
PCM3793RHB
(TOP VIEW)
24 23 22 21 20 19 18 17
25
16
15
14
13
12
11
10
9
AIN2L
HPOR/LOR
SPOLP
26
27
28
29
30
31
32
AIN1R
AIN1L
SPOLN
MODE
MS/ADR
MD/SDA
MC/SCL
LRCK
PGND
VPA
SPORP
SPORN
HPCOM/MONO
1
2
3
4
5
6
7
8
P0048-03
PCM3794RHB
(TOP VIEW)
24 23 22 21 20 19 18 17
25
16
15
14
13
12
11
10
9
AIN2L
HPOR/LOR
26
27
28
29
30
31
32
NC
AIN1R
AIN1L
NC
MODE
MS/ADR
MD/SDA
MC/SCL
LRCK
PGND
VPA
NC
NC
HPCOM/MONO
1
2
3
4
5
6
7
8
P0048-04
7
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
AGND
AIN1L
AIN1R
AIN2L
AIN2R
AIN3L
AIN3R
BCK
PCM3793RHB
PCM3794RHB
19
27
26
25
24
23
22
1
19
27
26
25
24
23
22
1
–
I
Ground for analog
Analog input 1 for L-channel
Analog input 1 for R-channel
Analog input 2 for L-channel
Analog input 2 for R-channel
Analog input 3 for L-channel
Analog input 3 for R-channel
I
I
I
I
I
I/O Serial bit clock
DGND
DIN
6
6
–
I
Digital ground
2
2
Serial audio data input
DOUT
HDTI
3
3
O
I
Serial audio data output
8
8
Headphone plug insertion detection
Headphone common/mono line output
Headphone/lineout for R-channel
Headphone/lineout for L-channel
HPCOM/MONO
HPOL/LOL
HPOR/LOR
LRCK
9
9
O
O
O
17
16
32
31
30
21
28
29
13
7
17
16
32
31
30
21
28
29
13
7
I/O Left and right channel clock
Mode control clock for three-wire/two-wire interface
I/O Mode control data for three-wire/two-wire interface
MC/SCL
MD/SDA
MICB
I
O
I
Microphone bias source output
MODE
MS/ADR
PGND
SCKI
Two- or three-wire interface selection (LOW: SPI, HIGH: I2C)
Mode control select for three-wire/two-wire interface
Ground for speaker power amplifier
System clock
I
–
I
SPOLN
SPOLP
SPORN
SPORP
VCC
14
15
10
11
20
18
5
–
O
O
O
O
–
–
–
–
–
Speaker output L-channel for negative (PCM3793)
Speaker output L-channel for positive (PCM3793)
Speaker output R-channel for negative (PCM3793)
Speaker output R-channel for positive (PCM3793)
Analog power supply
–
–
–
20
18
5
VCOM
Analog common voltage
VDD
Power supply for digital core
VIO
4
4
Power supply for digital I/O
VPA
12
12
Power supply for power amplifier
8
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
FUNCTIONAL BLOCK DIAGRAM
3 X U M
4 X U M
1 X U M
2 X U M
9
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 8 to 48 kHz, system clock = 256 fS, and 16-bit data,
unless otherwise noted.
INTERPOLATION FILTER, STOP BAND
INTERPOLATION FILTER, PASS BAND
0
–20
0.2
0.1
–40
–60
0
–80
–0.1
–0.2
–100
–120
0
1
2
3
4
0
0.1
0.2
0.3
0.4
0.5
Frequency [´ fS]
Frequency [´ fS]
G001
G002
Figure 1.
Figure 2.
DECIMATION FILTER, STOP BAND
DECIMATION FILTER, PASS BAND
0
–20
0.2
0.1
–40
–60
0
–80
–0.1
–0.2
–100
–120
0
1
2
3
4
0
0.1
0.2
0.3
0.4
0.5
Frequency [´ fS]
Frequency [´ fS]
G003
G004
Figure 3.
Figure 4.
10
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 8 to 48 kHz, system clock = 256 fS, and 16-bit data,
unless otherwise noted.
HIGH-PASS FILTER PASS-BAND CHARACTERISTICS
(fC = 4 Hz at fS = 48 kHz)
HIGH-PASS FILTER PASS-BAND CHARACTERISTICS
(fC = 240 Hz at fS = 48 kHz)
5
5
0
–5
0
–5
–10
–15
–20
–10
–15
–20
0
0.0005
0.001
0.0015
0.002
0
0.01
0.02
0.03
0.04
Frequency [´ fS]
Frequency [´ fS]
G005
G006
Figure 5.
Figure 6.
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 16-bit data, unless
otherwise noted.
THREE-BAND TONE CONTROL (BASS, MIDRANGE,
TREBLE)
THREE-BAND TONE CONTROL (BASS)
15
10
5
15
10
5
0
0
–5
–10
–15
–5
–10
–15
100k
0
1k
0.01
0.1
1
10
100
1k
10k
400
600
800
200
Frequency – Hz
Frequency – Hz
G007
G008
Figure 7.
Figure 8.
11
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 16-bit data, unless
otherwise noted.
THREE-BAND TONE CONTROL (MIDRANGE)
THREE-BAND TONE CONTROL (TREBLE)
15
10
5
15
10
5
0
0
–5
–10
–15
–5
–10
–15
0
5k
2k
12k
14k
2k
3k
4k
6k
8k
10k
1k
4k
Frequency – Hz
Frequency – Hz
G009
G010
Figure 9.
Figure 10.
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless
otherwise noted.
ADC SNR AT HIGH GAIN (PG1/PG2 = 0 dB)
ADC SNR AT HIGH GAIN (PG1/PG2 = 20 dB)
100
90
85
70
60
50
40
90
85
80
75
70
65
60
55
50
45
40
fIN = 1 kHz
Single Input
Single Input
Differential Input
Differential Input
fIN = 1 kHz
0
25
30
0
25
30
10
15
20
10
15
20
5
5
PG3/PG4 Gain – dB
PG3/PG4 Gain – dB
G011
G012
Figure 11.
Figure 12.
12
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PCM3794
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless
otherwise noted.
THD+N/SNR vs POWER SUPPLY
DAC TO SPEAKER OUTPUT, 8-Ω
THD+N/SNR vs POWER SUPPLY
DAC TO HEADPHONE OUTPUT, 16-Ω
1
0.8
0.6
0.4
0.2
0
95
94
93
92
91
90
0.05
0.04
0.03
0.02
0.01
0
95
94
93
92
91
90
fIN = 1 kHz
fIN = 1 kHz
THD+N
THD+N
SNR
SNR
2
2.5
3
3.5
4
2
2.5
3
3.5
4
Power Supply – V
Power Supply – V
G013
G014
Figure 13.
Figure 14.
THD+N/SNR vs POWER SUPPLY
DAC TO LINE OUTPUT, 10-kΩ
THD+N/SNR vs POWER SUPPLY
ADC TO DIGITAL OUTPUT
0.012
0.011
0.010
0.009
0.008
0.007
95
94
93
92
91
90
0.012
0.011
0.010
0.009
0.008
0.007
92
91
90
89
88
87
fIN = 1 kHz
fIN = 1 kHz
THD+N
SNR
THD+N
SNR
2
2.5
3
3.5
4
2
2.5
3
3.5
4
Power Supply – V
Power Supply – V
G015
G016
Figure 15.
Figure 16.
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TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless
otherwise noted.
OUTPUT POWER vs POWER SUPPLY
OUTPUT POWER vs POWER SUPPLY
(HEADPHONE, 16-Ω)
(SPEAKER, 8-Ω)
120
100
80
60
40
20
0
900
800
700
600
500
400
300
200
100
0
fIN = 1 kHz
fIN = 1 kHz
Vol = +6 dB
Vol = 6 dB
Vol = 0 dB
Vol = 0 dB
2
3.5
4
2.5
3
2
2.5
3
3.5
4
Power Supply – V
Power Supply – V
G017
G018
Figure 17.
Figure 18.
THD+N vs OUTPUT POWER
(HEADPHONE, 16-Ω, VOLUME = 6 dB)
THD+N vs OUTPUT POWER
(HEADPHONE, 16-Ω, VOLUME = 0 dB)
100
10
1
1
fIN = 1 kHz
fIN = 1 kHz
3.3 V
2.4 V
2.4 V
2.7 V
2.7 V
3.6 V
0.1
3.3 V
0.1
3.6 V
0.01
0.01
0
100
120
0
80
40
60
80
40
60
20
20
Output Power – mW
Output Power – mW
G019
G020
Figure 19.
Figure 20.
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TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless
otherwise noted.
THD+N vs OUTPUT POWER
(SPEAKER, 8-Ω, VOLUME = 6 dB)
THD+N vs OUTPUT POWER
(SPEAKER, 8-Ω, VOLUME = 0 dB)
100
10
1
1
fIN = 1 kHz
fIN = 1 kHz
2.7 V
2.4 V
2.4 V
3.6 V
3.3 V
3.3 V
0.1
2.7 V
3.6 V
0.1
0.01
0.01
0
1000
0
600
400
600
800
400
500
200
100
200
300
Output Power – mW
Output Power – mW
G021
G022
Figure 21.
Figure 22.
OUTPUT SPECTRUM (DAC TO HEADPHONE OUTPUT,
16-Ω)
OUTPUT SPECTRUM (DAC TO SPEAKER OUTPUT, 8-Ω)
0
0
fIN = 1 kHz/–60 dB
fIN = 1 kHz/–60 dB
–20
–20
–40
–60
–40
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
5
10
15
20
0
5
10
15
20
Frequency – kHz
Frequency – kHz
G023
G024
Figure 23.
Figure 24.
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PCM3793/94 DESCRIPTION
Analog Input
The AIN1L, AIN1R, AIN2L, AIN2R, AIN3L, and AIN3R pins can be used as microphone or line inputs with
selectable 0- or 20-dB boost and 1-Vrms input. All analog inputs have high input impedance (20 kΩ), which is
not changed by gain settings. One pair of inputs is selected by register 87 (AIL[1:0], AIR[1:0]). AIN1L and AIN1R
can be used as monaural differential inputs.
Gain Settings for Analog Input
Analog signals can be adjusted from 30 dB to –12 dB in 1-dB steps following the 0- or 20-dB boost amplifier.
The gain level can be set for each channel by registers 79 and 80 (ALV[5:0], ARV[5:0]).
A/D Converter
The ADC includes a multilevel delta-sigma modulator, aliasing filter, decimation filter, high-pass filter, and notch
filter and can accept a 1-Vrms full-scale voltage input. The decimation filter has a digital soft mute controlled by
register 81 (RMUL, RMUR). The high-pass filter can be disabled by register 81 (HPF[1:0]) and the notch filter
can be disabled by registers 96 to 104 if it is not necessary to cancel a dc offset or compensate for wind noise.
D/A Converter
The DAC includes a multilevel delta-sigma modulator and interpolation filter. These can be used to obtain high
PSRR, low jitter sensitivity, and low out-of-band noise quickly and easily. The interpolation filter includes digital
attenuator, digital soft mute, three-band tone control (bass, midrange and treble), and 3-D sound controlled by
registers 92 to 95. The de-emphasis filter (32, 44.1 and 48 kHz) is controlled by registers 68 to 70 (ATL[5:0],
ATR[5:0], PMUL, PMUR, DEM[1:0]). Oversampling rate control can reduce out-of-band noise when operating at
low sampling rate by using register 70 (OVER).
Common Voltage
The VCOM pin is normally biased to 0.5 VCC, and it provides the common voltage to internal circuitry. It is
recommended that a 10-µF capacitor be connected between this pin and ground to provide clean voltage and
avoid pop noise. The PCM3793/94 may have a little pop noise on each analog output if a capacitor smaller than
10 µF is used.
Line Output
The HPOL/LOL and HPOR/LOR and HPCOM/MONO pins can be used as a monaural single-ended, monaural
differential, or stereo single-line output with 1-Vrms output by register 74 (HPS[1:0]). The line outputs can drive a
10-kΩ load. These outputs include an analog volume amplifier, except for the HPCOM/MONO pin that can be
set from 6 dB to –70 dB and mute with 0.5-, 1-, 2- or 4-dB steps for each output, as controlled by registers 64
and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). A dc blocking capacitor is not required when connecting to an
external speaker amplifier with monaural differential input. The center voltage is 0.5 VCC with zero data input.
Headphone Output
The HPOL/LOL, HPOR/LOR, and HPCOM/MONO pins are stereo, monaural, or monaural differential
headphone outputs with more than 30 or 40 mWrms output power into a 32- or 16-Ω load, either through a dc
blocking capacitor or without a capacitor, as selected by register 74 (HPS[2:0]). These outputs include analog
volume amplifiers, except for the HPCOM/MONO pin, which can be set from 6 dB to –70 dB with 0.5-, 1-, 2- or
4-dB steps for each output using registers 64 and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). The center voltage is
0.5 VCC with zero data input.
Headphone Plug Insertion Detection
The HDTI pin detects the insertion status of headphone plug and writes the status to register 77 (HPDS), which
can be read by the I2C interface. The polarity of the status indication can be inverted by register 75 (HPDP). The
headphone and speaker amplifiers are disabled or enabled automatically by headphone plug
insertion/extractrion if register 75, HPDE = 1. They are controlled by register settings if register 75, HPDE = 0.
HPCOM/MONO is not affected by the status when register 74, CMS[0] = 1.
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Speaker Output (Class-D, PCM3793)
The SPOLP, SPOLN and SPORP, SPORN pins are stereo or mono speaker differential outputs (BTL) with a
maximum of 700 mWrms (VPA = 3.6 V, volume = 6 dB) into an 8-Ω load. The digital speaker amplifier offers
maximum battery life and minimum heat, eliminates the LC low-pass filter, and includes analog volume
amplification for each output from 6 dB to –70 dB with 0.5-, 1-, 2- or 4-dB steps, which can be set by register 66,
67 (SLV[5:0], SLR[5:0]). Spectrum spreading technology and selectable switching frequency to reduce EMI
noise is controlled by register 71 (DFQ[2:0], SPS[1:0] and SPSE). The speaker amplifiers have a thermal
shutdown circuit which detects when the device temperature reaches approximately 150°C; then the speaker
amplifier is powered down.
Analog Mixing and Bypass
Mixing amplifiers (MXL, MXR) mix gain-controlled analog inputs from the AIN pins which have bypassed ADC
and DAC and direct the mixed signal to the headphone or speaker outputs. Analog mixing is controlled by
register 87 (AD2S, AIR[1:0], AIL[1:0]), register 88 (MXR[2:0], MXL[2:0]), and register 89 (GMR[2:0], GML[2:0]).
The analog mixing functions are suitable for FM radio, headset, and another analog sources without an ADC.
Microphone Bias
The MICB pin is the microphone bias source for an external microphone and can provide 2 mA (typical) bias
current.
Automatic Level Control (ALC) for Recording
The sound for microphone recording should be expanded to a suitable level without saturation. The digitally
controlled automatic level control (ALC) provides automatic expansion for small input signals and compression
for large input signals while recording. The expansion level, compression level, attack time, and recovery time
can be selected by register 83. The register 83 description explains the details of these settings.
3-D Sound
A 3-D sound effect is provided by mixing L-channel and R-channel data with band pass filter that can be
controlled two parameters, mixing ratio and band pass filter characteristic by register 95 (3DP[3:0], 3FLO). The
3-D sound effect can be applied to the DAC digital input or ADC digital output, as selected by register 95
(SDAS).
Three-Band Tone Control
Tone control has bass, midrange, and treble controls that can be adjusted from 12 dB to –12 dB in 1-dB steps
by registers 92 to 94 (LGA[4:0], MGA[4:0] and HGA[4:0]). Register 92 (LPAE) attenuates the digital input signal
automatically to prevent clipping of the output signal at settings above 0 dB for bass control. LPAE has no effect
on midrange and treble controls.
High-Pass Filter and Notch Filter
The high-pass filter eliminates the dc offset of the ADC analog signal and can be set for a cutoff frequency of 4
Hz or 240 Hz at of 48-kHz sampling frequency by register 81 (HPF[1:0]). A register 95 (SDAS) selection applies
the filter to either the DAC digital input or the ADC digital output.
Notch filters are provided to remove noise of a particular frequency, such as CCD noise, motor noise, or other
mechanical noise in a particualr application. The PCM3793/94 has two notch filters for which the center
frequency and frequency bandwidth can be programmed by registers 96 to 104. A register 95 (SDAS) selection
applies the filter to either the DAC digital input or the ADC digital output.
Digital Monaural Mixing
Register 96 (MXEN) enables or disables the internal mixing of stereo digital data to monaural digital data.
Zero-Cross Detection
Zero-cross detection minimizes audible zipper noise while changing analog volume and digital attenuation. This
function can be applied to digital input or digital output by register 86 (ZCRS).
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Short Protection
The short-circuit protection on each headphone output prevents damage to the device while an output is shorted
to VPA, an output is shorted to PGND, or any two outputs are shorted together. When the short circuit is detected
on the outputs, the PCM3793/94 powers down the shorted amplifier at once. The short-protection status can be
monitored by reading register 77 (STHC, STHL, SCHR) through the I2C interface. Short-circuit protection
operates in any enabled headphone amplifier.
Thermal Protection
The thermal protection on the speaker amplifier prevents damage to the device when the internal die
temperature exceeds approximately 150°C. Once the die temperature exceeds the thermal set point, all analog
outputs are powered down. This status can be reset by setting register 76 (RLSR, RLSL) and can be watched
by reading register 77 (STSR, STSL) on the two-wire (I2C) interface. Thermal protection operates in any enabled
speaker amplifier.
Pop-Noise Reduction Circuit
The pop-noise reduction circuit prevents audible noise when turning the power supply on/off and powering the
device up/down in portable applications. It is recommended to establish the register settings in the sequence
that is shown in Table 3 and Table 4. No particular external parts are required, and power-supply sequencing is
not necessary.
Power Up/Down for Each Module
Using register 72 (PMXL, PMXR), register 73 (PBIS, PDAR, PDAL, PHPC, PHPR, PHPL, PSPR, PSPL), register
82 (PAIR, PAIL, PADS, PMCB, PADR, PADL), and register 90 (PCOM), unused modules can be powered down
to minimize power consumption (7 mW during playback only and 13 mW when recording only).
Digital Interface
All digital I/O pins can interface at various power supply voltages. The VIO pin can be connected to a 1.71-V to
3.6-V power supply.
Power Supply
The VCC pin and the VPA pin can be connected to 2.4 V to 3.6 V. The same voltage must be applied to both pins.
The VDD pin and the VIO pin can be connected to 1.71 V to 3.6 V. A different voltage can be applied to each of
these pins (for example, VDD = 1.8 V, VIO = 3.3 V).
DESCRIPTION OF OPERATION
System Clock Input
The PCM3793/94 can accept clocks of various frequencies without a PLL. They are used for clocking the digital
filters and automatic level control and delta-sigma modulators and are classified as common-audio and
application-specific clocks. Table 2 shows frequencies of the common-audio clock and application-specific clock.
Figure 25 shows the timing requirements for system clock inputs. The sampling rate and frequency of the
system clocks are determined by the settings of register 86 (MSR[2:0]) and register 85 (NPR[5:0]). Note that the
sampling rate of the application-specific clock has a little sampling error.
Table 2. System Clock Frequencies
CLOCK
FREQUENCIES
Common-audio clock
Application-specific clock
11.2896, 12.288, 16.9344, 18.432 MHz
12, 13, 13.5, 24, 26, 27, 19.2, 19.68, 38.4, 39.36 MHz
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tw(SCKH)
0.7 VIO
0.3 VIO
SCKI
tw(SCKL)
T0005-12
PARAMETERS
SYMBOL
tw(SCKH)
tw(SCKL)
MIN
7
UNITS
ns
System-clock pulse duration, high
System-clock pulse duration, low
7
ns
Figure 25. System Clock Timing
Power-On Reset and System Reset
The power-on-reset circuit outputs a reset signal, typically at VDD = 1.2 V, and this circuit does not depend on
the voltage of other power supplies (VCC, VPA and VIO). Internal circuits are cleared to default status, then signals
are removed from all analog and digital outputs. The PCM3793/94 does not require any power supply
sequencing. Register data must be written after turning all power supplies on.
System reset is enabled by setting register 85 (SRST), and all register are cleared automatically. All circuits are
reset to their default status at once. Note that the PCM3793/94 has audible pop noise on the analog outputs
when enabling SRST.
Power On/Off Sequence
To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when
powering up, or before turning the power supplies off when powering down. If some modules are not required for
a particular application or operation, they should be placed in the power-down state after performing the
power-on sequence. The recommended power-on and power-off sequences are shown in Table 3 and Table 4,
respectively.
Table 3. Recommended Power-On Sequence
STEP
REGISTER
SETTINGS
NOTE
1
2
–
Turn on all power supplies(1)
4027h
4127h
4227h
4327h
4427h
4527h
4620h
4BC0h
5102h
5A10h
49E0h
5601h
4803h
5811h
49FCh
Headphone amplifier L-ch volume (–6 dB)(2)
Headphone amplifier R-ch volume (–6 dB)(2)
Speaker amplifier L-ch volume (–6 dB)(2)
Speaker amplifier R-ch volume (–6 dB)(2)
Digital attenuator L-ch (–24 dB)(2)
3
4
5
6
7
Digital attenuator R-ch (–24 dB)(2)
DAC audio interface format (left-justified)(3)
8
9
Headphone detection enable and inverting polarity. Short and thermal detection enable
ADC audio interface format (left-justified)(3)
10
11
12
13
14
15
16
VCOM ramp up/down time control. PG1, PG2 gain control (0 dB)
DAC (DAL, DAR) and analog bias power up
Zero-cross detection enable
Analog mixer (MXL, MXR) power up
Analog mixer input (SW2, SW5) select
Headphone amplifier (HPL, HPR, HPC) power up
(1) Power supply sequencing is not required. It is recommended to set register data with system clock input after turning all power supplies
on.
(2) Any level is acceptable for volume or attenuation. Level should be resumed by register data recorded when system power off.
(3) Audio interface format should be set to match the DSP or decoder being used.
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Table 3. Recommended Power-On Sequence (continued)
STEP
REGISTER
SETTINGS
NOTE
17
18
19
20
21
22
23
24
4C03h
4A01h
523Fh
5711h
4F0Ch
500Ch
–
Speaker amplifier shut down release
VCOM power up
Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up
Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select
Analog input L-ch (PG3) volume (0 dB)(2)
Analog input R-ch (PG4) volume (0 dB)(2)
Any settings for other devices or wait time(4)(5)
49FFh
Speaker amplifier (SPL, SPR) power up (5)
(4) The PCM3793 requires time for VCOM to reach the common level from GND level. The delay depends on the capacitor value for VCOM
and the setting of register 90 CMT[1:0]. Wait time [s] = 4 × CVCOM× RCMT
(5) The PCM3794 does not require this setting because it has no speaker output.
Table 4. Recommended Power-Off Sequence
STEP
REGISTER
SETTINGS
NOTE
1
2
447Fh
457Fh
5132h
5811h
49FFh
5200h
5A10h
4A00h
–
DAC L-ch digital soft-mute enable(1)
DAC R-ch digital soft-mute enable(1)
ADC L-ch/R-ch digital soft-mute enable, ADC audio interface format (left-justified)(2)
3
4
Analog mixer input (SW2, SW5) Select
5
Headphone amplifier (HPL, HPR, HPC) power up (4), speaker amplifier (SPL, SPR) power up(3)(4)
Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power down
VCOM ramp up/down time control, PG1, PG2 gain control (0 dB)
VCOM power down
6
7
8
9
Wait time (100 ms)
10
11
12
13
14
15
16
17
18
5A00h
–
VCOM ramp up/down time control
Wait time (100 ms)
5A20h
–
VCOM ramp up/down time control
Wait time (4000 ms)
5A30h
49E0h
4800h
4900h
–
VCOM ramp up/down time control
Headphone amplifier (HPL, HPR, HPC) power down, speaker amplifier (SPL, SPR) power down
Analog mixer (MXL, MXR) power down
DAC (DAL, DAR) and analog bias power down
Turn off all power supplies(5)
(1) Any level is acceptable for volume or attenuation.
(2) Audio interface format should be set according to DSP or decoder.
(3) PCM3794 has no speaker amplifier.
(4) These modules must be powered up during the power-down sequence.
(5) Power supply sequencing is not required. It is recommended to turn off all power supply after register settings with system clock input.
Power-Supply Current
The current consumption of the PCM3793/94 depends on power up/down status of each circuit module. In order
to reduce the power consumption, disabling each module is recommended when it is not used in an application
or operation. Table 5 shows the current consumption in some states.
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Table 5. Power Consumption Table
OPERATION MODE
POWER SUPPLY CURRENT [mA]
PD [mW]
PD [mW]
VDD
(1.8 V)
VDD
(3.3 V)
VCC
(3.3 V)
VPA
(3.3 V)
VIO
(3.3 V)
TOTAL
(VDD = 1.8
V)
TOTAL
(VDD = 3.3 V)
All Power Down
All Active
0
0
0.007
7.5
0.002
11.6
0
0.03
67.7
0.03
80.2
2.5
5.1
0.1
PLAYBACK WITH DIGITAL INPUT
Line output and headphone output
1.18
1.81
1.18
1.18
1.18
1.18
2.51
3.84
2.51
2.52
2.52
2.52
1.79
1.79
1.8
0.54
0.54
0.75
0.54
0.54
0.54
0.09
0.09
0.09
0.09
0.09
0.09
10.1
11.2
10.8
11.1
12.5
13.4
16.3
20.7
17.0
17.3
18.6
19.6
Headphone output with sound effect
Capless headphone output
Headphone output with line input (AIN2L/AIN2R)
Headphone output with mono microphone input (AIN1L, 20 dB)
2.09
2.5
Headphone output with mono differential microphone input
(AIN1L/AIN1R, 20 dB)
2.8
Stereo speaker output
1.21
1.20
1.21
1.21
1.2
2.58
2.57
2.57
2.58
2.58
2.18
2.01
2.48
2.89
3.2
10.94
5.61
0.09
0.09
0.09
0.09
0.09
45.8
27.6
46.8
48.2
49.3
52.1
33.9
53.1
54.5
55.6
Mono speaker output
Speaker output with line input (AIN2L/AIN2R)
Speaker output with mono microphone input (AIN1L, 20 dB)
10.95
10.96
10.98
Speaker output with mono differential microphone input
(AIN1L/AIN1R, 20 dB)
PLAYBACK WITHOUT DIGITAL INPUT
Line input (AIN2L/AIN2R) to headphone output
Mono line input (AIN2L) to headphone output
Mono microphone Input (AIN1L, 20 dB) to headphone output
0
0
0
0
0
0
0
0
0.76
0.61
1.18
1.48
0.53
0.53
0.53
0.53
0
0
0
0
4.3
3.8
5.6
6.6
4.3
3.8
5.6
6.6
Mono differential microphone input (AIN1L/AIN1R, 20 dB) to
headphone output
Mono microphone input (AIN1L, 20 dB) to speaker output
RECORDING
0
0
1.57
10.92
0
41.2
41.2
Line input (AIN3L/AIN3R)
1.86
1.86
2.78
1.4
3.89
3.91
5.77
2.93
4.74
2.94
4.74
4.58
5.14
5.14
3.6
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.1
0.1
0.1
0.1
0.1
0.1
0.1
19.2
21.1
22.7
15.2
16.6
16.3
17.8
28.7
30.6
36.8
22.3
28.3
23.5
29.5
Microphone input (AIN1L/AIN1R, 20 dB)
Microphone input (AIN1L/AIN1R, 20 dB) with ALC
Mono microphone input (AIN1L, 20 dB)
Mono microphone input (AIN1L, 20 dB) with ALC
Mono differential microphone input (AIN1L/AIN1R, 20 dB)
2.2
3.6
1.4
3.96
3.96
Mono differential microphone input (AIN1L/AIN1R, 20 dB) with
ALC
2.2
Conditions: 48 kHz/256 fS, 16 bits, slave mode, zero data input, no load
Audio Serial Interface
The audio serial interface for the PCM3793/94 comprises LRCK, BCK, DIN, and DOUT. Sampling rate (fS), left
and right channel are present on LRCK. DIN receives the serial data for the DAC interpolation filter, and DOUT
transmits the serial data from the ADC decimation filter. BCK clocks the transfer of serial audio data on DIN and
DOUT in its high-to-low transition. BCK and LRCK should be synchronized with audio system clock. Ideally, it is
recommended that they be derived from it.
The PCM3793/94 requires LRCK to be synchronized with the system clock. The PCM3793/94 does not require
a specific phase relationship between LRCK and the system clock.
The PCM3793/94 has both master mode and slave mode interface formats, which can be selected by register
84, MSTR. In master mode, the PCM3793/94 generates LRCK and BCK from the system clock.
Audio Data Formats and Timing
The PCM3793/94 supports I2S, right-justified, left-justified and DSP formats. The data formats are shown in
Figure 28 and are selected using register 70 (RFM[1:0], PFM[1:0]). All formats require binary 2s-complement,
MSB-first audio data. The default format is I2S. Figure 26 shows a detailed timing diagram.
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50% of VIO
LRCK
tw(BCL)
tw(BCH)
t(LB)
50% of VIO
50% of VIO
50% of VIO
BCK
t(BL)
t(BCY)
DIN
t(DH)
t(DS)
t(CKDO)
t(LRDO)
DOUT
T0010-09
PARAMETERS
MIN
MAX UNITS
BCK pulse cycle time (I2S, left- and right-justified formats)
BCK pulse cycle time (DSP format)
BCK high-level time
1/(64 fS)(1)
1/(256 fS)(1)
t(BCY)
tw(BCH)
tw(BCL)
t(BL)
35
35
10
10
10
10
ns
ns
ns
ns
ns
ns
BCK low-level time
BCK rising edge to LRCK edge
LRCK edge to BCK rising edge
DIN set up time
t(LB)
t(DS)
t(DH)
DIN hold time
t(CKDO) DOUT delay time from BCK falling edge
15
15
10
10
ns
ns
ns
ns
t(LRDO)
DOUT delay time from LRCK falling edge
Rising time of all signals
tr
tf
Falling time of all signals
(1) fS is the sampling frequency.
Figure 26. Audio Interface Timing (Slave Mode)
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t(SCY)
50% of VIO
SCKI
LRCK (Output)
BCK (Output)
t(DL)
50% of VIO
50% of VIO
50% of VIO
tw(BCL)
tw(BCH)
t(DB)
t(DB)
t(BCY)
DIN
DOUT
t(DS)
t(DH)
T0011-04
PARAMETERS
MIN
MAX UNIT
t(SCY)
t(DL)
SCKI pulse cycle time
1/(256 fS)(1)
LRCK edge from SCKI rising edge
BCK edge from SCKI rising edge
BCK pulse cycle time
0
40
40
ns
ns
t(DB)
0
1/(64 fS)(1)
146
t(BCY)
tw(BCH) BCK high level time
ns
ns
ns
ns
tw(BCL)
t(DS)
BCK low level time
DATA setup time
DATA hold time
146
10
t(DH)
10
(1) fS is up to 48 kHz. fS is the sampling frequency.
Figure 27. Audio Interface Timing (Master Mode)
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(a) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
BCK
L-Channel
R-Channel
(= 32 f , 48 f or 64 f
)
S
S
S,
16-Bit Right-Justified
DIN/DOUT 14 15 16
1
2
3
14 15 16
1
2
3
14 15 16
LSB
MSB
LSB
1/f
MSB
(b) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
S
LRCK
BCK
L-Channel
R-Channel
(= 32 f , 48 f or 64 f )
S
S
S
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
1
2
DIN/DOUT
MSB
MSB
(c) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
L-Channel
R-Channel
BCK
(= 32 f , 48 f or 64 f
)
S
S
S,
DIN/DOUT
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
1
1
1
2
2
2
MSB
MSB
(d) Burst BCK Interface Format at Master Mode; L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
L-Channel
R-Channel
BCK
(= 32 f , 48 f or 64 f
)
S
S
S,
DIN/DOUT
1
2
3
14 15 16
1
2
3
14 15 16
LSB
MSB
LSB
MSB
(e) DSP Format
1/f
S
LRCK
BCK
(= 32 f , 48 f 64 f , 128 f or 256 f )
S, S
S
S
S
DIN/DOUT
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
T0009-07
NOTE: All audio interface formats support BCK = 64 fS in master mode (register 69, MSTR = 1). When setting the
multisampling rate, the fS of BCK is set to half the rate of the DSM operation frequency.
Figure 28. Audio Data Input and Output Formats
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THREE-WIRE INTERFACE (SPI, MODE (PIN 28) = LOW)
All write operations for the serial control port use 16-bit data words. Figure 29 shows the control data word
format. The most significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register address
for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
Figure 30 shows the functional timing diagram for writing to the serial control port. To write the data into the
mode register, the data is clocked into an internal shift register on the rising edge of the MC clock. The serial
data should change on the falling edge of MC clock and should be LOW during write mode. The rising edge of
MS should be aligned with the falling edge of the last MC clock pulse in the 16-bit frame. MC can run
continuously between transactions while MS is in the LOW state.
LSB
D0
MSB
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
Register Index (or Address)
D7
D6
D5
D4
D3
D2
D1
Register Data
R0001-01
Figure 29. Control Data Word Format for MD
(1) Single Write Operation
16 Bits
MS
MC
MD
MSB
LSB
MSB
(2) Continuous Write Operation
8 Bits x N Frames
MS
MC
MD
MSB
LSB MSB
LSB MSB
LSB
MSB
LSB
Register Index
8 Bits
Register (N) Data
Register (N+1) Data
N Frames
Register (N+2) Data
T0012-03
Figure 30. Register Write Operation
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Three-Wire Interface (SPI) Timing Requirements
Figure 31 shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
t
w(MHH)
MS
50% of V
IO
t
t
w(MCL)
(MLS)
t
t
w(MCH)
(MLH)
MC
MD
50% of V
IO
t
(MCY)
LSB
50% of V
IO
t
(MDS)
t
(MDH)
T0013-08
PARAMETERS
MIN
TYP
MAX
UNIT
t(MCY)
tw(MCL)
tw(MCH)
tw(MHH)
t(MLS)
MC pulse cycle time
MC low level time
MC high level time
MS high level time
500(1)
ns
ns
ns
ns
ns
ns
ns
ns
50
50
(1)
MS falling edge to MC rising edge
MS hold time
20
20
15
20
t(MLH)
t(MDH)
t(MDS)
MD hold time
MD setup time
(1) 3/(128 fS) s (min), where fS is sampling rate.
Figure 31. SPI Interface Timing
TWO-WIRE INTERFACE [I2C, MODE (PIN 28) = HIGH]
The PCM3793/94 supports the I2C serial bus and the data transmission protocol for the I2C standard as a slave
device. This protocol is explained in I2C specification 2.0.
In I2C mode, the control terminals are changed as follows.
TERMINAL NAME
MS/ADR
PROPERTY
Input
DESCRIPTION
I2C address
I2C data
MD/SDA
Input/output
Input
MC/SCL
I2C clock
SLAVE ADDRESS
MSB
LSB
R/W
1
0
0
0
1
1
ADR
The PCM3793/94 has its own 7-bit slave address. The first six bits (MSBs) of the slave address are factory
preset to 100011. The last bit of the address byte is the device select bit, which can be user-defined by the ADR
terminal. A maximum of two PCM3793/94s can be connected on the same bus at one time. Each PCM3793/94
responds when it receives its own slave address.
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Packet Protocol
The master device must control packet protocol, which consists of start condition, slave address with read/write
bit, data if write or acknowledgement if read, and stop condition. The PCM3793/94 supports only slave receiver
and slave transmitter.
SDA
SCL
St
1−7
8
9
1−8
9
1−8
9
Sp
Slave Address R/W
ACK
DATA
ACK
DATA
ACK
R/W: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgement of a Byte if 0
DATA: 8 Bits (Byte)
Start
Condition
Stop
Condition
Write Operation
Transmitter
Data Type
M
M
M
S
M
S
M
S
M
St
Slave Address
R/W
ACK
DATA
ACK
DATA
ACK
Sp
Read Operation
Transmitter
Data Type
M
M
M
S
S
M
S
M
M
St
Slave Address
R/W
ACK
DATA
ACK
DATA
NACK
Sp
M: Master Device
St: Start Condition
S: Slave Device
Sp: Stop Condition
T0049-03
Figure 32. Basic I2C Framework
WRITE OPERATION
A master can write any PCM3793/94 registers using single access. The master sends a PCM3793/94 slave
address with a write bit, a register address, and the data. When undefined registers are accessed, the
PCM3793/94 does not send an acknowledgement. Figure 33 shows a diagram of the write operation.
Transmitter
Data Type
M
M
M
S
M
S
M
S
M
St
Slave Address
W
ACK
Reg Address
ACK
Write Data
ACK
Sp
M: Master Device S: Slave Device
St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition
R0002-01
Figure 33. Framework for Write Operation
READ OPERATION
A master can read the PCM3793/94 register. The value of the register address is stored in an indirect index
register in advance. The master sends a PCM3793/94 slave address with a read bit after storing the register
address. Then the PCM3793/94 transfers the data which the index register points to. Figure 34 shows a diagram
of the write operation.
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Transmitter
Data Type
M
M
M
S
M
S
M
M
M
S
S
M
M
NACK
St
Slave Address
W
ACK
Reg Address
ACK Sr
Slave Address
R
ACK Read Data
Sp
M: Master Device S: Slave Device St: Start Condition
Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge
W: Write R: Read
R0002-02
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
Figure 34. Read Operation
Timing Diagram
Start
Stop
t
t
(SDA-F)
(D-HD)
t
t
t
t
(P-SU)
(BUF)
(D-SU)
(SDA-R)
SDA
t
t
t
(SP)
(SCL-R)
(RS-HD)
t
(LOW)
SCL
t
t
t
(RS-SU)
(S-HD)
(HI)
t
(SCL-F)
T0050-03
PARAMETERS
SCL clock frequency
CONDITIONS
MIN
MAX
UNIT
fSCL
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
ns
t(BUF)
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for START condition
Hold time for START condition
Data setup time
4.7
4.7
4
t(LOW)
t(HI)
t(RS-SU)
t(S-HD)
t(D-SU)
t(D-HD)
t(SCL-R)
t(SCL-R1)
4.7
4
250
0
Data hold time
900
1000
1000
Rise time of SCL signal
20 + 0.1 CB
20 + 0.1 CB
Rise time of SCL signal after a repeated START condition and
after an acknowledge bit
t(SCL-F)
t(SDA-R)
t(SDA-F)
t(P-SU)
CB
Fall time of SCL signal
Standard
Standard
Standard
Standard
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
4
1000
1000
1000
ns
ns
ns
µs
pF
ns
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Capacitive load for SDA and SCL line
Pulse duration of suppressed spike
400
25
t(SP)
Figure 35. I2C Interface Timing
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USER-PROGRAMMABLE MODE CONTROLS
Register Map
The mode control register map is shown in Table 6. Each register includes an index (or address) indicated by
the IDX[6:0] bits.
Table 6. Mode Control Register Map
IDX[6:0]
REGISTER
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
(B14–B8)
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
Register 64
Register 65
Register 66
Register 67
Register 68
Register 69
Register 70
Register 71
Register 72
Register 73
Register 74
Register 75
Register 76
Register 77
Register 79
Register 80
Register 81
Register 82
Register 83
Register 84
Register 85
Register 86
Register 87
Register 88
Register 89
Register 90
Register 92
Register 93
Register 94
Register 95
Register 96
Register 97
Register 98
Register 99
Register 100
Register 101
Register 102
Register 103
Register 104
Volume for HPA (L-ch)
Volume for HPA (R-ch)
Volume for SPA (L-ch)
Volume for SPA (R-ch)
RSV
RSV
HMUL
HMUR
SMUL
SMUR
PMUL
PMUR
DEM0
RSV
HLV5
HRV5
SLV5
SRV5
ATL5
ATR5
PFM1
RSV
HLV4
HRV4
SLV4
SRV4
ATL4
ATR4
PFM0
SPSE
RSV
HLV3
HRV3
SLV3
SRV3
ATL3
ATR3
RSV
HLV2
HRV2
SLV2
SRV2
ATL2
ATR2
RSV
HLV1
HRV1
SLV1
SRV1
ATL1
ATR1
RSV
HLV0
HRV0
SLV0
SRV0
ATL0
ATR0
OVER
DFQ0
PMXL
PSPL
PCOM
SDSL
RLSL
STSL
ALV0
ARV0
RFM0
PADL
RLV0
BIT0
RSV
RSV
DAC digital attenuation and soft mute (L-ch)
DAC digital attenuation and soft mute (R-ch)
DAC over sampling, de-emphasis, audio interface
SPA (class-D) switching frequency
Analog mixer power up/down
RSV
RSV
DEM1
RSV
SPS1
RSV
SPS0
RSV
DFQ1
PMXR
PSPR
SPKS
SDSR
RLSR
STSR
ALV1
ARV1
RFM1
PADR
RLV1
RSV
RSV
RSV
RSV
DAC, SPA and HPA power up/down
Analog output configuration select
HPA insertion detection, short/thermal protection
SPA shutdown release
PBIS
RSV
PDAR
CMS2
HPDE
RSV
PDAL
CMS1
RSV
PHPC
CMS0
SDHC
RSV
PHPR
HPS1
SDHR
RSV
PHPL
HPS0
SDHL
RSV
HPDP
RSV
RSV
Shut down status read back
HPDS
RSV
RSV
RSV
STHC
ALV4
ARV4
RMUR
PAIL
STHR
ALV3
ARV3
RSV
STHL
ALV2
ARV2
DSMC
PMCB
RCP0
MSTR
NPR2
RSV
Volume for ADC input (L-ch)
RSV
ALV5
ARV5
RMUL
PAIR
RRTC
RSV
Volume for ADC input (R-ch)
RSV
RSV
ADC high-pass filter, soft mute, audio interface
ADC, MCB, PG1, 2, 5, 6, D2S power up/down
Automatic level control for recording
Master mode
HPF1
RSV
HPF0
RSV
PADS
RCP1
RSV
RALC
RSV
RSV
RATC
RSV
RSV
System reset, sampling rate control
BCK configuration, sampling rate control, zero-cross
Analog input select (MUX1, 2, 3, 4)
Analog mixing switch (SW1, 2, 3, 4, 5, 6)
Analog to analog path (PG5, 6) gain
VCOM power up/down, ramp up/down time, boost
Bass boost gain level
SRST
MBST
AD2S
RSV
RSV
NPR5
MSR1
AIR1
MXR1
GMR1
CMT1
RSV
NPR4
MSR0
AIR0
NPR3
ATOD
RSV
NPR1
RSV
NPR0
ZCRS
AIL0
MSR2
RSV
RSV
AIL1
MXR2
GMR2
RSV
MXR0
GMR0
CMT0
LGA4
MGA4
HGA4
3FL0
RSV
MXL2
GML2
RSV
MXL1
GML1
G20R
LGA1
MGA1
HGA1
3DP1
RSV
MXL0
GML0
G20L
LGA0
MGA0
HGA0
3DP0
MXEN
F100
RSV
RSV
RSV
RSV
LPAE
RSV
RSV
LGA3
MGA3
HGA3
3DP3
RSV
LGA2
MGA2
HGA2
3DP2
RSV
Middle boost gain level
RSV
RSV
Treble boost gain level
RSV
RSV
RSV
Sound effect source select, 3D sound
2-stage notch filter, digital monaural mixing
1st stage notch filter lower coefficient (a1)
1st stage notch filter upper coefficient (a1)
1st stage notch filter lower coefficient (a2)
1st stage notch filter upper coefficient (a2)
2nd stage notch filter lower coefficient (a1)
2nd stage notch filter upper coefficient (a1)
2nd stage notch filter lower coefficient (a2)
2nd stage notch filter upper coefficient (a2)
SDAS
NEN2
F107
F115
F207
F215
S107
S115
S207
S215
3DEN
NEN1
F106
F114
F206
F214
S106
S114
S206
S214
RSV
NUP2
F105
F113
F205
F213
S105
S113
S205
S213
NUP1
F104
F103
F111
F203
F211
S103
S111
S203
S211
F102
F110
F202
F210
S102
S110
S202
S210
F101
F109
F201
F209
S101
S109
S201
S209
F112
F108
F204
F200
F212
F208
S104
S112
S204
S212
S100
S108
S200
S208
HPA: Headphone amplifier SPA: Speaker amplifier DAC: D/A converter ADC: A/D converter MCB: Microphone bias PGx: Analog input buffer D2S: Differential to
single-ended amplifier
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Register Definitions
B15
B14
IDX6
IDX6
B13
IDX5
IDX5
B12
IDX4
IDX4
B11
IDX3
IDX3
B10
IDX2
IDX2
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 64
Register 65
0
IDX1
IDX1
IDX0
IDX0
RSV
RSV
HMUL
HMUR
HLV5
HRV5
HLV4
HRV4
HLV3
HRV3
HLV2
HRV2
HLV1
HRV1
HLV0
HRV0
0
IDX[6:0]: 100 0000b (40h): Register 64
IDX[6:0]: 100 0001b (41h): Register 65
HMUL: Analog Mute Control for HPL (Line or Headphone L-Channel)
HMUR: Analog Mute Control for HPR (Line or Headphone R-Channel)
Default value: 1
HPOL/LOL and HPOR/LOR can be independently muted to zero level when HMUL and HMUR = 1. The HMUx
mute takes precedence over analog volume level settings.
HMUL, HMUR = 0
HMUL, HMUR = 1
Mute disabled
Mute enabled (default)
HLV[5:0]: Analog Volume for HPL (Headphone L-Channel)
HRV[5:0]: Analog Volume for HPR (Headphone R-Channel)
Default value: 00 0000.
HPOL/LOL and HPOR/LOR can be independently controlled from 6 dB to –70 dB, with step size depending on
the gain level. Outputs may have zipper noise while changing levels. In the PCM3793/94, the noise can be
reduced when making the change by using zero-cross detection (register 85, ZCRS).
Table 7. Headphone Gain Level Setting
HLV[5:0],
HRV[5:0]
GAIN LEVEL
SETTING
HLV[5:0],
HRV[5:0]
GAIN LEVEL
SETTING
HLV[5:0],
HRV[5:0]
GAIN LEVEL
SETTING
STEP
STEP
STEP
11 1111
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
6 dB
5.5 dB
5 dB
10 1001
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
–5 dB
–5.5 dB
–6 dB
01 0011
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
–21 dB
–22 dB
–23 dB
–24 dB
–26 dB
–28 dB
–30 dB
–32 dB
–34 dB
–36 dB
–38 dB
–40 dB
–42 dB
–46 dB
–50 dB
–54 dB
–58 dB
–62 dB
–66 dB
–70 dB
11 1110
11 1101
11 1100
11 1011
11 1010
11 1001
11 1000
11 0111
11 0110
11 0101
11 0100
11 0011
11 0010
11 0001
11 0000
10 1111
10 1110
10 1101
10 1100
10 1011
10 1010
10 1000
10 0111
10 0110
10 0101
10 0100
10 0011
10 0010
10 0001
10 0000
01 1111
01 1110
01 1101
01 1100
01 1011
01 1010
01 1001
01 1000
01 0111
01 0110
01 0101
01 0100
01 0010
01 0001
01 0000
00 1111
00 1110
00 1101
00 1100
00 1011
00 1010
00 1001
00 1000
00 0111
00 0110
00 0101
00 0100
00 0011
00 0010
00 0001
00 0000
1 dB
4.5 dB
4 dB
–6.5 dB
–7 dB
3.5 dB
3 dB
–7.5 dB
–8 dB
0.5 dB
2.5 dB
2 dB
–8.5 dB
–9 dB
2 dB
1.5 dB
1 dB
–9.5 dB
–10 dB
–10.5 dB
–11 dB
–12 dB
–13 dB
–14 dB
–15 dB
–16 dB
–17 dB
–18 dB
–19 dB
–20 dB
0.5 dB
0.5 dB
0 dB
–0.5 dB
–1 dB
–1.5 dB
–2 dB
–2.5 dB
–3 dB
–3.5 dB
–4 dB
– 4.5 dB
4 dB
1 dB
30
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B15
0
B14
IDX6
IDX6
B13
IDX5
IDX5
B12
IDX4
IDX4
B11
IDX3
IDX3
B10
IDX2
IDX2
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 66
Register 67
IDX1
IDX1
IDX0
IDX0
RSV
RSV
SMUL
SMUR
SLV5
SRV5
SLV4
SRV4
SLV3
SRV3
SLV2
SRV2
SLV1
SRV1
SLV0
SRV0
0
IDX[6:0]: 100 0010b (42h): Register 66
IDX[6:0]: 100 0011b (43h): Register 67
SMUL: Digital Soft Mute Control for SPL (Speaker Output, L-Channel)
SMUR: Digital Soft Mute Control for SPR (Speaker Output R-Channel)
Default value: 1
SPOLP/SPOLN and SPORP/SPORN can be independently muted to the zero level when HMUL and HMUR = 1.
The SMUx mute takes precedence over analog volume level settings.
SMUL, SMUR = 0
SMUL, SMUR = 1
Mute disabled
Mute enabled (default)
SLV[5:0]: Gain Setting for SPL (Speaker Output L-Channel)
SRV[5:0]: Gain Setting for SPR (Speaker Output R-Channel)
Default value: 00 0000.
SPOLP/SPOLN and SPORP/SPORN can be independently controlled from 6 dB to –70 dB, with step size
depending on the gain level. Outputs may have zipper noise while changing levels. In the PCM3793, the noise
can be reduced when making the change by using zero-cross detection (register 85, ZCRS).
Table 8. Speaker Gain Level Setting
SLV[5:0],
SRV[5:0]
GAIN LEVEL
SETTING
SLV[5:0],
SRV[5:0]
GAIN LEVEL
SETTING
SLV[5:0],
SRV[5:0]
GAIN LEVEL
SETTING
STEP
STEP
STEP
11 1111
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
6 dB
5.5 dB
5 dB
10 1001
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
–5 dB
–5.5 dB
–6 dB
01 0011
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
–21 dB
–22 dB
–23 dB
–24 dB
–26 dB
–28 dB
–30 dB
–32 dB
–34 dB
–36 dB
–38 dB
–40 dB
–42 dB
–46 dB
–50 dB
–54 dB
–58 dB
–62 dB
–66 dB
–70 dB
11 1110
11 1101
11 1100
11 1011
11 1010
11 1001
11 1000
11 0111
11 0110
11 0101
11 0100
11 0011
11 0010
11 0001
11 0000
10 1111
10 1110
10 1101
10 1100
10 1011
10 1010
10 1000
10 0111
10 0110
10 0101
10 0100
10 0011
10 0010
10 0001
10 0000
01 1111
01 1110
01 1101
01 1100
01 1011
01 1010
01 1001
01 1000
01 0111
01 0110
01 0101
01 0100
01 0010
01 0001
01 0000
00 1111
00 1110
00 1101
00 1100
00 1011
00 1010
00 1001
00 1000
00 0111
00 0110
00 0101
00 0100
00 0011
00 0010
00 0001
00 0000
1 dB
4.5 dB
4 dB
–6.5 dB
–7 dB
3.5 dB
3 dB
–7.5 dB
–8 dB
0.5 dB
2.5 dB
2 dB
–8.5 dB
–9 dB
2 dB
1.5 dB
1 dB
–9.5 dB
–10 dB
–10.5 dB
–11 dB
–12 dB
–13 dB
–14 dB
–15 dB
–16 dB
–17 dB
–18 dB
–19 dB
–20 dB
0.5 dB
0.5 dB
0 dB
–0.5 dB
–1 dB
–1.5 dB
–2 dB
–2.5 dB
–3 dB
–3.5 dB
–4 dB
– 4.5 dB
4 dB
1 dB
31
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B15
0
B14
IDX6
IDX6
B13
IDX5
IDX5
B12
IDX4
IDX4
B11
IDX3
IDX3
B10
IDX2
IDX2
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 68
Register 69
IDX1
IDX1
IDX0
IDX0
RSV
RSV
PMUL
PMUR
ATL5
ATR5
ATL4
ATR4
ATL3
ATR3
ATL2
ATR2
ATL1
ATR1
ATL0
ATR0
0
IDX[6:0]: 100 0100b (44h): Register 68
IDX[6:0]: 100 0101b (45h): Register 69
PMUL: Digital Soft Mute Control for DAL (DAC, L-Channel)
PMUR: Digital Soft Mute Control for DAR (DAC R-Channel)
Default value: 0
The digital input to the DAC can be independently muted or unmuted. The transition from the current volume
level to mute, or the return to the previous volume setting from mute, occurs at the rate of one 1-dB step for
each 8/fS time period. When PMUL and PMUR = 0, the digital data is increased from mute to the previous
attenuation level, and when PMUL and PMUR = 1, the digital data is decreased from the current attenuation
level to mute. In the PCM3793/94, audible zipper noise can be reduced by using zero-cross detection (register
85, ZCRS).
PMUL, PMUR = 0
PMUL, PMUR = 1
Mute disabled (default)
Mute enabled
ATL[5:0]: Digital Attenuation Setting for DAL (L-Channel DAC)
ATR[5:0]: Digital Attenuation Setting for DAR (R-Channel DAC)
Default value: 11 1111b
The digital inputs to the DAC can be independently attenuated. The attenuation of each digital input is controlled
in 1-dB step for every 8/fS time period. Audible zipper noise in the PCM3793/94 can be reduced by changing the
attenuation with zero-cross detection (register 85, ZCRS).
Table 9. Digital Attenuation Setting
ATL[5:0],
ATR[5:0]
ATTENUATION LEVEL
SETTING
ATL[5:0],
ATR[5:0]
ATTENUATION LEVEL
SETTING
ATL[5:0],
ATR[5:0]
ATTENUATION LEVEL
SETTING
11 1111
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
0 dB (default)
–1 dB
10 1001
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
–22 dB
–23 dB
–24 dB
–25 dB
–26 dB
–27 dB
–28 dB
–29 dB
–30 dB
–31 dB
–32 dB
–33 dB
–34 dB
–35 dB
–36 dB
–37 dB
–38 dB
–39 dB
–40 dB
–41 dB
–42 dB
–43 dB
01 0011
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
–44 dB
–45 dB
–46 dB
–47 dB
–48 dB
–49 dB
–50 dB
–51 dB
–52 dB
–53 dB
–54 dB
–55 dB
–56 dB
–57 dB
–58 dB
–59 dB
–60 dB
–61 dB
–62 dB
Mute
11 1110
11 1101
11 1100
11 1011
11 1010
11 1001
11 1000
11 0111
11 0110
11 0101
11 0100
11 0011
11 0010
11 0001
11 0000
10 1111
10 1110
10 1101
10 1100
10 1011
10 1010
10 1000
10 0111
10 0110
10 0101
10 0100
10 0011
10 0010
10 0001
10 0000
01 1111
01 1110
01 1101
01 1100
01 1011
01 1010
01 1001
01 1000
01 0111
01 0110
01 0101
01 0100
01 0010
01 0001
01 0000
00 1111
00 1110
00 1101
00 1100
00 1011
00 1010
00 1001
00 1000
00 0111
00 0110
00 0101
00 0100
00 0011
00 0010
00 0001
00 0000
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB
–13 dB
–14 dB
–15 dB
–16 dB
–17 dB
–18 dB
–19 dB
–20 dB
–21 dB
32
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 70
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
DEM1
DEM0
PFM1
PFM0
RSV
RSV
RSV
OVER
IDX[6:0]: 100 0110b (46h): Register 70
DEM[1:0]: De-Emphasis Filter Selection
Default value: 00
The digital de-emphasis filter is in front of the interpolation filter. One of three de-emphasis filters can be
selected, corresponding to sampling rate, 32 kHz, 44.1 kHz, or 48 kHz.
DEM[1:0]
De-Emphasis Filter Selection
00
01
10
11
OFF (default)
32 kHz
44.1 kHz
48 kHz
PFM[1:0]: Audio Interface Selection for DAC (Digital Input)
Default value: 00
The audio interface for the DAC digital input has I2S, right-justified, left-justified, and DSP formats.
PFM[1:0]
Audio Interface Selection for DAC Digital Input
I2S format (default)
00
01
10
11
Right-justified format
Left-justified format
DSP format
OVER: Oversampling Control for Delta-Sigma DAC
Default value: 0
This bit is used to control the oversampling rate of delta-sigma DAC. When the PCM3793/94 operates at low
sampling rates, less than 24 kHz with SCKI frequency less than 12.5 MHz, using this function with OVER = 1 is
recommended.
OVER = 0
OVER = 1
128 fS (default)
192 fS, 256 fS, 384 fS
33
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DFQ0
Register 71
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
RSV
SPSE
SPS1
SPS0
DFQ1
IDX[6:0]: 100 0111b (47h): Register 71
SPSE: Enable of Spectrum Spreading
Default value: 0
The class-D speaker amplifier output can cause RF interference due to switching noise. The PCM3793 can
reduce peak noise by the use of spectrum spreading technology when SPSE = 1.
SPSE = 0
SPSE = 1
Disable (default)
Enable
SPS[1:0]: Spectrum Spreading Efficiency
Default value: 00
The efficiency of spectrum spreading technology can be changed to low, medium, or high.
SPS[1:0]
Spectrum Spreading Efficiency
00
01
10
11
Low (default)
Medium
High
Reserved
DFQ[1:0]: Switching Frequency for Speaker Amplifier (Class-D)
Default value: 00
Switching frequency for the class-D speaker amplifier can be selected to avoid interference with other
equipment.
DFQ[1:0]
Class D Amplifier Switching Frequency
00
01
10
11
1.5 MHz (default)
2.25 MHz
2.65 MHz
3 MHz
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 72
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
RSV
RSV
RSV
RSV
PMXR
PMXL
IDX[6:0]: 100 1000b (48h) Register 72
PMXR: Power Up/Down for MXR (Mixer R-Channel)
PMXL: Power Up/Down for MXL (Mixer L-Channel)
Default value: 0
These bits are used to control power up and down for the analog mixer.
PMXL, PMXR = 0
PMXL, PMXR = 1
Power down (default)
Power up
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 73
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
PBIS
PDAR
PDAL
PHPC
PHPR
PHPL
PSPR
PSPL
IDX[6:0]: 100 1001b (49h): Register 73
PBIS: Power Up/Down Control for Bias
Default value: 0
This bit is used to control power up/down for the analog bias circuit.
PBIS = 0
PBIS = 1
Power down (default)
Power up
PDAR: Power Up/Down Control for DAR (DAC and R-Channel Digital Filter)
PDAL: Power Up/Down Control for DAL (DAC and L-Channel Digital Filter)
Default value: 0
This bit is used to control power up/down for the DAC and interpolation filter.
PDAR, PDAL = 0
PDAR, PDAL = 1
Power down (default)
Power up
PHPC: Power Up/Down Control for HPC (Headphone COM/Monaural Output)
Default value: 0
This bit is used to control power up/down for the headphone COM or monaural line amplifier.
PHPC = 0
PHPC = 1
Power down (default)
Power up
PHPR: Power Up/Down Control for HPR (Line or R-Channel Headphone Output)
PHPL: Power Up/Down Control for HPL (Line or L-Channel Headphone Output)
Default value: 0
This bit is used to control power up/down for the headphone amplifier.
PHPR, PHPL = 0
PHPR, PHPL = 1
Power down (default)
Power up
PSPR: Power Up/Down Control for SPR (R-Channel Speaker Output, PCM3793)
PSPL: Power Up/Down Control for SPL (L-Channel Speaker Output, PCM3793)
Default value: 0
This bit is used to control power up/down for the PCM3793 speaker amplifier. This bit is should be set to 0 for
the PCM3794, because it has no speaker outputs.
PSPR, PSPL = 0
PSPR, PSPL = 1
Power down (default)
Power up
35
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
PCOM
Register 74
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
CMS2
CMS1
CMS0
HPS1
HPS0
SPKS
IDX[6:0]: 100 1010b (4Ah): Register 74
CMS[2:0]: Output Selection for HPC (Headphone COM/Monaural Output)
Default value: 000
HPCOM/MONO output can be selected from several input analog sources, including inverted HPOR output,
inverted HPOL output, and monaural output.
CMS[2:0]
0 0 0
HPCOM/MONO Output Selection
Common voltage (0.5 VCC) output for capless mode (default)
Monaural output
0 0 1
0 1 0
Inverted HPOL output
1 0 0
Inverted HPOR output
Others
Reserved
HPS[1:0]: Line or Headphone Output Configuration
Default value: 00
The HPOL/LOL and HPOR/LOR output configuration can be selected as follows.
HPS[1:0]
0 0
Line or Headphone Output Configuration
Stereo output (default)
0 1
Single monaural output
Differential monaural output
Reserved
1 0
1 1
SPKS: Speaker Output Configuration
Default value: 00
The SPOLP/SPOLN and SPORP/SPORN output configuration can be selected as follows.
SPKS = 0
SPKS = 1
Stereo output (default)
Monaural output
PCOM: Power Up/Down Control for VCOM
Default value: 0
This bit is used to control power up/down for VCOM
.
PCOM = 0
PCOM = 1
Power down (default)
Power up
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 75
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
HPDP
HPDE
RSV
SDHC
SDHR
SDHL
SDSR
SDSL
IDX[6:0]: 1001011b (4Bh): Register 75
HPDP: Headphone Insertion Detection Polarity
HPDE: Enable for Headphone Insertion Detection
Default value: 0
Table 10. Headphone Insertion Detection
HPDE
HPDP
HDTI (PIN 8)
HP OUTPUT
SP OUTPUT
Up
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
Down
Up
Down
Down
Up
Up
Down
Headphone insertion detection disabled
SDHC: Short Protection Disable for HPC (Headphone COM/Monaural Output)
SDHR: Short Protection Disable for HPR (R-Channel Headphone)
SDHL: Short Protection Disable for HPL (L-Channel Headphone)
Default value: 0
Short-circuit protection can be disabled if this function is not needed in an application.
SDHC, SDHR, SDHL = 0
SDHC, SDHR, SDHL = 1
Enabled (default)
Disabled
SDSR: Thermal Protection Disable for SPR (Speaker Amplifier R-Channel)
SDSL: Thermal Protection Disable for SPL (Speaker Amplifier L-Channel)
Default value: 0
The thermal protection circuit can be disabled if this function is not needed in an application.
SDSR, SDSL = 0
SDSR, SDSL = 1
Enabled (default)
Disabled
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
RLSL
Register 76
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
RSV
RSV
RSV
RSV
RLSR
IDX[6:0]: 100 1100b (4Ch): Register 76
RLSR: Reset Thermal Protection Circuit for SPR (R-Channel Speaker Amplifier)
RLSL: Reset Thermal Protection Circuit for SPL (L-Channel Speaker Amplifier)
Default value: 0
Short-circuit protection puts the device in power-down status after it detects a temperature of approximately
150°C on the die. These bits must be set to 1 to restore power to the speaker amplifier.
RLSR, RLSL = 0
RLSR, RLSL = 1
Operation (default)
Reset (set to 0 automatically after being set to 1)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 77
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
HPDS
RSV
RSV
STHC
STHR
STHL
STSR
STSL
IDX[6:0]: 100 1101b (4Dh): Register 77
HPDS: Headphone Detection Status
Default value: 0
The HPDS bit shows the status of insert detection for the headphone. This is a read-only bit. The polarity
depends on register 75 HPDP setting.
HPDS = 0
HPDS = 1
HDTI input (when HPDP = 0) (default)
Inverted HDTI input (When HPDP = 1)
STHC: Short Protection Status for HPC (Headphone COM/Monaural Output)
STHR: Short Protection Status for HPR (R-Channel Headphone)
STHL: Short Protection Status for HPL (L-Channel Headphone)
These bits can be read through the I2C interface to determine short protection status.
STHC, STHR, STHL = 0
STHC, STHR, STHL = 1
Detect short circuit
Not detect short circuit
STSR: Thermal Protection Status for SPR (R-Channel Speaker)
STSL: Thermal Protection Status for SPL (L-Channel Speaker)
These bits can be read through the I2C interface to determine thermal protection status.
STSR, STSL = 0
STSR, STSL = 1
Detect thermal protection
Not detect thermal protection
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B15
0
B14
IDX6
IDX6
B13
IDX5
IDX5
B12
IDX4
IDX4
B11
IDX3
IDX3
B10
IDX2
IDX2
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 79
Register 80
IDX1
IDX1
IDX0
IDX0
RSV
RSV
RSV
RSV
ALV5
ARV5
ALV4
ARV4
ALV3
ARV3
ALV2
ARV2
ALV1
ARV1
ALV0
ARV0
0
IDX[6:0]: 100 1111b (4Fh): Register 79
IDX[6:0]: 101 0000b (50h): Register 80
ALV[5:0]: Gain Control for PG3 (R-Channel ADC Analog Input)
ARV[5:0]: Gain Control for PG4 (L-Channel ADC Analog Input)
Default value: 00
PG3 and PG4 can be independently controlled for ADC input from 30 dB to –12 dB in 1-dB steps. The ADC
output may have zipper noise while changing the level. In the PCM3793/94, the noise can be reduced when
making the change by using zero-cross detection (register 85, ZCRS).
Table 11. Gain Level Setting
ALV[5:0],
ARV[5:0]
GAIN LEVEL
SETTING
ALV[5:0],
ARV[5:0]
GAIN LEVEL
SETTING
10 1010
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
30 dB
29 dB
28 dB
27 dB
26 dB
25 dB
24 dB
23 dB
22 dB
21 dB
20 dB
19 dB
18 dB
17 dB
16 dB
15 dB
14 dB
13 dB
12 dB
11 dB
10 dB
9 dB
01 0100
14
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
8 dB
7 dB
10 1001
10 1000
10 0111
10 0110
10 0101
10 0100
10 0011
10 0010
10 0001
10 0000
01 1111
01 1110
01 1101
01 1100
01 1011
01 1010
01 1001
01 1000
01 0111
01 0110
01 0101
01 0011
01 0010
01 0001
01 0000
00 1111
00 1110
00 1101
00 1100
00 1011
00 1010
00 1001
00 1000
00 0111
00 0110
00 0101
00 0100
00 0011
00 0010
00 0001
00 0000
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB (default)
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
RFM0
Register 81
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
HPF1
HPF0
RMUL
RMUR
RSV
DSMC
RFM1
IDX[6:0]: 101 0001b (51h): Register 81
HPF[1:0]: High-Pass Filter Selection
Default value: 00
PCM3793/94 has digital high-pass filter to remove dc voltage at the input of the ADC. The cutoff frequency of
the high-pass filter can be selected.
HPF [1:0]
0 0
High-Pass Filter Selection
fC = 4 Hz at 48 kHz (default)
fC = 240 Hz at 48 kHz
Reserved
0 1
1 0
1 1
High-pass filter disabled
RMUL: Digital Soft Mute Control for L-Channel ADC
RMUR: Digital Soft Mute Control for R-Channel ADC
Default value: 1
The digital output of the ADC can be independently muted or unmuted. The transition from the current volume
level to mute, or the return to the previous volume setting from mute, occurs at the rate of one 1-dB step for
each 8/fS time period. When PMUL and PMUR = 0, the digital data is increased from mute to the previous
attenuation level, and when PMUL and PMUR = 1, the digital data is decreased from the current attenuation
level to mute. In the PCM3793/94, audible zipper noise can be reduced by using zero-cross detection (register
85, ZCRS).
RMUL, RMUR = 0
RMUL, RMUR = 1
Mute disabled
Mute enabled (default)
DSMC: Waiting Time for ADC Mute Off at Power Up
Default value: 0
The ADC digital output has an optional delay after power up when DSMC = 0. It is recommended to set
DSMC = 0.
DSMC = 0
DSMC = 1
10 ms at 48 kHz (default)
No delay
RFM[1:0]: Audio Interface Selection for ADC (Digital Output)
Default value: 00
The audio interface for the ADC digital input supports I2S, right-justified, left-justified, and DSP formats.
RFM [1:0]
0 0
Audio Interface Selection for ADC Digital Output
I2S format (default)
0 1
Right-justified format
1 0
Left-justified format
1 1
DSP format
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 82
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
PAIR
PAIL
PADS
PMCB
PADR
PADL
IDX[6:0]: 101 0010b (52h): Register 82
PAIR: Power Up/Down for PG2 and PG6 (Gain Amplifier for R-Channel Analog Input)
PAIL: Power Up/Down for PG1 and PG5 (Gain Amplifier for L-Channel Analog Input)
Default value: 0
This bit is used to control power up/down for PG2 and PG6 (gain amplifier for analog input).
PAIR, PAIL = 0
PAIR, PAIL = 1
Power down (default)
Power up
PADS: Power Up/Down for D2S (Differential Amplifier) of AIN1L and AIN1R
Default value: 0
This bit is used to control power up/down for D2S (differential-to-single amplifier).
PADS = 0
PADS = 1
Power down (default)
Power up
PMCB: Power Up/Down Control for Microphone Bias Source
Default value: 0
This bit is used to control power up/down for the microphone bias source.
PMCB = 0
PMCB = 1
Power down (default)
Power up
PADR: Power Up/Down Control for ADR (ADC and R-Channel Digital Filter)
PADL: Power Up/Down Control for ADL (ADC and L-Channel Digital Filter)
Default value: 0
This bit is used to control power up/down for the ADC and decimation filter.
PADR, PADL = 0
PADR, PADL = 1
Power down (default)
Power up
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
RLV0
Register 83
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RALC
RSV
RRTC
RATC
RCP1
RCP0
RLV1
IDX[6:0]: 101 0011b (53h): Register 83
RALC: Automatic Level Control (ALC) Enable for Recording
Default value: 0
Automatic level control can be enabled with some parameters for microphone input or lower analog source level.
RALC = 0
RALC = 1
Disable (default)
Enable
RRTC: ALC Recovery Time Control for Recording
Default value: 0
This bit is used to select the recovery time for the ALC. The response is shown in Figure 36.
RRTC = 0
RRTC = 1
3.4 s (default)
13.6 s
RATC: ALC Attack Time Control for Recording
Default value: 0
This bit is used to select the attack time for the ALC. The response is shown in Figure 36.
RATC = 0
RATC = 1
1 ms (default)
2 ms
Recovery
Attack
Input Data
Input Data
+FS
+FS
–FS
+FS
–FS
Output Data
Output Data
Recovery Time
Attack Time
+FS
–FS
–FS
T0166-01
Figure 36. Attack and Recovery Time Response
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RCP[1:0]: ALC Compression Level Control for Recording
Default value: 00
These bits are used to set the compression level for the ALC. The characteristic is shown in Figure 37.
RCP[1:0]
0 0
ALC Compression Level Control for Recording
–2 dB (default)
–6 dB
0 1
1 0
–12 dB
1 1
Reserved
RLV[1:0]: ALC Expansion Level Control for Recording
Default value: 00
These bits are used to set the expansion level for the ALC. The characteristic is shown in Figure 37.
RLV[1:0]
0 0
ALC Gain Level Control for Recording
0 dB (default)
6 dB
0 1
1 0
14 dB
1 1
24 dB
0 dB
Compression
–2, –6, –12 dB
Expansion
(0, 6, 12, 24 dB)
Input Amplitude
0 dB
M0057-01
Figure 37. Compression and Expansion Characteristics
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B15
0
B14
IDX6
IDX6
IDX6
B13
IDX5
IDX5
IDX5
B12
IDX4
IDX4
IDX4
B11
IDX3
IDX3
IDX3
B10
IDX2
IDX2
IDX2
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 84
Register 85
Register 86
IDX1
IDX1
IDX1
IDX0
IDX0
IDX0
RSV
RSV
RSV
MSR2
RSV
NPR5
RSV
NPR4
RSV
MSTR
NPR2
RSV
RSV
NPR1
RSV
BIT0
NPR0
ZCRS
0
SRST
MBST
NPR3
ATOD
0
MSR1 MSR0
IDX[6:0]: 101 0100b (54h): Register 84
IDX[6:0]: 101 0101b (55h): Register 85
IDX[6:0]: 101 0110b (56h): Register 86
MSTR: Master or Slave Selection for Audio Interface
Default value: 0
This bit is used to select either master or slave mode for the audio interface. In master mode, the PCM3793/94
generates LRCK and BCK from the system clock. In slave mode, it receives LRCK and BCK from another
device.
MSTR = 0
MSTR = 1
Slave interface (default)
Master interface
BIT0: Bit Length Selection for Audio Interface
Default value: 1
This bit is used to select the data bit length for DAC input.
BIT0 = 0
BIT0 = 1
Reserved
16 bits (default)
SRST: System Reset
Default value: 0
This bit is used to enable system reset. All circuits are reset by setting SRST = 1. After completing the reset
sequence, SRST is set to 0 automatically.
SRST = 0
SRST = 1
Reset disabled (default)
Reset enabled
NPR[5:0]: System Clock Rate Selection
Default value: 000000
MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70)
Default value: 000
These bits are used to select the system clock rate and the dividing rate of the input system clock. See Table 12
for the details.
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Table 12. System Clock Frequency for Common-Audio Clock
SYSTEM CLOCK
SCK (MHz)
ADC SAMPLING RATE
ADC fS (kHz)
DAC SAMPLING RATE
DAC fS (kHz)
REGISTER SETTINGS(1)
BIT CLOCK
BCK (fS)
MSR[2:0]
010
011
100
101
110
111
010
100
110
010
011
100
101
110
111
011
101
111
010
011
100
101
110
111
010
011
100
101
110
111
NPR[5:0]
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
24 (SCK/256)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
16 (SCK/384)
12 (SCK/512)
6.144
8.192
8 (SCK/768)
6 (SCK/1024)
4 (SCK/1536)
32 (SCK/256)
16 (SCK/512)
8 (SCK/1024)
48 (SCK/256)
32 (SCK/384)
24 (SCK/512)
12.288
18.432
5.6448
16 (SCK/768)
12 (SCK/1024)
8 (SCK/1536)
48 (SCK/384)
24 (SCK/768)
12 (SCK/1536)
22.05 (SCK/256)
14.7 (SCK/384)
11.025 (SCK/512)
7.35 (SCK/768)
5.5125 (SCK/1024)
3.675 (SCK/1536)
44.1 (SCK/256)
29.4 (SCK/384)
22.05 (SCK/512)
14.7 (SCK/768)
11.025 (SCK/1024)
7.35 (SCK/1536)
11.2896
(1) Other settings are reserved.
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Table 13. System Clock Frequency for Application-Specific Clock
SYSTEM CLOCK
SCK (MHz)
ADC SAMPLING RATE
ADC fS (kHz)
DAC SAMPLING RATE
DAC fS (kHz)
REGISTER SETTINGS
BIT CLOCK
BCK (fS)
MSR[2:0]
010
010
010
100
100
100
110
110
010
010
010
100
100
100
110
110
010
010
010
100
100
100
110
110
010
010
010
100
100
100
110
110
011
011
011
101
101
101
111
111
NPR[5:0]
00 0010
00 0001
10 0010
00 0010
00 0001
10 0010
00 0010
10 0010
01 0010
01 0001
11 0010
01 0010
01 0001
11 0010
01 0010
11 0010
00 0100
00 0011
10 0100
00 0100
00 0011
10 0100
00 0100
10 0100
01 0100
01 0011
11 0100
01 0100
01 0011
11 0100
01 0100
11 0100
00 0110
00 0101
10 0110
00 0110
00 0101
10 0110
00 0110
10 0110
48.214 (SCK/280)
70
76
70
70
76
70
70
70
70
76
70
70
76
70
70
70
62
68
62
62
68
62
62
62
62
68
62
62
68
62
62
62
66
72
66
66
72
66
66
66
44.407 (SCK/304)
32.142 (SCK/420)
24.107 (SCK/560)
22.203 (SCK/608)
16.071 (SCK/840)
12.053 (SCK/1120)
8.035 (SCK/1680)
48.214 (SCK/560)
44.407 (SCK/608)
32.142 (SCK/840)
24.107 (SCK/1120)
22.203 (SCK/1216)
16.071 (SCK/1680)
12.053 (SCK/2240)
8.035 (SCK/3360)
48.387 (SCK/248)
44.117 (SCK/272)
32.258 (SCK/372)
24.193 (SCK/496)
22.058 (SCK/544)
16.129 (SCK/744)
12.096 (SCK/992)
8.064 (SCK/1488)
48.387 (SCK/496)
44.117 (SCK/544)
32.258 (SCK/744)
24.193 (SCK/992)
22.058 (SCK/1088)
16.129 (SCK/1488)
12.096 (SCK/1984)
8.064 (SCK/2976)
48.484 (SCK/396)
44.444 (SCK/432)
32.323 (SCK/594)
24.242 (SCK/792)
22.222 (SCK/864)
16.161 (SCK/1188)
12.121 (SCK/1584)
8.080 (SCK/2376)
13.5
27
12
24
19.2
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Table 13. System Clock Frequency for Application-Specific Clock (continued)
SYSTEM CLOCK
SCK (MHz)
ADC SAMPLING RATE
ADC fS (kHz)
DAC SAMPLING RATE
DAC fS (kHz)
REGISTER SETTINGS
BIT CLOCK
BCK (fS)
MSR[2:0]
011
011
011
101
101
101
111
111
010
010
010
100
100
100
110
110
010
010
010
100
100
100
110
110
011
011
011
101
101
101
111
111
011
011
011
101
101
101
111
111
NPR[5:0]
01 0110
01 0101
11 0110
01 0110
01 0101
11 0110
01 0110
11 0110
00 1000
00 0111
10 1000
00 1000
00 0111
10 1000
00 1000
10 1000
01 1000
01 0111
11 1000
01 1000
01 0111
11 1000
01 1000
11 1000
00 1010
00 1001
10 1010
00 1010
00 1001
10 1010
00 1010
10 1010
01 1010
01 1001
11 1010
01 1010
01 1001
11 1010
01 1010
11 1010
48.484 (SCK/792)
66
72
66
66
72
66
66
66
68
74
68
68
74
68
68
68
68
74
68
68
74
68
68
68
68
74
68
68
74
68
68
68
68
74
68
68
74
68
68
68
44.444 (SCK/864)
32.323 (SCK/1188)
24.242 (SCK/1584)
22.222 (SCK/1728)
16.161 (SCK/2376)
12.121 (SCK/3168)
8.080 (SCK/4752)
47.794 (SCK/272)
43.918 (SCK/296)
31.862 (SCK/408)
23.897 (SCK/544)
21.959 (SCK/592)
15.931 (SCK/816)
11.948 (SCK/1088)
7.965 (SCK/1632)
47.794 (SCK/544)
43.918 (SCK/592)
31.862 (SCK/816)
23.897 (SCK/1088)
21.959 (SCK/1184)
15.931 (SCK/1632)
11.948 (SCK/2176)
7.965 (SCK/3264)
48.235 (SCK/408)
44.324 (SCK/444)
32.156 (SCK/612)
24.117 (SCK/816)
22.162 (SCK/888)
16.078 (SCK/1224)
12.058 (SCK/1632)
8.039 (SCK/2448)
48.235 (SCK/816)
44.324 (SCK/888)
32.156 (SCK/1224)
24.117 (SCK/1632)
22.162 (SCK/1776)
16.078 (SCK/2448)
12.058 (SCK/3264)
8.039 (SCK/4896)
38.4
13
26
19.68
39.36
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MBST: BCK Output Configuration in Master Mode
Default value: 0
This bit is used to control the BCK output configuration in master mode. In master mode, this bit sets the BCK
output configuration to normal mode or burst mode. In normal mode (MBST = 0), the BCK clock runs
continuously. In burst mode (MBST = 1), the BCK clock runs intermittently, and the number of clock cycles per
LRCK period is reduced to equal the number of bits of audio data being transmitted. Operating in burst mode
reduces the power consumption of VIO (I/O cell power supply). This is effective in master mode (register 69
MSTR = 1).
MBST = 0
MBST = 1
Normal output (default)
Burst output
ATOD: ADC Digital Output to DAC Digital Input (Loopback)
Default value: 0
The ADC digital output is internally connected to the DAC digital input by setting ATOD = 1. This setting can be
used to debug ADC functions or to monitor a recording.
ATOD= 0
ATOD= 1
Disabled (default)
Enabled
ZCRS: Zero-Cross for Digital Attenuation/Mute and Analog Gain Setting
Default value: 0
This bit is used to enablethe zero-cross detector, which reduces zipper noise while the digital soft mute, digital
attenuation analog gain setting, or analog volume setting is being changed. If no zero-cross data is input for a
512/fS period (10.6 ms at a 48-kHz sampling rate), then a time-out occurs and the PCM3793/94 starts changing
the attenuation, gain, or volume level. The zero-cross detector cannot be used with continuous-zero and dc
data.
ZCRS = 0
ZCRS = 1
Zero cross disabled (default)
Zero cross enabled
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 87
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AD2S
RSV
AIR1
AIR0
RSV
RSV
AIL1
AIL0
IDX[6:0]: 101 0111b (57h): Register 87
AD2S: Differential Amplifier Selector (MUX3 and MUX4)
Default value: 0
The PCM3793/94 has stereo single-input amplifiers (PG1, PG2) and a monaural differential-input amplifier (D2S)
which can be used as ADC inputs. MUX3 and MUX4 can be selected as the monaural differential input by
setting AD2S = 1.
AD2S = 0
AD2S = 1
Single-input amplifiers (default)
Differential-input amplifier
AIL[1:0]: AIN1L, AIN2L, and AIN3L Selector (MUX1)
Default value: 00
This bit is used to select one of the three analog inputs, AIN1L, AIN2L, or AIN3L.
AIL[1:0]
0 0
AIN L-channel Select
Disconnect (default)
AIN1L
0 1
1 0
AIN2L
1 1
AIN3L
AIR[1:0]: AIN1R, AIN2R, and AIN3R Selector (MUX2)
Default value: 00
This bit is used to select one of the three stereo analog inputs, AIN1R, AIN2R, or AIN3R.
AIR[1:0]
0 0
AIN R-channel Select
Disconnect (default)
AIN1R
0 1
1 0
AIN2R
1 1
AIN3R
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B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MXL0
Register 88
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
MXR2
MXR1
MXR0
RSV
MXL2
MXL1
IDX[6:0]: 101 1000b (58h): Register 88
MXR2: Mixing SW6 to MXR (R-Channel Mixing Amplifier) From L-Channel Analog Input
Default value: 0
This bit is used to connect an analog source to MXR (R-ch mixing amplifier) from the L-ch analog input.
MXR2 = 0
MXR2 = 1
Disable (default)
Enable
MXR1: Mixing SW4 to MXR (R-Channel Mixing Amplifier) From R-Channel Analog Input
Default value: 0
This bit is used to connect an analog source to MXR (R-ch mixing amplifier) from the R-ch analog input.
MXR1 = 0
MXR1 = 1
Disable (default)
Enable
MXR0: Mixing SW5 to MXR (R-Channel Mixing Amplifier) From R-Channel DAC
Default value: 0
This bit is used to connect an analog source to MXR (R-ch mixing amplifier) from the R-ch DAC.
MXR0 = 0
MXR0 = 1
Disable (default)
Enable
MXL2: Mixing SW3 to MXL (L-Channel Mixing Amplifier) From R-Channel Analog Input
Default value: 0
This bit is used to connect an analog source to MXL (L-ch mixing amplifier) from the R-ch analog input.
MXL2 = 0
MXL2 = 1
Disable (default)
Enable
MXL1: Mixing SW1 to MXL (L-Channel Mixing Amplifier) From L-Channel Analog Input
Default value: 0
This bit is used to connect an analog source to MXR (L-ch mixing amplifier) from the L-ch analog input.
MXL1 = 0
MXL1 = 1
Disable (default)
Enable
MXL0: Mixing SW2 to MXL (L-Channel Mixing Amplifier) From L-Channel DAC
Default value: 0
This bit is used to connect an analog source to MXR (L-ch mixing amplifier) from the L-ch DAC.
MXL0 = 0
MXL0 = 1
Disable (default)
Enable
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 89
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
GMR2
GMR1
GMR0
RSV
GML2
GML1
GML0
IDX[6:0]: 101 1001b (59h): Register 89
GMR[2:0]: Gain Level Control for PG6 (Gain Amplifier for Analog Input or R-Channel Bypass)
GML[2:0]: Gain Level Control for PG5 (Gain Amplifier for Analog Input or L-Channel Bypass)
Default value: 111
These bits are used for setting the gain level of the analog source to the mixing amplifier. It is recommended to
set the gain level to avoid saturation in the analog mixer.
GMR[2:0]
GML[2:0]
Gain Level Control for PG6
Gain Level Control for PG5
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
–21 dB
–18 dB
–15 dB
–12 dB
–9 dB
–6 dB
–3 dB
0 dB (default)
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
G20L
Register 90
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
CMT1
CMT0
RSV
RSV
G20R
IDX[6:0]: 1011010b (5Ah): Register 90
CMT[1:0]: VCOM Ramp Up/Down Time Control
Default value: 00
These bits are used for selecting ramp up/down time from ground level to the common-voltage level or from the
common-voltage to ground level during the power up/down sequence, in order to reduce audible pop noise.
CMT[1:0]
0 0
VCOM Ramp Up/Down Time Control
Nominal; RCMT = 60 kΩ (default)
Slow; RCMT = 120 kΩ
0 1
1 0
Fast; RCMT = 30 kΩ
1 1
Fastest; RCMT = 2.73 kΩ
G20R: 20-dB Boost for PG2 (Gain Amplifier for AIN1R, AIN2R, and AIN3R)
Default value: 0
This bit is used to boost the microphone signal when the analog input is small.
G20R = 0
G20R = 1
0 dB (default)
20-dB boost
G20L: 20-dB Boost for PG1 (Gain Amplifier for AIN1L, AIN2L, and AIN3L)
Default value: 0
This bit is used to boost the microphone signal when the analog input is small.
G20L = 0
G20L = 1
0 dB (default)
20-dB boost
52
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 92
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
LPAE
RSV
RSV
LGA4
LGA3
LGA2
LGA1
LGA0
IDX[6:0]: 101 1100b (5Ch): Register 92
LPAE: Gain Adjustment for Bass Boost Gain Control
Default value: 0
A gain setting for bass boost may cause digital data may saturation, depending on the input data level. Where
this could occur, LPAE can be used to set the same attenuation level as the bass boost gain level for the digital
input data.
LPAE = 0
LPAE = 1
Disable (default)
Enable
LGA[4:0]: Bass Boost Gain Control
Default value: 0 0000
These bits are used to set the bass boost gain level for digital data. The detailed characteristic is shown in the
Typical Performance Curves.
LGA[4:0]
0 0000
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
TONE CONTROL GAIN (BASS)
LGA[4:0]
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
TONE CONTROL GAIN (BASS)
0 dB (default)
12 dB
11 dB
10 dB
9 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB
8 dB
7 dB
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
53
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MGA0
Register 93
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
RSV
MGA4
MGA3
MGA2
MGA1
IDX[6:0]: 101 1101b (5Dh): Register 93
MGA[4:0]: Middle Boost Gain Control
Default value: 00000
These bits are used to set middle boost gain level to digital data. The detailed characteristic is shown in the
Typical Performance Curves.
MGA[4:0]
0 0000
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
TONE CONTROL GAIN (MIDRANGE)
MGA[4:0]
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
TONE CONTROL GAIN (MIDRANGE)
0 dB (default)
12 dB
11 dB
10 dB
9 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB
8 dB
7 dB
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
RSV
B5
B4
B3
B2
B1
B0
Register 94
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
HGA4
HGA3
HGA2
HGA1
HGA0
IDX[6:0]: 101 1110b (5Eh): Register 94
HGA[4:0]: Treble Boost Gain Control (fC = 5 kHz)
Default value: 00000
These bits are used to set middle boost gain level to digital data. The detailed characteristic is shown in the
Typical Performance Curves.
HGA[4:0]
0 0000
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
TONE CONTROL GAIN (TREBLE)
HGA[4:0]
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
TONE CONTROL GAIN (TREBLE)
0 dB (default)
12 dB
11 dB
10 dB
9 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB
8 dB
7 dB
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
54
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 95
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
SDAS
3DEN
RSV
3FL0
3DP3
3DP2
3DP1
3DP0
IDX[6:0]: 101 1111b (5Fh): Register 95
SDAS: Source Select for Sound Effect (Tone Control, 3-D Sound, Notch Filter, Mono Mix)
Default value: 0
The PCM3793/94 includes sound effect circuits (tone control, 3-D sound, notch filter, mono mix) which can be
used to filter either the digital input to the DAC or the digital output from the ADC. This bit selects the signal
source of the sound effect circuit.
SDAS = 0
SDAS = 1
DAC digital input (default)
ADC digital output
3DEN: 3-D Sound Effect Enable
Default value: 0
This bit is used for enabling the 3-D sound effect filter. This filter has two independently controlled parameters.
3DEN = 0
3DEN = 1
Disable (default)
Enable
3FL0: Filter Selection for 3-D Sound
Default value: 0
This bit is used for selecting fron two kinds of filter type, narrow and wide. These filters have a different 3-D
effect performance.
3FL0 = 0
3FL0 = 1
Narrow (default)
Wide
3DP[3:0]: Efficiency for 3-D Sound Effects
Default value: 0000
These bits are used for adjusting the 3-D sound efficiency. Higher percentages have greater efficiency.
3DP[3:0]
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
3D Sound Effect Efficiency
0% (default)
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
1 0 1 1
:
Reserved
:
1 1 1 1
Reserved
55
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MXEN
Register 96
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
NEN2
NEN1
NUP2
NUP1
RSV
RSV
RSV
IDX[6:0]: 110 0000b (60h): Register 96
NEN2: Second-Stage Notch Filter Enable
Default value: 0
PCM3793/94 has two notch filters with characteristics that can be set separately. This bit is used to enable the
second stage.
NEN2 = 0
NEN2 = 1
Disable (default)
Enable
NEN1: First-Stage Notch Filter Enable
Default value: 0
PCM3793/94 has two notch filters with characteristics that can be set separately. This bit is used to enable the
first stage.
NEN1 = 0
NEN1 = 1
Disable (default)
Enable
NUP2: Second-Stage Notch Filter Coefficients Update
Default value: 0
This bit is used to update the coefficients for 2nd stage notch filter. The coefficients written to registers 101, 102,
103, and 104 are updated when NUP2 = 1.
NUP2 = 0
NUP2 = 1
No Update (default)
Update (set to 0 automatically after set to 1)
NUP1: First-Stage Notch Filter Coefficients Update
Default value: 0
This bit is used to update the coefficients for the second-stage notch filter. The coefficients written to registers
97, 98, 99, and 100 are updated when NUP1 = 1.
NUP1 = 0
NUP1 = 1
No Update (default)
Update (set to 0 automatically after set to 1)
MXEN: Digital Monaural Mixing
Default value: 0
This bit is used to enable or disable monaural mixing in the section that combines L-ch data and R-ch data.
MXEN = 0
MXEN = 1
Stereo (default)
Monaural Mixing
56
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
B15
0
B14
IDX6
IDX6
IDX6
IDX6
B13
IDX5
IDX5
IDX5
IDX5
B12
IDX4
IDX4
IDX4
IDX4
B11
IDX3
IDX3
IDX3
IDX3
B10
IDX2
IDX2
IDX2
IDX2
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 97
IDX1
IDX1
IDX1
IDX1
IDX0
IDX0
IDX0
IDX0
F107
F115
F207
F215
F106
F114
F206
F214
F105
F113
F205
F213
F104
F112
F204
F212
F103
F111
F203
F211
F102
F110
F202
F210
F101
F109
F201
F209
F100
F108
F200
F208
Register 98
Register 99
Register 100
0
0
0
IDX[6:0]: 110 0001b (61h): Register 97
IDX[6:0]: 110 0010b (62h): Register 98
IDX[6:0]: 110 0011b (63h): Register 99
IDX[6:0]: 110 0100b (64h): Register 100
F[107:100]: Lower 8 Bits of Coefficient a1 for First-Stage Notch Filter
F[115:108]: Upper 8 Bits of Coefficient a1 for First-Stage Notch Filter
F[207:200]: Lower 8 Bits of Coefficient a2 for First-Stage Notch Filter
F[215:208]: Upper 8 Bits of Coefficient a2 for First-Stage Notch Filter
Default value: 0000 0000
These bits are used to change the characteristics of the first-stage notch filter. See Figure 38 for details.
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
B15
0
B14
IDX6
IDX6
IDX6
IDX6
B13
IDX5
IDX5
IDX5
IDX5
B12
IDX4
IDX4
IDX4
IDX4
B11
IDX3
IDX3
IDX3
IDX3
B10
IDX2
IDX2
IDX2
IDX2
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 101
Register 102
Register 103
Register 104
IDX1
IDX1
IDX1
IDX1
IDX0
IDX0
IDX0
IDX0
S107
S115
S207
S215
S106
S114
S206
S214
S105
S113
S205
S213
S104
S112
S204
S212
S103
S111
S203
S211
S102
S110
S202
S210
S101
S109
S201
S209
S100
S108
S200
S208
0
0
0
IDX[6:0]: 110 0101b (65h): Register 101
IDX[6:0]: 110 0110b (66h): Register 102
IDX[6:0]: 110 0111b (67h): Register 103
IDX[6:0]: 110 1000b (68h): Register 104
S[107:100]: Lower 8 bits of Coefficient a1 for Second-Stage Notch Filter
S[115:108]: Upper 8 bits of Coefficient a1 for Second-Stage Notch Filter
S[207:200]: Lower 8 bits of Coefficient a2 for Second-Stage Notch Filter
S[215:208]: Upper 8 bits of Coefficient a2 for Second-Stage Notch Filter
Default value: 00000000
These bits are used to change the characteristics of the second-stage notch filter. See Figure 38 for details.
The PCM3793/94 provides two notch filters for the digital input to the DAC or the digital output from the ADC.
The optional filter characteristics of each filter are programmable. The characteristics are given by calculating
the coefficients for three parameters, sampling frequency, center frequency, and bandwidth, as shown in
Figure 38. All coefficients must be written as 2s-complement binary data into registers 97, 98, 99, 100, 101, 102,
103, and 104.
fC
fS: Sampling Frequency [Hz]
0 dB
fC: Center Frequency [Hz]
fb
fb: Band Width [Hz]
–3 dB
2pf
æ
ç
ç
è
C ö
÷
a1 = –(1 + a2) cos
(Equation 1)
÷
fS
ø
2pf /f
æ
ç
ç
è
S ö
÷
b
1 – tan
1 + tan
÷
2
ø
(Equation 2)
a2 =
2pf /f
æ
ç
ç
è
S ö
÷
b
÷
Frequency – Hz
2
ø
M0058-01
Figure 38. Parameter Settings for Notch Filter
The coefficients are calculated using Equation 1 and Equation 2 in Figure 38. An example follows:
fS = 16 kHz, fC = 0.5 kHz, fb = 0.2 kHz
a2 = 0.924390492 → Decimal to Hex → 3B29h
a1 = –1.887413868 → Decimal to Hex → 8735h
a2: F[215:208] = 3Bh, F[207:200] = 29h
a1: F[115:108] = 87h, F[107:100] = 35h
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
CONNECTION DIAGRAM
To Regulator
(4) V
(5) V
IO
SCKI (7)
C8
DD
BCK (1)
C9
LRCK (32)
DIN (2)
(6) DGND
(20) VCC
DOUT (3)
MS/ADR (29)
MD/SDA (30)
MC/SCL (31)
MODE (28)
C10
(19) AGND
(12) VPA
C11
Low or High
(13) PGND
PCM3793/94
R3
(8) HDTI
R1 R2
MICB (21)
C12
(17) HPOL/LOL
(16) HPOR/LOR
C1
Stereo
C13
AIN1L (27)
AIN1R (26)
AIN2L (25)
C2
C3
C4
C5
C6
Headphone
Monaural
(9) HPCOM/MONO
C14
Line Output
AIN2R (24)
AIN3L (23)
R4
AIN3R (22)
VCOM (18)
(15) SPOLP
(14) SPOLN
C7
(11) SPORP
(10) SPORN
S0220-01
Figure 39. Connection Diagram
Table 14. Recommended External Parts
C1–C6
1 µF
1 µF–10 µF(1)
C12, C13
C14
10 µF–220 µF
1 µF–10 µF
2.2 kΩ
C7
C8
0.1 µF
R1, R2
R3
C9, C10
C11
1 µF–4.7 µF
4.7 µF–10 µF
33 kΩ
R4
10 kΩ
(1) 10 µF is recommended to reduce audible pop noise.
B
L
L
1
1
SPOLP/
SPORP
SPOLP/
SPORP
C
15
C
17
B
2
2
SPOLN/
SPORN
SPOLN/
SPORN
C
16
C
18
S0221-01
NOTE: C15, C16 = 1 nF C17, C18: 1 µF B1, B2: NEC/Tokin N2012ZPS121 L1, L2: 22 to 33 µH
Figure 40. Filter Consideration for Speaker Output
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SLES193C–AUGUST 2006–REVISED FEBRUARY 2007
Conventional Mode
Capless Mode
V
CC
V
CC
HP Jack
HDTI
HPOL
HPOR
HP Jack
HDTI
HPOL
HPOR
PGND
+
+
PGND
HPCOM
HPCOM
S0222-01
Figure 41. Connection for Headphone Output and Insertion Detection
HPOL
HPOL
+
+
C
L
4.7 W
C
L
16 W
16 W
16 W
16 W
HPOR
HPOR
+
+
C
R
4.7 W
C
R
C , C – mF
f
– Hz
C , C – mF
f
– Hz
L
R
C
L
R
C
10
770
10
995
47
163
77
47
212
100
45
100
220
100
220
35
S0223-01
Figure 42. High-Pass Filter for Headphone Output
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PACKAGE OPTION ADDENDUM
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17-May-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
PCM3793RHB
NRND
NRND
VQFN
VQFN
RHB
32
32
TBD
Call TI
Call TI
PCM3793RHBR
RHB
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
3793
3793
3794
PCM3793RHBRG4
PCM3793RHBT
NRND
NRND
VQFN
VQFN
RHB
RHB
32
32
TBD
Call TI
Call TI
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PCM3793RHBTG4
PCM3794RHBR
NRND
VQFN
VQFN
RHB
RHB
32
32
TBD
Call TI
Call TI
ACTIVE
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI Level-2-260C-1 YEAR
Call TI Call TI
CU NIPDAU | Call TI Level-2-260C-1 YEAR
Call TI Level-2-260C-1 YEAR
PCM3794RHBRG4
PCM3794RHBT
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHB
32
32
TBD
250
250
Green (RoHS
& no Sb/Br)
3794
3794
PCM3794RHBTG4
ACTIVE
VQFN
RHB
32
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM3793RHBR
PCM3793RHBT
PCM3794RHBR
PCM3794RHBT
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
32
32
32
32
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.5
1.5
1.5
1.5
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM3793RHBR
PCM3793RHBT
PCM3794RHBR
PCM3794RHBT
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
32
32
32
32
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
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endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
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of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
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requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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regulatory requirements in connection with such use.
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
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www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
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