PCM4202 [TI]
118dB SNR 立体声音频 ADC;
| 型号： | PCM4202 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 118dB SNR 立体声音频 ADC |
| 文件： | 总32页 (文件大小：595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS290B − JULY 2003 − SEPTEMBER 2004
High-Performance 24-Bit, 216kHz Sampling
Stereo Audio Analog-to-Digital Converter
FEATURES
APPLICATIONS
D
Two High-Performance Delta-Sigma
D
D
D
D
D
Digital Recorders and Mixing Desks
Digital Audio Effects Processors
Broadcast Studio Equipment
Surround-Sound Encoders
High-End A/V Receivers
Analog-to-Digital Converters
− 24-Bit Linear PCM or 1-Bit Direct Stream
Digital (DSD) Output Data
− Supports PCM Output Sampling Rates up
to 216kHz
− Supports 64f and 128f DSD Output Data
S
S
DESCRIPTION
Rates
D
Dynamic Performance: PCM Output
The PCM4202 is a high-performance, stereo audio
analog-to-digital (A/D) converter designed for professional
and broadcast audio applications. The PCM4202
architecture utilizes a 1-bit delta-sigma modulator per
channel, incorporating a novel density modulated dither
scheme for improved dynamic performance.
− Dynamic Range (V = −60dBFS,
IN
f
= 1kHz, A-Weighted): 118dB
IN
− THD+N (V = −0.5dB, f = 1kHz): −105dB
IN
IN
D
D
Dynamic Performance: DSD Output, 64f
− Dynamic Range (A-Weighted): 115dB
S
− THD+N (V = −0.5dB, f = 1kHz): −102dB
IN
IN
The PCM4202 supports 24-bit linear PCM output data,
with sampling frequencies up to 216kHz. The PCM4202
can also be configured to output either 64x or 128x
oversampled, 1-bit direct stream digital (DSD) data for
each channel. Support for PCM and DSD output formats
makes the PCM4202 suitable for a variety of digital audio
recording and processing applications.
Audio Serial Port
− 24-Bit Linear PCM Output Data
− Master or Slave Mode Operation
− Supports Left-Justified, Right-Justified,
2
and I SE Data Formats
D
Additional PCM Output Features:
The PCM4202 includes a flexible audio serial port inter-
face, which supports standard audio data formats. Audio
data format selection, sampling mode configuration, and
high-pass filter functions are all programmed using dedi-
cated control pins.
− Linear-Phase Digital Decimation Filter
− Digital High-Pass Filter for DC Removal
− Clipping Flag Output for Each Channel
Power Supplies: +5V Analog and +3.3V Digital
Power Dissipation:
D
D
The PCM4202 operates from a +5V analog power supply
and a +3.3V digital power supply. The digital I/O pins are
compatible with +3.3V logic families. The PCM4202 is
available in a small SSOP-28 package.
− f = 48kHz: 308mW typical
S
− f = 96kHz: 338mW typical
S
− f = 192kHz: 318mW typical
S
D
D
D
Power-Down Mode
Available in a SSOP-28 Package
Pin- and Function-Compatible with the
PCM1804
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
I S is a registered trademark of Royal Philips Electronics B.V., The Netherlands. All other trademarks are the property of their respective owners.
ꢀꢆ ꢇ ꢈꢉ ꢁ ꢊꢋ ꢇꢌ ꢈ ꢍꢊꢍ ꢎꢏ ꢐꢑ ꢒ ꢓꢔ ꢕꢎꢑꢏ ꢎꢖ ꢗꢘ ꢒ ꢒ ꢙꢏꢕ ꢔꢖ ꢑꢐ ꢚꢘꢛ ꢜꢎꢗ ꢔꢕꢎ ꢑꢏ ꢝꢔ ꢕꢙꢞ ꢀꢒ ꢑꢝꢘ ꢗꢕꢖ
ꢗ ꢑꢏ ꢐꢑꢒ ꢓ ꢕꢑ ꢖ ꢚꢙ ꢗ ꢎ ꢐꢎ ꢗ ꢔ ꢕꢎ ꢑꢏꢖ ꢚ ꢙꢒ ꢕꢟꢙ ꢕꢙ ꢒ ꢓꢖ ꢑꢐ ꢊꢙꢠ ꢔꢖ ꢋꢏꢖ ꢕꢒ ꢘꢓ ꢙꢏꢕ ꢖ ꢖꢕ ꢔꢏꢝ ꢔꢒ ꢝ ꢡ ꢔꢒ ꢒ ꢔ ꢏꢕꢢꢞ
ꢀꢒ ꢑ ꢝꢘꢗ ꢕ ꢎꢑ ꢏ ꢚꢒ ꢑ ꢗ ꢙ ꢖ ꢖ ꢎꢏ ꢣ ꢝꢑ ꢙ ꢖ ꢏꢑꢕ ꢏꢙ ꢗꢙ ꢖꢖ ꢔꢒ ꢎꢜ ꢢ ꢎꢏꢗ ꢜꢘꢝ ꢙ ꢕꢙ ꢖꢕꢎ ꢏꢣ ꢑꢐ ꢔꢜ ꢜ ꢚꢔ ꢒ ꢔꢓ ꢙꢕꢙ ꢒ ꢖꢞ
Copyright 2003−2004, Texas Instruments Incorporated
www.ti.com
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SBAS290B − JULY 2003 − SEPTEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
PCM4202
+6.0
UNIT
V
V
V
V
V
CC
Supply voltage
+3.6
DD
Ground voltage differences
Digital input voltage
(any AGND to DGND)
0.1
FMT0, FMT1, S/M, FS0, FS1, FS2, SCKI,
RST, HPFD, BCK, LRCK
−0.3 to (V
+ 0.3)
V
DD
Analog input voltage
V L+, V L−, V R+, V R−
IN IN IN IN
−0.3 to (V
+ 0.3)
V
V
CC
Input current (any pin except supplies)
Operating temperature range
10mA
−10 to +70
°C
°C
Storage temperature range, T
STG
−65 to +150
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this
datasheet.
PIN ASSIGNMENT
VREF
AGNDL
VCOM
L
1
2
3
4
5
6
7
8
9
28 VREF
R
27 AGNDR
26
25
L
VCOM
R
VINL+
V
INR+
−
−
24 VINR
VINL
FMT0
FMT1
S/M
23 AGND
22 VCC
PCM4202
21
20
CLIPL
CLIPR
FS0
FS1 10
19 RST
11
12
13
18
17
16
FS2
HPFD
DGND
SCKI
LRCK or DSDBCK
BCK or DSDL
VDD 14
15 DATA or DSDR
2
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SBAS290B − JULY 2003 − SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME
PIN NO.
I/O
DESCRIPTION
1
2
3
V
L
Output
Ground
Output
Left Channel Voltage Reference
Left Channel Reference Ground
REF
AGNDL
V
COM
L
Left Channel DC Common-mode Voltage, +2.5V Typical
Left Channel Non-inverting Analog Input
Left Channel Inverting Analog Input
Audio Data Format Selection
4
V
L+
L−
Input
Input
IN
5
V
IN
6
FMT0
FMT1
S/M
Input
7
Input
Audio Data Format Selection
8
Input
Audio Serial Port Slave/Master Mode Selection (0 = Master, 1 = Slave)
Sampling Mode Selection
9
FS0
Input
10
11
12
13
14
15
FS1
Input
Sampling Mode Selection
FS2
Input
Sampling Mode Selection
HPFD
DGND
Input
High-pass Filter Disable (Active High)
Digital Ground
Ground
Power
Output
V
DD
Digital Power Supply, +3.3V
DATA
or DSDR
Audio Serial Port Left and Right Channel PCM Data
or Right Channel DSD Data
16
17
BCK
or DSDL
I/O
I/O
Audio Serial Port Bit (or Data) Clock
or Left Channel DSD Data Output
LRCK
or DSDBCK
Audio Serial Port Left/Right (or Word) Clock
or DSD Data Clock Output
18
19
20
21
22
23
24
25
26
27
28
SCKI
RST
Input
Input
System Clock
Reset/Power-down (Active Low with internal pull-up)
Right Channel Clipping Flag (Active High)
Left Channel Clipping Flag (Active High)
Analog Power Supply, +5V
CLIPR
CLIPL
Output
Output
Power
Ground
Input
V
CC
AGND
Analog Ground
V
R−
R+
Right Channel Inverting Analog Input
Right Channel Non-inverting Analog Input
Right Channel DC Common-mode Voltage, +2.5V Typical
Right Channel Reference Ground
Right Channel Voltage Reference
IN
V
IN
Input
V
R
Output
Ground
Output
COM
AGNDR
V R
REF
3
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SBAS290B − JULY 2003 − SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
All parameters are specified at T = +25°C with V
= +5V, V
= +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise
A
CC DD
noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.
S
S
PCM4202
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
RESOLUTION
24
Bits
AUDIO DATA FORMAT
Linear PCM interface formats
Linear PCM word length
Direct Stream Digital (DSD) output
DIGITAL CHARACTERISTICS
Input logic level
2
Two’s complement, MSB first data
I S, Left or Right Justified
24
1
Bits
Bit
V
0.7 x V
0
V
DD
V
IH
DD
V
0.3 x V
V
IL
DD
Output logic level
Input current
V
I
= −2mA
= +2mA
OL
0.8 x V
V
OH
OH
DD
V
I
0.2 x V
+10
−10
+25
−25
54
V
OL
DD
I
V
= V
µA
IH
IN
DD
I
V
= 0V
µA
IL
IN
(1)
Input current
I
V
= V
µA
IH
IN
DD
I
V
= 0V
µA
IL
IN
Single rate
Dual rate
Quad rate
8
kHz
kHz
kHz
%
(2)
54
108
216
55
Sampling frequency
f
S
108
45
System clock duty cycle
50
Single rate, SCKI = 256f
Single rate, SCKI = 384f
Single rate, SCKI = 512f
Single rate, SCKI = 768f
2.048
3.072
13.824
20.736
27.648
38.4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
S
S
S
S
4.096
6.144
(2)
System clock frequency
Dual rate, SCKI = 256f
Dual rate, SCKI = 384f
13.824
20.736
13.824
20.736
27.648
38.4
S
S
Quad rate, SCKI = 128f
27.648
38.4
S
S
Quad rate, SCKI = 192f
ANALOG OUTPUTS
Input voltage, full-scale
Input impedance
Differential input
6.0
3
V
PP
kΩ
Common-mode rejection
DC PERFORMANCE
Output offset error
85
dB
HPFD = 1
4
4
3
% of FSR
% of FSR
% of FSR
Gain error
Gain mismatch channel-to-channel
(1)
(2)
(3)
Applies to the RST input, pin 19.
Single, Dual, and Quad Rate sampling modes are described within this data sheet.
Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. The
measurementbandwidth is limited by using the Audio Precision 22Hz high-pass filter in combination with the Audio Precision 20kHz, f /2, or
S
a user-defined 40kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination
with the previously mentioned filters.
4
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SBAS290B − JULY 2003 − SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All parameters are specified at T = +25°C with V
= +5V, V = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise
DD
A
CC
noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.
S
S
PCM4202
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
(3)
DYNAMIC PERFORMANCE
f
= 48kHz, Single Rate
BW = 20Hz to 20kHz
S
Total harmonic distortion + noise
Dynamic range
THD+N
THD+N
THD+N
V
= −0.5dBFS, f = 1kHz
IN
−105
118
−95
dB
dB
dB
dB
IN
V
V
= −60dBFS, f = 1kHz, A-Weighted
IN
112
100
IN
Dynamic range, no weighting
Channel separation
V
= −60dBFS, f = 1kHz
IN
116
IN
120
f
= 96kHz, Dual Rate
BW = 20Hz to 40kHz
= −0.5dBFS, f = 1kHz
S
Total harmonic distortion + noise
Dynamic range
V
−105
118
dB
dB
dB
dB
IN
IN
= −60dBFS, f = 1kHz, A-Weighted
IN
IN
= −60dBFS, f = 1kHz
Dynamic range, no weighting
Channel separation
V
112
IN
IN
120
f
= 192kHz, Quad Rate
BW = 20Hz to 40kHz
= −0.5dBFS, f = 1kHz
S
Total harmonic distortion + noise
Dynamic range
V
−103
117
dB
dB
dB
dB
IN
IN
V
= 0V
, A-Weighted
IN
RMS
= 0V
Dynamic range, no weighting
Channel separation
V
108
120
IN
RMS
DSD Output, 64f Rate
S
DSDBCK = 2.8224MHz
= −0.5dBFS, f = 1kHz
Total harmonic distortion + noise
Dynamic range
THD+N
THD+N
V
−102
115
dB
dB
dB
IN
IN
V
V
= −60dBFS, f = 1kHz, A-Weighted
IN
IN
Channel separation
120
DSD Output, 128f Rate
S
DSDBCK = 5.6448MHz
Total harmonic distortion + noise
Dynamic range
V
= −0.5dBFS, f = 1kHz
IN
−105
118
dB
dB
dB
IN
= −60dBFS, f = 1kHz, A-Weighted
IN
IN
Channel separation
120
(1)
(2)
(3)
Applies to the RST input, pin 19.
Single, Dual, and Quad Rate sampling modes are described within this data sheet.
Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. The
measurementbandwidth is limited by using the Audio Precision 22Hz high-pass filter in combination with the Audio Precision 20kHz, f /2, or
S
a user-defined 40kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination
with the previously mentioned filters.
5
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SBAS290B − JULY 2003 − SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All parameters are specified at T = +25°C with V
= +5V, V = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise
DD
A
CC
noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.
S
S
PCM4202
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
DIGITAL DECIMATION FILTER
Passband edge
Single and Dual Rate
Single and Dual Rate
Single and Dual Rate
Single and Dual Rate
Single and Dual Rate
Quad Rate
0.453f
Hz
dB
Hz
dB
sec
Hz
Hz
dB
Hz
dB
sec
S
Passband ripple
0.005
Passband edge
0.547f
S
Stop band attenuation
Group delay
−100
37/f
S
Passband edge (−0.005dB)
−3dB cutoff frequency
Passband ripple
0.375f
S
Quad Rate
0.490f
S
Quad Rate
0.005
Passband edge
Quad Rate
0.770f
S
Stop band attenuation
Group delay
Quad Rate
−135
Quad Rate
9.5/f
S
DIGITAL HIGH PASS FILTER
Frequency response (−3dB)
f /48000
S
Hz
POWER SUPPLY
Voltage range
V
V
+4.75
+3.0
+5.0
+3.3
+5.25
+3.6
VDC
VDC
CC
DD
Operating supply current
V
f
= +5V, V
= +3.3V
= 48kHz, Single Rate
CC
DD
55
55
55
65
65
65
mA
mA
mA
S
f
= 96kHz, Dual Rate
S
f
= 192kHz, Quad Rate
S
I
V
= +5V, V
= +3.3V
= 48kHz, Single Rate
DD
CC DD
f
10
19
13
12
25
15
mA
mA
mA
S
f
= 96kHz, Dual Rate
S
f
= 192kHz, Quad Rate
S
Power-down mode current
Total power dissipation
V
= +5V, V = +3.3V, RST = 0
DD
CC
I
I
Clocks applied
Clocks applied
10
2
mA
mA
CC
DD
V
= +5V, V
= +3.3V
= 48kHz, Single Rate
CC
DD
f
308
338
318
365
408
375
mW
mW
mW
S
f
= 96kHz, Dual Rate
S
f
= 192kHz, Quad Rate
S
(1)
(2)
(3)
Applies to the RST input, pin 19.
Single, Dual, and Quad Rate sampling modes are described within this data sheet.
Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. The
measurementbandwidth is limited by using the Audio Precision 22Hz high-pass filter in combination with the Audio Precision 20kHz, f /2, or
S
a user-defined 40kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination
with the previously mentioned filters.
6
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TYPICAL CHARACTERISTICS
At T = +25°C with V
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
CC
OVERALL CHARACTERISTICS
SINGLE RATE FILTER
STOP BAND ATTENUATION CHARACTERISTICS
SINGLE RATE FILTER
50
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
fS = 48 kHz
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
fS = 48 kHz
0
−
50
−
−
−
100
150
200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.5
Normalized Frequency (fS)
0
1
0.75
0.25
Normalized Frequency (fS)
TRANSIENT BAND CHARACTERISTICS
SINGLE RATE FILTER
PASSBAND RIPPLE CHARACTERISTICS
SINGLE RATE FILTER
0
0.02
fS = 48kHz
fS = 48kHz
−
1
2
3
4
5
6
7
8
9
0
0.02
0.04
0.06
0.08
−
−
−
−
−
−
−
−
−
−
−
−
−
10
−
0.1
0.45
0.47
0.49
0.51
0.53
0.55
0
0.2
0.4
0.6
0.1
0.3
0.5
Normalized Frequency (fS)
Normalized Frequency (fS)
OVERALL CHARACTERISTICS
DUAL RATE FILTER
STOP BAND ATTENUATION CHARACTERISTICS
DUAL RATE FILTER
50
0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
fS = 96kHz
−
−
−
−
−
−
−
−
−
fS = 96kHz
−
50
−
100
150
200
−
−
−
−
−
−
−
−
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Normalized Frequency (fS)
0.5
Normalized Frequency (fS)
0
1
0.75
0.25
7
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C with V
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
CC
TRANSIENT BAND CHARACTERISTICS
DUAL RATE FILTER
PASSBAND RIPPLE CHARACTERISTICS
DUAL RATE FILTER
0
1
2
3
4
5
6
7
8
9
0.02
0
fS = 96kHz
fS = 96kHz
−
−
−
−
−
−
−
−
−
−
−
−
−
0.02
0.04
0.06
0.08
−
10
−
0.1
0.45
0.47
0.49
0.51
0.53
0.55
0
0.2
0.4
0.6
0.1
0.3
0.5
Normalized Frequency (fS)
Normalized Frequency (fS)
OVERALL CHARACTERISTICS
QUAD RATE FILTER
STOP BAND ATTENUATION CHARACTERISTICS
QUAD RATE FILTER
50
0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
fS = 192kHz
−
−
−
−
−
−
−
−
−
fS = 192kHz
−
50
−
−
−
100
150
200
−
−
−
−
−
−
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Normalized Frequency (fS)
1
0.5
Normalized Frequency (fS)
0
1
0.75
0.25
TRANSIENT BAND CHARACTERISTICS
QUAD RATE FILTER
PASSBAND RIPPLE CHARACTERISTICS
QUAD RATE FILTER
0
0.02
0
fS = 192kHz
fS = 192kHz
−
1
2
3
4
5
6
7
8
9
−
−
3.90dB at 0.5fS
−
−
−
−
−
−
−
−
0.02
0.04
0.06
0.08
−
−
−
−
10
−
0.1
0
0.2
0.4
0.6
0.45
0.47
0.49
0.51
0.53
0.55
0.1
0.3
0.5
Normalized Frequency (fS)
Normalized Frequency (fS)
8
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C with V
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
CC
HIGH PASS FILTER
HIGH PASS FILTER
PASSBAND CHARACTERISTICS
STOP BAND CHARACTERISTICS
5
0.02
0
−
−
−
−
20
40
60
80
−
0.02
0.04
0.06
0.08
−
−
−
−
−
0.1
100
0
20
20
0.1
0.2
0.3
0.4
10k 20k
10k 20k
0
0.5
1
1.5
2
2.5
3
3.5
4
Normalized Frequency (fS/1000)
Normalized Frequency (fS/1000)
FFT PLOT
FFT PLOT
−
(fS = 48kHz, fIN = 997Hz at 60dB)
−
(fS = 48kHz, fIN = 997Hz at 20dB)
0
0
−
20
40
60
80
−
20
−
−
−
−
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
100
120
140
160
180
100
120
140
160
180
100
1k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
FFT PLOT
FFT PLOT
(fS = 48kHz, No Input [Idle])
−
(fS = 96kHz, fIN = 997Hz at 20dB)
0
0
−
−
−
−
20
40
60
80
−
−
−
−
20
40
60
80
−
−
−
−
−
100
120
140
160
180
−
−
−
−
−
100
120
140
160
180
100
1k
20
100
1k
10k
40k
Frequency (Hz)
Frequency (Hz)
9
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C with V
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
CC
FFT PLOT
(fS = 96kHz, fIN = 997Hz at 60dB)
FFT PLOT
(fS = 96kHz, No Input [Idle])
−
0
0
20
40
60
80
−
−
−
−
−
−
−
−
20
40
60
80
−
−
−
−
−
−
−
−
−
−
100
120
140
160
180
100
120
140
160
180
20
20
20
100
1k
10k
40k
20
100
1k
10k
40k
Frequency (Hz)
Frequency (Hz)
FFT PLOT
FFT PLOT
−
−
(fS = 192kHz, fIN = 997Hz at 60dB)
(fS = 192kHz, fIN = 997Hz at 20dB)
0
0
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
−
100
120
140
160
180
100
120
140
160
180
100
1k
10k
100k
20
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
THD+N vs AMPLITUDE
(fS = 48kHz, fIN = 1kHz, BW = 10Hz to 20kHz)
FFT PLOT
(fS = 192kHz, No Input [Idle])
−
−
−
−
−
90
92
94
96
98
0
−
−
−
−
20
40
60
80
−
100
102
104
106
108
110
112
114
116
118
120
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
120
140
160
180
−
−
−
−
−
−
−
20
140
120
100
80
60
40
0
100
1k
10k
100k
Input Amplitude (dB)
Frequency (Hz)
10
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C with V
CC
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
THD+N vs FREQUENCY
−
(fS = 48kHz, Input Amplitude = 0.5dB,
THD+N vs AMPLITUDE
BW = 10Hz to 20kHz)
(fS = 96kHz, fIN = 1kHz, BW = 10Hz to 40kHz)
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
90
92
94
96
98
−
−
−
−
−
90
92
94
96
98
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
20
100
1k
10k 20k
−
−
−
−
−
−
−
20
140
120
100
80
60
40
0
Input Frequency (Hz)
Input Amplitude (dB)
THD+N vs FREQUENCY
THD+N vs AMPLITUDE
(fS = 192kHz, fIN = 1kHz, BW = 10Hz to 40kHz)
−
(fS = 96kHz, Input Amplitude = 0.5dB,
BW = 10Hz to 40kHz)
−
−
−
−
−
90
92
94
96
98
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
90
92
94
96
98
−
−
−
−
−
−
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
20
140
120
100
80
60
40
0
20
100
1k
10k
40k
Input Amplitude (dB)
Input Frequency (Hz)
THD+N vs FREQUENCY
−
(fS = 192kHz, Input Amplitude = 0.5dB,
BW = 10Hz to 40kHz)
−
−
−
−
−
90
92
94
96
98
−
−
−
−
−
−
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
20
100
1k
10k
80k
Input Frequency (Hz)
11
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PRODUCT OVERVIEW
The PCM4202 is a high-performance, stereo audio
analog-to-digital (A/D) converter designed for use in
professional and broadcast audio applications. The
PCM4202 features 24-bit linear PCM or 1-bit Direct
Stream Digital (DSD) data output capability for both
channels. Sampling rates up to 216kHz are supported for
PCM output formats, while 64x or 128x oversampled 1-bit
data is supported for DSD output mode. Native support for
both PCM and DSD data formats makes the PCM4202
ideal for use in a wide variety of audio recording and
processing applications.
modulators, in addition to generating DC common-mode
bias voltage outputs for use with external input circuitry.
Linear phase digital decimation filtering is provided for the
24-bit PCM data outputs, with a minimum stop band
attenuation of −100dB for all sampling modes.
The PCM output mode features clipping flag outputs for
each channel, as well as a digital high-pass filter for DC
removal. The PCM4202 may be configured using
dedicated input pins for sampling mode and audio data
format selection, high-pass filter enable/disable, and
reset/power-down operation.
The PCM4202 features 1-bit delta-sigma modulators
employing density modulated dither for improved dynamic
performance. Differential voltage inputs are utilized for the
modulators, providing excellent common-mode rejection.
On-chip voltage references are provided for the
A +5V power supply is required for the analog section of
the device, while a +3.3V power supply is required for the
digital circuitry. Figure 1 shows the functional block
diagram for the PCM4202.
VINR+
LRCK
or DSDBCK
Delta−Sigma
Modulator
Decimation
Filter
HPF
−
VINR
BCK
or DSDL
V
COMR
AGNDR
REFR
DATA
or DSDR
Voltage
Reference
V
Audio
Serial
Port
VREF
AGNDL
COML
L
Voltage
Reference
CLIPR
CLIPL
S/M
V
FMT0
FMT1
−
VIN
L
Delta−Sigma
Modulator
Decimation
Filter
HPF
V
INL+
HPFD
FS0
Reset
Logic
Clock
Control
Power
FS1
FS2
SCKI
RST
VCC AGND
VDD DGND
Figure 1. PCM4202 Functional Block Diagram
12
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Refer to the Applications Information section of this
datasheet for the recommended voltage reference pin
connections.
ANALOG INPUTS
The PCM4202 includes two channels of A/D conversion,
each with its own pair of differential voltage input pins. The
VINL+ (pin 4) and VINL− (pin 5) inputs correspond to Left
channel input, while VINR+ (pin 25) and VINR− (pin 24)
correspond to the Right channel input. The average input
impedance of each input pin is 3kΩ.
Each analog input pair accepts a full-scale input voltage of
approximately 6.0VPP differential, which corresponds to a
2.12VRMS or +8.75dBu input swing. The analog input
should not swing below analog ground or above the VCC
power supply by more than 300mV. Refer to the
Applications Information section of this datasheet for an
example input buffer circuit.
The PCM4202 analog inputs are internally biased to
approximately VCC/2. This bias voltage is referred to as the
common mode voltage, and is output at VCOML (pin 3) and
VCOMR (pin 26), corresponding to the Left and Right
channels, respectively. These outputs provide a level
shifting voltage for biasing external input buffer circuitry.
Although the VCOML and VCOMR outputs are internally
buffered, the output current is limited to a few hundred µA.
It is recommended to connect these pins to external nodes
with greater than 1MΩ impedance, or to buffer the outputs
with a voltage follower circuit when driving multiple
external or low impedance nodes.
Refer to the Applications Information section of this
datasheet for an example input buffer circuit that utilizes
the common-mode bias voltage outputs.
VOLTAGE REFERENCES AND COMMON MODE
BIAS VOLTAGE OUTPUTS
The PCM4202 includes two on-chip voltage references,
one each for the Left and Right channels. The VREFL (pin
1) and VREFR (pin 28) outputs correspond to high
reference outputs for Left and Right channels,
respectively. De-coupling capacitors are connected
between each of these pins and the corresponding
reference ground pin, either AGNDL (pin 2) for the VREFL
output or AGNDR (pin 27) for the VREFR output. It is
recommended to have at least a 0.1µF X7R ceramic chip
capacitor connected in parallel with a 33µF low ESR
tantalum chip capacitor for de-coupling purposes. The
SYSTEM CLOCK INPUT
The PCM4202 requires an external system clock, from
which the modulator oversampling and digital sub-system
clocks are derived. The system clock is applied at the
SCKI input (pin 18). The frequency of the system clock is
dependent upon the desired PCM output sampling
frequency or DSD data rate, along with the sampling mode
selection. Table 1 shows the corresponding system clock
frequencies for common output sampling and data rates,
along with the corresponding sampling modes. Timing
requirements for the system clock are shown in Figure 2.
V
REFL and VREFR outputs should not be utilized to bias
external circuitry, because they are not buffered. Use the
COML (pin 3) and VCOMR (pin 26) outputs to bias external
circuitry, as described in the following paragraphs.
V
Table 1. System Clock Frequencies for Common Output Sampling and Data Rates
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING FREQUENCY, f
(kHz)
S
128f
192f
256f
384f
512f
768f
S
SAMPLING MODE
Single Rate
Single Rate
Single Rate
Dual Rate
S
S
S
S
S
32
44.1
48
n/a
n/a
n/a
n/a
8.192
11.2896
12.288
22.5792
24.576
n/a
12.288
16.9344
18.432
33.8688
36.864
n/a
16.384
22.5792
24.576
n/a
24.576
33.8688
36.864
n/a
n/a
n/a
88.2
96
n/a
n/a
Dual Rate
n/a
n/a
n/a
n/a
Quad Rate
176.4
192
22.5792
24.576
n/a
33.8688
36.864
n/a
n/a
n/a
Quad Rate
n/a
n/a
n/a
n/a
DSD Output
DSD Output
128f Data (Single Rate)
11.2896
11.2896
16.9344
16.9344
22.5792
n/a
33.8688
n/a
S
64f Data (Dual Rate)
n/a
n/a
S
13
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t
SCKIH
SCKI
t
t
SCKI
SCKIL
DESCRIPTION
System Clock Period
PARAMETER
tSCKI
MIN
26
MAX
UNITS
ns
tSCKIH
System Clock High Pulse Time
System Clock Low Pulse Time
12
ns
tSCKIL
12
ns
Figure 2. System Clock Timing Requirements
Table 3, and Table 4 indicate the sampling mode
selections for PCM Master and Slave mode operation, as
well as the DSD Output mode.
SAMPLING MODES
The PCM4202 may be operated in one of three PCM
sampling modes, or at one of two DSD output data rates.
The PCM sampling modes are referred to as Single Rate,
Dual Rate, and Quad Rate.
Table 2. Sampling Mode Selection for PCM
Master Mode Operation
Single Rate mode is utilized for sampling rates up to
54kHz. The delta-sigma modulator oversamples the
analog input signal by a rate equal to 128 times the desired
output sampling rate.
SAMPLING MODE WITH
SYSTEM CLOCK RATE
FS2
0
FS1
0
FS0
0
Single Rate with f
Single Rate with f
Single Rate with f
Single Rate with f
= 768f
= 512f
= 384f
= 256f
SCKI
SCKI
SCKI
SCKI
SCKI
SCKI
S
S
S
S
0
0
1
Dual Rate mode is utilized for sampling rates higher than
54kHz and up to 108kHz. The delta-sigma modulator
oversamples the analog input signal by a rate equal to 64
times the desired output sampling rate.
0
1
0
0
1
1
1
0
0
Dual Rate with f
Dual Rate with f
= 384f
= 256f
S
1
0
1
S
Quad Rate mode is utilized for sampling frequencies
higher than 108kHz and up to 216kHz. The delta-sigma
modulator oversamples the analog input signal by a rate
equal to 32 times the desired output sampling rate.
1
1
0
Quad Rate with f
= 192f
SCKI
SCKI
S
S
1
1
1
Quad Rate with f
= 128f
For DSD output data, the user may select either 64fS or
128fS oversampled data rates, where fS is the base
sampling rate, which is 44.1kHz for Super Audio CD
(SACD) applications. The 64fS data rate is analogous to
the Dual Rate PCM sampling mode, where the analog
input signal is oversampled by a rate equal to 64 times the
base sampling rate. The 128fS data rate corresponds to
the Single Rate PCM sampling mode, where the analog
input signal is oversampled by a rate equal to 128 times the
base sampling rate.
Table 3. Sampling Mode Selection for PCM Slave
Mode Operation
FS2
0
FS1
0
FS0
0
SAMPLING MODE
Single Rate with Clock Auto-Detection
Dual Rate with Clock Auto-Detection
Quad Rate with Clock Auto-Detection
Reserved
0
0
1
0
1
0
0
1
1
1
0
0
Reserved
1
0
1
Reserved
Table 1 indicates the sampling mode utilized for common
system clock and sampling rate combinations. The FS0
(pin 9), FS1 (pin 10), and FS2 (pin 11) inputs are utilized
to select the sampling mode for the PCM4202. If the state
of the sampling mode pins is changed any time after
power-up reset initialization, the user should issue an
external forced reset to re-initialize the PCM4202. Table 2,
1
1
0
Reserved
1
1
1
Reserved
14
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In Slave mode, the PCM bit and left/right clocks (BCK and
LRCK) are configured as input pins. DSD data formats are
not supported in Slave mode. Slave mode supports
commonly used PCM audio data formats, including Left
Justified, Right Justified, and Philips I2S.
Table 4. Sampling Mode Selection for DSD
Output Mode Operation
FS2 FS1 FS0
SAMPLING MODE
128f DSD Output Rate with f
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
= 768f
= 512f
= 384f
= 256f
S
SCKI
SCKI
SCKI
SCKI
SCKI
SCKI
S
S
S
S
128f DSD Output Rate with f
S
In Master mode, the PCM bit and left/right clocks (BCK and
LRCK respectively) are configured as output pins, and are
derived from the system clock input (SCKI). Alternatively,
the DSD output data may be provided at the port output.
128f DSD Output Rate with f
S
128f DSD Output Rate with f
S
64f DSD Output Rate with f
= 384f
S
S
64f DSD Output Rate with f
S
= 256f
S
Table 5 shows the available data format selections.
Figure 3 and Figure 4 illustrate the PCM and DSD data
formats.
Reserved
Reserved
Table 5. Audio Data Format Selection
AUDIO DATA FORMATS
FMT1
FMT0
AUDIO DATA FORMAT
0
0
1
1
0
1
0
1
24-bit Left Justified
As mentioned previously, the PCM4202 supports 24-bit
linear PCM output data, as well as 1-bit DSD output data.
The available data formats are dependent upon whether
the PCM4202 is configured in Slave or Master mode. The
S/M (pin 8), FMT0 (pin 6), and FMT1 (pin 7) inputs are
utilized to select either Slave or Master mode and the
corresponding audio data format.
2
24-bit I S
24-bit Right Justified
1-bit DSD (Master Mode Only)
Left Channel
Right Channel
LRCKI
BCKI
MSB
LSB
MSB
LSB
DATA
(a) Left Justified Data Format
LRCKI
BCKI
MSB
LSB
MSB
LSB
DATA
(b) Right Justified Data Format
LRCKI
BCKI
MSB
LSB
MSB
LSB
DATA
(c) I2S Data Format
1/fS
2
Figure 3. PCM Data Formats: Left Justified, Right Justified, and Philips I S
15
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In Slave mode, the BCK and LRCK signals are inputs, with
the clocks being generated by a master timing source,
such as a DSP serial port, PLL clock synthesizer, or a
crystal oscillator/divider circuit. The BCK rate is typically
equal to 128fS in Single Rate sampling mode, and 64fS in
Dual or Quad Rate sampling modes. Although other BCK
clock rates are possible, they are not recommended as a
result if potential clock phase sensitivity issues, which can
degrade the dynamic performance of the PCM4202. The
LRCK clock must be operated at fS, the output sampling
rate.
DSDBCK
DSDL
DN−3 DN−2 DN−1 DN DN+1 DN+2 DN+3 DN+4
DSDR
Figure 4. DSD Output Data Format
AUDIO SERIAL PORT OPERATION
This section provides additional details regarding the
PCM4202 audio serial port, utilized for 24-bit linear PCM
or 1-bit DSD output data. PCM output operation will be
described in this section, while DSD output mode
operation will be described in the following section.
Figure 5 illustrates the typical audio serial port
connections between a PCM4202 and an audio signal
processor when using the PCM output data formats.
Figure 6 illustrates the audio serial port timing for both the
Master and Slave modes of operation.
For PCM data formats, the serial port is comprised of three
signals: BCK (pin 16), LRCK (pin 17), and DATA (pin 15).
The BCK signal functions as the data (or bit) clock for the
serial audio data. The LRCK is the left/right word clock for
the audio serial port. The LRCK and BCK clocks must be
synchronous. The DATA signal is the serial audio data
output, with data being clocked out on the falling edge of
the BCK signal. DATA carries audio data for both the Left
and Right channels.
DSP
FSX
PCM4202
LRCK
CLKR
DR
BCK
DATA
SCKI
As mentioned in the Audio Data Format section of this
datasheet, the audio serial port can operate in Master or
Slave mode. In Master mode, the BCK and LRCK clock
signals are outputs, derived from the system clock input,
SCKI. The BCK clock is fixed at 128fS for Single Rate
sampling mode, and at 64fS for Dual or Quad Rate
sampling modes. The LRCK clock operates at fS, the
output sampling rate (that is, 48kHz, 96kHz, etc.).
System Clock
Figure 5. Typical Audio Serial Port Connections
2
for Left Justified, Right Justified, and I S Data
Formats
tLRCKHL
tLRCKHL
tLRCKHL
LRCK
BCK
tBCKP
tBCKHL
DATA
tBCKDO
DESCRIPTION
MIN
5
MAX
UNITS
µs
PARAMETER
tLRCKP
LRCK Period
LRCK High/Low Time
tLRCKHL
tBCKP
tBCKHL
tBCKDO
2.25
78
µs
BCK Period
ns
BCK High/Low Time
35
ns
SDOUT Data Output Delay from BCK Falling Edge
10
ns
2
Figure 6. Master and Slave Mode Audio Serial Port Timing: Left Justified, Right Justified, and Philips I S
16
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filter can be enabled or disabled for both the Left and Right
channels using the HPFD input (pin 12). Driving the HPFD
input low enables the high-pass filter. Driving the HPFD
input high disables the high-pass filter.
DSD OUTPUT MODE OPERATION
The output port DSD mode operation consists of a single
DSD data clock signal, DSDBCK (pin 17), along with two
synchronous DSD data lines, DSDR (pin 15) and DSDL
(pin 16). The data lines correspond to Right and Left
channels, respectively. The DSD output rate is determined
by the sampling mode settings for the device, discussed
in the Sampling Modes section of this datasheet.
The −3dB corner frequency for the high-pass filter scales
with the output sampling rate, where f−3dB = fS/48000,
where fS is the output sampling rate.
For DSD output data, the serial port is configured in Master
mode, with the DSDBCK derived from the system clock
input, SCKI. The DSDBCK is equivalent to the
oversampling clock supplied to the delta-sigma
modulators. The DSD data outputs, DSDR through DSDL,
are synchronous to the DSDBCK. The clock and data lines
are then connected to a data capture or processing device.
CLIPPING FLAGS
The PCM4202 includes a clipping flag output for each
channel. The outputs are designated CLIPL (pin 21) and
CLIPR (pin 20), corresponding to the Left and Right
channels, respectively. The clipping flags are only
available when using PCM output data formats.
A clipping flag is forced high as soon as the digital output
of the decimation filter exceeds the full-scale range for the
corresponding channel. The clipping flag output is held
high for a maximum of (256 x N) / fS seconds, where N =
128 for Single Rate sampling mode, 256 for Dual Rate
sampling mode, and 512 for Quad Rate sampling mode.
If the decimation filter output does not exceed the full-scale
range during the initial hold period, the output returns to a
low state upon termination of the hold period.
Figure 7 illustrates the DSD port timing for both the DSD
output mode.
HIGH-PASS FILTER
A digital high-pass filter is available for removing the DC
component of the digitized input signal. The filter is located
at the output of the digital decimation filter, and is available
only when using PCM output data formats. The high-pass
DSDBCK
tDCKP
tDCKHL
DSDL
DSDR
tDCKDO
DESCRIPTION
MIN
156
70
MAX
UNITS
PARAMETER
tDCKP
ns
ns
ns
LRCK pulse width
LRCK active edge to BCK sampling edge delay
Data setup time
tDCKP
tDCKP
10
Figure 7. DSD Data Port Timing
17
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢄ
www.ti.com
SBAS290B − JULY 2003 − SEPTEMBER 2004
forced low. Once the initialization sequence is completed,
the PCM4202 output is enabled. Figure 8 shows the
power-on reset sequence timing.
RESET OPERATION
The PCM4202 includes two reset functions: power-on and
externally controlled. This section describes the operation
of each of these functions.
The user may force a reset initialization sequence at any
time while the system clock input is active by utilizing the
RST input (pin 19). The RST input is active low, and
requires a minimum low pulse width of 40ns. The
low-to-high transition of the applied reset signal forces an
initialization sequence to begin. As in the case of the
power-on reset, the initialization sequence requires 1024
system clock periods for completion. Figure 9 illustrates
the reset sequence initiated when using the RST input.
On power-up, the internal reset signal is forced low, forcing
the PCM4202 into a reset state. The power-on reset circuit
monitors the VDD (pin 14) and VCC (pin 22) power supplies.
When the VDD supply exceeds +2.0V ( 400mV) and the
VCC supply exceeds +4.0V ( 400mV), the internal reset
signal is forced high. The PCM4202 then waits for the
system clock input (SCKI) to become active. Once the
system clock has been detected, the initialization
sequence begins. The initialization sequence requires
1024 system clock periods for completion. During the
initialization sequence, the ADC output data pins are
Figure 10 shows the state of the audio data outputs for the
PCM4202 before, during and after the reset operations.
~ 4.0V
VCC
0V
~ 2.0V
VDD
0V
Internal
Reset
1024 System Clock Periods
Required for Initialization
0V
0V
SCKI
System Clock
Indeterminate
or Inactive
Figure 8. Power-On Reset Sequence
18
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
www.ti.com
SBAS290B − JULY 2003 − SEPTEMBER 2004
t
> 40ns
RSTL
RST
0V
0V
1024 System Clock Periods
Required for Initialization
Internal
Reset
SCKI
0V
Figure 9. External Reset Sequence
HI
Internal
Reset
LO
Output
Data Pins
Outputs are Forced Low
for 1024 SCKI Periods
Valid Output Data
Outputs are Forced Low
Valid Output Data
Initialization
Period
Figure 10. ADC Digital Output State for Reset Operations
19
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢄ
www.ti.com
SBAS290B − JULY 2003 − SEPTEMBER 2004
A single ground plane is utilized for the analog and digital
ground connections. This approach ensures a low
impedance connection between the analog and digital
ground pins. The +5V analog and +3.3V digital power
connections are provided from separate supplies.
POWER-DOWN OPERATION
The PCM4202 can be forced to a power-down state by
applying a low level to the RST input (pin 19) for a minimum
of 65,536 system clock cycles. In power-down mode, all
internal clocks are stopped, and output data pins are
forced low. The system clock may then be removed to
conserve additional power. Before exiting power-down
mode, the system and audio clocks should be restarted.
Once the clocks are active, the RST input may be driven
high, which initiates a reset initialization sequence.
Figure 11 illustrates the state of the output data pins during
before, during, and upon exiting the power-down state.
Figure 13 illustrates an example input buffer circuit,
designed for balanced differential input signals. This circuit
is utilized on the PCM4202EVM evaluation board. The
2.7nF and 100pF capacitors shown at the output of the
buffer should be located as close as possible to the analog
input pins of the PCM4202. The buffer shown in Figure 13
can be easily made to function as a single ended to
differential converter by simply grounding the (−) input
terminal of the buffer circuit.
APPLICATIONS INFORMATION
The input impedance for the VCOMIN pin of the OPA1632
A typical connection diagram for the PCM4202 is shown
in Figure 12. Capacitors for power supply and reference
bypassing are shown with recommended values. Bypass
capacitors should be located as close as possible to the
power supply and reference pins of the PCM4202. Due to
its small size, the 0.1µF capacitor can be located on the
component (top) side of the board, while the larger 33µF
capacitor can be located on the solder (bottom) side of the
board.
is relatively low and will load down the VCOML or VCOM
R
outputs from the PCM4202. A voltage follower circuit is
required to buffer these outputs, with a typical circuit
configuration shown in Figure 14. An OPA227 is utilized as
the buffer for the PCM4202EVM evaluation board.
However, alternative op amps with comparable
performance may be substituted.
HI
RST
LO
Outputs are
Forced Low
Outputs are
Forced Low
Output
Data Pins
Outputs are
Forced Low
Valid Output Data
Valid Output Data
1024
65,536
SCKI Periods
Required for
Initialization
SCKI Periods
Enter
Power−Down
State
Figure 11. ADC Digital Output State for Power-Down Operations
20
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
www.ti.com
SBAS290B − JULY 2003 − SEPTEMBER 2004
µ
µ
33 F
33 F
+
+
µ
µ
0.1 F
0.1 F
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VREF
AGNDL
COML
VINL+
L
VREF
AGNDR
COMR
VINR+
R
µ
µ
0.1 F
0.1 F
3
Input Buffer
V
V
4
Left Channel
Analog Input
Right Channel
Analog Input
5
−
INL
−
VINR
V
6
+5V
FMT0
FMT1
S/M
AGND
VCC
7
+
PCM4202
µ
µ
33 F
0.1 F
8
From
CLIPL
CLIPR
RST
To Clipping
Indicators
µ
Logic, P,
9
or
FS0
Hardwired
Connection
10
11
12
13
14
To A/D or System Reset
To Audio System Clock
FS1
FS2
SCKI
HPFD
DGND
VDD
LRCK or DSDBCK
BCK or DSDL
Digital Audio
Transmitter or
Processor
µ
0.1 F
DATA or DSDR
µ
33 F
+
+3.3V
Figure 12. Typical Connection Diagram
21
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢄ
www.ti.com
SBAS290B − JULY 2003 − SEPTEMBER 2004
Ω
270
1nF
−
15V
µ
10 F
+
µ
0.01 F
6
7
100pF
Ω
Ω
1k
Ω
Ω
40.2
40.2
8
1
5
4
(+)
EN
−
+
To VIN
Differential
Analog Input
OPA1632
2.7nF
1k
−
( )
VOCM
To VIN
100pF
2
3
Ω
1k
From
Buffered VCOM
in Figure 14.
µ
0.01 F
µ
0.1 F
µ
10 F
+
+15V
1nF
Ω
270
Figure 13. Example Input Buffer Circuit
OPA227
PCM4202
or equivalent
VCOM
L
To
µ
0.1 F
Buffered VCOM
in Figure 13.
or
VCOM
R
Figure 14. Example Buffer Circuit for V
L and V
R
COM
COM
22
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
www.ti.com
SBAS290B − JULY 2003 − SEPTEMBER 2004
COMPATIBILITY WITH THE PCM1804
D
D
When operating in Master mode with Single Rate
sampling selected, the audio serial port bit clock
Although the PCM4202 and PCM1804 are pin- and
function-compatible, there are a few differences between
the two devices that the designer should be aware of.
(BCK) is equal to 64f for the PCM1804, while the
S
BCK rate is equal to 128f for the PCM4202.
S
The following pins on the PCM4202 and PCM1804
have different names, but they perform the same
functions.
DThese differences are noted here for clarity.
The full-scale input of the PCM4202 is 6.0V
PP
differential, while it is 5.0V for the PCM1804. This
PP
is a result of the PCM4202 having an internal +3.0V
voltage reference, and the PCM1804 having an
internal +2.5V voltage reference.
TERMINAL
NUMBER
PCM4202
TERMINAL NAME
PCM1804
TERMINAL NAME
9
FS0
FS1
OSR0
OSR1
OSR2
BYPAS
OVFR
OVFL
10
11
12
20
21
D
D
The PCM1804 includes +5V tolerant digital inputs.
The PCM4202 does not include these because the
digital inputs are designed for interfacing to +3.3V
logic.
FS2
HPFD
CLIPR
CLIPL
The reset pin (RST) pin of the PCM4202 has an
internal pull-up resistor. For the PCM1804, this pin
has an internal pull-down resistor.
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM4202DB
PCM4202DBR
PCM4202DBT
PCM4202DBTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
DB
DB
DB
DB
28
28
28
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-10 to 70
-10 to 70
-10 to 70
-10 to 70
PCM4202
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
PCM4202
PCM4202
PCM4202
250
250
RoHS & Green
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM4202DBR
PCM4202DBT
SSOP
SSOP
DB
DB
28
28
1000
250
330.0
180.0
16.4
16.4
8.45 10.55
8.45 10.55
2.5
2.5
12.0
12.0
16.2
16.2
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM4202DBR
PCM4202DBT
SSOP
SSOP
DB
DB
28
28
1000
250
356.0
210.0
356.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DB SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PCM4202DB
28
50
530
10.5
4000
4.1
Pack Materials-Page 3
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1
2X
10.5
9.9
8.45
NOTE 3
14
15
0.38
0.22
28X
0.15
C A B
5.6
5.0
B
NOTE 4
2 MAX
0.25
GAGE PLANE
(0.15) TYP
SEE DETAIL A
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022, Texas Instruments Incorporated
相关型号：
PCM4202IDBREP
High-Performance, 24 Bit, 216 kHz Sampling, Stereo Audio Analog-to-Digital Converte
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