PCM5100 [TI]
2VRMS DirectPath, 112/106/100dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface; 2VRMS的DirectPath 112 /106 /百分贝音频立体声DAC，具有32位， 384kHz的PCM接口
| 型号： | PCM5100 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2VRMS DirectPath, 112/106/100dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface |
| 文件： | 总31页 (文件大小：794K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
2V DirectPath™, 112/106/100dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface
RMS
Check for Samples: PCM5100, PCM5101, PCM5102
1
FEATURES
DESCRIPTION
23
•
Hardware Control
The PCM510x devices are a family of monolithic
CMOS integrated circuits that include a stereo
digital-to-analog converter and additional support
circuitry in a small TSSOP package. The PCM510x
uses the latest generation of TI’s advanced segment
DAC architecture to achieve excellent dynamic
performance and improved tolerance to clock jitter.
•
Analog Performance (3.3V Power Supply)
–
–
–
–
–
–
SNR: 112/106/100dB (Typical)
Dynamic Range: 112/106/100dB (Typical)
THD+N: - 93/-92/90dB @ - 1dBfs (Typical)
Full Scale Output: 2.1VRMS (Ground Center)
No DC Blocking Capacitors Required
Market leading low out of band noise.
The PCM510x devices are simpler hardware
controlled 2VRMS DACs, with filter select, PLL and
auto-mute functions.
•
•
Digital Filter Latency & Performance Select
Normal 8× Oversampling Digital Filter:
The PCM510x provides 2.1VRMS ground centered
outputs, allowing designers to eliminate DC blocking
capacitors on the output, as well as external muting
circuits traditionally associated with single supply line
drivers.
–
–
Stopband Attenuation: –60dB
Passband Ripple: ±0.02dB
•
Low Latency 8× Oversampling Digital Filter:
–
–
Stopband Attenuation: –52dB
Passband Ripple: ±0.0001dB
The integrated line driver surpasses all other
charge-pump based line drivers by supporting loads
down to 1kΩ.
•
•
Sampling Frequency: 8kHz To 384kHz
System Clock Multiples (fSCK): 64, 128, 192,
256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072
Accepts 16-, 24-, And 32-Bit Audio Data
PCM Data Formats: I2s, Left-Justified
Intelligent Muting System, Soft Up/Down Ramp
& Analog Mute For 120dB Mute SNR With
Popless Operation.
Integrated Power On Reset
Integrated Negative Charge Pump
Integrated High-Performance Audio PLL With
BCK Reference To Generate SCK Internally
Automatic Power-Save Mode When LRCK And
BCK Are Deactivated.
By supporting loads down to 1kΩ, the PCM510x can
essentially drive up to 10 products in parallel. (LCD
TV, DVDR, AV Receivers etc).
•
•
•
The integrated PLL on the device removes the
requirement for a system clock (commonly known as
master clock). This allows a 3-wire I2S connection,
along with reduced system EMI.
•
•
•
Intelligent clock error and PowerSense under voltage
protection utilizes a two level mute system for
pop-free performance. Upon clock error or system
power failure, the device digitally attenuates the data
(or last known good data), then mutes the analog
circuit
•
•
•
Internal Pop-Free Control For Sample-Rate
Changes Or Clock Halts
Single Supply Operation:
Compared with existing DAC technology, the
PCM510x family offers up to 20dB lower out-of-band
noise, reducing EMI and aliasing in downstream
amplifiers/ADCs. (from traditional 100kHz OBN
measurements all the way to 3MHz)
–
3.3V Analog, 3.3V Digital
•
•
3.3V Failsafe LVCMOS Digital Inputs
Small 20-pin TSSOP Package
The PCM510x accepts industry-standard audio data
formats with 16- to 32-bit data. Sampling rates up to
384kHz are supported.
APPLICATIONS
•
•
•
•
A/V Receivers
DVD, BD Players
HDTV Receivers
Other Applications Requiring 2Vrms output
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
System Two Cascade, Audio Precision are trademarks of Audio Precision.
DirectPath is a trademark of Texas, Instruments, Inc..
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
Table 1. Differences Between PCM510x Devices
Part Number
PCM5102
PCM5101
PCM5100
Dynamic Range
112dB
SNR
THD
112dB
106dB
100dB
–93dB
–92dB
–90dB
106dB
100dB
spacer
LINE OUT
Current
Segment
DAC
DIN (i2s)
Current
Segment
DAC
Zero
Data
Detector
Advanced Mute Control
Clock Halt
Detection
PCM510x
CPVDD (3.3V)
LRCK
BCK
AVDD (3.3V)
DVDD (3.3V)
GND
Power
Supply
PLL Clock
MCK
UVP/Reset
POR
Ch. Pump
Figure 1. PCM510x Functional Block Diagram
2
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
Supply Voltage
AVDD, CPVDD, DVDD
–0.3 to 3.9
–0.3 to 3.9
–0.3 to 3.9
–25 to 85
–65 to 150
Digital Input Voltage
Analog Input Voltage
V
Operating Temperature Range
Storage Temperature Range
°C
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Theta JA
TEST CONDITIONS
MIN
TYP
91.2
1.0
MAX
UNIT
θJA
ψJT
ψJB
θJC
θJB
High K
Top
Psi JT
Psi JB
41.5
25.3
42.0
94.4
ºC/W
Theta JC
Theta JB
Device Power Dissipation
185
mW
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PARAMETER
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
24
32
Bits
Data Format (PCM Mode)
Audio data interface format
I2S, left justified
Audio data bit length
Audio data format
16, 24, 32-bit acceptable
MSB First, 2’s Complement
8
fS
Sampling frequency
System clock frequency
384
kHz
64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or
3072
fSCK, up to 50Mhz
Digital Input/Output
Logic Family: 3.3V LVCMOS compatible
VIH
VIL
IIH
0.7×DVDD
Input logic level
Input logic current
Output logic level
V
0.3×DVDD
VIN = VDD
10
µA
IIL
VIN = 0V
–10
VOH
VOL
IOH = –4mA
IOL = 4mA
0.8×DVDD
V
0.22×DVDD
Copyright © 2011, Texas Instruments Incorporated
3
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic Performance (PCM Mode)(1)(2) (Values shown for three devices PCM5102/PCM5101/PCM5100)
fS = 48kHz
–93/–92/–90
–93/–92/–90
–93/–92/–90
112/106/100
112/106/100
112/106/100
112/106/100
112/106/100
112/106/100
123
-83/ -82/ -80
THD+N at VOUT = -1 dB(2)
Dynamic range(2)
fS = 96kHz
fS = 192kHz
EIAJ, A-weighted, fS = 48kHz
EIAJ, A-weighted, fS = 96kHz
EIAJ, A-weighted, fS = 192kHz
EIAJ, A-weighted, fS = 48kHz
EIAJ, A-weighted, fS = 96kHz
EIAJ, A-weighted, fS = 192kHz
EIAJ, A-weighted, fS = 48kHz
EIAJ, A-weighted, fS = 96kHz
EIAJ, A-weighted, fS = 192kHz
fS = 48 kHz
106/ 100/ 95
Signal-to-noise ratio(2)
dB
Signal to noise ratio with
analog mute(2)(3)
113
123
123
Channel Separation
100/ 95/ 90
109/ 103/ 97
109/ 103/ 97
109/ 103/ 97
fS = 96kHz
fS = 192kHz
Analog Output
Output voltage
Gain error
2.1
±2.0
±2.0
VRMS
–6
–6
6
6
% of FSR
Gain mismatch,
channel-to-channel
% of FSR
Bipolar zero error
Load impedance
At bipolar zero
–5
±1.0
5
mV
1
kΩ
Filter Characteristics–1: Normal
Pass band
0.45fS
Stop band
0.55fS
Stop band attenuation
Pass-band ripple
–60
dB
s
±0.02
Delay time
20/fS
Filter Characteristics–2: Low Latency
Pass band
0.47fS
Stop band
0.55fS
Stop band attenuation
Pass-band ripple
–52
dB
s
±0.0001
Delay time
3.5/fS
(1) Filter condition: THD+N: 20Hz HPF, 20kHz AES17 LPF Dynamic range: 20Hz HPF, 20kHz AES17 LPF, A-weighted Signal-to-noise
ratio: 20Hz HPF, 20kHz AES17 LPF, A-weighted Channel separation: 20Hz HPF, 20kHz AES17 LPF Analog performance specifications
are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.
(2) Output load is 10kΩ, with 470Ω output resistor and a 2.2nF shunt capacitor (see recommended output filter).
(3) Assert XSMT or both L-ch and R-ch PCM data are BPZ
4
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDC
mA
Power Supply Requirements
DVDD
AVDD
Digital supply voltage
Target DVDD = 3.3V
3.0
3.0
3.0
3.3
3.3
3.3
7
3.6
3.6
3.6
12
Analog supply voltage
Charge-pump suply voltage
CPVDD
fS = 48kHz
IDD
DVDD supply current at 3.3V(4) fS = 96kHz
8
fS = 192kHz
9
fS = 48kHz
8
13
IDD
IDD
ICC
DVDD supply current at 3.3V(5) fS = 96kHz
9
mA
mA
mA
fS = 192kHz
10
0.5
11
11
11
22
22
22
0.2
DVDD supply current at 3.3V(6)
fS = 48kHz
0.8
16
AVDD / CPVDD Supply
fS = 96kHz
Current(4)
fS = 192kHz
fS = 48kHz
32
AVDD / CPVDD Supply
ICC
fS = 96kHz
mA
mA
mW
Current(5)
fS = 192kHz
AVDD / CPVDD Supply
Current(6)
fS = n/a
0.4
ICC
fS = 48kHz
59.4
62.7
66.0
99.0
102.3
105.6
2.3
92.4
Power Dissipation, DVDD
3.3V(4)
=
fS = 96kHz
fS = 192kHz
fS = 48kHz
148.5
4.0
Power Dissipation, DVDD
3.3V(4)
=
=
fS = 96kHz
mW
mW
fS = 192kHz
Power Dissipation, DVDD
3.3V(6)
fS = n/a (Power Down Mode)
(4) Input is Bipolar Zero data.
(5) Input is 1kHz -1dBFS data
(6) Power Down Mode
Copyright © 2011, Texas Instruments Incorporated
5
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
DEVICE INFORMATION
PCM510X (top view)
TERMINAL FUNCTIONS, PCM510x
Table 2. TERMINAL FUNCTIONS, PCM510x
TERMINAL
NAME NO.
I/O
DESCRIPTION
CPVDD
CAPP
CPGND
CAPM
VNEG
OUTL
OUTR
AVDD
AGND
DEMP
FLT
1
2
-
O
-
Charge pump power supply, 3.3V
Charge pump flying capacitor terminal for positive rail
Charge pump ground
3
4
O
O
O
O
-
Charge pump flying capacitor terminal for negative rail
Negative charge pump rail terminal for decoupling, -3.3V
Analog output from DAC left channel
Analog output from DAC right channel
Analog power supply, 3.3V
5
6
7
8
9
-
Analog ground
10
11
12
13
14
15
16
17
18
19
20
I
De-emphasis control for 44.1kHz sampling rate(1): Off (Low) / On (High)
Filter select : Normal latency (Low) / Low latency (High)
System clock input
I
SCK
I
BCK
I
Audio data bit clock input
DIN
I
Audio data input
LRCK
FMT
I
Audio data word clock input
I
Audio format selection : I2S (Low) / Left justified (High)
Soft mute control : Soft mute (Low) / soft un-mute (High)
Internal logic supply rail terminal for decoupling
Digital ground
XSMT
LDOO
DGND
DVDD
I
-
-
-
Digital power supply, 3.3V
(1) Failsafe LVCMOS Schmitt trigger input
6
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
TYPICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5100 THD+N vs
vs
PCM5101 THD+N vs
vs
Input Level
Input Level
10
10
-10
-10
-30
-50
-70
-30
-50
-70
-90
-90
-110
-110
-100
-80
-60 -40
Input Level [dBFS]
-20
0
-100
-80
-60 -40
Input Level [dBFS]
-20
0
Figure 2.
Figure 3.
PCM5102 THD+N vs
vs
Input Level
10
-10
-30
-50
-70
-90
-110
-100
-80
-60 -40
Input Level [dBFS]
-20
0
Figure 4.
Copyright © 2011, Texas Instruments Incorporated
7
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5100 FFT Plot at BPZ With AMUTE
PCM5101 FFT Plot at BPZ With AMUTE
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
5
10
Frequency [kHz]
15
20
0
5
10
Frequency [kHz]
15
20
Figure 5.
Figure 6.
PCM5102 FFT Plot at BPZ With AMUTE
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
5
10
Frequency [kHz]
15
20
Figure 7.
8
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5100 FFT Plot at -60dB To 300kHz
PCM5101 FFT Plot at -60dB To 300kHz
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
Frequency [kHz]
200
250
300
0
50
100
150
Frequency [kHz]
200
250
300
Figure 8.
Figure 9.
PCM5102 FFT Plot at -60dB To 300kHz
0
-20
-40
-60
-80
-100
-120
-140
-160
0
50
100
150
Frequency [kHz]
200
250
300
Figure 10.
Copyright © 2011, Texas Instruments Incorporated
9
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
APPLICATION INFORMATION
Reset and System Clock Functions
Power-On Reset Function
The PCM510x includes a power-on reset function shown in Figure 11. With VDD > 2.8V, the power-on reset
function is enabled. After the initialization period, the PCM510x is set to its default reset state.
3.3V
2.8V
AVDD, CPVDD
Internal Reset
Reset Removal
Internal Reset
4ms
I2S Clocks
SCK, BCK, LRCK
Figure 11. Power-On Reset Timing
10
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
System Clock Input
The PCM510x requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 12) and supports up to 50MHz. The PCM510x has
a system clock detection circuit that automatically senses which frequency the system clock is operating.
Common audio sampling frequencies of 8kHz, 16kHz, 32kHz - 44.1kHz - 48kHz, 88.2kHz - 96kHz, 176.4kHz
-192kHz, and 384kHz with ±4% tolerance are supported. The sampling frequency detector sets the clock for the
digital filter, Delta Sigma Modulator (DSM) and the Negative Charge pump (NCP) automatically. Table 3 shows
examples of system clock frequencies for common audio sampling rates.
SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in the
PCM512x and PCM514x devices’ software mode, by configuring various registers. This allows the device to
become a clock master and drive the host’s serial port with LRCK and BCK, from a non audio related clock (e.g.
using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK) ).
Figure 12 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise.
Table 3. System Master Clock Inputs for Audio Related Clocks
System Clock Frequency (fSCK) (MHz)
Sampling
Frequency
64 fS
128 fS
192 fS
256 fS
2.0480
384 fS
3.0720
512 fS
4.0960
768 fS
6.1440
1024 fS
8.1920
1152 fS
9.2160
1536 fS
12.2880
24.5760
49.1520
2048 fS
16.3840
36.8640
3072 fS
24.5760
49.1520
(1)
8 kHz
16 kHz
–
1.0240(2) 1.5360(2)
2.0480(2) 3.0720(2)
4.0960(2) 6.1440(2)
5.6488(2) 8.4672(2)
6.1440(2) 9.2160(2)
11.2896(2) 16.9344
12.2880(2) 18.4320
(1)
–
4.0960
6.1440
8.1920
12.2880
24.5760
33.8688
36.8640
16.3840
32.7680
45.1584
49.1520
18.4320
36.8640
(1)
(1)
(1)
32 kHz
–
8.1920
12.2880
16.9344
18.4320
33.8688
36.8640
16.3840
22.5792
24.5760
45.1584
49.1520
–
–
(1)
(1)
(1)
(1)
(1)
44.1 kHz
48 kHz
–
11.2896
12.2880
22.5792
24.5760
45.1584
49.1520
–
–
–
–
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
88.2 kHz
96 kHz
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
176.4 kHz
192 kHz
384 kHz
–
22.5792
24.5760
49.1520
33.8688
36.8640
–
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
24.5760
–
–
–
–
–
–
–
–
–
–
(1) This system clock rate is not supported for the given sampling frequency.
(2) This system clock rate is supported by PLL mode.
tSCKH
"H"
0.7*DVDD
0.3*DVDD
System Clock
(SCK)
"L"
tSCKL
tSCY
Figure 12. Timing Requirements for SCK Input
Table 4. Timing Requirements for SCK Input
Parameters
Min
20
8
Max
1000
Unit
tSCY
tSCKH
tSCKL
System clock pulse cycle time
System clock pulse width, High
System clock pulse width, Low
ns
ns
ns
8
Copyright © 2011, Texas Instruments Incorporated
11
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
System Clock PLL mode
The system clock PLL mode allows designers to use a simple 3 wire I2S audio source when driving the DAC.
This reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency
electromagnetic interference.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly without SCK for 16
successive LRCK periods, then the internal PLL will start to generate internal SCK from BCK reference
automatically. In the PCM510x, the internal PLL is disabled when an external SCK is supplied; specific BCK
rates are required to generate an appropriate master clock.
Table 5 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate
an internal SCK.
Table 5. BCK Rates (MHz) by LRCK Sample Rate for
PCM510x PLL Operation
BCK (fS)
Sample f (kHz)
32
-
48
-
64
8
-
16
-
-
1.024
2.048
2.8224
3.072
6.144
12.288
24.576
32
1.024
1.4112
1.536
3.072
6.144
12.288
1.536
2.1168
2.304
4.608
9.216
18.432
44.1
48
96
192
384
Audio Data Interface
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 15), BCK (pin 13), and DIN (pin 14). BCK is
the serial audio bit clock, and it is used to clock the serial data present on DIN into the serial shift register of the
audio interface. Serial data is clocked into the PCM510x on the rising edge of BCK. LRCK is the serial audio
left/right word clock.
Table 6. PCM510x Audio Data Formats, Bit Depths and Clock Rates
MAX LRCK
CONTROL MODE
FORMAT
DATA BITS
SCK RATE [x fS]
BCK RATE [x fS]
FREQUENCY [fS]
Up to 192kHz
384kHz
128 – 3072
(≤50MHz)
64, 48, 32
64, 48, 32
Hardware Control
I2S/LJ
32, 24, 20, 16
64, 128
The PCM510x requires the synchronization of LRCK and system clock, but does not need a specific phase
relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and system clock is completed.
If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and BCK is completed.
12
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
PCM Audio Data Formats and Timing
The PCM510x supports industry-standard audio data formats, including standard I2S and left-justified. Data
formats are selected using the FMT (pin 16), Low for I2S, and High for Left-justified.
All formats require binary 2s complement, MSB-first audio data. Figure 13 shows a detailed timing diagram for
the serial audio interface.
LRCK
0.5 * DVDD
(Input)
tLB
tBCH
tBCL
BCK
0.5 * DVDD
0.5 * DVDD
0.5 * DVDD
(Input)
tBCY
tBL
DATA
(Input)
tDS
tDH
tDOD
DATA
(Output)
Figure 13. PCM510x Serial Audio Timing - Slave
Table 7. Audio Interface Slave Timing
Parameters
Min
40
16
16
8
Max
Units
ns
tBCY
BCK Pulse Cycle Time
BCK Pulse Width LOW
BCK Pulse Width HIGH
BCK Rising Edge to LRCK Edge
LRCK Edge to BCK Rising Edge
DATA Set Up Time
tBCL
tBCH
tBL
ns
ns
ns
tLB
8
ns
tDS
8
ns
tDH
DATA Hold Time
8
ns
Copyright © 2011, Texas Instruments Incorporated
13
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
Left Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 14. Left Justified Audio Data Format
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 15. I2S Audio Data Format
14
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
Function Descriptions
Interpolation Filter
The PCM510x provides 2 types of interpolation filter. Users can select which filter to use by using the FLT pin
(pin11)
Table 8. Digital Interpolation Filter Options
FLT Pin Description
0
1
FIR Normal x8/x4/x2/x1 Interpolation Filters
IIR Low Latency x8/x4/x2/x1 Interpolation Filters
The Normal x8 / x4 / x2 / x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sampling frequency
(FS) for from 8kHz to 384kHz.
Table 9. Normal x8 Interpolation Filter
Parameter
Condition
Value (Typ)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45Fs
0.55Fs ….. 7.455Fs
±0.02
–60
dB
22/Fs
s
space
0
−20
−40
−60
−80
1.0
0.8
0.6
0.4
0.2
0.0
−100
−120
−0.2
−0.4
0
1
2
3
4
0
50
100
150
200
Samples
250
300
350
400
Frequency (x fS)
G012
G023
Figure 16. Normal x8 Interpolation Filter Frequency
Response
Figure 17. Normal x8 Interpolation Filter Impulse
Response
Copyright © 2011, Texas Instruments Incorporated
15
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
0.05
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
G034
Figure 18. Normal x8 Interpolation Filter Passband Ripple
16
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
The Normal x4 / x2 / x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sampling frequency (FS) for
from 8kHz to 384kHz.
Table 10. Normal x4 Interpolation Filter
Parameter
Condition
Value (Typ)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45Fs
0.55Fs ….. 7.455Fs
±0.02
–60
dB
22/Fs
s
space
0
−20
−40
−60
−80
1.0
0.8
0.6
0.4
0.2
0.0
−100
−120
−0.2
−0.4
0
1
2
3
4
0
20
40
60
80
Samples
100
120
140
160
Frequency (x fS)
G009
G020
Figure 19. Normal x4 Interpolation Filter Frequency
Response
0.05
Figure 20. Normal x4 Interpolation Filter Impulse
Response
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.5
Frequency (x fS)
1.0
G031
Figure 21. Normal x4 Interpolation Filter Passband Ripple
Copyright © 2011, Texas Instruments Incorporated
17
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
Normal x2 / x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sampling frequency (FS) for from
8kHz to 384kHz.
Table 11. Normal x2 Interpolation Filter
Parameter
Condition
Value (Typ)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45Fs
0.55Fs ….. 7.455Fs
±0.02
–60
dB
22/Fs
s
space
0
−20
−40
−60
−80
1.0
0.8
0.6
0.4
0.2
0.0
−100
−120
−0.2
−0.4
0
1
2
3
4
0
10
20
30
40
50
Samples
60
70
80
90 100
Frequency (x fS)
G006
G017
Figure 22. Normal x2 Interpolation Filter Frequency
Response
0.05
Figure 23. Normal x2 Interpolation Filter Impulse
Response
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.5
1.0
1.5
2.0
Frequency (x fS)
G028
Figure 24. Normal x2 Interpolation Filter Passband Ripple
18
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
The low-latency x8 / x4 / x2 / x1(bypass) Interpolation filter is programmed in 256 cycles in 1 FS for from 8kHz to
384kHz.
Table 12. Low latency x8 Interpolation Filter
Parameter
Condition
Value (Typ)
±0.0001
–52
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45Fs
0.55Fs ….. 7.455Fs
dB
3.5/Fs
s
space
0
−20
−40
−60
−80
1.0
0.8
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−100
−120
0
1
2
3
4
0
50
100
150
200
Samples
250
300
350
400
Frequency (x fS)
G011
G022
Figure 25. Low latency x8 Interpolation Filter
Frequency Response
Figure 26. Low latency x8 Interpolation Filter
Impulse Response
0.00010
0.00008
0.00006
0.00004
0.00002
0.00000
−0.00002
−0.00004
−0.00006
−0.00008
−0.00010
0.0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
G033
Figure 27. Low latency x8 Interpolation Filter Passband Ripple
Copyright © 2011, Texas Instruments Incorporated
19
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
Table 13. Low latency x4 Interpolation Filter
Parameter
Condition
Value (Typ)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45Fs
0.55Fs ….. 3.455Fs
±0.0001
–52
dB
3.5
s
space
0
1.0
0.8
−20
−40
0.6
0.4
−60
0.2
0.0
−80
−0.2
−0.4
−0.6
−100
−120
0
1
2
3
4
0
20
40
60
80
Samples
100 120 140 160 180
Frequency (x fS)
G008
G019
Figure 28. Low latency x4 Interpolation Filter
Frequency Response
Figure 29. Low latency x4 Interpolation Filter
Impulse Response
0.0001
0.00008
0.00006
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.5
Frequency (x fS)
1.0
G030
Figure 30. Low latency x4 Interpolation Filter Passband Ripple
20
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
Table 14. Low latency x2 Interpolation Filter
Parameter
Condition
Value (Typ)
±0.0001
–52
Units
dB
Filter Gain Pass Band 0 ……. 0.45Fs
Filter Gain Stop Band 0.55Fs ….. 1.455Fs
Filter Group Delay
dB
3.5
s
space
0
1.0
0.8
0.6
−20
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
1
2
3
4
0
10
20
30
40
50
Samples
60
70
80
90 100
Frequency (x fS)
G005
G016
Figure 31. Low latency x2 Interpolation Filter
Frequency Response
Figure 32. Low latency x2 Interpolation Filter
Impulse Response
0.0001
0.00008
0.00006
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.5
Frequency (x fS)
1.0
G030
Figure 33. Low latency x2 Interpolation Filter Passband Ripple
Copyright © 2011, Texas Instruments Incorporated
21
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
Zero Data Detect
The PCM510x has a zero-data detect function. When the device detects continuous zero data, it will do a full
analog mute.
The PCM510x counts zero data over 1024LRCK’s (21ms @ 48kHz) before setting analog mute.
Power Save Mode
When any kind of clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510x will move into
Stand-by mode automatically. The Current segment DAC and Line driver will also be powered down.
When BCK and LRCK halt to a low level for more than 1 second, the PCM510x will go into Power down mode
automatically. Power-down mode includes the negative charge pump and Bias/Reference circuit power-down in
addition to stand-by.
Whenever expected Audio clocks (SCK, BCK, LRCK) are applied to the PCM510x, the device starts its powerup
sequence automatically.
XSMT Pin (Soft Mute / Soft Un-Mute)
For external digital control of the PCM510x, the XSMT pin needs to be driven by an external digital host with a
specific/minimum rising time (tr) and falling time (tf) for soft mute and soft un-mute. The PCM510x expects tr/tf
times of less than 20ns. In the majority of applications, this shouldn’t be a problem, however, traces with high
capacitance may have issues.
When the XSMT pin is shifted from high to low (3.3V to 0V), a soft digital attenuation ramp is started. -1dB
attenuation will be applied every 1fS from 0dBFS to - ∞. This takes 104 sample times.
When the XSMT pin is shifted from low to high (0V to 3.3V), a soft digital “un-mute” is started. 1dB gain steps are
applied every FS from - ∞ to 0dBFS. This takes 104 sample times.
0.9 * DVDD
XSMT
0.1 * DVDD
tR
tF
<20ns
<20ns
Figure 34. XSMT Timing for Soft Mute and Soft Un-Mute
Table 15. XSMT Timing Parameters
Parameters
Rise time (tR)
Fall time (tF)
Min
Max
20
Unit
ns
20
ns
22
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
External Power Sense Undervoltage Protection mode
The XSMT pin can also be used to monitor a system voltage, such as the 24VDC LCD TV backlight, or 12VDC
system supply using a potential divider created with two resistors. (See Figure 35 )
•
If the XSMT pin makes a transition from “1” to “0” over 6ms or more, the device will switch into external
under-voltage protection mode. In this mode, two trigger levels are used.
•
•
When XSMT pin level reaches 2V, soft mute process begins.
When XSMT pin level reaches 1.2V, analog mute will engage, regardless of digital audio level, and analog
shut down will begin. (i.e. DAC circuitry will power down etc).
A timing diagram to show this is shown in Figure 36.
NOTE
The XSMT input pins voltage range is from -0.3V to DVDD + 0.3V.The ratio of external
resistors must be considered within this input range. Any increase in power supply (such
as power supply positive noise/ripple) can pull the XSMT pin higher than DVDD+0.3V.
For example, if the PCM510x is monitoring a 12V input, and dividing the voltage by 4, then the voltage at XSMT
during ideal power supply conditions will be 3V. If the voltage spikes any higher than 14.4V, then XSMT will see
a voltage in excess of 3.6V (DVDD+0.3), potentially damaging the device.
Providing the divider is set appropriately, any DC voltage can be monitored.
System
VDD
12V
supply
7.25kO
XSMT
2.75kO
Figure 35. XSMT in External UVP Mode
Digital Attenuation Followed by Analog Mute
0.9 * DVDD
2.0 V
1.2 V
Analog Mute
XSMT
0.1 * DVDD
tf
Figure 36. XSMT Timing for Undervoltage Protection
Copyright © 2011, Texas Instruments Incorporated
23
PCM5100, PCM5101, PCM5102
SLAS764 –MAY 2011
www.ti.com
Typical Application Circuits
Figure 37. PCM510x Standard PCM Audio Operation, 3.3V
24
Copyright © 2011, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764 –MAY 2011
Recommended Output Filter for the PCM510x
The diagram in Figure 38 shows the recommended output filter for the PCM510x. The new PCM510x next
generation current segment architecture offers excellent out of band noise, making a traditional 20kHz low pass
filter a thing of the past.
The RC settings below offer a -3dB filter point at 153kHz (approx), giving the DAC the ability to reproduce
virtually all frequencies through to it’s maximum sampling rate of 384kHz.
OUTL
470ꢀ
2.2nF
LINE
OUT
PCM510x
2VRMS
Output voltage is
With a 10kꢀ Load
OUTR
470ꢀ
2.2nF
Figure 38. Recommended Output Lowpass Filter for 10kΩ Operation
Copyright © 2011, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
PCM5100PW
PCM5100PWR
PCM5101PW
PCM5101PWR
PCM5102PW
PCM5102PWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
20
20
20
20
20
20
70
2000
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
2000
70
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2011
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM5100PWR
PCM5101PWR
PCM5102PWR
TSSOP
TSSOP
TSSOP
PW
PW
PW
20
20
20
2000
2000
2000
330.0
330.0
330.0
16.4
16.4
16.4
6.95
6.95
6.95
7.1
7.1
7.1
1.6
1.6
1.6
8.0
8.0
8.0
16.0
16.0
16.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM5100PWR
PCM5101PWR
PCM5102PWR
TSSOP
TSSOP
TSSOP
PW
PW
PW
20
20
20
2000
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
33.0
33.0
33.0
Pack Materials-Page 2
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