PCM5310PAP [TI]
24-Bit, 96-/192-kHz, Asynchronous, 4-Channel/4-Channel Audio Codec with 2-VRMS Driver, Headphone Driver, and 6 Audio Interface Ports; 24位， 96 / 192 - kHz时，异步， 4通道/ 4通道音频编解码器与2 - VRMS驱动器，耳机驱动器，6个音频接口端口
| 型号： | PCM5310PAP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-Bit, 96-/192-kHz, Asynchronous, 4-Channel/4-Channel Audio Codec with 2-VRMS Driver, Headphone Driver, and 6 Audio Interface Ports |
| 文件： | 总103页 (文件大小：1808K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM5310
Burr-Brown Audio
www.ti.com ............................................................................................................................................................................................ SLES244–FEBRUARY 2009
24-Bit, 96-/192-kHz, Asynchronous, 4-Channel/4-Channel Audio Codec
with 2-V Driver, Headphone Driver, and 6 Audio Interface Ports
RMS
1
FEATURES
•
Power-Supply Voltage:
234
•
2- or 2.4-VRMS Output (Typ), 2-VRMS Input (Typ)
–
–
9 V for 2-VRMS Driver
•
Asynchronous Operation for 2 Stereo DACs
and 2 Stereo ADCs
3.3 V for Digital and Analog
•
Power Consumption:
•
•
6 Audio Interface Ports with Mux and Bypass
Performance:
–
–
360 mW at fS = 48-kHz Operation
25.5 µW in Power-Down Mode
–
–
–
–
–
–
–
–
–
THD+N (fS = 48 kHz):
0.01% (ADC), 0.01% (DAC)
•
•
•
Pop Noise Reduction at Clock Halt
Short-Circuit Protection for Headphone Output
Flexible GPIO Port:
SNR/DR (fS = 48 kHz):
95 dB (ADC), 100 dB (DAC)
–
–
–
–
–
Internal Mute Flag
Line Input (Stereo x6):
Available for 2-VRMS Input
Internal Zero Flag
Headphone Insertion Detection Status
Headphone Short-Circuit Protection Status
Line Output (Stereo x2):
Available for 2-VRMS or 2.4-VRMS Output
Logic Functions (AND, NAND, OR, NOR,
BUF, INV)
Headphone Output:
> 20 mW into 32 Ω, > 30 mW into 16 Ω
•
•
Package: 64-Pin HTQFP PowerPAD™
Sampling Rate:
96 kHz (ADC), 192 kHz (DAC)
Operating Temperature Range:–25°C to +85°C
System Clock:
128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS
APPLICATIONS
•
•
•
Digital TV
DVD Recorder
IP-STB (Set Top Box)
Digital Filter Passband Ripple:
±0.05 dB (ADC), ±0.04 dB (DAC)
Digital Filter Stop Band Attenuation:
–65 dB (ADC), –50 dB (DAC)
DESCRIPTION
•
•
I2C™ Interface
The PCM5310 is a four-channel/four-channel audio
codec with a 2-VRMS driver, headphone amplifier,
analog multiplexer (mux), and six audio interface
ports for digital TV applications.
Multifunctions:
–
–
Audio Interface:
I2S™, Left-Justified, and Right-Justified
Digital Attenuation:
The PCM5310 accepts left-justified, right-justified,
and I2S audio data formats with 16 or 24 bits. The
PCM5310 also incorporates many functions through
the I2C interface, such as an analog bypass mode,
analog volume control, analog level control, analog
multiplexer, GPIO, zero flag, short protection,
de-emphasis filter, high-pass filter, and digital
attenuator. The six audio interface ports each have a
built-in digital mux and bypass functions to reduce the
need for additional DSP ports or other devices.
0 dB to –100 dB in 0.5-dB Steps (DAC),
20 dB to –100 dB in 0.5-dB Steps (ADC)
–
–
–
–
–
–
Digital Soft Mute: 1.0-dB Steps to Mute
Digital De-Emphasis Filter: 32, 44.1, 48 kHz
Digital Audio Interface Mux and Bypass
Line Input Level Control: 9, 6, 3, 0 dB
Line Output Level Control: 0, –0.5, –1.0 dB
Headphone Output Volume Control:
12 dB to –70 dB in 1-dB Steps
–
Oversampling Rate Control for DAC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
PowerPAD is a trademark of Texas Instruments.
I2C, I2S are trademarks of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
PCM5310
SLES244–FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
VCCDA, VCCAD, VCCP, VDD
VCCH
PCM5310
–0.3 to 4.0
–0.3 to 10
±0.1
UNIT
V
Supply voltage
V
Ground voltage differences: AGNDAD, AGNDDA, PGND, HGND, DGND
Input voltage
V
–0.3 to 4.0
±10
V
Input current (all pins except supplies)
Ambient temperature under bias
Storage temperature
mA
°C
°C
°C
°C
°C
–40 to +125
–55 to +150
+150
Junction temperature
Lead temperature (soldering, 5s)
Package temperature (IR reflow, peak)
+260
+260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
MIN
3.0
NOM
MAX
3.6
UNIT
V
Analog supply voltage, VCCAD, VCCDA, VCCP
Analog supply voltage, VCCH
Digital supply voltage, VDD
3.3
8.55
3.0
9
3.3
9.45
3.6
V
V
Analog input voltage, full-scale (–0 dB)
Analog output voltage, full-scale (–0 dB)
Digital input logic family
2
VRMS
VRMS
2
2.4
CMOS
ADC system clock
ADC sampling clock
DAC system clock
DAC sampling clock
4.096
32
36.864
96
MHz
kHz
MHz
kHz
kΩ
Digital input clock frequency
4.096
32
36.864
192
Analog output load resistance
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature, TA
10
30
10
pF
pF
–25
+85
°C
2
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PCM5310
www.ti.com ............................................................................................................................................................................................ SLES244–FEBRUARY 2009
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS(1) = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
PCM5310
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO DATA
Data Format
Audio data bit length
Audio data interface format
Audio data format
16, 24
Bits
I2S, left-justified, right-justified
MSB, twos complement
ADC
DAC
ADC
DAC
ADC
DAC
108
216
kHz
kHz
Sampling
frequency
256 fS, 384 fS, 512 fS, 768 fS
MHz
MHz
MHz
MHz
System clock
Bit clock
128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS
48 fS, 64 fS
32 fS, 48 fS, 64 fS
DIGITAL INPUT/OUTPUT
Logic family
CMOS-compatible
VIH
VIL
IIH
Input logic high level
Input logic low level
0.7 VDD
0.3 VDD
10
V
V
Input logic high current
Input logic low current
Output logic high level
Output logic low level
µA
µA
V
IIL
–10
VOH
VOL
IOH = 2 mA
0.75 VDD
IOH = –2 mA
0.25 VDD
V
DAC LINE OUTPUT
Dynamic Performance
Digital input = 0 dB, G242, G241
= low
2
VRMS
VRMS
Full-scale output voltage
Digital input = 0 dB, G242, G241
= high
2.4
Dynamic range
EIAJ, A-weighted
EIAJ, A-weighted
90
90
88
100
100
97
dB
dB
dB
SNR
Signal-to-noise ratio
Channel separation
Digital input = 0 dB, G242, G241
= low
THD+N
Total harmonic distortion + noise
0.01
0.02
%
Load resistance
AC load
10
kΩ
DC Accuracy
Gain error
Digital input = 0 dB, G242, G241
= low
±3
±3
±13 % of FSR
±13 % of FSR
Gain mismatch,
channel-to-channel
Bipolar zero error
Center voltage
Zero data input
Zero data input
±40
±120
mV
V
0.5 VCCDA
Analog Gain Control
Gain range
Gain error
0, –0.5, –1.0
±0.5
dB
dB
(1) fS = sampling rate.
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
PCM5310
PARAMETER
DAC HEADPHONE OUTPUT
Dynamic Performance
Full-scale output voltage
Dynamic range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital input = 0 dB, VOL = 0dB
EIAJ, A-weighted
1
96
96
88
0.1
1
VRMS
dB
dB
dB
%
85
85
SNR
Signal-to-noise ratio
Channel separation
EIAJ, A-weighted
RL = 32 Ω
RL = 32 Ω, VOL = 0 dB
RL = 16 Ω, VOL = 0 dB
0.18
3
THD+N
Total harmonic distortion + noise
Load resistance
%
16
Ω
DC Accuracy
Gain error
Digital input = 0 dB, VOL = 0dB
±3
±3
±13 % of FSR
±13 % of FSR
Gain mismatch,
channel-to-channel
Bipolar zero error
Center voltage
Zero data input
Zero data input
±27
±80
mV
V
0.5 VCCDA
Analog Volume
Gain range
Gain error
Gain step
–70
12
dB
dB
dB
0.5
1.0
ADC LINE INPUT
Dynamic Performance
Full-scale input voltage
Digital input = 0 dB, VOL = 0dB
EIAJ, A-weighted
2
95
95
93
VRMS
dB
Dynamic range
85
85
SNR
Signal-to-noise ratio
Channel separation
EIAJ, A-weighted
dB
dB
Analog input = –1 dB, VOL =
0dB
THD+N
Total harmonic distortion + noise
0.01
0.018
%
DC Accuracy
Gain error
Analog input = 0 dB, VOL = 0dB
±3
±3
±13 % of FSR
±13 % of FSR
Gain mismatch,
channel-to-channel
Bipolar zero error
Center voltage
Zero data input
Zero data input
±17
±50
mV
V
0.5 VCCAD
Analog Input
Input impedance
Analog Gain Control
37.6
47
56.4
kΩ
Gain range
Gain error
9, 6, 3, 0
±0.5
dB
dB
4
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PCM5310
www.ti.com ............................................................................................................................................................................................ SLES244–FEBRUARY 2009
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
PCM5310
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT TO ANALOG OUTPUT PATH (BYPASS)
Dynamic Performance
Full-scale input voltage
Analog input = 0 dB, VOL = 0dB
2
2
VRMS
VRMS
Analog input = 0 dB, G242,
G241 = low
Full-scale output voltage
Dynamic range
EIAJ, A-weighted
EIAJ, A-weighted
90
90
88
100
100
97
dB
dB
dB
SNR
Signal-to-noise ratio
Channel separation
Analog input = 0 dB, G242,
G241 = low
THD+N
Total harmonic distortion + noise
0.003
0.006
%
DC Accuracy
Gain error
Analog input = 0 dB, G242,
G241 = low
±3
3
±13 % of FSR
±13 % of FSR
Gain mismatch,
channel-to-channel
Bipolar zero error
Zero data input
Zero data input
Zero data input
±20
0.5 VCCAD
0.5 VCCDA
±60
mV
V
analog input
analog output
Center voltage
V
Analog Input
Input impedance
37.6
47
56.4
kΩ
FILTERS
Interpolation Filters for DAC
Passband
0.454 fS
±0.04
kHz
kHz
dB
dB
s
Stop band
0.546 fS
–50
Passband ripple
Stop-band attenuation
Group delay
20/fS
±0.1
De-emphasis error
Analog Filter for DAC
Frequency response
Cutoff frequency
dB
fC = 20 kHz
±0.1
190
dB
Gain = –3 dB
kHz
Decimation Filter for ADC
Passband
0.454 fS
±0.05
kHz
kHz
dB
dB
s
Stop band
0.583 fS
–65
Passband ripple
Stop-band attenuation
Group delay
17.4/fS
Analog Filter for ADC
Frequency response
Cutoff frequency
fC = 20 kHz
±0.01
500
dB
Gain = –3 dB
kHz
High-Pass Filter for ADC
Frequency response
Gain = –3 dB
0.91
Hz
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
PCM5310
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER-SUPPLY REQUIREMENTS
VDD
Digital voltage range
3
3
3.3
3.3
3.3
3.3
9
3.6
3.6
V
V
VCCAD
VCCDA
VCCP
VCCH
DAC voltage range
ADC voltage range
3
3.6
V
Headphone driver voltage range
2-VRMS driver voltage range
3
3.6
V
8.55
9.45
120
100
450
350
V
Zero data input, all active
All power-down
98
mA
µA
mW
µW
Supply current
6
Zaro data input, all active
All power-down
360
25.5
Power dissipation
TEMPERATURE RANGE
Operating temperature range
Thermal resistance
–25
+85
°C
θJA
HTQFP-64
21
°C/W
6
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PCM5310
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PIN ASSIGNMENTS
PAP PACKAGE
HTQFP-64
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AIN1L
AIN1R
AIN2L
AIN2R
AIN3L
AIN3R
AIN4L
AIN4R
AIN5L
1
2
3
4
5
6
7
8
9
48 BCK5
47 SCK5
46 DATA4
45 LRCK4
44 BCK4
43 SCK4
42 DGND
41 VDD
PCM5310
PowerPAD
40 DATA3
39 LRCK3
38 BCK3
37 SCK3
36 DATA2
35 LRCK2
34 BCK2
33 SCK2
AIN5R 10
AIN6L 11
AIN6R 12
LO1L 13
LO1R 14
LO2L 15
LO2R 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN DESCRIPTIONS
PIN
NAME
AIN1L
AIN1R
AIN2L
AIN2R
AIN3L
AIN3R
AIN4L
AIN4R
AIN5L
AIN5R
AIN6L
AIN6R
LO1L
NO.
I/O
DESCRIPTION
Line input 1 L-channel
1
2
I
I
Line input 1 R-channel
3
I
Line input 2 L-channel
4
I
Line input 2 R-channel
5
I
Line input 3 L-channel
6
I
Line input 3 R-channel
7
I
Line input 4 L-channel
8
I
Line input 4 R-channel
9
I
Line input 5 L-channel
10
11
12
13
14
15
I
Line input 5 R-channel
I
Line input 6 L-channel
I
Line input 6 R-channel
O
O
O
Line output 1 L-channel
Line output 1 R-channel
Line output 2 L-channel
LO1R
LO2L
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PIN DESCRIPTIONS (continued)
PIN
NAME
LO2R
NO.
16
19
22
25
64
62
63
60
61
23
24
20
21
41
42
18
17
26
29
30
31
32
33
34
35
36
37
38
39
40
43
44
45
46
47
48
49
50
51
52
53
54
28
27
55
56
57
58
59
I/O
O
DESCRIPTION
Line output 2 R-channel
HPOL
O
Headphone output L-channel
Headphone output R-channel
Common voltage for DAC
Common voltage for ADC
Reference voltage 1 for ADC
Reference voltage 2 for ADC
Power supply for ADC (3.3-V typical)
Ground for ADC
HPOR
VCOMDA
VCOMAD
VREFAD1
VREFAD2
VCCAD
AGNDAD
VCCDA
AGNDDA
VCCP
O
—
—
—
—
—
—
—
Power supply for DAC (3.3-V typical)
Ground for DAC
—
—
Power supply for headphone (3.3-V typical)
Ground for headphone
PGND
VDD
—
—
Power supply for digital (3.3-V typical)
Digital ground
DGND
VCCH
HGND
AGNDS
SCK1
—
—
Power supply for 2-VRMS driver (9.0-V typical)
Ground for 2-VRMS driver
Analog ground
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PORT-1 system clock
BCK1
PORT-1 serial bit clock
LRCK1
DATA1
SCK2
PORT-1 left and right channel clock
PORT-1 serial audio data
PORT-2 system clock
BCK2
PORT-2 serial bit clock
LRCK2
DATA2
SCK3
PORT-2 left and right channel clock
PORT-2 serial audio data
PORT-3 system clock
BCK3
PORT-3 serial bit clock
LRCK3
DATA3
SCK4
PORT-3 left and right channel clock
PORT-3 serial audio data
PORT-4 system clock
BCK4
PORT-4 serial bit clock
LRCK4
DATA4
SCK5
PORT-4 left and right channel clock
PORT-4 serial audio data
PORT-5 system clock
BCK5
PORT-5 serial bit clock
LRCK5
DATA5
SCK6
PORT-5 left and right channel clock
PORT-5 serial audio data
PORT-6 system clock
BCK6
PORT-6 serial bit clock
LRCK6
DATA6
SCL
PORT-6 left and right channel clock
PORT-6 serial audio data
Clock for I2C interface
Data for I2C interface
SDA
I/O
I/O
I/O
I/O
I
GPIO1
GPIO2
GPIO3
RSTB
General-purpose input and output 1
General-purpose input and output 2
General-purpose input and output 3
Reset (active low)
AMUTE
I
Analog mute control for all analog outputs (active high)
8
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PCM5310
www.ti.com ............................................................................................................................................................................................ SLES244–FEBRUARY 2009
FUNCTIONAL BLOCK DIAGRAM
Digital Audio Interface
with Mux and Bypass
I2C
GPIO
Interpolation Filter
and
De-Emphasis
Decimation Filter
and
High-Pass Filter (HPF)
AGNDS
DGND
VDD
PGND
VCCP
Stereo
ADC
Stereo
ADC
HGND
Stereo
DAC
Stereo
DAC
VCCH
AGNDDA
VCCDA
AGNDAD
(VCCAD)
Mux
Mux
HP
HP
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TYPICAL CHARACTERISTICS: Digital Filter (DAC) Sharp, Slow
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
FREQUENCY RESPONSE
(0 fS to 4 fS)
FREQUENCY RESPONSE, PASSBAND
(0 fS to 0.5 fS)
0
-20
0.1
0
-40
-0.1
-0.2
-0.3
-0.4
-0.5
-60
-80
-100
-120
-140
-160
0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
Normalized Frequency (x fS)
Normalized Frequency (x fS)
Figure 1.
Figure 2.
TYPICAL CHARACTERISTICS: Analog Filter (DAC)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
FREQUENCY RESPONSE
(0 Hz to 10 MHz)
FREQUENCY RESPONSE
(0 Hz to 100 kHz)
2
1
0
-20
-40
0
-60
-1
-80
-100
-2
1
10
100
1 k
10 k 100 k 1 M
10 M
1
10
100
1 k
10 k
100 k
Frequency (Hz)
Frequency (Hz)
Figure 3.
Figure 4.
10
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TYPICAL CHARACTERISTICS: Digital Filter (ADC)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
FREQUENCY RESPONSE
(0 fS to 32 fS)
FREQUENCY RESPONSE, PASSBAND
(0 fS to 0.5 fS)
0
-20
0.1
0
-40
-0.1
-0.2
-0.3
-0.4
-0.5
-60
-80
-100
-120
-140
-160
0
0.1
0.2
0.3
0.4
0.5
0
4
8
12
16
20
24
28
32
Normalized Frequency (x fS)
Normalized Frequency (x fS)
Figure 5.
Figure 6.
HIGH-PASS FILTER RESPONSE
(0 fS to 0.4 fS)
HIGH-PASS FILTER RESPONSE
(0 fS to 0.1 fS)
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-10
-15
-20
-25
-30
-35
-40
-45
-50
0
0.1
0.2
0.3
0.4
0
0.02
0.04
0.06
0.08
0.10
Normalized Frequency (x fS)
Normalized Frequency (x fS)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS: Analog Performance (DAC)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
vs VCC SUPPLY VOLTAGE
SIGNAL-TO-NOISE RATIO AND DATA RATE
vs VCC SUPPLY VOLTAGE
0.1
110
105
100
95
THD+N_48(%)
THD+N_96(%)
THD+N_192(%)
0.01
SNR_48(dB)
SNR_96(dB)
SNR_192(dB)
DR_48(dB)
90
DR_96(dB)
DR_192(dB)
0.001
85
3.0
3.3
3.6
3.0
3.3
3.6
VCC (V)
VCC (V)
Figure 9.
Figure 10.
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
SIGNAL-TO-NOISE RATIO AND DATA RATE
vs TEMPERATURE
0.1
110
105
100
95
THD+N_48(%)
THD+N_96(%)
THD+N_192(%)
0.01
SNR_48(dB)
SNR_96(dB)
SNR_192(dB)
DR_48(dB)
DR_96(dB)
DR_192(dB)
90
0.001
85
-25
0
25
50
75
100
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS: Analog Performance (ADC)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
vs VCC SUPPLY VOLTAGE
SIGNAL-TO-NOISE RATIO AND DATA RATE
vs VCC SUPPLY VOLTAGE
0.1
110
105
100
95
SNR_48(dB)
SNR_96(dB)
DR_48(dB)
DR_96(dB)
THD+N_48(%)
THD+N_96(%)
0.01
90
0.001
85
3.0
3.3
3.6
3.0
3.3
3.6
VCC (V)
VCC (V)
Figure 13.
Figure 14.
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
SIGNAL-TO-NOISE RATIO AND DATA RATE
vs TEMPERATURE
0.1
110
105
100
95
THD+N_48(%)
THD+N_96(%)
0.01
SNR_48(dB)
SNR_96(dB)
DR_48(dB)
DR_96(dB)
90
0.001
85
-25
0
25
50
75
100
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS: Analog Performance (Headphone)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
vs OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs OUTPUT POWER
(48 kHz, 16 Ω)
(48 kHz, 32 Ω)
100
10
100
10
THD+N_3V(%)
THD+N_3.3V(%)
THD+N_3.6V(%)
THD+N_3V(%)
THD+N_3.3V(%)
THD+N_3.6V(%)
1
1
0.1
0.01
0.1
0.01
10
20
30
40
50
60
10
20
30
40
50
60
70
80
90
100
Output Power (mW)
Output Power (mW)
Figure 17.
Figure 18.
TOTAL HARMONIC DISTORTION + NOISE
vs OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs OUTPUT POWER
(48 kHz, 0 dB, 6 dB, 12 dB, 16 Ω)
(48 kHz, 0 dB, 6 dB, 12 dB, 32 Ω)
10
10
THD+N_0dB(%)
THD+N_6dB(%)
THD+N_12dB(%)
THD+N_0dB(%)
THD+N_6dB(%)
THD+N_12dB(%)
1
1
0.1
0.1
0.01
0.01
10
20
30
40
50
60
70
10
15
20
25
30
35
40
Output Power (mW)
Output Power (mW)
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS: Output Spectrum (DAC)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
AMPLITUDE vs FREQUENCY
(0 dB, 0 kHz to 20 kHz)
AMPLITUDE vs FREQUENCY
(–60 dB, 0 kHz to 20 kHz)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 21.
Figure 22.
AMPLITUDE vs FREQUENCY
(Zero Data Input, 0 kHz to 20 kHz)
AMPLITUDE vs FREQUENCY
(Zero Data Input, 0 kHz to 130 kHz)
0
-20
20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5
10
15
20
0
20
40
60
80
100
120
Frequency (kHz)
Frequency (kHz)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS: Output Spectrum (ADC)
All specifications at TA = +25°C, VDD = VCCAD = VCCDA = VCCP = 3.3 V, VCCH = 9 V, fS = 48 kHz, system clock = 256 fS, and
24-bit data, unless otherwise noted.
AMPLITUDE vs FREQUENCY
(0 dB, 0 kHz to 20 kHz)
AMPLITUDE vs FREQUENCY
(–60 dB, 0 kHz to 20 kHz)
20
0
20
0
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 25.
Figure 26.
AMPLITUDE vs FREQUENCY
(Zero Data Input, 0 kHz to 20 kHz)
20
0
-20
-40
-60
-80
-100
-120
-140
0
5
10
15
20
Frequency (kHz)
Figure 27.
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DETAILED DESCRIPTION
ANALOG INPUTS
The PCM5310 includes a four-channel analog-to-digital converter (ADC) with a programmable gain amplifier
(PGA) and six stereo analog inputs with a 2-VRMS input. Pins AIN1L/1R to AIN6L/6R are connected to the ADC
left (L) or right (R) channel through the analog multiplexer (mux) and PGA, as shown in Figure 28. If the analog
input voltage level is less than 2 VRMS, it can be amplified by using the PGA. The gain level can be set to 9 dB,
6 dB, or 3 dB. The descriptions for the analog input registers are shown in Table 1.
AIN1L
PGA-AD1L
AIN2L
AIN3L
ADC-1L
AIN4L
AIN5L
AIN6L
AIN1R
PGA-AD1R
AIN2R
AIN3R
ADC-1R
AIN4R
AIN5R
AIN6R
PGA-AD2L
ADC-2L
PGA-AD2R
ADC-2R
Figure 28. Analog Inputs
Table 1. Analog Input Registers
REGISTER DESCRIPTION
Analog input mux selection for ADC1L/1R
Analog input mux selection for ADC2L/2R
Analog input gain control for ADC1L/1RW
Analog input gain control for ADC2L/2R
REGISTER NUMBER
REGISTER BITS
AX1R[2:0], AX1L[2:0]
AX2R[2:0], AX2L[2:0]
AG1R[1:0], AG1L[1:0]
AG2R[1:0], AG2L[1:0]
20
21
22
23
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ANALOG OUTPUTS
The PCM5310 includes a four-channel digital-to-analog converter (DAC), two stereo line outputs with analog
level control, a headphone output with analog volume control, and an analog multiplexer (mux) with analog direct
input path. Line outputs (LO1L, LO1R, LO2L, LO2R) have a 2-VRMS capability without external amplifiers. If an
audio application requires a higher output voltage level, the PCM5310 can achieve a 2.4-VRMS output.
The headphone output (HPOL, HPOR) has a driving capability of more than 30 mW of output power into a 16-Ω
load at 0.1% THD, and an analog volume with zero crossing that can be controlled from –70 dB to 12 dB. For
audio applications that require it, the analog volume for the the L- and R-channels can be set simultaneously
using the headphone output update control.
The line outputs and headphone output can select analog input sources from all the analog inputs and each DAC
channel, as shown in Figure 29. The descriptions for the analog output registers are shown in Table 2.
AIN1L
AIN2L
AIN3L
AIN4L
AIN5L
AIN6L
AIN1R
AIN2R
AIN3R
AIN4R
AIN5R
AIN6R
PGA-L01L
DAC-1L
DAC-1R
PGA-L01R
DAC-2L
DAC-2R
PGA-L02L
PGA-L02R
PGA-HPOL
HP
PGA-HPOR
HP
Figure 29. Analog Outputs
Table 2. Analog Output Registers
REGISTER DESCRIPTION
Gain level control for line outputs
REGISTER NUMBER
REGISTER BITS
27
28
GL2R[1:0], GL2L[1:0], GL1R[1:0], GL1L[1:0]
G242, G241
2.0 VRMS or 2.4 VRMS selection for line outputs
Headphone volume zero crossing update control
Headphone output volume level setting
30
HUPE, HSUR, HSUL, HZRS
HMUL, HMUR, HVOL[6:0], HVOR[6:0]
AL1R[3:0], AL1L[3:0]
31, 32
24
Analog output mux selection for line output 1
Analog output mux selection for line output 2
25
AL2R[3:0], AL2L[3:0]
Analog output mux selection for headphone output
26
AHPR[3:0], AHPL[3:0]
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SYSTEM CLOCK INPUT, OUTPUT, AND fS AUTOMATIC DETECTION
The PCM5310 has six system clock input ports: SCK1, SCK2, SCK3, SCK4, SCK5, and SCK6. Each input port
can receive an independent clock at various frequencies. These ports are used for the internal clock of the digital
filters and delta-sigma modulators, which are combined into a single common audio clock. The PCM5310
automatically detects the input clock rate at 128 fS, 192 fS, 256 fS, 384 fS, 512 fS or 768 fS (where fS is the audio
sampling rate); if necessary, automatic clock rate detection can be disabled. The descriptions for the system
clock input, output, and fS automatic detection registers are shown in Table 3. Table 4 shows the frequency of
the common audio clock. Figure 30 and Table 5 shows the timing requirements for the system clock input.
Table 3. System Clock Input, Output, and fS Automatic Detection Registers
REGISTER DESCRIPTION
Master or slave with fS detection for DAC12
Audio interface format for DAC12
REGISTER NUMBER
REGISTER BITS
DMS12[3:0]
DFM12[1:0]
DMS34[3:0]
DFM34[1:0]
AMS12[3:0]
AFM12[1:0]
AMS34[3:0]
AFM34[1:0]
PSC6[2:0]
44
44
54
54
84
84
94
94
07
Master or slave with fS detection for DAC34
Audio interface format for DAC34
Master or slave with fS detection for ADC12
Audio interface format for ADC12
Master or slave with fS detection for ADC34
Audio interface format for ADC34
SCK6 clock output selection
Table 4. System Clock Frequencies for the Common Audio Clock
SAMPLING
FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY (MHz)
(1)
(1)
128 fS
192 fS
256 fS
8.1920
384 fS
12.2880
512 fS
768 fS
32
44.1
48
4.0960
5.6488
6.1440
8.4672
16.3840
24.5760
11.2896
16.9344
22.5792
33.8688
6.1440
9.2160
12.2880
18.4320
24.5760
36.8640
88.2
96
176.4(1)
192(1)
11.2896
12.2880
22.5792
24.5760
16.9344
18.4320
33.8688
36.8640
22.5792
33.8688
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
24.5760
36.8640
Not supported
Not supported
Not supported
Not supported
(1) This sampling frequency and system clock frequency are supported only for the DAC.
tSCH
High
2.0 V
SCK1 to 6
0.8 V
Low
tSCL
tSCY
Figure 30. System Clock Input Timing
Table 5. Timing Characteristics for Figure 30
PARAMETER
MIN
25
MAX
UNIT
ns
tSCY
tSCH
tSCL
System clock cycle time
System clock high time
System clock low time
System clock duty cycle
0.4 tSCY
0.4 tSCY
40
ns
ns
60
%
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POWER ON/OFF RESET
The power-on reset (POR) circuit generates a reset signal at typically 2.2 V; this circuit does not depend on the
other power supplies: VCCDA, VCCAD, VCCH, and VCCP. The internal circuit is cleared to default status, then all
analog and digital outputs have no signal. It is recommended to turn the device on and off as shown in Figure 31,
in order to avoid loud, audible pop noises when powering the device on or off.
2.2 V Typical
1.6 V Typical
(1.6 V to 2.8 V)
(1.0 V to 2.0 V)
VDD
Power-On Reset
0 s (min)
RSTB
I2C Setting is Effective
I2C Setting
1 ms (min)
Power-Up for ADCs and DACs(1)
SCKx
Clock Input
Clock Input
Clock Input
Internal Reset for
ADCs and DACs
1024 Clocks
(1) RSTB is active low. 100 ns (minimum) is needed for an effective reset to the internal circuit.
Figure 31. Power On/Off Reset
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REGISTER RESET AND SYSTEM RESET (Register 01)
Register reset (MRST) clears all register data to the default setting. The MRST register is automatically set to '1'
after the reset.
System reset (SRST) clears all internal circuits, including all register data, to default status simultaneously. The
SRST register is automatically set to '1' after the reset.
Note that the PCM5310 may have audible pop noises on the analog and digital outputs when enabling MRST
and SRST.
The descriptions for the register reset and system reset registers are shown in Table 6.
Table 6. Reset Registers
REGISTER DESCRIPTION
Reset register data only
REGISTER NUMBER
REGISTER BITS
MRST
01
01
Reset for all circuits including register data
SRST
RSTB Control
Taking RSTB (pin 58) from high to low clears all internal circuits to default status. If an application does not
require reset control, RSTB should be connected with an RC passive delay circuit to the digital power supply
(VDD).
Note that the PCM5310 may have audible pop noises on the analog and digital outputs when enabling RSTB.
The RSTB control status descriptions are shown in Table 6.
Table 7. RSTB Control
RSTB (PIN 58) STATUS
DESCRIPTION
Low
Reset all circuits including register data
Reset release
High
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POWER-SUPPLY SEQUENCE AND POWER ON/OFF SEQUENCE
In order to reduce audible pop noise, a register setting sequence is required after turning on all power supplies
and before turning off all power supplies. Any modules that are not used in the application or system should be
powered down after the recommended power-on sequence. Before the power-off sequence, all modules should
be in a power-on state. The recommended power-supply sequence is shown in Figure 32. The recommended
register settings are shown in Table 8 and Table 9.
VDD, VCCP,
VCCAD, VCCDA
VCCH (9 V)
Recommended
Power-On
Recommended
Power-Off
I2C Register Setting
Analog Output(1)
Sequence
Sequence
Half of
Power-Supply
Voltage
75 ms to 2000 ms(2)
37.5 ms to 1000 ms
Digital Output
(1) Ramp up/down time for the analog output can be changed through the register setting (see Register 18, PDTM[2:0]).
(2) A 1.0-µF capacitor should be connected to the VCOMAD and VCOMDA pins.
Figure 32. Recommended Power On/Off Sequence
Table 8. Recommended Register Settings When Powered On
REGISTER SETTING
STEP
1
ADDRESS
—
DATA
—
DESCRIPTION
Turn on all power supplies
Analog bias power up
2
11
00
3
1F
49
Headphone output L-channel mute disable and level (–42 dB) setting(1)
Headphone output R-channel mute disable and level (–42 dB) setting(1)
Headphone volume update control
4
20
49
5
1E
B0
00
6
1B
Line output gain (0 dB) control from DAC(1)
7
1C
2A
00
Line output 2 VRMS and 2.4 VRMS mode select
8
FF
FF
00
DAC12 L-channel digital attenuation level (0 dB) setting(1)
DAC12 R-channel digital attenuation level (0 dB) setting(1)
DAC12 digital mute setting and digital gain boost
9
2B
10
11
12
13
14
15
16
17
29
28
B1
FF
FF
00
DAC12 digital attenuation/mute control and zero crossing enable
DAC34 L-channel digital attenuation level (0 dB) setting(1)
DAC34 R-channel digital attenuation level (0 dB) setting(1)
DAC34 digital mute setting and digital gain (0 dB) boost
DAC34 digital attenuation/mute control and zero crossing enable
ADC12 L-channel digital attenuation level (0 dB) setting(1)
ADC12 R-channel digital attenuation level (0 dB) setting(1)
34
35
33
32
B1
D5
D5
52
53
(1) Any level is acceptable for volume, gain, and attenuation. The level should be resumed by register data recorded when the system
powers off.
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Table 8. Recommended Register Settings When Powered On (continued)
REGISTER SETTING
STEP
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
ADDRESS
51
DATA
00
DESCRIPTION
ADC12 digital mute disable
50
01
ADC12 digital attenuation/mute control and zero crossing enable
ADC34 L-channel digital attenuation level (0 dB) setting(1)
ADC34 R-channel digital attenuation level (0 dB) setting(1)
ADC34 digital mute disable
5C
5D
5B
D7
D7
00
5A
01
ADC34 digital attenuation/mute control and zero crossing enable
Line output 1 L-/R-channel mux select
18
77
19
00
Line output 2 L-/R-channel mux select
1A
88
Headphone output L-/R-channel mux select
ADC12 analog input mux select (AIN1L/R)(2)
ADC34 analog input mux select (AIN2L/R)(2)
ADC12 analog input gain level (0 dB) setting(1)
14
11
15
22
16
00
17
00
ADC34 analog input gain level (0 dB) setting(1)
65
98
Audio interface (LRCKx/BCKx) PORT-1 and PORT-2 setting (ADC12/34, master)(3)
Audio interface (DATAx) PORT-1 and PORT-2 setting (DATA output of ADC12/34)(3)
Audio interface (SCKx) PORT-1 and PORT-2 setting (input of SCK1/2)(4)
66
98
67
10
Audio interface (LRCKx/BCKx) PORT-3 and PORT-4 setting (input of LRCK3/4,
BCK3/4)(4)
34
68
32
35
36
69
6A
32
32
Audio interface (DATAx) PORT-3 and PORT-4 setting (input of DATA3/4)(4)
Audio interface (SCKx) PORT-3 and PORT-4 setting (input of SCK3/4)(4)
Audio interface (LRCKx/BCKx) PORT-5 and PORT-6 setting (input of LRCK3/4,
BCK3/4)(4)
37
6B
54
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
6C
6D
6E
6F
70
74
75
76
2C
36
54
5E
12
2E
38
55
5F
12
54
54
43
43
43
89
10
76
80
80
40
40
11
00
00
00
00
01
Audio interface (DATAx) PORT-5 and PORT-6 setting (input of DATA5/6)(4)
Audio interface (SCKx) PORT-5 and PORT-6 setting (input of SCK5/6)(4)
DAC12 and DAC34 LRCK/BCK select(4)
DAC12 and DAC34 DATA select(4)
DAC12 and DAC34 SCK select(4)
ADC12 and ADC34 LRCK/BCK select (ADC12/34, master)(4)
ADC12 and ADC34 SCK select(4)
GPIO control or GPIO1 and GPIO2 audio data select
DAC12 audio interface and master/slave select(5)
DAC34 audio interface and master/slave select(5)
ADC12 audio interface and master/slave select (master, 256 fS)(5)
ADC34 audio interface and master/slave select (master, 256 fS)(5)
Analog back-end and front-end power-up
DAC12 power-up
DAC34 power-up
ADC12 power-up
ADC34 power-up
Common voltage (VCOM) power-up and ramp up/down time setting
(2) Any input terminals are acceptable for input of ADC12 and ADC34.
(3) These settings are not required if application does not use audio interface mux and bypass selection.
(4) These settings are not required if application does not use audio interface mux and bypass selection.
(5) These settings are not required if application uses slave mode for audio interface and SCK automatic fS detection.
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Table 9. Recommended Register Setting When Powered Off
REGISTER SETTING
STEP
1
ADDRESS
DATA
00
00
00
00
00
11
80
80
80
80
71
80
—
DESCRIPTION
Line output1 L- and R-channel mux select
18
19
1A
14
15
12
55
5F
2E
38
12
11
—
2
Line output2 L- and R-channel mux select
Headphone output L- and R-channel mux select
ADC12 analog input mux select
ADC34 analog input mux select
Common voltage (VCOM) power-down and ramp up/down time setting
ADC12 power-down
3
4
5
6
7
8
ADC34 power-down
9
DAC12 power-down
10
11
12
13
DAC34 power-down
Analog back-end and front-end power-down
Analog bias power-down
Turn off all power supplies
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AUDIO SERIAL INTERFACE
The PCM5310 has six audio interface ports: SCKx, BCKx, LRCKx, and DATAx (bidirectional). Each port or signal
can be connected to any ADC or DAC. If an audio system application wants to bypass an audio signal, the
PCM5310 can bypass from any port to any port. Refer to Figure 33 for a diagram of the of the audio inteface port
and mux. See Figure 47 to Figure 52 for detailed diagrams of PORT-1 to PORT-6.
The audio interface consists of LRCKs, BCKs, and DATAs. The sampling rate (fS), left channel and right channel
data are present on the LRCKs. The DATAs receive the serial audio data from the interpolation filter for the DAC,
and the DATAs transmit the serial data to the decimation filter. The BCKs are used to receive and transmit the
serial audio data on the DATAs by high-to-low transition. The BCKs and LRCKs should be synchronized with the
system clocks, SCKs. The PCM5310 operates with the LRCKs/BCKs synchronized with the SCKs; however, the
PCM5310 does not need a specific phase between the BCKs/LRCKs and the SCKs. Each audio interface port
can select either the master or slave mode, and generate the LRCKs and BCKs from the SCKs in master mode.
The descriptions for the audio serial interface registers are shown in Table 6.
Table 10. Audio Serial Interface Registers
REGISTER DESCRIPTION
Master or slave with fS detection for DAC12
Audio interface format for DAC12
REGISTER NUMBER
REGISTER BITS
DMS12[3:0]
44
44
DFM12[1:0]
Master or slave with fS detection for DAC34
Audio interface format for DAC34
54
DMS34[3:0]
54
DFM34[1:0]
Master or slave with fS detection for ADC12
Audio interface format for ADC12
84
AMS12[3:0]
84
AFM12[1:0]
Master or slave with fS detection for ADC34
Audio interface format for ADC34
94
AMS34[3:0]
94
AFM34[1:0]
LRCK/BCK selection of PORT-1 and PORT-2
DATA selection of PORT-1 and PORT-2
SCK selection of PORT-1 and PORT-2
LRCK/BCK selection of PORT-3 and PORT-4
DATA selection of PORT-3 and PORT-4
SCK selection of PORT-3 and PORT-4
LRCK/BCK selection of PORT-5 and PORT-6
DATA selection of PORT-5 and PORT-6
SCK selection of PORT-5 and PORT-6
LRCK/BCK selection of DAC12 and DAC34
DATA selection of DAC12 and DAC34
SCK selection of DAC12 and DAC34
LRCK/BCK selection of ADC12 and ADC34
SCK selection of ADC12 and ADC34
GPIO-1 and GPIO-2 audio data selection
101
102
103
104
105
106
107
108
109
110
111
112
116
117
118
LBS2[3:0], LBS1[3:0]
DTS2[3:0], DTS1[3:0]
SCS2[2:0], SCS1[2:0]
LBS4[3:0], LBS3[3:0]
DTS4[3:0], DTS3[3:0]
SCS4[2:0], SCS3[2:0]
LBS6[3:0], LBS5[3:0]
DTS6[3:0], DTS5[3:0]
SCS6[2:0], SCS5[2:0]
D34LB[3:0], D12LB[3:0]
D34DT[3:0], D12DT[3:0]
D34S[2:0], D12S[2:0]
A34LB[3:0], A12LB[3:0]
A34SC[2:0], A12SC[2:0]
GP2S[3:0], GP1S[3:0]
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LRCK1
BCK1
DATA from ADC12
LRCK, BCK at Master
BCK/LRCK
Master
PORT-1
DATA1
SCK1
LRCK, BCK, DATA, SCK from PORT-1
LRCK, BCK, DATA, SCK from PORT-2
LRCK, BCK, DATA, SCK from PORT-3
LRCK, BCK, DATA, SCK from PORT-4
LRCK, BCK, DATA, SCK from PORT-5
LRCK, BCK, DATA, SCK from PORT-6
LRCK, BCK, SCK for ADC12
ADC12
Reg 116 A12LB[3:0]
Reg 117 A12S[2:0]
LRCK2
BCK2
PORT-2
PORT-3
PORT-4
PORT-5
DATA2
SCK2
DATA from ADC34
LRCK, BCK at Master
BCK/LRCK
Master
LRCK3
BCK3
LRCK, BCK, SCK for ADC34
ADC34
Reg 116 A34LB[3:0]
Reg 117 A34S[2:0]
DATA3
SCK3
LRCK4
BCK4
DATA4
SCK4
LRCK, BCK at Master
BCK/LRCK
Master
LRCK, BCK, SCK for DAC12
DAC12
LRCK5
BCK5
Reg 110 D12LB[3:0]
Reg 111 D12DT[3:0]
Reg 112 D12S[2:0]
DATA5
SCK5
LRCK, BCK at Master
BCK/LRCK
Master
LRCK6
BCK6
LRCK, BCK, SCK for DAC34
DAC34
PORT-6
Reg 110 D34LB[3:0]
Reg 111 D34DT[3:0]
Reg 112 D34S[2:0]
DATA6
SCK6
DATA for DAC12/34 from GPIO1 and GPIO2
DATA for ADC12/34 to GPIO1 and GPIO2
To
Register
Mapping
GPIO1
GPIO2
GPIO1
GPIO2
Figure 33. Audio Interface Port and Mux
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AUDIO DATA FORMATS AND TIMING
The PCM5310 supports I2S, left-justified, and right-justified data formats with 32 fS, 48 fS, or 64 fS BCK rates for
digital input, and 48 fS or 64 fS BCK rates for the ADC. The data formats are shown in Figure 34 and can be
selected through the I2C interface. All formats require binary twos complement, MSB first audio data. The default
format is 16- to 24-bits I2S. Figure 35 and Figure 36 show detailed timing diagrams. The descriptions for the
audio interface data format registers are shown in Table 11.
Table 11. Audio Interface Data Format Registers
REGISTER DESCRIPTION
Audio interface format for DAC12
REGISTER NUMBER
REGISTER BITS
DFM12[1:0]
DFM34[1:0]
AFM12[1:0]
44
54
84
94
Audio interface format for DAC34
Audio interface format for ADC12
Audio interface format for ADC34
AFM34[1:0]
(a) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
R-Channel
LRCK
L-Channel
BCK
(= 32 fS, 48 fS, or 64 fS)
DATA
MSB
LSB
MSB
LSB
(b) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 32 fS, 48 fS, or 64 fS)
DATA
MSB
LSB
MSB
LSB
(c) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 32 fS, 48 fS, or 64 fS)
DATA
MSB
LSB
MSB
LSB
Figure 34. Audio Data Input and Output Formats
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tBCH
tBCL
BCKx
(Input)
1.4 V
1.4 V
tBCY
tLRH
tLRS
LRCKx
(Input)
tDOD
DATAx(1)
(Output Mode)
0.5 VDD
tDIS
tDIH
DATAx
(Input Mode)
1.4 V
(1) Load capacitance of output is 20 pF.
Figure 35. Audio Interface Timing (Slave Mode)
Table 12. Timing Requirements for Figure 35
PARAMETER
MIN
75
35
35
15
10
10
10
0
MAX
UNIT
tBCY
tBCH
tBCL
tLRS
tLRH
tDIS
BCKx cycle time
ns
ns
ns
ns
ns
ns
ns
ns
BCKx pulse width high
BCKx pulse width low
LRCKx set-up time to BCKx rising edge
LRCKx hold time to BCKx rising edge
DATAx setup time to BCKx rising edge
DATAx hold time to BCKx rising edge
DATAx delay time from BCKx falling edge
tDIH
tDOD
30
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tBCH
tBCL
BCKx
(Output)
0.5 VDD
tBCY
tLRD
LRCKx
(Output)
0.5 VDD
tDOD
DATAx(1)
(Output Mode)
0.5 VDD
tDIS
tDIH
DATAx
(Input Mode)
1.4 V
(1) Load capacitance of output is 20 pF.
Figure 36. Audio Interface Timing (Master Mode)
Table 13. Timing Requirements for Figure 36
PARAMETER
MIN
TYP
MAX
UNIT
tBCY
tBCH
tBCL
tLRD
tDIS
BCKx cycle time
1/(64 fS)
0.5 tBCY
0.5 tBCY
BCKx pulse width high
0.4 tBCY
0.4 tBCY
–15
0.6 tBCY
0.6 tBCY
20
BCKx pulse width low
LRCKx delay time from BCKx falling edge
DATAx setup time to BCKx rising edge
DATAx hold time to BCKx rising edge
DATAx delay time from BCKx falling edge
ns
ns
ns
ns
10
tDIH
10
tDOD
–10
20
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ADC AND FILTER
The analog-to-digital converter (ADC) and digital filter include a delta-sigma modulator, decimation filter,
high-pass filter (HPF), digital gain control, digital attenuation control, and digital soft mute, as shown in Figure 37.
The HPF eliminates dc offset of the ADC analog section with 0.91 Hz as the cutoff frequency at a 48-kHz
sampling rate. The digital gain or attenuation control can be adjusted from 20 dB to –100 dB in 0.5-dB steps. The
descriptions for the ADC and filter registers are shown in Table 14.
PGA-AD1L
Decimation
Filter
ATT
ADC-1L
ADC-1R
ADC-2L
ADC-2R
HPF
HPF
HPF
HPF
MUTE
PGA-AD1R
PGA-AD2L
PGA-AD2R
Decimation
Filter
ATT
MUTE
Decimation
Filter
ATT
MUTE
Decimation
Filter
ATT
MUTE
Figure 37. ADCs and Filters
Table 14. ADC and Filter Registers
REGISTER DESCRIPTION
REGISTER NUMBER
REGISTER BITS
Digital attenuation and gain update control for ADC12
Digital soft mute setting for ADC12
80
81
A12E, AUC2, AUC1, AZ12
AMU2, AMU1
Digital attenuation and gain level setting for ADC12
High-pass filter disable for ADC12
82, 83
84
AAT2[7:0], AAT1[7:0]
HF12
Digital attenuation and gain update control for ADC34
Digital soft mute setting for ADC34
90
A34E, AUC4, AUC3, AZ34
AMU4, AMU3
91
Digital attenuation and gain level setting for ADC34
High-pass filter disable for ADC34
92, 93
94
AAT4[7:0], AAT3[7:0]
HF34
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DAC AND FILTER
The digital-to-analog converter (DAC) and digital filter include a delta-sigma modulator, interpolation filter,
de-emphasis filter (DEM), digital gain control, digital attenuation control, digital soft mute, and digital gain boost,
as shown in Figure 38. The digital gain or attenuation control can be adjusted from 20 dB to –100 dB in 0.5-dB
steps. To play back low-volume recorded audio data, the digital gain can be used with a boost of either 6 dB,
12 dB, or 18 dB selected through the I2C interface. The descriptions for the DAC and filter registers are shown in
Table 14.
ATT
MUTE
GAIN
Interpolation
DEM
DEM
DEM
DEM
DAC-1L
DAC-1R
DAC-2L
DAC-2R
Filter
ATT
MUTE
GAIN
Interpolation
Filter
ATT
MUTE
GAIN
Interpolation
Filter
ATT
MUTE
GAIN
Interpolation
Filter
Figure 38. DACs and Filters
Table 15. DAC and Filter Registers
REGISTER DESCRIPTION
REGISTER NUMBER
REGISTER BITS
D12E, DUC2, DUC1, DZ12
DMU2, DMU1, DB12[1:0]
DAT2[7:0], DAT1[7:0]
DM12, DF12[1:0]
Digital attenuation and gain update control for DAC12
Digital soft mute and boost setting for DAC12
Digital attenuation and gain level setting for DAC12
De-emphasis filter setting for DAC12
40
41
42, 43
45
Digital attenuation and gain update control for DAC34
Digital soft mute setting for DAC34
50
D34E, DUC4, DUC3, DZ34
DMU4, DMU3
51
Digital attenuation and gain level setting for DAC34
De-emphasis filter setting for DAC34
52, 53
55
DAT4[7:0], DAT3[7:0]
DM34, DF34[1:0]
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GPIO CONTROL
The PCM5310 has three general-purpose input/output (GPIO) pins (pins 55, 56, and 57) that can be assigned to
various functions and internal status reads shown in Table 16, Table 17, Table 18, and Figure 39.
Table 16. GPIO Control Registers
REGISTER DESCRIPTION
GPIO1 select, bypass PORT-4
REGISTER NUMBER
REGISTER BITS
GBP4, GSL1[4:0]
GBP5, GSL2[4:0]
GSL3[4:0]
09
10
11
GPIO2 select, bypass PORT-5
GPIO3 select
Table 17. Register Data Read Through the GPIO Pins
REGISTER DESCRIPTION
REGISTER NUMBER
REGISTER BITS
External device control
08
16
GPO3, GPO2, GPO1
SSHR, SSHL
Headphone short-circuit protection status
Headphone insertion detect status
35
RHPI
Mute status for headphone
35
RHMUR, RHMUL
System clock fS detect for DAC12, DAC34
System clock fS detect for ADC12, ADC34
Digital mute status for DAC12 and DAC34
Digital mute status for ADC12 and ADC34
Zero crossing timeout for DAC12 and DAC34
Zero crossing timeout for ADC12 and ADC34
Zero crossing timeout for headphone
35, 36
37, 38
36
RD12FS[2:0], RD34[2:0]
RA12FS[2:0], RA34[2:0]
RDM4, RDM3, RDM2, RDM1
RAM4, RAM3, RAM2, RAM1
RDZ4, RDZ3, RDZ2, RDZ1
RAZ4, RAZ3, RAZ2, RAZ1
RHZR, RHZL
37
38
39
39
Table 18. Other GPIO Pin Functions
GPIO PIN FUNCTION
Zero flag for digital input
Logic
DESCRIPTION
Read the status for each DAC channel or all DAC channels
OR, AND, NOR, NAND, buffer, inverter
Audio data
Bypass audio data to PORT-4 and PORT-5 from GPIO pins
GPIO1
GPIO2
HP Insertion
HP Protection
Zero Flag
GPIO1
GPIO2
GPIO3
GPIO
Control
Register Out
Logic In/Out
Connect to Port
GPIO3
Figure 39. GPIO Control
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HEADPHONE SHORT-CIRCUIT PROTECTION
The PCM5310 has short-circuit protection for each headphone output. The short-circuit status can be read from
the GPIO pins and the register data can be read through the I2C interface. The short-circuit detection time can be
internally adjusted to avoid the headphone amplifier shutting down when inserting or removing the headphone
jack. The descriptions for the headphone and short-circuit protection registers are shown in Table 19. The
headphone short-circuit protection sequence is shown in Figure 40.
Table 19. Headphone Short-Circuit Protection Registers
REGISTER DESCRIPTION
REGISTER NUMBER
REGISTER BITS
SRCR, SHCR, SPDR, SRCL, SHCL, SPDL
SDTR[1:0], SDTL[1:0]
Headphone short-circuit protection enable/disable
Headphone short-cicuit protection detect time
Headphone short-circuit protection release time
Headphone short-circuit protection status read
13
14
15
16
SRTR[1:0], SRTL[1:0]
SSHR, SSHL
Headphone
Amplifier
HPOL or HPOR
Headphone Jack
Protection Resistor
Current
Monitor
Enable/Disable
Headphone
16W or 32W
Increment
or
Internal Clock
Decrement
Counter
Detect/Release Time
4096 fS: 85.2 ms at fS = 48 kHz
8192 fS: 1704 ms at fS = 48 kHz
16384 fS: 340.8 ms at fS = 48 kHz
32768 fS: 681.6 ms at fS = 48 kHz
Short
or Not
Internal Resistor
GPIO
Control
GPIO1, GPIO2, or GPIO3
Figure 40. Headphone Short-Circuit Protection Sequence
When the short-circuit protection is enabled, it is recommended to insert a small protection resistor to limit
over-current flow. Table 20 shows the headphone output power with a small resistor.
Table 20. Headphone Amplifier Output Power Load
RL = 32 Ω + PROTECTION RESISTOR
32 Ω + 4 Ω
28 mW
32 Ω + 8 Ω
22 mW
32 Ω + 16 Ω
16 mW
0.1% THD
10% THD
37 mW
31 mW
22 mW
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HEADPHONE INSERTION DETECTION
The descriptions for the headphone insertion detection registers are shown in Table 21. The PCM5310 detects
the insertion status of a headphone plug using the GPIO pins through the register setting and writes the status to
the register, which can be read by the I2C interface. The status can also output to the GPIO pins, as shown in
Figure 41.
Table 21. Headphone Insertion Detection Registers
REGISTER DESCRIPTION
GPIO1 selection
REGISTER NUMBER
REGISTER BITS
GSL1[4:0]
GSL2[4:0]
GSL3[4:0]
RIPI
09
10
11
35
GPIO2 selection
GPIO3 selection
Read status for headphone insertion
SDA
SCL
I2C
Register
DSP
VDD
GPIO
Control
GPIO1, GPIO2, or GPIO3
Headphone
Jack
Headphone
Amplifier
HPOR
HPOL
PGND
Figure 41. Headphone Insertion Detection
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ZERO FLAG DETECTION
The PCM5310 detects continuous zero data input to either DAC12, DAC34, or both DAC12 and DAC34. The
GPIO pins can output the status to an external device by the register setting. The flag changes from low to high
when the L-and R-channel data are zero after 1024 fS. The descriptions for the zero flag detection registers are
shown in Table 22. Figure 42 shows the zero flag detection operation.
Table 22. Zero Flag Registers
REGISTER DESCRIPTION
GPIO1 selection
REGISTER NUMBER
REGISTER BITS
GSL1[4:0]
09
10
11
GPIO2 selection
GPIO3 selection
GSL2[4:0]
GSL3[4:0]
LRCK4
BCK4
PORT-4
PORT-5
DAC12
DATA4
LRCK5
BCK5
DAC34
DATA5
Zero Data
or Not
Zero Data
or Not
Increment
Counter
Increment
Counter
GPIO1
GPIO2
GPIO3
GPIO Control
Figure 42. Zero Flag Detection
AMUTE Control
The PCM5310 has an AMUTE pin (pin 59) that controls the digital and analog mute function linked to Register 19
(13h). If these settings are disabled and the AMUTE pin goes from low to high, the PCM5310 holds the digital
and analog mute disabled. If these settings are enabled and the AMUTE pin goes from low to high, the
PCM5310 enables digital and analog mute. The mute function set by the AMUTE pin is effective, regardless of
the setting in Register 19.
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MUTE CONTROL TIMING DURING CLOCK CHANGES
The PCM5310 has six audio interface ports and can change from the current source to another source. However,
the analog output or digital output may have an audible pop noise when changing or stopping clocks. It is
recommend to use the mute control with zero data input and waiting time to avoid pop noise and clean up the
internal circuit via I2C. Figure 43 illustrates the details.
Note that the digital and analog inputs should be zero data initially. After that, use the following steps:
1. Disable zero crossing detection.
2. Enable the analog or digital output mute.
3. Change the clock source.
4. Disable the analog or digital mute.
Clock Source A
Clock Source B
241(1) 8 fS(ADC)
1 fS (DAC)
35 fS(ADC)
25 fS (DAC)
I2C Setting
NOTE:
The digital and analog inputs should be zero data at first. Then use the following setting procedure:
a) Disable zero crossing detection.
b) Enable analog or digital output mute.
c) Change the clock source.
d) Disable the analog or digital mute.
(1) Value depends on attenuation level setting in Registers 82, 83, 92, and 93.
Figure 43. Mute Control Timing During Clock Changes
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ANALOG MUX CHANGING TO REDUCE AUDIBLE NOISE
The PCM5310 has an analog multiplexer (mux) that can select six stereo analog inputs. The ADC output may
have audible noise when selecting without mute control via I2C. It is recommend to use digital soft mute before
changing the analog input, as shown in Figure 44.
AIN1L
AIN2L
I2C Setting
(1)
(2)
(3)
ADC Output
(4)
(4)
(1) Enable digital soft mute of ADC.
(2) Change analog input source.
(3) Disable digital soft mute of ADC.
(4) Maximum mute time is [241 × 8 fS] seconds; however, this time depends on the wave form if zero crossing is
enabled. It is recommended to read the status of this mute from Register 35 to 39 via I2C. Then if the status is high,
disable mute.
Figure 44. Analog Mux Changing to Reduce Audible Noise
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TWO-WIRE INTERFACE (I2C)
The PCM5310 supports the I2C serial bus and the data transmission protocol for the I2C standard as a slave
device. This protocol is explained in the I2C specification 2.0.
In I2C mode, the control terminals are changed as shown in Table 23.
Table 23. Control Pins
PIN NAME
SDA
INPUT/OUTPUT
Input/Output
Input
DESCRIPTION
I2C data
SCL
I2C clock
Slave Address
The PCM5310 has its own 7-bit slave address, as shown in Table 24. The first six bits (MSBs) of the slave
address are factory preset to '1000110'. The last bit of the address byte is the device select bit, which can be
user-defined by the ADR terminal. A maximum of two PCM5310s can be connected on the same bus
simultaneously. Each PCM5310 responds when it receives its own slave address.
Table 24. Slave Address
MSB
1
LSB
R/W
0
0
0
1
1
0
Packet Protocol
The master device must control packet protocol, which consists of a start condition, a slave address with
read/write (R/W) bit, data (if write) or acknowledgement (if read), and a stop condition, as shown in Figure 45.
The PCM5310 supports only a slave receiver and slave transmitter. Table 25 shows a basic I2C write operation.
Table 26 shows a basic I2C read operation.
Start
Condition
Stop
Condition
SDA
SCL St
1-7
8
9
1-8
9
1-8
9
Sp
Slave Address
R/W
ACK
DATA
ACK
DATA
ACK
R/W: Read operation if ‘1’; otherwise, write operation.
ACK: Acknowledgement of a byte if ‘0’.
DATA: 8 bits (1 byte).
Figure 45. Basic I2C Framework
Table 25. Basic I2C Write Operation
TRANSMITTER
DATA TYPE
M
M
M
S
M
S
M
S
M
Slave
address
St
R/W
ACK
DATA
ACK
DATA
ACK
Sp
LEGEND: M = master device, S = slave device, St = START condition, Sp = STOP condition, R/W = read/write, ACK = acknowledge.
Table 26. Basic I2C Read Operation
TRANSMITTER
DATA TYPE
M
M
M
S
M
S
M
S
M
Slave
address
St
R/W
ACK
DATA
NACK
DATA
NACK
Sp
LEGEND: M = master device, S = slave device, St = START condition, Sp = STOP condition, R/W = read/write, ACK = acknowledge,
NACK = not acknowledge.
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Write Operation
The master can write to any PCM5310 register in a single access. The master sends a PCM5310 slave address
with a write bit, a register address, and data. When undefined registers are accessed, the PCM5310 does not
send any acknowledgement. Table 27 shows the framework for a write operation.
Table 27. Framework for Write Operation
TRANSMITTER
DATA TYPE
M
M
M
S
M
S
M
S
M
Slave
address
Register
address
St
W
ACK
ACK
Write data
ACK
Sp
LEGEND: M = master device, S = slave device, St = start condition, Sp = stop condition, W = write, ACK = acknowledge.
Read Operation
The master can read any PCM5310 register. The value of the register address is stored in an indirect index
register in advance. The master sends the PCM5310 slave address with a read bit after storing the register
address. The PCM5310 then transfers the data to the address specified by the index register. Table 28 shows
the framework for a read operation.
Table 28. Framework for Read Operation
TRANSMITTER
DATA TYPE
M
M
M
S
M
S
M
M
M
R
S
S
M
M
Slave
address
Register
address
Slave
address
Read
data
St
W
ACK
ACK
Sr
ACK
NACK
Sp
LEGEND: M = master device, S = slave device, St = START condition, Sr = repeated START condition, Sp = STOP condition,
W = write, R = read, ACK = acknowledge, NACK = not acknowledge.
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I2CTiming Diagram
Start
Condition
Stop
Condition
t(BUF)
t(D-SU)
t(D-HD)
t(SDA-R)
t(SDA-F)
t(P-SU)
SDA
SCL
t(LOW)
t(SCL-R)
t(RS-HD)
t(SP)
t(S-HD)
t(HI)
t(RS-SU)
t(SCL-F)
Figure 46. I2C Timing
Table 29. Timing Characteristics for Figure 46
PARAMETER
I2C SPECIFICATION
Standard
MIN
MAX
UNIT
fSCL
t(BUF)
t(LOW)
t(HI)
SCL clock frequency
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
Bus free time between STOP and START condition
SCL clock low period
Standard
4.7
Standard
4.7
SCL clock high period
Standard
4
t(RS-SU)
t(S-HD)
t(D-SU)
t(D-HD)
t(SCL-R)
START condition setup time
START condition hold time
Data setup time
Standard
4.7
Standard
4
Standard
250
0
Data hold time
Standard
900
SCL signal rise time
Standard
20 + 0.1 CB
1000
Rise time of SCL signal after a repeated START
condition and after an acknowledge bit
t(SCL-R1)
Standard
20 + 0.1 CB
1000
ns
t(SCL-F)
t(SDA-R)
t(SDA-F)
t(P-SU)
CB
SCL signal fall time
Standard
Standard
Standard
Standard
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
4
1000
1000
1000
ns
ns
ns
µs
pF
ns
SDA signal rise time
SDA signal fall time
STOP condition setup time
Capacitive load for SDA and SCL line
Suppressed spike pulse duration
400
25
t(SP)
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REGISTER MAP
The mode control register map is shown in Table 30. Each register includes an index (or address) indicated by
the IDX[6:0] bits.
Table 30. Mode Control Register Map
REG HEX
DESCRIPTION
Reset function
B7
B6
B5
B4
B3
B2
B1
B0
01
08
09
10
11
12
13
14
01h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
MRST SRST RSV(1)
RSV
RSV
RSV
RSV
RSV
RSV
GPIO pin output control
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV GPO3 GPO2 GPO1
GSL1[4:0]
GPIO PORT-1 selection
GPIO PORT-2 selection
GSL2[4:0]
GPIO PORT-3 selection
GSL3[4:0]
Not assigned
RSV
RSV
RSV
RSV
RSV
Headphone short-circuit protection enable/disable
Headphone short-circuit protection detect time
RSV SRCR SHCR SPDR RSV SRCL SHCL SPDL
RSV
RSV
SDTR[1:0]
RSV
RSV
SDTL[1:0]
Headphone short-circuit protection release time, auto
control
15
0Fh
RSV SADR
SRTR[1:0]
RSV SADL
SRTL[1:0]
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
Headphone short-circuit protection status read
Power up/down (bias)
RSV
RSV
RSV
RSV
RSV
SSHR RSV
RSV RSV
RSV
RSV SSHL
PBIS
PDCF[1:0]
PDTM[2:0]
MD12 MD34 MHPR MHPL ML2R ML2L ML1R ML1L
PDCS
Power up/down (analog), power up/down time
Mute control linked to AMUTE pin
RSV PABE PAFE PCOM RSV
Analog input mux selection for ADC12
Analog input mux selection for ADC34
Analog input gain control for ADC12
Analog input gain control for ADC12
Analog output mux selection for line output 1
Analog output mux selection for line output 2
Analog output mux selection for headphone output
Gain control for line output
RSV
RSV
RSV
RSV
AX1R[2:0]
AX2R[2:0]
RSV
RSV
RSV
RSV
AX1L[2:0]
AX2L[2:0]
RSV
RSV
AG1R[1:0]
AG2R[1:0]
RSV
RSV
AG1L[1:0]
AG2L[1:0]
AL1R[3:0]
AL1L[3:0]
AL2R[3:0]
AHPR[3:0]
AL2L[3:0]
AHPL[3:0]
GL2R[1:0]
GL2L[1:0]
GL1R[1:0]
GL1L[1:0]
RSV G241
RSV ACTH CHDE
RSV RSV HZRS
2.0 VRMS and 2.4 VRMS selection for line output
Clock halt detection control
RSV
RSV
RSV
RSV
RSV
RSV
G242
RSV
RSV
RSV
RSV
Headphone output volume control
HUPE RSV
HSUR HSUL RSV
Headphone mute and volume level setting for
R-channel
31
32
1Fh
20h
HMUL
HVOL[6:0]
Headphone mute and volume level setting for
L-channel
HMUR
HVOR[6:0]
33
34
35
36
37
38
39
40
41
42
43
44
45
46
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
System clock output disable
LRCK and BCK output disable at master mode
Read internal flag
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SC6D SC5D SC4D RSV SC2D SC1D
LB6D
LB5D LB4D LB3D LB2D LB1D
RHMR RHML RSV RHPI
RD12FS[2:0]
RD34FS[2:0]
RA12FS[2:0]
RA34FS[2:0]
Read internal flag
RDM4 RDM3 RDM2 RDM1
RAM4 RAM3 RAM2 RAM1
RDZ4 RDZ3 RDZ2 RDZ1
Read internal flag
Read internal flag
Read internal flag
CGLD RSV
D12E RSV
RHZR RHZL RAZ4 RAZ3 RAZ2 RAZ1
Digital attenuation and mute control for DAC12
Digital gain boost and digital soft mute for DAC12
Digital attenuation level setting for DAC12 L-channel
Digital attenuation level setting for DAC12 R-channel
Master/slave interface format for DAC12
De-emphasis filter control for DAC12
DUC2 DUC1 RSV
RSV RSV
RSV
RSV
DZ12
RSV
RSV
DB12[1:0]
DMU2 DMU1
DAT1[7:0]
DAT2[7:0]
DMS12[3:0]
RSV RSV
OV12[1:0]
RSV
RSV
DFM12[1:0]
DF12[1:0]
RSV
RSV DM12 RSV
ZR12 RSV
Power up/down, oversampling rate control for DAC12 PD12 RSV
RSV
RSV
(1) RSV = reserved (write '0' data).
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Table 30. Mode Control Register Map (continued)
REG HEX
DESCRIPTION
B7
B6
B5
DUC4 DUC3 RSV
RSV RSV
B4
B3
B2
B1
B0
50
51
32h
33h
34h
35h
36h
37h
38h
50h
51h
52h
53h
54h
55h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
Digital attenuation and mute control for DAC34
Digital gain boost and digital soft mute for DAC34
Digital attenuation level setting for DAC34 L-channel
Digital attenuation level setting for DAC34 R-channel
Master/slave interface format for DAC34
D34E RSV
RSV
RSV
DZ34
RSV
RSV
DB34[1:0]
DMU4 DMU3
52
DAT3[7:0]
DAT4[7:0]
53
54
DMS34[3:0]
RSV RSV
OV34[1:0]
AUC2 AUC1 RSV
RSV RSV RSV
RSV
RSV
DFM34[1:0]
DF34[1:0]
55
De-emphasis filter control for DAC34
RSV
RSV DM34 RSV
56
Power up/down, oversampling rate control for DAC34 PD34 RSV
ZR34
RSV
RSV
RSV
RSV
RSV
80
Digital attenuation and mute control for ADC12
Digital soft mute for ADC12
A12E
RSV
RSV
AZ12
81
FS12
RSV AMU2 AMU1
82
Digital attenuation level setting for ADC12 L-channel
Digital attenuation level setting for ADC12 R-channel
Master/slave interface format for ADC12
Power up/down for ADC12
AAT1[7:0]
AAT2[7:0]
83
84
AMS12[3:0]
RSV RSV
AUC4 AUC3 RSV
RSV RSV RSV
HF12
RSV
RSV
RSV
AFM12[1:0]
85
PA12
A34E
RSV
RSV
RSV
RSV
RSV
RSV
90
Digital attenuation and mute control for ADC34
Digital soft mute for ADC34
RSV
AZ34
91
FS34
RSV AMU4 AMU3
92
Digital attenuation level setting for ADC34 L-channel
Digital attenuation level setting for ADC34 R-channel
Master/slave, interface format for ADC34
Power up/down for ADC34
AAT3[7:0]
AAT4[7:0]
93
94
AMS34[3:0]
RSV RSV
LBS2[3:0]
DTS2[3:0]
SCS2[2:0]
HF34
RSV
RSV
AFM34[1:0]
95
PA34
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
LRCK/BCK selection of PORT-1 and PORT-2
DATA selection of PORT-1 and PORT-2
SCK selection of PORT-1 and PORT-2
LRCK/BCK selection of PORT-3 and PORT-4
DATA selection of PORT-3 and PORT-4
SCK selection of PORT-3 and PORT-4
LRCK/BCK selection of PORT-5 and PORT-6
DATA selection of PORT-5 and PORT-6
SCK selection of PORT-5 and PORT-6
LRCK/BCK selection of DAC12 and DAC34
DATA selection of DAC12 and DAC34
SCK selection of DAC12 and DAC34
Not assigned
LBS1[3:0]
DTS1[3:0]
SCS1[2:0]
LBS4[3:0]
DTS4[3:0]
LBS3[3:0]
DTS3[3:0]
SCS4[2:0]
SCS3[2:0]
LBS6[3:0]
DTS6[3:0]
LBS5[3:0]
DTS5[3:0]
SCS6[2:0]
SCS5[2:0]
D34LB[3:0]
D34DT[3:0]
D12LB[3:0]
D12DT[3:0]
RSV
RSV
RSV
RSV
D34S[2:0]
RSV
RSV
RSV
RSV
D12S[2:0]
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Not assigned
RSV
RSV
Not assigned
LRCK/BCK selection of ADC12 and ADC34
SCK selection of ADC12 and ADC34
GPIO1 and GPIO2 audio data selection
A34LB[3:0]
A34SC[2:0]
GP2S[3:0]
A12LB[3:0]
A12SC[2:0]
GP1S[3:0]
RSV
RSV
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REGISTER DESCRIPTIONS
Register 01 (01h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
01
01h
Reset function
MRST SRST RSV
RSV
RSV
RSV
RSV
RSV
MRST: Reset of All Registers Except for Other Internal Circuit
This bit enables the reset signal for register data only. All registers are initialized to default data by setting
MRST = '0'. After the reset sequence completes, MRST is automatically set to '1'.
Defalut value: 1
0
1
Reset (set to '0' automatically after set to '1')
Not reset (default)
SRST: Reset of All Internal Circuits Including All Registers
This bit enables the internal system reset. All circuits including the registers are initialized by setting SRST = '0'.
After completing the reset sequence, SRST is automatically set to '1'.
Defalut value: 1
0
1
Reset (set to '0' automatically after set to '1')
Not reset (default)
Register 08 (08h)
REG
08
HEX
08h
2Ah
DESCRIPTION
GPIO pin output control
B7
B6
B5
B4
B3
B2
B1
B0
RSV
RSV
RSV
RSV
RSV GPO3 GPO2 GPO1
42
Digital attenuation level setting for DAC12 L-channel
DAT1[7:0]
GPO1: General-Purpose Output (pin 55)
GPO2: General-Purpose Output (pin 56)
GPO3: General-Purpose Output (pin 57)
These three bits control the three GPIO pins that control external devices. These register data are effective by
setting '01000', '01001', or '01010' to bits GSL1[4:0], GSL2[4:0] and GSL[4:0] of registers 9 to 11.
Default value: 0
0
1
Low level output (default)
High level output
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Registers 09-12 (09h-0Ch)
REG
09
HEX
09h
0Ah
0Bh
0Ch
DESCRIPTION
GPIO PORT-1 selection
GPIO PORT-2 selection
GPIO PORT-3 selection
Not assigned
B7
B6
B5
B4
B3
B2
B1
B0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
GSL1[4:0]
GSL2[4:0]
GSL3[4:0]
RSV
10
11
12
RSV
RSV
RSV
RSV
GSL1[4:0]: GPO1 Function Selection (pin 55)
GSL2[4:0]: GPO2 Function Selection (pin 56)
GSL3[4:0]: GPO3 Function Selection (pin 57)
The three GPIO pins can be used as an input flag, output flag, and logic function, as shown in Table 31.
Default value: 00000
Table 31. GPIO Functions
GSL1-3[4:0]
00000
GSL1[4:0]/GPIO1
GSL2[4:0]/GPIO2
GSL3[4:0]/GPIO3
No assigned and input mode (default)
Headphone insertion detection input
Headphone insertion detection output
Headphone short detection status L-channel
Headphone short detection status R-channel
Zero flag output for digital input (DAC12)
Zero flag output for digital input (DAC34)
No assigned and input mode (default)
Headphone insertion detection input
Headphone insertion detection output
Headphone short detection status L-channel
Headphone short detection status R-channel
Zero flag output for digital input (DAC12)
Zero flag output for digital input (DAC34)
No assigned and input mode (default)
Headphone insertion detection input
Headphone insertion detection output
00001
00010
00011
Headphone short detection status L-channel
Headphone short detection status R-channel
Zero flag output for digital input (DAC12)
Zero flag output for digital input (DAC34)
00100
00101
00110
00111
Zero flag output for digital input (DAC12 and
DAC34)
Zero flag output for digital input (DAC12 and
DAC34)
Zero flag output for digital input (DAC12 and
DAC34)
01000
01001
01010
01011
01100
Output register data to GPIO1 pin
Output register data to GPIO2 pin
Output register data to GPIO3 pin
AND logic (GPIO1 = output, GPIO2,3 = input)
Output register data to GPIO1 pin
Output register data to GPIO2 pin
Output register data to GPIO3 pin
AND logic (GPIO2 = output, GPIO1,3 = input)
Output register data to GPIO1 pin
Output register data to GPIO2 pin
Output register data to GPIO3 pin
AND logic (GPIO2 = output, GPIO1,3 = input)
NAND logic (GPIO1 = output, GPIO2,3 =
input)
NAND logic (GPIO2 = output, GPIO1,3 =
input)
NAND logic (GPIO2 = output, GPIO1,3 =
input)
01101
01110
01111
10000
10001
10010
Others
OR logic (GPIO1 = output, GPIO2,3 = input)
OR logic (GPIO2 = output, GPIO1,3 = input)
OR logic (GPIO2 = output, GPIO1,3 = input)
NOR logic (GPIO1 = output, GPIO2,3 = input) NOR logic (GPIO2 = output, GPIO1,3 = input) NOR logic (GPIO2 = output, GPIO1,3 = input)
Buffer logic (GPIO1 = output, GPIO2 = input)
Buffer logic (GPIO1 = output, GPIO3 = input)
Buffer logic (GPIO2 = output, GPIO1 = input)
Buffer logic (GPIO2 = output, GPIO3 = input)
Buffer logic (GPIO2 = output, GPIO1 = input)
Buffer logic (GPIO2 = output, GPIO3 = input)
Inverter logic (GPIO1 = output, GPIO2 = input) Inverter logic (GPIO2 = output, GPIO1 = input) Inverter logic (GPIO2 = output, GPIO1 = input)
Inverter logic (GPIO1 = output, GPIO3 = input) Inverter logic (GPIO2 = output, GPIO3 = input) Inverter logic (GPIO2 = output, GPIO3 = input)
Reserved
Reserved
Reserved
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Registers 13-16 (0Dh-10h)
REG
13
HEX
0Dh
0Eh
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Headphone short-circuit protection enable/disable
Headphone short-circuit protection detect time
RSV SRCR SHCR SPDR RSV SRCL SHCL SPDL
14
RSV
RSV SADR
RSV RSV
RSV
SDTR[1:0]
SRTR[1:0]
RSV
RSV SADL
RSV
RSV
SDTL[1:0]
SRTL[1:0]
Headphone short-circuit protection release time,
auto control
15
16
0Fh
10h
Headphone short-circuit protection status read
RSV SSHR RSV
RSV SSHL
SRCR: Reset Short-Circuit Protection for Headphone Output R-Channel
SRCL: Reset Short-Circuit Protection for Headphone Output L-Channel
These bits initialize the short-circuit protection for the headphone outputs by setting SRCR = SRCL = '1'. After
completing the initialization, the data of both registers are automatically set to '1'.
Default value: 1
0
1
Reset (set to '1' automatically after set to '0')
Normal operation (default)
SPDR: Short-Circuit Protection Disable for Headphone Output R-Channel
SPDL: Short-Circuit Protection Disable for Headphone Output L-Channel
These bits disable the short-circuit protection for the headphone outputs.
Default value: 0
0
1
Enable (default)
Disable
SDTR[1:0]: Short-Circuit Protection Detect Time Control for Headphone Output R-Channel
SDTL[1:0]: Short-Circuit Protection Detect Time Control for Headphone Output L-Channel
These bits define the continuous time until a short-circuit is detected on the headphone outputs. If the
short-circuit time does not reach the defined time, the PCM5310 does not enable short-circuit protection.
Default value: 11
00
01
10
11
4096 fS, 85.2 ms at fS = 48 kHz
8192 fS, 170.4 ms at fS = 48 kHz
16384 fS, 340.8 ms at fS = 48 kHz
32768 fS, 681.6 ms at fS = 48 kHz (default)
SRTR[1:0]: Short-Circuit Protection Release Time Control for Headphone Output R-Channel
SRTL[1:0]: Short-Circuit Protection Release Time Control for Headphone Output L-Channel
These bits define the time until the short-circuit protection is released after detecting a short-circuit.
Default value: 11
00
01
10
11
4096 fS, 85.2 ms at fS = 48 kHz
8192 fS, 170.4 ms at fS = 48 kHz
16384 fS, 340.8 ms at fS = 48 kHz
32768 fS, 681.6 ms at fS = 48 kHz (default)
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SADR: Short-Circuit Protection Automatic Release Disable for Headphone Output R-Channel
SADL: Short-Circuit Protection Automatic Release Disable for Headphone Output L-Channel
These bits disable the automatic power down when a short-circuit is detected.
Default value: 0
0
1
Enable (default)
Disable
SSHR: Short-Circuit Status Read for Headphone Output R-Channel
SSHL: Short-Circuit Status Read for Headphone Output L-Channel
These bits are used to read the short-circuit status on the headphone through the I2C interface. If the status is '1',
then the headphone output is in short-circuit.
Default value: 0
0
1
Not shorted (default)
Short-circuit
Registers 17 and 18 (11h and 12h)
REG
17
HEX
11h
12h
DESCRIPTION
Power up/down (bias)
B7
B6
B5
B4
B3
B2
PDCF[1:0]
PDTM[2:0]
B1
B0
PBIS
RSV
RSV
RSV
RSV
PDCS
18
Power up/down (analog), power up/down time
RSV PABE PAFE PCOM RSV
PBIS: Power Up/Down Control for Analog Bias Circuit
This bit is used to power up/down the analog bias circuit.
Default value: 1
0
1
Power up
Power down (default)
PDCF[1:0]: Power Up/Down Time Control
These bits set the power up/down time for each sampling rate. Set this register when the sampling rate is greater
than 48 kHz at power up/down.
Default value: 00
00
01
10
11
x1 (default)
x1/2
x1/4
Reserved
PDCS: Power Up/Down Clock Selection
The PCM5310 has six clock inputs for the four DAC and four ADC channels. The power on/off sequence starts
using the DAC12 clock or the DAC34 clock. The appropriate clock source must be selected for the power
up/down sequence.
Default value: 0
0
1
Use the DAC12 clock for power up/down (default)
Use the DAC34 clock for power up/down
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PAFE: Power Up/Down Control for Input Mux and Gain Amplifier
This bit powers up/down the input mux and the gain amplifier.
Default value: 1
0
1
Power up
Power down (default)
PABE: Power Up/Down Control for Output Mux, Line Amp, and Headphone Amplifier
This bit powers up/down the output mux, the line amplifiers, and the headphone amplifier.
Default value: 1
0
1
Power up
Power down (default)
PCOM: Power Up/Down Control for Common Voltage Circuit
This bit powers up/down the common voltage circuit for the ADC and DAC channels.
Default value: 1
0
1
Power up
Power down (default)
PDTM[2:0]: Power Up/Down Time Control
The power-up time selection for the PCM5310 can be from ground level to common voltage for analog outputs.
The power-down time selection can be from the common voltage to ground level for analog outputs at the power
on/off sequence. The time described in Figure 32 is defined for a 48-kHz sampling rate. Set bits PDCF[1:0] in
Register 17 when the sampling rate is more than 48 kHz at the power up/down sequence.
Default value: 001
PDTM[2:0]
000
POWER-UP TIME
37.5 ms
POWER-DOWN TIME
75 ms
001
75 ms (default)
150 ms
150 ms
010
300 ms
011
300 ms
600 ms
100
1000 ms
2000 ms
101
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
110
111
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Register 19 (13h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
19
13h
Mute control linked to the AMUTE pin
MD12 MD34 MHPR MHPL ML2R ML2L ML1R ML1L
MD12: Mute Enable/Disable Linked to the AMUTE Pin for Digital Input (DAC12)
MD34: Mute Enable/Disable Linked to the AMUTE Pin for Digital Input (DAC34)
The PCM5310 has a mute control pin (AMUTE, 59 pin). When AMUTE = '1' and MD12 = '1' or MD34 = '1', the
digital soft mute of digital input data is enabled. When AMUTE = '0', mute is disabled.
Default value: 0
0
1
Mute disabled if the AMUTE pin is at a high or lo2w level (default)
Mute enabled if the AMUTE pin is at a high level
MHPR: Mute Enable/Disable Linked AMUTE Pin for Headphone Output, R-Channel
MHPL: Mute Enable/Disable Linked AMUTE Pin for Headphone Output, L-Channel
The PCM5310 has a mute control pin (AMUTE, 59 pin). When AMUTE = '1' and MHPR = '1' or MHPL = '1', the
analog mute for headphone outputs HPOL and HPOR is enabled. When AMUTE = '0', mute is disabled.
Default value: 1
0
1
Mute disabled if the AMUTE pin is at a high or low level
Mute enabled if the AMUTE pin is at a high level (default)
ML1R: Mute Enable/Disable Linked AMUTE Pin for Line Output 1, R-Channel
ML1L: Mute Enable/Disable Linked AMUTE Pin for Line Output 1, L-Channel
The PCM5310 has a mute control pin (AMUTE, 59 pin). When AMUTE = '1' and ML1R = '1' or ML1L = '1', the
analog mute for line outputs LO1L and LO1R are enabled. When AMUTE = '0', mute is disabled.
Default value: 1
0
1
Mute disabled if AMUTE pin is high or low level
Mute enabled if AMUTE pin is high level (default)
MML2R: Mute Enable/Disable Linked AMUTE Pin for Line Output 2, R-Channel
MML2L: Mute Enable/Disable Linked AMUTE Pin for Line Output 2, L-Channel
The PCM5310 has a mute control pin (AMUTE, 59 pin). When AMUTE = '1' and ML2R = '1' or ML2L = '1', the
analog mute for line outputs LO2L and LO2R are enabled. When AMUTE = '0', mute is disabled.
Default value: 1
0
1
Mute disabled if AMUTE pin is high or low level
Mute enabled if AMUTE pin is high level (default)
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Registers 20 and 21 (14h and 15h)
REG
20
HEX
14h
15h
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Analog input mux selection for ADC12
Analog input mux selection for ADC34
RSV
RSV
AX1R[2:0]
AX2R[2:0]
RSV
RSV
AX1L[2:0]
AX2L[2:0]
21
AX1R[2:0]: Analog Input Mux Selection for ADC12, R-Channel
AX1L[2:0]: Analog Input Mux Selection for ADC12, L-Channel
AX2R[2:0]: Analog Input Mux Selection for ADC34, R-Channel
AX2L[2:0]: Analog Input Mux Selection for ADC34, L-Channel
The PCM5310 has six stereo inputs that can select one stereo input for each ADC. It is recommended to use the
digital soft mute to reduce audible noise when the analog inputs are changed; see Figure 44 for details.
Default value: 000
000
001
010
011
100
101
110
No connection (default)
AIN1L or AIN1R
AIN2L or AIN2R
AIN3L or AIN3R
AIN4L or AIN4R
AIN5L or AIN5R
AIN6L or AIN6R
Others Reserved
Registers 22 and 23 (16h and 17h)
REG
22
HEX
16h
17h
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Analog input gain control for ADC12
Analog input gain control for ADC34
RSV
RSV
RSV
RSV
AG1R[1:0]
AG2R[1:0]
RSV
RSV
RSV
RSV
AG1L[1:0]
AG2L[1:0]
23
AG1R[1:0]: Analog Input Gain Control for ADC12, R-Channel
AG1L[1:0]: Analog Input Gain Control for ADC12, L-Channel
AG2R[1:0]: Analog Input Gain Control for ADC34, R-Channel
AG2L[1:0]: Analog Input Gain Control for ADC34, L-Channel
The PCM5310 has analog gain amplifiers in front of each ADC input that can be programmed to between 0 dB to
+9 dB in 3-dB steps; refer to Figure 28 for details.
Default value: 00
00
01
10
11
0 dB (default)
3 dB
6 dB
9 dB
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Registers 24-26 (18h-1Ah)
REG
24
HEX
18h
19h
1Ah
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Analog output mux selection for line output 1
Analog output mux selection for line output 2
Analog output mux selection for headphone output
AL1R[3:0]
AL2R[3:0]
AHPR[3:0]
AL1L[3:0]
25
AL2L[3:0]
AHPL[3:0]
26
AL1R[3:0]: Analog Output Mux Selection for Line Output 1, R-Channel
AL1L[3:0]: Analog Output Mux Selection for Line Output 1, L-Channel
AL2R[3:0]: Analog Output Mux Selection for Line Output 2, R-Channel
AL2L[3:0]: Analog Output Mux Selection for Line Output 2, L-Channel
AHPR[3:0]: Analog Output Mux Selection for Headphone Output, R-Channel
AHPL[3:0]: Analog Output Mux Selection for Headphone Output, L-Channel
Analog outputs LO1L/LO1R, LO2L/LO2R, and HPOL/HPOR can be selected as one of all the analog inputs and
DAC outputs; see Figure 29 for details.
Default value: 0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
No connection (default)
AIN1L or AIN1R
AIN2L or AIN2R
AIN3L or AIN3R
AIN4L or AIN4R
AIN5L or AIN5R
AIN6L or AIN6R
DAC12-L-channel or DAC12-R-channel
DAC34-L-channel or DAC34-R-channel
Others Reserved
Register 27 (1Bh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
27
1Bh
Gain control for line output
GL2R[1:0]
GL2L[1:0]
GL1R[1:0]
GL1L[1:0]
GL2R[1:0]: Gain Control for Line Output 2, R-Channel
GL2L[1:0]: Gain Control for Line Output 2, L-Channel
GL1R[1:0]: Gain Control for Line Output 1, R-Channelt
GL1L[1:0]: Gain Control for Line Output 1, L-Channel
The gain level for line outputs LO1L, LO1R, LO2L, and LO2R can be each be selected as 0 dB, –0.5 dB, or –1.0
dB.
Default value: 00
00
01
10
11
0 dB (default)
–0.5 dB
–1.0 dB
0 dB when selecting analog input to line output
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Register 28 (1Ch)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
28
1Ch
2.0 Vrms and 2.4 Vrms selection for line output
RSV
RSV
RSV
G242
RSV
RSV
RSV
G241
G242: 2-VRMS or 2.4-VRMS Output Mode Selection for Line Output 2
G241: 2-VRMS or 2.4-VRMS Output Mode Selection for Line Output 1
The line outputs can drive a 2-VRMS or 2.4-VRMS output with 10 kΩ. The 2.4-VRMS setting is recommend for use
when the equipment requires greater than 2-VRMS output.
Default value: 0
0
1
2 VRMS (default)
2.4 VRMS
Register 29 (1Dh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
29
1Dh
Clock halt detection control
RSV
RSV
RSV
RSV
RSV
RSV ACTH CHDE
ACTH: Activate Control for Clock Halt Detection
CHDE: Enable Clock Halt Detection
ACTH is used to control the power up/down for clock halt detection and CHDE is used to enable it. Setting
ACTH = CHDE = '1' activates and enables clock halt detection.
Clock halt detection can reduce audible noise. The analog outputs are muted when the clock input to DAC12 and
DAC34 is suddenly stopped.
Default value: 0
ACTH = 0 Deactivate clock halt detection (default)
ACTH = 1 Activate clock halt detection
CHDE = 0 Clock halt detection disabled (default)
CHDE = 1 Clock halt detection enabled
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Register 30 (1Eh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
30
1Eh
Headphone output volume control
HUPE RSV HSUR HSUL RSV
RSV
RSV HZRS
HUPE: Headphone Volume Update Control Enable
HSUR: Headphone Volume Setting Update for Headphone Output, R-Channel
HSUL: Headphone Volume Setting Update for Headphone Output, L-Channel
HZRS: Headphone Volume Zero Cross Enable
The volume level of the headphone output can be changed independently to any level by setting HMUL/HMUR
and HVOL[6:0]/HVOR[6:0] when HUPE = '0'. When HUPE = '1', the volume level is changed to any level at the
same time when HSUR = '1' or HSUL = '1'. Both bits are automatically set to '0' after being set to '1'. HSUR and
HSUL must be set to '1' for every volume level setting during HUPE = '1'.
Default value of HUPE and HZRS: 1. Default value of HSUR and HSUL: 0
HUPE = 0 Headphone volume update control disable
HUPE = 1 Headphone volume update control enable (default)
HSUR, HSUL = 0 No update volume setting data (default)
HSUR, HSUL = 1 Update volume setting data (set to '0' automatically after setting to '1')
HZRS = 0 Headphone volume zero crossing disable
HZRS = 1 Headphone volume zero crossing enable (default)
Register 31 and 32 (1Fh and 20h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Headphone mute and volume level setting for
R-channel
31
1Fh
HMUL
HVOL[6:0]
Headphone mute and volume level setting for
L-channel
32
20h
HMUR
HVOR[6:0]
HMUL: Headphone Volume Mute Control for L-Channel
HMUR: Headphone Volume Mute Control for R-Channel
The headphone output can be independently muted to zero level when HMUL and HMUR = '1'. These settings
take precedence over volume level settings by HVOL and HVOR. The headphone output may have audible
zipper noise while changing levels. This noise can be reduced by selecting zero-crossing detection (Register 30,
HZRS).
Default value: 0
0
1
Mute disabled (default)
Mute enabled
HVOL[6:0]: Headphone Volume Level Control for L-Channel
HVOR[6:0]: Headphone Volume Level Control for R-Channel
The headphone output can be independently programmed to between 12 dB to –70 dB in 1-dB steps. The
headphone output may have audible zipper noise while changing levels. This noise can be reduced by selecting
zero-crossing detection (Register 30, HZRS).
Default value: 010 1101
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Table 32. Headphone Volume Level Control
HP VOLUME
LEVEL
CONTROL
HP VOLUME
LEVEL
CONTROL
HP VOLUME
LEVEL
CONTROL
HVOL[6:0]
HVOR[6:0]
HVOL[6:0]
HVOR[6:0]
HVOL[6:0]
HVOR[6:0]
111 1111
7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
12 dB
11 dB
10 dB
9 dB
110 0010
62
61
60
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
–17 dB
–18 dB
–19 dB
–20 dB
–21 dB
–22 dB
–23 dB
–24 dB
–25 dB
–26 dB
–27 dB
–28 dB
–29 dB
–30 dB
–31 dB
–32 dB
–33 dB
–34 dB
–35 dB
–36 dB
–37 dB
–38 dB
–39 dB
–40 dB
–41 dB
–42 dB
–43 dB
–44 dB
–45 dB
100 0101
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
–46 dB
–47 dB
–48 dB
–49 dB
–50 dB
–51 dB
–52 dB
–53 dB
–54 dB
–55 dB
–56 dB
–57 dB
–58 dB
–59 dB
–60 dB
–61 dB
–62 dB
–63 dB
–64 dB
–65 dB
–66 dB
–67 dB
–68 dB
–69 dB
–70 dB (default)
111 1110
111 1101
111 1100
111 1011
111 1010
111 1001
111 1000
111 0111
111 0110
111 0101
111 0100
111 0011
1110010
111 0001
111 0000
110 1111
110 1110
110 1101
110 1100
110 1011
110 1010
110 1001
110 1000
110 0111
110 0110
110 0101
110 0100
110 0011
110 0001
110 0000
101 1111
101 1110
101 1101
101 1100
101 1011
101 1010
101 1001
101 1000
101 0111
101 0110
101 0101
101 0100
101 0011
101 0010
101 0001
101 0000
100 1111
100 1110
100 1101
100 1100
100 1011
100 1010
100 1001
100 1000
100 0111
100 0110
100 0100
100 0011
100 0010
100 0001
100 0000
011 1111
011 1110
011 1101
011 1100
011 1011
011 1010
011 1001
011 1000
011 0111
011 0110
011 0101
011 0100
011 0011
011 0010
011 0001
011 0000
010 1111
010 1110
010 1101
8 dB
7 dB
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB
–13 dB
–14 dB
–15 dB
–16 dB
010 1100
⋮
000 0000
2C
⋮
00
Mute
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Register 33 (21h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
33
21h
System clock output disable
RSV
RSV SC6D SC5D SC4D SC3D SC2D SC1D
SC6D: SCK6 Output Disable
SC5D: SCK5 Output Disable
SC4D: SCK4 Output Disable
SC3D: SCK3 Output Disable
SC2D: SCK2 Output Disable
SC1D: SCK1 Output Disable
These bits are used to disable (low-level output) the clock ports (SCK1, SCK2, SCK3, SCK4, SCK5 and SCK6)
in output mode. It is necessary to use these bits with Register 103 (SCS2[2:0], SCS1[2:0]), Register 106
(SCS4[2:0], SCS3[2:0]), and Register 109 (SCS6[2:0], SCS5[2:0]). Each clock port is set to input mode at the
default setting.
Default value: 1
0
1
Normal output
Disable, low-level output (default)
Register 34 (22h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
34
22h
LRCK and BCK output disable at master mode
RSV
RSV
LB6D LB5D LB4D LB3D LB2D LB1D
LB6D: LRCK6 and BCK6 Output Disable
LB5D: LRCK5 and BCK5 Output Disable
LB4D: LRCK4 and BCK4 Output Disable
LB3D: LRCK3 and BCK3 Output Disable
LB2D: LRCK2 and BCK2 Output Disable
LB1D: LRCK1 and BCK1 Output Disable
These bits are used to disable (low-level output) the LRCK/BCK ports (LRCK1/BCK1, LRCK2/BCK2,
LRCK3/BCK3, LRCK4/BCK4, LRCK5/BCK5 and LRCK6/BCK6) in output mode. It is necessary to use these bits
with Register 101 (LBS2[3:0], LBS1[3:0]), Register 104 (LBS4[3:0], LBS3[3:0]), and Register 107 (LBS6[3:0],
LBS5[3:0]). Each LRCK/BCK port is set to input mode at the default setting.
Default value: 1
0
1
Normal output
Disable, low-level output (default)
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Registers 35-39 (23h-27h)
REG
35
HEX
23h
24h
25h
26h
27h
DESCRIPTION
Read internal flag
Read internal flag
Read internal flag
Read internal flag
Read internal flag
B7
B6
B5
B4
B3
B2
B1
B0
RSV
RSV
RSV
RSV
RD12FS[2:0]
RD34FS[2:0]
RA12FS[2:0]
RA34FS[2:0]
RHMR RHML RSV
RHPI
36
RDM4 RDM3 RDM2 RDM1
RAM4 RAM3 RAM2 RAM1
RDZ4 RDZ3 RDZ2 RDZ1
37
38
39
CGLD RSV RHZR RHZL RAZ4 RAZ3 RAZ2 RAZ1
RD12FS[2:0]: Read System Clock fS Rate Detection Status for DAC12
RD34FS[2:0]: Read System Clock fS Rate Detection Status for DAC34
RA12FS[2:0]: Read System Clock fS Rate Detection Status for ADC12
RA34FS[2:0]: Read System Clock fS Rate Detection Status for ADC34
The PCM5310 includes automatic clock rate detection, which provides a divided clock to the ADC and DAC
channels. The result of the detected clock rate can be read through the I2C port.
Default value: 111
000
001
010
011
100
101
110
111
Reserved
128 fS (default)
192 fS
256 fS
384 fS
512 fS
768 fS
Reserved (default)
RHMR: Read Mute Status for Headphone Output R-Channel
RHML: Read Mute Status for Headphone Output L-Channel
These bits are used to read the mute status of the headphone output. The results can be read through the I2C
port.
Default value: 0
0
1
Mute disabled (default)
Mute enabled
RHPI: Read Headphone Insertion Detection Status for Headphone Output
This bit is used to read the headphone output insertion detection status through the I2C port. Headphone
insertion is set by Register 09 to Register 11 (GSL1[4:0], GSL2[4:0], GSL3[4:0]) with the GPIO port.
Default value: 0
0
1
Headphone not inserted (default)
Headphone inserted
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RDM4: Read Digital Mute Status for DAC34, R-Channel
RDM3: Read Digital Mute Status for DAC34, L-Channel
RDM2: Read Digital Mute Status for DAC12, R-Channel
RDM1: Read Digital Mute Status for DAC12, L-Channel
These bits are used to read the digital soft mute status for each DAC channel through the I2C port.
Default value: 1
0
1
Mute disabled
Mute enabled (default)
RAM4: Read Digital Mute Status for ADC34, R-Channel
RAM3: Read Digital Mute Status for ADC34, L-Channel
RAM2: Read Digital Mute Status for ADC12, R-Channel
RAM1: Read Digital Mute Status for ADC12, L-Channel
These bits are used to read the digital soft mute status for each ADC channel through the I2C port.
Default value: 1
0
1
Mute disabled
Mute enabled (default)
RRHZR: Read Volume Zero Cross Time Out Status for Headphone, R-Channel
RHZL: Read Volume Zero Cross Time Out Status for Headphone, L-Channel
RDZ4: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC34, R-Channel
RDZ3: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC34, L-Channel
RDZ2: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC12, R-Channel
RDZ1: Read Digital Attenuation/Mute Zero Cross Timeout Status for DAC12, L-Channel
RAZ4: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC34, R-Channel
RAZ3: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC34, L-Channel
RAZ2: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC12, R-Channel
RAZ1: Read Digital Attenuation/Mute Zero Cross Timeout Status for ADC12, L-Channel
These bits are used to read the zero-crossing timeout status of digital soft mute and digital attenuation for each
ADCs and DACs channel and for headphone output volume through the I2C port.
Default value: 0
0
1
not timed out (default)
Timed out
CGLD: Glitch Reduction Disable when Changing Clock Source
This bit disables the glitch reduction circuit, which reduces audible pop noise when changing the clock input from
any SCKx to SCKx.
Default value: 0
0
1
Enabled (default)
Disabled
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Registers 40 and 41 (28h and 29h)
REG
40
HEX
28h
29h
DESCRIPTION
B7
B6
RSV DUC2 DUC1 RSV
RSV RSV RSV
B5
B4
B3
B2
B1
B0
Digital attenuation and mute control for DAC12
Digital gain boost and digital soft mute for DAC12
D12E
RSV
RSV
RSV
DZ12
41
DB12[1:0]
DMU2 DMU1
D12E: Digital Attenuation and Mute Update Control Enable for DAC12
DUC2: Digital Attenuation and Mute Setting Update for DAC12, R-Channel
DUC1: Digital Attenuation and Mute Setting Update for DAC12, L-Channel
The digital attenuation and mute levels of DAC12 can be changed independently to any level by setting bits
DMU2 and DMU1 of Register 41, bits DAT1[7:0] of Register 42, and bits DAT2[7:0] of Register 43 when D12E =
'0'. When D12E = '1', the level is changed to any level at the same time when DUC2 = '1' or DUC1 = '1'. Both bits
are automatically set to '0' after being set to '1'. DUC2 and DUC1 must be set to '1' for every volume level setting
while HUPE = '1'.
Default value of D12E: 1. Default value of DUC2 and DUC1: 0
D12E = 0
D12E = 1
Digital attenuation and mute update control disabled
Digital attenuation and mute update control enabled (default)
DUC2, DUC1 = 0
DUC2, DUC1 = 1
No update level (default)
Update level (set to '0' automatically after setting to '1')
DZ12: Digital Attenuation and Mute Zero Crossing Enable for DAC12
This bit enables zero-crossing detection, which reduces zipper noise while the DAC digital attenuator and mute
settings are being changed. If no zero-crossing data are input for a 512/fS period (10.6 ms at a 48-kHz sampling
rate), then a timeout occurs and the PCM5310 volume level changes. Zero-crossing detection cannot be used
with continuous zero and dc data.
Default value: 1
0
1
Disabled
Enabled (default)
DB12[1:0]: Digital Gain Boost for DAC12
These bits boost the gain for the digital data input to the DAC12 channels before the digital attenuation.
Default value: 00
00
01
10
11
0dB (default)
6 dB
12 dB
18 dB
DMU2: Digital Mute Control for DAC12, R-Channel
DMU1: Digital Mute Control for DAC12, L-Channel
The PCM5310 can independently mute the DACs digital input data to zero level when DMU2 and DMU1 = '1'.
These settings take precedence over the attenuation level settings set by bits DAT1[7:0] and DAT2[7:0] in
regsiter 42. The analog outputs may have audible zipper noise while changing levels. This noise can be reduced
by selecting zero-crossing detection (Register 40, DZ12).
Default value: 0
0
1
Mute disabled (default)
Mute enabled
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Registers 42 and 43 (2Ah and 2Bh)
REG
42
HEX
2Ah
2Bh
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Digital attenuation level setting for DAC12 L-channel
Digital attenuation level setting for DAC12 R-channel
DAT1[7:0]
DAT2[7:0]
43
DAT1[7:0]: Digital Attenuation Setting for DAC12, L-Channel
DAT2[7:0]: Digital Attenuation Setting for DAC12, R-Channel
The digital attenuator of DAC12 can be independently set from 0 dB to –100 dB in 0.5-dB steps. The DAC12
output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero
crossing detection (Register 40, DZ12).
Default value : 1111 1111
Table 33. Digital Attenuation Level Setting for DAC12
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DAT1[7:0]
DAT2[7:0]
DAT1[7:0]
DAT2[7:0]
DAT1[7:0]
DAT2[7:0]
DAT1[7:0]
DAT2[7:0]
1111 1111 FF 0 dB (default)
1100 1100 CC
1100 1011 CB
1100 1010 CA
1100 1001 C9
1100 1000 C8
1100 0111 C7
1100 0110 C6
1100 0101 C5
1100 0100 C4
1100 0011 C3
1100 0010 C2
1100 0001 C1
1100 0000 C0
1011 1111 BF
1011 1110 BE
1011 1101 BD
1011 1100 BC
1011 1011 BB
1011 1010 BA
1011 1001 B9
1011 1000 B8
1011 0111 B7
1011 0110 B6
1011 0101 B5
1011 0100 B4
1011 0011 B3
1011 0010 B2
1011 0001 B1
1011 0000 B0
1010 1111 AF
1010 1110 AE
1010 1101 AD
1010 1100 AC
–25.5 dB
–26 dB
1001 1001 99
1001 1000 98
1001 0111 97
1001 0110 96
1001 0101 95
1001 0100 94
1001 0011 93
1001 0010 92
1001 0001 91
1001 0000 90
1000 1111 8F
1000 1110 8E
1000 1101 8D
1000 1100 8C
1000 1011 8B
1000 1010 8A
1000 1001 89
1000 1000 88
1000 0111 87
1000 0110 86
1000 0101 85
1000 0100 84
1000 0011 83
1000 0010 82
1000 0001 81
1000 0000 80
0111 1111 7F
0111 1110 7E
0111 1101 7D
0111 1100 7C
0111 1011 7B
0111 1010 7A
0111 1001 79
– 51 dB
–51.5 dB
–52 dB
0110 0110 66
0110 0101 65
0110 0100 64
0110 0011 63
0110 0010 62
0110 0001 61
0110 0000 60
0101 1111 5F
0101 1110 5E
0101 1101 5D
0101 1100 5C
0101 1011 5B
0101 1010 5A
0101 1001 59
0101 1000 58
0101 0111 57
0101 0110 56
0101 0101 55
0101 0100 54
0101 0011 53
0101 0010 52
0101 0001 51
0101 0000 50
0100 1111 4F
0100 1110 4E
0100 1101 4D
0100 1100 4C
0100 1011 4B
0100 1010 4A
0100 1001 49
0100 1000 48
0100 0111 47
0100 0110 46
–76.5 dB
–77 dB
1111 1110 FE
1111 1101 FD
1111 1100 FC
1111 1011 FB
1111 1010 FA
1111 1001 F9
1111 1000 F8
1111 0111 F7
1111 0110 F6
1111 0101 F5
1111 0100 F4
1111 0011 F3
1111 0010 F2
1111 0001 F1
1111 0000 F0
1110 1111 EF
1110 1110 EE
1110 1101 ED
1110 1100 EC
1110 1011 EB
1110 1010 EA
1110 1001 E9
1110 1000 E8
1110 0111 E7
1110 0110 E6
1110 0101 E5
1110 0100 E4
1110 0011 E3
1110 0010 E2
1110 0001 E1
1110 0000 E0
1101 1111 DF
–0.5 dB
–1 dB
–26.5 dB
–27 dB
–77.5 dB
–78 dB
–1.5 dB
–2 dB
–52.5 dB
–53 dB
–27.5 dB
–28 dB
–78.8 dB
–79 dB
–2.5 dB
–3 dB
–53.5 dB
–54 dB
–28.5 dB
–29 dB
–79.5 dB
–80 dB
–3.5 dB
–4 dB
–54.5 dB
–55 dB
–29.5 dB
–30 dB
–80.5 dB
–81 dB
–4.5 dB
–5 dB
–55.5 dB
–56 dB
–30.5 dB
–31 dB
–81.5 dB
–82 dB
–5.5 dB
–6 dB
–56.5 dB
–57 dB
–31.5 dB
–32 dB
–82.5 dB
–83 dB
–6.5 dB
–7 dB
–57.5 dB
–58 dB
–32.5 dB
–33 dB
–83.5 dB
–84 dB
–7.5 dB
–8 dB
–58.5 dB
–59 dB
–33.5 dB
–34 dB
–84.5 dB
–85 dB
–8.5 dB
–9 dB
–59.5 dB
–60 dB
–34.5 dB
–35 dB
–85.5 dB
–86 dB
–9.5 dB
–10 dB
–10.5 dB
–11 dB
–11.5 dB
–12 dB
–12.5 dB
–13 dB
–13.5 dB
–14 dB
–14.5 dB
–15 dB
–15.5 dB
–16 dB
–60.5 dB
–61 dB
–35.5 dB
–36 dB
–86.5 dB
–87 dB
–61.5 dB
–62 dB
–36.5 dB
–37 dB
–87.5 dB
–88 dB
–62.5 dB
–63 dB
–37.5 dB
–38 dB
–88.5 dB
–89 dB
–63.5 dB
–64 dB
–38.5 dB
–39 dB
–89.5 dB
–90 dB
–64.5 dB
–65 dB
–39.5 dB
–40 dB
–90.5 dB
–91 dB
–65.5 dB
–66 dB
–40.5 dB
–41 dB
–91.5 dB
–92 dB
–66.5 dB
–67 dB
–41.5 dB
–92.5 dB
58
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Table 33. Digital Attenuation Level Setting for DAC12 (continued)
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DAT1[7:0]
DAT2[7:0]
DAT1[7:0]
DAT2[7:0]
DAT1[7:0]
DAT2[7:0]
DAT1[7:0]
DAT2[7:0]
1101 1110 DE
1101 1101 DD
1101 1100 DC
1101 1011 DB
1101 1010 DA
1101 1001 D9
1101 1000 D8
1101 0111 D7
1101 0110 D6
1101 0101 D5
1101 0100 D4
1101 0011 D3
1101 0010 D2
1101 0001 D1
1101 0000 D0
1100 1111 CF
1100 1110 CE
1100 1101 CD
–16.5 dB
–17 dB
1010 1011 AB
1010 1010 AA
1010 1001 A9
1010 1000 A8
1010 0111 A7
1010 0110 A6
1010 0101 A5
1010 0100 A4
1010 0011 A3
1010 0010 A2
1010 0001 A1
1010 0000 A0
1001 1111 9F
1001 1110 9E
1001 1101 9D
1001 1100 9C
1001 1011 9B
1001 1010 9A
–42 dB
–42.5 dB
–43 dB
0111 1000 78
0111 0111 77
0111 0110 76
0111 0101 75
0111 0100 74
0111 0011 73
0111 0010 72
0111 0001 71
0111 0000 70
0110 1111 6F
0110 1110 6E
0110 1101 6D
0110 1100 6C
0110 1011 6B
0110 1010 6A
0110 1001 69
0110 1000 68
0110 0111 67
–67.5 dB
–68 dB
0100 0101 45
0100 0100 44
0100 0011 43
0100 0010 42
0100 0001 41
0100 0000 40
0011 1111 3F
0011 1110 3E
0011 1101 3D
0011 1100 3C
0011 1011 3B
0011 1010 3A
0011 1001 39
0011 1000 38
0011 0111 37
–93 dB
–93.5 dB
–94 dB
–17.5 dB
–18 dB
–68.5 dB
–69 dB
–43.5 dB
–44 dB
–94.5 dB
–95 dB
–18.5 dB
–19 dB
–69.5 dB
–70 dB
–44.5 dB
–45 dB
–95.5 dB
–96 dB
–19.5 dB
–20 dB
–70.5 dB
–71 dB
–45.5 dB
–46 dB
–96.5 dB
–97 dB
–20.5 dB
–21 dB
–71.5 dB
–72 dB
–46.5 dB
–47 dB
–97.5 dB
–98 dB
–21.5 dB
–22 dB
–72.5 dB
–73 dB
–47.5 dB
–48 dB
–98.5 dB
–99 dB
–22.5 dB
–23 dB
–73.5 dB
–74 dB
–48.5 dB
–49 dB
–99.5 dB
–100 dB
–23.5 dB
–24 dB
–74.5 dB
–75 dB
–49.5 dB
–50 dB
0011 0110 36
–24.5 dB
–25 dB
–75.5 dB
–76 dB
⋮
⋮
Mute
0000 0000 00
–50.5 dB
Registers 44 and 45 (2Ch and 2Dh)
REG
44
HEX
2Ch
2Dh
DESCRIPTION
B7
B6
DMS12[3:0]
RSV RSV
B5
B4
B3
B2
B1
B0
Master/slave interface format for DAC12
De-emphasis filter control for DAC12
RSV
RSV
DFM12[1:0]
DF12[1:0]
45
RSV
RSV DM12 RSV
DMS12[3:0]: Master/Slave Audio Interface Setting for DAC12
These bits set the master or slave mode. DAC12 receives LRCK and BCK from PORT-1, PORT-2, PORT-3,
PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode.
Default value: 1000
MASTER/SLAVE AUDIO INTERFACE SETTING FOR
DAC12
MASTER/SLAVE AUDIO INTERFACE SETTING FOR
DAC12
DMS12[3:0]
0000
DMS12[3:0]
1000
Reserved
Slave and system clock fS auto-detect mode (default)
Slave and system clock 768 fS
Slave and system clock 512 fS
Slave and system clock 384 fS
Slave and system clock 256 fS
Slave and system clock 192 fS
Slave and system clock 128 fS
Reserved
0001
Master and system clock 768 fS
Master and system clock 512 fS
Master and system clock 384 fS
Master and system clock 256 fS
Master and system clock 192 fS
Master and system clock 128 fS
Reserved
1001
0010
1010
0011
1011
0100
1100
0101
1101
0110
1110
0111
1111
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DFM12[1:0]: Audio Interface Format for DAC12
These bits select the DAC12 audio data format as I2S, right-justified, or left-justified.
Default value: 00
00
01
10
11
16 to 24 bits, I2S (default)
16 to 24 bits, left-justified
24 bits, right-justified
16 bits, right-justified
DM12: De-Emphasis Filter Enable for DAC12
This bit enables the DAC12 de-emphasis filter. The frequency can be selected by setting bits DF12[1:0] of
Register 45.
Default value: 0
0
1
Disable (default)
Enable
DF12[1:0]: De-Emphasis Filter Sampling Rate Selection for DAC12
A digital de-emphasis filter is in front of the interpolation filter. One of three de-emphasis filters can be selected
corresponding to the sampling rate: 32 kHz, 44.1 kHz, or 48 kHz.
Default value: 00
00
01
10
11
44.1 kHz (default)
48 kHz
32 kHz
Reserved
Register 46 (2Eh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
46
2Eh
Power up/down, oversampling rate control for DAC12 PD12 RSV
OV12[1:0]
ZR12 RSV
RSV
RSV
PD12: Power Up/Down Control for DAC12
This bit controls the power up/down for DAC12, including the interpolation filter.
Default value: 1
0
1
Power up
Power down (default)
OV12[1:0]: Oversampling Rate Control for DAC12
These bits are used to control the oversampling rate of the DAC12 delta-sigma modulator.
Default value: 01
SYSTEM CLOCK RATE
OV12
128 fS, 192 fS
16 fS
256 fS, 384 fS
128 fS, 192 fS
64 fS
00
01 (default)
10
32 fS
64 fS
—
32 fS
128 fS
—
(1)
(1)
11
32 fS
128 fS
128 fS
(1) Less than fS = 48 kHz
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ZR12: Zero Flag Reverse
This bit reverses the polarity of the zero flag output. The zero flag goes from low to high after the digital input
data are continuously zero during 1024 fS when ZR12 = '0'. The zero flag can output from the GPIO pins by
setting Registers 9 to 11 (GSL1[4:0], GSL2[4:0], GSL3[4:0]).
Default value: 0
0
1
Buffered output (default)
Inverted output
Registers 50 and 51 (32h and 33h)
REG
50
HEX
32h
33h
DESCRIPTION
B7
B6
RSV DUC4 DUC3 RSV
RSV RSV RSV
B5
B4
B3
B2
B1
B0
Digital attenuation and mute control for DAC34
Digital gain boost and digital soft mute for DAC34
D34E
RSV
RSV
RSV
DZ34
51
DB34[1:0]
DMU4 DMU3
D34E: Digital Attenuation and Mute Update Control Enable for DAC34
DUC4: Digital Attenuation and Mute Setting Update for DAC34, R-Channel
DUC3: Digital Attenuation and Mute Setting Update for DAC34, L-Channel
The digital attenuation and mute levels of DAC34 can be changed independently to any level by setting bits
DMU4 and DMU3 in Register 51, bits DAT3[7:0] in Register 52, and bits DAT4[7:0] in Register 53 when D34E =
'0'. When D34E = '1', the level is changed to any level at the same time when DUC4 = '1' or DUC3 = '1'. Both bits
are automatically set to '0' after they are set to '1'. DUC4 and DUC3 must be set to '1' for every volume level
setting while D34E = '1'.
Default value of D34E: 1. Default value of DUC4 and DUC3: 0
D34E = 0 Digital attenuation and mute update control disabled
D34E = 1 Digital attenuation and mute update control enabled (default)
DUC4, DUC3 = 0
DUC4, DUC3 = 1
No update level (default)
Update level (set to '0' automatically after setting to '1')
DZ34: Digital Attenuation and Mute Zero Cross Enable for DAC34
This bit enables zero-crossing detection, which reduces zipper noise while the DAC digital attenuator and mute
settings are being changed. If no zero-crossing data are input for a 512/fS period (10.6 ms at a 48-kHz sampling
rate), then a timeout occurs and the PCM5310 volume level changes. Zero-crossing detection cannot be used
with continuous zero and dc data.
Default value: 1
0
1
Disable
Enable (default)
DB34[1:0]: Digital Gain Boost for DAC34
These bits are used to boost the gain of digital data input to the DACs in front of the digital attenuator.
Default value: 00
00
01
10
11
0 dB (default)
6 dB
12 dB
18 dB
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DMU4: Digital Mute Control for DAC34, R-Channel
DMU3: Digital Mute Control for DAC34, L-Channel
The PCM5310 can independently mute the DAC digital input data to a zero level when DMU4 and DMU3 = '1'.
These settings take precedence over the attenuation level settings of bits DAT3[7:0] and DAT4[7:0] in registers
52 and 53. The analog outputs may have audible zipper noise while changing levels. This noise can be reduced
by selecting zero-crossing detection (Register 50, DZ34).
Default value: 0
0
1
Mute disabled (default)
Mute enabled
Registers 52 and 53 (34h and 35h)
REG
52
HEX
34h
35h
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Digital attenuation level setting for DAC34 L-channel
Digital attenuation level setting for DAC34 R-channel
DAT3[7:0]
DAT4[7:0]
53
DAT3[7:0]: Digital Attenuation Setting for DAC34, L-Channel
DAT4[7:0]: Digital Attenuation Setting for DAC34, R-Channel
The digital attenuator of DAC34 can be independently set from 0 dB to –100 dB in 0.5-dB steps. The DAC34
output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero
crossing detection (Register 50, DZ34).
Default value : 1111 1111
Table 34. Digital Attenuation Level Setting for DAC34
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DAT3[7:0]
DAT4[7:0]
DAT3[7:0]
DAT4[7:0]
DAT3[7:0]
DAT4[7:0]
DAT3[7:0]
DAT4[7:0]
1111 1111 FF 0 dB (default)
1100 1100 CC
1100 1011 CB
1100 1010 CA
1100 1001 C9
1100 1000 C8
1100 0111 C7
1100 0110 C6
1100 0101 C5
1100 0100 C4
1100 0011 C3
1100 0010 C2
1100 0001 C1
1100 0000 C0
1011 1111 BF
1011 1110 BE
1011 1101 BD
1011 1100 BC
1011 1011 BB
1011 1010 BA
1011 1001 B9
1011 1000 B8
1011 0111 B7
1011 0110 B6
–25.5 dB
–26 dB
1001 1001 99
1001 1000 98
1001 0111 97
1001 0110 96
1001 0101 95
1001 0100 94
1001 0011 93
1001 0010 92
1001 0001 91
1001 0000 90
1000 1111 8F
1000 1110 8E
1000 1101 8D
1000 1100 8C
1000 1011 8B
1000 1010 8A
1000 1001 89
1000 1000 88
1000 0111 87
1000 0110 86
1000 0101 85
1000 0100 84
1000 0011 83
– 51 dB
–51.5 dB
–52 dB
0110 0110 66
0110 0101 65
0110 0100 64
0110 0011 63
0110 0010 62
0110 0001 61
0110 0000 60
0101 1111 5F
0101 1110 5E
0101 1101 5D
0101 1100 5C
0101 1011 5B
0101 1010 5A
0101 1001 59
0101 1000 58
0101 0111 57
0101 0110 56
0101 0101 55
0101 0100 54
0101 0011 53
0101 0010 52
0101 0001 51
0101 0000 50
–76.5 dB
–77 dB
1111 1110 FE
1111 1101 FD
1111 1100 FC
1111 1011 FB
1111 1010 FA
1111 1001 F9
1111 1000 F8
1111 0111 F7
1111 0110 F6
1111 0101 F5
1111 0100 F4
1111 0011 F3
1111 0010 F2
1111 0001 F1
1111 0000 F0
1110 1111 EF
1110 1110 EE
1110 1101 ED
1110 1100 EC
1110 1011 EB
1110 1010 EA
1110 1001 E9
–0.5 dB
–1 dB
–26.5 dB
–27 dB
–77.5 dB
–78 dB
–1.5 dB
–2 dB
–52.5 dB
–53 dB
–27.5 dB
–28 dB
–78.8 dB
–79 dB
–2.5 dB
–3 dB
–53.5 dB
–54 dB
–28.5 dB
–29 dB
–79.5 dB
–80 dB
–3.5 dB
–4 dB
–54.5 dB
–55 dB
–29.5 dB
–30 dB
–80.5 dB
–81 dB
–4.5 dB
–5 dB
–55.5 dB
–56 dB
–30.5 dB
–31 dB
–81.5 dB
–82 dB
–5.5 dB
–6 dB
–56.5 dB
–57 dB
–31.5 dB
–32 dB
–82.5 dB
–83 dB
–6.5 dB
–7 dB
–57.5 dB
–58 dB
–32.5 dB
–33 dB
–83.5 dB
–84 dB
–7.5 dB
–8 dB
–58.5 dB
–59 dB
–33.5 dB
–34 dB
–84.5 dB
–85 dB
–8.5 dB
–9 dB
–59.5 dB
–60 dB
–34.5 dB
–35 dB
–85.5 dB
–86 dB
–9.5 dB
–10 dB
–10.5 dB
–11 dB
–60.5 dB
–61 dB
–35.5 dB
–36 dB
–86.5 dB
–87 dB
–61.5 dB
–62 dB
–36.5 dB
–87.5 dB
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Table 34. Digital Attenuation Level Setting for DAC34 (continued)
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DAT3[7:0]
DAT4[7:0]
DAT3[7:0]
DAT4[7:0]
DAT3[7:0]
DAT4[7:0]
DAT3[7:0]
DAT4[7:0]
1110 1000 E8
1110 0111 E7
1110 0110 E6
1110 0101 E5
1110 0100 E4
1110 0011 E3
1110 0010 E2
1110 0001 E1
1110 0000 E0
1101 1111 DF
1101 1110 DE
1101 1101 DD
1101 1100 DC
1101 1011 DB
1101 1010 DA
1101 1001 D9
1101 1000 D8
1101 0111 D7
1101 0110 D6
1101 0101 D5
1101 0100 D4
1101 0011 D3
1101 0010 D2
1101 0001 D1
1101 0000 D0
1100 1111 CF
1100 1110 CE
1100 1101 CD
–11.5 dB
–12 dB
1011 0101 B5
1011 0100 B4
1011 0011 B3
1011 0010 B2
1011 0001 B1
1011 0000 B0
1010 1111 AF
1010 1110 AE
1010 1101 AD
1010 1100 AC
1010 1011 AB
1010 1010 AA
1010 1001 A9
1010 1000 A8
1010 0111 A7
1010 0110 A6
1010 0101 A5
1010 0100 A4
1010 0011 A3
1010 0010 A2
1010 0001 A1
1010 0000 A0
1001 1111 9F
1001 1110 9E
1001 1101 9D
1001 1100 9C
1001 1011 9B
1001 1010 9A
–37 dB
–37.5 dB
–38 dB
1000 0010 82
1000 0001 81
1000 0000 80
0111 1111 7F
0111 1110 7E
0111 1101 7D
0111 1100 7C
0111 1011 7B
0111 1010 7A
0111 1001 79
0111 1000 78
0111 0111 77
0111 0110 76
0111 0101 75
0111 0100 74
0111 0011 73
0111 0010 72
0111 0001 71
0111 0000 70
0110 1111 6F
0110 1110 6E
0110 1101 6D
0110 1100 6C
0110 1011 6B
0110 1010 6A
0110 1001 69
0110 1000 68
0110 0111 67
–62.5 dB
–63 dB
0100 1111 4F
0100 1110 4E
0100 1101 4D
0100 1100 4C
0100 1011 4B
0100 1010 4A
0100 1001 49
0100 1000 48
0100 0111 47
0100 0110 46
0100 0101 45
0100 0100 44
0100 0011 43
0100 0010 42
0100 0001 41
0100 0000 40
0011 1111 3F
0011 1110 3E
0011 1101 3D
0011 1100 3C
0011 1011 3B
0011 1010 3A
0011 1001 39
0011 1000 38
0011 0111 37
–88 dB
–88.5 dB
–89 dB
–12.5 dB
–13 dB
–63.5 dB
–64 dB
–38.5 dB
–39 dB
–89.5 dB
–90 dB
–13.5 dB
–14 dB
–64.5 dB
–65 dB
–39.5 dB
–40 dB
–90.5 dB
–91 dB
–14.5 dB
–15 dB
–65.5 dB
–66 dB
–40.5 dB
–41 dB
–91.5 dB
–92 dB
–15.5 dB
–16 dB
–66.5 dB
–67 dB
–41.5 dB
–42 dB
–92.5 dB
–93 dB
–16.5 dB
–17 dB
–67.5 dB
–68 dB
–42.5 dB
–43 dB
–93.5 dB
–94 dB
–17.5 dB
–18 dB
–68.5 dB
–69 dB
–43.5 dB
–44 dB
–94.5 dB
–95 dB
–18.5 dB
–19 dB
–69.5 dB
–70 dB
–44.5 dB
–45 dB
–95.5 dB
–96 dB
–19.5 dB
–20 dB
–70.5 dB
–71 dB
–45.5 dB
–46 dB
–96.5 dB
–97 dB
–20.5 dB
–21 dB
–71.5 dB
–72 dB
–46.5 dB
–47 dB
–97.5 dB
–98 dB
–21.5 dB
–22 dB
–72.5 dB
–73 dB
–47.5 dB
–48 dB
–98.5 dB
–99 dB
–22.5 dB
–23 dB
–73.5 dB
–74 dB
–48.5 dB
–49 dB
–99.5 dB
–100 dB
–23.5 dB
–24 dB
–74.5 dB
–75 dB
–49.5 dB
–50 dB
0011 0110 36
–24.5 dB
–25 dB
–75.5 dB
–76 dB
⋮
⋮
Mute
0000 0000 00
–50.5 dB
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Registers 54 and 55 (36h and 37h)
REG
54
HEX
36h
37h
DESCRIPTION
B7
B6
DMS34[3:0]
RSV RSV
B5
B4
B3
B2
B1
B0
Master/slave interface format for DAC34
De-emphasis filter control for DAC34
RSV
RSV
DFM34[1:0]
DF34[1:0]
55
RSV
RSV DM34 RSV
DMS34[3:0]: Master/Slave Audio Interface Setting for DAC34
These bits set the master or slave mode. DAC34 receives LRCK and BCK from PORT-1, PORT-2, PORT-3,
PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode.
Default value: 1000
MASTER/SLAVE AUDIO INTERFACE SETTING FOR
DAC34
MASTER/SLAVE AUDIO INTERFACE SETTING FOR
DAC34
DMS34[3:0]
0000
DMS34[3:0]
1000
Reserved
Slave and system clock fS auto-detect mode (default)
Slave and system clock 768 fS
Slave and system clock 512 fS
Slave and system clock 384 fS
Slave and system clock 256 fS
Slave and system clock 192 fS
Slave and system clock 128 fS
Reserved
0001
Master and system clock 768 fS
Master and system clock 512 fS
Master and system clock 384 fS
Master and system clock 256 fS
Master and system clock 192 fS
Master and system clock 128 fS
Reserved
1001
0010
1010
0011
1011
0100
1100
0101
1101
0110
1110
0111
1111
DFM34[1:0]: Audio Interface Format for DAC34
These bits select the DAC34 audio data format as I2S, right-justified, or left-justified.
Default value: 00
00
01
10
11
16 to 24 bits, I2S (default)
16 to 24 bits, left-justified
24 bits, right-justified
16 bits, right-justified
DM34: De-Emphasis Filter Enable for DAC34
This bit enables the DAC34 de-emphasis filter. The frequency can be selected by setting bits DF34[1:0] of
Register 55.
Default value: 0
0
1
Disable (default)
Enable
DF34[1:0]: De-Emphasis Filter Sampling Rate Selection for DAC34
A digital de-emphasis filter is in front of the interpolation filter. One of three de-emphasis filters can be selected
corresponding to the sampling rate: 32 kHz, 44.1 kHz, or 48 kHz.
Default value: 00
00
01
10
11
44.1 kHz (default)
48 kHz
32 kHz
Reserved
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Register 56 (38h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
56
38h
Power up/down, oversampling rate control for DAC34 PD34 RSV
OV34[1:0]
ZR34 RSV
RSV
RSV
PD34: Power Up/Down Control for DAC34
This bit controls the power up/down for DAC34, including the interpolation filter.
Default value: 1
0
1
Power up
Power down (default)
OV34[1:0]: Oversampling Rate Control for DAC34
These bits control the oversampling rate of the DAC34 delta-sigma modulator.
Default value: 01
SYSTEM CLOCK RATE
OV34
128 fS, 192 fS
16 fS
256 fS, 384 fS
128 fS, 192 fS
64 fS
00
01 (default)
10
32 fS
64 fS
—
32 fS
128 fS
—
(1)
(1)
11
32 fS
128 fS
128 fS
(1) Less than fS = 48 kHz
ZR34: Zero Flag Reverse
This bit reverses the polarity of the zero flag output. The zero flag is high after input data are zero during 1024 fS
when ZR34 = '0', and is set with the GPIO port by bits GSL1[4:0], GSL2[4:0], GSL3[4:0] in registers 09 to 11.
Default value: 0
0
1
Buffered output (default)
Inverted output
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Registers 80 and 81 (50h and 51h)
REG
80
HEX
50h
51h
DESCRIPTION
B7
B6
RSV AUC2 AUC1 RSV
FS12 RSV RSV RSV
B5
B4
B3
B2
B1
B0
Digital attenuation and mute control for ADC12
Digital soft mute for ADC12
A12E
RSV
RSV
RSV
AZ12
81
RSV AMU2 AMU1
A12E: Digital Attenuation and Mute Update Control Enable for ADC12
AUC2: Digital Attenuation and Mute Setting Update for ADC12, R-Channel
AUC1: Digital Attenuation and Mute Setting Update for ADC12, L-Channel
The digital attenuation and mute levels of ADC12 can be changed independently to any level by setting bits
AMU2 and AMU1 in Register 81, bits AAT1[7:0] in Register 82, and bits AAT2[7:0] in Register 83 when A12E =
'0'. When A12E = '1', the level is changed to any level at the same time when AUC2 = '1' or AUC1 = '1'. Both bits
are automatically set to '0' after they are set to '1'. AUC2 and AUC1 must be set to '1' for every volume level
setting while A12E = '1'.
Default value of A12E: 1. Default value of AUC2 and AUC1: 0
A12E = 0 Digital attenuation and mute update control disabled
A12E = 1 Digital attenuation and mute update control enabled (default)
AUC2, AUC1 = 0 No update level (default)
AUC2, AUC1 = 1 Update level (set to '1' automatically after setting to '0')
AZ12: Digital Attenuation and Mute Zero Crossing Enable for ADC12
This bit enables zero-crossing detection, which reduces zipper noise while the ADC digital attenuator and mute
settings are being changed. If no zero-crossing data are input for a 512/fS period (10.6 ms at a 48-kHz sampling
rate), then a timeout occurs and the PCM5310 volume level changes. Zero-crossing detection cannot be used
with continuous zero and dc data.
Default value: 1
0
1
Disable
Enable (default)
FS12: Sampling Rate Selection for ADC12
This bit is used to select the ADS12 sampling rate. FS12 must be set to '1' when the sampling rate is greater
than 48 kHz.
Default value: 0
0
1
f
S ≤ 48 kHz (default)
fS > 48 kHz
AMU2: Digital Mute Control for ADC12, R-Channel
AMU1: Digital Mute Control for ADC12, L-Channel
The PCM5310 can independently mute the DAC digital input data to a zero level when AMU2 and AMU1 = '1'.
These settings take precedence over the attenuation level settings of bits AAT1[7:0] and AAT2[7:0] in registers
82 and 83. The analog outputs may have audible zipper noise while changing levels. This noise can be reduced
by selecting zero-crossing detection (Register 80, AZ12).
Default value: 0
0
1
Mute disabled (default)
Mute enabled
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Registers 82 and 83 (52h and 53h)
REG
82
HEX
52h
53h
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Digital attenuation level setting for ADC12 L-channel
Digital attenuation level setting for ADC12 R-channel
AAT1[7:0]
AAT2[7:0]
83
AAT1[7:0]: Digital Attenuation Setting for ADC12, L-Channel
AAT2[7:0]: Digital Attenuation Setting for ADC12, R-Channel
The digital attenuator of ADC12 can be independently set from 20 dB to –100 dB in 0.5-dB steps. The ADC12
output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero
crossing detection (Register 80, AZ12).
Default value : 1101 0111
Table 35. Digital Attenuation Level Setting for ADC12
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
1111 1111 FF
1111 1110 FE
1111 1101 FD
1111 1100 FC
1111 1011 FB
1111 1010 FA
1111 1001 F9
1111 1000 F8
1111 0111 F7
1111 0110 F6
1111 0101 F5
1111 0100 F4
1111 0011 F3
1111 0010 F2
1111 0001 F1
1111 0000 F0
1110 1111 EF
1110 1110 EE
1110 1101 ED
1110 1100 EC
1110 1011 EB
1110 1010 EA
1110 1001 E9
1110 1000 E8
1110 0111 E7
1110 0110 E6
1110 0101 E5
1110 0100 E4
1110 0011 E3
1110 0010 E2
1110 0001 E1
1110 0000 E0
1101 1111 DF
20 dB
19.5 dB
19 dB
18.5 dB
18 dB
17.5 dB
17 dB
16.5 dB
16 dB
15.5 dB
15 dB
14.5 dB
14 dB
13.5 dB
13 dB
12.5 dB
12 dB
11.5 dB
11 dB
10.5 dB
10 dB
9.5 dB
9 dB
1100 0010 C2
1100 0001 C1
1100 0000 C0
1011 1111 BF
1011 1110 BE
1011 1101 BD
1011 1100 BC
1011 1011 BB
1011 1010 BA
1011 1001 B9
1011 1000 B8
1011 0111 B7
1011 0110 B6
1011 0101 B5
1011 0100 B4
1011 0011 B3
1011 0010 B2
1011 0001 B1
1011 0000 B0
1010 1111 AF
1010 1110 AE
1010 1101 AD
1010 1100 AC
1010 1011 AB
1010 1010 AA
1010 1001 A9
1010 1000 A8
1010 0111 A7
1010 0110 A6
1010 0101 A5
1010 0100 A4
1010 0011 A3
1010 0010 A2
–10.5 dB
–11 dB
1000 0101 85
1000 0100 84
1000 0011 83
1000 0010 82
1000 0001 81
1000 0000 80
0111 1111 7F
0111 1110 7E
0111 1101 7D
0111 1100 7C
0111 1011 7B
0111 1010 7A
0111 1001 79
0111 1000 78
0111 0111 77
0111 0110 76
0111 0101 75
0111 0100 74
0111 0011 73
0111 0010 72
0111 0001 71
0111 0000 70
0110 1111 6F
0110 1110 6E
0110 1101 6D
0110 1100 6C
0110 1011 6B
0110 1010 6A
0110 1001 69
0110 1000 68
0110 0111 67
0110 0110 66
0110 0101 65
–41 dB
–41.5 dB
–42 dB
0100 1000 48
0100 0111 47
0100 0110 46
0100 0101 45
0100 0100 44
0100 0011 43
0100 0010 42
0100 0001 41
0100 0000 40
0011 1111 3F
0011 1110 3E
0011 1101 3D
0011 1100 3C
0011 1011 3B
0011 1010 3A
0011 1001 39
0011 1000 38
0011 0111 37
0011 0110 36
0011 0101 35
0011 0100 34
0011 0011 33
0011 0010 32
0011 0001 31
0011 0000 30
0010 1111 2F
0010 1110 2E
0010 1101 2D
0010 1100 2C
0010 1011 2B
0010 1010 2A
0010 1001 29
0010 1000 28
–71.5 dB
–72 dB
–11.5 dB
–12 dB
–72.5 dB
–73 dB
–42.5 dB
–43 dB
–12.5 dB
–13 dB
–73.5 dB
–74 dB
–43.5 dB
–44 dB
–13.5 dB
–14 dB
–74.5 dB
–75 dB
–44.5 dB
–45 dB
–14.5 dB
–15 dB
–75.5 dB
–76 dB
–45.5 dB
–46 dB
–15.5 dB
–16 dB
–76.5 dB
–77 dB
–46.5 dB
–47 dB
–16.5 dB
–17 dB
–77.5 dB
–78 dB
–47.5 dB
–48 dB
–17.5 dB
–18 dB
–78.8 dB
–79 dB
–48.5 dB
–49 dB
–18.5 dB
–19 dB
–79.5 dB
–80 dB
–49.5 dB
–50 dB
–19.5 dB
–20 dB
–80.5 dB
–81 dB
–50.5 dB
– 51 dB
–51.5 dB
–52 dB
–20.5 dB
–21 dB
–81.5 dB
–82 dB
–21.5 dB
–22 dB
–82.5 dB
–83 dB
8.5 dB
8 dB
–52.5 dB
–53 dB
–22.5 dB
–23 dB
–83.5 dB
–84 dB
7.5 dB
7 dB
–53.5 dB
–54 dB
–23.5 dB
–24 dB
–84.5 dB
–85 dB
6.5 dB
6 dB
–54.5 dB
–55 dB
–24.5 dB
–25 dB
–85.5 dB
–86 dB
5.5 dB
5 dB dB
4.5 dB
4 dB
–55.5 dB
–56 dB
–25.5 dB
–26 dB
–86.5 dB
–87 dB
–56.5 dB
–57 dB
–26.5 dB
–87.5 dB
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Table 35. Digital Attenuation Level Setting for ADC12 (continued)
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
1101 1110 DE
1101 1101 DD
1101 1100 DC
1101 1011 DB
1101 1010 DA
1101 1001 D9
1101 1000 D8
3.5 dB
3 dB
1010 0001 A1
1010 0000 A0
1001 1111 9F
1001 1110 9E
1001 1101 9D
1001 1100 9C
1001 1011 9B
1001 1010 9A
1001 1001 99
1001 1000 98
1001 0111 97
1001 0110 96
1001 0101 95
1001 0100 94
1001 0011 93
1001 0010 92
1001 0001 91
1001 0000 90
1000 1111 8F
1000 1110 8E
1000 1101 8D
1000 1100 8C
1000 1011 8B
1000 1010 8A
1000 1001 89
1000 1000 88
1000 0111 87
1000 0110 86
–27 dB
–27.5 dB
–28 dB
0110 0100 64
0110 0011 63
0110 0010 62
0110 0001 61
0110 0000 60
0101 1111 5F
0101 1110 5E
0101 1101 5D
0101 1100 5C
0101 1011 5B
0101 1010 5A
0101 1001 59
0101 1000 58
0101 0111 57
0101 0110 56
0101 0101 55
0101 0100 54
0101 0011 53
0101 0010 52
0101 0001 51
0101 0000 50
0100 1111 4F
0100 1110 4E
0100 1101 4D
0100 1100 4C
0100 1011 4B
0100 1010 4A
0100 1001 49
–57.5 dB
–58 dB
0010 0111 27
0010 0110 26
0010 0101 25
0010 0100 24
0010 0011 23
0010 0010 22
0010 0001 21
0010 0000 20
0001 1111 1F
0001 1110 1E
0001 1101 1D
0001 1100 1C
0001 1011 1B
0001 1010 1A
0001 1001 19
0001 1000 18
0001 0111 17
0001 0110 16
0001 0101 15
0001 0100 14
0001 0011 13
0001 0010 12
0001 0001 11
0001 0000 10
0000 1111 0F
–88 dB
–88.5 dB
–89 dB
2.5 dB
2 dB
–58.5 dB
–59 dB
–28.5 dB
–29 dB
–89.5 dB
–90 dB
1.5 dB
1 dB
–59.5 dB
–60 dB
–29.5 dB
–30 dB
–90.5 dB
–91 dB
0.5 dB
–60.5 dB
–61 dB
1101 0111 D7 0 dB (default)
–30.5 dB
–31 dB
–91.5 dB
–92 dB
1101 0110 D6
1101 0101 D5
1101 0100 D4
1101 0011 D3
1101 0010 D2
1101 0001 D1
1101 0000 D0
1100 1111 CF
1100 1110 CE
1100 1101 CD
1100 1100 CC
1100 1011 CB
1100 1010 CA
1100 1001 C9
1100 1000 C8
1100 0111 C7
1100 0110 C6
1100 0101 C5
1100 0100 C4
1100 0011 C3
–0.5 dB
–1 dB
–61.5 dB
–62 dB
–31.5 dB
–32 dB
–92.5 dB
–93 dB
–1.5 dB
–2 dB
–62.5 dB
–63 dB
–32.5 dB
–33 dB
–93.5 dB
–94 dB
–2.5 dB
–3 dB
–63.5 dB
–64 dB
–33.5 dB
–34 dB
–94.5 dB
–95 dB
–3.5 dB
–4 dB
–64.5 dB
–65 dB
–34.5 dB
–35 dB
–95.5 dB
–96 dB
–4.5 dB
–5 dB
–65.5 dB
–66 dB
–35.5 dB
–36 dB
–96.5 dB
–97 dB
–5.5 dB
–6 dB
–66.5 dB
–67 dB
–36.5 dB
–37 dB
–97.5 dB
–98 dB
–6.5 dB
–7 dB
–67.5 dB
–68 dB
–37.5 dB
–38 dB
–98.5 dB
–99 dB
–7.5 dB
–8 dB
–68.5 dB
–69 dB
–38.5 dB
–39 dB
–99.5 dB
–100 dB
–8.5 dB
–9 dB
–69.5 dB
–70 dB
–39.5 dB
–40 dB
0000 1110 0E
–9.5 dB
–10 dB
–70.5 dB
–71 dB
⋮
⋮
Mute
0000 0000 00
–40.5 dB
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Register 84 (54h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
84
54h
Master/slave interface format for ADC12
AMS12[3:0]
HF12
RSV
AFM12[1:0]
AMS12[3:0]: Master/Slave Audio Interface Setting for ADC12
These bits set the master or slave mode. ADC12 receives LRCK and BCK from PORT-1, PORT-2, PORT-3,
PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode.
Default value: 1000
MASTER/SLAVE AUDIO INTERFACE SETTING FOR
ADC12
MASTER/SLAVE AUDIO INTERFACE SETTING FOR
ADC12
AMS12[3:0]
0000
AMS12[3:0]
1000
Reserved
Slave and system clock fS auto-detect mode (default)
Slave and system clock 768 fS
Slave and system clock 512 fS
Slave and system clock 384 fS
Slave and system clock 256 fS
Reserved
0001
Master and system clock 768 fS
Master and system clock 512 fS
Master and system clock 384 fS
Master and system clock 256 fS
Reserved
1001
0010
1010
0011
1011
0100
1100
0101
1101
0110
Reserved
1110
Reserved
0111
Reserved
1111
Reserved
HF12: High-Pass Filter Disable for ADC12
This bit disables the digital high-pass filter of ADC12.
Default value: 0
0
1
(0.019 fS/1000) Hz (default)
Off
AFM12[1:0]: Audio Interface Format for ADC12
These bits select the ADC12 audio data format as I2S, right-justified, or left-justified.
Default value: 00
00
01
10
11
16 to 24 bits, I2S (default)
16 to 24 bits, left-justified
24 bits, right-justified
16 bits, right-justified
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Register 85 (55h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
85
55h
Power up/down for ADC12
PA12
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PA12: Power Up/Down Control for ADC12
This bit controls the power up/down for ADC12, including the decimation filter.
Default value: 1
0
1
Power up
Power down (default)
Register 90 (5Ah)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
90
5Ah
Digital attenuation and mute control for ADC34
A34E
RSV AUC4 AUC3 RSV
RSV
RSV
AZ34
A34E: Digital Attenuation and Mute Update Control Enable for ADC34
AUC4: Digital Attenuation and Mute Setting Update for ADC34, R-Channel
AUC3: Digital Attenuation and Mute Setting Update for ADC34, L-Channel
The digital attenuation and mute levels of ADC12 can be changed independently to any level by setting bits
AMU4 and AMU3 in Register 91, bits AAT3[7:0] in Register 92, and bits AAT4[7:0] in Register 93 when
A34E = '0'. When A34E = '1', the level is changed to any level at the same time when AUC4 = '1' or AUC3 = '1'.
Both bits are automatically set to '0' after they are to '1'. AUC4 and AUC3 must be set to '1' for every volume
level setting while A34E = '1'.
Default value of A34E: 1. Default value of AUC4 and AUC3: 0
A34E = 0 Digital attenuation and mute update control disabled
A34E = 1 Digital attenuation and mute update control enabled (default)
AUC4, AUC3 = 0 No update level (default)
AUC4, AUC3 = 1 Update level (set to '0' automatically after setting to '1')
AZ34: Digital Attenuation and Mute Zero Cross Enable for ADC34
This bit enables zero-crossing detection, which reduces zipper noise while the ADC digital attenuator and mute
settings are being changed. If no zero-crossing data are input for a 512/fS period (10.6 ms at a 48-kHz sampling
rate), then a timeout occurs and the PCM5310 volume level changes. Zero-crossing detection cannot be used
with continuous zero and dc data.
Default value: 1
0
1
Disable
Enable (default)
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Register 91 (5Bh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
91
5Bh
Digital soft mute for ADC34
RSV
FS34
RSV
RSV
RSV
RSV AMU4 AMU3
FS34: Sampling Rate Selection for ADC34
This bit sets the ADS34 sampling rate. FS34 must be set to '1' when the sampling rate is greater than 48 kHz.
Default value: 0
0
1
f
S ≤ 48 kHz (default)
fS > 48 kHz
AMU4: Digital Mute Control for ADC34, R-Channel
AMU3: Digital Mute Control for ADC34, L-Channel
The PCM5310 can independently mute the DAC digital input data to a zero level when AMU4 and AMU3 = '1'.
These settings take precedence over the attenuation level settings of bits AAT3[7:0] and AAT4[7:0] in registers
92 and 93. The analog outputs may have audible zipper noise while changing levels. This noise can be reduced
by selecting zero-crossing detection (Register 90, AZ34).
Default value: 0
0
1
Mute disabled (default)
Mute enabled
Registers 92 and 93 (5Ch and 5Dh)
REG
92
HEX
5Ch
5Dh
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
Digital attenuation level setting for ADC34 L-channel
Digital attenuation level setting for ADC34 R-channel
AAT3[7:0]
AAT4[7:0]
93
AAT3[7:0]: Digital Attenuation Setting for ADC34, L-Channel
AAT4[7:0]: Digital Attenuation Setting for ADC34, R-Channel
The digital attenuator of ADC34 can be independently set from 20 dB to –100 dB in 0.5-dB steps. The ADC34
output may have audible zipper noise while changing levels. This noise can be reduced by selecting zero
crossing detection (Register 90, AZ34).
Default value : 1101 0111
Table 36. Digital Attenuation Level Setting for ADC34
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
1111 1111
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
20 dB
19.5 dB
19 dB
1100 0010
C2
C1
C0
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
B5
B4
–10.5 dB
–11 dB
1000 0101
85
84
83
82
81
80
7F
7E
7D
7C
7B
7A
79
78
77
–41 dB
–41.5 dB
–42 dB
0100 1000
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
–71.5 dB
–72 dB
1111 1110
1111 1101
1111 1100
1111 1011
1111 1010
1111 1001
1111 1000
1111 0111
1111 0110
1111 0101
1111 0100
1111 0011
1111 0010
1111 0001
1100 0001
1100 0000
1011 1111
1011 1110
1011 1101
1011 1100
1011 1011
1011 1010
1011 1001
1011 1000
1011 0111
1011 0110
1011 0101
1011 0100
1000 0100
1000 0011
1000 0010
1000 0001
1000 0000
0111 1111
0111 1110
0111 1101
0111 1100
0111 1011
0111 1010
0111 1001
0111 1000
0111 0111
0100 0111
0100 0110
0100 0101
0100 0100
0100 0011
0100 0010
0100 0001
0100 0000
0011 1111
0011 1110
0011 1101
0011 1100
0011 1011
0011 1010
–11.5 dB
–12 dB
–72.5 dB
–73 dB
18.5 dB
18 dB
–42.5 dB
–43 dB
–12.5 dB
–13 dB
–73.5 dB
–74 dB
17.5 dB
17 dB
–43.5 dB
–44 dB
–13.5 dB
–14 dB
–74.5 dB
–75 dB
16.5 dB
16 dB
–44.5 dB
–45 dB
–14.5 dB
–15 dB
–75.5 dB
–76 dB
15.5 dB
15 dB
–45.5 dB
–46 dB
–15.5 dB
–16 dB
–76.5 dB
–77 dB
14.5 dB
14 dB
–46.5 dB
–47 dB
–16.5 dB
–17 dB
–77.5 dB
–78 dB
13.5 dB
13 dB
–47.5 dB
–48 dB
–17.5 dB
–78.8 dB
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Table 36. Digital Attenuation Level Setting for ADC34 (continued)
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
DIGITAL ATT
LEVEL
SETTING
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
AAT1[7:0]
AAT2[7:0]
1111 0000
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
C5
C4
C3
12.5 dB
12 dB
1011 0011
B3
B2
B1
B0
AF
AE
AD
AC
AB
AA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
9F
9E
9D
9C
9B
9A
99
98
97
96
95
94
93
92
91
90
8F
8E
8D
8C
8B
8A
89
88
87
86
–18 dB
–18.5 dB
–19 dB
0111 0110
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
–48.5 dB
–49 dB
0011 1001
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
13
12
11
10
0F
–79 dB
–79.5 dB
–80 dB
1110 1111
1110 1110
1110 1101
1110 1100
1110 1011
1110 1010
1110 1001
1110 1000
1110 0111
1110 0110
1110 0101
1110 0100
1110 0011
1110 0010
1110 0001
1110 0000
1101 1111
1101 1110
1101 1101
1101 1100
1101 1011
1101 1010
1101 1001
1101 1000
1101 0111
1101 0110
1101 0101
1101 0100
1101 0011
1101 0010
1101 0001
1101 0000
1100 1111
1100 1110
1100 1101
1100 1100
1100 1011
1100 1010
1100 1001
1100 1000
1100 0111
1100 0110
1100 0101
1100 0100
1100 0011
1011 0010
1011 0001
1011 0000
1010 1111
1010 1110
1010 1101
1010 1100
1010 1011
1010 1010
1010 1001
1010 1000
1010 0111
1010 0110
1010 0101
1010 0100
1010 0011
1010 0010
1010 0001
1010 0000
1001 1111
1001 1110
1001 1101
1001 1100
1001 1011
1001 1010
1001 1001
1001 1000
1001 0111
1001 0110
1001 0101
1001 0100
1001 0011
1001 0010
1001 0001
1001 0000
1000 1111
1000 1110
1000 1101
1000 1100
1000 1011
1000 1010
1000 1001
1000 1000
1000 0111
1000 0110
0111 0101
0111 0100
0111 0011
0111 0010
0111 0001
0111 0000
0110 1111
0110 1110
0110 1101
0110 1100
0110 1011
0110 1010
0110 1001
0110 1000
0110 0111
0110 0110
0110 0101
0110 0100
0110 0011
0110 0010
0110 0001
0110 0000
0101 1111
0101 1110
0101 1101
0101 1100
0101 1011
0101 1010
0101 1001
0101 1000
0101 0111
0101 0110
0101 0101
0101 0100
0101 0011
0101 0010
0101 0001
0101 0000
0100 1111
0100 1110
0100 1101
0100 1100
0100 1011
0100 1010
0100 1001
0011 1000
0011 0111
0011 0110
0011 0101
0011 0100
0011 0011
0011 0010
0011 0001
0011 0000
0010 1111
0010 1110
0010 1101
0010 1100
0010 1011
0010 1010
0010 1001
0010 1000
0010 0111
0010 0110
0010 0101
0010 0100
0010 0011
0010 0010
0010 0001
0010 0000
0001 1111
0001 1110
0001 1101
0001 1100
0001 1011
0001 1010
0001 1001
0001 1000
0001 0111
0001 0110
0001 0101
0001 0100
0001 0011
0001 0010
0001 0001
0001 0000
0000 1111
11.5 dB
11 dB
–49.5 dB
–50 dB
–19.5 dB
–20 dB
–80.5 dB
–81 dB
10.5 dB
10 dB
–50.5 dB
– 51 dB
–51.5 dB
–52 dB
–20.5 dB
–21 dB
–81.5 dB
–82 dB
9.5 dB
9 dB
–21.5 dB
–22 dB
–82.5 dB
–83 dB
8.5 dB
8 dB
–52.5 dB
–53 dB
–22.5 dB
–23 dB
–83.5 dB
–84 dB
7.5 dB
7 dB
–53.5 dB
–54 dB
–23.5 dB
–24 dB
–84.5 dB
–85 dB
6.5 dB
6 dB
–54.5 dB
–55 dB
–24.5 dB
–25 dB
–85.5 dB
–86 dB
5.5 dB
5 dB dB
4.5 dB
4 dB
–55.5 dB
–56 dB
–25.5 dB
–26 dB
–86.5 dB
–87 dB
–56.5 dB
–57 dB
–26.5 dB
–27 dB
–87.5 dB
–88 dB
3.5 dB
3 dB
–57.5 dB
–58 dB
–27.5 dB
–28 dB
–88.5 dB
–89 dB
2.5 dB
2 dB
–58.5 dB
–59 dB
–28.5 dB
–29 dB
–89.5 dB
–90 dB
1.5 dB
1 dB
–59.5 dB
–60 dB
–29.5 dB
–30 dB
–90.5 dB
–91 dB
0.5 dB
0 dB (default)
–0.5 dB
–1 dB
–60.5 dB
–61 dB
–30.5 dB
–31 dB
–91.5 dB
–92 dB
–61.5 dB
–62 dB
–31.5 dB
–32 dB
–92.5 dB
–93 dB
–1.5 dB
–2 dB
–62.5 dB
–63 dB
–32.5 dB
–33 dB
–93.5 dB
–94 dB
–2.5 dB
–3 dB
–63.5 dB
–64 dB
–33.5 dB
–34 dB
–94.5 dB
–95 dB
–3.5 dB
–4 dB
–64.5 dB
–65 dB
–34.5 dB
–35 dB
–95.5 dB
–96 dB
–4.5 dB
–5 dB
–65.5 dB
–66 dB
–35.5 dB
–36 dB
–96.5 dB
–97 dB
–5.5 dB
–6 dB
–66.5 dB
–67 dB
–36.5 dB
–37 dB
–97.5 dB
–98 dB
–6.5 dB
–7 dB
–67.5 dB
–68 dB
–37.5 dB
–38 dB
–98.5 dB
–99 dB
–7.5 dB
–8 dB
–68.5 dB
–69 dB
–38.5 dB
–39 dB
–99.5 dB
–100 dB
–8.5 dB
–9 dB
–69.5 dB
–70 dB
–39.5 dB
–40 dB
0000 1110
⋮
0000 0000
0E
⋮
00
–9.5 dB
–10 dB
–70.5 dB
–71 dB
Mute
–40.5 dB
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Register 94 (5Eh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
94
5Eh
Master/slave interface format for ADC34
AMS34[3:0]
HF34
RSV
AFM34[1:0]
AMS34[3:0]: Master/Slave Audio Interface Setting for ADC34
These bits set the master or slave mode. ADC34 receives LRCK and BCK from PORT-1, PORT-2, PORT-3,
PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode.
Default value: 1000
MASTER/SLAVE AUDIO INTERFACE SETTING FOR
ADC34
MASTER/SLAVE AUDIO INTERFACE SETTING FOR
ADC34
AMS34[3:0]
0000
AMS34[3:0]
1000
Reserved
Slave and system clock fS auto-detect mode (default)
Slave and system clock 768 fS
Slave and system clock 512 fS
Slave and system clock 384 fS
Slave and system clock 256 fS
Reserved
0001
Master and system clock 768 fS
Master and system clock 512 fS
Master and system clock 384 fS
Master and system clock 256 fS
Reserved
1001
0010
1010
0011
1011
0100
1100
0101
1101
0110
Reserved
1110
Reserved
0111
Reserved
1111
Reserved
HF34: High-Pass Filter Disable for ADC34
This bit disables the digital high-pass filter of ADC34.
Default value: 0
0
1
(0.019 fS/1000) Hz (default)
Off
AFM34[1:0]: Audio Interface Format for ADC34
These bits select the ADC34 audio data format as I2S, right-justified, or left-justified.
Default value: 00
00
01
10
11
16 to 24 bits, I2S (default)
16 to 24 bits, left-justified
24 bits, right-justified
16 bits, right-justified
Register 95 (5Fh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
95
5Fh
Power up/down for ADC34
PA34
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PA34: Power Up/Down Control for ADC34
This bit controls the power up/down for ADC34, including the decimation filter.
Default value: 1
0
1
Power up
Power down (default)
Register 101 (65h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
101
65h
LRCK/BCK selection of PORT-1 and PORT-2
LBS2[3:0]
LBS1[3:0]
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LBS2[3:0]: LRCK/BCK Selection of PORT-2 (MUX_P2BL)
These bits are used for routing LRCK and BCK of PORT-2. Any combination of LRCK1/BCK1 to LRCK6/BCK6
and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-2. Figure 47 shows a detailed
diagram of PORT-2.
Default value: 0001
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output LRCK1 and BCK1
Input LRCK2 and BCK2 (default)
Output LRCK3 and BCK3
Output LRCK4 and BCK4
Output LRCK5 and BCK5
Output LRCK6 and BCK6
Output LRCK and BCK from DAC12 in master mode
Output LRCK and BCK from DAC34 in master mode
Output LRCK and BCK from ADC12 in master mode
Output LRCK and BCK from ADC34 in master mode
Others Reserved
PORT-2
LRCK/BCK to MUX_ADCxx and MUXDACxx
LRCK2
BCK2
LRCK1
BCK1
LRCK3
BCK3
LRCK4
BCK4
LRCK5
BCK5
LRCK6
BCK6
Register 101
LBS2[3:0]
LRCK, BCK from ADC12 at Master
LRCK, BCK from ADC34 at Master
LRCK, BCK from DAC12 at Master
LRCK, BCK from DAC34 at Master
SCK to MUX_ADCxx and MUXDACxx
SCK2
SCK1
SCK3
SCK4
SCK5
SCK6
Register 103
SCS2[2:0]
DATA to MUXDACxx
DATA2
DATA1
DATA3
DATA4
DATA5
DATA6
DATA from ADC12
DATA from ADC34
DATA from GPIO1
DATA from GPIO2
Register 102
DTS2[3:0]
Figure 47. Detailed Diagram of PORT-2
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LBS1[3:0]: LRCK/BCK Selection of PORT-1 (MUX_P2BL)
These bits are used for routing LRCK and BCK of PORT-1. Any combination of LRCK1/BCK1 to LRCK6/BCK6
and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-1. Figure 48 shows a detailed
diagram of PORT-1.
Default value: 0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Input LRCK1 and BCK1 (default)
Output LRCK2 and BCK2
Output LRCK3 and BCK3
Output LRCK4 and BCK4
Output LRCK5 and BCK5
Output LRCK6 and BCK6
Output LRCK and BCK from DAC12 in master mode
Output LRCK and BCK from DAC34 in master mode
Output LRCK and BCK from ADC12 in master mode
Output LRCK and BCK from ADC34 in master mode
Others Reserved
PORT-1
LRCK/BCK to MUX_ADCxx and MUXDACxx
LRCK1
BCK1
LRCK2
BCK2
LRCK3
BCK3
LRCK4
BCK4
LRCK5
BCK5
LRCK6
BCK6
Register 101
LBS1[3:0]
LRCK, BCK from ADC12 at Master
LRCK, BCK from ADC34 at Master
LRCK, BCK from DAC12 at Master
LRCK, BCK from DAC34 at Master
SCK to MUX_ADCxx and MUXDACxx
SCK1
SCK2
SCK3
SCK4
SCK5
SCK6
Register 103
SCS1[2:0]
DATA to MUXDACxx
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
Register 102
DTS1[3:0]
DATA from ADC12
DATA from ADC34
DATA from GPIO1
DATA from GPIO2
Figure 48. Detailed Diagram of PORT-1
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Register 102 (66h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
102
66h
DATA selection of PORT-1 and PORT-2
DTS2[3:0]
DTS1[3:0]
DTS2[3:0]: DATA Selection of PORT-2 (MUX_P2DT)
These bits are used for routing DATA of PORT-2. Any combination of DATA1 to DATA6 and DATA of ADCs in
master mode can be connected to PORT-2. Refer to Figure 47 for more details.
Default value: 0001
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output DATA1
Input DATA2 (default)
Output DATA3
Output DATA4
Output DATA5
Output DATA6
Output GPIO1
Output GPIO2
Output DATA from ADC12
Output DATA from ADC34
Others Reserved
DTS1[3:0]: DATA Selection of PORT-1 (MUX_P1DT)
These bits are used for routing DATA of PORT-1. Any combination of DATA1 to DATA6 and DATA of ADCs in
master mode can be connected to PORT-1. Refer to Figure 48 for more details.
Default value: 0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Input DATA1 (default)
Output DATA2
Output DATA3
Output DATA4
Output DATA5
Output DATA6
Output GPIO1
Output GPIO2
Output DATA from ADC12
Output DATA from ADC34
Others Reserved
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Register 103 (67h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
103
67h
SCK selection of PORT-1 and PORT-2
RSV
SCS2[3:0]
RSV
SCS1[3:0]
SCS2[3:0]: SCK Selection of PORT-2 (MUX_P2SC)
These bits are used for routing SCK of PORT-2. Any combination of SCK1 to SCK6 and SCK can be connected
to PORT-2. Refer to Figure 47 for more details.
Default value: 001
000
001
010
011
100
101
Output SCK1
Input SCK2 (default)
Output SCK3
Output SCK4
Output SCK5
Output SCK6
Others Reserved
SCS1[3:0]: SCK Selection of PORT-1 (MUX_P1SC)
These bits are used for routing SCK of PORT-2. Any combination of SCK1 to SCK6 and SCK can be connected
to PORT-1. Refer to Figure 48 for more details.
Default value: 000
000
001
010
011
100
101
Input SCK1 (default)
Output SCK2
Output SCK3
Output SCK4
Output SCK5
Output SCK6
Others Reserved
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Register 104 (68h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
104
68h
LRCK/BCK selection of PORT-3 and PORT-4
LBS4[3:0]
LBS3[3:0]
LBS4[3:0]: LRCK/BCK Selection of PORT-4 (MUX_P4BL)
These bits are used for routing LRCK and BCK of PORT-4. Any combination of LRCK1/BCK1 to LRCK6/BCK6
and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-4. Figure 49 shows a detailed
diagram of PORT-4.
Default value: 0011
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output LRCK1 and BCK1
Output LRCK2 and BCK2
Output LRCK3 and BCK3
Input LRCK4 and BCK4 (default)
Output LRCK5 and BCK5
Output LRCK6 and BCK6
Output LRCK and BCK from DAC12 in master mode
Output LRCK and BCK from DAC34 in master mode
Output LRCK and BCK from ADC12 in master mode
Output LRCK and BCK from ADC34 in master mode
Others Reserved
PORT-4
LRCK/BCK to MUX_ADCxx and MUXDACxx
LRCK4
BCK4
LRCK1
BCK1
LRCK2
BCK2
LRCK3
BCK3
LRCK5
BCK5
LRCK6
BCK6
Register 104
LBS4[3:0]
LRCK, BCK from ADC12 at Master
LRCK, BCK from ADC34 at Master
LRCK, BCK from DAC12 at Master
LRCK, BCK from DAC34 at Master
SCK to MUX_ADCxx and MUXDACxx
SCK4
SCK1
SCK2
SCK3
SCK5
SCK6
Register 106
SCS1[2:0]
DATA to MUXDACxx
DATA4
DATA1
DATA2
DATA3
DATA5
DATA6
DATA from ADC12
DATA from ADC34
DATA from GPIO1
DATA from GPIO2
Register 105
DTS4[3:0]
Figure 49. Detailed Diagram of PORT-4
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LBS3[3:0]: LRCK/BCK Selection of PORT-3 (MUX_P3BL)
These bits are used for routing LRCK and BCK of PORT-3. Any combination of LRCK1/BCK1 to LRCK6/BCK6
and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-3. Figure 50 shows a detailed
diagram of PORT-3.
Default value: 0010
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output LRCK1 and BCK1
Output LRCK2 and BCK2
Input LRCK3 and BCK3 (default)
Output LRCK4 and BCK4
Output LRCK5 and BCK5
Output LRCK6 and BCK6
Output LRCK and BCK from DAC12 in master mode
Output LRCK and BCK from DAC34 in master mode
Output LRCK and BCK from ADC12 in master mode
Output LRCK and BCK from ADC34 in master mode
Others Reserved
PORT-3
LRCK/BCK to MUX_ADCxx and MUXDACxx
LRCK3
BCK3
LRCK1
BCK1
LRCK2
BCK2
LRCK4
BCK4
LRCK5
BCK5
LRCK6
BCK6
Register 104
LBS3[3:0]
LRCK, BCK from ADC12 at Master
LRCK, BCK from ADC34 at Master
LRCK, BCK from DAC12 at Master
LRCK, BCK from DAC34 at Master
SCK to MUX_ADCxx and MUXDACxx
SCK3
SCK1
SCK2
SCK4
SCK5
SCK6
Register 106
SCS3[2:0]
DATA to MUXDACxx
DATA3
DATA1
DATA2
DATA4
DATA5
DATA6
DATA from ADC12
DATA from ADC34
DATA from GPIO1
DATA from GPIO2
Register 105
DTS3[3:0]
Figure 50. Detailed Diagram of PORT-3
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Register 105 (69h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
105
69h
DATA selection of PORT-3 and PORT-4
DTS4[3:0]
DTS3[3:0]
DTS4[3:0]: DATA Selection of PORT-4 (MUX_P4DT)
These bits are used for routing DATA of PORT-4. Any combination of DATA1 to DATA6 and DATA of ADCs in
master mode can be connected to PORT-4. Refer to Figure 49 for more details.
Default value: 0011
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output DATA1
Output DATA2
Output DATA3
Input DATA4 (default)
Output DATA5
Output DATA6
Output GPIO1
Output GPIO2
Output DATA from ADC12
Output DATA from ADC34
Others Reserved
DTS3[3:0]: DATA Selection of PORT-3 (MUX_P3DT)
These bits are used for routing DATA of PORT-3. Any combination of DATA1 to DATA6 and DATA of ADCs in
master mode can be connected to PORT-3. Refer to Figure 50 for more details.
Default value: 0010
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output DATA1
Output DATA2
Input DATA3 (default)
Output DATA4
Output DATA5
Output DATA6
Output GPIO1
Output GPIO2
Output DATA from ADC12
Output DATA from ADC34
Others Reserved
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Register 106 (6Ah)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
106
6Ah
SCK selection of PORT-3 and PORT-4
RSV
SCS4[3:0]
RSV
SCS3[3:0]
SCS4[3:0]: SCK Selection of PORT-4 (MUX_P4SC)
These bits are used for routing SCK of PORT-4. Any combination of SCK1 to SCK6 and SCK can be connected
to PORT-4. Refer to Figure 49 for more details.
Default value: 011
000
001
010
011
100
101
Output SCK1
Output SCK2
Output SCK3
Input SCK4 (default)
Output SCK5
Output SCK6
Others Reserved
SCS3[3:0]: SCK Selection of PORT-3 (MUX_P3SC)
These bits are used for routing SCK of PORT-3. Any combination of SCK1 to SCK6 and SCK can be connected
to PORT-3. Refer to Figure 50 for more details.
Default value: 010
000
001
010
011
100
101
Output SCK1
Output SCK2
Input SCK3 (default)
Output SCK4
Output SCK5
Output SCK6
Others Reserved
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Register 107 (6Bh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
107
6Bh
LRCK/BCK selection of PORT-5 and PORT-6
LBS6[3:0]
LBS5[3:0]
LBS6[3:0]: LRCK/BCK Selection of PORT-6 (MUX_P6BL)
These bits are used for routing LRCK and BCK of PORT-6. Any combination of LRCK1/BCK1 to LRCK6/BCK6
and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-6. Figure 51 shows a detailed
diagram of PORT-6.
Default value: 0101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output LRCK1 and BCK1
Output LRCK2 and BCK2
Output LRCK3 and BCK3
Output LRCK4 and BCK4
Output LRCK5 and BCK5
Input LRCK6 and BCK6 (default)
Output LRCK and BCK from DAC12 in master mode
Output LRCK and BCK from DAC34 in master mode
Output LRCK and BCK from ADC12 in master mode
Output LRCK and BCK from ADC34 in master mode
Others Reserved
PORT-6
LRCK/BCK to MUX_ADCxx and MUXDACxx
LRCK6
BCK6
LRCK1
BCK1
LRCK2
BCK2
LRCK3
BCK3
LRCK4
BCK4
LRCK5
BCK5
Register 107
LBS6[3:0]
LRCK, BCK from ADC12 at Master
LRCK, BCK from ADC34 at Master
LRCK, BCK from DAC12 at Master
LRCK, BCK from DAC34 at Master
SCK to MUX_ADCxx and MUXDACxx
SCK6
SCK1
SCK2
SCK3
SCK4
SCK5
Register 109
SCS6[2:0]
DATA to MUXDACxx
DATA6
DATA1
DATA2
DATA3
DATA4
DATA5
DATA from ADC12
DATA from ADC34
DATA from GPIO1
DATA from GPIO2
Register 108
DTS6[3:0]
Figure 51. Detailed Diagram of PORT-6
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LBS5[3:0]: LRCK/BCK Selection of PORT-5 (MUX_P5BL)
These bits are used for routing LRCK and BCK of PORT-5. Any combination of LRCK1/BCK1 to LRCK6/BCK6
and LRCK/BCK of ADCs/DACs in master mode can be connected to PORT-5. Figure 52 shows a detailed
diagram of PORT-5.
Default value: 0100
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output LRCK1 and BCK1
Output LRCK2 and BCK2
Output LRCK3 and BCK3
Output LRCK4 and BCK4
Input LRCK5 and BCK5 (default)
Output LRCK6 and BCK6
Output LRCK and BCK from DAC12 in master mode
Output LRCK and BCK from DAC34 in master mode
Output LRCK and BCK from ADC12 in master mode
Output LRCK and BCK from ADC34 in master mode
Others Reserved
PORT-5
LRCK/BCK to MUX_ADCxx and MUXDACxx
LRCK5
BCK5
LRCK1
BCK1
LRCK2
BCK2
LRCK3
BCK3
LRCK4
BCK4
LRCK6
BCK6
Register 107
LBS5[3:0]
LRCK, BCK from ADC12 at Master
LRCK, BCK from ADC34 at Master
LRCK, BCK from DAC12 at Master
LRCK, BCK from DAC34 at Master
SCK to MUX_ADCxx and MUXDACxx
SCK5
SCK1
SCK2
SCK3
SCK4
SCK6
Register 109
SCS5[2:0]
DATA to MUXDACxx
DATA5
DATA1
DATA2
DATA3
DATA4
DATA6
DATA from ADC12
DATA from ADC34
DATA from GPIO1
DATA from GPIO2
Register 108
DTS5[3:0]
Figure 52. Detailed Diagram of PORT-5
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Register 108 (6Ch)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
108
6Ch
DATA selection of PORT-5 and PORT-6
DTS6[3:0]
DTS5[3:0]
DTS6[3:0]: DATA Selection of PORT-6 (MUX_P6DT)
These bits are used for routing DATA of PORT-6. Any combination of DATA1 to DATA6 and DATA of ADCs in
master mode can be connected to PORT-6. Refer to Figure 51 for more details.
Default value: 0101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output DATA1
Output DATA2
Output DATA3
Output DATA4
Output DATA5
Input DATA6 (default)
Output GPIO1
Output GPIO2
Output DATA from ADC12
Output DATA from ADC34
Others Reserved
DTS5[3:0]: DATA Selection of PORT-5 (MUX_P5DT)
These bits are used for routing DATA of PORT-5. Any combination of DATA1 to DATA6 and DATA of ADCs in
master mode can be connected to PORT-5. Refer to Figure 52 for more details.
Default value: 0100
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Output DATA1
Output DATA2
Output DATA3
Output DATA4
Input DATA5 (default)
Output DATA6
Output GPIO1
Output GPIO2
Output DATA from ADC12
Output DATA from ADC34
Others Reserved
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Register 109 (6Dh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
109
6Dh
SCK selection of PORT-5 and PORT-6
RSV
SCS6[3:0]
RSV
SCS5[3:0]
SCS6[3:0]: SCK Selection of PORT-6 (MUX_P6SC)
These bits are used for routing SCK of PORT-6. Any combination of SCK1 to SCK6 and SCK can be connected
to PORT-6. Refer to Figure 51 for more details.
Default value: 101
000
001
010
011
100
101
Output SCK1
Output SCK2
Output SCK3
Output SCK4
Output SCK5
Input SCK6 (default)
Others Reserved
SCS5[3:0]: SCK Selection of PORT-5 (MUX_P5SC)
These bits are used for routing SCK of PORT-5. Any combination of SCK1 to SCK6 and SCK can be connected
to PORT-5. Refer to Figure 52 for more details.
Default value: 100
000
001
010
011
100
101
Output SCK1
Output SCK2
Output SCK3
Output SCK4
Input SCK5 (default)
Output SCK6
Others Reserved
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Register 110 (6Eh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
110
6Eh
LRCK/BCK selection of DAC12 and DAC34
D34LB[3:0]
D12LB[3:0]
D34LB[3:0]: LRCK/BCK Selection of DAC34 (MUX_DA34)
These bits are used for routing LRCK and BCK from each audio interface port to DAC34, or routing LRCK and
BCK from DACs/ADCs to each audio interface port in master mode. Refer to Figure 33 for more details.
Default value: 0100
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Select LRCK and BCK from PORT-1
Select LRCK and BCK from PORT-2
Select LRCK and BCK from PORT-3
Select LRCK and BCK from PORT-4
Select LRCK and BCK from PORT-5 (default)
Select LRCK and BCK from PORT-6
Select LRCK and BCK from DAC12 in master mode
Select LRCK and BCK from DAC34 in master mode
Select LRCK and BCK from ADC12 in master mode
Select LRCK and BCK from ADC34 in master mode
Others Reserved
D12LB[3:0] LRCK/BCK Selection of DAC12 (MUX_DA12)
These bits are used for routing LRCK and BCK from each audio interface port to DAC12, or routing LRCK and
BCK from DACs/ADCs to each audio interface port in master mode. Refer to Figure 33 for more details.
Default value: 0011
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Select LRCK and BCK from PORT-1
Select LRCK and BCK from PORT-2
Select LRCK and BCK from PORT-3
Select LRCK and BCK from PORT-4 (default)
Select LRCK and BCK from PORT-5
Select LRCK and BCK from PORT-6
Select LRCK and BCK from DAC12 in master mode
Select LRCK and BCK from DAC34 in master mode
Select LRCK and BCK from ADC12 in master mode
Select LRCK and BCK from ADC34 in master mode
Others Reserved
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Register 111 (6Fh)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
111
6Fh
DATA selection of DAC12 and DAC34
D34DT[3:0]
D12DT[3:0]
D34DT[3:0] DATA Selection of DAC34 (MUX_DA34)
These bits are used for routing DATA from each audio interface port to DAC34, or routing DATA from ADCs to
each audio interface port in master mode. Refer to Figure 33 for more details.
Default value: 0100
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Select DATA from PORT-1
Select DATA from PORT-2
Select DATA from PORT-3
Select DATA from PORT-4
Select DATA from PORT-5 (default)
Select DATA from PORT-6
Select DATA from GPIO1
Select DATA from GPIO2
Select DATA from ADC12
Select DATA from ADC34
Others Reserved
D12DT[3:0] DATA Selection of DAC12 (MUX_DA12)
These bits are used for routing DATA from each audio interface port to DAC12, or routing DATA from ADCs to
each audio interface port in master mode. Refer to Figure 33 for more details.
Default value: 0011
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Select DATA from PORT-1
Select DATA from PORT-2
Select DATA from PORT-3
Select DATA from PORT-4 (default)
Select DATA from PORT-5
Select DATA from PORT-6
Select DATA from GPIO1
Select DATA from GPIO2
Select DATA from ADC12
Select DATA from ADC34
Others Reserved
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Register 112 (70h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
112
70h
SCK selection of DAC12 and DAC34
RSV
D34SC[3:0]
RSV
D12SC[3:0]
D34SC[2:0] SCK Selection of DAC34 (MUX_DA34)
These bits are used for routing SCK from each audio interface port to DAC34. Refer to Figure 33 for more
details.
Default value: 100
000
001
010
011
100
101
Select SCK from PORT-1
Select SCK from PORT-2
Select SCK from PORT-3
Select SCK from PORT-4
Select SCK from PORT-5 (default)
Select SCK from PORT-6
Others Reserved
D12SC[2:0] SCK Selection of DAC12 (MUX_DA12)
These bits are used for routing SCK from each audio interface port to DAC12. Refer to Figure 33 for more
details.
Default value: 011
000
001
010
011
100
101
Select SCK from PORT-1
Select SCK from PORT-2
Select SCK from PORT-3
Select SCK from PORT-4 (default)
Select SCK from PORT-5
Select SCK from PORT-6
Others Reserved
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Register 116 (74h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
116
74h
LRCK/BCK selection of ADC12 and ADC34
A34LB[3:0]
A12LB[3:0]
A34LB[3:0]: LRCK/BCK Selection of ADC34 (MUX_AD34)
These bits are used for routing LRCK and BCK from each audio interface port to ADC34, or routing LRCK and
BCK from DACs/ADCs to each audio interface port in master mode. Refer to Figure 33 for more details.
Default value: 0001
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Select LRCK and BCK from PORT-1
Select LRCK and BCK from PORT-2 (default)
Select LRCK and BCK from PORT-3
Select LRCK and BCK from PORT-4
Select LRCK and BCK from PORT-5
Select LRCK and BCK from PORT-6
Select LRCK and BCK from DAC12 in master mode
Select LRCK and BCK from DAC34 in master mode
Select LRCK and BCK from ADC12 in master mode
Select LRCK and BCK from ADC34 in master mode
Others Reserved
A12LB[3:0] LRCK/BCK Selection of ADC12 (MUX_AD12)
These bits are used for routing LRCK and BCK from each audio interface port to ADC12, or routing LRCK and
BCK from DACs/ADCs to each audio interface port in master mode. Refer to Figure 33 for more details.
Default value: 0000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Select LRCK and BCK from PORT-1 (default)
Select LRCK and BCK from PORT-2
Select LRCK and BCK from PORT-3
Select LRCK and BCK from PORT-4
Select LRCK and BCK from PORT-5
Select LRCK and BCK from PORT-6
Select LRCK and BCK from DAC12 in master mode
Select LRCK and BCK from DAC34 in master mode
Select LRCK and BCK from ADC12 in master mode
Select LRCK and BCK from ADC34 in master mode
Others Reserved
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Register 117 (75h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
117
75h
SCK selection of ADC12 and ADC34
RSV
A34SC[3:0]
RSV
A12SC[3:0]
A34SC[2:0] SCK Selection of ADC34 (MUX_AD34)
These bits are used for routing SCK from each audio interface port to ADC34. Refer to Figure 33 for more
details.
Default value: 001
000
001
010
011
100
101
Select SCK from PORT-1
Select SCK from PORT-2 (default)
Select SCK from PORT-3
Select SCK from PORT-4
Select SCK from PORT-5
Select SCK from PORT-6
Others Reserved
A12SC[2:0] SCK Selection of ADC12 (MUX_AD12)
These bits are used for routing SCK from each audio interface port to ADC12. Refer to Figure 33 for more
details.
Default value: 000
000
001
010
011
100
101
Select SCK from PORT-1 (default)
Select SCK from PORT-2
Select SCK from PORT-3
Select SCK from PORT-4
Select SCK from PORT-5
Select SCK from PORT-6
Others Reserved
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Register 118 (76h)
REG
HEX
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
118
76h
GPIO1 and GPIO2 audio data selection
GP2S[3:0]
GP1S[3:0]
GP2S[3:0] GPIO2 Audio Data Selection
Default value: 0111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Output DATA1
Output DATA2
Output DATA3
Output DATA4
Output DATA5
Output DATA6
Output GPIO1
Input GPIO2 (default)
Output DATA from ADC12
Output DATA from ADC34
Use GPIO function
Others Reserved
GP1S[3:0] GPIO1 Audio Data Selection
Default value: 0110
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Output DATA1
Output DATA2
Output DATA3
Output DATA4
Output DATA5
Output DATA6
Input GPIO1 (default)
Output GPIO2
Output DATA from ADC12
Output DATA from ADC34
Use GPIO function
Others Reserved
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BASIC CONNECTION DIAGRAMS
(1)
(2)
AIN1L (1)
AIN1R (2)
AIN2L (3)
AIN2R (4)
AIN3L (5)
AIN3R (6)
AIN4L (7)
AIN4R (8)
AIN5L (9)
AIN5R (10)
AIN6L (11)
(13) LO1L
(14) LO1R
(15) LO2L
(16) LO2R
External Circuit
External Circuit
External Circuit
External Circuit
External Circuit
External Circuit
External Circuit
External Circuit
External Circuit
External Circuit
External Circuit
Line
Output
(19) HPOL
(22) HPOR
External Circuit
External Circuit
Headphone
Output
Line
Input
(3)
External Circuit
External Circuit
External Circuit
External Circuit
1.0 mF
(25) VCOMDA
(64) VCOMAD
(62) VREFAD1
(63) VREFAD2
(41) VDD
1.0 mF
1.0 mF
Reference
Voltage
AIN6R (12)
External Circuit
22W to 100W
SCK1 (29)
BCK1 (30)
LRCK1 (31)
DATA1 (32)
SCK2 (33)
BCK2 (34)
LRCK2 (35)
DATA2 (36)
SCK3 (37)
BCK3 (38)
LRCK3 (39)
DATA3 (40)
SCK4 (43)
BCK4 (44)
LRCK4 (45)
DATA4 (46)
SCK5 (47)
BCK5 (48)
LRCK5 (49)
DATA5 (50)
SCK6 (51)
BCK6 (52)
LRCK6 (53)
3.3 V
+
(42) DGND
> 4.7 mF
(23) VCCDA
(24) AGNDDA
(60) VCCAD
(61) AGNDAD
(20) VCCP
+
+
+
+
> 4.7 mF
> 4.7 mF
Power
Supply
> 4.7 mF
(21) PGND
Audio Interface
and Clocks
(18) VCCH
9.0 V
> 4.7 mF
(17) HGND
(26) AGNDS
(58) RSTB
(59) AMUTE
(27) SDA
Control
Interface
(28) SCL
(55) GPIO1
(26) GPIO2
DATA6 (54)
(27) GPIO3
(1) See Figure 54 for the line input.
(2) See Figure 55 for the line output.
(3) See Figure 56 for the headphone output.
Figure 53. Basic Connections
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47 kW (typ)
47 kW (typ)
C1
C5
R3
AINL (1)
AINL (1)
47 kW (typ)
47 kW (typ)
R1
C3
To ADC
To ADC
47 kW (typ)
47 kW (typ)
C2
C6
R4
AINR (2)
AINR (2)
47 kW (typ)
47 kW (typ)
R2
C4
To ADC
To ADC
(a) External Circuit for Line Input with Low-Pass Filter
(b) External Circuit for Line Input without Low-Pass Filter
47 kW (typ)
C7
AINL (1)
47 kW (typ)
To ADC
47 kW (typ)
AINR (2)
47 kW (typ)
To ADC
(c) External Circuit for not using Analog Input
R1, R2: Greater than 100 kΩ
R3, R4: 100 Ω to 1 kΩ
C1, C2, C5, C6: 1 µF to 47 µF
C3, C4: 0.01 µF to 0.001 µF
C7: Less than 0.1 µF
Figure 54. External Circuit for the Line Input
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fC = 85 kHz
fC = 85 kHz
From DAC
From DAC
C1
C5
R1
R5
LO1L (13)
LO1L (13)
R3
C3
R7
C7
Mute
Circuit
Mute
Circuit
From DAC
From DAC
C2
C6
R2
R6
LO1R (14)
LO1R (14)
R4
C4
R8
C8
Mute
Circuit
Mute
Circuit
(a) External Circuit for Line Output with Low-Pass Filter
(b) External Circuit for Line Output with Low-Pass Filter
R1, R2, R5, R6: 270 Ω
R3, R4, R7: > 100 kΩ
C1, C2, C5, C6: 1 µF to 47 µF
C3, C4, C7, C8: 6800 pF
Figure 55. External Circuit for the Line Output
From DAC
From DAC
C1
C5
R1
HPOL (19)
HPOL (19)
R3
C3
R5
C7
Mute
Circuit
Mute
Circuit
From DAC
From DAC
C2
C6
R2
HPOR (20)
HPOR (20)
R4
C4
R6
C8
Mute
Circuit
Mute
Circuit
(a) External Circuit with Short-Circuit protection Resistor
(b) External Circuit without Short-Circuit Protection Resistor
R1, R2 : 4 Ω to 16 Ω
R3, R4, R5, R6 : 22 Ω
C1, C2, C5, C6: 47 µF to 220 µF
C3, C4, C7, C8 : 0.022 µF
Figure 56. External Circuit for the Headphone Output
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PCM5310
www.ti.com ............................................................................................................................................................................................ SLES244–FEBRUARY 2009
BOARD DESIGN AND LAYOUT CONSIDERATIONS
POWER-SUPPLY PINS
The digital and analog power supplies (VCC, VCCDA, VCCAD, VCCP, and VCCH) to the PCM5310 should be
bypassed to the corresponding ground pins with a 1-µF to 4.7-µF electrolytic or ceramic capacitor, placed as
close to the pins as possible to maximize the dynamic performance of ADC, DAC, and other analog circuits. If
the power supply includes high-frequency noise, it is recommended to add a 0.1 µF ceramic capacitor as close
as possible to the power-supply lines to improve the dynamic performance.
To maximize the dynamic performance of the ADC, DAC, and other analog circuits, the analog and ground pins
(DGND, AGNDDA, AGNDAD, PGND, HGND and AGNDS) are not connected internally. These grounds should
have a low impedance to avoid digital noise feeding to the analog ground. Therefore, they should be connected
directly to each other under the device to reduce the potential of a noise problem.
ANALOG INPUT PINS
All analog input pins (AIN1L/AIN1R to AIN6L/AIN6R) are single-ended inputs with an analog multiplexer.
Antialiasing low-pass filters are included on the these inputs to remove the out-of-band nose from the audio. If
the performance of these filters is not sufficient for a given application, appropriate external antialiasing filters are
required. The passive RC filter (see Figure 54) is used in general. Any pins that are not used in a given
application should be left open or connected to ground with a small, 0.1-µF ceramic capacitor.
LINE OUTPUT PINS
All line output pins (LO1L, LO1R, LO2L and LO2R) are single-ended outputs with a 2-VRMS driver. An amplifier
with a low-pass filter is not required as in a conventional DAC; however, the delta-sigma modulator generates
out-of-band noise. The passive RC filter (see Figure 55) is used to remove this noise in general. If any line output
pins are not used within a given application, they should be left open.
HEADPHONE OUTPUT PINS
The headphone output pins (HPOL and HPOR) are single-ended outputs with more than 30-mW output power
into either a 16-Ω or 32-Ω load. If the headphone output pins are not used within a given application, they should
be left open. Adding a small resistor to these outputs is recommended (see Figure 56). in order to protect the
application and device from short-circuiting.
COMMON VOLTAGE PINS
A 1µF ceramic capacitor should be connected between the common voltage pins (VCOMAD and VCOMDA) for
the analog circuit and ground to ensure low source impedance of the ADC and DAC common voltages. This
capacitor should be located as close as possible to these pins.
REFERENCE VOLTAGE PINS
A 1-µF ceramic capacitor should be connected between the VREFAD1 pin and ground to ensure low source
impedance of ADC reference voltage. This capacitor should be located as close as possible to these pins.
VREFAD2 pin should be connected to directly ground.
DIGITAL OUTPUT PINS
The audio interface pins (LRCKx, BCKx, SCKx), clock pins (SCKx) and general-purpose input/output (GPIOx)
pins change from input mode to output mode through register settings. In output mode, these pins have
adequate load drive capability (see the Electrical Characteristics); however, if the signal lines are long, placing a
buffer near the PCM5310 and minimizing the load capacitor is recommended in order to optimize crosstalk
between the digital and analog circuits, maximize the dynamic performance of the ADC and DAC, and reduce
overall power consumption. The digital output pins should be open if they are not used in a given application.
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SLES244–FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com
DIGITAL INPUT PINS
Series resistors (ranging from 22 Ω to 100 Ω) are recommended for the SCKx, LRCKx, BCKx, and DATAx pins.
These series resistors combine with the stray printed circuit board (PCB) and device input capacitance to form a
low-pass filter that removes high-frequency noise from the digital signal, thus reducing high-frequency emissions.
All digital input pins should be connected to ground if they are not used in a given application.
PowerPAD (THERMAL PAD)
The PCM5310 is available in an HTQFP-64 PowerPAD package. The PowerPAD is a heatsink, which is exposed
metal at the bottom of the package. The PowerPAD works to conduct heat away from the silicon through thermal
vias located at the bottom of the PowerPAD.
The PowerPAD does not need to be soldered onto an exposed metal area of the PCB because the device works
within the absolute maximum rating (junction temperature = +150°C) without soldering the PowerPAD.
Refer to application note SLMA002, PowerPAD Thermally Enhanced Package, when considering whether to
solder the PowerPAD in order to reduce more heat from the device.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2009
PACKAGING INFORMATION
Orderable Device
PCM5310PAP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PAP
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
PCM5310PAPR
HTQFP
PAP
64
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Mar-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
PCM5310PAPR
HTQFP
PAP
64
1000
330.0
24.4
13.0
13.0
1.4
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Mar-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PAP 64
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
PCM5310PAPR
1000
Pack Materials-Page 2
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Applications
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amplifier.ti.com
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dsp.ti.com
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interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
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相关型号：
PCM5310PAPR
24-Bit, 96-/192-kHz, Asynchronous, 4-Channel/4-Channel Audio Codec with 2-VRMS Driver, Headphone Driver, and 6 Audio Interface Ports
TI
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