PCM63P-J [TI]

Colinear 20-Bit Monolithic Audio IGITAL-TO-ANALOG CONVERTER; 直排20位单片音频IGITAL - TO- ANALOG CONVERTER


型号：	PCM63P-J
厂家：	TEXAS INSTRUMENTS
描述：	Colinear 20-Bit Monolithic Audio IGITAL-TO-ANALOG CONVERTER 直排20位单片音频IGITAL - TO- ANALOG CONVERTER 转换器数模转换器光电二极管
文件：	总11页 (文件大小：194K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCM63P

DEMO BOARD

AVAILABLE

See Appendix A

Colinear ^™20-Bit Monolithic Audio

DIGITAL-TO-ANALOG CONVERTER

FEATURES

DESCRIPTION

● COLINEAR 20-BIT AUDIO DAC

● NEAR-IDEAL LOW LEVEL OPERATION

● GLITCH-FREE OUTPUT

The PCM63P is a precision 20-bit digital-to-analog

converter with ultra-low distortion (–96dB max with a

full scale output; PCM63P-K). Incorporated into the

PCM63P is a unique Colinear dual-DAC per channel

architecture that eliminates unwanted glitches and

other nonlinearities around bipolar zero. The PCM63P

also features a very low noise (116dB max SNR;

A-weighted method) and fast settling current output

(200ns typ, 2mA step) which is capable of 16-times

oversampling rates.

● ULTRA LOW –96dB max THD+N

(Without External Adjustment)

● 116dB SNR min (A-Weight Method)

● INDUSTRY STD SERIAL INPUT FORMAT

● FAST (200ns) CURRENT OUTPUT

(±2mA; ±2% max)

Applications include very low distortion frequency

synthesis and high-end consumer and professional

digital audio applications.

● CAPABLE OF 16x OVERSAMPLING

● COMPLETE WITH REFERENCE

+5V

Analog

+5V

Digital

–5V

Analog

–5V

Digital

Upper Lower

B2 Adj B2 Adj

PCM63P

20-Bit DAC

Colinear

Upper DAC

Positive

19-Bit

Clock

Latch Enable

Data

Upper

DAC

Data Latches

R_FEEDBACK

I_OUT

Input Shift

and

Control

Logic

Lower DAC

Negative

Data Latches

19-Bit

Lower

DAC

Buried

Zener

Reference

Servo

Amp

Ref

Amp

Bipolar Offset Current

Offset Decouple

Reference

Decouple

Servo

Decouple

Potentiometer

Voltage

Analog

Common

Digital

Common

Colinear ™, Burr-Brown Corp.

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

FAXLine: (800) 548-6133 (US/Canada Only)

• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1083F

Printed in U.S.A. January, 1998

PCM63P

SBAS006

SPECIFICATIONS

ELECTRICAL

All specifications at 25°C and ±V_Aand ±V_D= ±5V, unless otherwise noted.

PCM63P, PCM63P-J, PCM63P-K

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

DYNAMIC RANGE, ΤΗD+Ν at –60dB Referred to Full Scale

PCM63P

PCM63P-J

PCM63P-K

100

104

100

104

108

DIGITAL INPUT

Logic Family

Logic Level: V_IH

V_IL

TTL/CMOS Compatible

+2.4

+V_D

0.8

µA

I_IH

I_IL

V_IH= +2.7V

V_IL= +0.4V

–50

Data Format

Input Clock Frequency

Serial, MSB First, BTC⁽¹⁾

12.5

MHz

TOTAL HARMONIC DISTORTION + N⁽²⁾, Without Adjustments

PCM63P

f = 991Hz (0dB)⁽³⁾

f = 991Hz (–20dB)

f = 991Hz (–60dB)

PCM63P-J

f_S= 352.8kHz⁽⁴⁾

f_S= 352.8kHz

–92

–80

–40

–88

–74

–36

f = 991Hz (0dB)

f = 991Hz (–20dB)

f = 991Hz (–60dB)

PCM63P-K

f_S= 352.8kHz

–96

–82

–44

–92

–76

–40

f = 991Hz (0dB)

f = 991Hz (–20dB)

f = 991Hz (–60dB)

f_S= 352.8kHz

–100

–88

–48

–96

–82

–44

ACCURACY

Level Linearity

Gain Error

at –90dB Signal Level

±0.3

±1

±2

Bipolar Zero Error⁽⁵⁾

Gain Drift

Bipolar Zero Drift

Warm-up Time

±12

µA

0°C to 70°C

ppm/°C

ppm of FSR/°C

Minute

IDLE CHANNEL SNR⁽⁶⁾

20Hz to 20kHz at BPZ⁽⁷⁾

+116

+120

+86

POWER SUPPLY REJECTION

ANALOG OUTPUT

Output Range

Output Impedance

Internal R_FEEDBACK

Settling Time

±2.00

670

1.5

200

Ω

kΩ

2mA Step

Glitch Energy

No Glitch Around Zero

POWER SUPPLY REQUIREMENTS

±V_A, ±V_DSupply Voltage Range

+I_A, +I_DCombined Supply Current

–I_A, –I_DCombined Supply Current

Power Dissipation

±4.50

±5

–35

225

±5.50

–45

300

+V_A, +V_D= +5V

–V_A, –V_D= –5V

±V_A, ±V_D= ±5V

TEMPERATURE RANGE

Specification

Operating

–40

–60

+70

+85

+100

°C

Storage

NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (Distortion_RMS+ Noise_RMS) / Signal_RMS. (3) D/A converter output frequency (signal level). (4) D/A

converter sample frequency (8 x 44.1kHz; 8x oversampling). (5) Offset error at bipolar zero. (6) Measured using an OPA27 and 1.5kΩ feedback and an A-weighted

filter. (7) Bipolar Zero.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

PCM63P

PIN ASSIGNMENTS

ABSOLUTE MAXIMUM RATINGS

DESCRIPTION

MNEMONIC

+V_A, +V_Dto ACOM/DCOM ........................................................ 0V to +8V

–V_A, –V_Dto ACOM/DCOM ........................................................ 0V to –8V

–V_A, –V_Dto +V_A, +V_D............................................................. 0V to +16V

ACOM to DCOM............................................................................... ±0.5V

Digital Inputs (pins 18, 20, 21) to DCOM ............................... –1V to +V_D

Power Dissipation .......................................................................... 500mW

Lead Temperature, (soldering, 10s) .............................................. +300°C

Max Junction Temperature .............................................................. 165°C

Thermal Resistance, θ_JA............................................................... 70°C/W

Servo Amp Decoupling Capacitor

+5V Analog Supply Voltage

Reference Decoupling Capacitor

Offset Decoupling Capacitor

Bipolar Offset Current Output (+2mA)

DAC Current Output (0 to –4mA)

Analog Common Connection

No Connection

CAP

+V_A

CAP

BPO

I_OUT

ACOM

Feedback Resistor Connection (1.5kΩ)

–5V Digital Supply Voltage

Digital Common Connection

+5V Digital Voltage Supply

No Connection

DAC Data Clock Input

RF₁

RF₂

–V_D

DCOM

+V_D

CLK

DATA

UB2 Adj

LB2 Adj

V_POT

NOTE: Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

PACKAGE INFORMATION

PACKAGE DRAWING

PRODUCT

PACKAGE

NUMBER⁽¹⁾

PCM63P

PCM63P-J

PCM63P-K

28-Pin Plastic DIP

215

No Connection

DAC Data Latch Enable

DAC Data Input

No Connection

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

Optional Upper DAC Bit-2 Adjust (–4.29V)*

Optional Lower DAC Bit-2 Adjust (–4.29V)*

Bit Adjust Reference Voltage Tap (–3.52V)*

No Connection

–5V Analog Supply Voltage

–V_A

*Nominal voltages at these nodes assuming ±V_A; ±V_D= ±5V.

ORDERING INFORMATION

TEMPERATURE

RANGE

MAX THD+N,

AT 0dB

PRODUCT

PACKAGE

PCM63P

PCM63P-J

PCM63P-K

28-Pin Plastic DIP 0°C to +70°C

–88dB

–92dB

–96dB

PCM63P

TYPICAL PERFORMANCE CURVES

All specifications at 25°C and ±V_Aand ±V_D= ±5.0V, unless otherwise noted.

16-BIT LEVEL LINEARITY

(Dithered Fade to Noise)

THD+N vs FREQUENCY

–40

–60dB

–60

–40dB

–80

–20dB

–2

–4

–6

–8

–100

0dB

–120

100

10k

–120

–110

–100

–90

–80

–70

–60

Output Frequency (Hz)

Output Signal Level (dB)

–90dB SIGNAL SPECTRUM

(100Hz Bandwidth)

16-BIT MONOTONICITY

1.5

–80

–100

–120

–140

–160

0.5

FPO

–0.5

–1

–1.5

8.83ms/div

12k

16k

20k

Frequency (Hz)

–110dB SIGNAL

–90dB SIGNAL

(10Hz to 20kHz Bandwidth)

200

100

FPO

–100

–200

–20

–40

400

800

1200

1600

2000

400

800

1200

1600

2000

Time (µs)

PCM63P

THEORY OF OPERATION

DISCUSSION OF SPECIFICATIONS

DUAL-DAC COLINEAR ARCHITECTURE

DYNAMIC SPECIFICATIONS

Digital audio systems have traditionally used laser-trimmed,

current-source DACs in order to achieve sufficient accuracy.

However even the best of these suffer from potential low-

level nonlinearity due to errors at the major carry bipolar

zero transition. More recently, DACs employing a different

architecture which utilizes noise shaping techniques and

very high oversampling frequencies, have been introduced

(“Bitstream”, “MASH”, or 1-bit DACs). These DACs over-

come the low level linearity problem, but only at the expense

of signal-to-noise performance, and often to the detriment of

channel separation and intermodulation distortion if the

succeeding circuitry is not carefully designed.

Total Harmonic Distortion + Noise

The key specification for the PCM63P is total harmonic

distortion plus noise (THD+N). Digital data words are read

into the PCM63P at eight times the standard compact disk

audio sampling frequency of 44.1kHz (352.8kHz) so that a

sine wave output of 991Hz is realized. For production

testing, the output of the DAC goes to an I to V converter,

then to a programmable gain amplifier to provide gain at

lower signal output test levels, and then through a 40kHz

low pass filter before being fed into an analog type distortion

analyzer. Figure 1 shows a block diagram of the production

THD+N test setup.

The PCM63 is a new solution to the problem. It combines all

the advantages of a conventional DAC (excellent full scale

performance, high signal-to-noise ratio and ease of use) with

superior low-level performance. Two DACs are combined

in a complementary arrangement to produce an extremely

linear output. The two DACs share a common reference and

a common R-2R ladder to ensure perfect tracking under all

conditions. By interleaving the individual bits of each DAC

and employing precise laser trimming of resistors, the highly

accurate match required between DACs is achieved.

For the audio bandwidth, THD+N of the PCM63P is essen-

tially flat for all frequencies. The typical performance curve,

“THD+N vs Frequency,” shows four different output signal

levels: 0dB, –20dB, –40dB, and –60dB. The test signals are

derived from a special compact test disk (the CBS CD-1). It

is interesting to note that the –20dB signal falls only about

10dB below the full scale signal instead of the expected

20dB. This is primarily due to the superior low-level signal

performance of the dual-DAC Colinear architecture of the

PCM63P.

This new, complementary linear or dual-DAC Colinear

approach, which steps away from zero with small steps in

both directions, avoids any glitching or “large” linearity

errors and provides an absolute current output. The low level

performance of the PCM63P is such that real 20-bit resolu-

tion can be realized, especially around the critical bipolar

zero point.

In terms of signal measurement, THD+N is the ratio of

Distortion_RMS+ Noise_RMS/ Signal_RMSexpressed in dB. For

the PCM63P, THD+N is 100% tested at all three specified

output levels using the test setup shown in Figure 1. It is

significant to note that this test setup does not include any

output deglitching circuitry. All specifications are achieved

without the use of external deglitchers.

Table I shows the conversion made by the internal logic of

the PCM63P from binary two’s complement (BTC). Also,

the resulting internal codes to the upper and lower DACs

(see front page block diagram) are listed. Notice that only

the LSB portions of either internal DAC are changing

around bipolar zero. This accounts for the superlative per-

formance of the PCM63P in this area of operation.

Dynamic Range

Dynamic range in audio converters is specified as the measure

of THD+N at an effective output signal level of –60dB

referred to 0dB. Resolution is commonly used as a theoretical

measure of dynamic range, but it does not take into account

the effects of distortion and noise at low signal levels. The

INPUT CODE

LOWER DAC CODE

UPPER DAC CODE

ANALOG OUTPUT

(20-bit Binary Two’s Complement)

(19-bit Straight Binary)

+Full Scale

011...111

011...110

000...010

000...001

000...000

111...111

111...110

100...001

100...000

111...111 + 1LSB*

111...111

111...110

000...010

000...001

000...000

+Full Scale – 1LSB

Bipolar Zero + 2LSB

Bipolar Zero + 1LSB

Bipolar Zero

Bipolar Zero – 1LSB

Bipolar Zero – 2LSB

–Full Scale + 1LSB

–Full Scale

111...110

000...001

000...000

*The extra weight of 1LSB is added at this point to make the transfer function symmetrical around bipolar zero.

TABLE I. Binary Two’s Complement to Colinear Conversion Chart.

PCM63P

Use 400Hz High-Pass

Filter and 30kHz

Low-Pass Filter

Low-Pass

Filter

40kHz 3rd Order

GIC Type

Programmable

Gain Amp

0dB to 60dB

Distortion

Analyzer

Meter Settings

(Shiba Soku Model

725 or Equivalent)

I to V

Converter

OPA627

Binary

Counter

Digital Code

(EPROM)

Parallel-to-Serial

Conversion

DUT

(PCM63P)

Clock

Latch Enable

Sampling Rate = 44.1kHz x 8 (352.8kHz)

Output Frequency = 991Hz

Timing

Logic

FIGURE 1. Production THD+N Test Setup.

Colinear architecture of the PCM63P, with its ideal

performance around bipolar zero, provides a more usable

dynamic range, even using the strict audio definition, than

any previously available D/A converter.

make this measurement, the digital input is continuously fed

the code for bipolar zero while the output of the DAC is

band-limited from 20Hz to 20kHz and an A-weighted filter

is applied. The idle channel SNR for the PCM63P is typi-

cally greater than 120dB, making it ideal for low-noise

applications.

Level Linearity

Deviation from ideal versus actual signal level is sometimes

called “level linearity” in digital audio converter testing. See

the “–90dB Signal Spectrum” plot in the Typical Perfor-

mance Curves section for the power spectrum of a PCM63P

at a –90dB output level. (The “–90dB Signal” plot shows the

actual –90dB output of the DAC). The deviation from ideal

for PCM63P at this signal level is typically less than ±0.3dB.

For the “–110dB Signal” plot in the Typical Performance

Curves section, true 20-bit digital code is used to generate a

–110dB output signal. This type of performance is possible

only with the low-noise, near-theoretical performance around

bipolar zero of the PCM63P’s Colinear DAC circuitry.

Monotonicity

Because of the unique dual-DAC Colinear architecture of

the PCM63P, increasing values of digital input will always

result in increasing values of DAC output as the signal

moves away from bipolar zero in one-LSB steps (in either

direction). The “16-Bit Monotonicity” plot in the Typical

Performance Curves section was generated using 16-bit

digital code from a test compact disk. The test starts with 10

periods of bipolar zero. Next are 10 periods of alternating

1LSBs above and below zero, and then 10 periods of

alternating 2LSBs above and below zero, and so on until

10LSBs above and below zero are reached. The signal

pattern then begins again at bipolar zero.

A commonly tested digital audio parameter is the amount of

deviation from ideal of a 1kHz signal when its amplitude is

decreased from –60dB to –120dB. A digitally dithered input

signal is applied to reach effective output levels of –120dB

using only the available 16-bit code from a special compact

disk test input. See the “16-Bit Level Linearity” plot in the

Typical Performance Curves section for the results of a

PCM63P tested using this 16-bit dithered fade-to-noise

signal. Note the very small deviation from ideal as the signal

goes from –60dB to –100dB.

With PCM63P, the low-noise steps are clearly defined and

increase in near-perfect proportion. This performance is

achieved without any external adjustments. By contrast,

sigma-delta (“Bitstream”, “MASH”, or 1-bit DAC) architec-

tures are too noisy to even see the first 3 or 4 bits change (at

16 bits), other than by a change in the noise level.

Absolute Linearity

Even though absolute integral and differential linearity specs

are not given for the PCM63P, the extremely low THD+N

performance is typically indicative of 16-bit to 17-bit inte-

gral linearity in the DAC, depending on the grade specified.

The relationship between THD+N and linearity, however, is

not such that an absolute linearity specification for every

individual output code can be guaranteed.

DC SPECIFICATIONS

Idle Channel SNR

Another appropriate specification for a digital audio con-

verter is idle channel signal-to-noise ratio (idle channel

SNR). This is the ratio of the noise on the DAC output at

bipolar zero in relation to the full scale range of the DAC. To

PCM63P

Offset, Gain, And Temperature Drift

sixteen times (16x oversampling) the standard audio word

bit length of 24 bits (44.1kHz x 16 x 24 = 16.9MHz). Note

that this clock rate accommodates a 24-bit word length, even

though only 20 bits are actually being used. The maximum

clock rate of 25MHz is guaranteed, but is not 100% final

tested. The setup and hold timing relationships are shown in

Figure 3.

Although the PCM63P is primarily meant for use in dy-

namic applications, specifications are also given for more

traditional DC parameters such as gain error, bipolar zero

offset error, and temperature gain and offset drift.

DIGITAL INPUT

“Stopped Clock” Operation

Timing Considerations

The PCM63P is normally operated with a continuous clock

input signal. If the clock is to be stopped between input data

words, the last 20 bits shifted in are not actually shifted from

the serial register to the latched parallel DAC register until

Latch Enable (LE, P20) goes low. Latch Enable must remain

low until after the first clock cycle of the next data word

to insure proper DAC operation. In any case, the setup and

hold times for Data and LE must be observed as shown in

Figure 3.

The PCM63P accepts TTL compatible logic input levels.

Noise immunity is enhanced by the use of differential

current mode logic input architectures on all input signal

lines. The data format of the PCM63P is binary two’s

complement (BTC) with the most significant bit (MSB)

being first in the serial input bit stream. Table II describes

the exact relationship of input data to voltage output coding.

Any number of bits can precede the 20 bits to be loaded,

since only the last 20 will be transferred to the parallel DAC

>20ns

All DAC serial input data (P21, DATA) bit transfers are

triggered on positive clock (P18, CLK) edges. The serial-to-

parallel data transfer to the DAC occurs on the falling edge

of Latch Enable (P20, LE). The change in the output of the

DAC coincides with the falling edge of Latch Enable (P20,

LE). Refer to Figure 2 for graphical relationships of these

signals.

Data

Input

LSB

MSB

>10ns >10ns

Clock

Input

>15ns

>1ns

>33ns

Latch

Enable

>10ns

Maximum Clock Rate

>One Clock Cycle

A typical clock rate of 16.9MHz for the PCM63P is derived

by multiplying the standard audio sample rate of 44.1kHz by

FIGURE 3. Setup and Hold Timing Diagram.

VOLTAGE OUTPUT

DIGITAL INPUT

ANALOG OUTPUT

CURRENT OUTPUT

(With External Op Amp)

1,048,576LSBs

1LSB

7FFFF_HEX

00000_HEX

FFFFF_HEX

80000_HEX

Full Scale Range

+Full Scale

Bipolar Zero

Bipolar Zero – 1LSB

–Full Scale

4.00000000mA

3.81469727nA

–1.99999619mA

0.00000000mA

+0.00000381mA

+2.00000000mA

6.00000000V

5.72204590µV

+2.99999428V

0.00000000V

–0.00000572V

–3.00000000V

TABLE II. Digital Input/Output Relationships.

P18 (Clock)

12 13 14 15 16 17 18 19 20

LSB

P21 (Data)

MSB

P20 (Latch Enable)

P6 (I_OUT

)

NOTES: (1) If clock is stopped between input of 20-bit data words, Latch Enable (LE) must remain low until after the first clock cycle of the next 20-bit data

word stream. (2) Data format is binary two’s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch Enable

(LE) must remain low at least one clock cycle after going negative. (4) Latch Enable (LE) must be high for at least one clock cycle before going negative.

(5) I_OUTchanges on negative going edge of Latch Enable (LE).

FIGURE 2. Timing Diagram.

PCM63P

desired. Use of the MSB adjustments will only affect larger

dynamic signals (between 0dB and –6dB). This improve-

ment comes from bettering the gain match between the

upper and lower DACs at these signal levels. The change is

realized by small adjustments in the bit-2 weights of each

DAC. Great care should be taken, however, as improper

adjustment will easily result in degraded performance.

INSTALLATION

POWER SUPPLIES

Refer to Figure 4 for proper connection of the PCM63P in

the voltage-out mode using the internal feedback resistor.

The feedback resistor connections (P9 and P10) should be

left open if not used. The PCM63P only requires a ±5V

supply. Both positive supplies should be tied together at a

single point. Similarly, both negative supplies should be

connected together. No real advantage is gained by using

separate analog and digital supplies. It is more important that

both these supplies be as “clean” as possible to reduce

coupling of supply noise to the output. Power supply decou-

pling capacitors should be used at each supply pin to

maximize power supply rejection, as shown in Figure 4,

regardless of how good the supplies are. Both commons

should be connected to an analog ground plane as close to

the PCM63P as possible.

In theory, the adjustments would seem very simple to

perform, but in practice they are actually quite complex. The

first step in the theoretical procedure would involve making

each bit-2 weight ideal in relation to its code minus one

value (adjusting each potentiometer for zero differential

nonlinearity error at the bit-2 major carries). This would be

the starting point of each 100kΩ potentiometer for the next

adjustment. Then, each potentiometer would be adjusted

equally, in opposite directions, to achieve the lowest full-

scale THD+N possible (reversing the direction of rotation

FILTER CAPACITOR REQUIREMENTS

–V_A28

As shown in Figure 4, various size decoupling capacitors

can be used, with no special tolerances being required. The

size of the offset decoupling capacitor is not critical either,

with larger values (up to 100µF) giving slightly better SNR

readings. All capacitors should be as close to the appropriate

pins of the PCM63P as possible to reduce noise pickup from

surrounding circuitry.

100kΩ

V_POT25

LB2 Adj 24

UB2 Adj 23

330kΩ

MSB ADJUSTMENT CIRCUITRY

0.1µF

Near optimum performance can be maintained at all signal

levels without using the optional MSB adjust circuitry of the

PCM63P shown in Figure 5. Adjustability is provided for

those cases where slightly better full-scale THD+N is

FIGURE 5. Optional Bit-2 Adjustment Circuitry.

PCM63P

1µF

0.1µF

–5V

CAP

+V_A

–V_A28

NC 27

+5V

1µF

CAP

BPO

I_OUT

NC 26

V_POT25

LB2 Adj 24

UB2 Adj 23

NC 22

0.1µF

4.7µF

±3V

1/2

OPA2604

ACOM

DATA 21

LE 20

10 RF

NC 19

11 –V_D

12 DCOM

13 +V_D

14 NC

CLK 18

NC 17

1µF

NC 16

NC 15

FIGURE 4. Connection Diagram.

PCM63P

for both if no immediate improvement were noted). This

procedure would require the generation of the digital bit-2

major carry code to the input of the PCM63P and a DVM or

oscilloscope capable of reading the output voltage for a one

LSB step (5.72µV) in addition to a distortion analyzer.

the correct starting direction would be arbitrary. This proce-

dure still requires a good DVM in addition to a distortion

analyzer.

Each user will have to determine if a small improvement in

full-scale THD+N for their application is worth the expense

of performing a proper MSB adjustment.

A more practical approach would be to forego the minor

correction for the bit-2 major carry adjustment and only

adjust for upper and lower DAC gain matching. The prob-

lem is that just by connecting the MSB circuitry to the

PCM63P, the odds are that the upper and lower bit-2 weights

would be greatly changed from their unadjusted states and

thereby adversely affect the desired gain adjustment. Just

centering the 100kΩ potentiometers would not necessarily

provide the correct starting point. To guarantee that each

100kΩ potentiometer would be set to the correct starting or

null point (no current into or out of the MSB adjust pins), the

voltage drop across each corresponding 330kΩ resistor would

have to measure 0V. A voltage drop of ±1.25mV across

either 330kΩ resistor would correspond to a ±1LSB change

in the null point from its unadjusted state (1LSB in current

or 3.81nA x 330kΩ = 1.26mV). Once these starting points

for each potentiometer had been set, each potentiometer

would then be adjusted equally, in opposite directions, to

achieve the lowest full-scale THD+N possible. If no imme-

diate improvement were noted, the direction of rotation for

both potentiometers would be reversed. One direction of

potentiometer counter-rotations would only make the gain

mismatch and resulting THD+N worse, while the opposite

would gradually improve and then worsen the THD+N after

passing through a no mismatch point. The determination of

APPLICATIONS

The most common application for the PCM63P is in high-

performance and professional digital audio playback, such

as in CD and DAT players. The circuit in Figure 6 shows the

PCM63P in a typical combination with a digital interface

format receiver chip (Yamaha YM3623), an 8x interpolating

digital filter (Burr-Brown DF1700P), and two third-order

low-pass anti-imaging filters (implemented using Burr-Brown

OPA2604APs).

Using an 8x digital filter increases the number of samples to

the DAC by a factor of 8, thereby reducing the need for a

higher order reconstruction or anti-imaging analog filter on

the DAC output. An analog filter can now be constructed

using a simple phase-linear GIC (generalized immittance

converter) architecture. Excellent sonic performance is

achieved using a digital filter in the design, while reducing

overall circuit complexity at the same time.

Because of its superior low-level performance, the PCM63P

is also ideally suited for other high-performance applications

such as direct digital synthesis (DDS).

PCM63P

FIGURE 6. Stereo Audio Application.

PCM63P

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

PCM63P-J [TI]

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