PCM6480-Q1 [TI]
具有集成麦克风偏置和输入诊断功能的汽车类 4 通道模拟和 4 通道数字音频 ADC;
| 型号： | PCM6480-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成麦克风偏置和输入诊断功能的汽车类 4 通道模拟和 4 通道数字音频 ADC |
| 文件： | 总170页 (文件大小：6077K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM6480-Q1
ZHCSMY2 –DECEMBER 2020
具有集成麦克风偏置和输入故障诊断功能的PCM6480-Q1 汽车类8 通道、
768kHz 音频ADC
对模拟和数字麦克风输入采样，可以非常高效地实现车
1 特性
内有源噪声消除 (ANC) 和语音识别 (VR) 应用。
PCM6480-Q1 包含高性能的音频模数转换器 (ADC)，
可支持最高10VRMS 的模拟输入信号。该器件具有集成
的高电压、可编程麦克风偏置和输入诊断电路，可直接
连接到基于麦克风的汽车系统，提供全面的直流耦合输
入故障诊断功能。该器件集成了一个高效的升压转换
器，以通过外部低电压 3.3V 电源（系统内随时可用的
电源）产生高电压麦克风偏置。PCM6480-Q1 集成了
可编程通道增益、数字音量控制、低抖动锁相环
(PLL)、可编程高通滤波器 (HPF)、双二阶滤波器、低
延迟滤波器模式，并可实现高达 768kHz 的采样率。
PCM6480-Q1 支持时分多路复用 (TDM)、I2S 或左平
衡(LJ) 音频格式，并可通过
• 符合面向汽车应用的AEC-Q100 标准
– 温度等级1：-40°C ≤TA ≤+125°C
• 最多8 通道音频同步转换
– 4 通道模拟麦克风输入或线路输入
– 4 通道数字PDM 麦克风输入
• ADC 性能：
– 线路差分输入动态范围：110dB
– 麦克风差分输入动态范围：110dB
– THD+N：-95dB
• ADC 模拟输入电压：
– 差分10VRMS 满量程输入
– 单端5VRMS 满量程输入
• ADC 采样率(fS) = 8kHz 至768kHz
• 可编程通道设置：
I2C 或SPI 接口进行控制。
器件信息
器件型号(1)
封装
封装尺寸（标称值）
– 模拟输入通道增益：0dB 至42dB
– 数字音量控制：–100dB 至27dB
– 增益校准分辨率为0.1dB
5.00mm x 5.00mm，
间距为0.5mm
PCM6480-Q1
WQFN (32)
– 相位校准分辨率为163ns
• 可编程麦克风偏置（5V 至9V）
• 可编程麦克风模拟输入故障诊断：
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
MICBIAS
BSTOUT
BSTSW
BSTVDD
IN1P
IN1M
SHDNZ
GPIO1
– 开路输入或短路输入
– 接地短路、MICBIAS 或VBAT
– 麦克风偏置过流保护
Boost Converter and
PLL and Clock
Generation
Programmable MICBIAS
IN2P
IN2M
Noise
Cancellation
Microphones
IN3P
IN3M
FSYNC
BCLK
Audio Serial
Programmable
4-Channel ADC
with Front-End PGA
and Input Attenuator
• 低延迟信号处理滤波器选择
• 可编程HPF 和双二阶数字滤波器
• I2C 或SPI 控制
Interface
(TDM, I2S, LJ)
Digital Filters and
Biquads
IN4P
IN4M
SDOUT
SDA_SSZ
PDMDIN2_GPI2
PDMCLK2_GPIO3
SCL_MOSI
Voice
Recognition
Digital
4-Channel Digital
PDM Microphones
Simultaneous
Sampling
Input Diagnostics,
Regulators and
Voltage Reference
• 音频串行数据接口：
I2
Control Interf ace
C or SPI
ADDR0_SCLK
ADDR1_MISO
Microphones
PDMDIN1_GPI1
– 格式：TDM、I2S 或左平衡(LJ)
– 字长：16 位、20 位、24 位或32 位
– 主/从接口
PDMCLK1_GPIO2
VBAT_IN VREF
AVSS
IOVDD
AVDD
AREG
DREG
VSS
简化版应用示意图
• 3.3V 单电源运行
• I/O 电源运行：3.3V 或1.8V
• 功耗：
– 在48kHz 下< 20mW/通道
2 应用
• 汽车有源噪声消除
• 汽车音响主机
• 数字驾驶舱处理单元
• 汽车外部放大器
3 说明
PCM6480-Q1 是一款高性能音频转换器，最多可支持
对脉冲密度调制 (PDM) 麦克风输入的 4 通道模拟麦克
风输入或线路输入进行同步采样。该集成器件通过同时
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASA30
PCM6480-Q1
ZHCSMY2 –DECEMBER 2020
www.ti.com.cn
Table of Contents
8 Detailed Description......................................................21
8.1 Overview...................................................................21
8.2 Functional Block Diagram.........................................22
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................64
8.5 Programming............................................................ 65
8.6 Register Maps...........................................................69
9 Application and Implementation................................155
9.1 Application Information........................................... 155
9.2 Typical Application.................................................. 156
9.3 What To Do and What Not To Do............................160
10 Power Supply Recommendations............................161
11 Layout.........................................................................162
11.1 Layout Guidelines................................................. 162
11.2 Layout Example.................................................... 163
12 Device and Documentation Support........................164
12.1 Device Support..................................................... 164
12.2 Documentation Support........................................ 164
12.3 接收文档更新通知................................................. 164
12.4 支持资源................................................................164
12.5 Trademarks...........................................................164
12.6 静电放电警告........................................................ 164
12.7 术语表................................................................... 164
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics ............................................7
7.6 Timing Requirements: I2C Interface ......................... 11
7.7 Switching Characteristics: I2C Interface ...................12
7.8 Timing Requirements: SPI Interface ........................ 13
7.9 Switching Characteristics: SPI Interface ..................13
7.10 Timing Requirements: TDM, I2S or LJ Interface .... 13
7.11 Switching Characteristics: TDM, I2S or LJ
Interface ..................................................................... 14
7.12 Timing Requirements: PDM Digital Microphone
Interface ..................................................................... 14
7.13 Switching Characteristics: PDM Digial
Microphone Interface ..................................................15
7.14 Timing Diagrams.....................................................15
7.15 Typical Characteristics............................................17
Information.................................................................. 165
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2020
*
Initial release.
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5 Device Comparison Table
FEATURE
PCM6020-Q1
PCM6240-Q1
PCM6260-Q1
PCM6480-Q1
PCM6340-Q1
PCM6360-Q1
Control interface
I2C or SPI
Digital audio serial
interface
TDM or I2S or left-justified (LJ)
Audio analog channel
2
0
4
0
6
0
4
4
4
0
6
0
Audio PDM input channel
5 (multiplexed
with PDM
interface)
General-purpose input or
output pins
5
5
1
5
1
Microphone bias voltage
Programmable 5 V to 9 V in steps of 0.5 V
Powered directly using external
high-voltage HVDD (as high as 12
V) supply
Microphone bias LDO
supply
Generated using integrated efficient boost converter with external low-
voltage BSTVDD = 3.3-V supply
Input fault diagnostics
Package
Comprehensive input fault diagnostics for DC-coupled microphone inputs with programmable thresholds
WQFN (RTV), 32-pin, 5.00 mm x 5.00 mm (0.5-mm pitch)
Package, and control registers compatible; replacements of each other. See the Scalable Automotive Audio
Solutions Using the PCM6xx0-Q1 Family of Products application report for further details.
Compatibility
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6 Pin Configuration and Functions
AVDD
AREG
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ADDR0_SCLK
ADDR1_MISO
SHDNZ
BSTVDD
BSTSW
BSTOUT
MICBIAS
VREF
VBAT_IN
Thermal Pad (VSS)
PDMCLK1_GPIO2
PDMDIN1_GPI1
PDMCLK2_GPIO3
PDMDIN2_GPI2
AVSS
Not to scale
图6-1. RTV Package, 32-Pin WQFN With Exposed Thermal Pad, Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
AVDD
AREG
Analog supply
Analog supply
Analog supply
Analog supply
Analog supply
Analog
Analog power (3.3 V, nominal)
2
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal)
Boost converter supply voltage (3.3 V, nominal)
Boost converter switch input
3
BSTVDD
BSTSW
BSTOUT
MICBIAS
VREF
4
5
Boost converter output voltage
6
MICBIAS output (programmable output up to 9 V)
Analog reference voltage filter output
Analog ground; short directly to the board ground plane
Analog input 1P pin
7
Analog
8
AVSS
Analog supply
Analog input
Analog input
9
IN1P
10
IN1M
Analog input 1M pin
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表6-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
11
NAME
IN2P
IN2M
IN3P
IN3M
IN4P
IN4M
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input 2P pin
Analog input 2M pin
Analog input 3P pin
Analog input 3M pin
Analog input 4P pin
Analog input 4M pin
12
13
14
15
16
PDM microphone data input 2 or general-purpose digital input 2 (multipurpose
functions such as daisy-chain input, PLL input clock source, and so forth)
17
18
19
20
PDMDIN2_GPI2
PDMCLK2_GPIO3
PDMDIN1_GPI1
PDMCLK1_GPIO2
Digital input
Digital I/O
Digital input
Digital I/O
PDM microphone clock output 2 or general-purpose digital input/output 3
(multipurpose functions such as daisy-chain input, audio data output, PLL input
clock source, interrupt, and so forth)
PDM microphone data input 1 or general-purpose digital input 1 (multipurpose
functions such as daisy-chain input, PLL input clock source, and so forth)
PDM microphone clock output 1 or general-purpose digital input/output 2
(multipurpose functions such as daisy-chain input, audio data output, PLL input
clock source, interrupt, and so forth)
21
22
VBAT_IN
SHDNZ
Analog
Analog VBAT input monitoring pin (used for input diagnostics)
Device hardware shutdown and reset (active low)
Digital input
For I2C operation: I2C slave address A1 pin.
For SPI operation: SPI slave output pin.
23
24
25
ADDR1_MISO
ADDR0_SCLK
SCL_MOSI
Digital I/O
Digital input
Digital input
For I2C operation: I2C slave address A0 pin.
For SPI operation : SPI serial bit clock.
For I2C operation: clock pin for I2C control bus.
For SPI operation: SPI slave input pin.
For I2C operation: data pin for I2C control bus.
For SPI operation: SPI slave-select pin.
26
27
28
SDA_SSZ
IOVDD
Digital I/O
Digital supply
Digital I/O
Digital I/O power supply (1.8 V or 3.3 V, nominal)
General-purpose digital input/output 1 (multipurpose functions such as daisy-chain
input, audio data output, PLL input clock source, interrupt, and so forth)
GPIO1
29
30
31
32
SDOUT
BCLK
Digital output
Digital I/O
Audio serial data interface bus output
Audio serial data interface bus bit clock
FSYNC
DREG
Digital I/O
Audio serial data interface bus frame synchronization signal
Digital regulator output voltage for digital core supply (1.5 V, nominal)
Digital supply
Thermal pad shorted to the internal device ground. Short the thermal pad directly to
the board ground plane.
Thermal Pad (VSS)
Ground supply
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7 Specifications
7.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–40
–65
MAX
UNIT
AVDD to AVSS
3.9
Supply voltage
BSTVDD to VSS (thermal pad)
IOVDD to VSS (thermal pad)
AVSS to VSS (thermal pad)
VBAT_IN to AVSS
3.9
V
3.9
Ground voltage differences
Battery voltage
0.3
V
V
V
V
18
Analog input voltage
Digital input voltage
Analog input pins voltage to AVSS
Digital input pins voltage to VSS (thermal pad)
Operating ambient, TA
18
IOVDD + 0.3
125
Temperature
Junction, TJ
150
°C
Storage, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Corner package pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per
AEC Q100-011
All other non-corner package
pins
±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER
AVDD(1)
BSTVDD
Analog supply voltage to AVSS
3.0
3.0
3.3
3.3
3.3
1.8
3.6
3.6
V
V
Boost converter supply voltage to VSS (thermal pad)
IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation
IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation
3.0
3.6
IOVDD
V
1.65
1.95
INPUTS
VBAT_IN
VBAT_IN input pin voltage to AVSS
0
0
12.6
18
V
V
Analog input pins voltage to AVSS for line-in recording
14.2
MICBIAS
INxx
Analog input pins voltage to AVSS for microphone recording
0.1
V
–0.1
Analog input pins voltage to AVSS during short to VBAT_IN
Digital input pins voltage to VSS (thermal pad)
VBAT_IN
IOVDD
V
V
0
TEMPERATURE
TA Operating ambient temperature
125
°C
–40
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7.3 Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
OTHERS
GPIOx or GPIx (used as MCLK input) clock frequency
SCL and SDA bus capacitance for I2C interface supports standard-mode
36.864(2)
400
MHz
pF
and fast-mode
Cb
CL
SCL and SDA bus capacitance for I2C interface supports fast-mode plus
550
50
Digital output load capacitance
20
pF
Boost converter inductor for 6MHz clocking mode (recommended inductor
CIGW201610GL2R2MLE)
2.2
µH
(1) AVSS and VSS (thermal pad); all ground pins must be tied together and must not differ in voltage by more than 0.2 V.
(2) MCLK input rise time (VIL to VIH) and fall time (VIH to VIL) must be less than 5 ns. For better audio noise performance, MCLK input
must be used with low jitter.
7.4 Thermal Information
PCM6480-Q1
THERMAL METRIC(1)
RTV (WQFN)
32 PINS
30.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
17.0
11.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
10.9
ψJB
RθJC(bot)
1.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
ADC PERFORMANCE FOR LINE INPUT RECORDING
AC-coupled input, input fault diagnostic not
TEST CONDITIONS
MIN
NOM
MAX
UNIT
supported
Differential input full-
10
VRMS
DC-coupled input, DC common-mode voltage
INxP = INxM = 7.1 V, input fault diagnostic not
supported
scale AC signal voltage
AC-coupled input, input fault diagnostic not
supported
Single-ended input full-
scale AC signal voltage
5
VRMS
DC-coupled input, DC common-mode voltage
INxP = INxM = 7.1 V, input fault diagnostic not
supported
IN1 differential AC-coupled input selected and AC
signal shorted to ground, 0-dB channel gain
105
110
110
101
Signal-to-noise ratio, A- IN1 differential DC-coupled input selected and AC
SNR
dB
weighted(1) (2)
signal shorted to ground, 0-dB channel gain
IN1 differential DC-coupled input selected and AC
signal shorted to ground, 12-dB channel gain
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7.5 Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
IN1 differential AC-coupled input selected and –
60-dB full-scale AC signal input, 0-dB channel
gain
110
IN1 differential DC-coupled input selected and –
60-dB full-scale AC signal input, 0-dB channel
gain
Dynamic range, A-
weighted(2)
DR
110
101
dB
IN1 differential DC-coupled input selected and –
72-dB full-scale AC signal input, 12-dB channel
gain
IN1 differential AC-coupled input selected and –
1-dB full-scale AC signal input, 0-dB channel gain
–95
–95
–78
IN1 differential DC-coupled input selected and –
1-dB full-scale AC signal input, 0-dB channel gain
Total harmonic
distortion(2)
THD+N
dB
dB
IN1 differential DC-coupled input selected and –
13-dB full-scale AC signal input, 12-dB channel
gain
–91
Channel gain control
range
Programmable 1-dB steps
0
42
ADC PERFORMANCE FOR MICROPHONE INPUT RECORDING
AC-coupled input, input fault diagnostic not
supported. CHx_MIC_RANGE register bit is set to
high.
DC-coupled input, DC differential common-mode
voltage INxP – INxM > 3.4 V, DC common-
mode voltage INxP < (MICBIAS –1.7 V) and DC
common-mode voltage INxM > 1.7 V.
Differential input full-
scale AC signal
voltage(3)
10
VRMS
CHx_MIC_RANGE register bit is set to high to
support AC differential signal max swing > 2
Vrms(4)
.
IN1 differential AC-coupled input selected and AC
signal shorted to ground, 0-dB channel gain
110
110
Signal-to-noise ratio, A-
weighted(1) (2)
IN1 differential DC-coupled input selected and
AC-signal shorted to ground, DC differential
common-mode voltage IN1P – IN1M < 5.0 V, 0-
dB channel gain
SNR
dB
dB
105
IN1 differential AC-coupled input selected and –
60-dB full-scale AC signal input, 0-dB channel
gain
110
110
Dynamic range, A-
weighted(2)
DR
IN1 differential DC-coupled input selected and –
60-dB full-scale AC signal input, DC differential
common-mode voltage IN1P – IN1M < 5.0 V, 0-
dB channel gain
IN1 differential AC-coupled input selected and –
1-dB full-scale AC signal input, 0-dB channel gain
–92
–90
Total harmonic
distortion(2)
THD+N
dB
dB
IN1 differential DC-coupled input selected and –
15-dB full-scale AC signal input, 0-dB channel
gain
–78
Channel gain control
range
Programmable 1-dB steps
0
42
ADC OTHER PARAMETERS
Differential input, between INxP and INxM
Single-ended input, between INxP and INxM
50
25
Input impedance
kΩ
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7.5 Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
–100
7.35
16
NOM
MAX
UNIT
Digital volume control
range
Programmable 0.5-dB steps
27
dB
Output data sample rate Programmable
768
32
kHz
Bits
Output data sample
Programmable
word length
First-order IIR filter with programmable
coefficients,
–3-dB point (default setting)
Digital high-pass filter
cutoff frequency
12
Hz
–1-dB full-scale AC signal line-in input to non
measurement channel
Interchannel isolation
dB
dB
–134
0.1
Interchannel gain
mismatch
–6-dB full-scale AC signal line-in input, 0-dB
channel gain
Interchannel phase
mismatch
1-kHz sinusoidal signal
0.01
92
Degrees
dB
Power-supply rejection 100-mVPP, 1-kHz sinusoidal signal on AVDD,
ratio
PSRR
CMRR
differential input selected, 0-dB channel gain
Differential microphone input selected, 0-dB
channel gain, 1-VRMS AC input, 1-kHz signal on
both pins and measure level at output,
CHx_CFG0 D3-2 register bits set to 2b'10 to
configure device in high CMRR performance
mode
Common-mode
rejection ratio
70
dB
MICROPHONE BIAS
MICBIAS noise
MICBIAS voltage
BW = 20 Hz to 20 kHz, A-weighted, 1-μF
capacitor between MICBIAS and AVSS
6.8
µVRMS
Programmable 0.5-V steps
5
9
V
MICBIAS current drive MICBIAS voltage 9 V
80
mA
MICBIAS load
regulation
MICBIAS voltage 9 V, measured up to maximum
load
0
1
%
MICBIAS over current
protection threshold
MICBIAS voltage 9 V
82
mA
INPUT DIAGNOSTICS
Fault monitoring
repetition rate
Programmable, DC-coupled input
1
4
8
ms
ms
Fault monitoring repetition rate 4-ms, DC-coupled
input
Fault response time
16
Threshold voltage for
(INxx –AVSS) input
shorted to ground
Programmable 60-mV steps, DC-coupled input
Programmable 30-mV steps, DC-coupled input
Programmable 30-mV steps, DC-coupled input
Programmable 30-mV steps, DC-coupled input
0
0
0
0
900
450
450
450
mV
mV
mV
mV
Threshold voltage for
(INxP –INxM) input
shorted together
Threshold voltage for
(MICBIAS –INxx) input
shorted to MICBIAS
Threshold voltage for
(VBAT –INxx) input
shorted to VBAT_IN
DIGITAL I/O
Low-level digital input
logic voltage threshold
0.25 ×
IOVDD
VIL(SHDNZ)
SHDNZ pin
V
–0.3
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7.5 Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
High-level digital input
logic voltage threshold
0.75 ×
IOVDD
IOVDD +
0.3
VIH(SHDNZ)
SHDNZ pin
V
All digital pins except SDA and SCL, IOVDD 1.8-
V operation
0.35 ×
IOVDD
–0.3
–0.3
Low-level digital input
logic voltage threshold
VIL
V
V
V
All digital pins except SDA and SCL, IOVDD 3.3-
V operation
0.8
All digital pins except SDA and SCL, IOVDD 1.8-
V operation
0.65 ×
IOVDD
IOVDD +
0.3
High-level digital input
logic voltage threshold
VIH
All digital pins except SDA and SCL, IOVDD 3.3-
V operation
IOVDD +
0.3
2
All digital pins except SDA and SCL, IOL = –2
mA, IOVDD 1.8-V operation
0.45
0.4
Low-level digital output
voltage
VOL
All digital pins except SDA and SCL, IOL = –2
mA, IOVDD 3.3-V operation
All digital pins except SDA and SCL, IOH = 2 mA,
IOVDD 1.8-V operation
IOVDD –
0.45
High-level digital output
voltage
VOH
V
All digital pins except SDA and SCL, IOH = 2 mA,
IOVDD 3.3-V operation
2.4
Low-level digital input
logic voltage threshold
0.3 ×
IOVDD
VIL(I2C)
SDA and SCL
V
V
V
V
–0.5
High-level digital input
logic voltage threshold
0.7 ×
IOVDD
IOVDD +
0.5
VIH(I2C)
VOL1(I2C)
VOL2(I2C)
SDA and SCL
Low-level digital output
voltage
0.4
SDA, IOL(I2C) = –3 mA, IOVDD > 2 V
SDA, IOL(I2C) = –2 mA, IOVDD ≤2 V
Low-level digital output
voltage
0.2 x
IOVDD
SDA, VOL(I2C) = 0.4 V, standard-mode or fast-
mode
3
20
Low-level digital output
current
IOL(I2C)
mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus
All digital pins, input = 0 V
Input logic-low leakage
for digital inputs
IIL
0.1
0.1
5
5
5
µA
µA
pF
–5
Input logic-high leakage
for digital inputs
IIH
All digital pins, input = IOVDD
All digital pins
–5
Input capacitance for
digital inputs
CIN
Pulldown resistance for
digital I/O pins when
asserted on
RPD
20
kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD
0.5
0.1
Current consumption in
hardware shutdown
mode
IBSTVDD
IIOVDD
IAVDD
SHDNZ = 0, all device external clocks stopped
All device external clocks stopped
fS = 48 kHz, BCLK = 256 × fS
µA
µA
0.1
4
Current consumption in
sleep mode (software
shutdown mode)
IBSTVDD
IIOVDD
IAVDD
0.1
0.1
Current consumption
when MICBIAS ON,
MICBIAS voltage 9 V,
40 mA load, ADC off
2.1
IBSTVDD
IIOVDD
162.5
0.01
mA
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7.5 Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
13.5
0
MAX
UNIT
IAVDD
Current consumption
with ADC 2-channel
analog input operation
at fS 16-kHz
IBSTVDD
IIOVDD
IAVDD
MICBIAS off, PLL on, BCLK = 512 × fS
mA
0.1
13.5
0
Current consumption
with ADC 2-channel
analog input operation
at fS 48-kHz
IBSTVDD
IIOVDD
IAVDD
MICBIAS off, PLL off, BCLK = 512 × fS
mA
mA
mA
0.1
24.7
0
Current consumption
with ADC 4-channel
analog input operation
at fS 48-kHz
IBSTVDD
IIOVDD
IAVDD
MICBIAS off, PLL on, BCLK = 256 × fS
0.2
9.7
0
Current consumption
with 4-channel digial
PDM input operation at and GPIO3 configured as PDMCLK = 64 × fS
fS 48 kHz
MICBIAS off, PLL on, BCLK = 256 × fS, GPIO2
IBSTVDD
IIOVDD
IAVDD
3.1
28.5
0
Current consumption
with ADC 4-channel
analog input and 4-
channel digial PDM
input operation at fS 48
kHz
IBSTVDD
MICBIAS off, PLL on, BCLK = 256 × fS, GPIO2
and GPIO3 configured as PDMCLK = 64 × fS
mA
IIOVDD
3.2
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-
weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can
result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, can affect dynamic specification values.
(3) Microphone inputs support a 2 VRMS differential input full-scale AC signal voltage, if the CHx_MIC_RANGE register bit is set to low
(default value). However, if the input DC common-mode differential voltage is higher than 4 V, then TI recommends setting the
CHx_MIC_RANGE register bit high to avoid any saturation resulting from the high input DC common-mode differential voltage.
(4) If the CHx_MIC_RANGE register bit is set to high (default value is low) in DC-coupled input configuration mode, then the input
differential DC common-mode along with input differential AC signal must be less than 10 VRMS for differential input configuration
mode. Similarly, for single-ended input configuration mode, the input DC common-mode voltage along with the input AC signal must be
less than 5 VRMS
.
7.6 Timing Requirements: I2C Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 7-1 for timing diagram
MIN
NOM
MAX
UNIT
STANDARD-MODE
fSCL
SCL clock frequency
0
4
100
kHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
tHD;STA
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
4.7
4
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
4.7
0
3.45
Data setup time
250
SDA and SCL rise time
1000
300
ns
tf
SDA and SCL fall time
ns
tSU;STO
tBUF
Setup time for STOP condition
Bus free time between a STOP and START condition
4
μs
μs
4.7
FAST-MODE
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7.6 Timing Requirements: I2C Interface (continued)
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 7-1 for timing diagram
MIN
NOM
MAX
400
UNIT
fSCL
SCL clock frequency
0
kHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
tHD;STA
0.6
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
1.3
0.6
0.6
0
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
0.9
Data setup time
100
20
SDA and SCL rise time
300
300
ns
20 ×
(IOVDD /
5.5 V)
tf
SDA and SCL fall time
ns
tSU;STO
Setup time for STOP condition
0.6
1.3
μs
μs
tBUF
Bus free time between a STOP and START condition
FAST-MODE PLUS
fSCL
SCL clock frequency
0
1000
kHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
tHD;STA
0.26
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
0.5
0.26
0.26
0
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
Data setup time
50
SDA and SCL Rise Time
120
120
ns
20 ×
(IOVDD /
5.5 V)
tf
SDA and SCL Fall Time
ns
tSU;STO
tBUF
Setup time for STOP condition
0.26
0.5
μs
μs
Bus free time between a STOP and START condition
7.7 Switching Characteristics: I2C Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 7-1 for timing diagram
PARAMETER
TEST CONDITIONS
MIN
200
200
TYP
MAX
1250
850
UNIT
ns
Standard-mode
td(SDA)
SCL to SDA delay
Fast-mode
ns
Fast-mode plus
400
ns
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7.8 Timing Requirements: SPI Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-2 for timing
diagram
MIN
40
18
18
16
16
20
8
NOM
MAX
UNIT
ns
t(SCLK)
tH(SCLK)
tL(SCLK)
tLEAD
SCLK period
SCLK high pulse duration
SCLK low pulse duration
Enable lead time
ns
ns
ns
tTRAIL
Enable trail time
ns
tDSEQ
Sequential transfer delay
MOSI data setup time
MOSI data hold time
SCLK rise time
ns
tSU(MOSI)
tHLD(MOSI)
tr(SCLK)
tf(SCLK)
ns
8
ns
10% - 90% rise time
90% - 10% fall time
6
6
ns
SCLK fall time
ns
7.9 Switching Characteristics: SPI Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-2 for timing
diagram
PARAMETER
TEST CONDITIONS
IOVDD = 1.8 V
MIN
TYP
MAX
18
UNIT
ta(MISO)
td(MISO)
tdis(MISO)
MISO access time
ns
IOVDD = 3.3 V
14
50% of SCLK to 50% of MISO,
IOVDD = 1.8 V
19
15
SCLK to MISO delay
MISO disable time
ns
ns
50% of SCLK to 50% of MISO,
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 3.3 V
18
14
7.10 Timing Requirements: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-3 for timing
diagram
MIN
40
18
18
8
NOM
MAX
UNIT
ns
t(BCLK)
BCLK period
tH(BCLK)
tL(BCLK)
tSU(FSYNC)
tHLD(FSYNC)
tr(BCLK)
BCLK high pulse duration (1)
BCLK low pulse duration (1)
FSYNC setup time
FSYNC hold time
BCLK rise time
ns
ns
ns
8
ns
10% - 90% rise time
90% - 10% fall time
10
10
ns
tf(BCLK)
BCLK fall time
ns
(1) The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is
latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
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7.11 Switching Characteristics: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-3 for timing
diagram
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50% of BCLK to 50% of
SDOUT, IOVDD = 1.8 V
18
td(SDOUT-BCLK)
BCLK to SDOUT delay
ns
50% of BCLK to 50% of
SDOUT, IOVDD = 3.3 V
14
18
50% of FSYNC to 50% of
SDOUT, IOVDD = 1.8 V
FSYNC to SDOUT delay in TDM
or LJ mode (for MSB data with
TX_OFFSET = 0)
td(SDOUT-FSYNC)
ns
50% of FSYNC to 50% of
SDOUT, IOVDD = 3.3 V
14
BCLK output clock frequency;
master mode (1)
f(BCLK)
24.576
MHz
ns
IOVDD = 1.8 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 3.3 V
14
14
14
14
BCLK high pulse duration; master
mode
tH(BCLK)
BCLK low pulse duration; master
mode
tL(BCLK)
ns
ns
50% of BCLK to 50% of
FSYNC, IOVDD = 1.8 V
18
14
10
10
8
BCLK to FSYNC delay; master
mode
td(FSYNC)
50% of BCLK to 50% of
FSYNC, IOVDD = 3.3 V
10% - 90% rise time, IOVDD =
1.8 V
tr(BCLK)
BCLK rise time; master mode
BCLK fall time; master mode
ns
ns
10% - 90% rise time, IOVDD =
3.3 V
90% - 10% fall time, IOVDD =
1.8 V
tf(BCLK)
90% - 10% fall time, IOVDD =
3.3 V
8
(1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched
on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
7.12 Timing Requirements: PDM Digital Microphone Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-4 for timing
diagram
MIN
30
0
NOM
MAX
UNIT
ns
tSU(PDMDINx)
tHLD(PDMDINx)
PDMDINx_GPIx setup time
PDMDINx_GPIx hold time
ns
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7.13 Switching Characteristics: PDM Digial Microphone Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-4 for timing
diagram
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PDMCLKx_GPIOx clock
frequency
f(PDMCLK)
tH(PDMCLK)
tL(PDMCLK)
0.768
6.144
MHz
PDMCLKx_GPIOx high pulse
duration
72
72
ns
ns
PDMCLKx_GPIOx low pulse
duration
tr(PDMCLK)
tf(PDMCLK)
PDMCLKx_GPIOx rise time
PDMCLKx_GPIOx fall time
10% - 90% rise time
18
18
ns
ns
90% - 10% fall time
7.14 Timing Diagrams
SDA
tBUF
tHD;STA
tLOW
tr
td(SDA)
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
STO
STA
tf
STA
STO
图7-1. I2C Interface Timing Diagram
SSZ
tDSEQ
tLAG
t(SCLK)
tf(SCLK)
tLEAD
tr(SCLK)
SCLK
tL(SCLK)
tH(SCLK)
td(MISO)
tdis(MISO)
MISO
MOSI
MSB OUT
LSB OUT
BIT6...1
BIT6...1
ta(MISO)
tSU(MOSI) tHLD(MOSI)
MSB IN
LSB IN
图7-2. SPI Interface Timing Diagram
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FSYNC
tSU(FSYNC)
tHLD(FSYNC)
t(BCLK)
tL(BCLK)
BCLK
tH(BCLK)
tr(BCLK)
tf(BCLK)
td(FSYNC)
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
SDOUT
图7-3. TDM, I2S, LJ Interface Timing Diagram
tSU(PDMDINx)
tHLD(PDMDINx) tSU(PDMDINx)
tHLD(PDMDINx)
tH(PDMCLK)
tL(PDMCLK)
PDMCLK
PDMDINx
t(PDMCLK)
tf(PDMCLK)
tr(PDMCLK)
Falling Edge Captured
Rising Edge Captured
图7-4. PDM Digital Microphone Interface Timing Diagram
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7.15 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode, PLL on, channel gain = 0 dB, linear phase decimation filter, and MICBIAS programmed
voltage = 8 V (unless otherwise noted); all performance measurements are done by feeding the device analog input and
PDM digital input signal using audio precision with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted)
-60
-60
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
Input Amplitude (dB)
Input Amplitude (dB)
THLiDn+e
THLiDn+e
AC-coupled differential line input
AC-coupled single-ended line input
图7-5. THD+N vs Input Amplitude
图7-6. THD+N vs Input Amplitude
-60
-70
-60
-70
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
20
50
100
500
1000
5000 10000 20000
Line
20
50
100
500
1000
5000 10000 20000
Line
Frequency (Hz)
Frequency (Hz)
AC-coupled differential line input
AC-coupled single-ended line input
图7-7. THD+N vs Input Frequency With a
–1-dBr Input (non A-weighted)
图7-8. THD+N vs Input Frequency With a
–1-dBr Input (non A-weighted)
0
-20
0
-20
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20
50
100
500
1000
5000 10000 20000
Line
20
50
100
500
1000
5000 10000 20000
Line
Frequency (Hz)
Frequency (Hz)
AC-coupled differential line input
图7-9. FFT With Idle Input (non A-weighted)
AC-coupled differential line input
图7-10. FFT With a –60-dBr Input (non A-weighted)
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7.15 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode, PLL on, channel gain = 0 dB, linear phase decimation filter, and MICBIAS programmed
voltage = 8 V (unless otherwise noted); all performance measurements are done by feeding the device analog input and
PDM digital input signal using audio precision with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted)
-60
-60
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-12
-130
-115
-100
-85
-70
-55
-40
-25
-12
Input Amplitude (dB)
Input Amplitude (dB)
TMHIDC+_
TMHIDC+_
DC-coupled differential microphone input with DC common-
mode 1NxP = 6 V and INxM = 2 V, high swing mode enabled
DC-coupled single-ended microphone input with DC common-
mode 1NxP = 4 V and INxM = 0 V, high swing mode enabled
图7-11. THD+N vs Input Amplitude
图7-12. THD+N vs Input Amplitude
DC-coupled differential microphone input with DC common-
mode 1NxP = 6 V and INxM = 2 V, High swing mode enabled
DC-coupled single-ended microphone input with DC common-
mode 1NxP = 4 V and INxM = 0 V, high swing mode enabled
图7-13. THD+N vs Input Frequency With a
–15-dBr Input (non A-weighted)
图7-14. THD+N vs Input Frequency With a
–15-dBr Input (non A-weighted)
0
0
Channel-1
Channel-2
Channel-1
Channel-2
-20
-20
Channel-3
Channel-4
Channel-5
Channel-3
Channel-4
Channel-5
-40
-40
Channel-6
-60
Channel-6
-60
-80
-100
-120
-140
-160
-180
-200
-80
-100
-120
-140
-160
-180
-200
20
50
100
500
1000
5000 10000 20000
MIC_
20
50
100
500
1000
5000 10000 20000
MIC_
Frequency (Hz)
Frequency (Hz)
DC-coupled differential microphone input with DC common-
mode 1NxP = 6 V and INxM = 2 V, high swing mode enabled
DC-coupled differential microphone input with DC common-
mode 1NxP = 6 V and INxM = 2 V, high swing mode enabled
图7-15. FFT With Idle Input (non A-weighted)
图7-16. FFT With a –60-dBr Input (non A-weighted)
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7.15 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode, PLL on, channel gain = 0 dB, linear phase decimation filter, and MICBIAS programmed
voltage = 8 V (unless otherwise noted); all performance measurements are done by feeding the device analog input and
PDM digital input signal using audio precision with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted)
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
20
50
100
500
1000
5000 10000 20000
Line
20
50
100
500
1000
5000 10000 20000
MIC_
Frequency (Hz)
Frequency (Hz)
AC-coupled differential line input
DC-coupled differential microphone input with DC common-
mode 1NxP = 6 V and INxM = 2 V, high swing mode enabled
图7-17. Power-Supply Rejection Ratio vs Ripple Frequency
图7-18. Power-Supply Rejection Ratio vs Ripple Frequency
With 1-VPP Amplitude
With 1-VPP Amplitude
0.5
70
68
66
64
62
60
58
56
54
MICBIAS 5.0 V
MICBIAS 5.5 V
MICBIAS 6.0 V
MICBIAS 6.5 V
0.4
MICBIAS 7.0 V
MICBIAS 7.5 V
MICBIAS 8.0 V
MICBIAS 8.5 V
MICBIAS 9.0 V
0.3
0.2
0.1
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
MICBIAS LOAD (mA)
MICBIAS LOAD (mA)
Effi
MICB
DC-coupled differential microphone input with DC common-
mode 1NxP = 6 V and INxM = 2 V, high swing mode enabled
DC-coupled differential microphone input
图7-19. MICBIAS Load Regulation vs MICBIAS Load Current
图7-20. Boost Efficiency vs MICBIAS Load Current
4th-order PDM modulator with PDMCLKx = 3.072 MHz
4th-order PDM modulator with PDMCLKx = 3.072 MHz
图7-22. THD+N vs Input Frequency With a –20-dBFS Input
图7-21. THD+N vs Input Amplitude
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7.15 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode, PLL on, channel gain = 0 dB, linear phase decimation filter, and MICBIAS programmed
voltage = 8 V (unless otherwise noted); all performance measurements are done by feeding the device analog input and
PDM digital input signal using audio precision with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted)
4th-order PDM modulator with PDMCLKx = 3.072 MHz
4th-order PDM modulator with PDMCLKx = 3.072 MHz
图7-23. FFT With a –60-dBFS Input (non A-weighted)
图7-24. Amplitude Response With a –20-dBFS Input
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8 Detailed Description
8.1 Overview
The PCM6480-Q1 is a scalable device that consists of high-performance, low-power, flexible, multichannel,
audio analog-to-digital converters (ADCs) with extensive feature integration. This device is intended for
automotive applications such as vehicle cabin active noise cancellation, hands-free in-vehicle communication,
emergency call, and multimedia applications. The PCM6480-Q1 is a high performance audio converter that
supports simultaneous sampling of up to a 4-channel analog microphone or a line input along with up to a 4-
channel digital pulse density-modulation (PDM) microphone input. The high dynamic range of this device
enables far-field audio recording with high fidelity. This device integrates a host of features that reduce cost,
board space, and power consumption in space-constrained automotive sub-system designs. Package,
performance, and device-compatible configuration registers make this device well suited for scalable system
designs.
The PCM6480-Q1 consists of the following blocks:
• 4-channel, multibit, high-performance delta-sigma (ΔΣ) ADCs
• 4-channel pulse density modulation (PDM) digital microphone interface with high-performance decimation
filter
• Configurable single-ended or differential audio inputs with high voltage signal swing
• High-voltage, low-noise programmable microphone bias output
• Highly flexible, comprehensive input fault diagnostic
• Automatic gain controller (AGC)
• Programmable decimation filters with linear-phase or low-latency filter
• Programmable channel gain, volume control, and biquad filters for each channel
• Programmable phase and gain calibration with fine resolution for each channel
• Programmable high-pass filter (HPF) and digital channel mixer
• Integrated low-jitter, phase-locked loop (PLL) supporting a wide range of system clocks
• Integrated digital and analog voltage regulators to support single-supply operation
Communication to the PCM6480-Q1 for configuring the control registers is supported using an I2C or SPI
interface. The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or
left-justified (LJ)] to transmit audio data seamlessly in the system across devices.
The device can support multiple devices by sharing the common I2C and TDM buses across devices. Moreover,
the device includes a daisy-chain feature and a secondary audio serial output data pin. These features relax the
shared TDM bus timing requirements and board design complexities when operating multiple devices for
applications requiring high audio data bandwidth.
表8-1 lists the reference abbreviations used throughout this document to registers that control the device.
表8-1. Abbreviations for Register References
REFERENCE
ABBREVIATION
DESCRIPTION
EXAMPLE
Single data bit. The value of a
single bit in a register.
Page y, register z, bit k
Py_Rz_Dk
Page 4, register 36, bit 0 = P4_R36_D0
Range of data bits. A range of
data bits (inclusive).
Page y, register z, bits k-m
Page y, register z
Py_Rz_D[k:m]
Py_Rz
Page 4, register 36, bits 3-0 = P4_R36_D[3:0]
Page 4, register 36 = P4_R36
One entire register. All eight
bits in the register as a unit.
Range of registers. A range of
registers in the same page.
Page y, registers z-n
Py_Rz-Rn
Page 4, registers 36, 37, 38 = P4_R36-R38
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8.2 Functional Block Diagram
PDMDIN1_GPI1
PDMDIN2_GPI2
4-Channel Digital PDM
Microphones
and Multi-Function Pin
(Faults, Interrupt, PLL Input
Clock, etc)
Audio Clock Generation
PLL
(Input Clock Source -
BCLK, GPIOx, GPIx)
Boost Converter
PDMCLK1_GPIO2
PDMCLK2_GPIO3
GPIO1
Programmable
MICBIAS
MICBIAS
Input Attenuator
and
PGA
IN1P
IN1M
ADC
Ch1
IN2P
IN2M
Input Attenuator
and
PGA
ADC
Ch2
SDOUT
BCLK
Digital Filters
(Low Latency
LPF,
Programmable
Biquads)
Audio Serial
Interface
(TDM, I2S, LJ)
Input Attenuator
and
PGA
IN3P
IN3M
FSYNC
ADC
Ch3
IN4P
IN4M
Input Attenuator
and
PGA
ADC
Ch4
SDA_SSZ
SCL_MOSI
I2C or SPI
Control Interface
Regulators / Current Bias /
Voltage Reference
ADDR0_SCLK
ADDR1_MISO
Input Diagnostics
FAULTS
SHDNZ
图8-1. Simplified Device Functional Block Diagram
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8.3 Feature Description
8.3.1 Serial Interfaces
This device has two serial interfaces: control and audio data. The control serial interface is used for device
configuration. The audio data serial interface is used for transmitting audio data to the host device.
8.3.1.1 Control Serial Interfaces
The device contains configuration registers and programmable coefficients that can be set to the desired values
for a specific system and application use. All registers can be accessed using either I2C or SPI communication to
the device. For more information, see the Programming section.
8.3.1.2 Audio Serial Interfaces
Digital audio data flows between the host processor and the PCM6480-Q1 on the digital audio serial interface
(ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S
or left-justified protocols format, programmable data length options, very flexible master-slave configurability for
bus clock lines, and the ability to communicate with multiple devices within a system directly.
The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0],
P0_R7_D[7:6] register bits. As shown in 表8-2 and 表8-3, these modes are all most significant byte (MSB)-first,
pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16, 20,
24, or 32 bits by configuring the ASI_WLEN[1:0], P0_R7_D[5:4] register bits.
表8-2. Audio Serial Interface Format
P0_R7_D[7:6] : ASI_FORMAT[1:0]
AUDIO SERIAL INTERFACE FORMAT
00 (default)
Time division multiplexing (TDM) mode
01
10
11
Inter IC sound (I2S) mode
Left-justified (LJ) mode
Reserved (do not use this setting)
表8-3. Audio Output Channel Data Word-Length
P0_R7_D[5:4] : ASI_WLEN[1:0]
AUDIO OUTPUT CHANNEL DATA WORD-LENGTH
00
01
Output channel data word-length set to 16 bits
Output channel data word-length set to 20 bits
Output channel data word-length set to 24 bits
Output channel data word-length set to 32 bits
10
11 (default)
The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the
same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio
data across the serial bus. The number of bit clock cycles in a frame must accommodate multiple device active
output channels with the programmed data word length.
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A frame consists of multiple time-division channel slots (up to 64) to allow all output channel audio data
transmissions to complete on the audio bus by a device or multiple PCM6480-Q1 devices sharing the same
audio bus. The device supports up to eight output channels that can be configured to place their audio data on
bus slot 0 to slot 63. 表 8-4 lists the output channel slot configuration settings. In I2S and LJ mode, the slots are
divided into two sets, left-channel slots and right-channel slots, as described in the Inter IC Sound (I2S) Interface
and Left-Justified (LJ) Interface sections.
表8-4. Output Channel Slot Assignment Settings
P0_R11_D[5:0] : CH1_SLOT[5:0]
00 0000 = 0d (default)
00 0001 = 1d
OUTPUT CHANNEL 1 SLOT ASSIGNMENT
Slot 0 for TDM or left slot 0 for I2S, LJ.
Slot 1 for TDM or left slot 1 for I2S, LJ.
…
…
01 1111 = 31d
10 0000 = 32d
Slot 31 for TDM or left slot 31 for I2S, LJ.
Slot 32 for TDM or right slot 0 for I2S, LJ.
…
…
11 1110 = 62d
11 1111 = 63d
Slot 62 for TDM or right slot 30 for I2S, LJ.
Slot 63 for TDM or right slot 31 for I2S, LJ.
Similarly, the slot assignment setting for output channel 2 to channel 6 can be done using the CH2_SLOT
(P0_R12) to CH6_SLOT (P0_R16) registers, respectively.
The slot word length is the same as the output channel data word length set for the device. The output channel
data word length must be set to the same value for all PCM6480-Q1 devices if all devices share the same ASI
bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available
bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data
word length configured.
The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by
up to 31 cycles of the bit clock. 表8-5 lists the programmable offset configuration settings.
表8-5. Programmable Offset Settings for the ASI Slot Start
P0_R8_D[4:0] : TX_OFFSET[4:0]
PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START
0 0000 = 0d (default)
The device follows the standard protocol timing without any offset.
Slot start is offset by one BCLK cycle, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to
standard protocol timing.
0 0001 = 1d
......
......
Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to
standard protocol timing.
1 1110 = 30d
Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to
standard protocol timing.
1 1111 = 31d
The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio
data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using
the FSYNC_POL, P0_R7_D3 register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK,
which can be set using the BCLK_POL, P0_R7_D2 register bit.
8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data
first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and
each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.
图8-2 to 图8-5 illustrate the protocol timing for TDM operation with various configurations.
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FSYNC
BCLK
SDOUT
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-2 to Slot-7
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-2. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
nth Sample
Slot-0
(Word Length : N)
(n+1)th Sample
Slot-2 to Slot-7
(Word Length : N)
TX_OFFSET = 2
TX_OFFSET = 2
图8-3. TDM Mode Protocol Timing (TX_OFFSET = 2)
FSYNC
BCLK
1
0
N-1
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
0
N-1 N-2
2
1
0
SDOUT
3
2
1
0
N-1
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
Slot-2 to Slot-7
(Word Length : N)
TX_OFFSET = 2
nth Sample
图8-4. TDM Mode Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 2)
FSYNC
BCLK
SDOUT
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-2 to Slot-7
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-5. TDM Mode Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)
For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels times the programmed word length of the output channel data.
The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well. For a
higher BCLK frequency operation, using TDM mode with a TX_OFFSET value higher than 0 is recommended.
8.3.1.2.2 Inter IC Sound (I2S) Interface
The standard I2S protocol is defined for only two channels: left and right. The device extends the same protocol
timing for multichannel operation. In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of
BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the
remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of
BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission,
the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge
of BCLK. 图8-6 to 图8-9 illustrate the protocol timing for I2S operation with various configurations.
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FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-6. I2S Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
1
0
N-1 N-2
1
0
N-1
1
0
N-1
N-1
1
0
1
0
Left
Slot-0
(Word Length : N) (Word Length : N)
Left
Slot-2 to Slot-3
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 1
TX_OFFSET = 1
TX_OFFSET = 1
nth Sample
图8-7. I2S Protocol Timing (TX_OFFSET = 1)
FSYNC
BCLK
N-1 N-2
1
0
N-1 N-2
0
0
N-1
1
0
N-1
1
0
N-1 N-2
0
N-1
1
0
1
0
N-1 N-2
SDOUT
Left
Slot-0
(Word Length : N)
(n+1)th Sample
Left
Slot-1 to Slot-3
(Word Length : N)
Right
Slot-1 to Slot-3
(Word Length : N)
nth Sample
图8-8. I2S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-9. I2S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)
For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the programmed word length
of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater
than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high
pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots
times the data word length configured.
8.3.1.2.3 Left-Justified (LJ) Interface
The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol
timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle
after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK.
Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB
of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data
bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining
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right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. 图 8-10 to 图 8-13
illustrate the protocol timing for LJ operation with various configurations.
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-10. LJ Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
1
0
N-1 N-2
1
0
N-1
1
0
N-1
N-1
1
0
1
0
Left
Slot-0
(Word Length : N) (Word Length : N)
Left
Slot-2 to Slot-3
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 2
TX_OFFSET = 2
TX_OFFSET = 2
nth Sample
图8-11. LJ Protocol Timing (TX_OFFSET = 2)
FSYNC
BCLK
N-1 N-2
1
0
N-1 N-2
0
0
N-1
1
0
N-1
1
0
N-1 N-2
0
N-1
1
0
1
0
N-1 N-2
SDOUT
Left
Slot-0
(Word Length : N)
(n+1)th Sample
Left
Slot-1 to Slot-3
(Word Length : N)
Right
Slot-1 to Slot-3
(Word Length : N)
nth Sample
图8-12. LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 1
TX_OFFSET = 1
TX_OFFSET = 1
nth Sample
图8-13. LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1)
For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the programmed word length
of the output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater
than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC low
pulse must be number of BCLK cycles wide that is greater than or equal to the number of active right slots times
the data word length configured. For a higher BCLK frequency operation, using LJ mode with a TX_OFFSET
value higher than 0 is recommended.
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8.3.1.3 Using Multiple Devices With Shared Buses
The device has many supported features and flexible options that can be used in the system to seamlessly
connect multiple PCM6480-Q1 devices by sharing a single common I2C control bus and an audio serial interface
bus. This architecture enables multiple applications to be applied to a system that require a microphone array for
beam-forming operation, hands-free in-vehicle communication, car cabin active noise cancellation, and so forth.
图 8-14 shows a diagram of multiple PCM6480-Q1 devices in a configuration where the control and audio data
buses are shared.
Control Bus œ I2C Interface
PCM6xx0-Q1
U1
PCM6xx0-Q1
U2
PCM6xx0-Q1
U3
PCM6xx0-Q1
U4
Host Processor
Audio Data Bus œ TDM, I2S, LJ Interface
图8-14. Multiple PCM6480-Q1 Devices With Shared Control and Audio Data Buses
The PCM6480-Q1 consist of the following features to enable seamless connection and interaction of multiple
devices using a shared bus:
• Supports up to four pin-programmable I2C slave addresses
• I2C broadcast simultaneously writes to (or triggers) all PCM6480-Q1 devices
• Supports up to 64 configuration output channel slots for the audio serial interface
• Tri-state feature (with enable and disable) for the unused audio data slots of the device
• Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus
• The GPIOx pin can be configured as a secondary output data lane for the audio serial interface
• The GPIOx or GPIx pin can be used in a daisy-chain configuration of multiple PCM6480-Q1 devices
• Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface
• Programmable master and slave options for the audio serial interface
• Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices
See the Multiple PCM6xx0-Q1 Devices With Shared TDM and I2C Bus application report for further details.
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8.3.2 Phase-Locked Loop (PLL) and Clock Generation
The device has a smart auto-configuration block to generate all necessary internal clocks required for the ADC
modulator and the digital filter engine used for signal processing. This configuration is done by monitoring the
frequency of the FSYNC and BCLK signal on the audio bus.
The device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to
FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming.
表8-6 and 表8-7 list the supported FSYNC and BCLK frequencies.
表8-6. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
RATIO
FSYNC
(8 kHz)
FSYNC
(16 kHz)
FSYNC
(24 kHz)
FSYNC
(32 kHz)
FSYNC
(48 kHz)
FSYNC
(96 kHz)
FSYNC (192 FSYNC (384 FSYNC (768
kHz)
kHz)
kHz)
16
24
Reserved
Reserved
0.256
0.256
0.384
0.384
0.576
0.512
0.768
0.768
1.152
1.536
2.304
3.072
6.144
12.288
4.608
9.216
18.432
32
0.512
0.768
1.024
1.536
3.072
6.144
12.288
24.576
48
0.384
0.768
1.152
1.536
2.304
4.608
9.216
18.432
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64
0.512
1.024
1.536
2.048
3.072
6.144
12.288
24.576
96
0.768
1.536
2.304
3.072
4.608
9.216
18.432
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
192
256
384
512
1024
2048
1.024
2.048
3.072
4.096
6.144
12.288
18.432
24.576
Reserved
Reserved
Reserved
Reserved
24.576
1.536
3.072
4.608
6.144
9.216
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2.048
4.096
6.144
8.192
12.288
18.432
24.576
Reserved
Reserved
3.072
6.144
9.216
12.288
16.384
Reserved
Reserved
4.096
8.192
12.288
24.576
Reserved
8.192
16.384
Reserved
16.384
表8-7. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
RATIO
FSYNC
(7.35 kHz)
FSYNC
FSYNC
FSYNC
FSYNC
(44.1 kHz)
FSYNC
FSYNC
FSYNC
FSYNC
(14.7 kHz) (22.05 kHz) (29.4 kHz)
(88.2 kHz) (176.4 kHz) (352.8 kHz) (705.6 kHz)
16
24
Reserved
Reserved
Reserved
0.3528
Reserved
0.3528
0.4704
0.7056
0.9408
1.4112
0.3528
0.5292
0.7056
1.0584
1.4112
0.4704
0.7056
0.7056
1.0584
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
16.9344
32
0.9408
1.4112
2.8224
5.6448
11.2896
22.5792
48
1.4112
2.1168
4.2336
8.4672
16.9344
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64
0.4704
1.8816
2.8224
5.6448
11.2896
22.5792
96
0.7056
2.1168
2.8224
4.2336
8.4672
16.9344
22.5792
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
192
256
384
512
1024
2048
0.9408
1.8816
2.8224
3.7632
5.6448
7.5264
15.0528
Reserved
2.8224
4.2336
5.6448
8.4672
11.2896
22.5792
Reserved
3.7632
5.6448
11.2896
16.9344
22.5792
Reserved
Reserved
Reserved
Reserved
1.4112
5.6448
8.4672
1.8816
7.5264
11.2896
16.9344
22.5792
Reserved
Reserved
2.8224
11.2896
15.0528
Reserved
Reserved
3.7632
7.5264
15.0528
The status register ASI_STS, P0_R21, captures the device auto detect result for the FSYNC frequency and the
BCLK to FSYNC ratio. If the device finds any unsupported combinations of FSYNC frequency and BCLK to
FSYNC ratios, the device generates an ASI clock-error interrupt and mutes the record channels accordingly.
The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the
ADC modulator and digital filter engine, as well as other control blocks. The device also supports an option to
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use the BCLK, GPIOx, or the GPIx pin (as MCLK) as the audio clock source without using the PLL to reduce
power consumption. However, the ADC performance may degrade based on jitter from the external clock
source, and some processing features may not be supported if the external audio clock source frequency is not
high enough. Therefore, TI recommends using the PLL for high-performance applications.
The device also supports an audio bus master mode operation using the GPIOx or GPIx pin (as MCLK) as the
reference input clock source and supports various flexible options and a wide variety of system clocks. More
details and information on master mode configuration and operation are discussed in the Configuring and
Operating TLV320ADCx140 as Audio Bus Master application report.
The audio bus clock error detection and auto-detect feature automatically generates all internal clocks, but can
be disabled using the ASI_ERR, P0_R9_D5 and AUTO_CLK_CFG, P0_R19_D6, register bits, respectively. In
the system, this disable feature can be used to support custom clock frequencies that are not covered by the
auto detect scheme. For such application use cases, care must be taken to ensure that the multiple clock
dividers are all configured appropriately. Therefore, TI recommends using the PPC3 GUI for device configuration
settings; for more details see the PCM6xx0Q1EVM-PDK Evaluation Module user's guide and the PurePath™
Console Graphical Development Suite for Audio System Design and Development development suite.
8.3.3 Analog Input Channel Configuration
The PCM6480-Q1 consists of four pairs of analog input pins (INxP and INxM) that can be configured as either
differential or single-ended inputs for the recording channel. The device supports simultaneous recording of up to
four channels using the multichannel ADC. The input source for the analog pins can be either analog
microphones or line, aux inputs from the system board. 表 8-8 describes how to set the input configuration for
the record channel.
表8-8. Input Source Selection for the Record Channel
P0_R60_D[6:5] :
CH1_INSRC[1:0]
INPUT CHANNEL 1 RECORD SOURCE SELECTION
00 (default)
01
Analog differential input for channel 1
Analog single-ended input for channel 1
Reserved (do not use this setting)
10 or 11
Similarly, the input source selection setting for input channel 2 to channel 6 can be configured using the
CH2_INSRC[1:0] (P0_R65_D[6:5]) to CH6_INSRC[1:0] (P0_R85_D[6:5]) registers bits, respectively.
The device supports the input DC fault diagnostic feature for microphone recording with the DC-coupled inputs
configuration; however, the device also supports an option for AC-coupled inputs if the DC diagnostic is not
required for the specific input pins. This configuration can be done independently for each channel by setting the
CH1_DC (P0_R60_D4) to CH6_DC (P0_R85_D4) register bits.
For the DC-coupled line input configuration, the DC common-mode difference (INxP – INxM) for the analog
input pins must be 0 V to support the 10-VRMS full-scale differential input. For the DC-coupled microphone input
configuration, the DC common-mode difference (INxP – INxM) for the analog input pins must be within 3.4 V to
5.0 V to support the 2-VRMS full-scale differential input in the default mode of operation. Alternatively, the device
has a mode to support more than a 2-VRMS differential DC-coupled microphone signal by setting the
CH1_MIC_IN_RANGE, P0_R60_D3, register bit for channel 1 and, similarly, the CH2_MIC_IN_RANGE,
P0_R65_D3 to CH6_MIC_IN_RANGE, P0_R85_D3 registers bit (respectively) for channels 2 to 6. If the
CH1_MIC_IN_RANGE bit is set high (the recommended setting to support a higher DC common-mode
difference and a higher AC signal swing), then the device supports the maximum differential input voltage
IN1P–IN1M as high as 8.4 V (for the MICBIAS 9-V setting), including the AC signal and DC differential
common-mode voltage. The DC differential common-mode voltage is later filtered out by the digital high-pass
filter and the digital output full-scale corresponds to the 10-VRMS AC signal in this case.
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图 8-15 and 图 8-16 show how to connect a DC-coupled microphone for a differential and single-ended input,
respectively. The value of the external bias resistor, R1, must be appropriately chosen based upon the
microphone impedance. For a differential input, the value of the external bias resistor is recommended to be
used for half of the microphone impedance, whereas for a single-ended input, the external bias resistor is
recommended to be the same as the microphone impedance.
MICBIAS
PCM6xx0-Q1
GND
DC-Coupled
Microphone
Differential Input
INxP
INxM
GND
图8-15. DC-Coupled Microphone Differential Input Connection
MICBIAS
PCM6xx0-Q1
GND
DC-Coupled
Microphone
Single-ended Input
INxP
INxM
GND
图8-16. DC-Coupled Microphone Single-Ended Input Connection
In AC-coupled mode, the value of the coupling capacitor must be so chosen that the high-pass filter formed by
the coupling capacitor and the input impedance do not affect the signal content. At power-up, before proper
recording can begin, this coupling capacitor must be charged up to the common-mode voltage. For single-ended
input configuration, the INxM pin must be grounded after the AC coupling capacitor in AC-coupled mode.
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图 8-17 and 图 8-18 show how to connect an AC-coupled microphone or line source for a differential and single-
ended input, respectively. In AC-coupled mode, the device input pins INxP and INxM, must be biased
appropriately for the DC common-mode value either using the on-chip MICBIAS output voltage along with
external bias resistor, R0, or using an external bias generator circuit. The maximum value for resistor R0
depends upon the signal swing and the MICBIAS value programmed. See the PCM6xx0-Q1 AC Coupled
External Resistor Calculator to calculate the R0 value for the desired system configuration.
MICBIAS
PCM6xx0-Q1
GND
C0 …F
INxP
INxM
AC-Coupled
Microphone or Line
Differential Input
C0 …F
图8-17. AC-Coupled Microphone or Line Differential Input Connection
MICBIAS
PCM6xx0-Q1
GND
C0 …F
INxP
INxM
AC-Coupled
Microphone or Line
Single-ended Input
C0 …F
GND
图8-18. AC-Coupled Microphone or Line Single-Ended Input Connection
8.3.4 Reference Voltage
All audio data converters require a DC reference voltage. The PCM6480-Q1 achieves its low-noise performance
by internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap
circuit with good PSRR performance. This audio converter reference voltage must be filtered externally using a
minimum 1-µF capacitor connected from the VREF pin to the analog ground (AVSS).
To achieve low power consumption, this audio reference block is powered down in sleep mode or software
shutdown; see the Sleep Mode or Software Shutdown section for more details. When exiting sleep mode, the
audio reference block is powered up using internal fast-charge scheme and the VREF pin settles to its steady-
state voltage after the settling time (a function of the decoupling capacitor on the VREF pin). This time is
approximately equal to 3.5 ms when using a 1-μF decoupling capacitor. If a higher value of the decoupling
capacitor is used on the VREF pin, the fast-charge setting must be reconfigured using the VREF_QCHG,
P0_R2_D[4:3] register bits, which support options of 3.5 ms (default), 10 ms, 50 ms, or 100 ms.
8.3.5 Microphone Bias
The device integrates a built-in, low-noise, programmable, high-voltage, microphone bias pin (MICBIAS) that can
be used in the system for biasing the analog microphone. The integrated bias amplifier supports up to 80 mA of
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load current, which can be used for multiple microphones and is designed to provide a combination of high
PSRR, low noise, and programmable bias voltages to allow the biasing to be fine tuned for specific microphone
combinations. The PCM6480-Q1 has an integrated efficient boost converter to generate the high voltage supply
for the programmable microphone bias using an external, low-voltage, 3.3-V BSTVDD supply.
When using the MICBIAS pin for biasing multiple microphones, TI recommends avoiding common impedance on
the board layout for the MICBIAS connection to minimize coupling across microphones. 表 8-9 shows the
available microphone bias programmable options.
表8-9. MICBIAS Programmable Settings
P0_R59_D[7:4] : MBIAS_VAL[3:0]
MICBIAS OUTPUT VOLTAGE
0000 to 0110
0111
Reserved (do not use these settings)
Set to 5.0 V
Set to 5.5 V
Set to 6.0 V
Set to 6.5 V
Set to 7.0 V
Set to 7.5 V
Set to 8.0 V
Set to 8.5 V
Set to 9.0 V
1000
1001
1010
1011
1100
1101
1110
1111
The microphone bias output can be powered on or powered off (default) by configuring the MICBIAS_PDZ,
P0_R117_D7 register bit. Additionally, the device provides an option to configure the GPIOx pins to directly
control the microphone bias output power on or power off. This feature is useful in some systems to control the
microphone directly without engaging the host for I2C or SPI communication. The MICBIAS_PDZ, P0_R117_D7
register bit value is ignored if the GPIOx pins are configured to control the microphone bias power on or power
off.
8.3.6 Input DC Fault Diagnostics
Each input of the PCM6480-Q1 features highly comprehensive DC fault diagnostics that can be configured to
detect fault conditions in the DC-coupled input configuration and trigger an interrupt request to a host processor.
Diagnostics are enabled for each channel by configuring DIAG_CFG0, P0_R100. For channels with diagnostics
enabled, the input pins are scanned automatically by an integrated SAR ADC with a programmable repetition
rate. The repetition rate can be configured using the REP_RATE, P0_R103_D7-6 register bits. For fastest fault
response time and also to get better signal integrity and signal chain performance for the record channel,
REP_RATE must be configured to 0 (non-default setting) . The diagnostic processor averages eight consecutive
samples per test to improve noise performance. The DC fault diagnostics is not supported in the AC-coupled
input configuration.
The device features various programmable threshold registers, P0_R101 to P0_R102, which can by configured
by the host processor to define the fault region for a different category of fault condition detection. Additionally,
there is also a debounce feature, configured with FAULT_DBNCE_SEL, P0_R103_D3-2. This feature sets the
number of consecutive scan counts where the fault condition occurs before the latched status register is tripped,
thus reducing false triggers by transient events. The device also has a moving average feature, P0_R104, which
continuously averages out the newly measured data with old measured data and thus reduces the false triggers
by any short-duration transient events.
8.3.6.1 Fault Conditions
8.3.6.1.1 Input Pin Short to Ground
A short to ground fault occurs when the voltage of the input pin is measured below the threshold voltage with
respect to ground (AVSS). The threshold can be set by configuring DIAG_SHT_GND, P0_R102_D7-4.
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8.3.6.1.2 Input Pin Short to MICBIAS
A short to MICBIAS fault occurs when the difference between the voltage measured for the MICBIAS pin and the
input pin (MICBIAS – INxx) is less than the threshold. The threshold can be set by configuring
DIAG_SHT_MICBIAS, P0_R102_D3-0.
8.3.6.1.3 Open Inputs
In the event that a microphone becomes disconnected from the inputs, the microphone bias resistors pull INxP
to MICBIAS and INxM to ground. The combination of INxP shorted to MICBIAS and INxM shorted to ground for
the same channel in a diagnostic sweep results in an open input fault condition.
8.3.6.1.4 Short Between INxP and INxM
An input terminal shorted fault occurs when the difference between the voltage measured for the input pin INxP
and the input pin INxM of the same channel is less than the threshold. The threshold can be set by configuring
DIAG_SHT_TERM, P0_R101_D7-4.
8.3.6.1.5 Input Pin Overvoltage
An input terminal overvoltage fault occurs when the voltage measured for the input pin is above the voltage
measured for the MICBIAS pin.
8.3.6.1.6 Input Pin Short to VBAT_IN
A short to VBAT_IN fault occurs when the difference between the voltage measured for the VBAT_IN pin and the
input pin, ABS(VBAT_IN – INxx), is less than the threshold or both the VBAT_IN and INxx pin measured
voltages are above 11.7 V. The threshold can be set by configuring DIAG_SHT_VBAT_IN, P0_R101_D3-0.
When VBAT_IN is less than MICBIAS, false fault detections can exist based on the signal level of the INxx pin.
To minimize false detections there is also a separate debounce count for this condition set by configuring
VSHORT_DBNCE, P0_R106_D1.
8.3.6.2 Fault Reporting
Faults are reported in live and latched status registers. The live registers, P1_R45 to P1_R55, are updated
continuously with each new scan and report the most recent measurements reported by the diagnostics
processor. The latched status of each diagnostic fault is reported by the channel in P0_R46 to P0_R55, and a
latched summary by the channel is reported in CHx_LTCH, P0_R45. If LTCH_CLR_ON_READ, P0_R40_D0, is
set to '0', then the latched registers clear upon reading and are latched if the associated bit in the live fault
registers transitions from a ‘0’ to a ‘1’. A transition of any bit in the latched register from a ‘0’ to ‘1’
triggers an interrupt request.
For detecting a persistent fault, an additional mode is available for the latched registers. In this mode, the
latched registers are only cleared upon reading if the status bit in the associated live status register is ‘0’ at
the time of reading. This mode is enabled (default setting) by configuring LTCH_CLR_ON_READ, P0_R40_D0
to a ‘1’.
8.3.6.2.1 Overcurrent and Overtemperature Protection
The device has an overcurrent protection circuit that limits the current drawn out of the MICBIAS output to the
maximum supported level when an external undesired short event occurs on the MICBIAS pin. The device sets
the status flag, P0_R44_D4 bit, on an overcurrent detection. Additionally, the device has an overtemperature
detection circuit that is enabled by default and sets the status flag, P0_R44_D5 bit, whenever the die junction
temperature goes higher than the supported level.
Additionally, the P0_R58 and P0_R40_D4:3 register can be configured to shutdown MICBIAS along with the on-
chip boost on an overtemperature detection. TI recommends configuring PD_ON_FLT_CFG, P0_R40_D4-3 to
"10" so that on an overtemperature detection, the device powers-down MICBIAS, the on-chip boost, and all ADC
channels.
More details and information on fault diagnostics are discussed in the PCM6xx0-Q1 Fault Diagnostics Features
application report.
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8.3.7 Digital PDM Microphone Record Channel
In addition to supporting analog microphones, the device also interfaces to digital PDM microphones and uses
high order and high performance decimation filters to generate PCM output data which can be transmitted on
audio serial interface to host. The PDMDINx_GPIx and PDMCLKx_GPIOx pins respectively and can be
configured for PDMDIN and PDMCLK for digital PDM microphone recording. The device support up to four
digital microphone recording channel.
The device internally generates PCMCLK with a programmable frequency either 6.144 MHz, 3.072 MHz, 1.536
MHz, or 768 kHz (for output data sample rates that are multiples or sub-multiples of 48 kHz) or 5.6448 MHz,
2.8224 MHz, 1.4112 MHz, or 705.6 kHz (for output data sample rates that are multiples or sub-multiples of
44.1 kHz) using PDMCLK_DIV[1:0], P0_R31_D[1:0] register bits. This PDMCLK can be routed on the
PDMCLKx_GPIOx pin. As shown in 图 8-19, this clock can be connected to the external digital microphone
device.
VDD
VDD
VDD
DATA
IOVDD
Digital
PDM
SEL Microphone
U1
CLK
GND
GND
PCM6480-Q1
VDD
VDD
PDMDINx_GPIx
DATA
CLK
Digital
PDM
SEL Microphone
U2
PDMCLKx_GPOIx
GND
GND
图8-19. Digital PDM Microphones Connection Diagram to the PCM6480-Q1
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The single-bit output of the external digital microphone device can be connected to the PDMDINx_GPIx pins.
The single data line can be shared by two digital microphones to place their data on the opposite edge of
PDMCLK. Internally, the device latches the steady value of data on the rising edge of PDMCLK or the falling
edge of PDMCLK based on the configuration register bits set in P0_R32_D[7:4]. 图 8-20 shows the digital PDM
microphone interface timing diagram.
PDMCLKx_GPIOx
PDMDINx_GPIx
D1[n]
D2[n]
D1[n+1]
D2[n+1]
D1[n+2]
Mic-1
Data
Mic-2
Data
Mic-1
Data
Mic-2
Data
Mic-1
Data
(n+1)th Sample
(n+2)th Sample
nth Sample
图8-20. Digital PDM Microphone Protocol Timing Diagram
When the digital microphone is used for recording, the analog section of the respective ADC channel is powered
down and bypassed for power efficiency. Selecting the analog microphone or digital microphone for channel 1 to
channel 4 is done by using the CH5_INSRC[1:0] (P0_R80_D[6:5]), CH6_INSRC[1:0] (P0_R85_D[6:5]),
CH7_INSRC[1:0] (P0_R90_D[6:5]), and CH8_INSRC[1:0] (P0_R95_D[6:5]) register bits.
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8.3.8 Signal-Chain Processing
The PCM6480-Q1 signal chain is comprised of very-low-noise, high-performance, and low-power analog blocks
and highly flexible and programmable digital processing blocks. The high performance and flexibility combined
with a compact package makes the PCM6480-Q1 optimized for a variety of end-equipment and applications that
require multichannel audio capture. 图 8-21 shows a conceptual block diagram that highlights the various
building blocks used in the signal chain, and how the blocks interact in the signal chain.
INxP
Phase
Calibration
Decimation
Filters
Input
Attenuator
PGA
ADC
INxM
Output
Channel
Data to ASI
Digital Summer/Mixer
(Applies to Ch1-Ch4
only)
Gain
Calibration
Biquad
Filters
Digital Volume
Control (DVC)
HPF
Ch1-Ch4 Processed Data after Gain
Calibration
图8-21. Analog Input Signal-Chain Processing Flowchart
The front-end input attenuator allows the device to accept the high-voltage input signal that is attenuated by the
input attenuator circuit before being routed to a low-noise programmable gain amplifier (PGA). Along with a low-
noise and low-distortion, multibit, delta-sigma ADC, the front-end PGA enables the PCM6480-Q1 to record a far-
field audio signal with very high fidelity, both in quiet and loud environments. Moreover, the ADC architecture has
inherent antialias filtering with a high rejection of out-of-band frequency noise around multiple modulator
frequency components. Therefore, the device prevents noise from aliasing into the audio band during ADC
sampling. Further on in the signal chain, an integrated, high-performance multistage digital decimation filter
sharply cuts off any out-of-band frequency noise with high stop-band attenuation.
The device also has an integrated programmable biquad filter that allows for custom low-pass, high-pass, or any
other desired frequency shaping. Thus, the overall signal chain architecture removes the requirement to add
external components for antialiasing low-pass filtering, and thus saves drastically on the external system
component cost and board space. See the PCM6xx0-Q1 Integrated Analog Antialiasing Filter and Flexible Digital
Filter application report for further details.
The device also supports up to a 4-channel digital PDM microphone recording for channels using the
PDMDINx_GPIx and PDMCLKx_GPIOx pins. The channel 1 to channel 4 signal chain block diagram is same as
shown in 图8-21; however, channel 5 to channel 8 only support a digital microphone recording option, as shown
in 图8-22, and do not support the digital summer or mixer option.
PDMCLK
High Performance
Decimation
Filters
PDM
Interface
Digital Microphone
Phase
Calibration
PDMIN
Output
Channel
Data to ASI
Gain
Calibration
Biquad
Filters
Digital Volume
Control (DVC)
HPF
图8-22. Digital PDM Input Signal-Chain Processing Flowchart
The signal chain also consists of various highly programmable digital processing blocks, such as phase
calibration, gain calibration, high-pass filter, digital summer or mixer, biquad filters, and volume control. The
details on these processing blocks are discussed further in this section.
The desired input channels for recording can be enabled or disabled by using the IN_CH_EN (P0_R115)
register, and the output channels for the audio serial interface can be enabled or disabled by using the
ASI_OUT_EN (P0_R116) register. In general, the device supports simultaneous power-up and power-down of all
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active channels for simultaneous recording. However, based on the application needs, if some channels must be
powered-up or powered-down dynamically when the other channel recording is on, then that use case is
supported by setting the DYN_CH_PUPD_EN, P0_R117_D4 register bit to 1'b1 but do not power-down channel
1 in this mode of operation.
The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal
to be recorded by using a 176.4-kHz (or higher) sample rate.
For output sample rates of 48 kHz or lower, the device supports all features for 8-channel recording and various
programmable processing blocks. However, for output sample rates higher than 48 kHz, there are limitations in
the number of simultaneous channel recordings supported and the number of biquad filters and such. See the
PCM6xx0-Q1 Sampling Rates and Programmable Processing Blocks Supported application report for further
details.
8.3.8.1 Programmable Channel Gain and Digital Volume Control
The device has an independent programmable channel gain setting for each input channel that can be set to the
appropriate value based on the maximum input signal expected in the system and the ADC VREF setting used
(see the Reference Voltage section), which determines the ADC full-scale signal level.
Configure the desired channel gain setting before powering up the ADC channel and do not change this setting
while the ADC is powered on. The programmable range supported for each channel gain is from 0 dB to 42 dB
in steps of 1 dB. To achieve low-noise performance, the device internal logic first maximizes the gain for the
front-end low-noise analog PGA, and then applies any residual programmed channel gain in the digital
processing block.
表8-10 shows the programmable options available for the channel gain.
表8-10. Channel Gain Programmable Settings
P0_R61_D[7:2] : CH1_GAIN[5:0]
00 0000 = 0d (default)
00 0001 = 1d
CHANNEL GAIN SETTING FOR INPUT CHANNEL 1
Input channel 1 gain is set to 0 dB
Input channel 1 gain is set to 1 dB
Input channel 1 gain is set to 2 dB
00 0010 = 2d
…
…
10 1001 = 41d
Input channel 1 gain is set to 41 dB
Input channel 1 gain is set to 42 dB
Reserved (do not use these settings)
10 1010 = 42d
10 1011 to 11 1111 = 43d to 63d
Similarly, the channel gain setting for input channel 2 to channel 6 can be configured using the CH2_GAIN
(P0_R66) to CH6_GAIN (P0_R86) register bits, respectively.
The device also has a programmable digital volume control with a range from –100 dB to 27 dB in steps of
0.5 dB with the option to mute the channel recording. The digital volume control value can be changed
dynamically while the ADC channel is powered-up and recording. During volume control changes, the soft ramp-
up or ramp-down volume feature is used internally to avoid any audible artifacts. Soft-stepping can be entirely
disabled using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.
The digital volume control setting is independently available for each output channel, including the digital
microphone record channel. However, the device also supports an option to gang-up the volume control setting
for all channels together using the channel 1 digital volume control setting, regardless if channel 1 is powered up
or powered down. This gang-up can be enabled using the DVOL_GANG (P0_R108_D7) register bit.
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表8-11 shows the programmable options available for the digital volume control.
表8-11. Digital Volume Control (DVC) Programmable Settings
P0_R62_D[7:0] : CH1_DVOL[7:0]
DVC SETTING FOR OUTPUT CHANNEL 1
0000 0000 = 0d
Output channel 1 DVC is set to mute
0000 0001 = 1d
Output channel 1 DVC is set to –100 dB
Output channel 1 DVC is set to –99.5 dB
Output channel 1 DVC is set to –99 dB
…
0000 0010 = 2d
0000 0011 = 3d
…
1100 1000 = 200d
1100 1001 = 201d (default)
1100 1010 = 202d
Output channel 1 DVC is set to –0.5 dB
Output channel 1 DVC is set to 0 dB
Output channel 1 DVC is set to 0.5 dB
…
…
1111 1101 = 253d
1111 1110 = 254d
1111 1111 = 255d
Output channel 1 DVC is set to 26 dB
Output channel 1 DVC is set to 26.5 dB
Output channel 1 DVC is set to 27 dB
Similarly, the digital volume control setting for output channel 2 to channel 6 can be configured using the
CH2_DVOL (P0_R67) to CH6_DVOL (P0_R87) register bits, respectively.
The internal digital processing engine soft ramps up the volume from a muted level to the programmed volume
level when the channel is powered up, and the internal digital processing engine soft ramps down the volume
from a programmed volume to mute when the channel is powered down. This soft-stepping of volume is done to
prevent abruptly powering up and powering down the record channel. This feature can also be entirely disabled
using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.
8.3.8.2 Programmable Channel Gain Calibration
Along with the programmable channel gain and digital volume, this device also provides programmable channel
gain calibration. The gain of each channel can be finely calibrated or adjusted in steps of 0.1 dB for a range of –
0.8-dB to 0.7-dB gain error. This adjustment is useful when trying to match the gain across channels resulting
from external components and microphone sensitivity. This feature, in combination with the regular digital
volume control, allows the gains across all channels to be matched for a wide gain error range with a resolution
of 0.1 dB. 表8-12 shows the programmable options available for the channel gain calibration.
表8-12. Channel Gain Calibration Programmable Settings
P0_R63_D[7:4] : CH1_GCAL[3:0]
CHANNEL GAIN CALIBRATION SETTING FOR INPUT CHANNEL 1
0000 = 0d
Input channel 1 gain calibration is set to –0.8 dB
0001 = 1d
Input channel 1 gain calibration is set to –0.7 dB
…
…
1000 = 8d (default)
Input channel 1 gain calibration is set to 0 dB
…
…
1110 = 14d
1111 = 15d
Input channel 1 gain calibration is set to 0.6 dB
Input channel 1 gain calibration is set to 0.7 dB
Similarly, the channel gain calibration setting for input channel 2 to channel 6 can be configured using the
CH2_GCAL (P0_R68) to CH6_GCAL (P0_R88) register bits, respectively.
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8.3.8.3 Programmable Channel Phase Calibration
In addition to the gain calibration, the phase delay in each channel can be finely calibrated or adjusted in steps
of one modulator clock cycle for a cycle range of 0 to 255 for the phase error. The modulator clock, the same
clock used for ADC_MOD_CLK, is 6.144 MHz (the output data sample rate is multiples or submultiples of 48
kHz) or 5.6448 MHz (the output data sample rate is multiples or submultiples of 44.1 kHz). This feature is very
useful for many applications that must match the phase with fine resolution between each channel, including any
phase mismatch across channels resulting from external components or microphones. 表 8-13 shows the
available programmable options for channel phase calibration.
表8-13. Channel Phase Calibration Programmable Settings
P0_R64_D[7:0] : CH1_PCAL[7:0]
0000 0000 = 0d (default)
0000 0001 = 1d
CHANNEL PHASE CALIBRATION SETTING FOR INPUT CHANNEL 1
Input channel 1 phase calibration with no delay
Input channel 1 phase calibration delay is set to one cycle of the modulator clock
Input channel 1 phase calibration delay is set to two cycles of the modulator clock
0000 0010 = 2d
…
…
1111 1110 = 254d
1111 1111 = 255d
Input channel 1 phase calibration delay is set to 254 cycles of the modulator clock
Input channel 1 phase calibration delay is set to 255 cycles of the modulator clock
Similarly, the channel phase calibration setting for input channel 2 to channel 6 can be configured using the
CH2_PCAL (P0_R69) to CH6_PCAL (P0_R89) register bits, respectively.
8.3.8.4 Programmable Digital High-Pass Filter
To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data,
the device supports a programmable high-pass filter (HPF). The HPF is not a channel-independent filter setting
but is globally applicable for all ADC channels. This HPF is constructed using the first-order infinite impulse
response (IIR) filter, and is efficient enough to filter out possible DC components of the signal. 表8-14 shows the
predefined –3-dB cutoff frequencies available that can be set by using the HPF_SEL[1:0] register bits of
P0_R107. Additionally, to achieve a custom –3-dB cutoff frequency for a specific application, the device also
allows the first-order IIR filter coefficients to be programmed when the HPF_SEL[1:0] register bits are set to
2'b00. 图8-23 illustrates a frequency response plot for the HPF filter.
表8-14. HPF Programmable Settings
P0_R107_D[1:0] :
HPF_SEL[1:0]
-3-dB CUTOFF FREQUENCY
SETTING
-3-dB CUTOFF FREQUENCY AT
16-kHz SAMPLE RATE
-3-dB CUTOFF FREQUENCY AT
48-kHz SAMPLE RATE
00
01 (default)
10
Programmable 1st-order IIR filter
0.00025 × fS
Programmable 1st-order IIR filter
Programmable 1st-order IIR filter
4 Hz
32 Hz
128 Hz
12 Hz
96 Hz
0.002 × fS
11
0.008 × fS
384 Hz
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3
0
-3
-6
-9
-12
-15
-18
-21
-24
-27
-30
-33
-36
-39
-42
-45
HPF -3 dB Cutoff = 0.00025 ì fS
HPF -3 dB Cutoff = 0.002 ì fS
HPF -3 dB Cutoff = 0.008 ì fS
5E-5
0.0001
0.0005
0.001
Normalized Frequency (1/fS)
0.005
0.01
0.05
D003
图8-23. HPF Filter Frequency Response Plot
方程式1 gives the transfer function for the first-order programable IIR filter:
00 + 01VF1
231 F &1VF1
: ;
* V =
(1)
The frequency response for this first-order programmable IIR filter with default coefficients is flat at a gain of 0 dB
(all-pass filter). The host device can override the frequency response by programming the IIR coefficients in 表
8-15 to achieve the desired frequency response for high-pass filtering or any other desired filtering. If
HPF_SEL[1:0] are set to 2'b00, the host device must write these coefficients values for the desired frequency
response before powering-up any ADC channel for recording. These programmable coefficients are 32-bit,
two’s complement numbers. 表8-15 shows the filter coefficients for the first-order IIR filter.
表8-15. 1st-Order IIR Filter Coefficients
FILTER
COEFFICIENT
COEFFICIENT REGISTER
MAPPING
FILTER
DEFAULT COEFFICIENT VALUE
0x7FFFFFFF
N0
N1
D1
P4_R72-R75
P4_R76-R79
P4_R80-R83
Programmable 1st-order IIR filter (can be
allocated to HPF or any other desired filter)
0x00000000
0x00000000
8.3.8.5 Programmable Digital Biquad Filters
The device supports up to 12 programmable digital biquad filters. These highly efficient filters achieve the
desired frequence response. In digital signal processing, a digital biquad filter is a second-order, recursive linear
filter with two poles and two zeros. 方程式2 gives the transfer function of each biquad filter:
00 + 201VF1 + 02VF2
231 F 2&1VF1 F &2VF2
: ;
* V =
(2)
The frequency response for the biquad filter section with default coefficients is flat at a gain of 0 dB (all-pass
filter). The host device can override the frequency response by programming the biquad coefficients to achieve
the desired frequency response for a low-pass, high-pass, or any other desired frequency shaping. The
programmable coefficients for the mixer operation are located in the Programmable Coefficient Registers: Page
2 and Programmable Coefficient Registers: Page 3 sections. If biquad filtering is required, then the host device
must write these coefficients values before powering up any ADC channels for recording. These programmable
coefficients are 32-bit, two’s complement numbers. As described in 表 8-16, these biquad filters can be
allocated for each output channel based on the BIQUAD_CFG[1:0] register setting of P0_R108. By setting
BIQUAD_CFG[1:0] to 2'b00, the biquad filtering for all record channels is disabled and the host device can
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choose this setting if no additional filtering is required for the system application. See the PCM6xx0-Q1
Programmable Biquad Filter Configuration and Applications application report for further details.
表8-16. Biquad Filter Allocation to the Record Output Channel
RECORD OUTPUT CHANNEL ALLOCATION USING P0_R108_D[6:5] REGISTER SETTING
BIQUAD_CFG[1:0] = 2'b01
(1 Biquad per Channel)
BIQUAD_CFG[1:0] = 2'b10 (Default)
(2 Biquads per Channel)
BIQUAD_CFG[1:0] = 2'b11
(3 Biquads per Channel)
PROGRAMMABLE
BIQUAD FILTER
SUPPORTS ALL 8 CHANNELS
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Not used
SUPPORTS UP TO 6 CHANNELS
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 5
Allocated to output channel 6
Allocated to output channel 5
Allocated to output channel 6
SUPPORTS UP TO 4 CHANNELS
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Biquad filter 1
Biquad filter 2
Biquad filter 3
Biquad filter 4
Biquad filter 5
Biquad filter 6
Biquad filter 7
Biquad filter 8
Biquad filter 9
Biquad filter 10
Biquad filter 11
Biquad filter 12
Not used
Not used
Not used
Allocated to output channel 5
Allocated to output channel 6
Not used
Not used
表8-17 shows the biquad filter coefficients mapping to the register space.
表8-17. Biquad Filter Coefficients Register Mapping
PROGRAMMABLE BIQUAD BIQUAD FILTER COEFFICIENTS PROGRAMMABLE BIQUAD BIQUAD FILTER COEFFICIENTS
FILTER
REGISTER MAPPING
FILTER
REGISTER MAPPING
Biquad filter 1
Biquad filter 2
Biquad filter 3
Biquad filter 4
Biquad filter 5
Biquad filter 6
P2_R8-R27
Biquad filter 7
Biquad filter 8
Biquad filter 9
Biquad filter 10
Biquad filter 11
Biquad filter 12
P3_R8-R27
P2_R28-R47
P3_R28-R47
P2_R48-R67
P3_R48-R67
P2_R68-R87
P3_R68-R87
P2_R88-R107
P2_R108-R127
P3_R88-R107
P3_R108-R127
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8.3.8.6 Programmable Channel Summer and Digital Mixer
For applications that require an even higher SNR than that supported for each channel, the device digital
summing mode can be used. In this mode, the digital record data are summed up across the channel with an
equal weightage factor, which helps in reducing the effective record noise. 表8-18 lists the configuration settings
available for channel summing mode.
表8-18. Channel Summing Mode Programmable Settings
SNR AND DYNAMIC RANGE
P0_R107_D[3:2] : CH_SUM[2:0]
CHANNEL SUMMING MODE FOR INPUT CHANNELS
Channel summing mode is disabled
BOOST
00 (Default)
Not applicable
Output channel 1 = (input channel 1 + input channel 2) / 2
Output channel 2 = (input channel 1 + input channel 2) / 2
Output channel 3 = (input channel 3 + input channel 4) / 2
Output channel 4 = (input channel 3 + input channel 4) / 2
3-dB boost in SNR and dynamic
range
01
3-dB boost in SNR and dynamic
range
Output channel 1 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
Output channel 2 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
6-dB boost in SNR and dynamic
range
10
11
Output channel 3 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
Output channel 4 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
Reserved (do not use this setting)
Not applicable
The device additionally supports a fully programmable mixer feature that can mix the various input channels with
their custom programmable scale factor to generate the final output channels. The programmable mixer feature
is available only if CH_SUM[2:0] is set to 2'b00. The mixer function is only supported for input channel 1 to
channel 4. 图 8-24 shows a block diagram that describes the mixer 1 operation to generate output channel 1.
The programmable coefficients for the mixer operation are located in the Programmable Coefficient Registers:
Page 4 section. All mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format. The
value of 0x7FFFFFFF is equivalent to +1 (0-dB gain), the value 0x00000000 is equivalent to mute (zero data),
and any values in between set the mixer attenuation computed using 方程式 3. If the MSB is set to '1' then the
attenuation remains the same but the signal phase is inverted.
hex2dec (value) / 231
(3)
Attenuated by
MIX1_CH1
factor
Input Channel-1
Processed Data
Attenuated by
MIX1_CH2
factor
Input Channel-2
Processed Data
Output Channel-1
Routed to Bi-Quad
Filter
+
Attenuated by
MIX1_CH3
factor
Input Channel-3
Processed Data
Attenuated by
MIX1_CH4
factor
Input Channel-4
Processed Data
图8-24. Programmable Digital Mixer Block Diagram
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A similar mixer operation is performed by mixer 2, mixer 3, and mixer 4 to generate output channel 2, channel 3,
and channel 4, respectively.
8.3.8.7 Configurable Digital Decimation Filters
The device record channel includes a high dynamic range, built-in digital decimation filter to process the
oversampled data from the multibit delta-sigma (ΔΣ) modulator to generate digital data at the same Nyquist
sampling rate as the FSYNC rate. The decimation filter can be chosen from three different types, depending on
the required frequency response, group delay, and phase linearity requirements for the target application. The
selection of the decimation filter option can be done by configuring the DECI_FILT, P0_R107_D[5:4] register bits.
表8-19 shows the configuration register setting for the decimation filter mode selection for the record channel.
表8-19. Decimation Filter Mode Selection for the Record Channel
P0_R107_D[5:4] : DECI_FILT[1:0]
DECIMATION FILTER MODE SELECTION
00 (default)
Linear phase filters are used for the decimation
01
10
11
Low-latency filters are used for the decimation
Ultra-low latency filters are used for the decimation
Reserved (do not use this setting)
8.3.8.7.1 Linear Phase Filters
The linear phase decimation filters are the default filters set by the device and can be used for all applications
that require a perfect linear phase with zero-phase deviation within the pass-band specification of the filter. The
filter performance specifications and various plots for all supported output sampling rates are listed in this
section.
8.3.8.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
图 8-25 and 图 8-26 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 8 kHz or 7.35 kHz. 表8-20 lists the specifications for a decimation filter with an
8-kHz or 7.35-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-25. Linear Phase Decimation Filter Magnitude 图8-26. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-20. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
72.7
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
81.2
17.1
1/fS
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8.3.8.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
图 8-27 and 图 8-28 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 16 kHz or 14.7 kHz. 表 8-21 lists the specifications for a decimation filter with an 16-kHz
or 14.7-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-27. Linear Phase Decimation Filter Magnitude 图8-28. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-21. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.3
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
95.0
15.7
1/fS
8.3.8.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
图 8-29 and 图 8-30 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 24 kHz or 22.05 kHz. 表8-22 lists the specifications for a decimation filter with an 24-kHz
or 22.05-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-29. Linear Phase Decimation Filter Magnitude 图8-30. Linear Phase Decimation Filter Pass-Band
Response
Ripple
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表8-22. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
MIN
–0.05
73.0
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
96.4
16.6
1/fS
8.3.8.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
图 8-31 and 图 8-32 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 32 kHz or 29.4 kHz. 表 8-23 lists the specifications for a decimation filter with an 32-kHz
or 29.4-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-31. Linear Phase Decimation Filter Magnitude 图8-32. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-23. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.7
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
107.2
16.9
1/fS
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8.3.8.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
图 8-33 and 图 8-34 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 48 kHz or 44.1 kHz. 表 8-24 lists the specifications for a decimation filter with an 48-kHz
or 44.1-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-33. Linear Phase Decimation Filter Magnitude 图8-34. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-24. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.8
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
98.1
17.1
1/fS
8.3.8.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
图 8-35 and 图 8-36 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 96 kHz or 88.2 kHz. 表 8-25 lists the specifications for a decimation filter with an 96-kHz
or 88.2-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-35. Linear Phase Decimation Filter Magnitude 图8-36. Linear Phase Decimation Filter Pass-Band
Response
Ripple
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表8-25. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
MIN
–0.05
73.6
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
97.9
17.1
1/fS
8.3.8.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
图 8-37 and 图 8-38 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 192 kHz or 176.4 kHz. 表 8-26 lists the specifications for a decimation filter with an 192-
kHz or 176.4-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
0.15
0.2
0.25
Normalized Frequency (1/fS)
0.3
0.35
0.4
D001
D001
图8-37. Linear Phase Decimation Filter Magnitude
图8-38. Linear Phase Decimation Filter Pass-Band
Response
Ripple
表8-26. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.3 × fS
Frequency range is 0.473 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.3 × fS
0.05
dB
–0.05
70.0
Stop-band attenuation
Group delay or latency
dB
111.0
11.9
1/fS
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8.3.8.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
图 8-39 and 图 8-40 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 384 kHz or 352.8 kHz. 表 8-27 lists the specifications for a decimation filter with an 384-
kHz or 352.8-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
0.15
Normalized Frequency (1/fS)
0.2
0.25
0.3
D001
D001
图8-39. Linear Phase Decimation Filter Magnitude 图8-40. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-27. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
70.0
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.212 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.212 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
108.8
7.2
1/fS
8.3.8.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
图 8-41 and 图 8-42 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 768 kHz or 705.6 kHz. 表 8-28 lists the specifications for a decimation filter with an 768-
kHz or 705.6-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
Normalized Frequency (1/fS)
0.15
0.2
D001
D001
图8-41. Linear Phase Decimation Filter Magnitude 图8-42. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-28. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
75.0
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.113 × fS
Frequency range is 0.58 × fS to 2 × fS
Frequency range is 2 × fS onwards
0.05
dB
Stop-band attenuation
dB
88.0
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表8-28. Linear Phase Decimation Filter Specifications (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Group Delay or Latency Frequency range is 0 to 0.113 × fS
5.9
1/fS
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8.3.8.7.2 Low-Latency Filters
For applications where low latency with minimal phase deviation (within the audio band) is critical, the low-
latency decimation filters on the PCM6480-Q1 can be used. The device supports these filters with a group delay
of approximately seven samples with an almost linear phase response within the 0.365 × fS frequency band.
This section provides the filter performance specifications and various plots for all supported output sampling
rates for the low-latency filters.
8.3.8.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
图 8-43 shows the magnitude response and 图 8-44 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 16 kHz or 14.7 kHz. 表 8-29 lists the specifications for a decimation filter
with a 16-kHz or 14.7-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-44. Low-Latency Decimation Filter Pass-Band
图8-43. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
表8-29. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.451 × fS
Frequency range is 0.61 × fS onwards
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
0.05
–0.05
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
87.3
dB
7.6
1/fS
0.022
0.25
1/fS
–0.022
–0.21
Degrees
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8.3.8.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
图 8-45 shows the magnitude response and 图 8-46 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 24 kHz or 22.05 kHz. 表 8-30 lists the specifications for a decimation
filter with a 24-kHz or 22.05-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-46. Low-Latency Decimation Filter Pass-Band
图8-45. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
表8-30. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.459 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
0.01
–0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
87.2
dB
7.5
1/fS
0.026
0.30
1/fS
–0.026
–0.26
Degrees
8.3.8.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
图 8-47 shows the magnitude response and 图 8-48 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 32 kHz or 29.4 kHz. 表 8-31 lists the specifications for a decimation filter
with a 32-kHz or 29.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-48. Low-Latency Decimation Filter Pass-Band
图8-47. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
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表8-31. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.04
88.3
TYP
MAX
UNIT
dB
Pass-band ripple
Frequency range is 0 to 0.457 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
8.7
1/fS
0.026
0.31
1/fS
–0.026
–0.26
Degrees
8.3.8.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
图 8-49 shows the magnitude response and 图 8-50 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 48 kHz or 44.1 kHz. 表 8-32 lists the specifications for a decimation filter
with a 48-kHz or 44.1-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-50. Low-Latency Decimation Filter Pass-Band
图8-49. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
表8-32. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.452 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
0.015
–0.015
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
86.4
dB
7.7
1/fS
0.027
0.30
1/fS
–0.027
–0.25
Degrees
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8.3.8.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
图 8-51 shows the magnitude response and 图 8-52 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 96 kHz or 88.2 kHz. 表 8-33 lists the specifications for a decimation filter
with a 96-kHz or 88.2-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-52. Low-Latency Decimation Filter Pass-Band
图8-51. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
表8-33. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.466 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
0.04
–0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
86.3
dB
7.7
1/fS
0.027
0.30
1/fS
–0.027
–0.26
Degrees
8.3.8.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
图 8-53 shows the magnitude response and 图 8-54 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 192 kHz or 176.4 kHz. 表 8-34 lists the specifications for a decimation
filter with a 192-kHz or 176.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-54. Low-Latency Decimation Filter Pass-Band
图8-53. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
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表8-34. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 463 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
MIN
–0.03
85.6
TYP
MAX
UNIT
dB
Pass-band ripple
0.03
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.7
1/fS
0.027
0.30
1/fS
–0.027
–0.26
Degrees
8.3.8.7.3 Ultra-Low-Latency Filters
For applications where ultra-low latency (within the audio band) is critical, the ultra-low-latency decimation filters
on the PCM6480-Q1 can be used. The device supports these filters with a group delay of approximately four
samples with an almost linear phase response within the 0.325 × fS frequency band. This section provides the
filter performance specifications and various plots for all supported output sampling rates for the ultra-low-latency
filters.
8.3.8.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
图 8-55 shows the magnitude response and 图 8-56 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 16 kHz or 14.7 kHz. 表 8-35 lists the specifications for a decimation filter
with a 16-kHz or 14.7-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-56. Ultra-Low-Latency Decimation Filter Pass-
图8-55. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-35. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.45 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.05
–0.05
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
87.2
dB
4.3
1/fS
0.512
14.2
1/fS
–0.512
–10.0
Degrees
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8.3.8.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
图 8-57 shows the magnitude response and 图 8-58 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 24 kHz or 22.05 kHz. 表 8-36 lists the specifications for a decimation
filter with a 24-kHz or 22.05-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-58. Ultra-Low-Latency Decimation Filter Pass-
图8-57. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-36. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.46 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.01
–0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
87.1
dB
4.1
1/fS
0.514
14.3
1/fS
–0.514
–10.0
Degrees
8.3.8.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
图 8-59 shows the magnitude response and 图 8-60 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 32 kHz or 29.4 kHz. 表 8-37 lists the specifications for a decimation filter
with an 32-kHz or 29.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-60. Ultra-Low-Latency Decimation Filter Pass-
图8-59. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
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表8-37. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.04
88.3
TYP
MAX
UNIT
dB
Pass-band ripple
Frequency range is 0 to 0.457 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
5.2
1/fS
0.492
13.5
1/fS
–0.492
–9.5
Degrees
8.3.8.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
图 8-61 shows the magnitude response and 图 8-62 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 48 kHz or 44.1 kHz. 表 8-38 lists the specifications for a decimation filter
with a 48-kHz or 44.1-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-62. Ultra-Low-Latency Decimation Filter Pass-
图8-61. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-38. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.452 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.015
–0.015
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
86.4
dB
4.1
1/fS
0.525
14.5
1/fS
–0.525
–10.3
Degrees
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8.3.8.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
图 8-63 shows the magnitude response and 图 8-64 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 96 kHz or 88.2 kHz. 表 8-39 lists the specifications for a decimation filter
with a 96-kHz or 88.2-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
5
10
0
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
3
2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-4
-5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-64. Ultra-Low-Latency Decimation Filter Pass-
图8-63. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-39. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.466 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.1625 × fS
Frequency range is 0 to 0.1625 × fS
Frequency range is 0 to 0.1625 × fS
0.04
–0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
86.3
dB
3.7
1/fS
0.091
1.30
1/fS
–0.091
–0.86
Degrees
8.3.8.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
图 8-65 shows the magnitude response and 图 8-66 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 192 kHz or 176.4 kHz. 表 8-40 lists the specifications for a decimation
filter with a 192-kHz or 176.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
5
10
0
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
3
2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-4
-5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-66. Ultra-Low-Latency Decimation Filter Pass-
图8-65. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
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表8-40. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.463 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.085 × fS
Frequency range is 0 to 0.085 × fS
Frequency range is 0 to 0.085 × fS
MIN
–0.03
85.6
TYP
MAX
UNIT
dB
Pass-band ripple
0.03
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
3.7
1/fS
0.024
0.18
1/fS
–0.024
–0.12
Degrees
8.3.8.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
图 8-67 shows the magnitude response and 图 8-68 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 384 kHz or 352.8 kHz. 表 8-41 lists the specifications for a decimation
filter with a 384-kHz or 352.8-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
2
10
0
1.6
1.2
0.8
0.4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.4
-0.8
-1.2
-1.6
-2
Pass-Band Ripple
Phase Deviation
0
0.05
0.1 0.15
Normalized Frequency (1/fS)
0.2
0.25
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-68. Ultra-Low-Latency Decimation Filter Pass-
图8-67. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-41. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.1 × fS
Frequency range is 0.56 × fS onwards
Frequency range is 0 to 0.157 × fS
Frequency range is 0 to 0.157 × fS
Frequency range is 0 to 0.157 × fS
0.01
–0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
70.1
dB
4.1
1/fS
0.18
2.07
1/fS
–0.18
–0.85
Degrees
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8.3.9 Automatic Gain Controller (AGC)
The device includes an automatic gain controller (AGC) for ADC recording that must be used only for the AC-
coupled input configuration. As shown in 图 8-69, the AGC can be used to maintain a nominally constant output
level when recording speech. Instead of manually setting the channel gain in AGC mode, the circuitry
automatically adjusts the channel gain when the input signal becomes overly loud or very weak, such as when a
person speaking into a microphone moves closer to or farther from the microphone. The AGC algorithm has
several programmable parameters, including target level, maximum gain allowed, attack and release (or decay)
time constants, and noise thresholds that allow the algorithm to be fine-tuned for any particular application.
Input
Signal
Output
Signal
Target
Level
AGC
Gain
Decay Time
Attack
Time
图8-69. AGC Characteristics
The target level (AGC_LVL) represents the nominal output level at which the AGC attempts to hold the ADC
output signal level. The PCM6480-Q1 allows programming of different target levels, which can be programmed
from –6 dB to –36 dB relative to a full-scale signal, and the AGC_LVL default value is set to –34 dB. The
target level is recommended to be set with enough margin to prevent clipping when loud sounds occur. 表 8-42
lists the AGC target level configuration settings.
表8-42. AGC Target Level Programmable Settings
P0_R112_D[7:4] : AGC_LVL[3:0]
AGC TARGET LEVEL FOR OUTPUT
0000
0001
0010
The AGC target level is the –6-dB output signal level
The AGC target level is the –8-dB output signal level
The AGC target level is the –10-dB output signal level
…
…
1110 (default)
The AGC target level is the –34-dB output signal level
The AGC target level is the –36-dB output signal level
1111
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The maximum gain allowed (AGC_MAXGAIN) gives flexibility to the designer to restrict the maximum gain
applied by the AGC. This feature limits the channel gain in situations where environmental noise is greater than
the programmed noise threshold. The AGC_MAXGAIN can be programmed from 3 dB to 42 dB with steps of 3
dB and the default value is set to 24 dB. 表8-43 lists the AGC_MAXGAIN configuration settings.
表8-43. AGC Maximum Gain Programmable Settings
P0_R112_D[3:0] :
AGC MAXIMUM GAIN ALLOWED
AGC_MAXGAIN[3:0]
0000
0001
0010
The AGC maximum gain allowed is 3 dB
The AGC maximum gain allowed is 6 dB
The AGC maximum gain allowed is 9 dB
…
…
0111 (default)
The AGC maximum gain allowed is 24 dB
…
…
1110
1111
The AGC maximum gain allowed is 39 dB
The AGC maximum gain allowed is 42 dB
For further details on the AGC various configurable parameter and application use, see the Using the Automatic
Gain Controller in PCM6xx0-Q1 application report.
8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
Certain events in the device may require host processor intervention and can be used to trigger interrupts to the
host processor. Such event are an audio serial interface (ASI) bus error and input DC fault diagnostic faults. The
device powers down the record channels if any faults are detected with the ASI bus error clocks, such as:
• Invalid FSYNC frequency
• Invalid SBCLK to FSYNC ratio
• Long pauses of the SBCLK or FSYNC clocks
When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After
all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record
channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the
clock error interrupt mask register bit INT_MASK0[7], P0_R51_D7 is set low. The clock fault is also available for
readback in the live fault status register bit INT_LIVE0, P1_R44 and is also latched to the fault status register bit
INT_LTCH0, P0_R44, which is a read-only register. Reading the latched fault status register, INT_LTCH0, clears
all latched fault statuses. The device can be additionally configured to route the internal IRQ interrupt signal on
the GPIOx pins and also can be configured as an open-drain output so that these pins can be wire-ANDed to the
open-drain interrupt outputs of other devices.
When an input DC fault event is detected, the internal IRQ signal is asserted if the interrupt mask registers
INT_MASK1, P0_R42 and INT_MASK2, P0_R43 are configured appropriately to unmask all desired fault
diagnostics interrupts. Each input channel can be independently set for an interrupt mask. 表 8-44 and 表 8-45
list the mask settings available for the input DC diagnostics fault interrupts.
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表8-44. Interrupt Mask Register 1 for DC Faults Diagnostic
P0_R42 : INT_MASK1
INT_MASK1[7]
INT_MASK1[6]
INT_MASK1[5]
INT_MASK1[4]
INT_MASK1[3]
INT_MASK1[2]
INTERRUPT MASK REGISTER 1 FOR DC FAULTS DIAGNOSTIC INTERRUPTS
Channel 1 input DC faults diagnostic interrupt mask and unmask register bit
Channel 2 input DC faults diagnostic interrupt mask and unmask register bit
Channel 3 input DC faults diagnostic interrupt mask and unmask register bit
Channel 4 input DC faults diagnostic interrupt mask and unmask register bit
Channel 5 input DC faults diagnostic interrupt mask and unmask register bit
Channel 6 input DC faults diagnostic interrupt mask and unmask register bit
Short to VBAT_IN (when VBAT_IN is lower than MICBIAS) fault interrupt mask and unmask register
bit
INT_MASK1[1]
INT_MASK1[0]
Reserved
表8-45. Interrupt Mask Register 2 for DC Faults Diagnostic
INTERRUPT MASK REGISTER 2 FOR DC FAULTS DIAGNOSTIC INTERRUPTS
Open input fault interrupt mask and unmask register bit for all channels
P0_R43 : INT_MASK2
INT_MASK2[7]
INT_MASK2[6]
INT_MASK2[5]
INT_MASK2[4]
INT_MASK2[3]
INT_MASK2[2]
INT_MASK2[1]
INT_MASK2[0]
Inputs shorted together fault interrupt mask and unmask register bit for all channels
INxP input shorted to ground fault interrupt mask and unmask register bit for all channels
INxM input shorted to ground fault interrupt mask and unmask register bit for all channels
INxP input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels
INxM input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels
INxP input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels
INxM input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels
The device supports the channel-specific input DC fault latched status registers for all channels from
CH1_LTCH, P0_R46 to CH6_LTCH, P0_R51, which are read-only registers. The device also has a consolidated
summary status register across channels for the input DC latched fault status register, CHx_LTCH, P0_R45 that
the host can read to quickly know which channel fault has occurred. Reading the latched fault status registers,
CH1_LTCH to CH6_LTCH, clears all the latched fault status including the summary status register, CHx_LTCH.
表8-46 shows various input DC fault diagnostics status bits that are supported by the device.
表8-46. Input DC Faults Diagnostic Latched Status
P0_R46 : CH1_LTCH
CH1_LTCH[7]
CH1_LTCH[6]
CH1_LTCH[5]
CH1_LTCH[4]
CH1_LTCH[3]
CH1_LTCH[2]
CH1_LTCH[1]
CH1_LTCH[0]
CHANNEL 1 INPUT FAULTS DIAGNOSTIC LATCHED STATUS
Channel 1 open input fault detection status bit (self-clearing bit)
Channel 1 inputs shorted together fault detection status bit (self-clearing bit)
Channel 1 IN1P input shorted to ground fault detection status bit (self-clearing bit)
Channel 1 IN1M input shorted to ground fault detection status bit (self-clearing bit)
Channel 1 IN1P input shorted to MICBIAS fault detection status bit (self-clearing bit)
Channel 1 IN1M input shorted to MICBIAS fault detection status bit (self-clearing bit)
Channel 1 IN1P input shorted to VBAT_IN fault detection status bit (self-clearing bit)
Channel 1 IN1M input shorted to VBAT_IN fault detection status bit (self-clearing bit)
Similarly, the DC faults diagnostic latched status for input channel 2 to channel 6 can be monitored using the
CH2_LTCH (P0_R47) to CH6_LTCH (P0_R51) registers, respectively.
The device GPIOx pins can be additionally configured to route the internal IRQ interrupt signal on the GPIOx
pins and also can be configured as an open-drain output so that this pin can be wire-ANDed to the open-drain
interrupt outputs of other devices.
The IRQ interrupt signal can either be configured as an active low or active high polarity by setting the INT_POL,
P0_R40_D7 register bit. This signal can also be configured as a single pulse or a series of pulses by
programming the INT_EVENT[1:0], P0_R40_D[6:5] register bits. If the interrupts are configured as a series of
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pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine
the cause of the interrupt.
The device also supports read-only live status registers that determine if all the channels are powered up or
down and if the device is in sleep mode or not. These status registers are located in P0_R118, DEV_STS0 and
P0_R119, DEV_STS1.
The device has a GPIO1 multifunction pin that can be configured for a desired specific function. Additionally, the
PCM6480-Q1 has two more GPIO pins and two GPI pins supported that can be used in the system for the PDM
microphone interface or for various other features. 表 8-47 shows all possible allocation of these multifunction
pins for all the various features.
表8-47. Multifunction Pin Assignments
ROW
PIN FUNCTION
GPIO1
GPIO2
GPIO3
GPI1
GPI2
GPIO1_CFG
[4:0]
GPIO2_CFG
[4:0]
GPIO3_CFG
[4:0]
GPI1_CFG[4:0] GPI2_CFG[4:0]
—
—
P0_R33[7:4]
P0_R34[7:4]
P0_R35[7:4]
P0_R36[7:4]
P0_R37[7:4]
—
A
B
C
D
F
—
Pin disabled
S(1)
S (default)
S (default)
S (default)
S (default)
General-purpose output (GPO)
Interrupt output (IRQ)
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
NS(2)
NS
NS
S
NS
NS
NS
S
S (default)
Secondary ASI output (SDOUT2)
MiCBIAS on/off input (BIASEN)
General-purpose input (GPI)
Master clock input (MCLK)
ASI daisy-chain input (SDIN)
S
S
S
S
S
G
H
I
S
S
S
S
S
S
(1) S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
(2) NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
Each GPIOx pin can be independently set for the desired drive configurations setting using the GPIOx_DRV[3:0]
register bits. 表8-48 lists the drive configuration settings.
表8-48. GPIOx Pins Drive Configuration Settings
P0_R33_D[3:0] : GPIO1_DRV[3:0]
GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1
000
001
The GPIO1 pin is set to high impedance (floated)
The GPIO1 pin is set to be driven active low or active high
The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)
The GPIO1 pin is set to be driven active low or Hi-Z (floated)
The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high
The GPIO1 pin is set to be driven Hi-Z (floated) or active high
Reserved (do not use these settings)
010 (default)
011
100
101
110 and 111
Similarly, the GPIO2 and GPIO3 pins can be configured using the GPIO2_DRV(P0_R34) and
GPIO3_DRV(P0_R35) register bits, respectively.
When configured as a general-purpose output (GPO), the GPIOx pin values can be driven by writing the
GPIO_VAL P0_R38 registers. The GPIO_MON, P0_R39 register can be used to readback the status of the
GPIOx and GPIx pins when configured as a general-purpose input (GPI).
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8.4 Device Functional Modes
8.4.1 Hardware Shutdown
The device enters hardware shutdown mode when the SHDNZ pin is asserted low or the AVDD supply voltage is
not applied to the device. In hardware shutdown mode, the device consumes the minimum quiescent current
from the AVDD supply. All configuration registers and programmable coefficients lose their value in this mode,
and I2C or SPI communication to the device is not supported.
If the SHDNZ pin is asserted low when the device is in active mode, the device ramps down volume on the
record data, powers down the analog and digital blocks, and puts the device into hardware shutdown mode in 25
ms (typical). The device can also be immediately put into hardware shutdown mode from active mode if the
SHDNZ_CFG[1:0], P0_R5_D[3:2], register bits are set to 2'b00. After the SHDNZ pin is asserted low, and after
the device enters hardware shutdown mode, keep the SHDNZ pin low for at least 1 ms before releasing SHDNZ
for further device operation.
Assert the SHDNZ pin high only when the IOVDD supply settles to a steady voltage level. When the SHDNZ pin
goes high, the device sets all configuration registers and programmable coefficients to their default values, and
then enters sleep mode.
8.4.2 Sleep Mode or Software Shutdown
In sleep mode or software shutdown mode, the device consumes very low quiescent current from the AVDD
supply and, at the same time, allows the I2C or SPI communication to wake the device for active operation.
The device can also enter sleep mode when the host device sets the SLEEP_ENZ, P0_R2_D0 bit to 1'b0. If the
SLEEP_ENZ bit is asserted low when the device is in active mode, the device ramps down the volume on the
record data, powers down the analog and digital blocks, and enters sleep mode. However, the device still
continues to retain the last programmed value of the device configuration registers and programmable
coefficients.
In sleep mode, do not perform any I2C or SPI transactions, except for exiting sleep mode in order to enter active
mode. After entering sleep mode, wait at least 10 ms before starting I2C or SPI transactions to exit sleep mode.
8.4.3 Active Mode
If the host device exits sleep mode by setting the SLEEP_ENZ bit to 1'b1, the device enters active mode. In
active mode, I2C or SPI transactions can be done to configure and power-up the device for active operation.
After entering active mode, wait at least 1 ms before starting any I2C or SPI transactions in order to allow the
device to complete the internal wake-up sequence.
After configuring all other registers for the target application and system settings, configure the input and output
channel enable registers, P0_R115 (IN_CH_EN) and P0_R116 (ASI_OUT_CH_EN), respectively. Lastly,
configure the device power-up register, P0_R117 (PWR_CFG). All programmable coefficient values must be
written before powering up the respective channel.
In active mode, the power-up and power-down status of various blocks is monitored by reading the read-only
device status bits located in the P0_R117 (DEV_STS0) and P0_R118 (DEV_STS1) registers.
8.4.4 Software Reset
A software reset can be done any time by asserting the SW_RESET bit, P0_R1_D0, which is a self-clearing bit.
This software reset immediately shuts down the device, and restores all device configuration registers and
programmable coefficients to their default values.
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8.5 Programming
The device contains configuration registers and programmable coefficients that can be set to the desired values
for a specific system and application use. These registers are called device control registers and are each eight
bits in width, mapped using a page scheme.
Each page contains 128 configuration registers. All device configuration registers are stored in page 0, which is
the default page setting at power up (and after a software reset). Page 1 consists of the live status registers and
input diagnostic successive-approximation register (SAR) data for advanced diagnostic purposes. All
programmable coefficient registers are located in page 2, page 3, and page 4. The current page of the device
can be switched to a new desired page by using the PAGE[7:0] bits located in register 0 of every page.
8.5.1 Control Serial Interfaces
The device control registers can be accessed using either I2C or SPI communication to the device.
By monitoring the SDA_SSZ, SCL_MOSI, ADDR0_SCLK, and ADDR1_MISO device pins, which are the
multiplexed pins for the I2C or SPI Interface, the device automatically detects whether the host device is using
I2C or SPI communication to configure the device. For a given end application, the host device must always use
either the I2C or SPI interface, but not both, to configure the device.
8.5.1.1 I2C Control Interface
The device supports the I2C control protocol as a slave device and is capable of operating in standard mode,
fast mode, and fast mode plus. The I2C control protocol requires a 7-bit slave address. The five most significant
bits (MSBs) of the slave address are fixed at 10010 and cannot be changed. The two least significant bits (LSBs)
are programmable and are controlled by the ADDR0_SCLK and ADDR1_MISO pins. These two pins must
always be either pulled to VSS or IOVDD. If the I2C_BRDCAST_EN (P0_R2_D2) bit is set to 1'b1, then the I2C
slave address is fixed to 1001000 in order to allow simultaneous I2C broadcast communication to all PCM6480-
Q1 devices in the system. 表8-49 lists the four possible device addresses resulting from this configuration.
表8-49. I2C Slave Address Settings
ADDR1_MISO
ADDR0_SCLK
I2C_BRDCAST_EN (P0_R2_D2)
I2C SLAVE ADDRESS
1001 000
0
0
1
1
X
0
1
0
1
X
0 (default)
0 (default)
0 (default)
0 (default)
1
1001 001
1001 010
1001 011
1001 000
8.5.1.1.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between the integrated circuits
in a system using serial data transmission. The address and data 8-bit bytes are transferred MSB first. In
addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit.
Each transfer operation begins with the master device driving a START condition on the bus and ends with the
master device driving a STOP condition on the bus. The bus uses transitions on the data pin (SDA) when the
clock is at logic high to indicate START and STOP conditions. A high-to-low transition on SDA indicates a
START, and a low-to-high transition indicates a STOP condition. Normal data-bit transitions must occur within the
low time of the clock period.
The master device drives a START condition followed by the 7-bit slave address and the read/write (R/W) bit to
open communication with another device and then waits for an acknowledgment condition. The slave device
holds SDA low during the acknowledge clock period to indicate acknowledgment. When this step occurs, the
master device transmits the next byte of the sequence. Each slave device is addressed by a unique 7-bit slave
address plus the R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a
wired-AND connection.
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There is no limit on the number of bytes that can be transmitted between START and STOP conditions. When
the last word transfers, the master device generates a STOP condition to release the bus. 图 8-70 shows a
generic data transfer sequence.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
图8-70. Typical I2C Sequence
In the system, use external pullup resistors for the SDA and SCL signals to set the logic high level for the bus.
The SDA and SCL voltages must not exceed the device supply voltage, IOVDD.
8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
The device I2C interface supports both single-byte and multiple-byte read/write operations for all registers.
During multiple-byte read operations, the device responds with data, a byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledges.
The device supports sequential I2C addressing. For write transactions, if a register is issued followed by data for
that register and all the remaining registers that follow, a sequential I2C write transaction takes place. For I2C
sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a STOP or START condition is transmitted, determines how many registers are
written.
8.5.1.1.2.1 I2C Single-Byte Write
As shown in 图 8-71, a single-byte data write transfer begins with the master device transmitting a START
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C
slave address and the read/write bit, the device responds with an acknowledge bit (ACK). Next, the master
device transmits the register byte corresponding to the device internal register address being accessed. After
receiving the register byte, the device again responds with an acknowledge bit (ACK). Then, the master
transmits the byte of data to be written to the specified register. When finished, the slave device responds with
an acknowledge bit (ACK). Finally, the master device transmits a STOP condition to complete the single-byte
data write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5 A4
A3 A2 A1 A0
Stop
2
I C Device Address and
Read/Write Bit
Register
Data Byte
Condition
图8-71. I2C Single-Byte Write Transfer
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8.5.1.1.2.2 I2C Multiple-Byte Write
As shown in 图8-72, a multiple-byte data write transfer is identical to a single-byte data write transfer except that
multiple data bytes are transmitted by the master device to the slave device. After receiving each data byte, the
device responds with an acknowledge bit (ACK). Finally, the master device transmits a STOP condition after the
last data-byte write transfer.
Register
图8-72. I2C Multiple-Byte Write Transfer
8.5.1.1.2.3 I2C Single-Byte Read
As shown in 图 8-73, a single-byte data read transfer begins with the master device transmitting a START
condition followed by the I2C slave address and the read/write bit. For the data read transfer, both a write
followed by a read are done. Initially, a write is done to transfer the address byte of the internal register address
to be read. As a result, the read/write bit is set to 0.
After receiving the slave address and the read/write bit, the device responds with an acknowledge bit (ACK). The
master device then sends the internal register address byte, after which the device issues an acknowledge bit
(ACK). The master device transmits another START condition followed by the slave address and the read/write
bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the device transmits the data
byte from the register address being read. After receiving the data byte, the master device transmits a not-
acknowledge (NACK) followed by a STOP condition to complete the single-byte data read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
2
2
Stop
Condition
I C Device Address and
Read/Write Bit
Register
I C Device Address and
Read/Write Bit
Data Byte
图8-73. I2C Single-Byte Read Transfer
8.5.1.1.2.4 I2C Multiple-Byte Read
As shown in 图 8-74, a multiple-byte data read transfer is identical to a single-byte data read transfer except that
multiple data bytes are transmitted by the device to the master device. With the exception of the last data byte,
the master device responds with an acknowledge bit after receiving each data byte. After receiving the last data
byte, the master device transmits a not-acknowledge (NACK) followed by a STOP condition to complete the data
read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
2
2
Register
Stop
Condition
I C Device Address and
Read/Write Bit
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
图8-74. I2C Multiple-Byte Read Transfer
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8.5.1.2 SPI Control Interface
The general SPI protocol allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions by taking the slave-select pin SSZ from high
to low. The SPI slave devices (such as the PCM6480-Q1) depend on a master to start and synchronize
transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins
shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). When the byte
shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.
The PCM6480-Q1 support a standard SPI control protocol with a clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0) and a clock phase setting of 1 (typical microprocessor SPI control bit
CPHA = 1). The SSZ pin can remain low between transmissions; however, the device only interprets the first
eight bits transmitted after the falling edge of SSZ as a command byte, and the next eight bits as a data byte
only if writing to a register. The device is entirely controlled by registers. Reading and writing these registers is
accomplished by an 8-bit command sent to the MOSI pin prior to the data for that register. 表 8-50 shows the
command structure. The first seven bits specify the address of the register that is being written or read, from 0 to
127 (decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the serial
bus.
In the case of a register write, set the R/W bit to 0. A second byte of data is sent to the MOSI pin and contains
the data to be written to the register. A register read is accomplished in a similar fashion. The 8-bit command
word sends the 7-bit register address, followed by the R/W bit equal to 1 to signify a register read. The 8-bit
register data is then clocked out of the device on the MISO pin during the second eight SCLK clocks in the
frame. The device supports sequential SPI addressing for a multiple-byte data write/read transfer until the SSZ
pin is pulled high. A multiple-byte data write or read transfer is identical to a single-byte data write or read
transfer, respectively, until all data byte transfers complete. The host device must keep the SSZ pin low during all
data byte transfers. 图 8-75 shows the single-byte write transfer and 图 8-76 illustrates the single-byte read
transfer.
表8-50. SPI Command Word
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDR(6)
ADDR(5)
ADDR(4)
ADDR(3)
ADDR(2)
ADDR(1)
ADDR(0)
R/WZ
SS
SCLK
MOSI
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
D(7)
D(6)
D(0)
7-bit Register Address
Write
8-bit Register Data
Hi-Z
Hi-Z
MISO
图8-75. SPI Single-Byte Write Transfer
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SS
SCLK
MOSI
Hi-Z
Hi-Z
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
Don’t Care
7-bit Register Address
Read
8-bit Register Data
MISO
D(7)
D(6)
D(0)
图8-76. SPI Single-Byte Read Transfer
8.6 Register Maps
This section describes the control registers for the device in detail. All registers are eight bits in width and are
allocated to the device configuration and programmable coefficients settings. These registers are mapped
internally using a page scheme that can be controlled using either I2C or SPI communication to the device. Each
page contains 128 bytes of registers. All device configuration registers are stored in page 0, which is the default
page setting at power up (and after a software reset). Page 1 consists of the live status registers and input
diagnostic SAR data for advanced diagnostic purposes. All programmable coefficient registers are located in
page 2, page 3, and page 4. The device current page can be switched to a new desired page by using the
PAGE[7:0] bits located in register 0 of every page.
Do not read from or write to reserved pages or reserved registers. Write only default values for the reserved bits
in the valid registers.
The procedure for register access across pages is:
• Select page N (write data N to register 0 regardless of the current page number)
• Read or write data from or to valid registers in page N
• Select the new page M (write data M to register 0 regardless of the current page number)
• Read or write data from or to valid registers in page M
• Repeat as needed
8.6.1 Device Configuration Registers
This section describes the device configuration registers for page 0 and page 1.
8.6.1.1 Registers Access Type
表8-51 lists the access codes used for the PCM6xx0-Q1 registers.
表8-51. PCM6xx0-Q1 Access Type Codes
ACCESS TYPE
CODE
DESCRIPTION
Read Type
R
R
Read
R-W
R/W
Read or write
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
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8.6.1.2 Page 0 Registers
表 8-52 lists the memory-mapped registers for the Page 0 registers. All register offset addresses not listed in 表
8-52 should be considered as reserved locations and the register contents should not be modified.
表8-52. PAGE 0 Registers
Address
0x0
Acronym
Register Name
Reset Value
0x00
0x00
0x00
0x05
0x30
0x00
0x00
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x02
0x48
0xFF
0x10
0x00
0x22
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Section
PAGE_CFG
SW_RESET
SLEEP_CFG
SHDN_CFG
ASI_CFG0
ASI_CFG1
ASI_CFG2
ASI_CH1
Device page register
节8.6.1.2.1
节8.6.1.2.2
节8.6.1.2.3
节8.6.1.2.4
节8.6.1.2.5
节8.6.1.2.6
节8.6.1.2.7
节8.6.1.2.8
节8.6.1.2.9
节8.6.1.2.10
节8.6.1.2.11
节8.6.1.2.12
节8.6.1.2.13
节8.6.1.2.14
节8.6.1.2.15
节8.6.1.2.16
节8.6.1.2.17
节8.6.1.2.18
节8.6.1.2.19
节8.6.1.2.20
节8.6.1.2.21
节8.6.1.2.22
节8.6.1.2.23
节8.6.1.2.24
节8.6.1.2.25
节8.6.1.2.26
节8.6.1.2.27
节8.6.1.2.28
节8.6.1.2.29
节8.6.1.2.30
节8.6.1.2.31
节8.6.1.2.32
节8.6.1.2.33
节8.6.1.2.34
节8.6.1.2.35
节8.6.1.2.36
节8.6.1.2.37
节8.6.1.2.38
节8.6.1.2.39
0x1
Software reset register
0x2
Sleep mode register
0x5
Shutdown configuration register
ASI configuration register 0
0x7
0x8
ASI configuration register 1
0x9
ASI configuration register 2
0xB
Channel 1 ASI slot configuration register
Channel 2 ASI slot configuration register
Channel 3 ASI slot configuration register
Channel 4 ASI slot configuration register
Channel 5 ASI slot configuration register
Channel 6 ASI slot configuration register
Channel 7 ASI slot configuration register
Channel 8 ASI slot configuration register
ASI master mode configuration register 0
ASI master mode configuration register 1
ASI bus clock monitor status register
Clock source configuration register
PDM DINx sampling edge register
GPIO configuration register 0
0xC
ASI_CH2
0xD
ASI_CH3
0xE
ASI_CH4
0xF
ASI_CH5
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x34
0x35
ASI_CH6
ASI_CH7
ASI_CH8
MST_CFG0
MST_CFG1
ASI_STS
CLK_SRC
PDMIN_CFG
GPIO_CFG0
GPIO_CFG1
GPIO_CFG2
GPI_CFG0
GPI_CFG1
GPIO_VAL
GPIO_MON
INT_CFG
GPIO configuration register 1
GPIO configuration register 2
GPI configuration register 0
GPI configuration register 1
GPIO output value register
GPIO monitor value register
Interrupt configuration register
INT_MASK0
INT_MASK1
INT_MASK2
INT_LTCH0
CHx_LTCH
CH1_LTCH
CH2_LTCH
CH3_LTCH
CH4_LTCH
INT_MASK3
INT_LTCH1
Interrupt mask register 0
Interrupt mask register 1
Interrupt mask register 2
Latched interrupt readback register 0
Channel diagnostic summary latched status register
Channel 1 diagnostic latched status register
Channel 2 diagnostic latched status register
Channel 3 diagnostic latched status register
Channel 4 diagnostic latched status register
Interrupt mask register 3
Latched interrupt readback register 1
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表8-52. PAGE 0 Registers (continued)
Register Name
Address
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x52
0x53
0x54
0x55
0x57
0x58
0x59
0x5A
0x5C
0x5D
0x5E
0x5F
0x61
0x62
0x63
0x64
Acronym
Reset Value
Section
INT_LTCH2
INT_LTCH3
MBDIAG_CFG0
MBDIAG_CFG1
MBDIAG_CFG2
BIAS_CFG
CH1_CFG0
CH1_CFG1
CH1_CFG2
CH1_CFG3
CH1_CFG4
CH2_CFG0
CH2_CFG1
CH2_CFG2
CH2_CFG3
CH2_CFG4
CH3_CFG0
CH3_CFG1
CH3_CFG2
CH3_CFG3
CH3_CFG4
CH4_CFG0
CH4_CFG1
CH4_CFG2
CH4_CFG3
CH4_CFG4
CH5_CFG0
CH5_CFG2
CH5_CFG3
CH5_CFG4
CH6_CFG0
CH6_CFG2
CH6_CFG3
CH6_CFG4
CH7_CFG0
CH7_CFG2
CH7_CFG3
CH7_CFG4
CH8_CFG0
CH8_CFG2
CH8_CFG3
CH8_CFG4
DIAG_CFG0
Latched interrupt readback register 2
0x00
0x00
0xBA
0x4B
0x10
0xD0
0x10
0x00
0xC9
0x80
0x00
0x10
0x00
0xC9
0x80
0x00
0x10
0x00
0xC9
0x80
0x00
0x10
0x00
0xC9
0x80
0x00
0x10
0xC9
0x80
0x00
0x10
0xC9
0x80
0x00
0x00
0xC9
0x80
0x00
0x00
0xC9
0x80
0x00
0x00
节8.6.1.2.40
节8.6.1.2.41
节8.6.1.2.42
节8.6.1.2.43
节8.6.1.2.44
节8.6.1.2.45
节8.6.1.2.46
节8.6.1.2.47
节8.6.1.2.48
节8.6.1.2.49
节8.6.1.2.50
节8.6.1.2.51
节8.6.1.2.52
节8.6.1.2.53
节8.6.1.2.54
节8.6.1.2.55
节8.6.1.2.56
节8.6.1.2.57
节8.6.1.2.58
节8.6.1.2.59
节8.6.1.2.60
节8.6.1.2.61
节8.6.1.2.62
节8.6.1.2.63
节8.6.1.2.64
节8.6.1.2.65
节8.6.1.2.66
节8.6.1.2.67
节8.6.1.2.68
节8.6.1.2.69
节8.6.1.2.70
节8.6.1.2.71
节8.6.1.2.72
节8.6.1.2.73
节8.6.1.2.74
节8.6.1.2.75
节8.6.1.2.76
节8.6.1.2.77
节8.6.1.2.78
节8.6.1.2.79
节8.6.1.2.80
节8.6.1.2.81
节8.6.1.2.82
Latched interrupt readback register 3
MICBIAS diagnostic register 0
MICBIAS diagnostic register 1
MICBIAS diagnostic register 2
Bias configuration register
Channel 1 configuration register 0
Channel 1 configuration register 1
Channel 1 configuration register 2
Channel 1 configuration register 3
Channel 1 configuration register 4
Channel 2 configuration register 0
Channel 2 configuration register 1
Channel 2 configuration register 2
Channel 2 configuration register 3
Channel 2 configuration register 4
Channel 3 configuration register 0
Channel 3 configuration register 1
Channel 3 configuration register 2
Channel 3 configuration register 3
Channel 3 configuration register 4
Channel 4 configuration register 0
Channel 4 configuration register 1
Channel 4 configuration register 2
Channel 4 configuration register 3
Channel 4 configuration register 4
Channel 5 configuration register 0
Channel 5 configuration register 2
Channel 5 configuration register 3
Channel 5 configuration register 4
Channel 6 configuration register 0
Channel 6 configuration register 2
Channel 6 configuration register 3
Channel 6 configuration register 4
Channel 7 configuration register 0
Channel 7 configuration register 2
Channel 7 configuration register 3
Channel 7 configuration register 4
Channel 8 configuration register 0
Channel 8 configuration register 2
Channel 8 configuration register 3
Channel 8 configuration register 4
Input diagnostic configuration register 0
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表8-52. PAGE 0 Registers (continued)
Register Name
Address
0x65
0x66
0x67
0x68
0x6A
0x6B
0x6C
0x70
0x73
0x74
0x75
0x76
0x77
0x7E
Acronym
Reset Value
0x37
Section
DIAG_CFG1
DIAG_CFG2
DIAG_CFG3
DIAG_CFG4
BOOST_CFG
DSP_CFG0
DSP_CFG1
AGC_CFG0
IN_CH_EN
Input diagnostic configuration register 1
节8.6.1.2.83
节8.6.1.2.84
节8.6.1.2.85
节8.6.1.2.86
节8.6.1.2.87
节8.6.1.2.88
节8.6.1.2.89
节8.6.1.2.90
节8.6.1.2.91
节8.6.1.2.92
节8.6.1.2.93
节8.6.1.2.94
节8.6.1.2.95
节8.6.1.2.96
Input diagnostic configuration register 2
Input diagnostic configuration register 3
Input diagnostic configuration register 4
Boost configuration register
0x87
0xB8
0x00
0x00
DSP configuration register 0
0x01
DSP configuration register 1
0x48
AGC configuration register 0
0xE7
0xFC
0x00
Input channel enable configuration register
ASI output channel enable configuration register
Power up configuration register
Device status value register 0
ASI_OUT_CH_EN
PWR_CFG
0x00
DEV_STS0
DEV_STS1
I2C_CKSUM
0x00
Device status value register 1
0x80
I2C Checksum
0x00
8.6.1.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x0]
PAGE_CFG is shown in 图8-77 and described in 表8-53.
Return to the 表8-52.
The device memory map is divided into pages. This register sets the page.
图8-77. PAGE_CFG Register
7
6
5
4
3
2
1
0
PAGE[7:0]
R/W-00000000b
表8-53. PAGE_CFG Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
PAGE[7:0]
R/W
00000000b These bits set the device page.
0d = Page 0
1d = Page 1
…
255d = Page 255
8.6.1.2.2 SW_RESET Register (Address = 0x1) [Reset = 0x0]
SW_RESET is shown in 图8-78 and described in 表8-54.
Return to the 表8-52.
This register is the software reset register. Asserting a software reset places all register values in their default
power-on-reset (POR) state.
图8-78. SW_RESET Register
7
6
5
4
3
2
1
0
RESERVED
R-0000000b
SW_RESET
R/W-0b
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表8-54. SW_RESET Register Field Descriptions
Bit
7-1
0
Field
Type
Reset
0000000b
0b
Description
RESERVED
SW_RESET
R
Reserved bits; Write only reset value
R/W
Software reset. This bit is self-clearing.
0d = Do not reset
1d = Reset
8.6.1.2.3 SLEEP_CFG Register (Address = 0x2) [Reset = 0x0]
SLEEP_CFG is shown in 图8-79 and described in 表8-55.
Return to the 表8-52.
This register configures the regulator, VREF quick charge, I2C broadcast and sleep mode.
图8-79. SLEEP_CFG Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
R/W-00b
VREF_QCHG[1:0]
I2C_BRDCAST
_EN
RESERVED
SLEEP_ENZ
R/W-0b
R/W-00b
R/W-0b
R-0b
R/W-0b
表8-55. SLEEP_CFG Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
Reset
Description
RESERVED
0b
Reserved bit; Write only reset value
6-5
4-3
RESERVED
00b
00b
Reserved bits; Write only reset values
VREF_QCHG[1:0]
The duration of the quick-charge for the VREF external capacitor is
set using an internal series impedance of 200 Ω.
0d = VREF quick-charge duration of 3.5 ms (typical)
1d = VREF quick-charge duration of 10 ms (typical)
2d = VREF quick-charge duration of 50 ms (typical)
3d = VREF quick-charge duration of 100 ms (typical)
2
I2C_BRDCAST_EN
R/W
0b
I2C broadcast addressing setting.
0d = I2C broadcast mode disabled; the I2C slave address is
determined based on the ADDR pins
1d = I2C broadcast mode enabled; the I2C slave address is fixed at
1001 100
1
0
RESERVED
SLEEP_ENZ
R
0b
0b
Reserved bit; Write only reset value
R/W
Sleep mode setting.
0d = Device is in sleep mode
1d = Device is not in sleep mode
8.6.1.2.4 SHDN_CFG Register (Address = 0x5) [Reset = 0x5]
SHDN_CFG is shown in 图8-80 and described in 表8-56.
Return to the 表8-52.
This register configures the device shutdown
图8-80. SHDN_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
SHDNZ_CFG[1:0]
R/W-01b
DREG_KA_TIME[1:0]
R/W-01b
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表8-56. SHDN_CFG Register Field Descriptions
Bit
7-4
3-2
Field
Type
Reset
0000b
01b
Description
RESERVED
SHDNZ_CFG[1:0]
R
Reserved bits; Write only reset value
Shutdown configuration.
R/W
0d = DREG is powered down immediately after SHDNZ asserts
1d = DREG remains active to enable a clean shut down until a time-
out is reached; after the time-out period, DREG is forced to power off
2d = DREG remains active until the device cleanly shuts down
3d = Reserved
1-0
DREG_KA_TIME[1:0]
R/W
01b
These bits set how long DREG remains active after SHDNZ asserts.
0d = DREG remains active for 30 ms (typical)
1d = DREG remains active for 25 ms (typical)
2d = DREG remains active for 10 ms (typical)
3d = DREG remains active for 5 ms (typical)
8.6.1.2.5 ASI_CFG0 Register (Address = 0x7) [Reset = 0x30]
ASI_CFG0 is shown in 图8-81 and described in 表8-57.
Return to the 表8-52.
This register is the ASI configuration register 0.
图8-81. ASI_CFG0 Register
7
6
5
4
3
2
1
0
ASI_FORMAT[1:0]
R/W-00b
ASI_WLEN[1:0]
R/W-11b
FSYNC_POL
R/W-0b
BCLK_POL
R/W-0b
TX_EDGE
R/W-0b
TX_FILL
R/W-0b
表8-57. ASI_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
ASI_FORMAT[1:0]
R/W
00b
ASI protocol format.
0d = TDM mode
1d = I2S mode
2d = LJ (left-justified) mode
3d = Reserved
5-4
ASI_WLEN[1:0]
R/W
11b
ASI word or slot length.
0d = 16 bits
1d = 20 bits
2d = 24 bits
3d = 32 bits
3
2
1
FSYNC_POL
BCLK_POL
TX_EDGE
R/W
R/W
R/W
0b
0b
0b
ASI FSYNC polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
ASI BCLK polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
ASI data output (on the primary and secondary data pin) transmit
edge.
0d = Default edge as per the protocol configuration setting in bit 2
(BCLK_POL)
1d = Inverted following edge (half cycle delay) with respect to the
default edge setting
0
TX_FILL
R/W
0b
ASI data output (on the primary and secondary data pin) for any
unused cycles
0d = Always transmit 0 for unused cycles
1d = Always use Hi-Z for unused cycles
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8.6.1.2.6 ASI_CFG1 Register (Address = 0x8) [Reset = 0x0]
ASI_CFG1 is shown in 图8-82 and described in 表8-58.
Return to the 表8-52.
This register is the ASI configuration register 1.
图8-82. ASI_CFG1 Register
7
6
5
4
3
2
1
0
TX_LSB
R/W-0b
TX_KEEPER[1:0]
R/W-00b
TX_OFFSET[4:0]
R/W-00000b
表8-58. ASI_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TX_LSB
R/W
0b
ASI data output (on the primary and secondary data pin) for LSB
transmissions.
0d = Transmit the LSB for a full cycle
1d = Transmit the LSB for the first half cycle and Hi-Z for the second
half cycle
6-5
4-0
TX_KEEPER[1:0]
TX_OFFSET[4:0]
R/W
R/W
00b
ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled
1d = Bus keeper is always enabled
2d = Bus keeper is enabled during LSB transmissions only for one
cycle
3d = Bus keeper is enabled during LSB transmissions only for one
and half cycles
00000b
ASI data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard
protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is
the left and right slot 0) offset of one BCLK cycle with respect to
standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is
the left and right slot 0) offset of two BCLK cycles with respect to
standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ
mode is the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is
the left and right slot 0) offset of 31 BCLK cycles with respect to
standard protocol
8.6.1.2.7 ASI_CFG2 Register (Address = 0x9) [Reset = 0x0]
ASI_CFG2 is shown in 图8-83 and described in 表8-59.
Return to the 表8-52.
This register is the ASI configuration register 2.
图8-83. ASI_CFG2 Register
7
6
5
4
3
2
1
0
ASI_DAISY
RESERVED
ASI_ERR
ASI_ERR_RCO
V
RESERVED
R-0000b
R/W-0b
R-0b
R/W-0b
R/W-0b
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表8-59. ASI_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ASI_DAISY
R/W
0b
ASI daisy chain connection.
0d = All devices are connected in the common ASI bus
1d = All devices are daisy-chained for the ASI bus
6
5
RESERVED
ASI_ERR
R
0b
0b
Reserved bit; Write only reset value
R/W
ASI bus error detection.
0d = Enable bus error detection
1d = Disable bus error detection
4
ASI_ERR_RCOV
RESERVED
R/W
R
0b
ASI bus error auto resume.
0d = Enable auto resume after bus error recovery
1d = Disable auto resume after bus error recovery and remain
powered down until the host configures the device
3-0
0000b
Reserved bits; Write only reset value
8.6.1.2.8 ASI_CH1 Register (Address = 0xB) [Reset = 0x0]
ASI_CH1 is shown in 图8-84 and described in 表8-60.
Return to the 表8-52.
This register is the ASI slot configuration register for channel 1.
图8-84. ASI_CH1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH1_OUTPUT
R/W-0b
CH1_SLOT[5:0]
R/W-000000b
表8-60. ASI_CH1 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
0b
Reserved bit; Write only reset value
Channel 1 output line.
6
CH1_OUTPUT
R/W
0b
0d = Channel 1 output is on the ASI primary output pin (SDOUT)
1d = Channel 1 output is on the ASI secondary output pin (GPIO1 or
GPOx)
5-0
CH1_SLOT[5:0]
R/W
000000b
Channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.2.9 ASI_CH2 Register (Address = 0xC) [Reset = 0x1]
ASI_CH2 is shown in 图8-85 and described in 表8-61.
Return to the 表8-52.
This register is the ASI slot configuration register for channel 2.
图8-85. ASI_CH2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH2_OUTPUT
R/W-0b
CH2_SLOT[5:0]
R/W-000001b
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图8-85. ASI_CH2 Register (continued)
表8-61. ASI_CH2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R
0b
Reserved bit; Write only reset value
Channel 2 output line.
6
CH2_OUTPUT
R/W
0b
0d = Channel 2 output is on the ASI primary output pin (SDOUT)
1d = Channel 2 output is on the ASI secondary output pin (GPIO1 or
GPOx)
5-0
CH2_SLOT[5:0]
R/W
000001b
Channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.2.10 ASI_CH3 Register (Address = 0xD) [Reset = 0x2]
ASI_CH3 is shown in 图8-86 and described in 表8-62.
Return to the 表8-52.
This register is the ASI slot configuration register for channel 3.
图8-86. ASI_CH3 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH3_OUTPUT
R/W-0b
CH3_SLOT[5:0]
R/W-000010b
表8-62. ASI_CH3 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
0b
Reserved bit; Write only reset value
Channel 3 output line.
6
CH3_OUTPUT
R/W
0b
0d = Channel 3 output is on the ASI primary output pin (SDOUT)
1d = Channel 3 output is on the ASI secondary output pin (GPIO1 or
GPOx)
5-0
CH3_SLOT[5:0]
R/W
000010b
Channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.2.11 ASI_CH4 Register (Address = 0xE) [Reset = 0x3]
ASI_CH4 is shown in 图8-87 and described in 表8-63.
Return to the 表8-52.
This register is the ASI slot configuration register for channel 4.
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图8-87. ASI_CH4 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH4_OUTPUT
R/W-0b
CH4_SLOT[5:0]
R/W-000011b
表8-63. ASI_CH4 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
0b
Reserved bit; Write only reset value
Channel 4 output line.
6
CH4_OUTPUT
R/W
0b
0d = Channel 4 output is on the ASI primary output pin (SDOUT)
1d = Channel 4 output is on the ASI secondary output pin (GPIO1 or
GPOx)
5-0
CH4_SLOT[5:0]
R/W
000011b
Channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.2.12 ASI_CH5 Register (Address = 0xF) [Reset = 0x4]
ASI_CH5 is shown in 图8-88 and described in 表8-64.
Return to the 表8-52.
This register is the ASI slot configuration register for channel 5.
图8-88. ASI_CH5 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH5_OUTPUT
R/W-0b
CH5_SLOT[5:0]
R/W-000100b
表8-64. ASI_CH5 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
0b
Reserved bit; Write only reset value
6
CH5_OUTPUT
R/W
0b
Channel 5 output line.
0d = Channel 5 output is on the ASI primary output pin (SDOUT)
1d = Channel 5 output is on the ASI secondary output pin (GPIO1 or
GPOx)
5-0
CH5_SLOT[5:0]
R/W
000100b
Channel 5 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.2.13 ASI_CH6 Register (Address = 0x10) [Reset = 0x5]
ASI_CH6 is shown in 图8-89 and described in 表8-65.
Return to the 表8-52.
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This register is the ASI slot configuration register for channel 6.
图8-89. ASI_CH6 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH6_OUTPUT
R/W-0b
CH6_SLOT[5:0]
R/W-000101b
表8-65. ASI_CH6 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
0b
Reserved bit; Write only reset value
Channel 6 output line.
6
CH6_OUTPUT
R/W
0b
0d = Channel 6 output is on the ASI primary output pin (SDOUT)
1d = Channel 6 output is on the ASI secondary output pin (GPIO1 or
GPOx)
5-0
CH6_SLOT[5:0]
R/W
000101b
Channel 6 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.2.14 ASI_CH7 Register (Address = 0x11) [Reset = 0x6]
ASI_CH7 is shown in 图8-90 and described in 表8-66.
Return to the 表8-52.
This register is the ASI slot configuration register for channel 7.
图8-90. ASI_CH7 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH7_OUTPUT
R/W-0b
CH7_SLOT[5:0]
R/W-000110b
表8-66. ASI_CH7 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
0b
Reserved bit; Write only reset value
Channel 7 output line.
6
CH7_OUTPUT
R/W
0b
0d = Channel 7 output is on the ASI primary output pin (SDOUT)
1d = Channel 7 output is on the ASI secondary output pin (GPIO1 or
GPOx)
5-0
CH7_SLOT[5:0]
R/W
000110b
Channel 7 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.2.15 ASI_CH8 Register (Address = 0x12) [Reset = 0x7]
ASI_CH8 is shown in 图8-91 and described in 表8-67.
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Return to the 表8-52.
This register is the ASI slot configuration register for channel 8.
图8-91. ASI_CH8 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH8_OUTPUT
R/W-0b
CH8_SLOT[5:0]
R/W-000111b
表8-67. ASI_CH8 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R
0b
Reserved bit; Write only reset value
Channel 8 output line.
6
CH8_OUTPUT
R/W
0b
0d = Channel 8 output is on the ASI primary output pin (SDOUT)
1d = Channel 8 output is on the ASI secondary output pin (GPIO1 or
GPOx)
5-0
CH8_SLOT[5:0]
R/W
000111b
Channel 8 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.2.16 MST_CFG0 Register (Address = 0x13) [Reset = 0x2]
MST_CFG0 is shown in 图8-92 and described in 表8-68.
Return to the 表8-52.
This register is the ASI master mode configuration register 0.
图8-92. MST_CFG0 Register
7
6
5
4
3
2
1
0
MST_SLV_CFG AUTO_CLK_CF AUTO_MODE_ BCLK_FSYNC_
FS_MODE
MCLK_FREQ_SEL[2:0]
G
PLL_DIS
GATE
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-010b
表8-68. MST_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MST_SLV_CFG
R/W
0b
ASI master or slave configuration register setting.
0d = Device is in slave mode (both BCLK and FSYNC are inputs to
the device)
1d = Device is in master mode (both BCLK and FSYNC are
generated from the device)
6
5
AUTO_CLK_CFG
AUTO_MODE_PLL_DIS
R/W
R/W
0b
0b
Automatic clock configuration setting.
0d = Auto clock configuration is enabled (all internal clock divider and
PLL configurations are auto derived)
1d = Auto clock configuration is disabled (custom mode and device
GUI must be used for the device configuration settings)
Automatic mode PLL setting.
0d = PLL is enabled in auto clock configuration
1d = PLL is disabled in auto clock configuration
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表8-68. MST_CFG0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
BCLK_FSYNC_GATE
R/W
0b
BCLK and FSYNC clock gate (valid when the device is in master
mode).
0d = Do not gate BCLK and FSYNC
1d = Force gate BCLK and FSYNC when being transmitted from the
device in master mode
3
FS_MODE
R/W
R/W
0b
Sample rate setting (valid when the device is in master mode).
0d = fS is a multiple (or submultiple) of 48 kHz
1d = fS is a multiple (or submultiple) of 44.1 kHz
2-0
MCLK_FREQ_SEL[2:0]
010b
These bits select the MCLK (GPIO or GPIx) frequency for the PLL
source clock input (valid when the device is in master mode and
MCLK_FREQ_SEL_MODE = 0).
0d = 12 MHz
1d = 12.288 MHz
2d = 13 MHz
3d = 16 MHz
4d = 19.2 MHz
5d = 19.68 MHz
6d = 24 MHz
7d = 24.576 MHz
8.6.1.2.17 MST_CFG1 Register (Address = 0x14) [Reset = 0x48]
MST_CFG1 is shown in 图8-93 and described in 表8-69.
Return to the 表8-52.
This register is the ASI master mode configuration register 1.
图8-93. MST_CFG1 Register
7
6
5
4
3
2
1
0
FS_RATE[3:0]
R/W-0100b
FS_BCLK_RATIO[3:0]
R/W-1000b
表8-69. MST_CFG1 Register Field Descriptions
Bit
7-4
Field
FS_RATE[3:0]
Type
Reset
Description
R/W
0100b
Programmed sample rate of the ASI bus (not used when the device
is configured in slave mode auto clock configuration).
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 15d = Reserved
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表8-69. MST_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
FS_BCLK_RATIO[3:0]
R/W
1000b
Programmed BCLK to FSYNC frequency ratio of the ASI bus (not
used when the device is configured in slave mode auto clock
configuration).
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d = Reserved
14d = Reserved
15d = Reserved
8.6.1.2.18 ASI_STS Register (Address = 0x15) [Reset = 0xFF]
ASI_STS is shown in 图8-94 and described in 表8-70.
Return to the 表8-52.
This register s the ASI bus clock monitor status register
图8-94. ASI_STS Register
7
6
5
4
3
2
1
0
FS_RATE_STS[3:0]
R-1111b
FS_RATIO_STS[3:0]
R-1111b
表8-70. ASI_STS Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
FS_RATE_STS[3:0]
R
1111b
Detected sample rate of the ASI bus.
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 14d = Reserved
15d = Invalid sample rate
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表8-70. ASI_STS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
FS_RATIO_STS[3:0]
R
1111b
Detected BCLK to FSYNC frequency ratio of the ASI bus.
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d = Reserved
14d = Reserved
15d = Invalid ratio
8.6.1.2.19 CLK_SRC Register (Address = 0x16) [Reset = 0x10]
CLK_SRC is shown in 图8-95 and described in 表8-71.
Return to the 表8-52.
This register is the clock source configuration register.
图8-95. CLK_SRC Register
7
6
5
4
3
2
1
0
DIS_PLL_SLV_ MCLK_FREQ_
MCLK_RATIO_SEL[2:0]
RESERVED
CLK_SRC
SEL_MODE
R/W-0b
R/W-0b
R/W-010b
R-000b
表8-71. CLK_SRC Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DIS_PLL_SLV_CLK_SRC R/W
0b
Audio root clock source setting when the device is configured with
the PLL disabled in the auto clock configuration for slave mode
(AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source
1d = MCLK (GPIOx or GPIx) is used as the audio root clock source
(the MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting)
6
MCLK_FREQ_SEL_MOD R/W
E
0b
Master mode MCLK (GPIOx or GPIx) frequency selection mode
(valid when the device is in auto clock configuration).
0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19)
configuration
1d = MCLK frequency is specified as a multiple of FSYNC in the
MCLK_RATIO_SEL (P0_R22) configuration
5-3
MCLK_RATIO_SEL[2:0]
R/W
010b
These bits select the MCLK (GPIOx or GPIx) to FSYNC ratio for
master mode or when MCLK is used as the audio root clock source
in slave mode.
0d = Ratio of 64
1d = Ratio of 256
2d = Ratio of 384
3d = Ratio of 512
4d = Ratio of 768
5d = Ratio of 1024
6d = Ratio of 1536
7d = Ratio of 2304
2-0
RESERVED
R
000b
Reserved bits; Write only reset values
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8.6.1.2.20 PDMIN_CFG Register (Address = 0x20) [Reset = 0x0]
PDMIN_CFG is shown in 图8-96 and described in 表8-72.
Return to the 表8-52.
This register is the PDM DINx sampling edge configuration register.
图8-96. PDMIN_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
PDMDIN1_EDG PDMDIN2_EDG
RESERVED
R-0000b
E
E
R/W-0b
R/W-0b
表8-72. PDMIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
00b
0b
Description
7-6
5
RESERVED
R
Reserved bits; Write only reset value
PDMDIN1_EDGE
R/W
PDMCLK latching edge used for channel 5 and channel 6 data.
0d = Channel 5 data are latched on the negative edge, channel 6
data are latched on the positive edge
1d = Channel 5 data are latched on the positive edge, channel 6 data
are latched on the negative edge
4
PDMDIN2_EDGE
RESERVED
R/W
R
0b
PDMCLK latching edge used for channel 7 and channel 8 data.
0d = Channel 7 data are latched on the negative edge, channel 8
data are latched on the positive edge
1d = Channel 7 data are latched on the positive edge, channel 8 data
are latched on the negative edge
3-0
0000b
Reserved bits; Write only reset value
8.6.1.2.21 GPIO_CFG0 Register (Address = 0x21) [Reset = 0x22]
GPIO_CFG0 is shown in 图8-97 and described in 表8-73.
Return to the 表8-52.
This register is the GPIO configuration register 0.
图8-97. GPIO_CFG0 Register
7
6
5
4
3
2
1
0
GPIO1_CFG[3:0]
R/W-0010b
RESERVED
R-0b
GPIO1_DRV[2:0]
R/W-010b
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表8-73. GPIO_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPIO1_CFG[3:0]
R/W
0010b
GPIO1 configuration.
0d = GPIO1 is disabled
1d = GPIO1 is configured as a general-purpose output (GPO)
2d = GPIO1 is configured as a device interrupt output (IRQ)
3d = GPIO1 is configured as a secondary ASI output (SDOUT2)
4d = GPIO1 is configured as a PDM clock output (PDMCLK)
5d = Reserved
6d = Reserved
7d = GPIO1 is configured as an input to power down all ADC
channels
8d = GPIO1 is configured as an input to control when MICBIAS turns
on or off (MICBIAS_EN)
9d = GPIO1 is configured as a general-purpose input (GPI)
10d = GPIO1 is configured as a master clock input (MCLK)
11d = GPIO1 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = GPIO1 is configured as a PDM data input for channel 5 and
channel 6 (PDMDIN1)
15d = GPIO1 is configured as a PDM data input for channel 7 and
channel 8 (PDMDIN2)
3
RESERVED
R
0b
Reserved bit; Write only reset value
2-0
GPIO1_DRV[2:0]
R/W
010b
GPIO1 output drive configuration (not used when GPIO1 is
configured as SDOUT2).
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved
8.6.1.2.22 GPIO_CFG1 Register (Address = 0x22) [Reset = 0x0]
GPIO_CFG1 is shown in 图8-98 and described in 表8-74.
Return to the 表8-52.
This register is the GPIO configuration register 1.
图8-98. GPIO_CFG1 Register
7
6
5
4
3
2
1
0
GPIO2_CFG[3:0]
R/W-0000b
RESERVED
R-0b
GPIO2_DRV[2:0]
R/W-000b
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表8-74. GPIO_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPIO2_CFG[3:0]
R/W
0000b
GPIO2 configuration.
0d = GPIO2 is disabled
1d = GPIO2 is configured as a general-purpose output (GPO)
2d = GPIO2 is configured as a device interrupt output (IRQ)
3d = GPIO2 is configured as a secondary ASI output (SDOUT2)
4d = GPIO2 is configured as a PDM clock output (PDMCLK)
5d = Reserved
6d = Reserved
7d = GPIO2 is configured as an input to power down all ADC
channels
8d = GPIO2 is configured as an input to control when MICBIAS turns
on or off (MICBIAS_EN)
9d = GPIO2 is configured as a general-purpose input (GPI)
10d = GPIO2 is configured as a master clock input (MCLK)
11d = GPIO2 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = GPIO2 is configured as a PDM data input for channel 5 and
channel 6 (PDMDIN1)
15d = GPIO2 is configured as a PDM data input for channel 7 and
channel 8 (PDMDIN2)
3
RESERVED
R
0b
Reserved bit; Write only reset value
2-0
GPIO2_DRV[2:0]
R/W
000b
GPIO2 output drive configuration (not used when GPIO2 is
configured as SDOUT2).
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved
8.6.1.2.23 GPIO_CFG2 Register (Address = 0x23) [Reset = 0x0]
GPIO_CFG2 is shown in 图8-99 and described in 表8-75.
Return to the 表8-52.
This register is the GPIO configuration register 2.
图8-99. GPIO_CFG2 Register
7
6
5
4
3
2
1
0
GPIO3_CFG[3:0]
R/W-0000b
RESERVED
R-0b
GPIO3_DRV[2:0]
R/W-000b
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表8-75. GPIO_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPIO3_CFG[3:0]
R/W
0000b
GPIO3 configuration.
0d = GPIO3 is disabled
1d = GPIO3 is configured as a general-purpose output (GPO)
2d = GPIO3 is configured as a device interrupt output (IRQ)
3d = GPIO3 is configured as a secondary ASI output (SDOUT2)
4d = GPIO3 is configured as a PDM clock output (PDMCLK)
5d = Reserved
6d = Reserved
7d = GPIO3 is configured as an input to power down all ADC
channels
8d = GPIO3 is configured as an input to control when MICBIAS turns
on or off (MICBIAS_EN)
9d = GPIO3 is configured as a general-purpose input (GPI)
10d = GPIO3 is configured as a master clock input (MCLK)
11d = GPIO3 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = GPIO3 is configured as a PDM data input for channel 5 and
channel 6 (PDMDIN1)
15d = GPIO3 is configured as a PDM data input for channel 7 and
channel 8 (PDMDIN2)
3
RESERVED
R
0b
Reserved bit; Write only reset value
2-0
GPIO3_DRV[2:0]
R/W
000b
GPIO3 output drive configuration (not used when GPIO3 is
configured as SDOUT2).
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved
8.6.1.2.24 GPI_CFG0 Register (Address = 0x24) [Reset = 0x0]
GPI_CFG0 is shown in 图8-100 and described in 表8-76.
Return to the 表8-52.
This register is the GPI configuration register 0.
图8-100. GPI_CFG0 Register
7
6
5
4
3
2
1
0
GPI1_CFG[3:0]
R/W-0000b
RESERVED
R-0000b
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表8-76. GPI_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPI1_CFG[3:0]
R/W
0000b
GPI1 configuration.
0d = GPI1 is disabled
1d to 6d = Reserved
7d = GPI1 is configured as an input to power down all ADC channels
8d = GPI1 is configured as an input to control when MICBIAS turns
on or off (MICBIAS_EN)
9d = GPI1 is configured as a general-purpose input (GPI)
10d = GPI1 is configured as a master clock input (MCLK)
11d = GPI1 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = GPI1 is configured as a PDM data input for channel 5 and
channel 6 (PDMDIN1)
15d = GPI1 is configured as a PDM data input for channel 7 and
channel 8 (PDMDIN2)
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.25 GPI_CFG1 Register (Address = 0x25) [Reset = 0x0]
GPI_CFG1 is shown in 图8-101 and described in 表8-77.
Return to the 表8-52.
This register is the GPI configuration register 1.
图8-101. GPI_CFG1 Register
7
6
5
4
3
2
1
0
GPI2_CFG[3:0]
R/W-0000b
RESERVED
R-0000b
表8-77. GPI_CFG1 Register Field Descriptions
Bit
7-4
Field
GPI2_CFG[3:0]
Type
Reset
Description
R/W
0000b
GPI2 configuration.
0d = GPI2 is disabled
1d to 6d = Reserved
7d = GPI2 is configured as an input to power down all ADC channels
8d = GPI2 is configured as an input to control when MICBIAS turns
on or off (MICBIAS_EN)
9d = GPI2 is configured as a general-purpose input (GPI)
10d = GPI2 is configured as a master clock input (MCLK)
11d = GPI2 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = GPI2 is configured as a PDM data input for channel 5 and
channel 6 (PDMDIN1)
15d = GPI2 is configured as a PDM data input for channel 7 and
channel 8 (PDMDIN2)
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.26 GPIO_VAL Register (Address = 0x26) [Reset = 0x0]
GPIO_VAL is shown in 图8-102 and described in 表8-78.
Return to the 表8-52.
This register is the GPIO output value register.
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图8-102. GPIO_VAL Register
7
6
5
4
3
2
1
0
GPIO1_VAL
R/W-0b
GPIO2_VAL
R/W-0b
GPIO3_VAL
R/W-0b
RESERVED
R-00000b
表8-78. GPIO_VAL Register Field Descriptions
Bit
Field
GPIO1_VAL
Type
Reset
Description
7
R/W
0b
GPIO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
6
5
GPIO2_VAL
GPIO3_VAL
RESERVED
R/W
R/W
R
0b
GPIO2 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
0b
GPIO3 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
4-0
00000b
Reserved bits; Write only reset value
8.6.1.2.27 GPIO_MON Register (Address = 0x27) [Reset = 0x0]
GPIO_MON is shown in 图8-103 and described in 表8-79.
Return to the 表8-52.
This register is the GPIO monitor value register.
图8-103. GPIO_MON Register
7
6
5
4
3
2
1
0
GPIO1_MON
R-0b
GPIO2_MON
R-0b
GPIO3_MON
R-0b
GPI1_MON
R-0b
GPI2_MON
R-0b
RESERVED
R-000b
表8-79. GPIO_MON Register Field Descriptions
Bit
Field
GPIO1_MON
Type
Reset
Description
7
R
0b
GPIO1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
6
5
GPIO2_MON
GPIO3_MON
GPI1_MON
GPI2_MON
RESERVED
R
R
R
R
R
0b
GPIO2 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
0b
GPIO3 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
4
0b
GPI1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
3
0b
GPI2 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
2-0
000b
Reserved bits; Write only reset value
8.6.1.2.28 INT_CFG Register (Address = 0x28) [Reset = 0x0]
INT_CFG is shown in 图8-104 and described in 表8-80.
Return to the 表8-52.
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This regiser is the interrupt configuration register.
图8-104. INT_CFG Register
7
6
5
4
3
2
1
0
INT_POL
INT_EVENT[1:0]
PD_ON_FLT_CFG[1:0]
R/W-00b
LTCH_READ_C PD_ON_FLT_R LTCH_CLR_ON
FG
CV_CFG
_READ
R/W-0b
R/W-00b
R/W-0b
R/W-0b
R/W-0b
表8-80. INT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_POL
R/W
0b
Interrupt polarity.
0d = Active low (IRQZ)
1d = Active high (IRQ)
6-5
INT_EVENT[1:0]
R/W
R/W
00b
00b
Interrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event
Dont use
2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration
on any unmasked latched interrupts event
3d = INT asserts for 2 ms (typical) one time on each pulse for any
unmasked interrupts event
4-3
PD_ON_FLT_CFG[1:0]
Powerdown configuration when fault detected for any channel or
MICBIAS fault detected.
0d = Faults event are not used for ADC and MICBIAS power down. It
is recommend to set these bits as 2d to shutdown the blocks for
which fault occurred.
1d = Only unmasked faults are used for power down of respective
ADC channel; In case of MICBIAS fault detected, MICBIAS and all
ADC channels gets powered-down based on P0_R58 settings
2d = Both masked or unmasked faults are used for power down of
respective ADC channel; In case of MICBIAS fault detected,
MICBIAS and all ADC channels gets powered-down based on
P0_R58 settings.
3d = Reserved
2
1
LTCH_READ_CFG
R/W
0b
0b
Interrupt latch registers readback configuration.
0d = All interrupts can be read through the LTCH registers
1d = Only unmasked interrupts can be read through the LTCH
registers
PD_ON_FLT_RCV_CFG R/W
Recovery configuration for ADC channels when fault goes away.
0d = Auto recovery, ADC channels are re-powered up when fault
goes away
1d = Manual recovery, ADC channels are required to power-up
manually using P0_R119 when fault goes away
0
LTCH_CLR_ON_READ
R/W
0b
Configuration for clearing LTCH register bits.
0d = LTCH register bits are cleared on register read only if live status
is zero
1d = LTCH register bits are cleared on register read irrespective of
live status and set only if live status goes again low to high
8.6.1.2.29 INT_MASK0 Register (Address = 0x29) [Reset = 0xFF]
INT_MASK0 is shown in 图8-105 and described in 表8-81.
Return to the 表8-52.
This register is the interrupt masks register 0.
图8-105. INT_MASK0 Register
7
6
5
4
3
2
1
0
INT_MASK0
R/W-1b
INT_MASK0
R/W-1b
INT_MASK0
R/W-1b
INT_MASK0
R/W-1b
RESERVED
R/W-1b
RESERVED
R/W-1b
RESERVED
R/W-1b
RESERVED
R/W-1b
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图8-105. INT_MASK0 Register (continued)
表8-81. INT_MASK0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK0
INT_MASK0
INT_MASK0
INT_MASK0
R/W
1b
ASI clock error mask.
0d = Unmask
1d = Mask
6
5
4
R/W
R/W
R/W
1b
1b
1b
PLL lock interrupt mask.
0d = Unmask
1d = Mask
Boost or MICBIAS over temperature interrupt mask.
0d = Unmask
1d = Mask
Boost or MICBIAS over current interrupt mask.
0d = Unmask
1d = Mask
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R/W
1b
1b
1b
1b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.1.2.30 INT_MASK1 Register (Address = 0x2A) [Reset = 0x3]
INT_MASK1 is shown in 图8-106 and described in 表8-82.
Return to the 表8-52.
This register is the interrupt masks register 1.
图8-106. INT_MASK1 Register
7
6
5
4
3
2
1
0
INT_MASK1
R/W-0b
INT_MASK1
R/W-0b
INT_MASK1
R/W-0b
INT_MASK1
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-1b
RESERVED
R/W-1b
表8-82. INT_MASK1 Register Field Descriptions
Bit
Field
INT_MASK1
Type
Reset
Description
7
R/W
0b
Channel 1 input DC faults diagnostic interrupt mask.
0d = Unmask
1d = Mask
6
5
4
INT_MASK1
INT_MASK1
INT_MASK1
R/W
R/W
R/W
0b
0b
0b
Channel 2 input DC faults diagnostic interrupt mask.
0d = Unmask
1d = Mask
Channel 3 input DC faults diagnostic interrupt mask.
0d = Unmask
1d = Mask
Channel 4 input DC faults diagnostic interrupt mask.
0d = Unmask
1d = Mask
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R/W
0b
0b
1b
1b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
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8.6.1.2.31 INT_MASK2 Register (Address = 0x2B) [Reset = 0x0]
INT_MASK2 is shown in 图8-107 and described in 表8-83.
Return to the 表8-52.
This register is the interrupt masks register 2.
图8-107. INT_MASK2 Register
7
6
5
4
3
2
1
0
INT_MASK2
R/W-0b
INT_MASK2
R/W-0b
INT_MASK2
R/W-0b
INT_MASK2
R/W-0b
INT_MASK2
R/W-0b
INT_MASK2
R/W-0b
INT_MASK2
R/W-0b
INT_MASK2
R/W-0b
表8-83. INT_MASK2 Register Field Descriptions
Bit
Field
INT_MASK2
Type
Reset
Description
7
R/W
0b
Input diagnostics; Open inputs fault interrupt mask.
0d = Unmask
1d = Mask
6
5
4
3
2
1
0
INT_MASK2
INT_MASK2
INT_MASK2
INT_MASK2
INT_MASK2
INT_MASK2
INT_MASK2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
Input diagnostics; Inputs shorted fault interrupt mask.
0d = Unmask
1d = Mask
Input diagnostics; INxP shorted to ground fault interrupt mask.
0d = Unmask
1d = Mask
Input diagnostics; INxM shorted to ground fault interrupt mask.
0d = Unmask
1d = Mask
Input diagnostics; INxP shorted to MICBIAS fault interrupt mask.
0d = Unmask
1d = Mask
Input diagnostics; INxM shorted to MICBIAS fault interrupt mask.
0d = Unmask
1d = Mask
Input diagnostics; INxP shorted to VBAT_IN fault interrupt mask.
0d = Unmask
1d = Mask
Input diagnostics; INxM shorted to VBAT_IN fault interrupt mask.
0d = Unmask
1d = Mask
8.6.1.2.32 INT_LTCH0 Register (Address = 0x2C) [Reset = 0x0]
INT_LTCH0 is shown in 图8-108 and described in 表8-84.
Return to the 表8-52.
This register is the latched Interrupt readback register 0.
图8-108. INT_LTCH0 Register
7
6
5
4
3
2
1
0
INT_LTCH0
R-0b
INT_LTCH0
R-0b
INT_LTCH0
R-0b
INT_LTCH0
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-0b
表8-84. INT_LTCH0 Register Field Descriptions
Bit
Field
INT_LTCH0
Type
Reset
Description
7
R
0b
Fault status for an ASI bus clock error (self-clearing bit).
0d = No fault detected
1d = Fault detected
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表8-84. INT_LTCH0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
INT_LTCH0
R
0b
Status of PLL lock (self-clearing bit).
0d = No PLL lock detected
1d = PLL lock detected
5
4
INT_LTCH0
R
R
0b
0b
Fault status for boost or MICBIAS over temperature (self-clearing
bit).
0d = No fault detected
1d = Fault detected
INT_LTCH0
Fault status for boost or MICBIAS over current (self-clearing bit).
0d = No fault detected
1d = Fault detected
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
0b
0b
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.1.2.33 CHx_LTCH Register (Address = 0x2D) [Reset = 0x0]
CHx_LTCH is shown in 图8-109 and described in 表8-85.
Return to the 表8-52.
This register is the latched Interrupt status register for channel level diagnostic summary.
图8-109. CHx_LTCH Register
7
6
5
4
3
2
1
0
STS_CHx_LTC STS_CHx_LTC STS_CHx_LTC STS_CHx_LTC
RESERVED
RESERVED
STS_CHx_LTC
H
RESERVED
H
H
H
H
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表8-85. CHx_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
STS_CHx_LTCH
STS_CHx_LTCH
STS_CHx_LTCH
STS_CHx_LTCH
R
0b
Status of CH1_LTCH (self-clearing bit).
0d = No faults occurred in channel 1
1d = Atleast a fault has occurred in channel 1
R
R
R
0b
0b
0b
Status of CH2_LTCH (self-clearing bit).
0d = No faults occurred in channel 2
1d = Atleast a fault has occurred in channel 2
Status of CH3_LTCH (self-clearing bit).
0d = No faults occurred in channel 3
1d = Atleast a fault has occurred in channel 3
Status of CH4_LTCH (self-clearing bit).
0d = No faults occurred in channel 4
1d = Atleast a fault has occurred in channel 4
3
2
1
RESERVED
R
R
R
0b
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
RESERVED
STS_CHx_LTCH
Status of short to VBAT_IN fault detected when VBAT_IN is less than
MICBIAS (self-clearing bit).
0d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS
has not occurred in any channel
1d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS
has occurred in atleast one channel
0
RESERVED
R
0b
Reserved bit; Write only reset value
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8.6.1.2.34 CH1_LTCH Register (Address = 0x2E) [Reset = 0x0]
CH1_LTCH is shown in 图8-110 and described in 表8-86.
Return to the 表8-52.
This register is the latched Interrupt status register for channel 1 fault diagnostic
图8-110. CH1_LTCH Register
7
6
5
4
3
2
1
0
CH1_LTCH
R-0b
CH1_LTCH
R-0b
CH1_LTCH
R-0b
CH1_LTCH
R-0b
CH1_LTCH
R-0b
CH1_LTCH
R-0b
CH1_LTCH
R-0b
CH1_LTCH
R-0b
表8-86. CH1_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_LTCH
CH1_LTCH
CH1_LTCH
CH1_LTCH
CH1_LTCH
CH1_LTCH
CH1_LTCH
CH1_LTCH
R
0b
Channel 1 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
Channel 1 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
Channel 1 IN1P short to ground fault status (self-clearing bit).
0d = IN1P no short to ground detected
1d = IN1P short to ground detected
Channel 1 IN1M short to ground fault status (self-clearing bit).
0d = IN1M no short to ground detected
1d = IN1M short to ground detected
Channel 1 IN1P short to MICBIAS fault status (self-clearing bit).
0d = IN1P no short to MICBIAS detected
1d = IN1P short to MICBIAS detected
Channel 1 IN1M short to MICBIAS fault status (self-clearing bit).
0d = IN1M no short to MICBIAS detected
1d = IN1M short to MICBIAS detected
Channel 1 IN1P short to VBAT_IN fault status (self-clearing bit).
0d = IN1P no short to VBAT_IN detected
1d = IN1P short to VBAT_IN detected
Channel 1 IN1M short to VBAT_IN fault status (self-clearing bit - This
bit gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN1M no short to VBAT_IN detected
1d = IN1M short to VBAT_IN detected
8.6.1.2.35 CH2_LTCH Register (Address = 0x2F) [Reset = 0x0]
CH2_LTCH is shown in 图8-111 and described in 表8-87.
Return to the 表8-52.
This register is the latched Interrupt status register for channel 2 fault diagnostic.
图8-111. CH2_LTCH Register
7
6
5
4
3
2
1
0
CH2_LTCH
R-0b
CH2_LTCH
R-0b
CH2_LTCH
R-0b
CH2_LTCH
R-0b
CH2_LTCH
R-0b
CH2_LTCH
R-0b
CH2_LTCH
R-0b
CH2_LTCH
R-0b
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表8-87. CH2_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH2_LTCH
CH2_LTCH
CH2_LTCH
CH2_LTCH
CH2_LTCH
CH2_LTCH
CH2_LTCH
CH2_LTCH
R
0b
Channel 2 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
Channel 2 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
Channel 2 IN2P short to ground fault status (self-clearing bit).
0d = IN2P no short to ground detected
1d = IN2P short to ground detected
Channel 2 IN2M short to ground fault status (self-clearing bit).
0d = IN2M no short to ground detected
1d = IN2M short to ground detected
Channel 2 IN2P short to MICBIAS fault status (self-clearing bit).
0d = IN2P no short to MICBIAS detected
1d = IN2P short to MICBIAS detected
Channel 2 IN2M short to MICBIAS fault status (self-clearing bit).
0d = IN2M no short to MICBIAS detected
1d = IN2M short to MICBIAS detected
Channel 2 IN2P short to VBAT_IN fault status (self-clearing bit).
0d = IN2P no short to VBAT_IN detected
1d = IN2P short to VBAT_IN detected
Channel 2 IN2M short to VBAT_IN fault status (self-clearing bit - This
bit gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN2M no short to VBAT_IN detected
1d = IN2M short to VBAT_IN detected
8.6.1.2.36 CH3_LTCH Register (Address = 0x30) [Reset = 0x0]
CH3_LTCH is shown in 图8-112 and described in 表8-88.
Return to the 表8-52.
This register is the latched Interrupt status register for channel3 fault diagnostic
图8-112. CH3_LTCH Register
7
6
5
4
3
2
1
0
CH3_LTCH
R-0b
CH3_LTCH
R-0b
CH3_LTCH
R-0b
CH3_LTCH
R-0b
CH3_LTCH
R-0b
CH3_LTCH
R-0b
CH3_LTCH
R-0b
CH3_LTCH
R-0b
表8-88. CH3_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH3_LTCH
CH3_LTCH
CH3_LTCH
CH3_LTCH
CH3_LTCH
R
0b
Channel 3 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
5
4
3
R
R
R
R
0b
0b
0b
0b
Channel 3 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
Channel 3 IN3P short to ground fault status (self-clearing bit).
0d = IN3P no short to ground detected
1d = IN3P short to ground detected
Channel 3 IN3M short to ground fault status (self-clearing bit).
0d = IN3M no short to ground detected
1d = IN3M short to ground detected
Channel 3 IN3P short to MICBIAS fault status (self-clearing bit).
0d = IN3P no short to MICBIAS detected
1d = IN3P short to MICBIAS detected
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表8-88. CH3_LTCH Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
CH3_LTCH
R
0b
Channel 3 IN3M short to MICBIAS fault status (self-clearing bit).
0d = IN3M no short to MICBIAS detected
1d = IN3M short to MICBIAS detected
1
0
CH3_LTCH
CH3_LTCH
R
R
0b
0b
Channel 3 IN3P short to VBAT_IN fault status (self-clearing bit).
0d = IN3P no short to VBAT_IN detected
1d = IN3P short to VBAT_IN detected
Channel 3 IN3M short to VBAT_IN fault status (self-clearing bit - This
bit gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN3M no short to VBAT_IN detected
1d = IN3M short to VBAT_IN detected
8.6.1.2.37 CH4_LTCH Register (Address = 0x31) [Reset = 0x0]
CH4_LTCH is shown in 图8-113 and described in 表8-89.
Return to the 表8-52.
This register is the latched Interrupt status register for channel 4 fault diagnostic.
图8-113. CH4_LTCH Register
7
6
5
4
3
2
1
0
CH4_LTCH
R-0b
CH4_LTCH
R-0b
CH4_LTCH
R-0b
CH4_LTCH
R-0b
CH4_LTCH
R-0b
CH4_LTCH
R-0b
CH4_LTCH
R-0b
CH4_LTCH
R-0b
表8-89. CH4_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH4_LTCH
CH4_LTCH
CH4_LTCH
CH4_LTCH
CH4_LTCH
CH4_LTCH
CH4_LTCH
CH4_LTCH
R
0b
Channel 4 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
Channel 4 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
Channel 4 IN4P short to ground fault status (self-clearing bit).
0d = IN4P no short to ground detected
1d = IN4P short to ground detected
Channel 4 IN4M short to ground fault status (self-clearing bit).
0d = IN4M no short to ground detected
1d = IN4M short to ground detected
Channel 4 IN4P short to MICBIAS fault status (self-clearing bit).
0d = IN4P no short to MICBIAS detected
1d = IN4P short to MICBIAS detected
Channel 4 IN4M short to MICBIAS fault status (self-clearing bit).
0d = IN4M no short to MICBIAS detected
1d = IN4M short to MICBIAS detected
Channel 4 IN4P short to VBAT_IN fault status (self-clearing bit).
0d = IN4P no short to VBAT_IN detected
1d = IN4P short to VBAT_IN detected
Channel 4 IN4M short to VBAT_IN fault status (self-clearing bit - This
bit gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN4M no short to VBAT_IN detected
1d = IN4M short to VBAT_IN detected
8.6.1.2.38 INT_MASK3 Register (Address = 0x34) [Reset = 0x0]
INT_MASK3 is shown in 图8-114 and described in 表8-90.
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Return to the 表8-52.
This register is the interrupt masks register 3.
图8-114. INT_MASK3 Register
7
6
5
4
3
2
1
0
INT_MASK3
R/W-0b
INT_MASK3
R/W-0b
INT_MASK3
R/W-0b
INT_MASK3
R/W-0b
INT_MASK3
R/W-0b
RESERVED
R-000b
表8-90. INT_MASK3 Register Field Descriptions
Bit
Field
INT_MASK3
Type
Reset
Description
7
R/W
0b
INxP over voltage fault mask.
0d = Unmask
1d = Mask
6
5
INT_MASK3
INT_MASK3
INT_MASK3
INT_MASK3
RESERVED
R/W
R/W
R/W
R/W
R
0b
INxM over voltage fault mask.
0d = Unmask
1d = Mask
0b
MICBIAS high current fault mask.
0d = Unmask
1d = Mask
4
0b
MICBIAS low current fault mask.
0d = Unmask
1d = Mask
3
0b
MICBIAS over voltage fault mask.
0d = Unmask
1d = Mask
2-0
000b
Reserved bits; Write only reset value
8.6.1.2.39 INT_LTCH1 Register (Address = 0x35) [Reset = 0x0]
INT_LTCH1 is shown in 图8-115 and described in 表8-91.
Return to the 表8-52.
This register is the latched Interrupt readback register 1.
图8-115. INT_LTCH1 Register
7
6
5
4
3
2
1
0
INT_LTCH1
R-0b
INT_LTCH1
R-0b
INT_LTCH1
R-0b
INT_LTCH1
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-00b
表8-91. INT_LTCH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH1
INT_LTCH1
INT_LTCH1
R
0b
Channel 1 IN1P over voltage fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-46d, CH1_LTCH register).
0d = No IN1P over voltage fault detected
1d = IN1P over voltage fault has detected
6
5
R
R
0b
0b
Channel 2 IN2P over voltage fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-47d, CH2_LTCH register).
0d = No IN2P over voltage fault detected
1d = IN2P over voltage fault has detected
Channel 3 IN3P over voltage fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-48d, CH3_LTCH register).
0d = No IN3P over voltage fault detected
1d = IN3P over voltage fault has detected
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表8-91. INT_LTCH1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
INT_LTCH1
R
0b
Channel 4 IN4P over voltage fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-49d, CH4_LTCH register).
0d = No IN4P over voltage fault detected
1d = IN4P over voltage fault has detected
3
2
RESERVED
RESERVED
RESERVED
R
R
R
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bits; Write only reset value
0b
1-0
00b
8.6.1.2.40 INT_LTCH2 Register (Address = 0x36) [Reset = 0x0]
INT_LTCH2 is shown in 图8-116 and described in 表8-92.
Return to the 表8-52.
This register is the latched Interrupt readback register 2.
图8-116. INT_LTCH2 Register
7
6
5
4
3
2
1
0
INT_LTCH2
R-0b
INT_LTCH2
R-0b
INT_LTCH2
R-0b
INT_LTCH2
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-00b
表8-92. INT_LTCH2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH2
INT_LTCH2
INT_LTCH2
INT_LTCH2
R
0b
Channel 1 IN1M over voltage fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-46d, CH1_LTCH register).
0d = No IN1M over voltage fault detected
1d = IN1M over voltage fault has detected
6
5
4
R
R
R
0b
0b
0b
Channel 2 IN2M over voltage fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-47d, CH2_LTCH register).
0d = No IN2M over voltage fault detected
1d = IN2M over voltage fault has detected
Channel 3 IN3M over voltage fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-48d, CH3_LTCH register).
0d = No IN3M over voltage fault detected
1d = IN3M over voltage fault has detected
Channel 4 IN4M over voltage fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-49d, CH4_LTCH register).
0d = No IN4M over voltage fault detected
1d = IN4M over voltage fault has detected
3
2
RESERVED
RESERVED
RESERVED
R
R
R
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bits; Write only reset value
0b
1-0
00b
8.6.1.2.41 INT_LTCH3 Register (Address = 0x37) [Reset = 0x0]
INT_LTCH3 is shown in 图8-117 and described in 表8-93.
Return to the 表8-52.
This register is the latched Interrupt readback register 3.
图8-117. INT_LTCH3 Register
7
6
5
4
3
2
1
0
INT_LTCH3
INT_LTCH3
INT_LTCH3
RESERVED
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图8-117. INT_LTCH3 Register (continued)
R-0b
R-0b
R-0b
R-00000b
表8-93. INT_LTCH3 Register Field Descriptions
Bit
Field
INT_LTCH3
Type
Reset
Description
7
R
0b
Fault status for MICBIAS high current (self-clearing bit).
0d = No fault detected
1d = Fault detected
6
5
INT_LTCH3
INT_LTCH3
RESERVED
R
R
R
0b
Fault status for MICBIAS low current (self-clearing bit)
0d = No fault detected
1d = Fault detected
0b
Fault status for MICBIAS over voltage (self-clearing bit).
0d = No fault detected
1d = Fault detected
4-0
00000b
Reserved bits; Write only reset value
8.6.1.2.42 MBDIAG_CFG0 Register (Address = 0x38) [Reset = 0xBA]
MBDIAG_CFG0 is shown in 图8-118 and described in 表8-94.
Return to the 表8-52.
This register is the MICBIAS diagnostic configuration register 0.
图8-118. MBDIAG_CFG0 Register
7
6
5
4
3
2
1
0
MBIAS_HIGH_CURR_THRS[7:0]
R/W-10111010b
表8-94. MBDIAG_CFG0 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
MBIAS_HIGH_CURR_TH R/W
RS[7:0]
10111010b Threshold for MICBIAS high load current fault diagnostic.
0d to 56d = Reserved
57d = High load current threshold is set as 0 mA (typ)
58d = High load current threshold is set as 0.54 mA (typ)
59d = High load current threshold is set as 1.08 mA (typ)
60d to 185d = High load current threshold is set as per configuration
186d = High load current threshold is set as 69.66 mA (typ)
187d to 241d = High load current threshold is set as per
configuration
242d = High load current threshold is set as 99.90 mA (typ)
243d to 255d = Reserved
8.6.1.2.43 MBDIAG_CFG1 Register (Address = 0x39) [Reset = 0x4B]
MBDIAG_CFG1 is shown in 图8-119 and described in 表8-95.
Return to the 表8-52.
This register is the MICBIAS diagnostic configuration register 1.
图8-119. MBDIAG_CFG1 Register
7
6
5
4
3
2
1
0
MBIAS_LOW_CURR_THRS[7:0]
R/W-01001011b
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表8-95. MBDIAG_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
MBIAS_LOW_CURR_TH R/W
RS[7:0]
01001011b Threshold for MICBIAS low load current fault diagnostic.
0d to 56d = Reserved
57d = Low load current threshold is set as 0 mA (typ)
58d = Low load current threshold is set as 0.54 mA (typ)
59d = Low load current threshold is set as 1.08 mA (typ)
60d to 74d = Low load current threshold is set as per configuration
75d = Low load current threshold is set as 9.72 mA (typ)
76d to 241d = Low load current threshold is set as per configuration
242d = Low load current threshold is set as 99.90 mA (typ)
243d to 255d = Reserved
8.6.1.2.44 MBDIAG_CFG2 Register (Address = 0x3A) [Reset = 0x10]
MBDIAG_CFG2 is shown in 图8-120 and described in 表8-96.
Return to the 表8-52.
This register is the MICBIAS diagnostic configuration register 2.
图8-120. MBDIAG_CFG2 Register
7
6
5
4
3
2
1
0
PD_MBIAS_FA PD_MBIAS_FA PD_MBIAS_FA PD_MBIAS_FA
RESERVED
RESERVED
ULT1
ULT2
ULT3
ULT4
R/W-0b
R/W-0b
R/W-0b
R/W-1b
R/W-0b
R-000b
表8-96. MBDIAG_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PD_MBIAS_FAULT1
PD_MBIAS_FAULT2
PD_MBIAS_FAULT3
PD_MBIAS_FAULT4
R/W
0b
Powerdown configuration of MICBIAS fault 1
0d = No powerdown when MICBIAS fault detected
1d = MICBIAS and all ADC channels gets powerdown when low
current fault occurs and P0_R40, PD_ON_FLT_CFG = 1d
1d = MICBIAS and all ADC channels gets powerdown when high
current fault occurs and P0_R40, PD_ON_FLT_CFG = 2d
6
5
4
R/W
R/W
R/W
0b
0b
1b
Powerdown configuration of MICBIAS fault 2
0d = No powerdown when MICBIAS fault detected
1d = MICBIAS and all ADC channels gets powerdown when over
voltage fault occurs and P0_R40, PD_ON_FLT_CFG = 1d
1d = MICBIAS and all ADC channels gets powerdown when low
current fault occurs and P0_R40, PD_ON_FLT_CFG = 2d
Powerdown configuration of MICBIAS fault 3
0d = No powerdown when MICBIAS fault detected
1d = MICBIAS and all ADC channels gets powerdown when over
temperature fault occurs and P0_R40, PD_ON_FLT_CFG = 1d
1d = MICBIAS and all ADC channels gets powerdown when over
voltage fault occurs and P0_R40, PD_ON_FLT_CFG = 2d
Powerdown configuration of MICBIAS fault 4
0d = No powerdown when MICBIAS fault detected
1d = MICBIAS and all ADC channels gets powerdown when high
current fault occurs and P0_R40, PD_ON_FLT_CFG = 1d
1d = MICBIAS and all ADC channels gets powerdown when over
temperature fault occurs and P0_R40, PD_ON_FLT_CFG = 2d. It is
recommended to use this setting to protect chip from over
temperature fault.
3
RESERVED
RESERVED
R/W
R
0b
Reserved bit; Write only reset value
Reserved bits; Write only reset value
2-0
000b
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8.6.1.2.45 BIAS_CFG Register (Address = 0x3B) [Reset = 0xD0]
BIAS_CFG is shown in 图8-121 and described in 表8-97.
Return to the 表8-52.
This register is the MICBIAS configuration register.
图8-121. BIAS_CFG Register
7
6
5
4
3
2
1
0
MBIAS_VAL[3:0]
R/W-1101b
RESERVED
R-00b
RESERVED
R/W-00b
表8-97. BIAS_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
MBIAS_VAL[3:0]
R/W
1101b
MICBIAS value.
Dont use
Dont use
Dont use
Dont use
Dont use
Dont use
Dont use
7d = Microphone bias is set to 5 V
8d = Microphone bias is set to 5.5 V
9d = Microphone bias is set to 6 V
10d = Microphone bias is set to 6.5 V
11d = Microphone bias is set to 7 V
12d = Microphone bias is set to 7.5 V
13d = Microphone bias is set to 8 V
14d = Microphone bias is set to 8.5 V
15d = Microphone bias is set to 9 V
3-2
1-0
RESERVED
RESERVED
R
00b
00b
Reserved bits; Write only reset value
Reserved bits; Write only reset values
R/W
8.6.1.2.46 CH1_CFG0 Register (Address = 0x3C) [Reset = 0x10]
CH1_CFG0 is shown in 图8-122 and described in 表8-98.
Return to the 表8-52.
This register is configuration register 0 for channel 1.
图8-122. CH1_CFG0 Register
7
6
5
4
3
2
1
0
CH1_INTYP
CH1_INSRC[1:0]
CH1_DC
CH1_MIC_IN_R
ANGE
CH1_PGA_CFG[1:0]
CH1_AGCEN
R/W-0b
R/W-00b
R/W-1b
R/W-0b
R/W-00b
R/W-0b
表8-98. CH1_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_INTYP
R/W
0b
Channel 1 input type.
0d = Microphone input
1d = Line input
6-5
CH1_INSRC[1:0]
R/W
00b
Channel 1 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
3d = Reserved
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表8-98. CH1_CFG0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
CH1_DC
R/W
1b
Channel 1 input coupling.
0d = AC-coupled input
1d = DC-coupled input
3
CH1_MIC_IN_RANGE
R/W
0b
Channel 1 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-
VRMS supported provided DC differential common mode voltage
IN1P - IN1M < 4.2 V. Single-ended AC signal 1-VRMS supported
provided DC common mode voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up
to 14.14 V or single ended 7.07 V supported. User rquired to adjust
the channel gain and digital volume control based on the max signal
level used in system.
2-1
0
CH1_PGA_CFG[1:0]
CH1_AGCEN
R/W
R/W
00b
0b
Channel 1 CMRR Configuration.
0d = High SNR performance mode
Dont use
2d = High CMRR performance mode
3d = Reserved
Channel 1 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
8.6.1.2.47 CH1_CFG1 Register (Address = 0x3D) [Reset = 0x0]
CH1_CFG1 is shown in 图8-123 and described in 表8-99.
Return to the 表8-52.
This register is configuration register 1 for channel 1.
图8-123. CH1_CFG1 Register
7
6
5
4
3
2
1
0
CH1_GAIN[5:0]
R/W-000000b
RESERVED
R/W-0b
RESERVED
R-0b
表8-99. CH1_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH1_GAIN[5:0]
R/W
000000b
Channel 1 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
0
RESERVED
RESERVED
R/W
R
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.1.2.48 CH1_CFG2 Register (Address = 0x3E) [Reset = 0xC9]
CH1_CFG2 is shown in 图8-124 and described in 表8-100.
Return to the 表8-52.
This register is configuration register 2 for channel 1.
图8-124. CH1_CFG2 Register
7
6
5
4
3
2
1
0
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图8-124. CH1_CFG2 Register (continued)
CH1_DVOL[7:0]
R/W-11001001b
表8-100. CH1_CFG2 Register Field Descriptions
Bit
Field
CH1_DVOL[7:0]
Type
Reset
Description
7-0
R/W
11001001b Channel 1 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.2.49 CH1_CFG3 Register (Address = 0x3F) [Reset = 0x80]
CH1_CFG3 is shown in 图8-125 and described in 表8-101.
Return to the 表8-52.
This register is configuration register 3 for channel 1.
图8-125. CH1_CFG3 Register
7
6
5
4
3
2
1
0
CH1_GCAL[3:0]
R/W-1000b
RESERVED
R-0000b
表8-101. CH1_CFG3 Register Field Descriptions
Bit
7-4
Field
CH1_GCAL[3:0]
Type
Reset
Description
R/W
1000b
Channel 1 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.50 CH1_CFG4 Register (Address = 0x40) [Reset = 0x0]
CH1_CFG4 is shown in 图8-126 and described in 表8-102.
Return to the 表8-52.
This register is configuration register 4 for channel 1.
图8-126. CH1_CFG4 Register
7
6
5
4
3
2
1
0
CH1_PCAL[7:0]
R/W-00000000b
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表8-102. CH1_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH1_PCAL[7:0]
R/W
00000000b Channel 1 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.1.2.51 CH2_CFG0 Register (Address = 0x41) [Reset = 0x10]
CH2_CFG0 is shown in 图8-127 and described in 表8-103.
Return to the 表8-52.
This register is configuration register 0 for channel 2.
图8-127. CH2_CFG0 Register
7
6
5
4
3
2
1
0
CH2_INTYP
CH2_INSRC[1:0]
CH2_DC
CH2_MIC_IN_R
ANGE
CH2_PGA_CFG[1:0]
CH2_AGCEN
R/W-0b
R/W-00b
R/W-1b
R/W-0b
R/W-00b
R/W-0b
表8-103. CH2_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH2_INTYP
R/W
0b
Channel 2 input type.
0d = Microphone input
1d = Line input
6-5
CH2_INSRC[1:0]
R/W
00b
Channel 2 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
3d = Reserved
4
3
CH2_DC
R/W
R/W
1b
0b
Channel 2 input coupling.
0d = AC-coupled input
1d = DC-coupled input
CH2_MIC_IN_RANGE
Channel 2 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-
VRMS supported provided DC differential common mode voltage
IN1P - IN1M < 4.2 V. Single-ended AC signal 1-VRMS supported
provided DC common mode voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up
to 14.14 V or single ended 7.07 V supported. User rquired to adjust
the channel gain and digital volume control based on the max signal
level used in system.
2-1
0
CH2_PGA_CFG[1:0]
CH2_AGCEN
R/W
R/W
00b
0b
Channel 2 CMRR Configuration.
0d = High SNR performance mode
Dont use
2d = High CMRR performance mode
3d = Reserved
Channel 2 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
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8.6.1.2.52 CH2_CFG1 Register (Address = 0x42) [Reset = 0x0]
CH2_CFG1 is shown in 图8-128 and described in 表8-104.
Return to the 表8-52.
This register is configuration register 1 for channel 2.
图8-128. CH2_CFG1 Register
7
6
5
4
3
2
1
0
CH2_GAIN[5:0]
R/W-000000b
RESERVED
R/W-0b
RESERVED
R-0b
表8-104. CH2_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH2_GAIN[5:0]
R/W
000000b
Channel 2 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
0
RESERVED
RESERVED
R/W
R
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.1.2.53 CH2_CFG2 Register (Address = 0x43) [Reset = 0xC9]
CH2_CFG2 is shown in 图8-129 and described in 表8-105.
Return to the 表8-52.
This register is configuration register 2 for channel 2.
图8-129. CH2_CFG2 Register
7
6
5
4
3
2
1
0
CH2_DVOL[7:0]
R/W-11001001b
表8-105. CH2_CFG2 Register Field Descriptions
Bit
7-0
Field
CH2_DVOL[7:0]
Type
Reset
Description
R/W
11001001b Channel 2 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.2.54 CH2_CFG3 Register (Address = 0x44) [Reset = 0x80]
CH2_CFG3 is shown in 图8-130 and described in 表8-106.
Return to the 表8-52.
This register is configuration register 3 for channel 2.
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图8-130. CH2_CFG3 Register
7
6
5
4
3
2
1
0
CH2_GCAL[3:0]
R/W-1000b
RESERVED
R-0000b
表8-106. CH2_CFG3 Register Field Descriptions
Bit
7-4
Field
CH2_GCAL[3:0]
Type
Reset
Description
R/W
1000b
Channel 2 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.55 CH2_CFG4 Register (Address = 0x45) [Reset = 0x0]
CH2_CFG4 is shown in 图8-131 and described in 表8-107.
Return to the 表8-52.
This register is configuration register 4 for channel 2.
图8-131. CH2_CFG4 Register
7
6
5
4
3
2
1
0
CH2_PCAL[7:0]
R/W-00000000b
表8-107. CH2_CFG4 Register Field Descriptions
Bit
7-0
Field
CH2_PCAL[7:0]
Type
Reset
Description
R/W
00000000b Channel 2 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.1.2.56 CH3_CFG0 Register (Address = 0x46) [Reset = 0x10]
CH3_CFG0 is shown in 图8-132 and described in 表8-108.
Return to the 表8-52.
This register is configuration register 0 for channel 3.
图8-132. CH3_CFG0 Register
7
6
5
4
3
2
1
0
CH3_INTYP
CH3_INSRC[1:0]
CH3_DC
CH3_MIC_IN_R
ANGE
CH3_PGA_CFG[1:0]
CH3_AGCEN
R/W-0b
R/W-00b
R/W-1b
R/W-0b
R/W-00b
R/W-0b
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图8-132. CH3_CFG0 Register (continued)
表8-108. CH3_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH3_INTYP
R/W
0b
Channel 3 input type.
0d = Microphone input
1d = Line input
6-5
CH3_INSRC[1:0]
R/W
00b
Channel 3 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
3d = Reserved
4
3
CH3_DC
R/W
R/W
1b
0b
Channel 3 input coupling.
0d = AC-coupled input
1d = DC-coupled input
CH3_MIC_IN_RANGE
Channel 3 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-
VRMS supported provided DC differential common mode voltage
IN1P - IN1M < 4.2 V. Single-ended AC signal 1-VRMS supported
provided DC common mode voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up
to 14.14 V or single ended 7.07 V supported. User rquired to adjust
the channel gain and digital volume control based on the max signal
level used in system.
2-1
0
CH3_PGA_CFG[1:0]
CH3_AGCEN
R/W
R/W
00b
0b
Channel 3 CMRR Configuration.
0d = High SNR performance mode
Dont use
2d = High CMRR performance mode
3d = Reserved
Channel 3 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
8.6.1.2.57 CH3_CFG1 Register (Address = 0x47) [Reset = 0x0]
CH3_CFG1 is shown in 图8-133 and described in 表8-109.
Return to the 表8-52.
This register is configuration register 1 for channel 3.
图8-133. CH3_CFG1 Register
7
6
5
4
3
2
1
0
CH3_GAIN[5:0]
R/W-000000b
RESERVED
R/W-0b
RESERVED
R-0b
表8-109. CH3_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH3_GAIN[5:0]
R/W
000000b
Channel 3 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
0
RESERVED
RESERVED
R/W
R
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
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8.6.1.2.58 CH3_CFG2 Register (Address = 0x48) [Reset = 0xC9]
CH3_CFG2 is shown in 图8-134 and described in 表8-110.
Return to the 表8-52.
This register is configuration register 2 for channel 3.
图8-134. CH3_CFG2 Register
7
6
5
4
3
2
1
0
CH3_DVOL[7:0]
R/W-11001001b
表8-110. CH3_CFG2 Register Field Descriptions
Bit
7-0
Field
CH3_DVOL[7:0]
Type
Reset
Description
R/W
11001001b Channel 3 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.2.59 CH3_CFG3 Register (Address = 0x49) [Reset = 0x80]
CH3_CFG3 is shown in 图8-135 and described in 表8-111.
Return to the 表8-52.
This register is configuration register 3 for channel 3.
图8-135. CH3_CFG3 Register
7
6
5
4
3
2
1
0
CH3_GCAL[3:0]
R/W-1000b
RESERVED
R-0000b
表8-111. CH3_CFG3 Register Field Descriptions
Bit
7-4
Field
CH3_GCAL[3:0]
Type
Reset
Description
R/W
1000b
Channel 3 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.60 CH3_CFG4 Register (Address = 0x4A) [Reset = 0x0]
CH3_CFG4 is shown in 图8-136 and described in 表8-112.
Return to the 表8-52.
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This register is configuration register 4 for channel 3.
图8-136. CH3_CFG4 Register
7
6
5
4
3
2
1
0
CH3_PCAL[7:0]
R/W-00000000b
表8-112. CH3_CFG4 Register Field Descriptions
Bit
7-0
Field
CH3_PCAL[7:0]
Type
Reset
Description
R/W
00000000b Channel 3 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.1.2.61 CH4_CFG0 Register (Address = 0x4B) [Reset = 0x10]
CH4_CFG0 is shown in 图8-137 and described in 表8-113.
Return to the 表8-52.
This register is configuration register 0 for channel 4.
图8-137. CH4_CFG0 Register
7
6
5
4
3
2
1
0
CH4_INTYP
CH4_INSRC[1:0]
CH4_DC
CH4_MIC_IN_R
ANGE
CH4_PGA_CFG[1:0]
CH4_AGCEN
R/W-0b
R/W-00b
R/W-1b
R/W-0b
R/W-00b
R/W-0b
表8-113. CH4_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH4_INTYP
R/W
0b
Channel 4 input type.
0d = Microphone input
1d = Line input
6-5
CH4_INSRC[1:0]
R/W
00b
Channel 4 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
3d = Reserved
4
3
CH4_DC
R/W
R/W
1b
0b
Channel 4 input coupling.
0d = AC-coupled input
1d = DC-coupled input
CH4_MIC_IN_RANGE
Channel 4 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-
VRMS supported provided DC differential common mode voltage
IN1P - IN1M < 4.2 V. Single-ended AC signal 1-VRMS supported
provided DC common mode voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up
to 14.14 V or single ended 7.07 V supported. User rquired to adjust
the channel gain and digital volume control based on the max signal
level used in system.
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表8-113. CH4_CFG0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-1
CH4_PGA_CFG[1:0]
R/W
00b
Channel 4 CMRR Configuration.
0d = High SNR performance mode
Dont use
2d = High CMRR performance mode
3d = Reserved
0
CH4_AGCEN
R/W
0b
Channel 4 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
8.6.1.2.62 CH4_CFG1 Register (Address = 0x4C) [Reset = 0x0]
CH4_CFG1 is shown in 图8-138 and described in 表8-114.
Return to the 表8-52.
This register is configuration register 1 for channel 4.
图8-138. CH4_CFG1 Register
7
6
5
4
3
2
1
0
CH4_GAIN[5:0]
R/W-000000b
RESERVED
R/W-0b
RESERVED
R-0b
表8-114. CH4_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH4_GAIN[5:0]
R/W
000000b
Channel 4 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
0
RESERVED
RESERVED
R/W
R
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.1.2.63 CH4_CFG2 Register (Address = 0x4D) [Reset = 0xC9]
CH4_CFG2 is shown in 图8-139 and described in 表8-115.
Return to the 表8-52.
This register is configuration register 2 for channel 4.
图8-139. CH4_CFG2 Register
7
6
5
4
3
2
1
0
CH4_DVOL[7:0]
R/W-11001001b
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表8-115. CH4_CFG2 Register Field Descriptions
Bit
Field
CH4_DVOL[7:0]
Type
Reset
Description
7-0
R/W
11001001b Channel 4 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.2.64 CH4_CFG3 Register (Address = 0x4E) [Reset = 0x80]
CH4_CFG3 is shown in 图8-140 and described in 表8-116.
Return to the 表8-52.
This register is configuration register 3 for channel 4.
图8-140. CH4_CFG3 Register
7
6
5
4
3
2
1
0
CH4_GCAL[3:0]
R/W-1000b
RESERVED
R-0000b
表8-116. CH4_CFG3 Register Field Descriptions
Bit
7-4
Field
CH4_GCAL[3:0]
Type
Reset
Description
R/W
1000b
Channel 4 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.65 CH4_CFG4 Register (Address = 0x4F) [Reset = 0x0]
CH4_CFG4 is shown in 图8-141 and described in 表8-117.
Return to the 表8-52.
This register is configuration register 4 for channel 4.
图8-141. CH4_CFG4 Register
7
6
5
4
3
2
1
0
CH4_PCAL[7:0]
R/W-00000000b
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表8-117. CH4_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH4_PCAL[7:0]
R/W
00000000b Channel 4 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.1.2.66 CH5_CFG0 Register (Address = 0x50) [Reset = 0x10]
CH5_CFG0 is shown in 图8-142 and described in 表8-118.
Return to the 表8-52.
This register is configuration register 0 for channel 5.
图8-142. CH5_CFG0 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
CH5_INSRC[1:0]
R/W-00b
RESERVED
R/W-1b
RESERVED
R/W-0b
RESERVED
R/W-00b
RESERVED
R/W-0b
表8-118. CH5_CFG0 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
0b
Reserved bit; Write only reset value
6-5
CH5_INSRC[1:0]
00b
Channel 5 input configuration.
0d = Reserved
1d = Reserved
2d = Digital microphone PDM input (Configure GPIO's/GPI's pin
accordingly for PDMDIN1 and PDMCLK)
3d = Channel-5 digital filter input is generated same as channel 1
digital filter input (cloned input mode)
4
3
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R/W
1b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bits; Write only reset values
Reserved bit; Write only reset value
0b
2-1
0
00b
0b
8.6.1.2.67 CH5_CFG2 Register (Address = 0x52) [Reset = 0xC9]
CH5_CFG2 is shown in 图8-143 and described in 表8-119.
Return to the 表8-52.
This register is configuration register 2 for channel 5.
图8-143. CH5_CFG2 Register
7
6
5
4
3
2
1
0
CH5_DVOL[7:0]
R/W-11001001b
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表8-119. CH5_CFG2 Register Field Descriptions
Bit
Field
CH5_DVOL[7:0]
Type
Reset
Description
7-0
R/W
11001001b Channel 5 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.2.68 CH5_CFG3 Register (Address = 0x53) [Reset = 0x80]
CH5_CFG3 is shown in 图8-144 and described in 表8-120.
Return to the 表8-52.
This register is configuration register 3 for channel 5.
图8-144. CH5_CFG3 Register
7
6
5
4
3
2
1
0
CH5_GCAL[3:0]
R/W-1000b
RESERVED
R-0000b
表8-120. CH5_CFG3 Register Field Descriptions
Bit
7-4
Field
CH5_GCAL[3:0]
Type
Reset
Description
R/W
1000b
Channel 5 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.69 CH5_CFG4 Register (Address = 0x54) [Reset = 0x0]
CH5_CFG4 is shown in 图8-145 and described in 表8-121.
Return to the 表8-52.
This register is configuration register 4 for channel 5.
图8-145. CH5_CFG4 Register
7
6
5
4
3
2
1
0
CH5_PCAL[7:0]
R/W-00000000b
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表8-121. CH5_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH5_PCAL[7:0]
R/W
00000000b Channel 5 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.1.2.70 CH6_CFG0 Register (Address = 0x55) [Reset = 0x10]
CH6_CFG0 is shown in 图8-146 and described in 表8-122.
Return to the 表8-52.
This register is configuration register 0 for channel 6.
图8-146. CH6_CFG0 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
CH6_INSRC[1:0]
R/W-00b
RESERVED
R/W-1b
RESERVED
R/W-0b
RESERVED
R/W-00b
RESERVED
R/W-0b
表8-122. CH6_CFG0 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
0b
Reserved bit; Write only reset value
6-5
CH6_INSRC[1:0]
00b
Channel 6 input configuration.
0d = Reserved
1d = Reserved
2d = Digital microphone PDM input (Configure GPIO's/GPI's pin
accordingly for PDMDIN1 and PDMCLK)
3d = Channel-5 digital filter input is generated same as channel 1
digital filter input (cloned input mode)
4
3
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R/W
1b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bits; Write only reset values
Reserved bit; Write only reset value
0b
2-1
0
00b
0b
8.6.1.2.71 CH6_CFG2 Register (Address = 0x57) [Reset = 0xC9]
CH6_CFG2 is shown in 图8-147 and described in 表8-123.
Return to the 表8-52.
This register is configuration register 2 for channel 6.
图8-147. CH6_CFG2 Register
7
6
5
4
3
2
1
0
CH6_DVOL[7:0]
R/W-11001001b
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表8-123. CH6_CFG2 Register Field Descriptions
Bit
Field
CH6_DVOL[7:0]
Type
Reset
Description
7-0
R/W
11001001b Channel 6 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.2.72 CH6_CFG3 Register (Address = 0x58) [Reset = 0x80]
CH6_CFG3 is shown in 图8-148 and described in 表8-124.
Return to the 表8-52.
This register is configuration register 3 for channel 6.
图8-148. CH6_CFG3 Register
7
6
5
4
3
2
1
0
CH6_GCAL[3:0]
R/W-1000b
RESERVED
R-0000b
表8-124. CH6_CFG3 Register Field Descriptions
Bit
7-4
Field
CH6_GCAL[3:0]
Type
Reset
Description
R/W
1000b
Channel 6 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.73 CH6_CFG4 Register (Address = 0x59) [Reset = 0x0]
CH6_CFG4 is shown in 图8-149 and described in 表8-125.
Return to the 表8-52.
This register is configuration register 4 for channel 6.
图8-149. CH6_CFG4 Register
7
6
5
4
3
2
1
0
CH6_PCAL[7:0]
R/W-00000000b
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表8-125. CH6_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH6_PCAL[7:0]
R/W
00000000b Channel 6 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.1.2.74 CH7_CFG0 Register (Address = 0x5A) [Reset = 0x0]
CH7_CFG0 is shown in 图8-150 and described in 表8-126.
Return to the 表8-52.
This register is configuration register 0 for channel 7.
图8-150. CH7_CFG0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH7_INSRC[1:0]
R/W-00b
RESERVED
R-00000b
表8-126. CH7_CFG0 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R
0b
Reserved bit; Write only reset value
Channel-7 Input Configuration.
6-5
CH7_INSRC[1:0]
R/W
00b
0d = Digital Microphone PDM Input (Configure GPIO's/GPI's pin
accordingly for PDMDIN2 and PDMCLK)
1d = Digital Microphone PDM Input (Configure GPIO's/GPI's pin
accordingly for PDMDIN2 and PDMCLK)
2d = Digital Microphone PDM Input (Configure GPIO's/GPI's pin
accordingly for PDMDIN2 and PDMCLK)
3d = Channel-7 Digital Filter Input is generated same as Channel-3
Digital Filter Input (Cloned Input)
4-0
RESERVED
R
00000b
Reserved bits; Write only reset value
8.6.1.2.75 CH7_CFG2 Register (Address = 0x5C) [Reset = 0xC9]
CH7_CFG2 is shown in 图8-151 and described in 表8-127.
Return to the 表8-52.
This register is configuration register 2 for channel 7.
图8-151. CH7_CFG2 Register
7
6
5
4
3
2
1
0
CH7_DVOL[7:0]
R/W-11001001b
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表8-127. CH7_CFG2 Register Field Descriptions
Bit
Field
CH7_DVOL[7:0]
Type
Reset
Description
7-0
R/W
11001001b Channel-7 Digital Volume Control.
0d = Digtial Volume is Mute
1d = Digital Volume Control set to -100 dB
2d = Digital Volume Control set to -99.5 dB
3d to 200d = Digital Volume Control set to as per configuration
201d = Digital Volume Control set to 0 dB
202d = Digital Volume Control set to +0.5 dB
203d to 253d = Digital Volume Control set to as per configuration
254d = Digital Volume Control set to +26.5 dB
255d = Digital Volume Control set to +27 dB
8.6.1.2.76 CH7_CFG3 Register (Address = 0x5D) [Reset = 0x80]
CH7_CFG3 is shown in 图8-152 and described in 表8-128.
Return to the 表8-52.
This register is configuration register 3 for channel 7.
图8-152. CH7_CFG3 Register
7
6
5
4
3
2
1
0
CH7_GCAL[3:0]
R/W-1000b
RESERVED
R-0000b
表8-128. CH7_CFG3 Register Field Descriptions
Bit
7-4
Field
CH7_GCAL[3:0]
Type
Reset
Description
R/W
1000b
Channel-7 Gain Calibration.
0d = Gain Calibration set to -0.8 dB
1d = Gain Calibration set to -0.7 dB
2d = Gain Calibration set to -0.6 dB
3d to 7d = Gain Calibration set to as per configuration
8d = Gain Calibration set to 0 dB
9d = Gain Calibration set to +0.1 dB
10d to 13d = Gain Calibration set to as per configuration
14d = Gain Calibration set to +0.6 dB
15d = Gain Calibration set to +0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.77 CH7_CFG4 Register (Address = 0x5E) [Reset = 0x0]
CH7_CFG4 is shown in 图8-153 and described in 表8-129.
Return to the 表8-52.
This register is configuration register 4 for channel 7.
图8-153. CH7_CFG4 Register
7
6
5
4
3
2
1
0
CH7_PCAL[7:0]
R/W-00000000b
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表8-129. CH7_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH7_PCAL[7:0]
R/W
00000000b Channel-7 Phase Calibration with modulator clock resolution.
0d = Phase Calibration with 0-cycle of modulator clock delay
1d = Phase Calibration with 1-cycles of modulator clock delay
2d = Phase Calibration with 1-cycles of modulator clock delay
3d to 254d = Delay Value is as per configuration
255d = Phase Calibration with 255-cycles of modulator clock delay
8.6.1.2.78 CH8_CFG0 Register (Address = 0x5F) [Reset = 0x0]
CH8_CFG0 is shown in 图8-154 and described in 表8-130.
Return to the 表8-52.
This register is configuration register 0 for channel 8.
图8-154. CH8_CFG0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH8_INSRC[1:0]
R/W-00b
RESERVED
R-00000b
表8-130. CH8_CFG0 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R
0b
Reserved bit; Write only reset value
Channel-8 Input Configuration.
6-5
CH8_INSRC[1:0]
R/W
00b
0d = Digital Microphone PDM Input (Configure GPIO's/GPI's pin
accordingly for PDMDIN2 and PDMCLK)
1d = Digital Microphone PDM Input (Configure GPIO's/GPI's pin
accordingly for PDMDIN2 and PDMCLK)
2d = Digital Microphone PDM Input (Configure GPIO's/GPI's pin
accordingly for PDMDIN2 and PDMCLK)
3d = Channel-8 Digital Filter Input is generated same as Channel-4
Digital Filter Input (Cloned Input)
4-0
RESERVED
R
00000b
Reserved bits; Write only reset value
8.6.1.2.79 CH8_CFG2 Register (Address = 0x61) [Reset = 0xC9]
CH8_CFG2 is shown in 图8-155 and described in 表8-131.
Return to the 表8-52.
This register is configuration register 2 for channel 8.
图8-155. CH8_CFG2 Register
7
6
5
4
3
2
1
0
CH8_DVOL[7:0]
R/W-11001001b
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表8-131. CH8_CFG2 Register Field Descriptions
Bit
Field
CH8_DVOL[7:0]
Type
Reset
Description
7-0
R/W
11001001b Channel-8 Digital Volume Control.
0d = Digtial Volume is Mute
1d = Digital Volume Control set to -100 dB
2d = Digital Volume Control set to -99.5 dB
3d to 200d = Digital Volume Control set to as per configuration
201d = Digital Volume Control set to 0 dB
202d = Digital Volume Control set to +0.5 dB
203d to 253d = Digital Volume Control set to as per configuration
254d = Digital Volume Control set to +26.5 dB
255d = Digital Volume Control set to +27 dB
8.6.1.2.80 CH8_CFG3 Register (Address = 0x62) [Reset = 0x80]
CH8_CFG3 is shown in 图8-156 and described in 表8-132.
Return to the 表8-52.
This register is configuration register 3 for channel 8.
图8-156. CH8_CFG3 Register
7
6
5
4
3
2
1
0
CH8_GCAL[3:0]
R/W-1000b
RESERVED
R-0000b
表8-132. CH8_CFG3 Register Field Descriptions
Bit
7-4
Field
CH8_GCAL[3:0]
Type
Reset
Description
R/W
1000b
Channel-8 Gain Calibration.
0d = Gain Calibration set to -0.8 dB
1d = Gain Calibration set to -0.7 dB
2d = Gain Calibration set to -0.6 dB
3d to 7d = Gain Calibration set to as per configuration
8d = Gain Calibration set to 0 dB
9d = Gain Calibration set to +0.1 dB
10d to 13d = Gain Calibration set to as per configuration
14d = Gain Calibration set to +0.6 dB
15d = Gain Calibration set to +0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.1.2.81 CH8_CFG4 Register (Address = 0x63) [Reset = 0x0]
CH8_CFG4 is shown in 图8-157 and described in 表8-133.
Return to the 表8-52.
This register is configuration register 4 for channel 8.
图8-157. CH8_CFG4 Register
7
6
5
4
3
2
1
0
CH8_PCAL[7:0]
R/W-00000000b
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表8-133. CH8_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH8_PCAL[7:0]
R/W
00000000b Channel-8 Phase Calibration with modulator clock resolution.
0d = Phase Calibration with 0-cycle of modulator clock delay
1d = Phase Calibration with 1-cycles of modulator clock delay
2d = Phase Calibration with 1-cycles of modulator clock delay
3d to 254d = Delay Value is as per configuration
255d = Phase Calibration with 255-cycles of modulator clock delay
8.6.1.2.82 DIAG_CFG0 Register (Address = 0x64) [Reset = 0x0]
DIAG_CFG0 is shown in 图8-158 and described in 表8-134.
Return to the 表8-52.
This register is configuration register 0 for input fault diagnostics setting.
图8-158. DIAG_CFG0 Register
7
6
5
4
3
2
1
0
CH1_DIAG_EN CH2_DIAG_EN CH3_DIAG_EN CH4_DIAG_EN
RESERVED
RESERVED
INCL_SE_INM INCL_AC_COU
P
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-134. DIAG_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_DIAG_EN
CH2_DIAG_EN
CH3_DIAG_EN
CH4_DIAG_EN
R/W
0b
Channel 1 input (IN1P and IN1M) scan for diagnostics.
0d = Diagnostic disabled
1d = Diagnostic enabled
6
5
4
R/W
R/W
R/W
0b
0b
0b
Channel 2 input (IN2P and IN2M) scan for diagnostics.
0d = Diagnostic disabled
1d = Diagnostic enabled
Channel 3 input (IN3P and IN3M) scan for diagnostics.
0d = Diagnostic disabled
1d = Diagnostic enabled
Channel 4 input (IN4P and IN4M) scan for diagnostics.
0d = Diagnostic disabled
1d = Diagnostic enabled
3
2
1
RESERVED
RESERVED
INCL_SE_INM
R/W
R/W
R/W
0b
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
INxM pin diagnostics scan selection for single-ended configuration.
0d = INxM pins of single-ended channels are excluded for diagnosis
1d = INxM pins of single-ended channels are included for diagnosis
0
INCL_AC_COUP
R/W
0b
AC-coupled channels pins scan selection for diagnostics.
0d = INxP and INxM pins of AC-coupled channels are excluded for
diagnosis
1d = INxP and INxM pins of AC-coupled channels are included for
diagnosis
8.6.1.2.83 DIAG_CFG1 Register (Address = 0x65) [Reset = 0x37]
DIAG_CFG1 is shown in 图8-159 and described in 表8-135.
Return to the 表8-52.
This register is configuration register 1 for input fault diagnostics setting.
图8-159. DIAG_CFG1 Register
7
6
5
4
3
2
1
0
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图8-159. DIAG_CFG1 Register (continued)
DIAG_SHT_TERM[3:0]
DIAG_SHT_VBAT_IN[3:0]
R/W-0011b
R/W-0111b
表8-135. DIAG_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_SHT_TERM[3:0]
R/W
0011b
INxP and INxM terminal short detect threshold.
0d = INxP and INxM terminal short detect threshold value is 0 mV
(typ)
1d = INxP and INxM terminal short detect threshold value is 30 mV
(typ)
2d = INxP and INxM terminal short detect threshold value is 60 mV
(typ)
10d to 13d = INxP and INxM terminal short detect threshold value is
set as per configuration
14d = INxP and INxM terminal short detect threshold value is 420
mV (typ)
15d = INxP and INxM terminal short detect threshold value is 450
mV (typ)
3-0
DIAG_SHT_VBAT_IN[3:0] R/W
0111b
Short to VBAT_IN detect threshold.
0d = Short to VBAT_IN detect threshold value is 0 mV (typ)
1d = Short to VBAT_IN detect threshold value is 30 mV (typ)
2d = Short to VBAT_IN detect threshold value is 60 mV (typ)
10d to 13d = Short to VBAT_IN detect threshold value is set as per
configuration
14d = Short to VBAT_IN detect threshold value is 420 mV (typ)
15d = Short to VBAT_IN detect threshold value is 450 mV (typ)
8.6.1.2.84 DIAG_CFG2 Register (Address = 0x66) [Reset = 0x87]
DIAG_CFG2 is shown in 图8-160 and described in 表8-136.
Return to the 表8-52.
This register is configuration register 2 for input fault diagnostics setting.
图8-160. DIAG_CFG2 Register
7
6
5
4
3
2
1
0
DIAG_SHT_GND[3:0]
R/W-1000b
DIAG_SHT_MICBIAS[3:0]
R/W-0111b
表8-136. DIAG_CFG2 Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
DIAG_SHT_GND[3:0]
R/W
1000b
Short to ground detect threshold.
0d = Short to ground detect threshold value is 0 mV (typ)
1d = Short to ground detect threshold value is 60 mV (typ)
2d = Short to ground detect threshold value is 120 mV (typ)
10d to 13d = Short to ground detect threshold value is set as per
configuration
14d = Short to ground detect threshold value is 840 mV (typ)
15d = Short to ground detect threshold value is 900 mV (typ)
3-0
DIAG_SHT_MICBIAS[3:0] R/W
0111b
Short to MICBIAS detect threshold.
0d = Short to MICBIAS detect threshold value is 0 mV (typ)
1d = Short to MICBIAS detect threshold value is 30 mV (typ)
2d = Short to MICBIAS detect threshold value is 60 mV (typ)
10d to 13d = Short to MICBIAS detect threshold value is set as per
configuration
14d = Short to MICBIAS detect threshold value is 420 mV (typ)
15d = Short to MICBIAS detect threshold value is 450 mV (typ)
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8.6.1.2.85 DIAG_CFG3 Register (Address = 0x67) [Reset = 0xB8]
DIAG_CFG3 is shown in 图8-161 and described in 表8-137.
Return to the 表8-52.
This register is configuration register 3 for input fault diagnostics setting.
图8-161. DIAG_CFG3 Register
7
6
5
4
3
2
1
0
REP_RATE[1:0]
R/W-10b
RESERVED
R/W-11b
FAULT_DBNCE_SEL[1:0]
VSHORT_DBN DIAG_2X_THR
CE
ES
R/W-10b
R/W-0b
R/W-0b
表8-137. DIAG_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
REP_RATE[1:0]
R/W
10b
Fault monitoring scan repetition rate.
0d = Countinuos back to back scanning of selected channels input
pins without any idle time
1d = Fault monitoring repetition rate of 1 ms for selected channels
input pins scanning
2d = Fault monitoring repetition rate of 4 ms for selected channels
input pins scanning
3d = Fault monitoring repetition rate of 8 ms for selected channels
input pins scanning
5-4
3-2
RESERVED
R/W
11b
10b
Reserved bits; Write only reset values
FAULT_DBNCE_SEL[1:0] R/W
Debounce count for all the faults (except VBAT_IN short when
VBAT_IN < MICBIAS).
0d = 16 counts for debounce to filter-out any false faults detection
1d = 8 counts for debounce to filter-out any false faults detection
2d = 4 counts for debounce to filter-out any false faults detection
3d = No debounce count
1
0
VSHORT_DBNCE
DIAG_2X_THRES
R/W
R/W
0b
0b
VBAT_IN short debounce count only when VBAT_IN < MICBIAS.
0d = 16 counts for debounce to filter-out any false faults detection
1d = 8 counts for debounce to filter-out any false faults detection
Diagnostic thresholds range scale.
0d = Thresholds same as configured in P0_R101 and P0_R102
1d = All the configuration thresholds gets scale by 2 times
8.6.1.2.86 DIAG_CFG4 Register (Address = 0x68) [Reset = 0x0]
DIAG_CFG4 is shown in 图8-162 and described in 表8-138.
Return to the 表8-52.
This register is configuration register 4 for input fault diagnostics setting.
图8-162. DIAG_CFG4 Register
7
6
5
4
3
2
1
0
DIAG_MOV_AVG_CFG[1:0]
MOV_AVG_DIS MOV_AVG_DIS
_MBIAS_LOAD _TEMP_SENS
RESERVED
R-0000b
R/W-00b
R/W-0b
R/W-0b
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表8-138. DIAG_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
DIAG_MOV_AVG_CFG[1: R/W
0]
00b
Moving average configuration.
0d = Moving average disabled
1d = Moving average enabled with 0.5 weightage for old scanned
data and new scanned data
2d = Moving average enabled with 0.75 weightage for old scanned
data and 0.25 weightage for new scanned data
3d = Reserved
5
MOV_AVG_DIS_MBIAS_L R/W
OAD
0b
Moving average configuration for MICBIAS high and low load current
fault detection
0d = Moving average as defined by DIAG_MOV_AVG_CFG setting
1d = Moving average is forced disabled for MICBIAS load current
fault detection to achieve faster response time
4
MOV_AVG_DIS_TEMP_S R/W
ENS
0b
Moving average configuration for over temperature fault detection
0d = Moving average as defined by DIAG_MOV_AVG_CFG setting
1d = Moving average is forced disabled for over temperature fault
detection to achieve faster response time
3-0
RESERVED
R
0000b
Reserved bits; Write only reset values
8.6.1.2.87 BOOST_CFG Register (Address = 0x6A) [Reset = 0x0]
BOOST_CFG is shown in 图8-163 and described in 表8-139.
Return to the 表8-52.
This register is configuration register for boost setting.
图8-163. BOOST_CFG Register
7
6
5
4
3
2
1
0
BOOST_DIS
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R/W-0b
RESERVED
R-000b
表8-139. BOOST_CFG Register Field Descriptions
Bit
Field
BOOST_DIS
Type
Reset
Description
7
R/W
0b
Boost Enable/Disable
0d = Boost is enable
1d = Boost is disable/bypass
6
5
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R/W
R
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
0b
4
0b
3
0b
2-0
000b
Reserved bits; Write only reset values
8.6.1.2.88 DSP_CFG0 Register (Address = 0x6B) [Reset = 0x1]
DSP_CFG0 is shown in 图8-164 and described in 表8-140.
Return to the 表8-52.
This register is the digital signal processor (DSP) configuration register 0.
图8-164. DSP_CFG0 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
DECI_FILT[1:0]
R/W-00b
CH_SUM[1:0]
R/W-00b
HPF_SEL[1:0]
R/W-01b
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图8-164. DSP_CFG0 Register (continued)
表8-140. DSP_CFG0 Register Field Descriptions
Bit
7-6
5-4
Field
Type
Reset
Description
RESERVED
DECI_FILT[1:0]
R
00b
Reserved bits; Write only reset value
R/W
00b
Decimation filter response.
0d = Linear phase
1d = Low latency
2d = Ultra-low latency
Dont use
3-2
1-0
CH_SUM[1:0]
HPF_SEL[1:0]
R/W
R/W
00b
01b
Channel summation mode for higher SNR
0d = Channel summation mode is disabled
1d = 2-channel summation mode is enabled to generate a (CH1 +
CH2) / 2 and a (CH3 + CH4) / 2 output
2d = 4-channel summation mode is enabled to generate a (CH1 +
CH2 + CH3 + CH4) / 4 output
3d = Reserved
High-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default
coefficient values in P4_R72 to P4_R83 set as the all-pass filter
1d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is
selected
2d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected
3d = HPF with a cutoff of 0.008 x fS (384 Hz at fS = 48 kHz) is
selected
8.6.1.2.89 DSP_CFG1 Register (Address = 0x6C) [Reset = 0x48]
DSP_CFG1 is shown in 图8-165 and described in 表8-141.
Return to the 表8-52.
This register is the digital signal processor (DSP) configuration register 1.
图8-165. DSP_CFG1 Register
7
6
5
4
3
2
1
0
DVOL_GANG
BIQUAD_CFG[1:0]
DISABLE_SOF
T_STEP
AGC_SEL
RESERVED
RESERVED
R-00b
R/W-0b
R/W-10b
R/W-0b
R/W-1b
R/W-0b
表8-141. DSP_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DVOL_GANG
R/W
0b
DVOL control ganged across channels.
0d = Each channel has its own DVOL CTRL settings as programmed
in the CHx_DVOL bits
1d = All active channels must use the channel 1 DVOL setting
(CH1_DVOL) irrespective of whether channel 1 is turned on or not
6-5
BIQUAD_CFG[1:0]
R/W
10b
Number of biquads per channel configuration.
0d = No biquads per channel; biquads are all disabled
1d = 1 biquad per channel
2d = 2 biquads per channel
3d = 3 biquads per channel
4
3
DISABLE_SOFT_STEP
AGC_SEL
R/W
R/W
0b
1b
Soft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled
1d = Soft-stepping disabled
AGC master enable setting.
0d = Reserved; Write always 1 to this register bit
1d = AGC selected as configured for each channel using CHx_CFG0
register
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表8-141. DSP_CFG1 Register Field Descriptions (continued)
Bit
2
Field
Type
R/W
R
Reset
Description
RESERVED
RESERVED
0b
Reserved bit; Write only reset value
Reserved bits; Write only reset value
1-0
00b
8.6.1.2.90 AGC_CFG0 Register (Address = 0x70) [Reset = 0xE7]
AGC_CFG0 is shown in 图8-166 and described in 表8-142.
Return to the 表8-52.
This register is the automatic gain controller (AGC) configuration register 0.
图8-166. AGC_CFG0 Register
7
6
5
4
3
2
1
0
AGC_LVL[3:0]
R/W-1110b
AGC_MAXGAIN[3:0]
R/W-0111b
表8-142. AGC_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
AGC_LVL[3:0]
R/W
1110b
AGC output signal target level.
0d = Output signal target level is -6 dB
1d = Output signal target level is -8 dB
2d = Output signal target level is -10 dB
3d to 13d = Output signal target level is as per configuration
14d = Output signal target level is -34 dB
15d = Output signal target level is -36 dB
3-0
AGC_MAXGAIN[3:0]
R/W
0111b
AGC maximum gain allowed.
0d = Maximum gain allowed is 3 dB
1d = Maximum gain allowed is 6 dB
2d = Maximum gain allowed is 9 dB
3d to 11d = Maximum gain allowed is as per configuration
12d = Maximum gain allowed is 39 dB
13d = Maximum gain allowed is 42 dB
14d to 15d = Reserved
8.6.1.2.91 IN_CH_EN Register (Address = 0x73) [Reset = 0xFC]
IN_CH_EN is shown in 图8-167 and described in 表8-143.
Return to the 表8-52.
This register is the input channel enable configuration register.
图8-167. IN_CH_EN Register
7
6
5
4
3
2
1
0
IN_CH1_EN
R/W-1b
IN_CH2_EN
R/W-1b
IN_CH3_EN
R/W-1b
IN_CH4_EN
R/W-1b
IN_CH5_EN
R/W-1b
IN_CH6_EN
R/W-1b
IN_CH7_EN
R/W-0b
IN_CH8_EN
R/W-0b
表8-143. IN_CH_EN Register Field Descriptions
Bit
Field
IN_CH1_EN
Type
Reset
Description
7
R/W
1b
Input channel 1 enable setting.
0d = Channel 1 is disabled
1d = Channel 1 is enabled
6
IN_CH2_EN
R/W
1b
Input channel 2 enable setting.
0d = Channel 2 is disabled
1d = Channel 2 is enabled
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表8-143. IN_CH_EN Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
IN_CH3_EN
R/W
1b
Input channel 3 enable setting.
0d = Channel 3 is disabled
1d = Channel 3 is enabled
4
3
2
1
0
IN_CH4_EN
IN_CH5_EN
IN_CH6_EN
IN_CH7_EN
IN_CH8_EN
R/W
R/W
R/W
R/W
R/W
1b
1b
1b
0b
0b
Input channel 4 enable setting.
0d = Channel 4 is disabled
1d = Channel 4 is enabled
Input channel 5 (PDM only) enable setting.
0d = Channel 5 is disabled
1d = Channel 5 is enabled
Input channel 6 (PDM only) enable setting.
0d = Channel 6 is disabled
1d = Channel 6 is enabled
Input channel 7 (PDM only) enable setting.
0d = Channel 7 is disabled
1d = Channel 7 is enabled
Input channel 8 (PDM only) enable setting.
0d = Channel 8 is disabled
1d = Channel 8 is enabled
8.6.1.2.92 ASI_OUT_CH_EN Register (Address = 0x74) [Reset = 0x0]
ASI_OUT_CH_EN is shown in 图8-168 and described in 表8-144.
Return to the 表8-52.
This register is the ASI output channel enable configuration register.
图8-168. ASI_OUT_CH_EN Register
7
6
5
4
3
2
1
0
ASI_OUT_CH1 ASI_OUT_CH2 ASI_OUT_CH3 ASI_OUT_CH4 ASI_OUT_CH5 ASI_OUT_CH6 ASI_OUT_CH7 ASI_OUT_CH8
_EN
_EN
_EN
_EN
_EN
_EN
_EN
_EN
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-144. ASI_OUT_CH_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ASI_OUT_CH1_EN
ASI_OUT_CH2_EN
ASI_OUT_CH3_EN
ASI_OUT_CH4_EN
ASI_OUT_CH5_EN
ASI_OUT_CH6_EN
ASI_OUT_CH7_EN
R/W
0b
ASI output channel 1 enable setting.
0d = Channel 1 output slot is in a tri-state condition
1d = Channel 1 output slot is enabled
6
5
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
ASI output channel 2 enable setting.
0d = Channel 2 output slot is in a tri-state condition
1d = Channel 2 output slot is enabled
ASI output channel 3 enable setting.
0d = Channel 3 output slot is in a tri-state condition
1d = Channel 3 output slot is enabled
ASI output channel 4 enable setting.
0d = Channel 4 output slot is in a tri-state condition
1d = Channel 4 output slot is enabled
ASI output channel 5 enable setting.
0d = Channel 5 output slot is in a tri-state condition
1d = Channel 5 output slot is enabled
ASI output channel 6 enable setting.
0d = Channel 6 output slot is in a tri-state condition
1d = Channel 6 output slot is enabled
ASI output channel 7 enable setting.
0d = Channel 7 output slot is in a tri-state condition
1d = Channel 7 output slot is enabled
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表8-144. ASI_OUT_CH_EN Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
ASI_OUT_CH8_EN
R/W
0b
ASI output channel 8 enable setting.
0d = Channel 8 output slot is in a tri-state condition
1d = Channel 8 output slot is enabled
8.6.1.2.93 PWR_CFG Register (Address = 0x75) [Reset = 0x0]
PWR_CFG is shown in 图8-169 and described in 表8-145.
Return to the 表8-52.
This register is the power-up configuration register.
图8-169. PWR_CFG Register
7
6
5
4
3
2
1
0
MICBIAS_PDZ
ADC_PDZ
PLL_PDZ
DYN_CH_PUP
D_EN
DYN_MAXCH_SEL[1:0]
RESERVED
RESERVED
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-00b
R/W-0b
R-0b
表8-145. PWR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MICBIAS_PDZ
R/W
0b
Power control for MICBIAS.
0d = Power down MICBIAS
1d = Power up MICBIAS
6
5
4
ADC_PDZ
R/W
R/W
R/W
0b
0b
0b
Power control for ADC and PDM channels.
0d = Power down all ADC and PDM channels
1d = Power up all enabled ADC and PDM channels
PLL_PDZ
Power control for the PLL.
0d = Power down the PLL
1d = Power up the PLL
DYN_CH_PUPD_EN
Dynamic channel power-up, power-down enable.
0d = Channel power-up, power-down is not supported if any channel
recording is on
1d = Channel can be powered up or down individually, even if
channel recording is on. Do not powered-down channel 1 if this bit is
set to '1'
3-2
DYN_MAXCH_SEL[1:0]
R/W
00b
Dynamic mode maximum channel select configuration.
0d = Channel 1 and channel 2 are used with dynamic channel
power-up, power-down feature enabled
1d = Channel 1 to channel 4 are used with dynamic channel power-
up, power-down feature enabled
2d = Channel 1 to channel 6 are used with dynamic channel power-
up, power-down feature enabled
3d = Channel 1 to channel 8 are used with dynamic channel power-
up, power-down feature enabled
1
0
RESERVED
RESERVED
R/W
R
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.1.2.94 DEV_STS0 Register (Address = 0x76) [Reset = 0x0]
DEV_STS0 is shown in 图8-170 and described in 表8-146.
Return to the 表8-52.
This register is the device status value register 0.
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图8-170. DEV_STS0 Register
7
6
5
4
3
2
1
0
CH1_STATUS CH2_STATUS CH3_STATUS CH4_STATUS CH5_STATUS CH6_STATUS CH7_STATUS CH8_STATUS
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
表8-146. DEV_STS0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
2
1
0
CH1_STATUS
CH2_STATUS
CH3_STATUS
CH4_STATUS
CH5_STATUS
CH6_STATUS
CH7_STATUS
CH8_STATUS
R
0b
ADC channel 1 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
ADC channel 2 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
ADC channel 3 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
ADC channel 4 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
ADC channel 5 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
ADC channel 6 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
PDM channel 7 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
PDM channel 8 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
8.6.1.2.95 DEV_STS1 Register (Address = 0x77) [Reset = 0x80]
DEV_STS1 is shown in 图8-171 and described in 表8-147.
Return to the 表8-52.
This register is the device status value register 1.
图8-171. DEV_STS1 Register
7
6
5
4
3
2
1
0
MODE_STS[2:0]
BOOST_STS
MBIAS_STS
CHx_PD_FLT_ ALL_CHx_PD_ MAN_RCV_PD
STS
FLT_STS
R-0b
_FLT_CHK
R/W-0b
R-100b
R-0b
R-0b
R-0b
表8-147. DEV_STS1 Register Field Descriptions
Bit
7-5
Field
Type
Reset
Description
MODE_STS[2:0]
R
100b
Device mode status.
4d = Device is in sleep mode or software shutdown mode
6d = Device is in active mode with all ADC or PDM channels turned
off
7d = Device is in active mode with at least one ADC or PDM channel
turned on
4
BOOST_STS
R
0b
Boost power up status.
0d = Boost is powered down
1d = Boost is powered up
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表8-147. DEV_STS1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
MBIAS_STS
R
0b
MICBIAS power up status.
0d = MICBIAS is powered down
1d = MICBIAS is powered up
2
CHx_PD_FLT_STS
R
R
0b
ADC channel power down status caused by INxx inputs faults.
0d = No ADC channel is powered down caused by INxx inputs faults
1d = Atleast a ADC channel is powered down caused by INxx inputs
faults
1
0
ALL_CHx_PD_FLT_STS
0b
0b
ADC channel power down status caused by MICBIAS faults.
0d = No ADC channel is powered down caused by MICBIAS faults
1d = All ADC channels are powered down caused by MICBIAS faults
MAN_RCV_PD_FLT_CHK R/W
Manual recovery (self-clearing bit).
0d = No effect
1d = Recheck all fault status and re-powerup ADC channels and/or
MICBIAS if they do not have any faults. Before setting this bit, reset
P0_R58 register and re-configure P0_R58 to desired setting only
after manual recover gets over.
8.6.1.2.96 I2C_CKSUM Register (Address = 0x7E) [Reset = 0x0]
I2C_CKSUM is shown in 图8-172 and described in 表8-148.
Return to the 表8-52.
This register returns the I2C transactions checksum value
图8-172. I2C_CKSUM Register
7
6
5
4
3
2
1
0
I2C_CKSUM[7:0]
R/W-00000000b
表8-148. I2C_CKSUM Register Field Descriptions
Bit
7-0
Field
I2C_CKSUM[7:0]
Type
Reset
Description
R/W
00000000b These bits return the I2C transactions checksum value. Writing to this
register resets the checksum to the written value. This register is
updated on writes to other registers on all pages.
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8.6.1.3 Page 1 Registers
表8-149 lists the memory-mapped registers for the Page 1 registers. All register offset addresses not listed in 表
8-149 should be considered as reserved locations and the register contents should not be modified.
表8-149. PAGE 1 Registers
Address
0x0
Acronym
Register Name
Reset Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x40
0x00
0x00
0x00
0x00
0x01
0x00
0x02
0x00
0x03
0x00
0x04
0x00
0x05
0x00
0x06
0x00
0x07
0x00
0x08
0x00
0x09
0x00
0x0E
Section
PAGE_CFG
Device page register
节8.6.1.3.1
节8.6.1.3.2
节8.6.1.3.3
节8.6.1.3.4
节8.6.1.3.5
节8.6.1.3.6
节8.6.1.3.7
节8.6.1.3.8
节8.6.1.3.9
节8.6.1.3.10
节8.6.1.3.11
节8.6.1.3.12
节8.6.1.3.13
节8.6.1.3.14
节8.6.1.3.15
节8.6.1.3.16
节8.6.1.3.17
节8.6.1.3.18
节8.6.1.3.19
节8.6.1.3.20
节8.6.1.3.21
节8.6.1.3.22
节8.6.1.3.23
节8.6.1.3.24
节8.6.1.3.25
节8.6.1.3.26
节8.6.1.3.27
节8.6.1.3.28
节8.6.1.3.29
节8.6.1.3.30
节8.6.1.3.31
节8.6.1.3.32
节8.6.1.3.33
节8.6.1.3.34
节8.6.1.3.35
节8.6.1.3.36
节8.6.1.3.37
0x16
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x35
0x37
0x55
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x76
0x77
0x78
0x79
0x7E
MBIAS_LOAD
INT_LIVE0
MICBIAS internal load sink configuration register
Live interrupt readback register 0
CHx_LIVE
Channel diagnostic summary live status register
Channel 1 diagnostic live status register
Channel 2 diagnostic live status register
Channel 3 diagnostic live status register
Channel 4 diagnostic live status register
Live interrupt readback register 1
CH1_LIVE
CH2_LIVE
CH3_LIVE
CH4_LIVE
INT_LIVE1
INT_LIVE3
Live interrupt readback register 3
MBIAS_OV_CFG
DIAGDATA_CFG
DIAG_MON_MSB_VBAT
DIAG_MON_LSB_VBAT
MICBIAS overvoltage threshold register
Diagnostic data configuration register
Diagnostic VBAT_IN data MSB byte register
Diagnostic VBAT_IN data LSB nibble register
DIAG_MON_MSB_MBIAS Diagnostic MICBIAS data MSB byte register
DIAG_MON_LSB_MBIAS
DIAG_MON_MSB_IN1P
DIAG_MON_LSB_IN1P
DIAG_MON_MSB_IN1M
DIAG_MON_LSB_IN1M
DIAG_MON_MSB_IN2P
DIAG_MON_LSB_IN2P
DIAG_MON_MSB_IN2M
DIAG_MON_LSB_IN2M
DIAG_MON_MSB_IN3P
DIAG_MON_LSB_IN3P
DIAG_MON_MSB_IN3M
DIAG_MON_LSB_IN3M
DIAG_MON_MSB_IN4P
DIAG_MON_LSB_IN4P
DIAG_MON_MSB_IN4M
DIAG_MON_LSB_IN4M
DIAG_MON_MSB_TEMP
DIAG_MON_LSB_TEMP
DIAG_MON_MSB_LOAD
DIAG_MON_LSB_LOAD
REV_ID
Diagnostic MICBIAS data LSB nibble register
Diagnostic IN1P data MSB byte register
Diagnostic IN1P data LSB nibble register
Diagnostic IN1M data MSB byte register
Diagnostic IN1M data LSB nibble register
Diagnostic IN2P data MSB byte register
Diagnostic IN2P data LSB nibble register
Diagnostic IN2M data MSB byte register
Diagnostic IN2M data LSB nibble register
Diagnostic IN3P data MSB byte register
Diagnostic IN3P data LSB nibble register
Diagnostic IN3M data MSB byte register
Diagnostic IN3M data LSB nibble register
Diagnostic IN4P data MSB byte register
Diagnostic IN4P data LSB nibble register
Diagnostic IN4M data MSB byte register
Diagnostic IN4M data LSB nibble register
Diagnostic temperature data MSB byte register
Diagnostic temperature data LSB nibble register
Diagnostic MICBIAS load current data MSB byte register 0x00
Diagnostic MICBIAS load current data LSB nibble register 0x0F
Silicon revision ID register
0x20
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8.6.1.3.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x0]
PAGE_CFG is shown in 图8-173 and described in 表8-150.
Return to the 表8-149.
The device memory map is divided into pages. This register sets the page.
图8-173. PAGE_CFG Register
7
6
5
4
3
2
1
0
PAGE[7:0]
R/W-00000000b
表8-150. PAGE_CFG Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
PAGE[7:0]
R/W
00000000b These bits set the device page.
0d = Page 0
1d = Page 1
…
255d = Page 255
8.6.1.3.2 MBIAS_LOAD Register (Address = 0x16) [Reset = 0x0]
MBIAS_LOAD is shown in 图8-174 and described in 表8-151.
Return to the 表8-149.
This register is the MICBIAS internal load sink configuration register.
图8-174. MBIAS_LOAD Register
7
6
5
4
3
2
1
0
MICBIAS_INT_
LOAD_SINK_E
N
MICBIAS_INT_LOAD_SINK_VAL[2:0]
RESERVED
R-0000b
R/W-0b
R/W-000b
表8-151. MBIAS_LOAD Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MICBIAS_INT_LOAD_SIN R/W
K_EN
0b
MICBIAS internal load sink setting.
0d = MICBIAS internal load sink is enabled with setting automatically
calculated based on device configuration
1d = MICBIAS internal load sink is enabled based on D6-4 register
bits; This setting must be used for single-ended AC-coupled input to
support high signal swing
6-4
MICBIAS_INT_LOAD_SIN R/W
K_VAL[2:0]
000b
MICBIAS internal load sink current value.
0d = MICBIAS internal load sink current is set to 0 mA (typ)
1d = MICBIAS internal load sink current is set to 4.3 mA (typ)
2d = MICBIAS internal load sink current is set to 8.6 mA (typ)
3d = MICBIAS internal load sink current is set to 12.9 mA (typ)
4d = MICBIAS internal load sink current is set to 17.2 mA (typ)
5d = MICBIAS internal load sink current is set to 21.5 mA (typ)
6d = MICBIAS internal load sink current is set to 25.8 mA (typ)
7d = MICBIAS internal load sink current is set to 30.1 mA (typ)
3-0
RESERVED
R
0000b
Reserved bits; Write only reset values
8.6.1.3.3 INT_LIVE0 Register (Address = 0x2C) [Reset = 0x0]
INT_LIVE0 is shown in 图8-175 and described in 表8-152.
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Return to the 表8-149.
This register is the live Interrupt readback register 0.
图8-175. INT_LIVE0 Register
7
6
5
4
3
2
1
0
INT_LIVE0
R-0b
INT_LIVE0
R-0b
INT_LIVE0
R-0b
INT_LIVE0
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-0b
表8-152. INT_LIVE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE0
INT_LIVE0
INT_LIVE0
INT_LIVE0
R
0b
Fault status for an ASI bus clock error.
0d = No fault detected
1d = Fault detected
6
5
4
R
R
R
0b
0b
0b
Status of PLL lock.
0d = No PLL lock detected
1d = PLL lock detected
Fault status for boost or MICBIAS over temperature.
0d = No fault detected
1d = Fault detected
Fault status for boost or MICBIAS over current.
0d = No fault detected
1d = Fault detected
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
0b
0b
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.1.3.4 CHx_LIVE Register (Address = 0x2D) [Reset = 0x0]
CHx_LIVE is shown in 图8-176 and described in 表8-153.
Return to the 表8-149.
This register is the live Interrupt status register for channel level diagnostic summary.
图8-176. CHx_LIVE Register
7
6
5
4
3
2
1
0
STS_CHx_LIVE STS_CHx_LIVE STS_CHx_LIVE STS_CHx_LIVE RESERVED
R-0b R-0b R-0b R-0b R-0b
RESERVED STS_CHx_LIVE RESERVED
R-0b R-0b R-0b
表8-153. CHx_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
STS_CHx_LIVE
STS_CHx_LIVE
STS_CHx_LIVE
STS_CHx_LIVE
RESERVED
R
0b
Status of CH1_LIVE.
0d = No faults occurred in channel 1
1d = Atleast a fault has occurred in channel 1
R
R
R
R
0b
0b
0b
0b
Status of CH2_LIVE.
0d = No faults occurred in channel 2
1d = Atleast a fault has occurred in channel 2
Status of CH3_LIVE.
0d = No faults occurred in channel 3
1d = Atleast a fault has occurred in channel 3
Status of CH4_LIVE.
0d = No faults occurred in channel 4
1d = Atleast a fault has occurred in channel 4
Reserved bit; Write only reset value
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表8-153. CHx_LIVE Register Field Descriptions (continued)
Bit
2
Field
Type
Reset
Description
RESERVED
R
0b
Reserved bit; Write only reset value
1
STS_CHx_LIVE
R
0b
Status of short to VBAT_IN fault detected when VBAT_IN is less than
MICBIAS.
0d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS
has not occurred in any channel
1d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS
has occurred in atleast one channel
0
RESERVED
R
0b
Reserved bit; Write only reset value
8.6.1.3.5 CH1_LIVE Register (Address = 0x2E) [Reset = 0x0]
CH1_LIVE is shown in 图8-177 and described in 表8-154.
Return to the 表8-149.
This register is the live Interrupt status register for channel 1 fault diagnostic
图8-177. CH1_LIVE Register
7
6
5
4
3
2
1
0
CH1_LIVE
R-0b
CH1_LIVE
R-0b
CH1_LIVE
R-0b
CH1_LIVE
R-0b
CH1_LIVE
R-0b
CH1_LIVE
R-0b
CH1_LIVE
R-0b
CH1_LIVE
R-0b
表8-154. CH1_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_LIVE
CH1_LIVE
CH1_LIVE
CH1_LIVE
CH1_LIVE
CH1_LIVE
CH1_LIVE
CH1_LIVE
R
0b
Channel 1 open input fault status.
0d = No open input detected
1d = Open input detected
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
Channel 1 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
Channel 1 IN1P short to ground fault status.
0d = IN1P no short to ground detected
1d = IN1P short to ground detected
Channel 1 IN1M short to ground fault status.
0d = IN1M no short to ground detected
1d = IN1M short to ground detected
Channel 1 IN1P short to MICBIAS fault status.
0d = IN1P no short to MICBIAS detected
1d = IN1P short to MICBIAS detected
Channel 1 IN1M short to MICBIAS fault status.
0d = IN1M no short to MICBIAS detected
1d = IN1M short to MICBIAS detected
Channel 1 IN1P short to VBAT_IN fault status.
0d = IN1P no short to VBAT_IN detected
1d = IN1P short to VBAT_IN detected
Channel 1 IN1M short to VBAT_IN fault status.
0d = IN1M no short to VBAT_IN detected
1d = IN1M short to VBAT_IN detected
8.6.1.3.6 CH2_LIVE Register (Address = 0x2F) [Reset = 0x0]
CH2_LIVE is shown in 图8-178 and described in 表8-155.
Return to the 表8-149.
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This register is the live Interrupt status register for channel 2 fault diagnostic.
图8-178. CH2_LIVE Register
7
6
5
4
3
2
1
0
CH2_LIVE
R-0b
CH2_LIVE
R-0b
CH2_LIVE
R-0b
CH2_LIVE
R-0b
CH2_LIVE
R-0b
CH2_LIVE
R-0b
CH2_LIVE
R-0b
CH2_LIVE
R-0b
表8-155. CH2_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH2_LIVE
CH2_LIVE
CH2_LIVE
CH2_LIVE
CH2_LIVE
CH2_LIVE
CH2_LIVE
CH2_LIVE
R
0b
Channel 2 open input fault status.
0d = No open input detected
1d = Open input detected
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
Channel 2 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
Channel 2 IN2P short to ground fault status.
0d = IN2P no short to ground detected
1d = IN2P short to ground detected
Channel 2 IN2M short to ground fault status.
0d = IN2M no short to ground detected
1d = IN2M short to ground detected
Channel 2 IN2P short to MICBIAS fault status.
0d = IN2P no short to MICBIAS detected
1d = IN2P short to MICBIAS detected
Channel 2 IN2M short to MICBIAS fault status.
0d = IN2M no short to MICBIAS detected
1d = IN2M short to MICBIAS detected
Channel 2 IN2P short to VBAT_IN fault status.
0d = IN2P no short to VBAT_IN detected
1d = IN2P short to VBAT_IN detected
Channel 2 IN2M short to VBAT_IN fault status.
0d = IN2M no short to VBAT_IN detected
1d = IN2M short to VBAT_IN detected
8.6.1.3.7 CH3_LIVE Register (Address = 0x30) [Reset = 0x0]
CH3_LIVE is shown in 图8-179 and described in 表8-156.
Return to the 表8-149.
This register is the live Interrupt status register for channel3 fault diagnostic
图8-179. CH3_LIVE Register
7
6
5
4
3
2
1
0
CH3_LIVE
R-0b
CH3_LIVE
R-0b
CH3_LIVE
R-0b
CH3_LIVE
R-0b
CH3_LIVE
R-0b
CH3_LIVE
R-0b
CH3_LIVE
R-0b
CH3_LIVE
R-0b
表8-156. CH3_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH3_LIVE
R
0b
Channel 3 open input fault status.
0d = No open input detected
1d = Open input detected
6
CH3_LIVE
R
0b
Channel 3 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
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表8-156. CH3_LIVE Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
CH3_LIVE
CH3_LIVE
CH3_LIVE
CH3_LIVE
CH3_LIVE
CH3_LIVE
R
0b
Channel 3 IN3P short to ground fault status.
0d = IN3P no short to ground detected
1d = IN3P short to ground detected
4
3
2
1
0
R
R
R
R
R
0b
0b
0b
0b
0b
Channel 3 IN3M short to ground fault status.
0d = IN3M no short to ground detected
1d = IN3M short to ground detected
Channel 3 IN3P short to MICBIAS fault status.
0d = IN3P no short to MICBIAS detected
1d = IN3P short to MICBIAS detected
Channel 3 IN3M short to MICBIAS fault status.
0d = IN3M no short to MICBIAS detected
1d = IN3M short to MICBIAS detected
Channel 3 IN3P short to VBAT_IN fault status.
0d = IN3P no short to VBAT_IN detected
1d = IN3P short to VBAT_IN detected
Channel 3 IN3M short to VBAT_IN fault status.
0d = IN3M no short to VBAT_IN detected
1d = IN3M short to VBAT_IN detected
8.6.1.3.8 CH4_LIVE Register (Address = 0x31) [Reset = 0x0]
CH4_LIVE is shown in 图8-180 and described in 表8-157.
Return to the 表8-149.
This register is the live Interrupt status register for channel 4 fault diagnostic.
图8-180. CH4_LIVE Register
7
6
5
4
3
2
1
0
CH4_LIVE
R-0b
CH4_LIVE
R-0b
CH4_LIVE
R-0b
CH4_LIVE
R-0b
CH4_LIVE
R-0b
CH4_LIVE
R-0b
CH4_LIVE
R-0b
CH4_LIVE
R-0b
表8-157. CH4_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH4_LIVE
CH4_LIVE
CH4_LIVE
CH4_LIVE
CH4_LIVE
CH4_LIVE
CH4_LIVE
R
0b
Channel 4 open input fault status.
0d = No open input detected
1d = Open input detected
6
5
4
3
2
1
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
Channel 4 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
Channel 4 IN4P short to ground fault status.
0d = IN4P no short to ground detected
1d = IN4P short to ground detected
Channel 4 IN4M short to ground fault status.
0d = IN4M no short to ground detected
1d = IN4M short to ground detected
Channel 4 IN4P short to MICBIAS fault status.
0d = IN4P no short to MICBIAS detected
1d = IN4P short to MICBIAS detected
Channel 4 IN4M short to MICBIAS fault status.
0d = IN4M no short to MICBIAS detected
1d = IN4M short to MICBIAS detected
Channel 4 IN4P short to VBAT_IN fault status.
0d = IN4P no short to VBAT_IN detected
1d = IN4P short to VBAT_IN detected
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表8-157. CH4_LIVE Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
CH4_LIVE
R
0b
Channel 4 IN4M short to VBAT_IN fault status.
0d = IN4M no short to VBAT_IN detected
1d = IN4M short to VBAT_IN detected
8.6.1.3.9 INT_LIVE1 Register (Address = 0x35) [Reset = 0x0]
INT_LIVE1 is shown in 图8-181 and described in 表8-158.
Return to the 表8-149.
This register is the live Interrupt readback register 1.
图8-181. INT_LIVE1 Register
7
6
5
4
3
2
1
0
INT_LIVE1
R-0b
INT_LIVE1
R-0b
INT_LIVE1
R-0b
INT_LIVE1
R-0b
RESERVED
R-0b
RESERVED
R-0b
RESERVED
R-00b
表8-158. INT_LIVE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE1
INT_LIVE1
INT_LIVE1
INT_LIVE1
R
0b
Channel 1 IN1P over voltage fault status.
0d = No IN1P over voltage fault detected
1d = IN1P over voltage fault has detected
6
5
4
R
R
R
0b
0b
0b
Channel 2 IN2P over voltage fault status.
0d = No IN2P over voltage fault detected
1d = IN2P over voltage fault has detected
Channel 3 IN3P over voltage fault status.
0d = No IN3P over voltage fault detected
1d = IN3P over voltage fault has detected
Channel 4 IN4P over voltage fault status.
0d = No IN4P over voltage fault detected
1d = IN4P over voltage fault has detected
3
2
RESERVED
RESERVED
RESERVED
R
R
R
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bits; Write only reset value
0b
1-0
00b
8.6.1.3.10 INT_LIVE3 Register (Address = 0x37) [Reset = 0x0]
INT_LIVE3 is shown in 图8-182 and described in 表8-159.
Return to the 表8-149.
This register is the live Interrupt readback register 3.
图8-182. INT_LIVE3 Register
7
6
5
4
3
2
1
0
INT_LIVE3
R-0b
INT_LIVE3
R-0b
INT_LIVE3
R-0b
RESERVED
R-00000b
表8-159. INT_LIVE3 Register Field Descriptions
Bit
Field
INT_LIVE3
Type
Reset
Description
7
R
0b
Fault status for MICBIAS high current.
0d = No fault detected
1d = Fault detected
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表8-159. INT_LIVE3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
INT_LIVE3
INT_LIVE3
RESERVED
R
0b
Fault status for MICBIAS low current.
0d = No fault detected
1d = Fault detected
5
R
R
0b
Fault status for MICBIAS over voltage.
0d = No fault detected
1d = Fault detected
4-0
00000b
Reserved bits; Write only reset value
8.6.1.3.11 MBIAS_OV_CFG Register (Address = 0x55) [Reset = 0x40]
MBIAS_OV_CFG is shown in 图8-183 and described in 表8-160.
Return to the 表8-149.
This register is the MICBIAS overvoltage configuration register.
图8-183. MBIAS_OV_CFG Register
7
6
5
4
3
2
1
0
MBIAS_OV_THRES[2:0]
R/W-010b
RESERVED
R-00000b
表8-160. MBIAS_OV_CFG Register Field Descriptions
Bit
7-5
Field
Type
Reset
Description
MBIAS_OV_THRES[2:0] R/W
010b
MICBIAS overvoltage fault detection threshold above MICBIAS
programmed voltage.
0d = No threshold over programmed voltage
1d = 10mV (typ) threshold over programmed voltage
2d = 40mV (typ) threshold over programmed voltage (default)
3d to 6d = Threshold value is set as per configuration with step size
of 30mV (typ)
7d = 190mV (typ) threshold over programmed voltage (default)
4-0
RESERVED
R
00000b
Reserved bits; Write only reset value
8.6.1.3.12 DIAGDATA_CFG Register (Address = 0x59) [Reset = 0x0]
DIAGDATA_CFG is shown in 图8-184 and described in 表8-161.
Return to the 表8-149.
This register is the diagnostic data configuration register.
图8-184. DIAGDATA_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0000b
RESERVED
HOLD_SAR_D
ATA
R-000b
R/W-0b
表8-161. DIAGDATA_CFG Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
0000b
000b
Description
7-4
3-1
RESERVED
RESERVED
Reserved bits; Write only reset values
Reserved bits; Write only reset values
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表8-161. DIAGDATA_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
HOLD_SAR_DATA
R/W
0b
Hold SAR data update during register readback.
0d = Data update is not held, data register is continuously updated;
this setting must be used when moving average is enabled for fault
detection
1d = Data update is held, data register readback can be done
8.6.1.3.13 DIAG_MON_MSB_VBAT Register (Address = 0x5A) [Reset = 0x0]
DIAG_MON_MSB_VBAT is shown in 图8-185 and described in 表8-162.
Return to the 表8-149.
This register is the MSB data byte of VBAT_IN monitoring.
图8-185. DIAG_MON_MSB_VBAT Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_VBAT[7:0]
R-00000000b
表8-162. DIAG_MON_MSB_VBAT Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_VBAT[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.14 DIAG_MON_LSB_VBAT Register (Address = 0x5B) [Reset = 0x0]
DIAG_MON_LSB_VBAT is shown in 图8-186 and described in 表8-163.
Return to the 表8-149.
This register is the LSB data nibble of VBAT_IN monitoring.
图8-186. DIAG_MON_LSB_VBAT Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_VBAT[3:0]
R-0000b
CHANNEL_ID[3:0]
R-0000b
表8-163. DIAG_MON_LSB_VBAT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_VBAT[3
:0]
R
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
0000b
Channel ID value.
8.6.1.3.15 DIAG_MON_MSB_MBIAS Register (Address = 0x5C) [Reset = 0x0]
DIAG_MON_MSB_MBIAS is shown in 图8-187 and described in 表8-164.
Return to the 表8-149.
This register is the MSB data byte of MICBIAS monitoring.
图8-187. DIAG_MON_MSB_MBIAS Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_MBIAS[7:0]
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图8-187. DIAG_MON_MSB_MBIAS Register (continued)
R-00000000b
表8-164. DIAG_MON_MSB_MBIAS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIAG_MON_MSB_MBIA
S[7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.16 DIAG_MON_LSB_MBIAS Register (Address = 0x5D) [Reset = 0x1]
DIAG_MON_LSB_MBIAS is shown in 图8-188 and described in 表8-165.
Return to the 表8-149.
This register is the LSB data nibble of MICBIAS monitoring.
图8-188. DIAG_MON_LSB_MBIAS Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_MBIAS[3:0]
R-0000b
CHANNEL_ID[3:0]
R-0001b
表8-165. DIAG_MON_LSB_MBIAS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_MBIAS[ R
3:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
0001b
Channel ID value.
8.6.1.3.17 DIAG_MON_MSB_IN1P Register (Address = 0x5E) [Reset = 0x0]
DIAG_MON_MSB_IN1P is shown in 图8-189 and described in 表8-166.
Return to the 表8-149.
This register is the MSB data byte of IN1P monitoring.
图8-189. DIAG_MON_MSB_IN1P Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_CH1P[7:0]
R-00000000b
表8-166. DIAG_MON_MSB_IN1P Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_CH1P[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.18 DIAG_MON_LSB_IN1P Register (Address = 0x5F) [Reset = 0x2]
DIAG_MON_LSB_IN1P is shown in 图8-190 and described in 表8-167.
Return to the 表8-149.
This register is the LSB data nibble of IN1P monitoring.
图8-190. DIAG_MON_LSB_IN1P Register
7
6
5
4
3
2
1
0
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图8-190. DIAG_MON_LSB_IN1P Register (continued)
DIAG_MON_LSB_CH1P[3:0]
CHANNEL_ID[3:0]
R-0000b
R-0010b
表8-167. DIAG_MON_LSB_IN1P Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_CH1P[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
0010b
Channel ID value.
8.6.1.3.19 DIAG_MON_MSB_IN1M Register (Address = 0x60) [Reset = 0x0]
DIAG_MON_MSB_IN1M is shown in 图8-191 and described in 表8-168.
Return to the 表8-149.
This register is the MSB data byte of IN1M monitoring.
图8-191. DIAG_MON_MSB_IN1M Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_CH1N[7:0]
R-00000000b
表8-168. DIAG_MON_MSB_IN1M Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_CH1N[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.20 DIAG_MON_LSB_IN1M Register (Address = 0x61) [Reset = 0x3]
DIAG_MON_LSB_IN1M is shown in 图8-192 and described in 表8-169.
Return to the 表8-149.
This register is the LSB data nibble of IN1M monitoring.
图8-192. DIAG_MON_LSB_IN1M Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_CH1N[3:0]
R-0000b
CHANNEL_ID[3:0]
R-0011b
表8-169. DIAG_MON_LSB_IN1M Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_CH1N[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
0011b
Channel ID value.
8.6.1.3.21 DIAG_MON_MSB_IN2P Register (Address = 0x62) [Reset = 0x0]
DIAG_MON_MSB_IN2P is shown in 图8-193 and described in 表8-170.
Return to the 表8-149.
This register is the MSB data byte of IN2P monitoring.
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图8-193. DIAG_MON_MSB_IN2P Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_CH2P[7:0]
R-00000000b
表8-170. DIAG_MON_MSB_IN2P Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIAG_MON_MSB_CH2P[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.22 DIAG_MON_LSB_IN2P Register (Address = 0x63) [Reset = 0x4]
DIAG_MON_LSB_IN2P is shown in 图8-194 and described in 表8-171.
Return to the 表8-149.
This register is the LSB data nibble of IN2P monitoring.
图8-194. DIAG_MON_LSB_IN2P Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_CH2P[3:0]
R-0000b
CHANNEL_ID[3:0]
R-0100b
表8-171. DIAG_MON_LSB_IN2P Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_CH2P[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
0100b
Channel ID value.
8.6.1.3.23 DIAG_MON_MSB_IN2M Register (Address = 0x64) [Reset = 0x0]
DIAG_MON_MSB_IN2M is shown in 图8-195 and described in 表8-172.
Return to the 表8-149.
This register is the MSB data byte of IN2M monitoring.
图8-195. DIAG_MON_MSB_IN2M Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_CH2N[7:0]
R-00000000b
表8-172. DIAG_MON_MSB_IN2M Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_CH2N[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.24 DIAG_MON_LSB_IN2M Register (Address = 0x65) [Reset = 0x5]
DIAG_MON_LSB_IN2M is shown in 图8-196 and described in 表8-173.
Return to the 表8-149.
This register is the LSB data nibble of IN2M monitoring.
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图8-196. DIAG_MON_LSB_IN2M Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_CH2N[3:0]
R-0000b
CHANNEL_ID[3:0]
R-0101b
表8-173. DIAG_MON_LSB_IN2M Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_CH2N[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
0101b
Channel ID value.
8.6.1.3.25 DIAG_MON_MSB_IN3P Register (Address = 0x66) [Reset = 0x0]
DIAG_MON_MSB_IN3P is shown in 图8-197 and described in 表8-174.
Return to the 表8-149.
This register is the MSB data byte of IN3P monitoring.
图8-197. DIAG_MON_MSB_IN3P Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_CH3P[7:0]
R-00000000b
表8-174. DIAG_MON_MSB_IN3P Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_CH3P[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.26 DIAG_MON_LSB_IN3P Register (Address = 0x67) [Reset = 0x6]
DIAG_MON_LSB_IN3P is shown in 图8-198 and described in 表8-175.
Return to the 表8-149.
This register is the LSB data nibble of IN3P monitoring.
图8-198. DIAG_MON_LSB_IN3P Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_CH3P[3:0]
R-0000b
CHANNEL_ID[3:0]
R-0110b
表8-175. DIAG_MON_LSB_IN3P Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_CH3P[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
0110b
Channel ID value.
8.6.1.3.27 DIAG_MON_MSB_IN3M Register (Address = 0x68) [Reset = 0x0]
DIAG_MON_MSB_IN3M is shown in 图8-199 and described in 表8-176.
Return to the 表8-149.
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This register is the MSB data byte of IN3M monitoring.
图8-199. DIAG_MON_MSB_IN3M Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_CH3N[7:0]
R-00000000b
表8-176. DIAG_MON_MSB_IN3M Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_CH3N[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.28 DIAG_MON_LSB_IN3M Register (Address = 0x69) [Reset = 0x7]
DIAG_MON_LSB_IN3M is shown in 图8-200 and described in 表8-177.
Return to the 表8-149.
This register is the LSB data nibble of IN3M monitoring.
图8-200. DIAG_MON_LSB_IN3M Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_CH3N[3:0]
R-0000b
CHANNEL_ID[3:0]
R-0111b
表8-177. DIAG_MON_LSB_IN3M Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_CH3N[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
0111b
Channel ID value.
8.6.1.3.29 DIAG_MON_MSB_IN4P Register (Address = 0x6A) [Reset = 0x0]
DIAG_MON_MSB_IN4P is shown in 图8-201 and described in 表8-178.
Return to the 表8-149.
This register is the MSB data byte of IN4P monitoring.
图8-201. DIAG_MON_MSB_IN4P Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_CH4P[7:0]
R-00000000b
表8-178. DIAG_MON_MSB_IN4P Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_CH4P[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.30 DIAG_MON_LSB_IN4P Register (Address = 0x6B) [Reset = 0x8]
DIAG_MON_LSB_IN4P is shown in 图8-202 and described in 表8-179.
Return to the 表8-149.
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This register is the LSB data nibble of IN4P monitoring.
图8-202. DIAG_MON_LSB_IN4P Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_CH4P[3:0]
R-0000b
CHANNEL_ID[3:0]
R-1000b
表8-179. DIAG_MON_LSB_IN4P Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_CH4P[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
1000b
Channel ID value.
8.6.1.3.31 DIAG_MON_MSB_IN4M Register (Address = 0x6C) [Reset = 0x0]
DIAG_MON_MSB_IN4M is shown in 图8-203 and described in 表8-180.
Return to the 表8-149.
This register is the MSB data byte of IN4M monitoring.
图8-203. DIAG_MON_MSB_IN4M Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_CH4N[7:0]
R-00000000b
表8-180. DIAG_MON_MSB_IN4M Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_CH4N[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.32 DIAG_MON_LSB_IN4M Register (Address = 0x6D) [Reset = 0x9]
DIAG_MON_LSB_IN4M is shown in 图8-204 and described in 表8-181.
Return to the 表8-149.
This register is the LSB data nibble of IN4M monitoring.
图8-204. DIAG_MON_LSB_IN4M Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_CH4N[3:0]
R-0000b
CHANNEL_ID[3:0]
R-1001b
表8-181. DIAG_MON_LSB_IN4M Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_CH4N[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
1001b
Channel ID value.
8.6.1.3.33 DIAG_MON_MSB_TEMP Register (Address = 0x76) [Reset = 0x0]
DIAG_MON_MSB_TEMP is shown in 图8-205 and described in 表8-182.
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Return to the 表8-149.
This register is the MSB data byte of temperature monitoring.
图8-205. DIAG_MON_MSB_TEMP Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_TEMP[7:0]
R-00000000b
表8-182. DIAG_MON_MSB_TEMP Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_TEMP[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.34 DIAG_MON_LSB_TEMP Register (Address = 0x77) [Reset = 0xE]
DIAG_MON_LSB_TEMP is shown in 图8-206 and described in 表8-183.
Return to the 表8-149.
This register is the LSB data nibble of temperature monitoring.
图8-206. DIAG_MON_LSB_TEMP Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_TEMP[3:0]
R-0000b
CHANNEL_ID[3:0]
R-1110b
表8-183. DIAG_MON_LSB_TEMP Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_TEMP[
3:0]
R
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
1110b
Channel ID value.
8.6.1.3.35 DIAG_MON_MSB_LOAD Register (Address = 0x78) [Reset = 0x0]
DIAG_MON_MSB_LOAD is shown in 图8-207 and described in 表8-184.
Return to the 表8-149.
This register is the MSB data byte of MICBIAS load current monitoring.
图8-207. DIAG_MON_MSB_LOAD Register
7
6
5
4
3
2
1
0
DIAG_MON_MSB_LOAD[7:0]
R-00000000b
表8-184. DIAG_MON_MSB_LOAD Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIAG_MON_MSB_LOAD[
7:0]
R
00000000b Diagnostic SAR monitor data MSB byte.
8.6.1.3.36 DIAG_MON_LSB_LOAD Register (Address = 0x79) [Reset = 0xF]
DIAG_MON_LSB_LOAD is shown in 图8-208 and described in 表8-185.
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Return to the 表8-149.
This register is the LSB data nibble of MICBIAS load current monitoring.
图8-208. DIAG_MON_LSB_LOAD Register
7
6
5
4
3
2
1
0
DIAG_MON_LSB_LOAD[3:0]
R-0000b
CHANNEL_ID[3:0]
R-1111b
表8-185. DIAG_MON_LSB_LOAD Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_LOAD[3 R
:0]
0000b
Diagnostic SAR monitor data LSB nibble.
3-0
CHANNEL_ID[3:0]
R
1111b
Channel ID value.
8.6.1.3.37 REV_ID Register (Address = 0x7E) [Reset = 0x20]
REV_ID is shown in 图8-209 and described in 表8-186.
Return to the 表8-149.
This register is the silicon revision ID register.
图8-209. REV_ID Register
7
6
5
4
3
2
1
0
REV_ID[3:0]
R-0010b
RESERVED
R-0000b
表8-186. REV_ID Register Field Descriptions
Bit
Field
Type
Reset
0010b
0000b
Description
7-4
3-0
REV_ID[3:0]
RESERVED
R
Returns the revision ID.
Reserved bits; Write only reset values
R
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8.6.2 Programmable Coefficient Registers
8.6.2.1 Programmable Coefficient Registers: Page 2
This register page (shown in 表 8-187) consists of the programmable coefficients for the biquad 1 to biquad 6
filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also
supports (by default) auto-incremented pages for the I2C and SPI burst writes and reads. After a transaction of
register address 0x7F, the device auto increments to the next page at register 0x08 to transact the next
coefficient value. These programmable coefficients are 32-bit, two’s complement numbers. For a successful
coefficient register transaction, the host device must write and read all four bytes starting with the most
significant byte (BYT1) for a target coefficient register transaction. When using SPI for a coefficient register read
transaction, the device transmits the first byte as a dummy read byte; therefore, the host must read five bytes,
including the first dummy read byte and the last four bytes corresponding to the coefficient register value starting
with the most significant byte (BYT1).
表8-187. Page 2 Programmable Coefficient Registers
ADDRESS
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
ACRONYM
RESET VALUE
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
REGISTER DESCRIPTION
PAGE[7:0]
节8.6.1.2.1
BQ1_N0_BYT1[7:0]
BQ1_N0_BYT2[7:0]
BQ1_N0_BYT3[7:0]
BQ1_N0_BYT4[7:0]
BQ1_N1_BYT1[7:0]
BQ1_N1_BYT2[7:0]
BQ1_N1_BYT3[7:0]
BQ1_N1_BYT4[7:0]
BQ1_N2_BYT1[7:0]
BQ1_N2_BYT2[7:0]
BQ1_N2_BYT3[7:0]
BQ1_N2_BYT4[7:0]
BQ1_D1_BYT1[7:0]
BQ1_D1_BYT2[7:0]
BQ1_D1_BYT3[7:0]
BQ1_D1_BYT4[7:0]
BQ1_D2_BYT1[7:0]
BQ1_D2_BYT2[7:0]
BQ1_D2_BYT3[7:0]
BQ1_D2_BYT4[7:0]
BQ2_N0_BYT1[7:0]
BQ2_N0_BYT2[7:0]
BQ2_N0_BYT3[7:0]
BQ2_N0_BYT4[7:0]
BQ2_N1_BYT1[7:0]
BQ2_N1_BYT2[7:0]
BQ2_N1_BYT3[7:0]
BQ2_N1_BYT4[7:0]
BQ2_N2_BYT1[7:0]
BQ2_N2_BYT2[7:0]
BQ2_N2_BYT3[7:0]
BQ2_N2_BYT4[7:0]
BQ2_D1_BYT1[7:0]
BQ2_D1_BYT2[7:0]
BQ2_D1_BYT3[7:0]
BQ2_D1_BYT4[7:0]
Programmable biquad 1, N0 coefficient byte[31:24]
Programmable biquad 1, N0 coefficient byte[23:16]
Programmable biquad 1, N0 coefficient byte[15:8]
Programmable biquad 1, N0 coefficient byte[7:0]
Programmable biquad 1, N1 coefficient byte[31:24]
Programmable biquad 1, N1 coefficient byte[23:16]
Programmable biquad 1, N1 coefficient byte[15:8]
Programmable biquad 1, N1 coefficient byte[7:0]
Programmable biquad 1, N2 coefficient byte[31:24]
Programmable biquad 1, N2 coefficient byte[23:16]
Programmable biquad 1, N2 coefficient byte[15:8]
Programmable biquad 1, N2 coefficient byte[7:0]
Programmable biquad 1, D1 coefficient byte[31:24]
Programmable biquad 1, D1 coefficient byte[23:16]
Programmable biquad 1, D1 coefficient byte[15:8]
Programmable biquad 1, D1 coefficient byte[7:0]
Programmable biquad 1, D2 coefficient byte[31:24]
Programmable biquad 1, D2 coefficient byte[23:16]
Programmable biquad 1, D2 coefficient byte[15:8]
Programmable biquad 1, D2 coefficient byte[7:0]
Programmable biquad 2, N0 coefficient byte[31:24]
Programmable biquad 2, N0 coefficient byte[23:16]
Programmable biquad 2, N0 coefficient byte[15:8]
Programmable biquad 2, N0 coefficient byte[7:0]
Programmable biquad 2, N1 coefficient byte[31:24]
Programmable biquad 2, N1 coefficient byte[23:16]
Programmable biquad 2, N1 coefficient byte[15:8]
Programmable biquad 2, N1 coefficient byte[7:0]
Programmable biquad 2, N2 coefficient byte[31:24]
Programmable biquad 2, N2 coefficient byte[23:16]
Programmable biquad 2, N2 coefficient byte[15:8]
Programmable biquad 2, N2 coefficient byte[7:0]
Programmable biquad 2, D1 coefficient byte[31:24]
Programmable biquad 2, D1 coefficient byte[23:16]
Programmable biquad 2, D1 coefficient byte[15:8]
Programmable biquad 2, D1 coefficient byte[7:0]
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表8-187. Page 2 Programmable Coefficient Registers (continued)
ADDRESS
ACRONYM
BQ2_D2_BYT1[7:0]
BQ2_D2_BYT2[7:0]
RESET VALUE
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
REGISTER DESCRIPTION
Programmable biquad 2, D2 coefficient byte[31:24]
Programmable biquad 2, D2 coefficient byte[23:16]
Programmable biquad 2, D2 coefficient byte[15:8]
Programmable biquad 2, D2 coefficient byte[7:0]
Programmable biquad 3, N0 coefficient byte[31:24]
Programmable biquad 3, N0 coefficient byte[23:16]
Programmable biquad 3, N0 coefficient byte[15:8]
Programmable biquad 3, N0 coefficient byte[7:0]
Programmable biquad 3, N1 coefficient byte[31:24]
Programmable biquad 3, N1 coefficient byte[23:16]
Programmable biquad 3, N1 coefficient byte[15:8]
Programmable biquad 3, N1 coefficient byte[7:0]
Programmable biquad 3, N2 coefficient byte[31:24]
Programmable biquad 3, N2 coefficient byte[23:16]
Programmable biquad 3, N2 coefficient byte[15:8]
Programmable biquad 3, N2 coefficient byte[7:0]
Programmable biquad 3, D1 coefficient byte[31:24]
Programmable biquad 3, D1 coefficient byte[23:16]
Programmable biquad 3, D1 coefficient byte[15:8]
Programmable biquad 3, D1 coefficient byte[7:0]
Programmable biquad 3, D2 coefficient byte[31:24]
Programmable biquad 3, D2 coefficient byte[23:16]
Programmable biquad 3, D2 coefficient byte[15:8]
Programmable biquad 3, D2 coefficient byte[7:0]
Programmable biquad 4, N0 coefficient byte[31:24]
Programmable biquad 4, N0 coefficient byte[23:16]
Programmable biquad 4, N0 coefficient byte[15:8]
Programmable biquad 4, N0 coefficient byte[7:0]
Programmable biquad 4, N1 coefficient byte[31:24]
Programmable biquad 4, N1 coefficient byte[23:16]
Programmable biquad 4, N1 coefficient byte[15:8]
Programmable biquad 4, N1 coefficient byte[7:0]
Programmable biquad 4, N2 coefficient byte[31:24]
Programmable biquad 4, N2 coefficient byte[23:16]
Programmable biquad 4, N2 coefficient byte[15:8]
Programmable biquad 4, N2 coefficient byte[7:0]
Programmable biquad 4, D1 coefficient byte[31:24]
Programmable biquad 4, D1 coefficient byte[23:16]
Programmable biquad 4, D1 coefficient byte[15:8]
Programmable biquad 4, D1 coefficient byte[7:0]
Programmable biquad 4, D2 coefficient byte[31:24]
Programmable biquad 4, D2 coefficient byte[23:16]
Programmable biquad 4, D2 coefficient byte[15:8]
Programmable biquad 4, D2 coefficient byte[7:0]
Programmable biquad 5, N0 coefficient byte[31:24]
Programmable biquad 5, N0 coefficient byte[23:16]
Programmable biquad 5, N0 coefficient byte[15:8]
Programmable biquad 5, N0 coefficient byte[7:0]
Programmable biquad 5, N1 coefficient byte[31:24]
Programmable biquad 5, N1 coefficient byte[23:16]
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
BQ2_D2_BYT3[7:0]
BQ2_D2_BYT4[7:0]
BQ3_N0_BYT1[7:0]
BQ3_N0_BYT2[7:0]
BQ3_N0_BYT3[7:0]
BQ3_N0_BYT4[7:0]
BQ3_N1_BYT1[7:0]
BQ3_N1_BYT2[7:0]
BQ3_N1_BYT3[7:0]
BQ3_N1_BYT4[7:0]
BQ3_N2_BYT1[7:0]
BQ3_N2_BYT2[7:0]
BQ3_N2_BYT3[7:0]
BQ3_N2_BYT4[7:0]
BQ3_D1_BYT1[7:0]
BQ3_D1_BYT2[7:0]
BQ3_D1_BYT3[7:0]
BQ3_D1_BYT4[7:0]
BQ3_D2_BYT1[7:0]
BQ3_D2_BYT2[7:0]
BQ3_D2_BYT3[7:0]
BQ3_D2_BYT4[7:0]
BQ4_N0_BYT1[7:0]
BQ4_N0_BYT2[7:0]
BQ4_N0_BYT3[7:0]
BQ4_N0_BYT4[7:0]
BQ4_N1_BYT1[7:0]
BQ4_N1_BYT2[7:0]
BQ4_N1_BYT3[7:0]
BQ4_N1_BYT4[7:0]
BQ4_N2_BYT1[7:0]
BQ4_N2_BYT2[7:0]
BQ4_N2_BYT3[7:0]
BQ4_N2_BYT4[7:0]
BQ4_D1_BYT1[7:0]
BQ4_D1_BYT2[7:0]
BQ4_D1_BYT3[7:0]
BQ4_D1_BYT4[7:0]
BQ4_D2_BYT1[7:0]
BQ4_D2_BYT2[7:0]
BQ4_D2_BYT3[7:0]
BQ4_D2_BYT4[7:0]
BQ5_N0_BYT1[7:0]
BQ5_N0_BYT2[7:0]
BQ5_N0_BYT3[7:0]
BQ5_N0_BYT4[7:0]
BQ5_N1_BYT1[7:0]
BQ5_N1_BYT2[7:0]
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表8-187. Page 2 Programmable Coefficient Registers (continued)
ADDRESS
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
ACRONYM
RESET VALUE
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
REGISTER DESCRIPTION
BQ5_N1_BYT3[7:0]
Programmable biquad 5, N1 coefficient byte[15:8]
Programmable biquad 5, N1 coefficient byte[7:0]
Programmable biquad 5, N2 coefficient byte[31:24]
Programmable biquad 5, N2 coefficient byte[23:16]
Programmable biquad 5, N2 coefficient byte[15:8]
Programmable biquad 5, N2 coefficient byte[7:0]
Programmable biquad 5, D1 coefficient byte[31:24]
Programmable biquad 5, D1 coefficient byte[23:16]
Programmable biquad 5, D1 coefficient byte[15:8]
Programmable biquad 5, D1 coefficient byte[7:0]
Programmable biquad 5, D2 coefficient byte[31:24]
Programmable biquad 5, D2 coefficient byte[23:16]
Programmable biquad 5, D2 coefficient byte[15:8]
Programmable biquad 5, D2 coefficient byte[7:0]
Programmable biquad 6, N0 coefficient byte[31:24]
Programmable biquad 6, N0 coefficient byte[23:16]
Programmable biquad 6, N0 coefficient byte[15:8]
Programmable biquad 6, N0 coefficient byte[7:0]
Programmable biquad 6, N1 coefficient byte[31:24]
Programmable biquad 6, N1 coefficient byte[23:16]
Programmable biquad 6, N1 coefficient byte[15:8]
Programmable biquad 6, N1 coefficient byte[7:0]
Programmable biquad 6, N2 coefficient byte[31:24]
Programmable biquad 6, N2 coefficient byte[23:16]
Programmable biquad 6, N2 coefficient byte[15:8]
Programmable biquad 6, N2 coefficient byte[7:0]
Programmable biquad 6, D1 coefficient byte[31:24]
Programmable biquad 6, D1 coefficient byte[23:16]
Programmable biquad 6, D1 coefficient byte[15:8]
Programmable biquad 6, D1 coefficient byte[7:0]
Programmable biquad 6, D2 coefficient byte[31:24]
Programmable biquad 6, D2 coefficient byte[23:16]
Programmable biquad 6, D2 coefficient byte[15:8]
Programmable biquad 6, D2 coefficient byte[7:0]
BQ5_N1_BYT4[7:0]
BQ5_N2_BYT1[7:0]
BQ5_N2_BYT2[7:0]
BQ5_N2_BYT3[7:0]
BQ5_N2_BYT4[7:0]
BQ5_D1_BYT1[7:0]
BQ5_D1_BYT2[7:0]
BQ5_D1_BYT3[7:0]
BQ5_D1_BYT4[7:0]
BQ5_D2_BYT1[7:0]
BQ5_D2_BYT2[7:0]
BQ5_D2_BYT3[7:0]
BQ5_D2_BYT4[7:0]
BQ6_N0_BYT1[7:0]
BQ6_N0_BYT2[7:0]
BQ6_N0_BYT3[7:0]
BQ6_N0_BYT4[7:0]
BQ6_N1_BYT1[7:0]
BQ6_N1_BYT2[7:0]
BQ6_N1_BYT3[7:0]
BQ6_N1_BYT4[7:0]
BQ6_N2_BYT1[7:0]
BQ6_N2_BYT2[7:0]
BQ6_N2_BYT3[7:0]
BQ6_N2_BYT4[7:0]
BQ6_D1_BYT1[7:0]
BQ6_D1_BYT2[7:0]
BQ6_D1_BYT3[7:0]
BQ6_D1_BYT4[7:0]
BQ6_D2_BYT1[7:0]
BQ6_D2_BYT2[7:0]
BQ6_D2_BYT3[7:0]
BQ6_D2_BYT4[7:0]
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8.6.2.2 Programmable Coefficient Registers: Page 3
This register page (shown in 表 8-188) consists of the programmable coefficients for the biquad 7 to biquad 12
filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also
supports (by default) auto-incremented pages for the I2C and SPI burst writes and reads. After a transaction of
register address 0x7F, the device auto increments to the next page at register 0x08 to transact the next
coefficient value. These programmable coefficients are 32-bit, two’s complement numbers. For a successful
coefficient register transaction, the host device must write and read all four bytes starting with the most
significant byte (BYT1) for a target coefficient register transaction. When using SPI for a coefficient register read
transaction, the device transmits the first byte as a dummy read byte; therefore, the host must read five bytes,
including the first dummy read byte and the last four bytes corresponding to the coefficient register value starting
with the most significant byte (BYT1).
表8-188. Page 3 Programmable Coefficient Registers
ADDRESS
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
ACRONYM
RESET VALUE
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
REGISTER DESCRIPTION
PAGE[7:0]
节8.6.1.2.1
BQ7_N0_BYT1[7:0]
BQ7_N0_BYT2[7:0]
BQ7_N0_BYT3[7:0]
BQ7_N0_BYT4[7:0]
BQ7_N1_BYT1[7:0]
BQ7_N1_BYT2[7:0]
BQ7_N1_BYT3[7:0]
BQ7_N1_BYT4[7:0]
BQ7_N2_BYT1[7:0]
BQ7_N2_BYT2[7:0]
BQ7_N2_BYT3[7:0]
BQ7_N2_BYT4[7:0]
BQ7_D1_BYT1[7:0]
BQ7_D1_BYT2[7:0]
BQ7_D1_BYT3[7:0]
BQ7_D1_BYT4[7:0]
BQ7_D2_BYT1[7:0]
BQ7_D2_BYT2[7:0]
BQ7_D2_BYT3[7:0]
BQ7_D2_BYT4[7:0]
BQ8_N0_BYT1[7:0]
BQ8_N0_BYT2[7:0]
BQ8_N0_BYT3[7:0]
BQ8_N0_BYT4[7:0]
BQ8_N1_BYT1[7:0]
BQ8_N1_BYT2[7:0]
BQ8_N1_BYT3[7:0]
BQ8_N1_BYT4[7:0]
BQ8_N2_BYT1[7:0]
BQ8_N2_BYT2[7:0]
BQ8_N2_BYT3[7:0]
BQ8_N2_BYT4[7:0]
BQ8_D1_BYT1[7:0]
BQ8_D1_BYT2[7:0]
BQ8_D1_BYT3[7:0]
BQ8_D1_BYT4[7:0]
BQ8_D2_BYT1[7:0]
Programmable biquad 7, N0 coefficient byte[31:24]
Programmable biquad 7, N0 coefficient byte[23:16]
Programmable biquad 7, N0 coefficient byte[15:8]
Programmable biquad 7, N0 coefficient byte[7:0]
Programmable biquad 7, N1 coefficient byte[31:24]
Programmable biquad 7, N1 coefficient byte[23:16]
Programmable biquad 7, N1 coefficient byte[15:8]
Programmable biquad 7, N1 coefficient byte[7:0]
Programmable biquad 7, N2 coefficient byte[31:24]
Programmable biquad 7, N2 coefficient byte[23:16]
Programmable biquad 7, N2 coefficient byte[15:8]
Programmable biquad 7, N2 coefficient byte[7:0]
Programmable biquad 7, D1 coefficient byte[31:24]
Programmable biquad 7, D1 coefficient byte[23:16]
Programmable biquad 7, D1 coefficient byte[15:8]
Programmable biquad 7, D1 coefficient byte[7:0]
Programmable biquad 7, D2 coefficient byte[31:24]
Programmable biquad 7, D2 coefficient byte[23:16]
Programmable biquad 7, D2 coefficient byte[15:8]
Programmable biquad 7, D2 coefficient byte[7:0]
Programmable biquad 8, N0 coefficient byte[31:24]
Programmable biquad 8, N0 coefficient byte[23:16]
Programmable biquad 8, N0 coefficient byte[15:8]
Programmable biquad 8, N0 coefficient byte[7:0]
Programmable biquad 8, N1 coefficient byte[31:24]
Programmable biquad 8, N1 coefficient byte[23:16]
Programmable biquad 8, N1 coefficient byte[15:8]
Programmable biquad 8, N1 coefficient byte[7:0]
Programmable biquad 8, N2 coefficient byte[31:24]
Programmable biquad 8, N2 coefficient byte[23:16]
Programmable biquad 8, N2 coefficient byte[15:8]
Programmable biquad 8, N2 coefficient byte[7:0]
Programmable biquad 8, D1 coefficient byte[31:24]
Programmable biquad 8, D1 coefficient byte[23:16]
Programmable biquad 8, D1 coefficient byte[15:8]
Programmable biquad 8, D1 coefficient byte[7:0]
Programmable biquad 8, D2 coefficient byte[31:24]
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表8-188. Page 3 Programmable Coefficient Registers (continued)
ADDRESS
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
ACRONYM
RESET VALUE
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
REGISTER DESCRIPTION
BQ8_D2_BYT2[7:0]
Programmable biquad 8, D2 coefficient byte[23:16]
Programmable biquad 8, D2 coefficient byte[15:8]
Programmable biquad 8, D2 coefficient byte[7:0]
Programmable biquad 9, N0 coefficient byte[31:24]
Programmable biquad 9, N0 coefficient byte[23:16]
Programmable biquad 9, N0 coefficient byte[15:8]
Programmable biquad 9, N0 coefficient byte[7:0]
Programmable biquad 9, N1 coefficient byte[31:24]
Programmable biquad 9, N1 coefficient byte[23:16]
Programmable biquad 9, N1 coefficient byte[15:8]
Programmable biquad 9, N1 coefficient byte[7:0]
Programmable biquad 9, N2 coefficient byte[31:24]
Programmable biquad 9, N2 coefficient byte[23:16]
Programmable biquad 9, N2 coefficient byte[15:8]
Programmable biquad 9, N2 coefficient byte[7:0]
Programmable biquad 9, D1 coefficient byte[31:24]
Programmable biquad 9, D1 coefficient byte[23:16]
Programmable biquad 9, D1 coefficient byte[15:8]
Programmable biquad 9, D1 coefficient byte[7:0]
Programmable biquad 9, D2 coefficient byte[31:24]
Programmable biquad 9, D2 coefficient byte[23:16]
Programmable biquad 9, D2 coefficient byte[15:8]
Programmable biquad 9, D2 coefficient byte[7:0]
Programmable biquad 10, N0 coefficient byte[31:24]
Programmable biquad 10, N0 coefficient byte[23:16]
Programmable biquad 10, N0 coefficient byte[15:8]
Programmable biquad 10, N0 coefficient byte[7:0]
Programmable biquad 10, N1 coefficient byte[31:24]
Programmable biquad 10, N1 coefficient byte[23:16]
Programmable biquad 10, N1 coefficient byte[15:8]
Programmable biquad 10, N1 coefficient byte[7:0]
Programmable biquad 10, N2 coefficient byte[31:24]
Programmable biquad 10, N2 coefficient byte[23:16]
Programmable biquad 10, N2 coefficient byte[15:8]
Programmable biquad 10, N2 coefficient byte[7:0]
Programmable biquad 10, D1 coefficient byte[31:24]
Programmable biquad 10, D1 coefficient byte[23:16]
Programmable biquad 10, D1 coefficient byte[15:8]
Programmable biquad 10, D1 coefficient byte[7:0]
Programmable biquad 10, D2 coefficient byte[31:24]
Programmable biquad 10, D2 coefficient byte[23:16]
Programmable biquad 10, D2 coefficient byte[15:8]
Programmable biquad 10, D2 coefficient byte[7:0]
Programmable biquad 11, N0 coefficient byte[31:24]
Programmable biquad 11, N0 coefficient byte[23:16]
Programmable biquad 11, N0 coefficient byte[15:8]
Programmable biquad 11, N0 coefficient byte[7:0]
Programmable biquad 11, N1 coefficient byte[31:24]
Programmable biquad 11, N1 coefficient byte[23:16]
Programmable biquad 11, N1 coefficient byte[15:8]
BQ8_D2_BYT3[7:0]
BQ8_D2_BYT4[7:0]
BQ9_N0_BYT1[7:0]
BQ9_N0_BYT2[7:0]
BQ9_N0_BYT3[7:0]
BQ9_N0_BYT4[7:0]
BQ9_N1_BYT1[7:0]
BQ9_N1_BYT2[7:0]
BQ9_N1_BYT3[7:0]
BQ9_N1_BYT4[7:0]
BQ9_N2_BYT1[7:0]
BQ9_N2_BYT2[7:0]
BQ9_N2_BYT3[7:0]
BQ9_N2_BYT4[7:0]
BQ9_D1_BYT1[7:0]
BQ9_D1_BYT2[7:0]
BQ9_D1_BYT3[7:0]
BQ9_D1_BYT4[7:0]
BQ9_D2_BYT1[7:0]
BQ9_D2_BYT2[7:0]
BQ9_D2_BYT3[7:0]
BQ9_D2_BYT4[7:0]
BQ10_N0_BYT1[7:0]
BQ10_N0_BYT2[7:0]
BQ10_N0_BYT3[7:0]
BQ10_N0_BYT4[7:0]
BQ10_N1_BYT1[7:0]
BQ10_N1_BYT2[7:0]
BQ10_N1_BYT3[7:0]
BQ10_N1_BYT4[7:0]
BQ10_N2_BYT1[7:0]
BQ10_N2_BYT2[7:0]
BQ10_N2_BYT3[7:0]
BQ10_N2_BYT4[7:0]
BQ10_D1_BYT1[7:0]
BQ10_D1_BYT2[7:0]
BQ10_D1_BYT3[7:0]
BQ10_D1_BYT4[7:0]
BQ10_D2_BYT1[7:0]
BQ10_D2_BYT2[7:0]
BQ10_D2_BYT3[7:0]
BQ10_D2_BYT4[7:0]
BQ11_N0_BYT1[7:0]
BQ11_N0_BYT2[7:0]
BQ11_N0_BYT3[7:0]
BQ11_N0_BYT4[7:0]
BQ11_N1_BYT1[7:0]
BQ11_N1_BYT2[7:0]
BQ11_N1_BYT3[7:0]
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表8-188. Page 3 Programmable Coefficient Registers (continued)
ADDRESS
ACRONYM
BQ11_N1_BYT4[7:0]
BQ11_N2_BYT1[7:0]
RESET VALUE
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
REGISTER DESCRIPTION
Programmable biquad 11, N1 coefficient byte[7:0]
Programmable biquad 11, N2 coefficient byte[31:24]
Programmable biquad 11, N2 coefficient byte[23:16]
Programmable biquad 11, N2 coefficient byte[15:8]
Programmable biquad 11, N2 coefficient byte[7:0]
Programmable biquad 11, D1 coefficient byte[31:24]
Programmable biquad 11, D1 coefficient byte[23:16]
Programmable biquad 11, D1 coefficient byte[15:8]
Programmable biquad 11, D1 coefficient byte[7:0]
Programmable biquad 11, D2 coefficient byte[31:24]
Programmable biquad 11, D2 coefficient byte[23:16]
Programmable biquad 11, D2 coefficient byte[15:8]
Programmable biquad 11, D2 coefficient byte[7:0]
Programmable biquad 12, N0 coefficient byte[31:24]
Programmable biquad 12, N0 coefficient byte[23:16]
Programmable biquad 12, N0 coefficient byte[15:8]
Programmable biquad 12, N0 coefficient byte[7:0]
Programmable biquad 12, N1 coefficient byte[31:24]
Programmable biquad 12, N1 coefficient byte[23:16]
Programmable biquad 12, N1 coefficient byte[15:8]
Programmable biquad 12, N1 coefficient byte[7:0]
Programmable biquad 12, N2 coefficient byte[31:24]
Programmable biquad 12, N2 coefficient byte[23:16]
Programmable biquad 12, N2 coefficient byte[15:8]
Programmable biquad 12, N2 coefficient byte[7:0]
Programmable biquad 12, D1 coefficient byte[31:24]
Programmable biquad 12, D1 coefficient byte[23:16]
Programmable biquad 12, D1 coefficient byte[15:8]
Programmable biquad 12, D1 coefficient byte[7:0]
Programmable biquad 12, D2 coefficient byte[31:24]
Programmable biquad 12, D2 coefficient byte[23:16]
Programmable biquad 12, D2 coefficient byte[15:8]
Programmable biquad 12, D2 coefficient byte[7:0]
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
BQ11_N2_BYT2[7:0]
BQ11_N2_BYT3[7:0]
BQ11_N2_BYT4[7:0]
BQ11_D1_BYT1[7:0]
BQ11_D1_BYT2[7:0]
BQ11_D1_BYT3[7:0]
BQ11_D1_BYT4[7:0]
BQ11_D2_BYT1[7:0]
BQ11_D2_BYT2[7:0]
BQ11_D2_BYT3[7:0]
BQ11_D2_BYT4[7:0]
BQ12_N0_BYT1[7:0]
BQ12_N0_BYT2[7:0]
BQ12_N0_BYT3[7:0]
BQ12_N0_BYT4[7:0]
BQ12_N1_BYT1[7:0]
BQ12_N1_BYT2[7:0]
BQ12_N1_BYT3[7:0]
BQ12_N1_BYT4[7:0]
BQ12_N2_BYT1[7:0]
BQ12_N2_BYT2[7:0]
BQ12_N2_BYT3[7:0]
BQ12_N2_BYT4[7:0]
BQ12_D1_BYT1[7:0]
BQ12_D1_BYT2[7:0]
BQ12_D1_BYT3[7:0]
BQ12_D1_BYT4[7:0]
BQ12_D2_BYT1[7:0]
BQ12_D2_BYT2[7:0]
BQ12_D2_BYT3[7:0]
BQ12_D2_BYT4[7:0]
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8.6.2.3 Programmable Coefficient Registers: Page 4
This register page (shown in 表 8-189) consists of the programmable coefficients for mixer 1 to mixer 4 and the
first-order IIR filter. All mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format.
The value of 0x7FFFFFFF is equivalent to +1 (0-dB gain), the value 0x00000000 is equivalent to mute (zero
data) and all values in between set the mixer attenuation computed using 方程式 4. If the MSB is set to '1' then
the attenuation remains the same but the signal phase is inverted. All IIR filter programmable coefficients are 32-
bit, two’s complement numbers. For a successful coefficient register transaction, the host device must write
and read all four bytes starting with the most significant byte (BYT1) for a target coefficient register transaction.
When using SPI for a coefficient register read transaction, the device transits the first byte as a dummy read
byte; therefore, the host must read five bytes, including the first dummy read byte and the last four bytes
corresponding to the coefficient register value starting with the most significant byte (BYT1).
hex2dec (value) / 231
(4)
表8-189. Page 4 Programmable Coefficient Registers
ADDRESS
ACRONYM
RESET VALUE
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
REGISTER DESCRIPTION
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
PAGE[7:0]
节8.6.1.2.1
MIX1_CH1_BYT1[7:0]
MIX1_CH1_BYT2[7:0]
MIX1_CH1_BYT3[7:0]
MIX1_CH1_BYT4[7:0]
MIX1_CH2_BYT1[7:0]
MIX1_CH2_BYT2[7:0]
MIX1_CH2_BYT3[7:0]
MIX1_CH2_BYT4[7:0]
MIX1_CH3_BYT1[7:0]
MIX1_CH3_BYT2[7:0]
MIX1_CH3_BYT3[7:0]
MIX1_CH3_BYT4[7:0]
MIX1_CH4_BYT1[7:0]
MIX1_CH4_BYT2[7:0]
MIX1_CH4_BYT3[7:0]
MIX1_CH4_BYT4[7:0]
MIX2_CH1_BYT1[7:0]
MIX2_CH1_BYT2[7:0]
MIX2_CH1_BYT3[7:0]
MIX2_CH1_BYT4[7:0]
MIX2_CH2_BYT1[7:0]
MIX2_CH2_BYT2[7:0]
MIX2_CH2_BYT3[7:0]
MIX2_CH2_BYT4[7:0]
MIX2_CH3_BYT1[7:0]
MIX2_CH3_BYT2[7:0]
MIX2_CH3_BYT3[7:0]
MIX2_CH3_BYT4[7:0]
MIX2_CH4_BYT1[7:0]
MIX2_CH4_BYT2[7:0]
MIX2_CH4_BYT3[7:0]
MIX2_CH4_BYT4[7:0]
MIX3_CH1_BYT1[7:0]
MIX3_CH1_BYT2[7:0]
MIX3_CH1_BYT3[7:0]
Digital mixer 1, channel 1 coefficient byte[31:24]
Digital mixer 1, channel 1 coefficient byte[23:16]
Digital mixer 1, channel 1 coefficient byte[15:8]
Digital mixer 1, channel 1 coefficient byte[7:0]
Digital mixer 1, channel 2 coefficient byte[31:24]
Digital mixer 1, channel 2 coefficient byte[23:16]
Digital mixer 1, channel 2 coefficient byte[15:8]
Digital mixer 1, channel 2 coefficient byte[7:0]
Digital mixer 1, channel 3 coefficient byte[31:24]
Digital mixer 1, channel 3 coefficient byte[23:16]
Digital mixer 1, channel 3 coefficient byte[15:8]
Digital mixer 1, channel 3 coefficient byte[7:0]
Digital mixer 1, channel 4 coefficient byte[31:24]
Digital mixer 1, channel 4 coefficient byte[23:16]
Digital mixer 1, channel 4 coefficient byte[15:8]
Digital mixer 1, channel 4 coefficient byte[7:0]
Digital mixer 2, channel 1 coefficient byte[31:24]
Digital mixer 2, channel 1 coefficient byte[23:16]
Digital mixer 2, channel 1 coefficient byte[15:8]
Digital mixer 2, channel 1 coefficient byte[7:0]
Digital mixer 2, channel 2 coefficient byte[31:24]
Digital mixer 2, channel 2 coefficient byte[23:16]
Digital mixer 2, channel 2 coefficient byte[15:8]
Digital mixer 2, channel 2 coefficient byte[7:0]
Digital mixer 2, channel 3 coefficient byte[31:24]
Digital mixer 2, channel 3 coefficient byte[23:16]
Digital mixer 2, channel 3 coefficient byte[15:8]
Digital mixer 2, channel 3 coefficient byte[7:0]
Digital mixer 2, channel 4 coefficient byte[31:24]
Digital mixer 2, channel 4 coefficient byte[23:16]
Digital mixer 2, channel 4 coefficient byte[15:8]
Digital mixer 2, channel 4 coefficient byte[7:0]
Digital mixer 3, channel 1 coefficient byte[31:24]
Digital mixer 3, channel 1 coefficient byte[23:16]
Digital mixer 3, channel 1 coefficient byte[15:8]
Copyright © 2021 Texas Instruments Incorporated
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表8-189. Page 4 Programmable Coefficient Registers (continued)
ADDRESS
ACRONYM
RESET VALUE
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
REGISTER DESCRIPTION
Digital mixer 3, channel 1 coefficient byte[7:0]
Digital mixer 3, channel 2 coefficient byte[31:24]
Digital mixer 3, channel 2 coefficient byte[23:16]
Digital mixer 3, channel 2 coefficient byte[15:8]
Digital mixer 3, channel 2 coefficient byte[7:0]
Digital mixer 3, channel 3 coefficient byte[31:24]
Digital mixer 3, channel 3 coefficient byte[23:16]
Digital mixer 3, channel 3 coefficient byte[15:8]
Digital mixer 3, channel 3 coefficient byte[7:0]
Digital mixer 3, channel 4 coefficient byte[31:24]
Digital mixer 3, channel 4 coefficient byte[23:16]
Digital mixer 3, channel 4 coefficient byte[15:8]
Digital mixer 3, channel 4 coefficient byte[7:0]
Digital mixer 4, channel 1 coefficient byte[31:24]
Digital mixer 4, channel 1 coefficient byte[23:16]
Digital mixer 4, channel 1 coefficient byte[15:8]
Digital mixer 4, channel 1 coefficient byte[7:0]
Digital mixer 4, channel 2 coefficient byte[31:24]
Digital mixer 4, channel 2 coefficient byte[23:16]
Digital mixer 4, channel 2 coefficient byte[15:8]
Digital mixer 4, channel 2 coefficient byte[7:0]
Digital mixer 4, channel 3 coefficient byte[31:24]
Digital mixer 4, channel 3 coefficient byte[23:16]
Digital mixer 4, channel 3 coefficient byte[15:8]
Digital mixer 4, channel 3 coefficient byte[7:0]
Digital mixer 4, channel 4 coefficient byte[31:24]
Digital mixer 4, channel 4 coefficient byte[23:16]
Digital mixer 4, channel 4 coefficient byte[15:8]
Digital mixer 4, channel 4 coefficient byte[7:0]
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
MIX3_CH1_BYT4[7:0]
MIX3_CH2_BYT1[7:0]
MIX3_CH2_BYT2[7:0]
MIX3_CH2_BYT3[7:0]
MIX3_CH2_BYT4[7:0]
MIX3_CH3_BYT1[7:0]
MIX3_CH3_BYT2[7:0]
MIX3_CH3_BYT3[7:0]
MIX3_CH3_BYT4[7:0]
MIX3_CH4_BYT1[7:0]
MIX3_CH4_BYT2[7:0]
MIX3_CH4_BYT3[7:0]
MIX3_CH4_BYT4[7:0]
MIX4_CH1_BYT1[7:0]
MIX4_CH1_BYT2[7:0]
MIX4_CH1_BYT3[7:0]
MIX4_CH1_BYT4[7:0]
MIX4_CH2_BYT1[7:0]
MIX4_CH2_BYT2[7:0]
MIX4_CH2_BYT3[7:0]
MIX4_CH2_BYT4[7:0]
MIX4_CH3_BYT1[7:0]
MIX4_CH3_BYT2[7:0]
MIX4_CH3_BYT3[7:0]
MIX4_CH3_BYT4[7:0]
MIX4_CH4_BYT1[7:0]
MIX4_CH4_BYT2[7:0]
MIX4_CH4_BYT3[7:0]
MIX4_CH4_BYT4[7:0]
IIR_N0_BYT1[7:0]
Programmable first-order IIR, N0 coefficient byte[31:24]
Programmable first-order IIR, N0 coefficient byte[23:16]
Programmable first-order IIR, N0 coefficient byte[15:8]
Programmable first-order IIR, N0 coefficient byte[7:0]
Programmable first-order IIR, N1 coefficient byte[31:24]
Programmable first-order IIR, N1 coefficient byte[23:16]
Programmable first-order IIR, N1 coefficient byte[15:8]
Programmable first-order IIR, N1 coefficient byte[7:0]
Programmable first-order IIR, D1 coefficient byte[31:24]
Programmable first-order IIR, D1 coefficient byte[23:16]
Programmable first-order IIR, D1 coefficient byte[15:8]
Programmable first-order IIR, D1 coefficient byte[7:0]
IIR_N0_BYT2[7:0]
IIR_N0_BYT3[7:0]
IIR_N0_BYT4[7:0]
IIR_N1_BYT1[7:0]
IIR_N1_BYT2[7:0]
IIR_N1_BYT3[7:0]
IIR_N1_BYT4[7:0]
IIR_D1_BYT1[7:0]
IIR_D1_BYT2[7:0]
IIR_D1_BYT3[7:0]
IIR_D1_BYT4[7:0]
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The PCM6480-Q1 is a multichannel, automotive qualified audio analog-to-digital converter (ADC) that supports
output sample rates of up to 768 kHz. The PCM6480-Q1 is a high-performance audio converter that supports
simultaneous sampling of up to a 4-channel analog microphone or a line input along with up to a 4-channel
digital pulse density-modulation (PDM) microphone input. The device integration enables both an in-cabin active
noise cancellation (ANC) and a voice recognition (VR) application in a very efficient manner by using the analog
and digital microphones input sampling simultaneously. The PCM6480-Q1 is intended for automotive
applications such as vehicle cabin active noise cancellation, hands-free in-vehicle communication, emergency
call, and multi-media applications. This device integrates a host of features to reduce cost, board space, and
power consumption in space-constrained automotive subsystem designs.
Communication to the PCM6480-Q1 for configuration of the control registers is supported using an I2C or SPI
interface. The device supports a highly flexible audio serial interface (TDM, I2S, or LJ) to transmit audio data
seamlessly in the system across devices.
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9.2 Typical Application
9.2.1 Four-Channel Analog Microphone and Four-Channel PDM Microphone Simultaneous Recording
Using the PCM6480-Q1
图 9-1 shows a typical configuration of the PCM6480-Q1 for an application using four analog microphones and
four digital PDM microphones for simultaneous recording operation with an I2C control interface and the TDM
audio data slave interface.
2.2 ꢀF
3.3 V
(3.0 V to 3.6 V)
2.2 ꢀF
10 ꢀF
1 ꢀF
3.3 V
(3.0 V to 3.6 V)
0.1 ꢀF
GND
1 ꢀF
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
GND
VBAT_IN
(Max 18V)
2.2µH
GND
VBAT_IN
GND
GND
10 ꢀF
1 ꢀF
DREG
GND
0.1 ꢀF
MICBIAS
GND
VDD
IN1P
IN1M
10 ꢀF
Mic 1
3.3 V
(3.0 V to 3.6 V)
OR
IOVDD
1.8 V
(1.65 V to 1.95 V)
0.1 ꢀF
GND
GND
Thermal Pad
(VSS)
IN2P
IN2M
PCM6480-Q1
Mic 2
GND
ADDR1_MISO
(ADDR1)
GND
IN3P
IN3M
GND
GND
Mic 3
ADDR0_SCLK
(ADDR0)
GND
IN4P
IN4M
Mic 4
R2 ꢁ
R2 ꢁ
GND
VDD
SEL
CLK
VDD
SEL
CLK
VDD
0.1 ꢀF
GND
VDD
0.1 ꢀF
GND
DMIC3
Rterm
DMIC1
Rterm
Rterm
DOUT
VSS
DOUT
VSS
Host
Processor
VDD
SEL
VSS
VDD
CLK
CLK
VDD
0.1 ꢀF
GND
VDD
0.1 ꢀF
GND
Rterm
DMIC4
SEL
DMIC2
VSS
Rterm
DOUT
DOUT
Rterm
图9-1. Four-Channel Analog Microphone and Four-Channel Digital Microphone Simultaenous Recording
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9.2.1.1 Design Requirements
表9-1 lists the design parameters for this application.
表9-1. Design Parameters
KEY PARAMETER
SPECIFICATION
AVDD, BSTVDD
AVDD supply current
IOVDD
3.3 V
28 mA (PLL on, all eight-channel record, fS = 44.1 kHz)
1.8 V or 3.3 V
< 28 mA (MICBIAS voltage = 8 V, microphone impedance = 680 Ω
and R1 = 340 Ω)
Maximum MICBIAS current
9.2.1.2 Detailed Design Procedure
This section describes the necessary steps to configure the PCM6480-Q1 for this specific application. The
following steps give a sequence of items that must be executed in the time between powering the device up and
reading data from the device or transitioning from one mode to other mode of operation.
1. Apply Power to Device:
a. Power up the IOVDD, AVDD, and BSTVDD power supplies, keeping the SHDNZ pin voltage low
b. The device now goes into hardware shutdown mode (ultra-low-power mode < 1 µA)
2. Transition From Hardware Shutdown Mode to Sleep Mode (or Software Shutdown Mode):
a. Release SHDNZ only when the IOVDD, AVDD, and BSTVDD power supplies settle to the steady-state
operating voltage
b. Wait for at least 1 ms to allow the device to initialize the internal registers
c. The device now goes into sleep mode (low-power mode < 20 µA)
3. Transition From Sleep Mode to Active Mode Whenever Required for the Record Operation:
a. Wake-up the device by writing P0_R2 to disable sleep mode
b. Wait for at least 1ms to allow the device internal wake-up sequence to complete
c. Override the default configuration registers or programmable coefficients value as required (optional)
d. Enable all desired input channels by writing P0_R115
e. Enable all desired audio serial interface output channels by writing P0_R116
f. Power-up the ADC, MICBIAS, and PLL by writing P0_R117
g. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
This specific step can be done at any point in the sequence after step a
See the Phase-Locked Loop (PLL) and Clock Generation section for the supported sample rates and the
BCLK to FSYNC ratio
h. The device recording data are now sent to the host processor via the TDM audio serial data bus
i. Wait for at least 10 ms to allow the MICBIAS to power up
j. Enable the fault diagnostics for all desired input channels by writing P0_R100
4. Transition From Active Mode to Sleep Mode (Again) as Required in the System Low Power:
a. Disable the fault diagnostics for all desired input channels by writing P0_R100
b. Go to sleep mode by writing P0_R2 to enable sleep mode
c. Wait at least 20 ms to allow the volume to gradually ramp down and for all blocks to power down
d. Read P0_R119 to check the device shutdown and sleep mode status
e. If the device P0_R119_D7 status bit is 1'b1, then stop FSYNC and BCLK in the system
f. The device now goes into sleep mode (low-power mode < 20 µA) and retains all register values
5. Transition From Sleep Mode to Active Mode (Again) as Required for the Record Operation:
a. Wake-up the device by writing P0_R2 to disable sleep mode
b. Wait for at least 1 ms to allow the device internal wake-up sequence to complete
c. Apply FSYNC and BCLK with the desired output sample rates and BCLK to FSYNC ratio
d. The device recording data are now sent to the host processor via the TDM audio serial data bus
e. Wait for at least 10 ms to allow the MICBIAS to power up
f. Enable the fault diagnostics for all desired input channels by writing P0_R100
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6. Repeat Step 4 and Step 5 as Required for Mode Transitions
7. Assert the SHDNZ Pin Low to Enter Hardware Shutdown Mode (Again) at Any Time
8. Follow Step 2 Onwards to Exit Hardware Shutdown Mode (Again)
9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
This section provides a typical EVM I2C register control script that shows how to set up the PCM6480-Q1 in a 4-
channel digital PDM input and a 4-channel analog microphone record mode with differential inputs.
#
# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#
#
# ==> comment delimiter
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# Refer to the PCM6xx0-Q1 EVM user guide for key jumper settings and audio connections:
#
# 4-channel differential analog input : INP1/INM1 - Ch1, INP2/INM2 - Ch2, INP3/INM3 - Ch3 and INP4/
INM4 - Ch4
# High swing mode enabled
# 4-channel digital PDM input : PDMDIN1_GPI1 - Ch5 and Ch6 and PDMDIN2_GPI2 - Ch7 and Ch8
# FSYNC = 44.1 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD, AVDD and BSTVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD, AVDD and BSTVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
# Wake-up device by I2C write into P0_R2 using internal AREG
w 90 0281
#
# Powerdown MICBIAS and ADC channels on fault detection (overtemperature, and so forth)
w 90 28 10
#
# Configure channel 1 DC-coupled, differential microphone input with high-swing mode
w 90 3C 18
#
# Configure channel 2 DC-coupled, differential microphone input with high-swing mode
w 90 41 18
#
# Configure channel 3 DC-coupled, differential microphone input with high-swing mode
w 90 46 18
#
# Configure channel 4 DC-coupled, differential microphone input with high-swing mode
w 90 4B 18
#
# Configure CH5_INSRC as Digital PDM Input by I2C write into P0_R80
w 98 50 40
#
# Configure CH6_INSRC as Digital PDM Input by I2C write into P0_R85
w 98 55 40
#
# Configure CH7_INSRC as Digital PDM Input by I2C write into P0_R90
w 98 5A 40
#
# Configure CH8_INSRC as Digital PDM Input by I2C write into P0_R95
w 98 5F 40
#
# Configure PDMCLK1_GPIO2 as PDMCLK by I2C write into P0_R34
w 98 22 41
#
# Configure PDMCLK1_GPIO3 as PDMCLK by I2C write into P0_R35
w 98 23 41
#
# Configure PDMDIN1_GPI1 as PDMDIN1 by I2C write into P0_R36
w 98 24 E0
#
# Configure PDMDIN2_GPI2 as PDMDIN2 by I2C write into P0_R37
w 98 25 F0
#
# Enable input channel 1 to channel 4 by I2C write into P0_R115
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w 90 73 FF
#
# Enable ASI output channel 1 to channel 4 slots by I2C write into P0_R116
w 90 74 FF
#
# Power-up ADC,MICBIAS and PLL by I2C write into P0_R117
w 90 75 E0
#
# Apply FSYNC = 44.1 kHz and BCLK = 11.2896 MHz and
# Start recording data by host on ASI bus with TDM protocol 32-bit channel word length
#
# Wait for 10 ms.
# Enable diagnostics for channel 1 to channel 4 by I2C write into P0_R100
w 90 64 F0
#
9.2.1.3 Application Curves
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 44.1 kHz, 32-bit
audio data, BCLK = 256 × fS, TDM slave mode, PLL on, channel gain = 0 dB, linear phase decimation filter, and
MICBIAS programmed voltage = 8 V (unless otherwise noted); all measurements are done on the EVM by
feeding the device analog input and PDM digital input signal using audio precision, however, in the real system
application, the device performance is expected to be limited by single-bit PDM modulator digital microphone
output performance; all performance measurements are done with a 20-kHz, low-pass filter and an A-weighted
filter (unless otherwise noted)
DC-coupled differential microphone input with DC common-
mode 1NxP = ~6 V and INxM = ~2 V, high swing mode
enabled, measured using an external audio input source
DC-coupled differential microphone input with DC common-
mode 1NxP = ~6 V and INxM = ~2 V, high swing mode
enabled, measured using an external audio input source
图9-2. Analog Inputs FFT With a –60-dBr Input
图9-3. Analog Inputs THD+N vs Input Amplitude
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4th-order PDM modulator with PDMCLKx = 2.8224 MHz
4th-order PDM modulator with PDMCLKx = 2.8224 MHz
图9-5. PDM Inputs THD+N vs Input Amplitude
图9-4. PDM Inputs FFT With a –60-dBFS Input
9.3 What To Do and What Not To Do
In master mode operation with I2S or LJ format, the device generates FSYNC half a cycle earlier than the normal
protocol timing behavior expected. This timing behavior can still function for most of the system, however for
further details and a suggested workaround for this weakness, see the Configuring and Operating
TLV320ADCx140 as Audio Bus Master application report.
The automatic gain controller (AGC) feature has some limitation when using sampling rates lower than 44.1 kHz.
For further details about this limitation, see the Using the Automatic Gain Controller in PCM6xx0-Q1 application
report.
For I2C operation, if the ADDR0_SCLK pin is tied high, then the I2C bus must remain idle (which means the
SDA_SSZ and SCL_MOSI pins must be high) when the SHDNZ pin is released from low to high.
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10 Power Supply Recommendations
The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, keep
the SHDNZ pin low until the IOVDD supply voltage settles to a stable and supported operating voltage range.
After the IOVDD and AVDD supplies are stable, set the SHDNZ pin high to initialize the device. BSTVDD can be
either applied along with AVDD or later but before turning on the MICBIAS. 图 10-1 shows the power supply
sequencing requirements.
AVDD
t1
t3
IOVDD
SHDNZ
t4
t2
图10-1. Power-Supply Sequencing Requirement
For the supply power-up requirement, t1 and t2 must be at least 100 µs. For the supply power-down requirement,
t3 and t4 must be at least 10 ms. This time allows the device to ramp down the volume on the record data, and
power down the analog and digital blocks, and lastly put the device into hardware shutdown mode. The device
can also be immediately put into hardware shutdown mode from active mode if SHDNZ_CFG[1:0] is set to 2'b00
using the P0_R5_D[3:2] bits. In that case, t3 and t4 are required to be at least 100 µs.
Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a
power-up event is at least 100 ms. For a supply ramp rate slower than 0.1 V/ms, the host device must apply a
software reset as the first transaction before configuring the device.
After releasing SHDNZ, or after a software reset, delay any additional I2C or SPI transactions to the device for at
least 2 ms to allow the device to initialize the internal registers. See the Device Functional Modes section to
operate the device in various modes after the device power supplies are settled to the recommended operating
voltage levels.
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11 Layout
11.1 Layout Guidelines
Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in
the context of a specific PCB design. However, the following guidelines can optimize the device performance:
• Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, the area directly
under the device, to the ground planes. This connection helps dissipate heat from the device.
• The decoupling capacitors for the power supplies must be placed close to the device pins.
• The supply decoupling capacitors used must be of a ceramic type with low ESR.
• The boost converter inductor and decoupling capacitors for the power supplies must be placed close to the
device pins.
• Route analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing
digital and analog signals to avoid undesirable crosstalk.
• The device internal voltage references must be filtered using external capacitors. Place the filter capacitors
near the VREF pin for optimal performance.
• Directly tap the MICBIAS pin to avoid common impedance when routing the biasing or supply for multiple
microphones to avoid coupling across microphones.
• Place the MICBIAS capacitor (with low equivalent series resistance) close to the device with minimal trace
impedance.
• Use MICBIAS and BSTOUT capacitors with a high voltage rating (> 25V) to support higher voltage MICBIAS
operation.
• An external circuit must be used to suppress or filter the amount of high-frequency electromagnetic
interference (EMI) noise found in the microphone input path resulting from long cables (if used) in the system.
• Use ground planes to provide the lowest impedance for power and signal current between the device and the
decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and
all device grounds must be connected directly to that area.
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11.2 Layout Example
Audio output and digital interface
1: AVDD
2: AREG
24: ADDR0_SCLK
23: ADDR1_MISO
22: SHDNZ
3: BSTVDD
4: BSTSW
5: BSTOUT
21: VBAT_IN
20: PDMCLK1_GPIO2
19: PDMDIN1_GPI1
18: PDMCLK2_GPIO3
17: PDMDIN2_GPI2
6: MICBIAS
7: VREF
8: AVSS
Analog input signals
图11-1. Layout Example of the PCM6480-Q1
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
PurePath™ console graphical development suite
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Multiple PCM6xx0-Q1 Devices With Shared TDM and I2C Bus application report
• Texas Instruments, PCM6xx0-Q1 Programmable Biquad Filter Configuration and Applications application
report
• Texas Instruments, PCM6xx0-Q1 Sampling Rates and Programmable Processing Blocks Supported
application report
• Texas Instruments, PCM6xx0-Q1 Integrated Analog Anti-Aliasing Filter and Flexible Digital Filter application
report
• Texas Instruments, Configuring and Operating TLV320ADCx140 as Audio Bus Master application report
• Texas Instruments, Using the Automatic Gain Controller in PCM6xx0-Q1 application report
• Texas Instruments, PCM6xx0-Q1 Fault Diagnostics Features application report
• Texas Instruments, Scalable Automotive Audio Solutions Using the PCM6xx0-Q1 Family of Products
application report
• Texas Instruments, PCM6xx0-Q1 Use-Case Scenarios in Automotive Audio Applications application report
• Texas Instruments, PCM6xx0-Q1 AC-Coupled External Resistor Calculator
• Texas Instruments, PCM6xx0-Q1 SIMULATION IBIS Models
• Texas Instruments, PCM6xx0Q1EVM-PDK Evaluation Module user's guide
• Texas Instruments, PurePath™ Console Graphical Development Suite for Audio System Design and
Development development suite
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
PurePath™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM6480QRTVRQ1
ACTIVE
WQFN
RTV
32
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PCM6480
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM6480QRTVRQ1
WQFN
RTV
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTV 32
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
PCM6480QRTVRQ1
3000
Pack Materials-Page 2
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