PCMD3140-Q1_技术文档

PCMD3140-Q1

ZHCSPD7A –APRIL 2022 –REVISED SEPTEMBER 2022

PCMD3140-Q1 四通道、PDM 输入至TDM 或I²S 输出转换器

1 特性

3 说明

• 4 通道PDM 麦克风同步转换

PCMD3140-Q1 是一款高性能脉冲密度调制 (PDM) 输

入至时分多路复用 (TDM) 或 I²S 输出转换器，最多可

支持对 PDM 麦克风输入的四个数字通道进行同步采

样。该器件集成了可编程数字音量控制、麦克风偏置电

压、锁相环 (PLL)、可编程高通滤波器 (HPF)、双二阶

滤波器、低延迟滤波器模式，并可实现高达 768 kHz

的输出采样率。该器件支持时分多路复用 (TDM)、I²S

或左对齐 (LJ) 音频格式，并可通过 I²C 接口进行控

制。此外，PCMD3140-Q1 还支持主从模式选择，从

而实现音频总线接口操作。这些集成的高性能特性，以

及采用 3.3V 或 1.8V 单电源供电的功能，使该器件非

常适用于远场麦克风录音应用中空间受限的音频系统。

• PDM 输入至TDM 或I²S 输出转换器性能：

– 127 dB 动态范围(DR)，带高性能5 阶PDM 输

入

– 117 dB 动态范围(DR)，带高性能4 阶PDM 输

入

• 通道相加模式，DR 性能，带高性能4 阶PDM 输

入：

– 120 dB，2 通道相加

• 可编程PDM 时钟输出：

– 768 kHz 至6.144 MHz

• 可编程输出采样率(f_S)：

– 8 kHz 至768 kHz

PCMD3140-Q1 的额定工作温度范围为 –40°C 至

+125°C，并且采用20 引脚WQFN 封装。

• 可编程通道设置：

– 数字音量控制：–100 dB 至27 dB

– 增益校准：0.1 dB 分辨率

– 相位校准：163 ns 分辨率

• 麦克风偏置或电源电压生成

• 话音激活检测(VAD)

• 低延迟信号处理滤波器选择

• 可编程HPF 和双二阶数字滤波器

• I²C 控制

器件信息

器件型号⁽¹⁾

封装尺寸（标称值）

封装

3.00mm × 3.00mm，间距

为0.5mm

PCMD3140-Q1

WQFN (20)

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

PLL and Clock Generation

• 集成高性能音频PLL

• 自动时钟分频器设置配置

• 音频串行数据接口：

FSYNC

PDMDIN1_GPI1

BCLK

4-Channel

Digital PDM

Microphones

Simultaneous

Conversion

Programmable

Digital Filters,

Biquads

Audio Serial

Interface

– 格式：TDM、I²S 或左对齐(LJ)

– 字长：16 位、20 位、24 位或32 位

– 主/从接口

SDOUT

PDMCLK_GPO1

PDMDIN2_GPI2

(TDM, I²S, LJ)

SDA

SCL

• 单电源运行：3.3V 或1.8V

• I/O 电源运行：3.3V 或1.8V

• 1.8V 电源电压下的功耗：

MICBIAS, Regulators and

Voltage Reference

I²C Interface

GPIO1

VREF

Thermal Pad

(VSS)

AVDD

DREG

AVSS

IOVDD

AREG

– 16 kHz 采样率下为2.8 mW/通道

– 48 kHz 采样率下为3.6 mW/通道

简化版方框图

2 应用

• 汽车主动噪声消除

• 汽车音响主机

• 后座娱乐系统

• 数字驾驶舱处理单元

• 远程信息处理控制单元

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBASAH3

PCMD3140-Q1

ZHCSPD7A –APRIL 2022 –REVISED SEPTEMBER 2022

www.ti.com.cn

Table of Contents

7.1 Overview...................................................................15

7.2 Functional Block Diagram.........................................16

7.3 Feature Description...................................................16

7.4 Device Functional Modes..........................................50

7.5 Programming............................................................ 51

7.6 Register Maps...........................................................54

8 Application and Implementation..................................93

8.1 Application Information............................................. 93

8.2 Typical Application.................................................... 93

8.3 What to Do and What Not to Do............................... 96

9 Power Supply Recommendations................................97

10 Layout.........................................................................100

10.1 Layout Guidelines................................................. 100

10.2 Layout Example.................................................... 100

11 Device and Documentation Support........................101

11.1 Documentation Support........................................ 101

11.2 接收文档更新通知................................................. 101

11.3 支持资源................................................................101

11.4 Trademarks........................................................... 101

11.5 Electrostatic Discharge Caution............................101

11.6 术语表................................................................... 101

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Timing Requirements: I²C Interface............................8

6.7 Switching Characteristics: I²C Interface......................9

6.8 Timing Requirements: TDM, I²S or LJ Interface......... 9

6.9 Switching Characteristics: TDM, I²S or LJ

Interface........................................................................ 9

Timing Requirements: PDM Digital Microphone

Interface...................................................................... 10

6.10 Switching Characteristics: PDM Digial

Microphone Interface...................................................10

6.11 Timing Diagrams..................................................... 10

6.12 Typical Characteristics............................................12

7 Detailed Description......................................................15

Information.................................................................. 101

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (April 2022) to Revision A (September 2022)

Page

• 将文档状态从预告信息更改为量产数据...............................................................................................................1

• 将器件状态更新为“生产数据”......................................................................................................................... 1

2

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5 Pin Configuration and Functions

20

VSS

15

VSS

NC

1

14

13

12

11

DREG

SCL

2

3

4

Thermal Pad (VSS)

PDMDIN1_GPI1

PDMCLK_GPO1

SDA

GPIO1

5

VSS

10

Not to scale

图5-1. RTE Package, 20-Pin WQFN With Exposed Thermal Pad, Top View

表5-1. Pin Functions

TYPE

DESCRIPTION

NO.

1

NAME

NC

No connect

No connection

2

NC

Digital input 1 (multipurpose functions such as digital microphones data, PLL input clock

source, and so forth).

3

4

PDMDIN1_GPI1

PDMCLK_GPO1

Digital input

General-purpose digital output 1 (multipurpose functions such as digital microphone clock,

interrupt, and so forth).

Digital output

Device ground internally shorted to thermal pad. Short this package corner pin directly to

the board ground plane. See the package drawing at the end of this document for corner

pin dimensions.

5

VSS

Ground supply

6

7

8

9

SDOUT

BCLK

Digital output

Digital I/O

Audio serial data interface bus output.

Audio serial data interface bus bit clock.

FSYNC

IOVDD

Digital I/O

Audio serial data interface bus frame synchronization signal.

Digital I/O power supply (1.8 V or 3.3 V, nominal).

Digital supply

Device ground internally shorted to thermal pad. Short this package corner pin directly to

the board ground plane. See the package drawing at the end of this document for corner

pin dimensions.

10

11

VSS

Ground supply

Digital I/O

General-purpose digital input/output 1 (multipurpose functions such as digital microphones

clock or data, PLL input clock source, interrupt, and so forth).

GPIO1

12

13

SDA

SCL

Digital I/O

Data pin for I²C control bus.

Clock pin for I²C control bus.

Digital input

Digital regulator output voltage for digital core supply (1.5 V, nominal). Connect a 10-µF

and a 0.1-µF low ESR capacitor in parallel to the device ground (VSS).

14

DREG

Digital supply

Device ground internally shorted to thermal pad. Short this package corner pin directly to

the board ground plane. See the package drawing at the end of this document for corner

pin dimensions.

15

16

17

18

VSS

AVDD

AREG

VREF

Ground supply

Analog supply

Analog

Analog power (1.8 V or 3.3 V, nominal).

Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) or external

analog power (1.8 V, nominal). Connect a 10-µF and a 0.1-µF low ESR capacitor in parallel

to the analog ground (AVSS).

Analog reference voltage filter output. Connect a 1-µF to the analog ground (AVSS).

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

Digital Input 2. MICBIAS output or general-purpose digital input 2 (multipurpose functions

such as digital microphones data, MICBIAS, PLL input clock source, and so forth). If used

as MICBIAS output, then connect a 1 µF to analog ground (AVSS)

19

PDMDIN2_GPI2

VSS

Analog output/digital input

Device ground internally shorted to thermal pad. Short this package corner pin directly to

the board ground plane. See the package drawing at the end of this document for corner

pin dimensions.

20

Ground supply

Thermal Pad

(VSS)

Thermal pad is shorted to the internal device ground. Short the thermal pad directly to the

board ground plane.

Thermal Pad

6 Specifications

6.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

3.9

UNIT

V

AVDD to AVSS

Supply voltage

AREG to AVSS

2.0

IOVDD to VSS (thermal pad)

AVSS to VSS (thermal pad)

3.9

Ground voltage differences

Digital input voltage

0.3

V

Digital input except PDMDINx_GPIx pins voltage to VSS

(thermal pad)

IOVDD + 0.3

AVDD + 0.3

–0.3

V

Digital input PDMDINx_GPIx pins voltage to VSS

(thermal pad)

Operating ambient, T_A

Junction, T_J

125

150

–40

–65

Temperature

°C

Storage, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

POWER

Analog supply voltage AVDD to AVSS (AREG is generated using onchip regulator) -

AVDD 3.3-V operation

3.0

1.7

3.3

1.8

3.6

1.9

AVDD,

V

AREG⁽¹⁾

Analog supply voltage AVDD and AREG to AVSS (AREG internal regulator is

shutdown) - AVDD 1.8-V operation

IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation

IOVDD

3.0

3.3

1.8

3.6

IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation

1.65

1.95

INPUTS

Digital input except PDMDIN1_GPI1 and PDMDIN2_GPI2 pins voltage to VSS

(thermal pad)

0

IOVDD

AVDD

V

Digital input PDMDIN1_GPI1 and PDMDIN2_GPI2 pins voltage to VSS (thermal pad)

TEMPERATURE

T_A

Operating ambient temperature

125

°C

–40

OTHERS

GPIOx or GPIx (used as MCLK input) clock frequency

36.864

400

MHz

pF

SCL and SDA bus capacitance for I²C interface supports standard-mode and fast-

mode

C_b

C_L

SCL and SDA bus capacitance for I²C interface supports fast-mode plus

Digital output load capacitance

550

50

20

pF

(1) AVSS and VSS (thermal pad): all ground pins must be tied together and must not differ in voltage by more than 0.2 V.

6.4 Thermal Information

PCMD3140

THERMAL METRIC⁽¹⁾

RTW (WQFN)

24 PINS

55.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

33.1

23.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

ψ_JT

23.3

ψ_JB

R_θJC(bot)

16.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

at T_A= 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f_IN= 1-kHz sinusoidal signal, f_S= 48 kHz, PDMCLKx = 64 × f_S,32-bit audio

data, BCLK = 256 × f_S, TDM slave mode, and PLL on (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PERFORMANCE FOR PDM INPUT CONVERSION

No signal, input generated using 5^th-order PDM

modulator

130

118

127

116

Signal-to-noise ratio, A-

weighted^{(1) (2) (3)}

SNR

DR

dB

No signal, input generated using 4^th-order PDM

modulator

–60-dB full-scale signal input, input generated using 5^th-

order PDM modulator

Dynamic range, A-

weighted^{(2) (3)}

dB

–60-dB full-scale signal input, input generated using 4^th-

order PDM modulator

OTHER PARAMETERS

Digital volume control

Programmable 0.5-dB steps

Programmable

27

768

32

dB

–100

7.35

16

range

Output data sample rate

kHz

Bits

Output data sample word

length

Programmable

First-order IIR filter with programmable coefficients,

–3-dB point (default setting)

Digital high-pass filter cutoff

frequency

12

Hz

MICROPHONE BIAS

BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor

between MICBIAS and AVSS

MICBIAS noise

MICBIAS voltage

2.1

µV_RMS

MICBIAS programmed to VREF and VREF programmed

to either 2.75 V, 2.5 V, or 1.375 V

VREF

V

MICBIAS programmed to VREF × 1.096 and VREF

programmed to either 2.75 V, 2.5 V, or 1.375 V

VREF ×

1.096

MICBIAS voltage

Bypass to AVDD with 5-mA load

V

AVDD –0.2

MICBIAS current drive

5

1

mA

MICBIAS programmed to either VREF or VREF × 1.096,

measured up to max load

MICBIAS load regulation

0

0.6

%

MICBIAS overcurrent

protection threshold

6.1

mA

DIGITAL I/O

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2,

SDA and SCL, IOVDD 1.8-V operation

0.35 ×

IOVDD

–0.3

Low-level digital input logic

voltage threshold

V_IL

V

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2,

SDA and SCL, IOVDD 3.3-V operation

0.8

IOVDD + 0.3

0.45

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2,

SDA and SCL, IOVDD 1.8-V operation

0.65 ×

IOVDD

High-level digital input logic

voltage threshold

V_IH

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2,

SDA and SCL, IOVDD 3.3-V operation

2

All digital pins except PDMCLK_GPO1, SDA and SCL,

I_OL= –2 mA, IOVDD 1.8-V operation

Low-level digital output

voltage

V_OL

All digital pins except PDMCLK_GPO1, SDA and SCL,

I_OL= –2 mA, IOVDD 3.3-V operation

0.4

All digital pins except PDMCLK_GPO1, SDA and SCL,

I_OH= 2 mA, IOVDD 1.8-V operation

IOVDD –

0.45

High-level digital output

voltage

V_OH

V

All digital pins except PDMCLK_GPO1, SDA and SCL,

I_OH= 2 mA, IOVDD 3.3-V operation

2.4

–0.5

Low-level digital input logic

voltage threshold

V_IL(I2C)

SDA and SCL

0.3 x IOVDD

IOVDD + 0.5

0.4

V

High-level digital input logic

voltage threshold

V_IH(I2C)

V_OL1(I2C)

V_OL2(I2C)

SDA and SCL

0.7 x IOVDD

Low-level digital output

voltage

SDA, I_OL(I2C)= –3 mA, IOVDD > 2 V

SDA, I_OL(I2C)= –2 mA, IOVDD ≤2 V

Low-level digital output

voltage

0.2 x IOVDD

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at T_A= 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f_IN= 1-kHz sinusoidal signal, f_S= 48 kHz, PDMCLKx = 64 × f_S,32-bit audio

data, BCLK = 256 × f_S, TDM slave mode, and PLL on (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SDA, V_OL(I2C)= 0.4 V, standard-mode or fast-mode

SDA, V_OL(I2C)= 0.4 V, fast-mode plus

MIN

TYP

MAX

UNIT

3

Low-level digital output

current

I_OL(I2C)

mA

20

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2

pins,

input = IOVDD

Input logic-high leakage for

digital inputs

I_IH

0.1

5

µA

–5

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2

pins,

input = 0 V

Input logic-low leakage for

digital inputs

I_IL

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

1.8-V operation

0.35 × AVDD

0.8

–0.3

Low-level digital input logic

voltage threshold

V_IL(GPIx)

V

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

3.3-V operation

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

1.8-V operation

0.65 × AVDD

2

AVDD + 0.3

0.45

High-level digital input logic

voltage threshold

V_IH(GPIx)

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

3.3-V operation

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, I_OL= –2

mA, AVDD 1.8-V operation

Low-level digital output

voltage

V_OL(GPOx)

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, I_OL= –2

mA, AVDD 3.3-V operation

0.4

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, I_OH= 2

mA, AVDD 1.8-V operation

AVDD –

0.45

High-level digital output

voltage

V_OH(GPOx)

V

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, I_OH= 2

mA, AVDD 3.3-V operation

2.4

–5

Input logic-high leakage for PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input =

digital inputs AVDD

I_IH(GPIx)

I_IL(GPIx)

C_IN

0.1

5

µA

pF

Input logic-high leakage for PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input = 0

digital inputs

V

Input capacitance for digital

inputs

All digital pins

Pulldown resistance for

digital I/O pins when

asserted on

R_PD

20

kΩ

TYPICAL SUPPLY CURRENT CONSUMPTION

I_AVDDAll external clocks stopped, AVDD = 3.3 V

5

All external clocks stopped, AVDD = 1.8 V, external

AREG supply (AREG shorted to AVDD)

Current consumption in

sleep mode (software

shutdown mode)

I_AVDD

10

µA

I_IOVDD

I_AVDD

All external clocks stopped, IOVDD = 3.3 V

All external clocks stopped, IOVDD = 1.8 V

AVDD = 3.3 V

0.5

0.3

9.1

AVDD = 1.8 V, external AREG supply (AREG shorted to

AVDD)

Current consumption with

4-channel PDM input

recording

I_AVDD

8.1

mA

I_IOVDD

I_AVDD

IOVDD = 3.3 V

IOVDD = 1.8 V

AVDD = 3.3 V

0.1

0.05

7.3

Current consumption with

4-channel PDM input

recording, f_S= 16 kHz,

PDMCLKx = 96 × f_S, PLL

on and BCLK = 384 × f_S

AVDD = 1.8 V, external AREG supply (AREG shorted to

AVDD)

I_AVDD

6.3

I_IOVDD

IOVDD = 3.3 V

IOVDD = 1.8 V

0.1

0.05

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with no signal, measured A-weighted over a 20-Hz to 20-

kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter

removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) The device performance parameters, SNR, DR and THD+N, are mainly limited by single-bit PDM modulator generated data output.

The THD+N peformance for single-bit PDM modulator output itself is generally not so good for signal above –10-dB full-scale.

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6.6 Timing Requirements: I²C Interface

at T_A= 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 6-1 for timing diagram

MIN

NOM

MAX

UNIT

STANDARD-MODE

f_SCL

SCL clock frequency

0

4

100

kHz

Hold time (repeated) START condition. After this period, the first clock pulse is

generated.

t_HD;STA

μs

t_LOW

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated START condition

Data hold time

4.7

4

μs

ns

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

4.7

0

3.45

Data setup time

250

SDA and SCL rise time

1000

300

ns

t_f

SDA and SCL fall time

ns

t_SU;STO

t_BUF

Setup time for STOP condition

Bus free time between a STOP and START condition

4

μs

4.7

FAST-MODE

f_SCL

SCL clock frequency

0

400

kHz

Hold time (repeated) START condition. After this period, the first clock pulse is

generated.

t_HD;STA

0.6

μs

t_LOW

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated START condition

Data hold time

1.3

0.6

0

μs

ns

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

0.9

Data setup time

100

20

SDA and SCL rise time

300

ns

20 ×

(IOVDD / 5.5

V)

t_f

SDA and SCL fall time

ns

t_SU;STO

Setup time for STOP condition

0.6

1.3

μs

t_BUF

Bus free time between a STOP and START condition

FAST-MODE PLUS

f_SCL

SCL clock frequency

0

1000

kHz

Hold time (repeated) START condition. After this period, the first clock pulse is

generated.

t_HD;STA

0.26

μs

t_LOW

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated START condition

Data hold time

0.5

0.26

0

μs

ns

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

Data setup time

50

SDA and SCL rise time

120

ns

20 ×

(IOVDD / 5.5

V)

t_f

SDA and SCL fall time

ns

t_SU;STO

t_BUF

Setup time for STOP condition

0.26

0.5

μs

Bus free time between a STOP and START condition

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6.7 Switching Characteristics: I²C Interface

at T_A= 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 6-1 for timing diagram

PARAMETER

TEST CONDITIONS

MIN

250

TYP

MAX

1250

850

UNIT

Standard-mode

t_d(SDA)

SCL to SDA delay

Fast-mode

ns

Fast-mode plus

400

6.8 Timing Requirements: TDM, I²S or LJ Interface

at T_A= 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 6-2 for timing

diagram

MIN

40

25

8

NOM

MAX

UNIT

ns

t_(BCLK)

BCLK period

t_H(BCLK)

t_L(BCLK)

t_SU(FSYNC)

t_HLD(FSYNC)

t_r(BCLK)

BCLK high pulse duration ⁽¹⁾

BCLK low pulse duration ⁽¹⁾

FSYNC setup time

FSYNC hold time

BCLK rise time

ns

8

ns

10% - 90% rise time⁽²⁾

90% - 10% fall time⁽²⁾

10

ns

t_f(BCLK)

BCLK fall time

ns

(1) The BCLK minimum high or low pulse duration can be relaxed to 14 ns (to meet the timing specifications), if the SDOUT data line is

latched on the same BCLK edge polarity as the edge used by the device to transmit SDOUT data.

(2) BCLK maximum rise and fall time can be relaxed to 13ns if BCLK frequency used in the system is below 20MHz. This can cause noise

increase due to higher clock jitter.

6.9 Switching Characteristics: TDM, I²S or LJ Interface

at T_A= 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 6-2 for timing

diagram

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_{d(SDOUT-BCLK)}

t_{d(SDOUT-FSYNC)}

BCLK to SDOUT delay

50% of BCLK to 50% of SDOUT

3

18

ns

FSYNC to SDOUT delay in TDM

or LJ mode (for MSB data with

TX_OFFSET = 0)

50% of FSYNC to 50% of

SDOUT

18

ns

BCLK output clock frequency:

master mode ⁽¹⁾

f_(BCLK)

24.576

MHz

ns

BCLK high pulse duration: master

mode

t_H(BCLK)

t_L(BCLK)

t_d(FSYNC)

14

3

BCLK low pulse duration: master

mode

ns

BCLK to FSYNC delay: master

mode

50% of BCLK to 50% of FSYNC

18

ns

t_r(BCLK)

t_f(BCLK)

BCLK rise time: master mode

BCLK fall time: master mode

10% - 90% rise time

90% - 10% fall time

8

ns

(1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched

on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

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Timing Requirements: PDM Digital Microphone Interface

at T_A= 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 6-3 for timing

diagram

MIN

30

0

NOM

MAX

UNIT

ns

t_SU(PDMDINx)

t_HLD(PDMDINx)

PDMDINx setup time

PDMDINx hold time

ns

6.10 Switching Characteristics: PDM Digial Microphone Interface

at T_A= 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 6-3 for timing

diagram

PARAMETER

TEST CONDITIONS

MIN

0.768

72

TYP

MAX

UNIT

MHz

ns

f_(PDMCLK)

t_H(PDMCLK)

t_L(PDMCLK)

t_r(PDMCLK)

t_f(PDMCLK)

PDMCLK clock frequency

PDMCLK high pulse duration

PDMCLK low pulse duration

PDMCLK rise time

6.144

72

ns

10% - 90% rise time

18

ns

PDMCLK fall time

90% - 10% fall time

ns

6.11 Timing Diagrams

SDA

t_BUF

t_HD;STA

t_LOW

t_r

t_d(SDA)

SCL

t_HD;STA

t_HD;DAT

t_HIGH

t_SU;DAT

t_SU;STA

t_SU;STO

STO

STA

t_f

STA

STO

图6-1. I²C Interface Timing Diagram

FSYNC

t_SU(FSYNC)

t_HLD(FSYNC)

t_(BCLK)

t_L(BCLK)

BCLK

t_H(BCLK)

t_r(BCLK)

t_f(BCLK)

t_d(FSYNC)

t_{d(SDOUT-BCLK)}

t_{d(SDOUT-FSYNC)}

SDOUT

图6-2. TDM (With BCLK_POL = 1), I²S, and LJ Interface Timing Diagram

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t_SU(PDMDINx)

t_HLD(PDMDINx)t_SU(PDMDINx)

t_HLD(PDMDINx)

t_H(PDMCLK)

t_L(PDMCLK)

PDMCLK

PDMDINx

t_(PDMCLK)

t_f(PDMCLK)

t_r(PDMCLK)

Falling Edge Captured

Rising Edge Captured

图6-3. PDM Digital Microphone Interface Timing Diagram

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6.12 Typical Characteristics

at T_A= 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f_IN= 1-kHz sinusoidal signal, f_S= 48 kHz, PDMCLKx = 64 × f_S, 32-bit audio

data, BCLK = 256 × f_S, TDM slave mode, PLL on, and linear phase decimation filter (unless otherwise noted); all

performance measurements are done with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted); all

measurements are done by feeding the device PDM digital input signal using audio precision

-60

Channel-1

Channel-2

Channel-3

Channel-4

Channel-1

Channel-2

Channel-3

Channel-4

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

-130

-115

-100

-85

-70

-55

-40

-25

-10 -1

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

D002

Input Amplitude (dB)

Frequency (Hz)

TDH0D0+1

5th-order PDM modulator with PDMCLKx = 3.072 MHz

图6-4. THD+N vs Input Amplitude

图6-5. THD+N vs Input Frequency With a –20-dBr Input

20

10

0

Channel-1

Channel-2

-20

Channel-3

0

Channel-4

-40

-10

-20

-30

-40

-50

-60

-70

-80

-60

-80

-100

-120

-140

-160

-180

-200

-90

Channel-1

Channel-2

Channel-3

-100

-110

Channel-4

-120

20 30 50 70100 200300 500 1000 2000

5000 1000020000

100000

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

D004

Frequency (Hz)

Freq

Frequency (Hz)

D003

5th-order PDM modulator with PDMCLKx = 3.072 MHz

图6-6. Frequency Response With a –20-dBr Input

图6-7. FFT With a –60-dBr Input

-60

Channel-1

Channel-2

Channel-1

Channel-2

Channel-3

-70

Channel-4

-70

Channel-4

-80

-90

-100

-110

-120

-130

-90

-100

-110

-120

-130

-115

-100

-85

-70

-55

-40

-25

-10 -1

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

Input Amplitude (dB)

Frequency (Hz)

Freq

TDH0D0+5

D006

4th-order PDM modulator with PDMCLKx = 3.072 MHz

图6-8. THD+N vs Input Amplitude

图6-9. THD+N vs Input Frequency With a –20-dBr Input

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6.12 Typical Characteristics (continued)

at T_A= 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f_IN= 1-kHz sinusoidal signal, f_S= 48 kHz, PDMCLKx = 64 × f_S, 32-bit audio

data, BCLK = 256 × f_S, TDM slave mode, PLL on, and linear phase decimation filter (unless otherwise noted); all

performance measurements are done with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted); all

measurements are done by feeding the device PDM digital input signal using audio precision

20

10

0

-20

Channel-1

Channel-2

Channel-3

Channel-4

0

-40

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-60

-80

-100

-120

-140

-160

-180

-200

Channel-1

Channel-2

Channel-3

Channel-4

20 30 50 70100 200300 500 1000 2000

5000 1000020000

100000

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

D008

Frequency (Hz)

Freq

Frequency (Hz)

D007

4th-order PDM modulator with PDMCLKx = 3.072 MHz

图6-10. Frequency Response With a –20-dBr Input

图6-11. FFT With a –60-dBr Input

-60

Channel-1

Channel-2

Channel-1

Channel-2

Channel-3

-70

Channel-4

Channel-3

-70

Channel-4

-80

-90

-100

-110

-120

-130

-90

-100

-110

-120

-130

-115

-100

-85

-70

-55

-40

-25

-10 -1

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

D010

Input Amplitude (dB)

Frequency (Hz)

TDH0D0+9

4th-order PDM modulator with PDMCLKx = 1.536 MHz

图6-12. THD+N vs Input Amplitude

图6-13. THD+N vs Input Frequency With a –20-dBr Input

20

10

0

Channel-1

Channel-2

-20

Channel-3

0

Channel-4

-40

-10

-20

-30

-40

-50

-60

-70

-80

-60

-80

-100

-120

-140

-160

-180

-200

-90

Channel-1

Channel-2

Channel-3

-100

-110

Channel-4

-120

20 30 50 70100 200300 500 1000 2000

5000 1000020000

100000

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

D012

Frequency (Hz)

Freq

Frequency (Hz)

D011

4th-order PDM modulator with PDMCLKx = 1.536 MHz

图6-14. Frequency Response With a –20-dBr Input

图6-15. FFT With a –60-dBr Input

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6.12 Typical Characteristics (continued)

at T_A= 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f_IN= 1-kHz sinusoidal signal, f_S= 48 kHz, PDMCLKx = 64 × f_S, 32-bit audio

data, BCLK = 256 × f_S, TDM slave mode, PLL on, and linear phase decimation filter (unless otherwise noted); all

performance measurements are done with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted); all

measurements are done by feeding the device PDM digital input signal using audio precision

-60

Channel-1

Channel-2

Channel-1

Channel-2

-70

-80

-90

-100

-110

-120

-130

-100

-110

-120

-130

-115

-100

-85

-70

-55

-40

-25

-10

0

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

D014

Input Amplitude (dB)

Frequency (Hz)

TDH0D1+3

4th-order PDM modulator with PDMCLKx = 6.144 MHz

图6-16. THD+N vs Input Amplitude

图6-17. THD+N vs Input Frequency With a –20-dBr Input

20

0

Channel-1

Channel-2

Channel-1

10

Channel-2

-20

0

-10

-40

-60

-20

-30

-80

-40

-50

-100

-120

-140

-160

-180

-200

-60

-70

-80

-90

-100

-110

-120

20 30 50 70100 200300 500 1000 2000

5000 1000020000

100000

DF0re1q5

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

D016

Frequency (Hz)

4th-order PDM modulator with PDMCLKx = 6.144 MHz

图6-19. FFT With a –60-dBr Input

图6-18. Frequency Response With a –20-dBr Input

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7 Detailed Description

7.1 Overview

The PCMD3140-Q1 is a high-performance, low-power, flexible, 4-channel, pulse-density-modulation (PDM) input

to time-division multiplexing (TDM) or I²S audio output converter with extensive feature integration. This device

is intended for applications in voice-activated systems, portable computing, communication, and entertainment

applications. The low power consumption makes this device suitable for battery-powered, portable audio

systems. This device integrates a host of features that reduces cost, board space, and power consumption in

space-constrained, battery-powered, consumer, home, and industrial applications.

The PCMD3140-Q1 consists of the following blocks:

• Four-channel, pulse density modulation (PDM) digital microphone interface with high-performance decimation

filter

• Low-noise, microphone bias output to power the digital microphone

• Programmable decimation filters with linear-phase or low-latency filter

• Programmable digital volume control, biquad filters for each channel

• Programmable phase and gain calibration with fine resolution for each channel

• Programmable high-pass filter (HPF), and digital channel mixer

• Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks

• Integrated digital and analog voltage regulators to support single-supply operation

Communication to the PCMD3140-Q1 to configure the control registers is supported using an I²C interface. The

device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I²S, or left-justified (LJ)]

to transmit audio data seamlessly in the system across devices.

The device can support multiple devices by sharing the common TDM buses across devices. Moreover, the

device includes a daisy-chain feature as well. These features relax the shared TDM bus timing requirements and

board design complexities when operating multiple devices for applications requiring high audio data bandwidth.

表7-1 lists the reference abbreviations used throughout this document to registers that control the device.

表7-1. Abbreviations for Register References

REFERENCE

ABBREVIATION

DESCRIPTION

EXAMPLE

Single data bit. The value of a

single bit in a register.

Page y, register z, bit k

Py_Rz_Dk

Page 4, register 36, bit 0 = P4_R36_D0

Range of data bits. A range of

data bits (inclusive).

Page y, register z, bits k-m

Page y, register z

Py_Rz_D[k:m]

Py_Rz

Page 4, register 36, bits 3-0 = P4_R36_D[3:0]

Page 4, register 36 = P4_R36

One entire register. All eight

bits in the register as a unit.

Range of registers. A range of

registers in the same page.

Page y, registers z-n

Py_Rz-Rn

Page 4, registers 36, 37, 38 = P4_R36-R38

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7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Serial Interfaces

This device has two serial interfaces: control and audio data. The control serial interface is used for device

configuration. The audio data serial interface is used for transmitting audio data to the host device.

7.3.1.1 Control Serial Interfaces

The device control registers can be accessed using I²C communication to the device. The device operates with

a fixed I²C address and can be configured using this address.

7.3.1.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the PCMD3140-Q1 on the digital audio serial interface

(ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I²S

or left-justified protocols format, programmable data length options, very flexible master-slave configurability for

bus clock lines, and the ability to communicate with multiple devices within a system directly.

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The bus protocol TDM, I²S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0]

(P0_R7_D[7:6]) register bits. As shown in 表 7-2 and 表 7-3, these modes are all most significant byte (MSB)-

first, pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16,

20, 24, or 32 bits by configuring the ASI_WLEN[1:0] (P0_R7_D[5:4]) register bits.

表7-2. Audio Serial Interface Format

P0_R7_D[7:6] : ASI_FORMAT[1:0]

AUDIO SERIAL INTERFACE FORMAT

00 (default)

Time division multiplexing (TDM) mode

01

10

11

Inter IC sound (I²S) mode

Left-justified (LJ) mode

Reserved (do not use this setting)

表7-3. Audio Output Channel Data Word-Length

P0_R7_D[5:4] : ASI_WLEN[1:0]

AUDIO OUTPUT CHANNEL DATA WORD-LENGTH

00

01

Output channel data word-length set to 16 bits

Output channel data word-length set to 20 bits

Output channel data word-length set to 24 bits

Output channel data word-length set to 32 bits

10

11 (default)

The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the

same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio

data across the serial bus. The number of bit-clock cycles in a frame must accommodate multiple device active

output channels with the programmed data word length.

A frame consists of multiple time-division channel slots (up to 64) to allow all output channel audio data

transmissions to complete on the audio bus by a device or PCMD3140-Q1 and other Audio devices sharing the

same bus. The device supports up to four output channels that can be configured to place their audio data on

bus slot 0 to slot 63. 表 7-4 lists the output channel slot configuration settings. In I²S and LJ mode, the slots are

divided into two sets, left-channel slots and right-channel slots, as described in the 节 7.3.1.2.2 and 节 7.3.1.2.3

sections.

表7-4. Output Channel Slot Assignment Settings

P0_R11_D[5:0] : CH1_SLOT[5:0]

00 0000 = 0d (default)

00 0001 = 1d

OUTPUT CHANNEL 1 SLOT ASSIGNMENT

Slot 0 for TDM or left slot 0 for I²S, LJ.

Slot 1 for TDM or left slot 1 for I²S, LJ.

…

01 1111 = 31d

10 0000 = 32d

Slot 31 for TDM or left slot 31 for I²S, LJ.

Slot 32 for TDM or right slot 0 for I²S, LJ.

…

11 1110 = 62d

11 1111 = 63d

Slot 62 for TDM or right slot 30 for I²S, LJ.

Slot 63 for TDM or right slot 31 for I²S, LJ.

Similarly, the slot assignment setting for output channel 2 to channel 4 can be done using the CH2_SLOT

(P0_R12) to CH8_SLOT (P0_R18) registers, respectively.

The slot word length is the same as the output channel data word length set for the device. The output channel

data word length must be set to the same value for all PCMD3140-Q1 devices if all devices share the same ASI

bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available

bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data

word length configured.

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The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by

up to 31 cycles of the bit clock. 表7-5 lists the programmable offset configuration settings.

表7-5. Programmable Offset Settings for the ASI Slot Start

P0_R8_D[4:0] : TX_OFFSET[4:0]

PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START

0 0000 = 0d (default)

The device follows the standard protocol timing without any offset.

Slot start is offset by one BCLK cycle, as compared to standard protocol timing.

For I²S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to

standard protocol timing.

0 0001 = 1d

......

Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.

For I²S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to

standard protocol timing.

1 1110 = 30d

Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.

For I²S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to

standard protocol timing.

1 1111 = 31d

The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio

data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using

the FSYNC_POL (P0_R7_D3) register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK,

which can be set using the BCLK_POL (P0_R7_D2) register bit.

7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface

In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data

first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and

each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.

图7-1 to 图7-4 illustrate the protocol timing for TDM operation with various configurations.

FSYNC

BCLK

SDOUT

N-1 N-2 N-3

2

1

0

N-1 N-2 N-3

2

1

0

N-1 N-2 N-3

2

1

0

N-1 N-2 N-3

2

1

0

Slot-1

(Word Length : N)

Slot-0

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

Slot-0

(Word Length : N)

(n+1)^thSample

n^thSample

图7-1. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)

FSYNC

BCLK

SDOUT

N-1

2

1

0

N-1 N-2 N-3

2

1

0

N-1 N-2 N-3

2

1

0

N-1

2

1

0

Slot-1

(Word Length : N)

Slot-0

(Word Length : N)

n^thSample

Slot-0

(Word Length : N)

(n+1)^thSample

Slot-2 to Slot-7

(Word Length : N)

TX_OFFSET = 2

图7-2. TDM Mode Protocol Timing (TX_OFFSET = 2)

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FSYNC

BCLK

1

0

N-1

2

1

0

N-1 N-2 N-3

2

1

0

2

1

0

N-1 N-2 N-3

0

N-1 N-2

3

2

1

0

N-1

SDOUT

Slot-1

(Word Length : N)

Slot-0

(Word Length : N)

Slot-0

(Word Length : N)

(n+1)^thSample

Slot-2 to Slot-7

(Word Length : N)

TX_OFFSET = 2

n^thSample

图7-3. TDM Mode Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 2)

FSYNC

BCLK

SDOUT

N-1 N-2 N-3

2

1

0

N-1 N-2 N-3

2

1

0

N-1 N-2 N-3

2

1

0

N-1 N-2 N-3

2

1

0

Slot-1

(Word Length : N)

Slot-0

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

Slot-0

(Word Length : N)

(n+1)^thSample

n^thSample

图7-4. TDM Mode Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)

For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or

equal to the number of active output channels times the programmed word length of the output channel data.

The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well. For a

higher BCLK frequency operation, using TDM mode with a TX_OFFSET value higher than 0 is recommended.

7.3.1.2.2 Inter IC Sound (I²S) Interface

The standard I²S protocol is defined for only two channels: left and right. The device extends the same protocol

timing for multichannel operation. In I²S mode, the MSB of the left slot 0 is transmitted on the falling edge of

BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the

remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of

BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission,

the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge

of BCLK. 图7-5 to 图7-8 illustrate the protocol timing for I²S operation with various configurations.

FSYNC

BCLK

SDOUT

N-1 N-2

1

0

N-1 N-2

1

0

N-1

1

0

N-1 N-2

1

0

1

0

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

Right

Slot-0

Right

Slot-2 to Slot-3

(Word Length : N) (Word Length : N)

Left

Slot-0

(Word Length : N)

(n+1)^thSample

n^thSample

图7-5. I²S Mode Standard Protocol Timing (TX_OFFSET = 0)

FSYNC

BCLK

SDOUT

N-1

1

0

N-1 N-2

1

0

N-1

1

0

N-1

1

0

1

0

Left

Slot-0

(Word Length : N) (Word Length : N)

Left

Slot-2 to Slot-3

Right

Slot-0

Right

Slot-2 to Slot-3

(Word Length : N) (Word Length : N)

Left

Slot-0

(Word Length : N)

(n+1)^thSample

TX_OFFSET = 1

n^thSample

图7-6. I²S Protocol Timing (TX_OFFSET = 1)

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FSYNC

BCLK

N-1 N-2

1

0

N-1 N-2

0

N-1

1

0

N-1

1

0

N-1 N-2

0

N-1

1

0

1

0

N-1 N-2

SDOUT

Left

Slot-0

(Word Length : N)

(n+1)^thSample

Left

Slot-1 to Slot-3

(Word Length : N)

Right

Slot-1 to Slot-3

(Word Length : N)

n^thSample

图7-7. I²S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)

FSYNC

BCLK

SDOUT

N-1 N-2

1

0

N-1 N-2

1

0

N-1

1

0

N-1 N-2

1

0

1

0

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

Right

Slot-0

Right

Slot-2 to Slot-3

(Word Length : N) (Word Length : N)

Left

Slot-0

(Word Length : N)

(n+1)^thSample

n^thSample

图7-8. I²S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)

For proper operation of the audio bus in I²S mode, the number of bit clocks per frame must be greater than or

equal to the number of active output channels (including left and right slots) times the programmed word length

of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater

than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high

pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots

times the data word length configured.

7.3.1.2.3 Left-Justified (LJ) Interface

The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol

timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle

after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK.

Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB

of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data

bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining

right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. 图 7-9 to 图 7-12

illustrate the protocol timing for LJ operation with various configurations.

FSYNC

BCLK

SDOUT

N-1 N-2

1

0

N-1 N-2

1

0

N-1

1

0

N-1 N-2

1

0

1

0

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

Right

Slot-0

Right

Slot-2 to Slot-3

(Word Length : N) (Word Length : N)

Left

Slot-0

(Word Length : N)

(n+1)^thSample

n^thSample

图7-9. LJ Mode Standard Protocol Timing (TX_OFFSET = 0)

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FSYNC

BCLK

SDOUT

N-1

1

0

N-1 N-2

1

0

N-1

1

0

N-1

1

0

1

0

Left

Slot-0

(Word Length : N) (Word Length : N)

Left

Slot-2 to Slot-3

Right

Slot-0

Right

Slot-2 to Slot-3

(Word Length : N) (Word Length : N)

Left

Slot-0

(Word Length : N)

(n+1)^thSample

TX_OFFSET = 2

n^thSample

图7-10. LJ Protocol Timing (TX_OFFSET = 2)

FSYNC

BCLK

N-1 N-2

1

0

N-1 N-2

0

N-1

1

0

N-1

1

0

N-1 N-2

0

N-1

1

0

N-1 N-2

1

0

SDOUT

Left

Slot-0

(Word Length : N)

(n+1)^thSample

Left

Slot-1 to Slot-3

(Word Length : N)

Right

Slot-1 to Slot-3

(Word Length : N)

n^thSample

图7-11. LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)

FSYNC

BCLK

SDOUT

N-1 N-2

1

0

N-1 N-2

1

0

N-1

1

0

N-1 N-2

1

0

1

0

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

Right

Slot-0

Right

Slot-2 to Slot-3

(Word Length : N) (Word Length : N)

Left

Slot-0

(Word Length : N)

(n+1)^thSample

TX_OFFSET = 1

n^thSample

图7-12. LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1)

For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or

equal to the number of active output channels (including left and right slots) times the programmed word length

of the output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater

than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC low

pulse must be number of BCLK cycles wide that is greater than or equal to the number of active right slots times

the data word length configured. For a higher BCLK frequency operation, using LJ mode with a TX_OFFSET

value higher than 0 is recommended.

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7.3.1.3 Using Multiple Devices With Shared Buses

The device has many supported features and flexible options that can be used in the system to seamlessly

connect the PCMD3140-Q1 and any other audio device by sharing a single common I²C control bus and an

audio serial interface bus. This architecture enables multiple applications to be applied to a system that require a

microphone array for beam-forming operations, audio conferencing, noise cancellation, and so forth. 图 7-13

shows a diagram of the PCMD3140-Q1 and PCMD3180 devices in a configuration where the control and audio

data buses are shared.

Control Bus – I²C Interface

PCMD3140-Q1

U1

PCMD3180-Q1

U2

Host Processor

Audio Data Bus – TDM, I²S, LJ Interface

图7-13. Multiple Devices With Shared Control and Audio Data Buses

The PCMD3140-Q1 consists of the following features to enable seamless connection and interaction of multiple

devices using a shared bus:

• I²C broadcast simultaneously writes to (or triggers) the PCMD3140-Q1 and PCMD3180-Q1 devices

• Supports up to 64 configuration output channel slots for the audio serial interface

• Tri-state feature (with enable and disable) for the unused audio data slots of the device

• Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus

• The GPIO1 or PDMCLK_GPO1 pin can be configured as a secondary output data lane for the audio serial

interface

• The GPIO1 or PDMDINx_GPIx pin can be used in a daisy-chain configuration of multiple devices

• Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface

• Programmable master and slave options for the audio serial interface

• Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices

The system can also connect multiple PCMD3140-Q1 devices in combination with PCMx120-Q1 devices by

sharing a single common I²C control bus and an audio serial interface bus. See the Multiple TLV320ADCx140 &

TLV320ADCx120 Devices With Shared TDM and I²C Bus application report for further details.

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7.3.2 Phase-Locked Loop (PLL) and Clock Generation

The device has a smart auto-configuration block to generate all necessary internal clocks required for the PDM

clock generation and the digital filter engine used for signal processing. This configuration is done by monitoring

the frequency of the FSYNC and BCLK signal on the audio bus.

The device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to

FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming.

表7-6 and 表7-7 list the supported FSYNC and BCLK frequencies.

表7-6. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies

BCLK (MHz)

BCLK TO

FSYNC

RATIO

FSYNC

(8 kHz)

FSYNC

(16 kHz)

FSYNC

(24 kHz)

FSYNC

(32 kHz)

FSYNC

(48 kHz)

FSYNC

(96 kHz)

FSYNC (192 FSYNC (384 FSYNC (768

kHz)

16

24

Reserved

0.256

0.384

0.576

0.512

0.768

1.152

1.536

2.304

3.072

6.144

12.288

4.608

9.216

18.432

32

0.512

0.768

1.024

1.536

3.072

6.144

12.288

24.576

48

0.384

0.768

1.152

1.536

2.304

4.608

9.216

18.432

Reserved

64

0.512

1.024

1.536

2.048

3.072

6.144

12.288

24.576

96

0.768

1.536

2.304

3.072

4.608

9.216

18.432

Reserved

128

192

256

384

512

1024

2048

1.024

2.048

3.072

4.096

6.144

12.288

18.432

24.576

Reserved

24.576

1.536

3.072

4.608

6.144

9.216

Reserved

2.048

4.096

6.144

8.192

12.288

18.432

24.576

Reserved

3.072

6.144

9.216

12.288

16.384

Reserved

4.096

8.192

12.288

24.576

Reserved

8.192

16.384

Reserved

16.384

表7-7. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies

BCLK (MHz)

BCLK TO

FSYNC

RATIO

FSYNC

(7.35 kHz)

FSYNC

(44.1 kHz)

FSYNC

(14.7 kHz) (22.05 kHz) (29.4 kHz)

(88.2 kHz) (176.4 kHz) (352.8 kHz) (705.6 kHz)

16

24

Reserved

0.3528

Reserved

0.3528

0.4704

0.7056

0.9408

1.4112

0.3528

0.5292

0.7056

1.0584

1.4112

0.4704

0.7056

1.0584

1.4112

2.1168

2.8224

4.2336

5.6448

8.4672

11.2896

16.9344

32

0.9408

1.4112

2.8224

5.6448

11.2896

22.5792

48

1.4112

2.1168

4.2336

8.4672

16.9344

Reserved

64

0.4704

1.8816

2.8224

5.6448

11.2896

22.5792

96

0.7056

2.1168

2.8224

4.2336

8.4672

16.9344

22.5792

Reserved

128

192

256

384

512

1024

2048

0.9408

1.8816

2.8224

3.7632

5.6448

7.5264

15.0528

Reserved

2.8224

4.2336

5.6448

8.4672

11.2896

22.5792

Reserved

3.7632

5.6448

11.2896

16.9344

22.5792

Reserved

1.4112

5.6448

8.4672

1.8816

7.5264

11.2896

16.9344

22.5792

Reserved

2.8224

11.2896

15.0528

Reserved

3.7632

7.5264

15.0528

The status register ASI_STS (P0_R21) captures the device auto detect result for the FSYNC frequency and the

BCLK to FSYNC ratio. If the device finds any unsupported combinations of FSYNC frequency and BCLK to

FSYNC ratios, the device generates an ASI clock-error interrupt and mutes the record channels accordingly.

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the

PDM clock generation and digital filter engine, as well as other control blocks. The device also supports an

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option to use BCLK, GPIO1, or the GPIx pin (as MCLK) as the audio clock source without using the PLL to

reduce power consumption. However, the PDM microphone performance may degrade based on jitter from the

external clock source, and some processing features may not be supported if the external audio clock source

frequency is not high enough. Therefore, TI recommends using the PLL for high-performance applications. More

details and information on how to configure and use the device in low-power mode without using the PLL are

discussed in the TLV320ADCx120 Power Consumption Matrix Across Various Usage Scenarios application

report.

The device also supports an audio bus master mode operation using the GPIO1 or GPIx pin (as MCLK) as the

reference input clock source and supports various flexible options and a wide variety of system clocks. More

details and information on master mode configuration and operation are discussed in the Configuring and

Operating TLV320ADCx120 as an Audio Bus Master application report.

The audio bus clock error detection and auto-detect feature automatically generates all internal clocks, but can

be disabled using the ASI_ERR (P0_R9_D5) and AUTO_CLK_CFG (P0_R19_D6) register bits, respectively. In

the system, this disable feature can be used to support custom clock frequencies that are not covered by the

auto detect scheme. For such application use cases, care must be taken to ensure that the multiple clock

dividers are all configured appropriately. Therefore, TI recommends using the PPC3 GUI for device configuration

settings; for more details see the ADCx120EVM-PDK Evaluation module user's guide and the PurePath^™

Console Graphical Development Suite for Audio System Design and Development.

7.3.3 Reference Voltage

The PCMD3140-Q1 achieves low-noise performance by internally generating a low-noise reference voltage. This

reference voltage is generated using a band-gap circuit with high PSRR performance and must be filtered

externally using a 1-µF capacitor connected from the VREF pin to analog ground (AVSS).

The value of this reference voltage can be configured using the P0_R59_D[1:0] register bits and must be set to

an appropriate value based on the AVDD supply voltage available in the system. The default VREF value is set

to 2.75 V, which require minimum AVDD voltage for this mode is 3 V. 表 7-8 lists the various VREF settings

supported along with required AVDD range for that configuration.

表7-8. VREF Programmable Settings

P0_R59_D[1:0] : VREF_SEL[1:0]

VREF OUTPUT VOLTAGE

AVDD RANGE REQUIREMENT

3 V to 3.6 V

00 (default)

2.75 V

2.5 V

01

10

11

2.8 V to 3.6 V

1.375 V

Reserved

1.7 V to 1.9 V

Reserved

To achieve low-power consumption, this audio reference block is powered down as described in the 节 7.4.1

section. When exiting sleep mode, the audio reference block is powered up using the internal fast-charge

scheme and the VREF pin settles to its steady-state voltage after the settling time (a function of the decoupling

capacitor on the VREF pin). This time is approximately equal to 3.5 ms when using a 1-μF decoupling capacitor.

If a higher-value decoupling capacitor is used on the VREF pin, the fast-charge setting must be reconfigured

using the VREF_QCHG (P0_R2_D[4:3]) register bits, which support options of 3.5 ms (default), 10 ms, 50 ms, or

100 ms.

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7.3.4 Microphone Bias

The device integrates a built-in, low-noise programmable microphone bias pin that can be used in the system for

providing the supply to the MEMS digital microphone. The MICBIAS pin must be connected to an external 1-µF

capacitor to analog ground (AVSS). The MICBIAS pin supports up to 5 mA of load current that can be used for

multiple microphones. When using this MICBIAS pin for biasing or supplying to multiple microphones, avoid any

common impedance on the board layout for the MICBIAS connection to minimize coupling across microphones.

In the system, if the MICBIAS pin is used as a supply for digital microphones, then TI recommends using the

MICBIAS configuration as AVDD, so that the digital microphone PDMCLKx and PDMDINx signals can be directly

interface to the PCMD3140-Q1 without using any external level shifters. 表 7-9 shows the available microphone

bias programmable options.

表7-9. MICBIAS Programmable Settings

P0_R59_D[6:4] : MBIAS_VAL[2:0]

P0_R59_D[1:0] : VREF_SEL[1:0]

MICBIAS OUTPUT VOLTAGE

2.75 V (same as the VREF output)

2.5 V (same as the VREF output)

1.375 V (same as the VREF output)

Reserved (do not use these settings)

Same as AVDD

00 (default)

000 (default)

01

10

001 to 101

110

XX

111

Reserved (do not use this setting)

The microphone bias output can be powered on or powered off (default) by configuring the MICBIAS_PDZ

(P0_R117_D7) register bit. Additionally, the device provides an option to configure the GPIO1 or GPIx pin to

directly control the microphone bias output powering on or off. This feature is useful to control the microphone

directly without engaging the host for I²C communication. The MICBIAS_PDZ (P0_R117_D7) register bit value is

ignored if the GPIO1 or GPIx pin is configured to set the microphone bias on or off.

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7.3.5 Digital PDM Microphone Record Channel

The device interfaces up to four digital pulse-density-modulation (PDM) microphones for simultaneous

conversion and uses high-order and high-performance decimation filters to generate pulse code modulation

(PCM) output data that can be transmitted on the audio serial interface to the host using either time-division

multiplexing (TDM), I²S, or left-justified (LJ) audio formats.

The device internally generates PDMCLK with a programmable frequency of either 6.144 MHz, 3.072 MHz,

1.536 MHz, or 768 kHz (for output data sample rates in multiples or submultiples of 48 kHz) or 5.6448 MHz,

2.8224 MHz, 1.4112 MHz, or 705.6 kHz (for output data sample rates in multiples or submultiples of 44.1 kHz)

using the PDMCLK_DIV[1:0] (P0_R31_D[1:0]) register bits. PDMCLK can be routed on the PDMCLKx_GPOx

pin. This clock can be connected to the external digital microphone device. The device also support control

register to independently configure each channel PDMDINx data to be latched using either rising edge or falling

edge. 图7-14 shows a connection diagram of the digital PDM microphones.

VDD

IOVDD

DATA

Digital

PDM

SEL

Microphone

U1

CLK

GND

PCMD3140-Q1

VDD

SEL

GPIx (PDMDINx)

GPOx (PDMCLK)

DATA

CLK

Digital

PDM

Microphone

U2

GND

图7-14. Digital PDM Microphones Connection Diagram to the PCMD3140-Q1

The single-bit output of the external digital microphone device can be connected to the GPIx pin. This single

data line can be shared by two digital microphones to place their data on the opposite edge of PDMCLK.

Internally, the device latches the steady value of the data on the rising edge of PDMCLK or the falling edge of

PDMCLK based on the configuration register bits set in P0_R32_D[7:4]. 图 7-15 shows the digital PDM

microphone interface timing diagram.

PDMCLK

PDMDINx

D1[n]

D2[n]

D1[n+1]

D2[n+1]

D1[n+2]

Mic-1

Data

Mic-2

Data

Mic-1

Data

Mic-2

Data

Mic-1

Data

(n+1)^thSample

(n+2)^thSample

n^thSample

图7-15. Digital PDM Microphone Protocol Timing Diagram

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7.3.6 Signal-Chain Processing

The PCMD3140-Q1 signal chain is comprised of high-performance, low-power, and highly flexible and

programmable digital processing blocks. The high performance and flexibility combined with a compact package

makes the PCMD3140-Q1 optimized for a wide variety of end-equipment and applications that require

multichannel audio capture. 图7-16 shows a conceptual block diagram that highlights the various building blocks

used in the signal chain, and how the blocks interact in the signal chain.

PDMCLK

High Performance

Decimation

Filters

PDM

Interface

Digital Microphone

Phase

Calibration

PDMDIN

Output

Channel

Data to ASI

Digital Summer/Mixer

(Applies to Ch1-Ch4

only)

Gain

Calibration

Biquad

Filters

Digital Volume

Control (DVC)

HPF

Ch1-Ch4 Processed Data after Gain

Calibration

图7-16. Signal-Chain Processing Flowchart

The device supports up to four digital PDM microphone recording channels for simultaneous operation. The

signal chain consists of various highly programmable digital processing blocks such as phase calibration, gain

calibration, high-pass filter, digital summer or mixer, biquad filters, and volume control. The details on these

processing blocks are discussed further in this section. Channels 1 to 4 in the signal chain block diagram of 图

7-16 are as described in this section.

The desired input channels for recording can be enabled or disabled by using the IN_CH_EN (P0_R115)

register, and the output channels for the audio serial interface can be enabled or disabled by using the

ASI_OUT_EN (P0_R116) register. In general, the device supports simultaneous power-up and power-down of all

active channels for simultaneous recording. However, based on the application needs, if some channels must be

powered-up or powered-down dynamically when the other channel recording is on, then that use case is

supported by setting the DYN_CH_PUPD_EN (P0_R117_D4) register bit to 1'b1 but do not power-down channel

1 in this mode of operation.

The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal

to be recorded by using a 176.4-kHz (or higher) sample rate.

For output sample rates of 48 kHz or lower, the device supports all features for 4-channel recording and various

programmable processing blocks. However, for output sample rates higher than 48 kHz, there are limitations in

the number of simultaneous channel recordings supported and the number of biquad filters and such. See the

TLV320ADCx120 Sampling Rates and Programmable Processing Blocks Supported application report for further

details.

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7.3.6.1 Programmable Digital Volume Control

The device has a programmable digital volume control with a range from –100 dB to 27 dB in steps of 0.5 dB

with the option to mute the channel recording. The digital volume control value can be changed dynamically

when the channel is powered-up and recording. During volume control changes, the soft ramp-up or ramp-down

volume feature is used internally to avoid any audible artifacts. Soft-stepping can be entirely disabled using the

DISABLE_SOFT_STEP (P0_R108_D4) register bit.

The digital volume control setting is independently available for each output channel, including the digital

microphone record channel. However, the device also supports an option to gang-up the volume control setting

for all channels together using the channel 1 digital volume control setting, regardless if channel 1 is powered up

or powered down. This gang-up can be enabled using the DVOL_GANG (P0_R108_D7) register bit.

表7-10 shows the programmable options available for the digital volume control.

表7-10. Digital Volume Control (DVC) Programmable Settings

P0_R62_D[7:0] : CH1_DVOL[7:0]

0000 0000 = 0d

DVC SETTING FOR OUTPUT CHANNEL 1

Output channel 1 DVC is set to mute

0000 0001 = 1d

Output channel 1 DVC is set to –100 dB

Output channel 1 DVC is set to –99.5 dB

Output channel 1 DVC is set to –99 dB

…

0000 0010 = 2d

0000 0011 = 3d

…

1100 1000 = 200d

1100 1001 = 201d (default)

1100 1010 = 202d

Output channel 1 DVC is set to –0.5 dB

Output channel 1 DVC is set to 0 dB

Output channel 1 DVC is set to 0.5 dB

…

1111 1101 = 253d

1111 1110 = 254d

1111 1111 = 255d

Output channel 1 DVC is set to 26 dB

Output channel 1 DVC is set to 26.5 dB

Output channel 1 DVC is set to 27 dB

Similarly, the digital volume control setting for output channel 2 to channel 4 can be configured using the

CH2_DVOL (P0_R67) to CH4_DVOL (P0_R77) register bits, respectively.

The internal digital processing engine soft ramps up the volume from a muted level to the programmed volume

level when the channel is powered up, and the internal digital processing engine soft ramps down the volume

from a programmed volume to mute when the channel is powered down. This soft-stepping of volume is done to

prevent abruptly powering up and powering down the record channel. This feature can also be entirely disabled

using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.

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7.3.6.2 Programmable Channel Gain Calibration

Along with the programmable channel gain and digital volume, this device also provides programmable channel

gain calibration. The gain of each channel can be finely calibrated or adjusted in steps of 0.1 dB for a range of –

0.8-dB to 0.7-dB gain error. This adjustment is useful when trying to match the gain across channels resulting

from external components and microphone sensitivity. This feature, in combination with the regular digital

volume control, allows the gains across all channels to be matched for a wide gain error range with a resolution

of 0.1 dB. 表7-11 shows the programmable options available for the channel gain calibration.

表7-11. Channel Gain Calibration Programmable Settings

P0_R63_D[7:4] : CH1_GCAL[3:0]

CHANNEL GAIN CALIBRATION SETTING FOR INPUT CHANNEL 1

0000 = 0d

Input channel 1 gain calibration is set to –0.8 dB

0001 = 1d

Input channel 1 gain calibration is set to –0.7 dB

…

1000 = 8d (default)

Input channel 1 gain calibration is set to 0 dB

…

1110 = 14d

1111 = 15d

Input channel 1 gain calibration is set to 0.6 dB

Input channel 1 gain calibration is set to 0.7 dB

Similarly, the channel gain calibration setting for input channel 2 to channel 4 can be configured using the

CH2_GCAL (P0_R68) to CH4_GCAL (P0_R78) register bits, respectively.

7.3.6.3 Programmable Channel Phase Calibration

In addition to the gain calibration, the phase delay in each channel can be finely calibrated or adjusted in steps

of one modulator clock cycle for a cycle range of 0 to 255 for the phase error. Phase calibration clock is

dependent on PDM clock used. For a PDM_CLK of 6.144 MHz (the output data sample rate is multiples or

submultiples of 48 kHz) or 5.6448 MHz (the output data sample rate is multiples or submultiples of 44.1 kHz), the

phase calibration clock is the same as the PDM_CLK. For a PDM_CLK equal to or lower than 3.072 MHz (the

output data sample rate is multiples or submultiples of 48 kHz), the phase calibration clock used is 3.072 MHz.

Similarly, for a PDM_CLK of 2.8224 MHz, 1.4112 MHz, or 705.6 kHz (the output data sample rate is multiples or

submultiples of 44.1 kHz), the phase calibration clock used is 2.8224MHz. This feature is very useful for many

applications that must match the phase with fine resolution between each channel, including any phase

mismatch across channels resulting from external components or microphones. 表 7-12 shows the available

programmable options for channel phase calibration for a digital microphone with a PDM_CLK of 6.144 MHz or

5.6448 MHz.

表7-12. Channel Phase Calibration Programmable Settings

P0_R64_D[7:0] : CH1_PCAL[7:0]

0000 0000 = 0d (default)

0000 0001 = 1d

CHANNEL PHASE CALIBRATION SETTING FOR INPUT CHANNEL 1

Input channel 1 phase calibration with no delay

Input channel 1 phase calibration delay is set to one cycle of the modulator clock

Input channel 1 phase calibration delay is set to two cycles of the modulator clock

0000 0010 = 2d

…

1111 1110 = 254d

1111 1111 = 255d

Input channel 1 phase calibration delay is set to 254 cycles of the modulator clock

Input channel 1 phase calibration delay is set to 255 cycles of the modulator clock

For a digital microphone interface with a PDM_CLK frequency below 3.072 MHz, the phase calibration range is

from 0 to 127 of the phase calibration clock (3.072 MHz for the output data sample rate is multiples or

submultiples of 48 kHz and 2.8224 MHz for the output data sample rate is multiples or submultiples of 44.1 kHz).

The phase calibration for a PDM_CLK frequency below 3.072 MHz can be configured using the CH1_PCAL[7:1]

register bits for channel 1.

Similarly, the channel phase calibration setting for input channel 2 to channel 4 can be configured using the

CH2_PCAL (P0_R69) to CH4_PCAL (P0_R79) register bits, respectively.

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7.3.6.4 Programmable Digital High-Pass Filter

To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data,

the device supports a programmable high-pass filter (HPF). The HPF is not a channel-independent filter setting

but is globally applicable for all the channels. This HPF is constructed using the first-order infinite impulse

response (IIR) filter, and is efficient enough to filter out possible DC components of the signal. 表7-13 shows the

predefined –3-dB cutoff frequencies available that can be set by using the HPF_SEL[1:0] register bits of

P0_R107. Additionally, to achieve a custom –3-dB cutoff frequency for a specific application, the device also

allows the first-order IIR filter coefficients to be programmed when the HPF_SEL[1:0] register bits are set to

2'b00. 图7-17 illustrates a frequency response plot for the HPF filter.

表7-13. HPF Programmable Settings

P0_R107_D[1:0] :

HPF_SEL[1:0]

-3-dB CUTOFF FREQUENCY

SETTING

-3-dB CUTOFF FREQUENCY AT

16-kHz SAMPLE RATE

-3-dB CUTOFF FREQUENCY AT

48-kHz SAMPLE RATE

00

01 (default)

10

Programmable 1st-order IIR filter

0.00025 × f_S

Programmable 1st-order IIR filter

4 Hz

32 Hz

128 Hz

12 Hz

96 Hz

0.002 × f_S

11

0.008 × f_S

384 Hz

3

0

-3

-6

-9

-12

-15

-18

-21

-24

-27

-30

-33

-36

-39

-42

-45

HPF -3 dB Cutoff = 0.00025 ì f_S

HPF -3 dB Cutoff = 0.002 ì f_S

HPF -3 dB Cutoff = 0.008 ì f_S

5E-5

0.0001

0.0005

0.001

Normalized Frequency (1/f_S

0.005

0.01

0.05

D003

)

图7-17. HPF Filter Frequency Response Plot

方程式1 gives the transfer function for the first-order programable IIR filter:

0₀+ 0₁V^F1

2³¹F &₁V^F1

: ;

* V =

(1)

The frequency response for this first-order programmable IIR filter with default coefficients is flat at a gain of 0 dB

(all-pass filter). The host device can override the frequency response by programming the IIR coefficients in 表

7-14 to achieve the desired frequency response for high-pass filtering or any other desired filtering. If

HPF_SEL[1:0] are set to 2'b00, the host device must write these coefficients values for the desired frequency

response before powering-up any PDM channel for recording. These programmable coefficients are 32-bit,

two’s complement numbers. 表7-14 shows the filter coefficients for the first-order IIR filter.

表7-14. 1st-Order IIR Filter Coefficients

FILTER

COEFFICIENT

COEFFICIENT REGISTER

MAPPING

FILTER

DEFAULT COEFFICIENT VALUE

0x7FFFFFFF

N₀

N₁

D₁

P4_R72-R75

P4_R76-R79

P4_R80-R83

Programmable 1st-order IIR filter (can be

allocated to HPF or any other desired filter)

0x00000000

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7.3.6.5 Programmable Digital Biquad Filters

The device supports up to 12 programmable digital biquad filters. These highly efficient filters achieve the

desired frequency response. In digital signal processing, a digital biquad filter is a second-order, recursive linear

filter with two poles and two zeros. 方程式2 gives the transfer function of each biquad filter:

0₀+ 20₁V^F1+ 0₂V^F2

2³¹F 2&₁V^F1F &₂V^F2

: ;

* V =

(2)

The frequency response for the biquad filter section with default coefficients is flat at a gain of 0 dB (all-pass

filter). The host device can override the frequency response by programming the biquad coefficients to achieve

the desired frequency response for a low-pass, high-pass, or any other desired frequency shaping. The

programmable coefficients for the mixer operation are located in the 节 7.6.3.1 and 节 7.6.3.2 sections. If biquad

filtering is required, then the host device must write these coefficients values before powering up any PDM

channels for recording. These programmable coefficients are 32-bit, two’s complement numbers. As described

in 表 7-15, these biquad filters can be allocated for each output channel based on the BIQUAD_CFG[1:0]

register setting of P0_R108. By setting BIQUAD_CFG[1:0] to 2'b00, the biquad filtering for all record channels is

disabled and the host device can choose this setting if no additional filtering is required for the system

application. See the TLV320ADCx140 Programmable Biquad Filter Configuration and Applications application

report for further details.

表7-15. Biquad Filter Allocation to the Record Output Channel

RECORD OUTPUT CHANNEL ALLOCATION USING P0_R108_D[6:5] REGISTER SETTING

BIQUAD_CFG[1:0] = 2'b01

(1 Biquad per Channel)

BIQUAD_CFG[1:0] = 2'b10 (Default)

(2 Biquads per Channel)

BIQUAD_CFG[1:0] = 2'b11

(3 Biquads per Channel)

PROGRAMMABLE

BIQUAD FILTER

SUPPORTS ALL 8 CHANNELS

Allocated to output channel 1

Allocated to output channel 2

Allocated to output channel 3

Allocated to output channel 4

Not used

SUPPORTS UP TO 6 CHANNELS

Allocated to output channel 1

Allocated to output channel 2

Allocated to output channel 3

Allocated to output channel 4

Allocated to output channel 1

Allocated to output channel 2

Allocated to output channel 3

Allocated to output channel 4

Not used

SUPPORTS UP TO 4 CHANNELS

Allocated to output channel 1

Allocated to output channel 2

Allocated to output channel 3

Allocated to output channel 4

Allocated to output channel 1

Allocated to output channel 2

Allocated to output channel 3

Allocated to output channel 4

Allocated to output channel 1

Allocated to output channel 2

Allocated to output channel 3

Allocated to output channel 4

Biquad filter 1

Biquad filter 2

Biquad filter 3

Biquad filter 4

Biquad filter 5

Biquad filter 6

Biquad filter 7

Biquad filter 8

Biquad filter 9

Biquad filter 10

Biquad filter 11

Biquad filter 12

Not used

表7-16 shows the biquad filter coefficients mapping to the register space.

表7-16. Biquad Filter Coefficients Register Mapping

PROGRAMMABLE BIQUAD BIQUAD FILTER COEFFICIENTS PROGRAMMABLE BIQUAD BIQUAD FILTER COEFFICIENTS

FILTER

REGISTER MAPPING

FILTER

REGISTER MAPPING

Biquad filter 1

Biquad filter 2

Biquad filter 3

Biquad filter 4

Biquad filter 5

Biquad filter 6

P2_R8-R27

Biquad filter 7

Biquad filter 8

Biquad filter 9

Biquad filter 10

Biquad filter 11

Biquad filter 12

P3_R8-R27

P2_R28-R47

P3_R28-R47

P2_R48-R67

P3_R48-R67

P2_R68-R87

P3_R68-R87

P2_R88-R107

P2_R108-R127

P3_R88-R107

P3_R108-R127

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7.3.6.6 Programmable Channel Summer and Digital Mixer

For applications that require an even higher SNR than that supported for each channel, the device digital

summing mode can be used. In this mode, the digital record data are summed up across the channel with an

equal weightage factor, which helps in reducing the effective record noise. 表7-17 lists the configuration settings

available for channel summing mode.

表7-17. Channel Summing Mode Programmable Settings

SNR AND DYNAMIC RANGE

P0_R107_D[3:2] : CH_SUM[2:0]

CHANNEL SUMMING MODE FOR INPUT CHANNELS

Channel summing mode is disabled

BOOST

00 (default)

Not applicable

Output channel 1 = (input channel 1 + input channel 2) / 2

Output channel 2 = (input channel 1 + input channel 2) / 2

Output channel 3 = (input channel 3 + input channel 4) / 2

Output channel 4 = (input channel 3 + input channel 4) / 2

Reserved (do not use this setting)

3-dB boost in SNR and dynamic

range

01

3-dB boost in SNR and dynamic

range

10

11

Not applicable

Reserved (do not use this setting)

The device additionally supports a fully programmable mixer feature that can mix the various input channels with

their custom programmable scale factor to generate the final output channels. The programmable mixer feature

is available only if CH_SUM[2:0] is set to 2'b00. The mixer function is supported for all 4 input channels. 图 7-18

shows a block diagram that describes the mixer 1 operation to generate output channel 1. The programmable

coefficients for the mixer operation are located in the 节 7.6.3.3 section. All mixer coefficients are 32-bit, two’s

complement numbers using a 1.31 number format. The value of 0x7FFFFFFF is equivalent to +1 (0-dB gain),

the value 0x00000000 is equivalent to mute (zero data), and any values in between set the mixer attenuation

computed using 方程式 3. If the MSB is set to '1' then the attenuation remains the same but the signal phase is

inverted.

hex2dec (value) / 2³¹

(3)

Attenuated by

MIX1_CH1

factor

Input Channel-1

Processed Data

Attenuated by

MIX1_CH2

factor

Input Channel-2

Processed Data

Output Channel-1

Routed to Bi-Quad

Filter

+

Attenuated by

MIX1_CH3

factor

Input Channel-3

Processed Data

Attenuated by

MIX1_CH4

factor

Input Channel-4

Processed Data

图7-18. Programmable Digital Mixer Block Diagram

A similar mixer operation is performed by mixer 2, mixer 3, and mixer 4 to generate output channel 2, channel 3,

and channel 4, respectively.

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7.3.6.7 Configurable Digital Decimation Filters

The device record channel includes a high dynamic range, built-in digital decimation filter to process the

oversampled PDM data stream from the digital microphone to generate digital data at the same Nyquist

sampling rate as the FSYNC rate. The decimation filter can be chosen from three different types, depending on

the required frequency response, group delay, and phase linearity requirements for the target application. The

selection of the decimation filter option can be done by configuring the DECI_FILT (P0_R107_D[5:4]) register

bits. 表 7-18 shows the configuration register setting for the decimation filter mode selection for the record

channel.

表7-18. Decimation Filter Mode Selection for the Record Channel

P0_R107_D[5:4] : DECI_FILT[1:0]

DECIMATION FILTER MODE SELECTION

00 (default)

Linear phase filters are used for the decimation

01

10

11

Low latency filters are used for the decimation

Ultra-low latency filters are used for the decimation

Reserved (do not use this setting)

7.3.6.7.1 Linear Phase Filters

The linear phase decimation filters are the default filters set by the device and can be used for all applications

that require a perfect linear phase with zero-phase deviation within the pass-band specification of the filter. The

filter performance specifications and various plots for all supported output sampling rates are listed in this

section.

7.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz

图 7-19 and 图 7-20 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 7.35 kHz to 8 kHz. 表7-19 lists the specifications for a decimation filter with a 7.35-kHz to

8-kHz sampling rate.

10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

D001

图7-19. Linear Phase Decimation Filter Magnitude 图7-20. Linear Phase Decimation Filter Pass-Band

Response Ripple

表7-19. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.05

72.7

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.454 × f_S

Frequency range is 0.58 × f_Sto 4 × f_S

Frequency range is 4 × f_Sonwards

Frequency range is 0 to 0.454 × f_S

0.05

dB

Stop-band attenuation

Group delay or latency

dB

81.2

17.1

1/f_S

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7.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz

图 7-21 and 图 7-22 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 14.7 kHz to 16kHz. 表 7-20 lists the specifications for a decimation filter with a 14.7-kHz

to 16 kHz sampling rate.

10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

D001

图7-21. Linear Phase Decimation Filter Magnitude 图7-22. Linear Phase Decimation Filter Pass-Band

Response Ripple

表7-20. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.05

73.3

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.454 × f_S

Frequency range is 0.58 × f_Sto 4 × f_S

Frequency range is 4 × f_Sonwards

Frequency range is 0 to 0.454 × f_S

0.05

dB

Stop-band attenuation

Group delay or latency

dB

95.0

15.7

1/f_S

7.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz

图 7-23 and 图 7-24 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 22.05 kHz to 24 kHz. 表 7-21 lists the specifications for a decimation filter with a 22.05-

kHz to 24-kHz sampling rate.

10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

D001

图7-23. Linear Phase Decimation Filter Magnitude 图7-24. Linear Phase Decimation Filter Pass-Band

Response Ripple

表7-21. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.05

73.0

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.454 × f_S

Frequency range is 0.58 × f_Sto 4 × f_S

Frequency range is 4 × f_Sonwards

0.05

dB

Stop-band attenuation

dB

96.4

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表7-21. Linear Phase Decimation Filter Specifications (continued)

PARAMETER

Group delay or latency

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Frequency range is 0 to 0.454 × f_S

16.6

1/f_S

7.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz

图 7-25 and 图 7-26 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 29.4 kHz to 32 kHz. 表 7-22 lists the specifications for a decimation filter with a 29.4-kHz

to 32-kHz sampling rate.

10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

D001

图7-25. Linear Phase Decimation Filter Magnitude 图7-26. Linear Phase Decimation Filter Pass-Band

Response Ripple

表7-22. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.05

73.7

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.454 × f_S

Frequency range is 0.58 × f_Sto 4 × f_S

Frequency range is 4 × f_Sonwards

Frequency range is 0 to 0.454 × f_S

0.05

dB

Stop-band attenuation

Group delay or latency

dB

107.2

16.9

1/f_S

7.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz

图 7-27 and 图 7-28 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 44.1 kHz to 48 kHz. 表 7-23 lists the specifications for a decimation filter with a 44.1-kHz

to 48-kHz sampling rate.

10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

D001

图7-27. Linear Phase Decimation Filter Magnitude 图7-28. Linear Phase Decimation Filter Pass-Band

Response

Ripple

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表7-23. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.05

73.8

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.454 × f_S

Frequency range is 0.58 × f_Sto 4 × f_S

Frequency range is 4 × f_Sonwards

Frequency range is 0 to 0.454 × f_S

0.05

dB

Stop-band attenuation

Group delay or latency

dB

98.1

17.1

1/f_S

7.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz

图 7-29 and 图 7-30 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 88.2 kHz to 96 kHz. 表7-24 lists the specifications for a decimation filter with an 88.2-kHz

to 96-kHz sampling rate.

10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

D001

图7-29. Linear Phase Decimation Filter Magnitude 图7-30. Linear Phase Decimation Filter Pass-Band

Response Ripple

表7-24. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.05

73.6

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.454 × f_S

Frequency range is 0.58 × f_Sto 4 × f_S

Frequency range is 4 × f_Sonwards

Frequency range is 0 to 0.454 × f_S

0.05

dB

Stop-band attenuation

Group delay or latency

dB

97.9

17.1

1/f_S

7.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz

图 7-31 and 图 7-32 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 176.4 kHz to 192 kHz. 表 7-25 lists the specifications for a decimation filter with a 176.4-

kHz to 192-kHz sampling rate.

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10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05

0.1

0.15

0.2

0.25

Normalized Frequency (1/f_S)

0.3

0.35

0.4

D001

图7-31. Linear Phase Decimation Filter Magnitude

图7-32. Linear Phase Decimation Filter Pass-Band

Response

Ripple

表7-25. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.3 × f_S

Frequency range is 0.473 × f_Sto 4 × f_S

Frequency range is 4 × f_Sonwards

Frequency range is 0 to 0.3 × f_S

0.05

dB

–0.05

70.0

Stop-band attenuation

Group delay or latency

dB

111.0

11.9

1/f_S

7.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz

图 7-33 and 图 7-34 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 352.8 kHz to 384 kHz. 表 7-26 lists the specifications for a decimation filter with a 352.8-

kHz to 384-kHz sampling rate.

10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05

0.1

0.15

Normalized Frequency (1/f_S)

0.2

0.25

0.3

D001

图7-33. Linear Phase Decimation Filter Magnitude 图7-34. Linear Phase Decimation Filter Pass-Band

Response Ripple

表7-26. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.05

70.0

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.212 × f_S

Frequency range is 0.58 × f_Sto 4 × f_S

Frequency range is 4 × f_Sonwards

Frequency range is 0 to 0.212 × f_S

0.05

dB

Stop-band attenuation

Group delay or latency

dB

108.8

7.2

1/f_S

7.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz

图 7-35 and 图 7-36 respectively show the magnitude response and the pass-band ripple for a decimation filter

with a sampling rate of 705.6 kHz to 768 kHz. 表 7-27 lists the specifications for a decimation filter with a 705.6-

kHz to 768-kHz sampling rate.

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10

0

0.5

0.4

0.3

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

0

0.05

0.1

Normalized Frequency (1/f_S)

0.15

0.2

D001

图7-35. Linear Phase Decimation Filter Magnitude 图7-36. Linear Phase Decimation Filter Pass-Band

Response Ripple

表7-27. Linear Phase Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.05

75.0

TYP

MAX

UNIT

Pass-band ripple

Frequency range is 0 to 0.113 × f_S

Frequency range is 0.58 × f_Sto 2 × f_S

Frequency range is 2 × f_Sonwards

0.05

dB

Stop-band attenuation

dB

88.0

Group Delay or Latency Frequency range is 0 to 0.113 × f_S

5.9

1/f_S

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7.3.6.7.2 Low-Latency Filters

For applications where low latency with minimal phase deviation (within the audio band) is critical, the low-

latency decimation filters on the PCMD3140-Q1 can be used. The device supports these filters with a group

delay of approximately seven samples with an almost linear phase response within the 0.365 × f_Sfrequency

band. This section provides the filter performance specifications and various plots for all supported output

sampling rates for the low-latency filters.

7.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz

图 7-37 shows the magnitude response and 图 7-38 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 14.7 kHz to 16 kHz. 表 7-28 lists the specifications for a decimation filter

with a 14.7-kHz to 16-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D002

图7-38. Low-Latency Decimation Filter Pass-Band

图7-37. Low-Latency Decimation Filter Magnitude

Ripple and Phase Deviation

Response

表7-28. Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.451 × f_S

Frequency range is 0.61 × f_Sonwards

Frequency range is 0 to 0.363 × f_S

0.05

–0.05

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

87.3

dB

7.6

1/f_S

0.022

0.25

1/f_S

–0.022

–0.21

Degrees

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7.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz

图 7-39 shows the magnitude response and 图 7-40 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 22.05 kHz to 24 kHz. 表 7-29 lists the specifications for a decimation

filter with a 22.05-kHz to 24-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D002

图7-40. Low-Latency Decimation Filter Pass-Band

图7-39. Low-Latency Decimation Filter Magnitude

Ripple and Phase Deviation

Response

表7-29. Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.459 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.365 × f_S

0.01

–0.01

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

87.2

dB

7.5

1/f_S

0.026

0.30

1/f_S

–0.026

–0.26

Degrees

7.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz

图 7-41 shows the magnitude response and 图 7-42 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 29.4 kHz to 32 kHz. 表 7-30 lists the specifications for a decimation filter

with a 29.4-kHz to 32-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D002

图7-42. Low-Latency Decimation Filter Pass-Band

图7-41. Low-Latency Decimation Filter Magnitude

Ripple and Phase Deviation

Response

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表7-30. Low-Latency Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.04

88.3

TYP

MAX

UNIT

dB

Pass-band ripple

Frequency range is 0 to 0.457 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.368 × f_S

0.04

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

dB

8.7

1/f_S

0.026

0.31

1/f_S

–0.026

–0.26

Degrees

7.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz

图 7-43 shows the magnitude response and 图 7-44 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 44.1 kHz to 48 kHz. 表 7-31 lists the specifications for a decimation filter

with a 44.1-kHz to 48-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D002

图7-44. Low-Latency Decimation Filter Pass-Band

图7-43. Low-Latency Decimation Filter Magnitude

Ripple and Phase Deviation

Response

表7-31. Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.452 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.365 × f_S

0.015

–0.015

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

86.4

dB

7.7

1/f_S

0.027

0.30

1/f_S

–0.027

–0.25

Degrees

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7.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz

图 7-45 shows the magnitude response and 图 7-46 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 88.2 kHz to 96 kHz. 表 7-32 lists the specifications for a decimation filter

with an 88.2-kHz to 96-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D002

图7-46. Low-Latency Decimation Filter Pass-Band

图7-45. Low-Latency Decimation Filter Magnitude

Ripple and Phase Deviation

Response

表7-32. Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.466 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.365 × f_S

0.04

–0.04

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

86.3

dB

7.7

1/f_S

0.027

0.30

1/f_S

–0.027

–0.26

Degrees

7.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz

图 7-47 shows the magnitude response and 图 7-48 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 176.4 kHz to 192 kHz. 表 7-33 lists the specifications for a decimation

filter with a 176.4-kHz to 192-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D002

图7-48. Low-Latency Decimation Filter Pass-Band

图7-47. Low-Latency Decimation Filter Magnitude

Ripple and Phase Deviation

Response

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表7-33. Low-Latency Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

Frequency range is 0 to 463 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.365 × f_S

MIN

–0.03

85.6

TYP

MAX

UNIT

dB

Pass-band ripple

0.03

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

dB

7.7

1/f_S

0.027

0.30

1/f_S

–0.027

–0.26

Degrees

7.3.6.7.3 Ultra-Low-Latency Filters

For applications where ultra-low latency (within the audio band) is critical, the ultra-low-latency decimation filters

on the PCMD3140-Q1 can be used. The device supports these filters with a group delay of approximately four

samples with an almost linear phase response within the 0.325 × f_Sfrequency band. This section provides the

filter performance specifications and various plots for all supported output sampling rates for the ultra-low-latency

filters.

7.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz

图 7-49 shows the magnitude response and 图 7-50 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 14.7 kHz to 16 kHz. 表 7-34 lists the specifications for a decimation filter

with a 14.7-kHz to 16-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

25

20

15

10

5

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-0.1

-0.2

-0.3

-0.4

-0.5

-5

-10

-15

-20

-25

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D003

图7-50. Ultra-Low-Latency Decimation Filter Pass-

图7-49. Ultra-Low-Latency Decimation Filter

Band Ripple and Phase Deviation

Magnitude Response

表7-34. Ultra-Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.45 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.325 × f_S

0.05

–0.05

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

87.2

dB

4.3

1/f_S

0.512

14.2

1/f_S

–0.512

–10.0

Degrees

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7.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz

图 7-51 shows the magnitude response and 图 7-52 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 22.05 kHz to 24 kHz. 表 7-35 lists the specifications for a decimation

filter with a 22.05-kHz to 24-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

25

20

15

10

5

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-0.1

-0.2

-0.3

-0.4

-0.5

-5

-10

-15

-20

-25

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D003

图7-52. Ultra-Low-Latency Decimation Filter Pass-

图7-51. Ultra-Low-Latency Decimation Filter

Band Ripple and Phase Deviation

Magnitude Response

表7-35. Ultra-Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.46 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.325 × f_S

0.01

–0.01

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

87.1

dB

4.1

1/f_S

0.514

14.3

1/f_S

–0.514

–10.0

Degrees

7.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz

图 7-53 shows the magnitude response and 图 7-54 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 29.4 kHz to 32 kHz. 表 7-36 lists the specifications for a decimation filter

with a 29.4-kHz to 32-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

25

20

15

10

5

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-0.1

-0.2

-0.3

-0.4

-0.5

-5

-10

-15

-20

-25

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D003

图7-54. Ultra-Low-Latency Decimation Filter Pass-

图7-53. Ultra-Low-Latency Decimation Filter

Band Ripple and Phase Deviation

Magnitude Response

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表7-36. Ultra-Low-Latency Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

MIN

–0.04

88.3

TYP

MAX

UNIT

dB

Pass-band ripple

Frequency range is 0 to 0.457 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.325 × f_S

0.04

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

dB

5.2

1/f_S

0.492

13.5

1/f_S

–0.492

–9.5

Degrees

7.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz

图 7-55 shows the magnitude response and 图 7-56 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 44.1 kHz to 48 kHz. 表 7-37 lists the specifications for a decimation filter

with a 44.1-kHz to 48-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

25

20

15

10

5

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-0.1

-0.2

-0.3

-0.4

-0.5

-5

-10

-15

-20

-25

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D003

图7-56. Ultra-Low-Latency Decimation Filter Pass-

图7-55. Ultra-Low-Latency Decimation Filter

Band Ripple and Phase Deviation

Magnitude Response

表7-37. Ultra-Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.452 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.325 × f_S

0.015

–0.015

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

86.4

dB

4.1

1/f_S

0.525

14.5

1/f_S

–0.525

–10.3

Degrees

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7.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz

图 7-57 shows the magnitude response and 图 7-58 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 88.2 kHz to 96 kHz. 表 7-38 lists the specifications for a decimation filter

with an 88.2-kHz to 96-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

5

10

0

4

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

3

2

1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-1

-2

-3

-4

-5

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D003

图7-58. Ultra-Low-Latency Decimation Filter Pass-

图7-57. Ultra-Low-Latency Decimation Filter

Band Ripple and Phase Deviation

Magnitude Response

表7-38. Ultra-Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.466 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.1625 × f_S

0.04

–0.04

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

86.3

dB

3.7

1/f_S

0.091

1.30

1/f_S

–0.091

–0.86

Degrees

7.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz

图 7-59 shows the magnitude response and 图 7-60 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 176.4 kHz to 192 kHz. 表 7-39 lists the specifications for a decimation

filter with a 176.4-kHz to 192-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

5

10

0

4

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

3

2

1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-1

-2

-3

-4

-5

Pass-Band Ripple

Phase Deviation

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (1/f_S)

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D003

图7-60. Ultra-Low-Latency Decimation Filter Pass-

图7-59. Ultra-Low-Latency Decimation Filter

Band Ripple and Phase Deviation

Magnitude Response

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表7-39. Ultra-Low-Latency Decimation Filter Specifications

PARAMETER

TEST CONDITIONS

Frequency range is 0 to 0.463 × f_S

Frequency range is 0.6 × f_Sonwards

Frequency range is 0 to 0.085 × f_S

MIN

–0.03

85.6

TYP

MAX

UNIT

dB

Pass-band ripple

0.03

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

dB

3.7

1/f_S

0.024

0.18

1/f_S

–0.024

–0.12

Degrees

7.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz

图 7-61 shows the magnitude response and 图 7-62 shows the pass-band ripple and phase deviation for a

decimation filter with a sampling rate of 352.8 kHz to 384 kHz. 表 7-40 lists the specifications for a decimation

filter with a 352.8-kHz to 384-kHz sampling rate.

0.5

0.4

0.3

0.2

0.1

0

2

10

0

1.6

1.2

0.8

0.4

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-0.1

-0.2

-0.3

-0.4

-0.5

-0.4

-0.8

-1.2

-1.6

-2

Pass-Band Ripple

Phase Deviation

0

0.05

0.1 0.15

Normalized Frequency (1/f_S)

0.2

0.25

0

0.4 0.8 1.2 1.6

2

Normalized Frequency (1/f_S)

2.4 2.8 3.2 3.6

4

D002

图7-62. Ultra-Low-Latency Decimation Filter Pass-

图7-61. Ultra-Low-Latency Decimation Filter

Band Ripple and Phase Deviation

Magnitude Response

表7-40. Ultra-Low-Latency Decimation Filter Specifications

PARAMETER

Pass-band ripple

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dB

Frequency range is 0 to 0.1 × f_S

Frequency range is 0.56 × f_Sonwards

Frequency range is 0 to 0.157 × f_S

0.01

–0.04

Stop-band attenuation

Group delay or latency

Group delay deviation

Phase deviation

70.1

dB

4.1

1/f_S

0.18

2.07

1/f_S

–0.18

–0.85

Degrees

7.3.7 Voice Activity Detection (VAD)

The PCMD3140-Q1 supports voice activity detection (VAD) mode. In this mode, the PCMD3140-Q1 continuously

monitors one of the input channels for voice detection. The device consumes low quiescent current from the

AVDD supply in this mode. This feature can be enabled by setting the VAD_EN (P0_R117_D0) bit to 1'b1. On

detecting voice activity, the PCMD3140-Q1 can alert the host through an interrupt or auto wake up and start

recording based on the I²C programmed configuration. This feature can configured through the VAD_MODE

(P1_R30_D[7:6]) register bits.

The input channel for the VAD can be selected by setting the VAD_CH_SEL (P1_R30_D[5:4]) register bits to an

appropriate value. See the Using the Voice Activity Detector (VAD) in the TLV320ADCx120 and PCMx120-Q1

application report for further details.

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7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing

Certain events in the device may require host processor intervention and can be used to trigger interrupts to the

host processor. One such event is an audio serial interface (ASI) bus error. The device powers down the record

channels if any faults are detected with the ASI bus error clocks, such as:

• Invalid FSYNC frequency

• Invalid SBCLK to FSYNC ratio

• Long pauses of the SBCLK or FSYNC clocks

When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After

all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record

channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the

clock error interrupt mask register bit INT_MASK0[7] (P0_R51_D7) is set low. The clock fault is also available for

readback in the latched fault status register bit INT_LTCH0 (P0_R54), which is a read-only register. Reading the

latched fault status register, INT_LTCH0, clears all latched fault status. The device can be additionally configured

to route the internal IRQ interrupt signal on the GPIO1 or GPOx pins and also can be configured as open-drain

outputs so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices.

The IRQ interrupt signal can either be configured as active low or active high polarity by setting the INT_POL

(P0_R50_D7) register bit. This signal can also be configured as a single pulse or a series of pulses by

programming the INT_EVENT[1:0] (P0_R50_D[6:5]) register bits. If the interrupts are configured as a series of

pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine

the cause of the interrupt.

The device also supports read-only live-status registers to determine if the channels are powered up or down

and if the device is in sleep mode or not. These status registers are located in the DEV_STS0 (P0_R118) and

DEV_STS1 (P0_R119) registers.

The device has a multifunctional GPIO1 pin that can be configured for a desired specific function. Additionally,

GPIx and GPOx can be repurposed as multifunction pins GPIx and GPOx respectively, as required for system

application. 表7-41 shows all possible allocations of these multifunctional pins for the various features.

表7-41. Multifunction Pin Assignments

ROW

PIN FUNCTION

GPIO1

GPO1

GPI1

GPI2

GPIO1_CFG

GPO1_CFG

GPI1_CFG

GPI2_CFG

—

A

B

C

D

E

F

—

P0_R33[7:4]

P0_R34[7:4]

P0_R43[6:4]

P0_R43[2:0]

—

Pin disabled

S⁽¹⁾

S (default)

General-purpose output (GPO)

Interrupt output (IRQ)

S

NS⁽²⁾

NS

S

NS

S

S (default)

S

Power-down for all record channels

PDM clock output (PDMCLK)

MiCBIAS on/off input (BIASEN)

General-purpose input (GPI)

Master clock input (MCLK)

ASI daisy-chain input (SDIN)

PDM data input 1 (PDMDIN1)

PDM data input 2 (PDMDIN2)

S

NS

S

NS

S

NS

S

NS

G

H

I

S

J

S

K

S

(1) S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.

(2) NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.

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Each GPOx or GPIOx pin can be independently set for the desired drive configurations setting using the

GPOx_DRV[3:0] or GPIO1_DRV[3:0] register bits. 表7-42 lists the drive configuration settings.

表7-42. GPIO or GPOx Pins Drive Configuration Settings

P0_R33_D[3:0] : GPIO1_DRV[3:0]

GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1

000

001

The GPIO1 pin is set to high impedance (floated)

The GPIO1 pin is set to be driven active low or active high

The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)

The GPIO1 pin is set to be driven active low or Hi-Z (floated)

The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high

The GPIO1 pin is set to be driven Hi-Z (floated) or active high

Reserved (do not use these settings)

010 (default)

011

100

101

110 and 111

Similarly, the GPO1 pin can be configured using the GPO1_DRV (P0_R34) register bits.

When configured as a general-purpose output (GPO), the GPIO1 or GPOx pin values can be driven by writing

the GPIO_VAL or GPOx_VAL (P0_R41) registers. The GPIO_MON (P0_R42) register can be used to readback

the status of the GPIO1 pin when configured as a general-purpose input (GPI). Similarly, the GPI_MON

(P0_R47) register can be used to readback the status of the GPIx pins when configured as a general-purpose

input (GPI).

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7.4 Device Functional Modes

7.4.1 Sleep Mode or Software Shutdown

In sleep mode or software shutdown mode, the device consumes very low quiescent current from the AVDD

supply and, at the same time, allows the I²C communication to wake the device for active operation.

The device enters sleep mode when the host device sets the SLEEP_ENZ (P0_R2_D0) bit to 1'b0. If the

SLEEP_ENZ bit is asserted low when the device is in active mode, the device ramps down the volume on the

record data, powers down the analog and digital blocks, and enters sleep mode. However, the device still

continues to retain the last programmed value of the device configuration registers and programmable

coefficients.

In sleep mode, do not perform any I²C transactions, except for exiting sleep mode in order to enter active mode.

After entering sleep mode, wait at least 10 ms before starting I²C transactions to exit sleep mode.

When exiting sleep mode, the host device must configure the PCMD3140-Q1 to use either an external 1.8-V

AREG supply (default setting) or an on-chip, regulator-generated AREG supply. To configure the AREG supply,

write to AREG_SELECT (bit D7) in the same P0_R2 register.

7.4.2 Active Mode

If the host device exits sleep mode by setting the SLEEP_ENZ bit to 1'b1, the device enters active mode. In

active mode, I²C transactions can be done to configure and power-up the device for active operation. After

entering active mode, wait at least 1 ms before starting any I²C transactions to allow the device to complete the

internal wake-up sequence.

Read and write operations to the programmable coefficient registers in page 2, page 3, and page 4 and to the

channel configuration registers (CHx_CFG[1:4]) in page 0 must be done 10 ms after exiting sleep mode.

After configuring all other registers for the target application and system settings, configure the input and output

channel enable registers, IN_CH_EN (P0_R115) and ASI_OUT_CH_EN (P0_R116), respectively. Lastly,

configure the device power-up register, PWR_CFG (P0_R117). All programmable coefficient values must be

written before powering up the respective channel.

In active mode, the power-up and power-down status of various blocks is monitored by reading the read-only

device status bits located in the DEV_STS0 (P0_R117) and DEV_STS1 (P0_R118) registers.

7.4.3 Software Reset

A software reset can be done any time by asserting the SW_RESET (P0_R1_D0) bit, which is a self-clearing bit.

This software reset immediately shuts down the device, and restores all device configuration registers and

programmable coefficients to their default values.

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7.5 Programming

The device contains configuration registers and programmable coefficients that can be set to the desired values

for a specific system and application use. These registers are called device control registers and are each eight

bits in width, mapped using a page scheme.

Each page contains 128 configuration registers. All device configuration registers are stored in page 0, which is

the default page setting at power up and after a software reset. All programmable coefficient registers are

located in page 2, page 3, and page 4. The current page of the device can be switched to a new desired page by

using the PAGE[7:0] bits located in register 0 of every page.

7.5.1 Control Serial Interfaces

The device control registers can be accessed using I²C communication to the device. The device operates with

a fixed I²C address and can be configured using this address.

7.5.1.1 I²C Control Interface

The device supports the I²C control protocol as a target device, and is capable of operating in standard mode,

fast mode, and fast mode plus. The I²C control protocol requires a 7-bit target address. The 7-bit target address

is fixed at 1001110 and cannot be changed. If the I2C_BRDCAST_EN (P0_R2_D2) bit is set to 1'b1, then the I²C

target address is fixed to 1001100 in order to allow simultaneous I²C broadcast communication to multiple

devices in the system including the PCMD3140-Q1 and PCMD3180-Q1. 表 7-43 lists the possible device

addresses resulting from this configuration.

表7-43. I²C Target Address Settings

I2C_BRDCAST_EN (P0_R2_D2)

I²C TARGET ADDRESS

0 (default)

1

1001 110

1001 100

7.5.1.1.1 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system using serial data transmission. The address and data 8-bit bytes are transferred MSB first. In addition,

each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each

transfer operation begins with the controller device driving a start condition on the bus and ends with the

controller device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the

clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a

low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock

period.

The controller device drives a start condition followed by the 7-bit target address and the read/write (R/W) bit to

open communication with another device and then waits for an acknowledgment condition. The target device

holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the

controller device transmits the next byte of the sequence. Each target device is addressed by a unique 7-bit

target address plus the R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus

using a wired-AND connection.

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There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the controller device generates a stop condition to release the bus. 图7-63 shows a generic data

transfer sequence.

8- Bit Data for

Register (N)

8- Bit Data for

Register (N+1)

图7-63. Typical I²C Sequence

In the system, use external pullup resistors for the SDA and SCL signals to set the logic high level for the bus.

The SDA and SCL voltages must not exceed the device supply voltage, IOVDD.

7.5.1.1.2 I²C Single-Byte and Multiple-Byte Transfers

The device I²C interface supports both single-byte and multiple-byte read/write operations for all registers.

During multiple-byte read operations, the device responds with data, a byte at a time, starting at the register

assigned, as long as the controller device continues to respond with acknowledges.

The device supports sequential I²C addressing. For write transactions, if a register is issued followed by data for

that register and all the remaining registers that follow, a sequential I²C write transaction takes place. For I²C

sequential write transactions, the register issued then serves as the starting point, and the amount of data

subsequently transmitted, before a stop or start is transmitted, determines how many registers are written.

7.5.1.1.2.1 I²C Single-Byte Write

As shown in 图 7-64, a single-byte data write transfer begins with the controller device transmitting a start

condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I²C

target address and the read/write bit, the device responds with an acknowledge bit (ACK). Next, the controller

device transmits the register byte corresponding to the device internal register address being accessed. After

receiving the register byte, the device again responds with an acknowledge bit (ACK). Then, the controller

transmits the byte of data to be written to the specified register. When finished, the target device responds with

an acknowledge bit (ACK). Finally, the controller device transmits a stop condition to complete the single-byte

data write transfer.

Start

Condition

Acknowledge

R/W

ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

A6 A5 A4

A3 A2 A1 A0

Stop

2

I C Device Address and

Read/Write Bit

Register

Data Byte

Condition

图7-64. I²C Single-Byte Write Transfer

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7.5.1.1.2.2 I²C Multiple-Byte Write

As shown in 图7-65, a multiple-byte data write transfer is identical to a single-byte data write transfer except that

multiple data bytes are transmitted by the controller device to the target device. After receiving each data byte,

the device responds with an acknowledge bit (ACK). Finally, the controller device transmits a stop condition after

the last data-byte write transfer.

Register

图7-65. I²C Multiple-Byte Write Transfer

7.5.1.1.2.3 I²C Single-Byte Read

As shown in 图 7-66, a single-byte data read transfer begins with the controller device transmitting a start

condition followed by the I²C target address and the read/write bit. For the data read transfer, both a write

followed by a read are done. Initially, a write is done to transfer the address byte of the internal register address

to be read. As a result, the read/write bit is set to 0.

After receiving the target address and the read/write bit, the device responds with an acknowledge bit (ACK).

The controller device then sends the internal register address byte, after which the device issues an

acknowledge bit (ACK). The controller device transmits another start condition followed by the target address

and the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the device

transmits the data byte from the register address being read. After receiving the data byte, the controller device

transmits a not-acknowledge (NACK) followed by a stop condition to complete the single-byte data read transfer.

Repeat Start

Condition

Not

Start

Acknowledge

Condition

Acknowledge

A0 ACK

Acknowledge

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4

A6 A5

A1 A0 R/W ACK D7 D6

D1 D0 ACK

2

Stop

Condition

I C Device Address and

Read/Write Bit

Register

I C Device Address and

Read/Write Bit

Data Byte

图7-66. I²C Single-Byte Read Transfer

7.5.1.1.2.4 I²C Multiple-Byte Read

As shown in 图 7-67, a multiple-byte data read transfer is identical to a single-byte data read transfer except that

multiple data bytes are transmitted by the device to the controller device. With the exception of the last data byte,

the controller device responds with an acknowledge bit after receiving each data byte. After receiving the last

data byte, the controller device transmits a not-acknowledge (NACK) followed by a stop condition to complete

the data read transfer.

Repeat Start

Condition

Not

Start

Acknowledge

Condition

Acknowledge

A0 ACK

Acknowledge

D0 ACK D7

A6

A0 R/W ACK A7 A6 A5

A6

A0 R/W ACK D7

D0 ACK D7

D0 ACK

2

Register

Stop

Condition

I C Device Address and

Read/Write Bit

I C Device Address and

Read/Write Bit

First Data Byte

Other Data Bytes

Last Data Byte

图7-67. I²C Multiple-Byte Read Transfer

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7.6 Register Maps

This section describes the control registers for the device in detail. All registers are eight bits in width and are

allocated to device configuration and programmable coefficients settings. These registers are mapped internally

using a page scheme that can be controlled using I²C communication to the device. Each page contains 128

bytes of registers. All device configuration registers are stored in page 0, which is the default page setting at

power up (and after a software reset). All programmable coefficient registers are located in page 2, page 3, and

page 4. The device current page can be switch to a new desired page by using the PAGE[7:0] bits located in

register 0 of every page.

Do not read from or write to reserved pages or reserved registers. Write only default values for the reserved bits

in the valid registers.

The procedure for register access across pages is:

• Select page N (write data N to register 0 regardless of the current page number)

• Read or write data from or to valid registers in page N

• Select the new page M (write data M to register 0 regardless of the current page number)

• Read or write data from or to valid registers in page M

• Repeat as needed

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7.6.1 Page 0 Registers

表 7-44 lists the memory-mapped registers for the Page 0 registers. All register offset addresses not listed in 表

7-44 should be considered as reserved locations and the register contents should not be modified.

表7-44. PAGE 0 Registers

Address

0x0

Acronym

Register Name

Reset Value

0x00

0x30

0x00

0x01

0x02

0x03

0x02

0x48

0xFF

0x10

0x40

0x00

0x22

0x00

0xFF

0x00

0xC9

0x80

0x00

0xC9

0x80

0x00

0xC9

0x80

0x00

0xC9

0x80

Section

PAGE_CFG

SW_RESET

SLEEP_CFG

ASI_CFG0

ASI_CFG1

ASI_CFG2

ASI_MIX_CFG

ASI_CH1

Device page register

节7.6.1.1

节7.6.1.2

节7.6.1.3

节7.6.1.4

节7.6.1.5

节7.6.1.6

节7.6.1.7

节7.6.1.8

节7.6.1.9

节7.6.1.10

节7.6.1.11

节7.6.1.12

节7.6.1.13

节7.6.1.14

节7.6.1.15

节7.6.1.16

节7.6.1.17

节7.6.1.18

节7.6.1.19

节7.6.1.20

节7.6.1.21

节7.6.1.22

节7.6.1.23

节7.6.1.24

节7.6.1.25

节7.6.1.26

节7.6.1.27

节7.6.1.28

节7.6.1.29

节7.6.1.30

节7.6.1.31

节7.6.1.32

节7.6.1.33

节7.6.1.34

节7.6.1.35

节7.6.1.36

节7.6.1.37

节7.6.1.38

节7.6.1.39

0x1

Software reset register

0x2

Sleep mode register

0x7

ASI configuration register 0

0x8

ASI configuration register 1

0x9

ASI configuration register 2

0xA

ASI input mixing configuration register

Channel 1 ASI slot configuration register

Channel 2 ASI slot configuration register

Channel 3 ASI slot configuration register

Channel 4 ASI slot configuration register

ASI master mode configuration register 0

ASI master mode configuration register 1

ASI bus clock monitor status register

Clock source configuration register 0

PDM clock generation configuration register

PDM DINx sampling edge register

GPIO configuration register 0

0xB

0xC

ASI_CH2

0xD

ASI_CH3

0xE

ASI_CH4

0x13

0x14

0x15

0x16

0x1F

0x20

0x21

0x22

0x29

0x2A

0x2B

0x2F

0x32

0x33

0x36

0x3B

0x3E

0x3F

0x40

0x41

0x43

0x44

0x45

0x48

0x49

0x4A

0x4D

0x4E

MST_CFG0

MST_CFG1

ASI_STS

CLK_SRC

PDMCLK_CFG

PDMIN_CFG

GPIO_CFG0

GPO_CFG0

GPO_VAL

GPO configuration register 0

GPIO, GPO output value register

GPIO monitor value register

GPIO_MON

GPI_CFG0

GPI_MON

GPI configuration register 0

GPI monitor value register

INT_CFG

Interrupt configuration register

Interrupt mask register 0

INT_MASK0

INT_LTCH0

BIAS_CFG

CH1_CFG2

CH1_CFG3

CH1_CFG4

CH2_CFG0

CH2_CFG2

CH2_CFG3

CH2_CFG4

CH3_CFG2

CH3_CFG3

CH3_CFG4

CH4_CFG2

CH4_CFG3

Latched interrupt readback register 0

Bias and ADC configuration register

Channel 1 configuration register 2

Channel 1 configuration register 3

Channel 1 configuration register 4

Channel 2 configuration register 0

Channel 2 configuration register 2

Channel 2 configuration register 3

Channel 2 configuration register 4

Channel 3 configuration register 2

Channel 3 configuration register 3

Channel 3 configuration register 4

Channel 4 configuration register 2

Channel 4 configuration register 3

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表7-44. PAGE 0 Registers (continued)

Address

0x4F

0x6B

0x6C

0x73

Acronym

Register Name

Reset Value

0x00

Section

CH4_CFG4

DSP_CFG0

DSP_CFG1

IN_CH_EN

ASI_OUT_CH_EN

PWR_CFG

DEV_STS0

DEV_STS1

I2C_CKSUM

Channel 4 configuration register 4

DSP configuration register 0

DSP configuration register 1

Input channel enable configuration register

ASI output channel enable configuration register

Power up configuration register

Device status value register 0

Device status value register 1

I²C checksum register

节7.6.1.40

节7.6.1.41

节7.6.1.42

节7.6.1.43

节7.6.1.44

节7.6.1.45

节7.6.1.46

节7.6.1.47

节7.6.1.48

0x01

0x40

0xC0

0x00

0x74

0x75

0x00

0x76

0x00

0x77

0x80

0x7E

0x00

7.6.1.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in 图7-68 and described in 表7-45.

Return to the 表7-44.

The device memory map is divided into pages. This register sets the page.

图7-68. PAGE_CFG Register

7

6

5

4

3

2

1

0

PAGE[7:0]

R/W-00000000b

表7-45. PAGE_CFG Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

PAGE[7:0]

R/W

00000000b These bits set the device page.

0d = Page 0

1d = Page 1

2d to 254d = Page 2 to page 254 respectively

255d = Page 255

7.6.1.2 SW_RESET Register (Address = 0x1) [Reset = 0x00]

SW_RESET is shown in 图7-69 and described in 表7-46.

Return to the 表7-44.

This register is the software reset register. Asserting a software reset places all register values in their default

power-on-reset (POR) state.

图7-69. SW_RESET Register

7

6

5

4

3

2

1

0

RESERVED

R-0000000b

SW_RESET

R/W-0b

表7-46. SW_RESET Register Field Descriptions

Bit

7-1

Field

RESERVED

Type

Reset

Description

R

0000000b

Reserved bits; Write only reset value

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表7-46. SW_RESET Register Field Descriptions (continued)

Bit

Field

SW_RESET

Type

Reset

Description

0

R/W

0b

Software reset. This bit is self clearing.

0d = Do not reset

1d = Reset all registers to their reset values

7.6.1.3 SLEEP_CFG Register (Address = 0x2) [Reset = 0x00]

SLEEP_CFG is shown in 图7-70 and described in 表7-47.

Return to the 表7-44.

This register configures the regulator, VREF quick charge, I²C broadcast and sleep mode.

图7-70. SLEEP_CFG Register

7

6

5

4

3

2

1

0

AREG_SELEC

T

RESERVED

R/W-00b

VREF_QCHG[1:0]

I2C_BRDCAST

_EN

RESERVED

SLEEP_ENZ

R/W-0b

R/W-00b

R/W-0b

R-0b

R/W-0b

表7-47. SLEEP_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

AREG_SELECT

R/W

0b

The analog supply selection from either the internal regulator supply

or the external AREG supply.

0d = External 1.8-V AREG supply (use this setting when AVDD is 1.8

V and short AREG with AVDD)

1d = Internally generated 1.8-V AREG supply using an on-chip

regulator (use this setting when AVDD is 3.3 V)

6-5

4-3

RESERVED

R/W

00b

Reserved bits; Write only reset values

VREF_QCHG[1:0]

The duration of the quick-charge for the VREF external capacitor is

set using an internal series impedance of 200 Ω.

0d = VREF quick-charge duration of 3.5 ms (typical)

1d = VREF quick-charge duration of 10 ms (typical)

2d = VREF quick-charge duration of 50 ms (typical)

3d = VREF quick-charge duration of 100 ms (typical)

2

I2C_BRDCAST_EN

R/W

0b

I²C broadcast addressing setting.

0d = I²C broadcast mode disabled

1d = I²C broadcast mode enabled; the I²C target address is fixed at

1001 100

1

0

RESERVED

SLEEP_ENZ

R

0b

Reserved bit; Write only reset value

R/W

Sleep mode setting.

0d = Device is in sleep mode

1d = Device is not in sleep mode

7.6.1.4 ASI_CFG0 Register (Address = 0x7) [Reset = 0x30]

ASI_CFG0 is shown in 图7-71 and described in 表7-48.

Return to the 表7-44.

This register is the ASI configuration register 0.

图7-71. ASI_CFG0 Register

7

6

5

4

3

2

1

0

ASI_FORMAT[1:0]

R/W-00b

ASI_WLEN[1:0]

R/W-11b

FSYNC_POL

R/W-0b

BCLK_POL

R/W-0b

TX_EDGE

R/W-0b

TX_FILL

R/W-0b

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表7-48. ASI_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

ASI_FORMAT[1:0]

R/W

00b

ASI protocol format.

0d = TDM mode

1d = I²S mode

2d = LJ (left-justified) mode

3d = Reserved; Don't use

5-4

ASI_WLEN[1:0]

R/W

11b

ASI word or slot length.

0d = 16 bits (Recommended this setting to be used with 10-kΩor

20-kΩinput impedance configuration)

1d = 20 bits

2d = 24 bits

3d = 32 bits

3

2

1

FSYNC_POL

BCLK_POL

TX_EDGE

R/W

0b

ASI FSYNC polarity.

0d = Default polarity as per standard protocol

1d = Inverted polarity with respect to standard protocol

ASI BCLK polarity.

0d = Default polarity as per standard protocol

1d = Inverted polarity with respect to standard protocol

ASI data output (on the primary and secondary data pin) transmit

edge.

0d = Default edge as per the protocol configuration setting in bit 2

(BCLK_POL)

1d = Inverted following edge (half cycle delay) with respect to the

default edge setting

0

TX_FILL

R/W

0b

ASI data output (on the primary and secondary data pin) for any

unused cycles

0d = Always transmit 0 for unused cycles

1d = Always use Hi-Z for unused cycles

7.6.1.5 ASI_CFG1 Register (Address = 0x8) [Reset = 0x00]

ASI_CFG1 is shown in 图7-72 and described in 表7-49.

Return to the 表7-44.

This register is the ASI configuration register 1.

图7-72. ASI_CFG1 Register

7

6

5

4

3

2

1

0

TX_LSB

R/W-0b

TX_KEEPER[1:0]

R/W-00b

TX_OFFSET[4:0]

R/W-00000b

表7-49. ASI_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

TX_LSB

R/W

0b

ASI data output (on the primary and secondary data pin) for LSB

transmissions.

0d = Transmit the LSB for a full cycle

1d = Transmit the LSB for the first half cycle and Hi-Z for the second

half cycle

6-5

TX_KEEPER[1:0]

R/W

00b

ASI data output (on the primary and secondary data pin) bus keeper.

0d = Bus keeper is always disabled

1d = Bus keeper is always enabled

2d = Bus keeper is enabled during LSB transmissions only for one

cycle

3d = Bus keeper is enabled during LSB transmissions only for one

and half cycles

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表7-49. ASI_CFG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

4-0

TX_OFFSET[4:0]

R/W

00000b

ASI data MSB slot 0 offset (on the primary and secondary data pin).

0d = ASI data MSB location has no offset and is as per standard

protocol

1d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is

the left and right slot 0) offset of one BCLK cycle with respect to

standard protocol

2d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is

the left and right slot 0) offset of two BCLK cycles with respect to

standard protocol

3d to 30d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ

mode is the left and right slot 0) offset assigned as per configuration

31d = ASI data MSB location (TDM mode is slot 0 or I²S, LJ mode is

the left and right slot 0) offset of 31 BCLK cycles with respect to

standard protocol

7.6.1.6 ASI_CFG2 Register (Address = 0x9) [Reset = 0x00]

ASI_CFG2 is shown in 图7-73 and described in 表7-50.

Return to the 表7-44.

This register is the ASI configuration register 2.

图7-73. ASI_CFG2 Register

7

6

5

4

3

2

1

0

ASI_DAISY

RESERVED

ASI_ERR

ASI_ERR_RCO

V

RESERVED

R/W-0b

R-0b

R/W-0b

R-000b

表7-50. ASI_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ASI_DAISY

R/W

0b

ASI daisy chain connection.

0d = All devices are connected in the common ASI bus

1d = All devices are daisy-chained for the ASI bus. This is supported

only if ASI input mixing is disabled, refer register 10 for details on

ASI input mixing feature.

6

5

RESERVED

ASI_ERR

R

0b

Reserved bit; Write only reset value

R/W

ASI bus error detection.

0d = Enable bus error detection

1d = Disable bus error detection

4

ASI_ERR_RCOV

R/W

0b

ASI bus error auto resume.

0d = Enable auto resume after bus error recovery

1d = Disable auto resume after bus error recovery and remain

powered down until the host configures the device

3

RESERVED

R/W

R

0b

Reserved bit; Write only reset value

Reserved bits; Write only reset value

2-0

000b

7.6.1.7 ASI_MIX_CFG Register (Address = 0xA) [Reset = 0x00]

ASI_MIX_CFG is shown in 图7-74 and described in 表7-51.

Return to the 表7-44.

This register is the ASI input mixing configuration register.

图7-74. ASI_MIX_CFG Register

7

6

5

4

3

2

1

0

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图7-74. ASI_MIX_CFG Register (continued)

ASI_MIX_SEL[1:0]

R/W-00b

ASI_GAIN_SEL[1:0]

ASI_IN_INVER

SE

RESERVED

R-0b

RESERVED

R-0b

R/W-00b

R/W-0b

R-0b

表7-51. ASI_MIX_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

ASI_MIX_SEL[1:0]

R/W

00b

ASI input (from GPIx or GPIO) mixing selection with channel data.

0d = No mixing

1d = Channel 1 and channel 2 output data mixed with ASI input data

on channel 1 (slot 0)

2d = Channel 1 and channel 2 output data mixed with ASI input data

on channel 2 (slot 1)

3d = Mixed both channel data with ASI input data independently.

Mixed asi_in_ch_1 with channel 1 output data and similarly mix

asi_in_ch_2 with channel 2 output data

5-4

3

ASI_GAIN_SEL[1:0]

ASI_IN_INVERSE

R/W

00b

0b

ASI input data gain selection before mixing to channel data.

0d = No gain

1d = Gain asi input data by -6dB

2d = Gain asi input data by -12dB

3d = Gain asi input data by -18dB

Invert ASI input data before mixing to channel data.

0d = No inversion done for ASI input data

1d = ASI input data inverted before mixing with channel data

2

1

0

RESERVED

R

0b

Reserved bit; Write only reset value

7.6.1.8 ASI_CH1 Register (Address = 0xB) [Reset = 0x00]

ASI_CH1 is shown in 图7-75 and described in 表7-52.

Return to the 表7-44.

This register is the ASI slot configuration register for channel 1.

图7-75. ASI_CH1 Register

7

6

5

4

3

2

1

0

RESERVED

R-00b

CH1_SLOT[5:0]

R/W-000000b

表7-52. ASI_CH1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-0

RESERVED

R

00b

Reserved bits; Write only reset value

CH1_SLOT[5:0]

R/W

000000b

Channel 1 slot assignment.

0d = TDM is slot 0 or I²S, LJ is left slot 0

1d = TDM is slot 1 or I²S, LJ is left slot 1

2d to 30d = Slot assigned as per configuration

31d = TDM is slot 31 or I²S, LJ is left slot 31

32d = TDM is slot 32 or I²S, LJ is right slot 0

33d = TDM is slot 33 or I²S, LJ is right slot 1

34d to 62d = Slot assigned as per configuration

63d = TDM is slot 63 or I²S, LJ is right slot 31

7.6.1.9 ASI_CH2 Register (Address = 0xC) [Reset = 0x01]

ASI_CH2 is shown in 图7-76 and described in 表7-53.

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Return to the 表7-44.

This register is the ASI slot configuration register for channel 2.

图7-76. ASI_CH2 Register

7

6

5

4

3

2

1

0

RESERVED

R-00b

CH2_SLOT[5:0]

R/W-000001b

表7-53. ASI_CH2 Register Field Descriptions

Type

Bit

Field

Reset

Description

7-6

5-0

RESERVED

R

00b

Reserved bits; Write only reset value

CH2_SLOT[5:0]

R/W

000001b

Channel 2 slot assignment.

0d = TDM is slot 0 or I²S, LJ is left slot 0

1d = TDM is slot 1 or I²S, LJ is left slot 1

2d to 30d = Slot assigned as per configuration

31d = TDM is slot 31 or I²S, LJ is left slot 31

32d = TDM is slot 32 or I²S, LJ is right slot 0

33d = TDM is slot 33 or I²S, LJ is right slot 1

34d to 62d = Slot assigned as per configuration

63d = TDM is slot 63 or I²S, LJ is right slot 31

7.6.1.10 ASI_CH3 Register (Address = 0xD) [Reset = 0x02]

ASI_CH3 is shown in 图7-77 and described in 表7-54.

Return to the 表7-44.

This register is the ASI slot configuration register for channel 3.

图7-77. ASI_CH3 Register

7

6

5

4

3

2

1

RESERVED

R-00b

CH3_SLOT[5:0]

R/W-000010b

表7-54. ASI_CH3 Register Field Descriptions

Type

Bit

Field

Reset

Description

7-6

5-0

RESERVED

R

00b

Reserved bits; Write only reset value

CH3_SLOT[5:0]

R/W

000010b

Channel 3 slot assignment.

0d = TDM is slot 0 or I²S, LJ is left slot 0

1d = TDM is slot 1 or I²S, LJ is left slot 1

2d to 30d = Slot assigned as per configuration

31d = TDM is slot 31 or I²S, LJ is left slot 31

32d = TDM is slot 32 or I²S, LJ is right slot 0

33d = TDM is slot 33 or I²S, LJ is right slot 1

34d to 62d = Slot assigned as per configuration

63d = TDM is slot 63 or I²S, LJ is right slot 31

7.6.1.11 ASI_CH4 Register (Address = 0xE) [Reset = 0x03]

ASI_CH4 is shown in 图7-78 and described in 表7-55.

Return to the 表7-44.

This register is the ASI slot configuration register for channel 4.

图7-78. ASI_CH4 Register

7

6

5

4

3

2

1

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图7-78. ASI_CH4 Register (continued)

RESERVED

R-00b

CH4_SLOT[5:0]

R/W-000011b

表7-55. ASI_CH4 Register Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

Description

RESERVED

CH4_SLOT[5:0]

R

00b

Reserved bits; Write only reset value

R/W

000011b

Channel 4 slot assignment.

0d = TDM is slot 0 or I²S, LJ is left slot 0

1d = TDM is slot 1 or I²S, LJ is left slot 1

2d to 30d = Slot assigned as per configuration

31d = TDM is slot 31 or I²S, LJ is left slot 31

32d = TDM is slot 32 or I²S, LJ is right slot 0

33d = TDM is slot 33 or I²S, LJ is right slot 1

34d to 62d = Slot assigned as per configuration

63d = TDM is slot 63 or I²S, LJ is right slot 31

7.6.1.12 MST_CFG0 Register (Address = 0x13) [Reset = 0x02]

MST_CFG0 is shown in 图7-79 and described in 表7-56.

Return to the 表7-44.

This register is the ASI master mode configuration register 0.

图7-79. MST_CFG0 Register

7

6

5

4

3

2

1

0

MST_SLV_CFG AUTO_CLK_CF AUTO_MODE_ BCLK_FSYNC_

FS_MODE

MCLK_FREQ_SEL[2:0]

G

PLL_DIS

GATE

R/W-0b

R/W-010b

表7-56. MST_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MST_SLV_CFG

R/W

0b

ASI master or slave configuration register setting.

0d = Device is in slave mode (both BCLK and FSYNC are inputs to

the device)

1d = Device is in master mode (both BCLK and FSYNC are

generated from the device)

6

AUTO_CLK_CFG

R/W

0b

Automatic clock configuration setting.

0d = Auto clock configuration is enabled (all internal clock divider and

PLL configurations are auto derived)

1d = Auto clock configuration is disabled (custom mode and device

GUI must be used for the device configuration settings)

5

4

AUTO_MODE_PLL_DIS

BCLK_FSYNC_GATE

R/W

0b

Automatic mode PLL setting.

0d = PLL is enabled in auto clock configuration

1d = PLL is disabled in auto clock configuration

BCLK and FSYNC clock gate (valid when the device is in master

mode).

0d = Do not gate BCLK and FSYNC

1d = Force gate BCLK and FSYNC when being transmitted from the

device in master mode

3

FS_MODE

R/W

0b

Sample rate setting (valid when the device is in master mode).

0d = f_Sis a multiple (or submultiple) of 48 kHz

1d = f_Sis a multiple (or submultiple) of 44.1 kHz

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表7-56. MST_CFG0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2-0

MCLK_FREQ_SEL[2:0]

R/W

010b

These bits select the MCLK (GPIO or GPIx) frequency for the PLL

source clock input (valid when the device is in master mode and

MCLK_FREQ_SEL_MODE = 0).

0d = 12 MHz

1d = 12.288 MHz

2d = 13 MHz

3d = 16 MHz

4d = 19.2 MHz

5d = 19.68 MHz

6d = 24 MHz

7d = 24.576 MHz

7.6.1.13 MST_CFG1 Register (Address = 0x14) [Reset = 0x48]

MST_CFG1 is shown in 图7-80 and described in 表7-57.

Return to the 表7-44.

This register is the ASI master mode configuration register 1.

图7-80. MST_CFG1 Register

7

6

5

4

3

2

1

0

FS_RATE[3:0]

R/W-0100b

FS_BCLK_RATIO[3:0]

R/W-1000b

表7-57. MST_CFG1 Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

FS_RATE[3:0]

R/W

0100b

Programmed sample rate of the ASI bus (not used when the device

is configured in slave mode auto clock configuration).

0d = 7.35 kHz or 8 kHz

1d = 14.7 kHz or 16 kHz

2d = 22.05 kHz or 24 kHz

3d = 29.4 kHz or 32 kHz

4d = 44.1 kHz or 48 kHz

5d = 88.2 kHz or 96 kHz

6d = 176.4 kHz or 192 kHz

7d = 352.8 kHz or 384 kHz

8d = 705.6 kHz or 768 kHz

9d to 15d = Reserved; Don't use

3-0

FS_BCLK_RATIO[3:0]

R/W

1000b

Programmed BCLK to FSYNC frequency ratio of the ASI bus (not

used when the device is configured in slave mode auto clock

configuration).

0d = Ratio of 16

1d = Ratio of 24

2d = Ratio of 32

3d = Ratio of 48

4d = Ratio of 64

5d = Ratio of 96

6d = Ratio of 128

7d = Ratio of 192

8d = Ratio of 256

9d = Ratio of 384

10d = Ratio of 512

11d = Ratio of 1024

12d = Ratio of 2048

13d to 15d = Reserved; Don't use

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7.6.1.14 ASI_STS Register (Address = 0x15) [Reset = 0xFF]

ASI_STS is shown in 图7-81 and described in 表7-58.

Return to the 表7-44.

This register s the ASI bus clock monitor status register

图7-81. ASI_STS Register

7

6

5

4

3

2

1

0

FS_RATE_STS[3:0]

R-1111b

FS_RATIO_STS[3:0]

R-1111b

表7-58. ASI_STS Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

FS_RATE_STS[3:0]

R

1111b

Detected sample rate of the ASI bus.

0d = 7.35 kHz or 8 kHz

1d = 14.7 kHz or 16 kHz

2d = 22.05 kHz or 24 kHz

3d = 29.4 kHz or 32 kHz

4d = 44.1 kHz or 48 kHz

5d = 88.2 kHz or 96 kHz

6d = 176.4 kHz or 192 kHz

7d = 352.8 kHz or 384 kHz

8d = 705.6 kHz or 768 kHz

9d to 14d = Reserved status

15d = Invalid sample rate

3-0

FS_RATIO_STS[3:0]

R

1111b

Detected BCLK to FSYNC frequency ratio of the ASI bus.

0d = Ratio of 16

1d = Ratio of 24

2d = Ratio of 32

3d = Ratio of 48

4d = Ratio of 64

5d = Ratio of 96

6d = Ratio of 128

7d = Ratio of 192

8d = Ratio of 256

9d = Ratio of 384

10d = Ratio of 512

11d = Ratio of 1024

12d = Ratio of 2048

13d to 14d = Reserved status

15d = Invalid ratio

7.6.1.15 CLK_SRC Register (Address = 0x16) [Reset = 0x10]

CLK_SRC is shown in 图7-82 and described in 表7-59.

Return to the 表7-44.

This register is the clock source configuration register.

图7-82. CLK_SRC Register

7

6

5

4

3

2

1

0

DIS_PLL_SLV_ MCLK_FREQ_

MCLK_RATIO_SEL[2:0]

RESERVED

INV_BCLK_FO

R_FSYNC

RESERVED

CLK_SRC

SEL_MODE

R/W-0b

R/W-010b

R/W-0b

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表7-59. CLK_SRC Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DIS_PLL_SLV_CLK_SRC R/W

0b

Audio root clock source setting when the device is configured with

the PLL disabled in the auto clock configuration for slave mode

(AUTO_MODE_PLL_DIS = 1).

0d = BCLK is used as the audio root clock source

1d = MCLK (GPIO or GPIx) is used as the audio root clock source

(the MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting)

6

MCLK_FREQ_SEL_MOD R/W

E

0b

Master mode MCLK (GPIO or GPIx) frequency selection mode (valid

when the device is in auto clock configuration).

0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19)

configuration

1d = MCLK frequency is specified as a multiple of FSYNC in the

MCLK_RATIO_SEL (P0_R22) configuration

5-3

MCLK_RATIO_SEL[2:0]

R/W

010b

These bits select the MCLK (GPIO or GPIx) to FSYNC ratio for

master mode or when MCLK is used as the audio root clock source

in slave mode.

0d = Ratio of 64

1d = Ratio of 256

2d = Ratio of 384

3d = Ratio of 512

4d = Ratio of 768

5d = Ratio of 1024

6d = Ratio of 1536

7d = Ratio of 2304

2

1

RESERVED

R/W

0b

Reserved bit; Write only reset value

INV_BCLK_FOR_FSYNC R/W

Invert BCLK polarity only for FSYNC generation in master mode

configuration.

0d = Do not invert BCLK polarity for FSYNC generation

1d = Invert BCLK polarity for FSYNC generation

0

RESERVED

R/W

0b

Reserved bit; Write only reset value

7.6.1.16 PDMCLK_CFG Register (Address = 0x1F) [Reset = 0x40]

PDMCLK_CFG is shown in 图7-83 and described in 表7-60.

Return to the 表7-44.

This register is the PDM clock generation configuration register.

图7-83. PDMCLK_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

RESERVED

R/W-10000b

PDMCLK_DIV[1:0]

R/W-00b

表7-60. PDMCLK_CFG Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

0b

Reserved bit; Write only reset value

Reserved bits; Write only reset values

PDMCLK divider value.

6-2

1-0

RESERVED

10000b

00b

PDMCLK_DIV[1:0]

0d = PDMCLK is 2.8224 MHz or 3.072 MHz

1d = PDMCLK is 1.4112 MHz or 1.536 MHz

2d = PDMCLK is 705.6 kHz or 768 kHz

3d = PDMCLK is 5.6448 MHz or 6.144 MHz (applicable only for PDM

channel 1 and 2)

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7.6.1.17 PDMIN_CFG Register (Address = 0x20) [Reset = 0x00]

PDMIN_CFG is shown in 图7-84 and described in 表7-61.

Return to the 表7-44.

This register is the PDM DINx sampling edge configuration register.

图7-84. PDMIN_CFG Register

7

6

5

4

3

2

1

0

PDMDIN1_EDG RESERVED

E

RESERVED

R-000000b

R/W-0b

表7-61. PDMIN_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PDMDIN1_EDGE

R/W

0b

PDMCLK latching edge used for channel 1 and channel 2 data.

0d = Channel 1 data are latched on the negative edge, channel 2

data are latched on the positive edge

1d = Channel 1 data are latched on the positive edge, channel 2 data

are latched on the negative edge

6

RESERVED

R/W

R

0b

Reserved bit; Write only reset value

Reserved bits; Write only reset value

5-0

000000b

7.6.1.18 GPIO_CFG0 Register (Address = 0x21) [Reset = 0x22]

GPIO_CFG0 is shown in 图7-85 and described in 表7-62.

Return to the 表7-44.

This register is the GPIO configuration register 0.

图7-85. GPIO_CFG0 Register

7

6

5

4

3

2

1

0

GPIO1_CFG[3:0]

R/W-0010b

RESERVED

R-0b

GPIO1_DRV[2:0]

R/W-010b

表7-62. GPIO_CFG0 Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

GPIO1_CFG[3:0]

R/W

0010b

GPIO1 configuration.

0d = GPIO1 is disabled

1d = GPIO1 is configured as a general-purpose output (GPO)

2d = GPIO1 is configured as a device interrupt output (IRQ)

3d = Reserved; Don't use

4d = GPIO1 is configured as a PDM clock output (PDMCLK)

5d = Reserved; Don't use

6d = Reserved; Don't use

7d = PD all ADC channels

8d = GPIO1 is configured as an input to control when MICBIAS turns

on or off (MICBIAS_EN)

9d = GPIO1 is configured as a general-purpose input (GPI)

10d = GPIO1 is configured as a master clock input (MCLK)

11d = GPIO1 is configured as an ASI input for daisy-chain or ASI

input for mixing (SDIN)

12d = GPIO1 is configured as a PDM data input for channel 1 and

channel 2 (PDMDIN1)

13d = GPIO1 is configured as a PDM data input for channel 3 and

channel 4 (PDMDIN2)

14d to 15d = Reserved; Don't use

3

RESERVED

R

0b

Reserved bit; Write only reset value

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表7-62. GPIO_CFG0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2-0

GPIO1_DRV[2:0]

R/W

010b

GPIO1 output drive configuration.

0d = Hi-Z output

1d = Drive active low and active high

2d = Drive active low and weak high

3d = Drive active low and Hi-Z

4d = Drive weak low and active high

5d = Drive Hi-Z and active high

6d to 7d = Reserved; Don't use

7.6.1.19 GPO_CFG0 Register (Address = 0x22) [Reset = 0x00]

GPO_CFG0 is shown in 图7-86 and described in 表7-63.

Return to the 表7-44.

This registeris the GPO configuration register 0.

图7-86. GPO_CFG0 Register

7

6

5

4

3

2

1

0

GPO1_CFG[3:0]

R/W-0000b

RESERVED

R-0b

GPO1_DRV[2:0]

R/W-000b

表7-63. GPO_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

GPO1_CFG[3:0]

R/W

0000b

GPO1 configuration.

0d = GPO1 is disabled

1d = GPO1 is configured as a general-purpose output (GPO)

2d = GPO1 is configured as a device interrupt output (IRQ)

3d = Reserved; Don't use

4d = GPO1 is configured as a PDM clock output (PDMCLK)

5d to 15d = Reserved; Don't use

3

RESERVED

R

0b

Reserved bit; Write only reset value

2-0

GPO1_DRV[2:0]

R/W

000b

IN2M_GPO1 (GPO1) output drive configuration.

0d = Hi-Z output

1d = Drive active low and active high

2d = Reserved; Don't use

3d = Drive active low and Hi-Z

4d = Reserved; Don't use

5d = Drive Hi-Z and active high

6d to 7d = Reserved; Don't use

7.6.1.20 GPO_VAL Register (Address = 0x29) [Reset = 0x00]

GPO_VAL is shown in 图7-87 and described in 表7-64.

Return to the 表7-44.

This register is the GPIO and GPO output value register.

图7-87. GPO_VAL Register

7

6

5

4

3

2

1

0

GPIO1_VAL

R/W-0b

GPO1_VAL

R/W-0b

RESERVED

R-000000b

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表7-64. GPO_VAL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO1_VAL

R/W

0b

GPIO1 output value when configured as a GPO.

0d = Drive the output with a value of 0

1d = Drive the output with a value of 1

6

GPO1_VAL

RESERVED

R/W

R

0b

GPO1 output value when configured as a GPO.

0d = Drive the output with a value of 0

1d = Drive the output with a value of 1

5-0

000000b

Reserved bits; Write only reset value

7.6.1.21 GPIO_MON Register (Address = 0x2A) [Reset = 0x00]

GPIO_MON is shown in 图7-88 and described in 表7-65.

Return to the 表7-44.

This register is the GPIO monitor value register.

图7-88. GPIO_MON Register

7

6

5

4

3

2

1

0

GPIO1_MON

R-0b

RESERVED

R-0000000b

表7-65. GPIO_MON Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO1_MON

R

0b

GPIO1 monitor value when configured as a GPI.

0d = Input monitor value 0

1d = Input monitor value 1

6-0

RESERVED

R

0000000b

Reserved bits; Write only reset value

7.6.1.22 GPI_CFG0 Register (Address = 0x2B) [Reset = 0x00]

GPI_CFG0 is shown in 图7-89 and described in 表7-66.

Return to the 表7-44.

This register is the GPI configuration register 0.

图7-89. GPI_CFG0 Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

GPI1_CFG[2:0]

R/W-000b

RESERVED

R-0b

GPI2_CFG[2:0]

R/W-000b

表7-66. GPI_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R

0b

Reserved bit; Write only reset value

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表7-66. GPI_CFG0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

6-4

GPI1_CFG[2:0]

R/W

000b

GPI1 (GPI1) configuration.

0d = GPI1 is disabled

1d = GPI1 is configured as a general-purpose input (GPI)

2d = GPI1 is configured as a master clock input (MCLK)

3d = GPI1 is configured as an ASI input for daisy-chain or ASI input

for mixing (SDIN)

4d = GPI1 is configured as a PDM data input for channel 1 and

channel 2 (PDMDIN1)

5d = GPI1 is configured as a PDM data input for channel 3 and

channel 4 (PDMDIN2)

6d = Reserved; Don't use

7d = PD all ADC channels

3

RESERVED

R

0b

Reserved bit; Write only reset value

2-0

GPI2_CFG[2:0]

R/W

000b

MICBIAS_GPI2 as GPI2 configuration.

0d = GPI2 is disabled

1d = GPI2 is configured as a general-purpose input (GPI)

2d = GPI2 is configured as a master clock input (MCLK)

3d = GPI2 is configured as an ASI input for daisy-chain or ASI input

for mixing (SDIN)

4d = GPI2 is configured as a PDM data input for channel 1 and

channel 2 (PDMDIN1)

5d = GPI2 is configured as a PDM data input for channel 3 and

channel 4 (PDMDIN2)

6d = Reserved; Don't use

7d = PD all ADC channels

7.6.1.23 GPI_MON Register (Address = 0x2F) [Reset = 0x00]

GPI_MON is shown in 图7-90 and described in 表7-67.

Return to the 表7-44.

This regiser is the GPI monitor value register.

图7-90. GPI_MON Register

7

6

5

4

3

2

1

0

GPI1_MON

R-0b

GPI2_MON

R-0b

RESERVED

R-000000b

表7-67. GPI_MON Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPI1_MON

GPI2_MON

RESERVED

R

0b

GPI1 monitor value when configured as a GPI.

0d = Input monitor value 0

1d = Input monitor value 1

6

R

0b

GPI2 monitor value when MICBIAS_GPI2 is configured as a GPI.

0d = Input monitor value 0

1d = Input monitor value 1

5-0

000000b

Reserved bits; Write only reset value

7.6.1.24 INT_CFG Register (Address = 0x32) [Reset = 0x00]

INT_CFG is shown in 图7-91 and described in 表7-68.

Return to the 表7-44.

This regiser is the interrupt configuration register.

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图7-91. INT_CFG Register

7

6

5

4

3

2

1

0

INT_POL

INT_EVENT[1:0]

RESERVED

R-00b

LTCH_READ_C

FG

RESERVED

R-00b

R/W-0b

R/W-00b

R/W-0b

表7-68. INT_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

INT_POL

R/W

0b

Interrupt polarity.

0d = Active low (IRQZ)

1d = Active high (IRQ)

6-5

INT_EVENT[1:0]

R/W

00b

Interrupt event configuration.

0d = INT asserts on any unmasked latched interrupts event

Dont use

2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration

on any unmasked latched interrupts event

3d = INT asserts for 2 ms (typical) one time on each pulse for any

unmasked interrupts event

4-3

2

RESERVED

R

00b

0b

Reserved bits; Write only reset value

LTCH_READ_CFG

R/W

Interrupt latch registers readback configuration.

0d = All interrupts can be read through the LTCH registers

1d = Only unmasked interrupts can be read through the LTCH

registers

1-0

RESERVED

R

00b

Reserved bits; Write only reset value

7.6.1.25 INT_MASK0 Register (Address = 0x33) [Reset = 0xFF]

INT_MASK0 is shown in 图7-92 and described in 表7-69.

Return to the 表7-44.

This register is the interrupt masks register 0.

图7-92. INT_MASK0 Register

7

6

5

4

3

2

1

0

INT_MASK0

R/W-1b

INT_MASK0

R/W-1b

INT_MASK0

R/W-1b

INT_MASK0

R/W-1b

INT_MASK0

R/W-1b

RESERVED

R/W-1b

RESERVED

R/W-1b

RESERVED

R/W-1b

表7-69. INT_MASK0 Register Field Descriptions

Bit

Field

INT_MASK0

Type

Reset

Description

7

R/W

1b

ASI clock error mask.

0d = Do not mask

1d = Mask

6

5

4

3

2

INT_MASK0

RESERVED

R/W

1b

PLL Lock interrupt mask.

0d = Do not mask

1d = Mask

ASI input mixing saturation alert mask.

0d = Do not mask

1d = Mask

VAD Power up detect interrupt mask.

0d = Do not mask

1d = Mask

VAD Power down detect interrupt mask.

0d = Do not mask

1d = Mask

Reserved bit; Write only reset value

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表7-69. INT_MASK0 Register Field Descriptions (continued)

Bit

1

Field

Type

R/W

Reset

Description

RESERVED

1b

Reserved bit; Write only reset value

0

1b

7.6.1.26 INT_LTCH0 Register (Address = 0x36) [Reset = 0x00]

INT_LTCH0 is shown in 图7-93 and described in 表7-70.

Return to the 表7-44.

This register is the latched Interrupt readback register 0.

图7-93. INT_LTCH0 Register

7

6

5

4

3

2

1

0

INT_LTCH0

R-0b

INT_LTCH0

R-0b

INT_LTCH0

R-0b

INT_LTCH0

R-0b

INT_LTCH0

R-0b

RESERVED

R-0b

RESERVED

R-0b

RESERVED

R-0b

表7-70. INT_LTCH0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

INT_LTCH0

R

0b

Interrupt caused by an ASI bus clock error (self-clearing bit).

0d = No interrupt

1d = Interrupt

6

5

R

0b

Interrupt caused by PLL LOCK (self-clearing bit).

0d = No interrupt

1d = Interrupt

Interrupt caused by ASI input mixing channel saturation alert (self

clearing bit).

0d = No interrupt

1d = Interrupt

4

3

INT_LTCH0

R

0b

Interrupt caused by VAD power up detect (self clearing bit).

0d = No interrupt

1d = Interrupt

Interrupt caused by VAD power down detect (self clearing bit).

0d = No interrupt

1d = Interrupt

2

1

0

RESERVED

R

0b

Reserved bit; Write only reset value

7.6.1.27 BIAS_CFG Register (Address = 0x3B) [Reset = 0x00]

BIAS_CFG is shown in 图7-94 and described in 表7-71.

Return to the 表7-44.

This register is the bias and ADC configuration register

图7-94. BIAS_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

MBIAS_VAL[2:0]

R/W-000b

RESERVED

R-00b

RESERVED

R/W-00b

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表7-71. BIAS_CFG Register Field Descriptions

Bit

7

Field

Type

Reset

Description

RESERVED

MBIAS_VAL[2:0]

R

0b

Reserved bit; Write only reset value

MICBIAS value.

6-4

R/W

000b

0d = Microphone bias is set to VREF (2.750 V, 2.500 V, or 1.375 V)

1d = Microphone bias is set to VREF x 1.096 (3.014 V, 2.740 V, or

1.507 V)

Dont use

6d = Microphone bias is set to AVDD

7d = MICBIAS configured as GPI2

3-2

1-0

RESERVED

R

00b

Reserved bits; Write only reset value

Reserved bits; Write only reset values

R/W

7.6.1.28 CH1_CFG2 Register (Address = 0x3E) [Reset = 0xC9]

CH1_CFG2 is shown in 图7-95 and described in 表7-72.

Return to the 表7-44.

This register is configuration register 2 for channel 1.

图7-95. CH1_CFG2 Register

7

6

5

4

3

2

1

0

CH1_DVOL[7:0]

R/W-11001001b

表7-72. CH1_CFG2 Register Field Descriptions

Bit

7-0

Field

CH1_DVOL[7:0]

Type

Reset

Description

R/W

11001001b Channel 1 digital volume control.

0d = Digital volume is muted

1d = Digital volume control is set to -100 dB

2d = Digital volume control is set to -99.5 dB

3d to 200d = Digital volume control is set as per configuration

201d = Digital volume control is set to 0 dB

202d = Digital volume control is set to 0.5 dB

203d to 253d = Digital volume control is set as per configuration

254d = Digital volume control is set to 26.5 dB

255d = Digital volume control is set to 27 dB

7.6.1.29 CH1_CFG3 Register (Address = 0x3F) [Reset = 0x80]

CH1_CFG3 is shown in 图7-96 and described in 表7-73.

Return to the 表7-44.

This register is configuration register 3 for channel 1.

图7-96. CH1_CFG3 Register

7

6

5

4

3

2

1

0

CH1_GCAL[3:0]

R/W-1000b

RESERVED

R-0000b

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表7-73. CH1_CFG3 Register Field Descriptions

Bit

Field

CH1_GCAL[3:0]

Type

Reset

Description

7-4

R/W

1000b

Channel 1 gain calibration.

0d = Gain calibration is set to -0.8 dB

1d = Gain calibration is set to -0.7 dB

2d = Gain calibration is set to -0.6 dB

3d to 7d = Gain calibration is set as per configuration

8d = Gain calibration is set to 0 dB

9d = Gain calibration is set to 0.1 dB

10d to 13d = Gain calibration is set as per configuration

14d = Gain calibration is set to 0.6 dB

15d = Gain calibration is set to 0.7 dB

3-0

RESERVED

R

0000b

Reserved bits; Write only reset value

7.6.1.30 CH1_CFG4 Register (Address = 0x40) [Reset = 0x00]

CH1_CFG4 is shown in 图7-97 and described in 表7-74.

Return to the 表7-44.

This register is configuration register 4 for channel 1.

图7-97. CH1_CFG4 Register

7

6

5

4

3

2

1

0

CH1_PCAL[7:0]

R/W-00000000b

表7-74. CH1_CFG4 Register Field Descriptions

Bit

7-0

Field

CH1_PCAL[7:0]

Type

Reset

Description

R/W

00000000b Channel 1 phase calibration with modulator clock resolution.

0d = No phase calibration

1d = Phase calibration delay is set to one cycle of the modulator

clock

2d = Phase calibration delay is set to two cycles of the modulator

clock

3d to 254d = Phase calibration delay as per configuration

255d = Phase calibration delay is set to 255 cycles of the modulator

clock

7.6.1.31 CH2_CFG0 Register (Address = 0x41) [Reset = 0x00]

CH2_CFG0 is shown in 图7-98 and described in 表7-75.

Return to the 表7-44.

This register is configuration register 0 for channel 2.

图7-98. CH2_CFG0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

CH2_INSRC[1:0]

R/W-00b

RESERVED

R/W-0b

RESERVED

R/W-00b

RESERVED

R-0b

RESERVED

R/W-0b

表7-75. CH2_CFG0 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7

R/W

0b

Reserved bit; Write only reset value

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表7-75. CH2_CFG0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

6-5

CH2_INSRC[1:0]

R/W

00b

Channel 2 input configuration.

0d = Input Source is not enabled

Dont use

2d = Digital microphone PDM input (configure the GPO and GPI pins

accordingly for PDMDIN1 and PDMCLK)

Dont use

4

3-2

1

RESERVED

R/W

R

0b

Reserved bit; Write only reset value

Reserved bits; Write only reset values

Reserved bit; Write only reset value

00b

0b

0

R/W

0b

7.6.1.32 CH2_CFG2 Register (Address = 0x43) [Reset = 0xC9]

CH2_CFG2 is shown in 图7-99 and described in 表7-76.

Return to the 表7-44.

This register is configuration register 2 for channel 2.

图7-99. CH2_CFG2 Register

7

6

5

4

3

2

1

0

CH2_DVOL[7:0]

R/W-11001001b

表7-76. CH2_CFG2 Register Field Descriptions

Bit

7-0

Field

CH2_DVOL[7:0]

Type

Reset

Description

R/W

11001001b Channel 2 digital volume control.

0d = Digital volume is muted

1d = Digital volume control is set to -100 dB

2d = Digital volume control is set to -99.5 dB

3d to 200d = Digital volume control is set as per configuration

201d = Digital volume control is set to 0 dB

202d = Digital volume control is set to 0.5 dB

203d to 253d = Digital volume control is set as per configuration

254d = Digital volume control is set to 26.5 dB

255d = Digital volume control is set to 27 dB

7.6.1.33 CH2_CFG3 Register (Address = 0x44) [Reset = 0x80]

CH2_CFG3 is shown in 图7-100 and described in 表7-77.

Return to the 表7-44.

This register is configuration register 3 for channel 2.

图7-100. CH2_CFG3 Register

7

6

5

4

3

2

1

0

CH2_GCAL[3:0]

R/W-1000b

RESERVED

R-0000b

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表7-77. CH2_CFG3 Register Field Descriptions

Bit

Field

CH2_GCAL[3:0]

Type

Reset

Description

7-4

R/W

1000b

Channel 2 gain calibration.

0d = Gain calibration is set to -0.8 dB

1d = Gain calibration is set to -0.7 dB

2d = Gain calibration is set to -0.6 dB

3d to 7d = Gain calibration is set as per configuration

8d = Gain calibration is set to 0 dB

9d = Gain calibration is set to 0.1 dB

10d to 13d = Gain calibration is set as per configuration

14d = Gain calibration is set to 0.6 dB

15d = Gain calibration is set to 0.7 dB

3-0

RESERVED

R

0000b

Reserved bits; Write only reset value

7.6.1.34 CH2_CFG4 Register (Address = 0x45) [Reset = 0x00]

CH2_CFG4 is shown in 图7-101 and described in 表7-78.

Return to the 表7-44.

This register is configuration register 4 for channel 2.

图7-101. CH2_CFG4 Register

7

6

5

4

3

2

1

0

CH2_PCAL[7:0]

R/W-00000000b

表7-78. CH2_CFG4 Register Field Descriptions

Bit

7-0

Field

CH2_PCAL[7:0]

Type

Reset

Description

R/W

00000000b Channel 2 phase calibration with modulator clock resolution.

0d = No phase calibration

1d = Phase calibration delay is set to one cycle of the modulator

clock

2d = Phase calibration delay is set to two cycles of the modulator

clock

3d to 254d = Phase calibration delay as per configuration

255d = Phase calibration delay is set to 255 cycles of the modulator

clock

7.6.1.35 CH3_CFG2 Register (Address = 0x48) [Reset = 0xC9]

CH3_CFG2 is shown in 图7-102 and described in 表7-79.

Return to the 表7-44.

This register is configuration register 2 for channel 3.

图7-102. CH3_CFG2 Register

7

6

5

4

3

2

1

0

CH3_DVOL[7:0]

R/W-11001001b

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表7-79. CH3_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

CH3_DVOL[7:0]

R/W

11001001b Channel 3 digital volume control.

0d = Digital volume is muted

1d = Digital volume control is set to -100 dB

2d = Digital volume control is set to -99.5 dB

3d to 200d = Digital volume control is set as per configuration

201d = Digital volume control is set to 0 dB

202d = Digital volume control is set to 0.5 dB

203d to 253d = Digital volume control is set as per configuration

254d = Digital volume control is set to 26.5 dB

255d = Digital volume control is set to 27 dB

7.6.1.36 CH3_CFG3 Register (Address = 0x49) [Reset = 0x80]

CH3_CFG3 is shown in 图7-103 and described in 表7-80.

Return to the 表7-44.

This register is configuration register 3 for channel 3.

图7-103. CH3_CFG3 Register

7

6

5

4

3

2

1

0

CH3_GCAL[3:0]

R/W-1000b

RESERVED

R-0000b

表7-80. CH3_CFG3 Register Field Descriptions

Bit

7-4

Field

CH3_GCAL[3:0]

Type

Reset

Description

R/W

1000b

Channel 3 gain calibration.

0d = Gain calibration is set to -0.8 dB

1d = Gain calibration is set to -0.7 dB

2d = Gain calibration is set to -0.6 dB

3d to 7d = Gain calibration is set as per configuration

8d = Gain calibration is set to 0 dB

9d = Gain calibration is set to 0.1 dB

10d to 13d = Gain calibration is set as per configuration

14d = Gain calibration is set to 0.6 dB

15d = Gain calibration is set to 0.7 dB

3-0

RESERVED

R

0000b

Reserved bits; Write only reset value

7.6.1.37 CH3_CFG4 Register (Address = 0x4A) [Reset = 0x00]

CH3_CFG4 is shown in 图7-104 and described in 表7-81.

Return to the 表7-44.

This register is configuration register 4 for channel 3.

图7-104. CH3_CFG4 Register

7

6

5

4

3

2

1

0

CH3_PCAL[7:0]

R/W-00000000b

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表7-81. CH3_CFG4 Register Field Descriptions

Bit

Field

CH3_PCAL[7:0]

Type

Reset

Description

7-0

R/W

00000000b Channel 3 phase calibration with modulator clock resolution.

0d = No phase calibration

1d = Phase calibration delay is set to one cycle of the modulator

clock

2d = Phase calibration delay is set to two cycles of the modulator

clock

3d to 254d = Phase calibration delay as per configuration

255d = Phase calibration delay is set to 255 cycles of the modulator

clock

7.6.1.38 CH4_CFG2 Register (Address = 0x4D) [Reset = 0xC9]

CH4_CFG2 is shown in 图7-105 and described in 表7-82.

Return to the 表7-44.

This register is configuration register 2 for channel 4.

图7-105. CH4_CFG2 Register

7

6

5

4

3

2

1

0

CH4_DVOL[7:0]

R/W-11001001b

表7-82. CH4_CFG2 Register Field Descriptions

Bit

7-0

Field

CH4_DVOL[7:0]

Type

Reset

Description

R/W

11001001b Channel 4 digital volume control.

0d = Digital volume is muted

1d = Digital volume control is set to -100 dB

2d = Digital volume control is set to -99.5 dB

3d to 200d = Digital volume control is set as per configuration

201d = Digital volume control is set to 0 dB

202d = Digital volume control is set to 0.5 dB

203d to 253d = Digital volume control is set as per configuration

254d = Digital volume control is set to 26.5 dB

255d = Digital volume control is set to 27 dB

7.6.1.39 CH4_CFG3 Register (Address = 0x4E) [Reset = 0x80]

CH4_CFG3 is shown in 图7-106 and described in 表7-83.

Return to the 表7-44.

This register is configuration register 3 for channel 4.

图7-106. CH4_CFG3 Register

7

6

5

4

3

2

1

0

CH4_GCAL[3:0]

R/W-1000b

RESERVED

R-0000b

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表7-83. CH4_CFG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CH4_GCAL[3:0]

R/W

1000b

Channel 4 gain calibration.

0d = Gain calibration is set to -0.8 dB

1d = Gain calibration is set to -0.7 dB

2d = Gain calibration is set to -0.6 dB

3d to 7d = Gain calibration is set as per configuration

8d = Gain calibration is set to 0 dB

9d = Gain calibration is set to 0.1 dB

10d to 13d = Gain calibration is set as per configuration

14d = Gain calibration is set to 0.6 dB

15d = Gain calibration is set to 0.7 dB

3-0

RESERVED

R

0000b

Reserved bits; Write only reset value

7.6.1.40 CH4_CFG4 Register (Address = 0x4F) [Reset = 0x00]

CH4_CFG4 is shown in 图7-107 and described in 表7-84.

Return to the 表7-44.

This register is configuration register 4 for channel 4.

图7-107. CH4_CFG4 Register

7

6

5

4

3

2

1

0

CH4_PCAL[7:0]

R/W-00000000b

表7-84. CH4_CFG4 Register Field Descriptions

Bit

7-0

Field

CH4_PCAL[7:0]

Type

Reset

Description

R/W

00000000b Channel 4 phase calibration with modulator clock resolution.

0d = No phase calibration

1d = Phase calibration delay is set to one cycle of the modulator

clock

2d = Phase calibration delay is set to two cycles of the modulator

clock

3d to 254d = Phase calibration delay as per configuration

255d = Phase calibration delay is set to 255 cycles of the modulator

clock

7.6.1.41 DSP_CFG0 Register (Address = 0x6B) [Reset = 0x01]

DSP_CFG0 is shown in 图7-108 and described in 表7-85.

Return to the 表7-44.

This register is the digital signal processor (DSP) configuration register 0.

图7-108. DSP_CFG0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

RESERVED

R/W-0b

DECI_FILT[1:0]

R/W-00b

CH_SUM[1:0]

R/W-00b

HPF_SEL[1:0]

R/W-01b

表7-85. DSP_CFG0 Register Field Descriptions

Bit

7

Field

RESERVED

Type

R/W

Reset

Description

0b

Reserved bit; Write only reset value

6

0b

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表7-85. DSP_CFG0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-4

DECI_FILT[1:0]

R/W

00b

Decimation filter response.

0d = Linear phase

1d = Low latency

2d = Ultra-low latency

3d = Reserved; Don't use

3-2

1-0

CH_SUM[1:0]

R/W

00b

01b

Channel summation mode for higher SNR

0d = Channel summation mode is disabled

1d = 2-channel summation mode is enabled to generate a (CH1 +

CH2) / 2 output

2d = Reserved; Don't use

3d = Reserved; Don't use

HPF_SEL[1:0]

High-pass filter (HPF) selection.

0d = Programmable first-order IIR filter for a custom HPF with default

coefficient values in P4_R72 to P4_R83 set as the all-pass filter

1d = HPF with a cutoff of 0.00025 x f_S(12 Hz at f_S= 48 kHz) is

selected

2d = HPF with a cutoff of 0.002 x f_S(96 Hz at f_S= 48 kHz) is selected

3d = HPF with a cutoff of 0.008 x f_S(384 Hz at f_S= 48 kHz) is

selected

7.6.1.42 DSP_CFG1 Register (Address = 0x6C) [Reset = 0x40]

DSP_CFG1 is shown in 图7-109 and described in 表7-86.

Return to the 表7-44.

This register is the digital signal processor (DSP) configuration register 1.

图7-109. DSP_CFG1 Register

7

6

5

4

3

2

1

0

DVOL_GANG

BIQUAD_CFG[1:0]

DISABLE_SOF

T_STEP

RESERVED

R/W-0b

R/W-10b

R/W-0b

表7-86. DSP_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DVOL_GANG

R/W

0b

DVOL control ganged across channels.

0d = Each channel has its own DVOL CTRL settings as programmed

in the CHx_DVOL bits

1d = All active channels must use the channel 1 DVOL setting

(CH1_DVOL) irrespective of whether channel 1 is turned on or not

6-5

4

BIQUAD_CFG[1:0]

DISABLE_SOFT_STEP

R/W

10b

0b

Number of biquads per channel configuration.

0d = No biquads per channel; biquads are all disabled

1d = 1 biquad per channel

2d = 2 biquads per channel

3d = 3 biquads per channel

Soft-stepping disable during DVOL change, mute, and unmute.

0d = Soft-stepping enabled

1d = Soft-stepping disabled

3

2

1

0

RESERVED

R/W

0b

Reserved bit; Write only reset value

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7.6.1.43 IN_CH_EN Register (Address = 0x73) [Reset = 0xC0]

IN_CH_EN is shown in 图7-110 and described in 表7-87.

Return to the 表7-44.

This register is the input channel enable configuration register.

图7-110. IN_CH_EN Register

7

6

5

4

3

2

1

0

IN_CH1_EN

R/W-1b

IN_CH2_EN

R/W-1b

IN_CH3_EN

R/W-0b

IN_CH4_EN

R/W-0b

RESERVED

R-0000b

表7-87. IN_CH_EN Register Field Descriptions

Bit

Field

IN_CH1_EN

Type

Reset

Description

7

R/W

1b

Input channel 1 enable setting.

0d = Channel 1 is disabled

1d = Channel 1 is enabled

6

5

IN_CH2_EN

IN_CH3_EN

IN_CH4_EN

RESERVED

R/W

R

1b

Input channel 2 enable setting.

0d = Channel 2 is disabled

1d = Channel 2 is enabled

0b

Input channel 3 (PDM only) enable setting.

0d = Channel 3 is disabled

1d = Channel 3 is enabled

4

0b

Input channel 4 (PDM only) enable setting.

0d = Channel 4 is disabled

1d = Channel 4 is enabled

3-0

0000b

Reserved bits; Write only reset value

7.6.1.44 ASI_OUT_CH_EN Register (Address = 0x74) [Reset = 0x00]

ASI_OUT_CH_EN is shown in 图7-111 and described in 表7-88.

Return to the 表7-44.

This register is the ASI output channel enable configuration register.

图7-111. ASI_OUT_CH_EN Register

7

6

5

4

3

2

1

0

ASI_OUT_CH1 ASI_OUT_CH2 ASI_OUT_CH3 ASI_OUT_CH4

RESERVED

R-0000b

_EN

R/W-0b

表7-88. ASI_OUT_CH_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ASI_OUT_CH1_EN

ASI_OUT_CH2_EN

ASI_OUT_CH3_EN

ASI_OUT_CH4_EN

R/W

0b

ASI output channel 1 enable setting.

0d = Channel 1 output slot is in a tri-state condition

1d = Channel 1 output slot is enabled

6

5

4

R/W

0b

ASI output channel 2 enable setting.

0d = Channel 2 output slot is in a tri-state condition

1d = Channel 2 output slot is enabled

ASI output channel 3 enable setting.

0d = Channel 3 output slot is in a tri-state condition

1d = Channel 3 output slot is enabled

ASI output channel 4 enable setting.

0d = Channel 4 output slot is in a tri-state condition

1d = Channel 4 output slot is enabled

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表7-88. ASI_OUT_CH_EN Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

RESERVED

R

0000b

Reserved bits; Write only reset value

7.6.1.45 PWR_CFG Register (Address = 0x75) [Reset = 0x00]

PWR_CFG is shown in 图7-112 and described in 表7-89.

Return to the 表7-44.

This register is the power-up configuration register.

图7-112. PWR_CFG Register

7

6

5

4

3

2

1

0

MICBIAS_PDZ

ADC_PDZ

PLL_PDZ

DYN_CH_PUP

D_EN

DYN_MAXCH_SEL[1:0]

RESERVED

VAD_EN

R/W-0b

R/W-00b

R/W-0b

表7-89. PWR_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MICBIAS_PDZ

R/W

0b

Power control for MICBIAS.

0d = Power down MICBIAS

1d = Power up MICBIAS

6

5

4

ADC_PDZ

R/W

0b

Power control for PDM channels.

0d = Power down all PDM channels

1d = Power up all enabled PDM channels

PLL_PDZ

Power control for the PLL.

0d = Power down the PLL

1d = Power up the PLL

DYN_CH_PUPD_EN

Dynamic channel power-up, power-down enable.

0d = Channel power-up, power-down is not supported if any channel

recording is on

1d = Channel can be powered up or down individually, even if

channel recording is on

3-2

DYN_MAXCH_SEL[1:0]

R/W

00b

Dynamic mode maximum channel select configuration.

0d = Channel 1 and channel 2 are used with dynamic channel

power-up, power-down feature enabled

1d = Channel 1 to channel 4 are used with dynamic channel power-

up, power-down feature enabled

2d = Reserved; Don't use

3d = Reserved; Don't use

1

0

RESERVED

VAD_EN

R/W

0b

Reserved bit; Write only reset value

Enable voice activity detection (VAD) algorithm.

0d = VAD is disabled

1d = VAD is enabled

7.6.1.46 DEV_STS0 Register (Address = 0x76) [Reset = 0x00]

DEV_STS0 is shown in 图7-113 and described in 表7-90.

Return to the 表7-44.

This register is the device status value register 0.

图7-113. DEV_STS0 Register

7

6

5

4

3

2

1

0

CH1_STATUS CH2_STATUS

RESERVED

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图7-113. DEV_STS0 Register (continued)

R-0b

R-000000b

表7-90. DEV_STS0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

CH1_STATUS

CH2_STATUS

RESERVED

R

0b

PDM channel 1 power status.

0d = PDM channel is powered down

1d = PDM channel is powered up

6

R

0b

PDM channel 2 power status.

0d = PDM channel is powered down

1d = PDM channel is powered up

5-0

000000b

Reserved bits; Write only reset value

7.6.1.47 DEV_STS1 Register (Address = 0x77) [Reset = 0x80]

DEV_STS1 is shown in 图7-114 and described in 表7-91.

Return to the 表7-44.

This register is the device status value register 1.

图7-114. DEV_STS1 Register

7

6

5

4

3

2

1

0

MODE_STS[2:0]

R-100b

RESERVED

R-00000b

表7-91. DEV_STS1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

MODE_STS[2:0]

R

100b

Device mode status.

4d = Device is in sleep mode or software shutdown mode

6d = Device is in active mode with all PDM channels turned off

7d = Device is in active mode with at least one PDM channel turned

on

4-0

RESERVED

R

00000b

Reserved bits; Write only reset value

7.6.1.48 I2C_CKSUM Register (Address = 0x7E) [Reset = 0x00]

I2C_CKSUM is shown in 图7-115 and described in 表7-92.

Return to the 表7-44.

This register returns the I²C transactions checksum value.

图7-115. I2C_CKSUM Register

7

6

5

4

3

2

1

0

I2C_CKSUM[7:0]

R/W-00000000b

表7-92. I2C_CKSUM Register Field Descriptions

Bit

7-0

Field

I2C_CKSUM[7:0]

Type

Reset

Description

R/W

00000000b These bits return the I²C transactions checksum value. Writing to this

register resets the checksum to the written value. This register is

updated on writes to other registers on all pages.

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7.6.2 Page 1 Registers

表 7-93 lists the memory-mapped registers for the Page 1 registers. All register offset addresses not listed in 表

7-93 should be considered as reserved locations and the register contents should not be modified.

表7-93. PAGE 1 Registers

Address

0x0

Acronym

Register Name

Reset Value

0x00

Section

节7.6.2.1

节7.6.2.2

节7.6.2.3

PAGE_CFG

VAD_CFG1

VAD_CFG2

Device page register

0x1E

Voice activity detection configuration register 1

Voice activity detection configuration register 2

0x20

0x1F

0x08

7.6.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x0]

PAGE_CFG is shown in 图7-116 and described in 表7-94.

Return to the 表7-93.

The device memory map is divided into pages. This register sets the page.

图7-116. PAGE_CFG Register

7

6

5

4

3

2

1

0

PAGE[7:0]

R/W-00000000b

表7-94. PAGE_CFG Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

PAGE[7:0]

R/W

00000000b These bits set the device page.

0d = Page 0

1d = Page 1

2d to 254d = Page 2 to page 254 respectively

255d = Page 255

7.6.2.2 VAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]

VAD_CFG1 is shown in 图7-117 and described in 表7-95.

Return to the 表7-93.

This register is configuration register 1 for voice activity detection.

图7-117. VAD_CFG1 Register

7

6

5

4

3

2

1

0

VAD_MODE[1:0]

VAD_CH_SEL[1:0]

R/W-10b

VAD_CLK_CFG[1:0]

R/W-00b

VAD_EXT_CLK_CFG[1:0]

R/W-00b

表7-95. VAD_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

VAD_MODE[1:0]

R/W

00b

Auto ADC power up / power down configuration selection.

0d = User initiated ADC power-up and ADC power-down

1d = VAD interrupt based ADC power up and ADC power down

2d = VAD interrupt based ADC power up but user initiated ADC

power down

3d = User initiated ADC power-up but VAD interrupt based ADC

power down

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表7-95. VAD_CFG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-4

VAD_CH_SEL[1:0]

R/W

10b

VAD channel select.

0d = Channel 1 is monitored for VAD activity

1d = Channel 2 is monitored for VAD activity

2d = Channel 3 is monitored for VAD activity

3d = Channel 4 is monitored for VAD activity

3-2

1-0

VAD_CLK_CFG[1:0]

R/W

00b

Clock select for VAD

0d = VAD processing using internal oscillator clock

1d = VAD processing using external clock on BCLK input

2d = VAD processing using external clock on MCLK input

3d = Custom clock configuration based on MST_CFG, CLK_SRC

and CLKGEN_CFG registers in page 0

VAD_EXT_CLK_CFG[1:0] R/W

Clock configuration using external clock for VAD.

0d = External clock is 3.072 MHz

1d = External clock is 6.144 MHz

2d = External clock is 12.288 MHz

3d = External clock is 18.432 MHz

7.6.2.3 VAD_CFG2 Register (Address = 0x1F) [Reset = 0x8]

VAD_CFG2 is shown in 图7-118 and described in 表7-96.

Return to the 表7-93.

This register is configuration register 2 for voice activity detection.

图7-118. VAD_CFG2 Register

7

6

5

4

3

2

1

0

RESERVED

SDOUT_INT_C

FG

RESERVED

VAD_PD_DET_

EN

RESERVED

R/W-0b

R-0b

R/W-0b

R/W-1b

R-000b

表7-96. VAD_CFG2 Register Field Descriptions

Bit

7

Field

RESERVED

Type

R/W

Reset

Description

0b

Reserved bit; Write only reset value

SDOUT interrupt configuration.

6

SDOUT_INT_CFG

0b

0d = SDOUT pin is not enabled for interrupt function

1d = SDOUT pin is enabled to support interrupt output when channel

data in not being recorded

5

4

3

RESERVED

R

0b

1b

Reserved bit; Write only reset value

RESERVED

R/W

VAD_PD_DET_EN

Enable ASI output data during VAD activity.

0d = VAD processing is not enabled during ADC recording

1d = VAD processing is enabled during ADC recording and VAD

interrupts are generated as configured

2-0

RESERVED

R

000b

Reserved bits; Write only reset values

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7.6.3 Programmable Coefficient Registers

7.6.3.1 Programmable Coefficient Registers: Page 2

This register page (shown in 表 7-97) consists of the programmable coefficients for the biquad 1 to biquad 6

filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also

supports (by default) auto-incremented pages for the I²C writes and reads. After a transaction of register address

0x7F, the device auto increments to the next page at register 0x08 to transact the next coefficient value.

表7-97. Page 2 Programmable Coefficient Registers

Address

0x00

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

Acronym

Register Name

Reset Value

0x00

0x7F

0xFF

0x00

0x7F

0xFF

0x00

0x7F

0xFF

PAGE[7:0]

Device page register

BQ1_N0_BYT1[7:0]

BQ1_N0_BYT2[7:0]

BQ1_N0_BYT3[7:0]

BQ1_N0_BYT4[7:0]

BQ1_N1_BYT1[7:0]

BQ1_N1_BYT2[7:0]

BQ1_N1_BYT3[7:0]

BQ1_N1_BYT4[7:0]

BQ1_N2_BYT1[7:0]

BQ1_N2_BYT2[7:0]

BQ1_N2_BYT3[7:0]

BQ1_N2_BYT4[7:0]

BQ1_D1_BYT1[7:0]

BQ1_D1_BYT2[7:0]

BQ1_D1_BYT3[7:0]

BQ1_D1_BYT4[7:0]

BQ1_D2_BYT1[7:0]

BQ1_D2_BYT2[7:0]

BQ1_D2_BYT3[7:0]

BQ1_D2_BYT4[7:0]

BQ2_N0_BYT1[7:0]

BQ2_N0_BYT2[7:0]

BQ2_N0_BYT3[7:0]

BQ2_N0_BYT4[7:0]

BQ2_N1_BYT1[7:0]

BQ2_N1_BYT2[7:0]

BQ2_N1_BYT3[7:0]

BQ2_N1_BYT4[7:0]

BQ2_N2_BYT1[7:0]

BQ2_N2_BYT2[7:0]

BQ2_N2_BYT3[7:0]

BQ2_N2_BYT4[7:0]

BQ2_D1_BYT1[7:0]

BQ2_D1_BYT2[7:0]

BQ2_D1_BYT3[7:0]

BQ2_D1_BYT4[7:0]

BQ2_D2_BYT1[7:0]

BQ2_D2_BYT2[7:0]

BQ2_D2_BYT3[7:0]

BQ2_D2_BYT4[7:0]

BQ3_N0_BYT1[7:0]

BQ3_N0_BYT2[7:0]

Programmable biquad 1, N0 coefficient byte[31:24]

Programmable biquad 1, N0 coefficient byte[23:16]

Programmable biquad 1, N0 coefficient byte[15:8]

Programmable biquad 1, N0 coefficient byte[7:0]

Programmable biquad 1, N1 coefficient byte[31:24]

Programmable biquad 1, N1 coefficient byte[23:16]

Programmable biquad 1, N1 coefficient byte[15:8]

Programmable biquad 1, N1 coefficient byte[7:0]

Programmable biquad 1, N2 coefficient byte[31:24]

Programmable biquad 1, N2 coefficient byte[23:16]

Programmable biquad 1, N2 coefficient byte[15:8]

Programmable biquad 1, N2 coefficient byte[7:0]

Programmable biquad 1, D1 coefficient byte[31:24]

Programmable biquad 1, D1 coefficient byte[23:16]

Programmable biquad 1, D1 coefficient byte[15:8]

Programmable biquad 1, D1 coefficient byte[7:0]

Programmable biquad 1, D2 coefficient byte[31:24]

Programmable biquad 1, D2 coefficient byte[23:16]

Programmable biquad 1, D2 coefficient byte[15:8]

Programmable biquad 1, D2 coefficient byte[7:0]

Programmable biquad 2, N0 coefficient byte[31:24]

Programmable biquad 2, N0 coefficient byte[23:16]

Programmable biquad 2, N0 coefficient byte[15:8]

Programmable biquad 2, N0 coefficient byte[7:0]

Programmable biquad 2, N1 coefficient byte[31:24]

Programmable biquad 2, N1 coefficient byte[23:16]

Programmable biquad 2, N1 coefficient byte[15:8]

Programmable biquad 2, N1 coefficient byte[7:0]

Programmable biquad 2, N2 coefficient byte[31:24]

Programmable biquad 2, N2 coefficient byte[23:16]

Programmable biquad 2, N2 coefficient byte[15:8]

Programmable biquad 2, N2 coefficient byte[7:0]

Programmable biquad 2, D1 coefficient byte[31:24]

Programmable biquad 2, D1 coefficient byte[23:16]

Programmable biquad 2, D1 coefficient byte[15:8]

Programmable biquad 2, D1 coefficient byte[7:0]

Programmable biquad 2, D2 coefficient byte[31:24]

Programmable biquad 2, D2 coefficient byte[23:16]

Programmable biquad 2, D2 coefficient byte[15:8]

Programmable biquad 2, D2 coefficient byte[7:0]

Programmable biquad 3, N0 coefficient byte[31:24]

Programmable biquad 3, N0 coefficient byte[23:16]

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表7-97. Page 2 Programmable Coefficient Registers (continued)

Address

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

Acronym

Register Name

Reset Value

BQ3_N0_BYT3[7:0]

Programmable biquad 3, N0 coefficient byte[15:8]

Programmable biquad 3, N0 coefficient byte[7:0]

Programmable biquad 3, N1 coefficient byte[31:24]

Programmable biquad 3, N1 coefficient byte[23:16]

Programmable biquad 3, N1 coefficient byte[15:8]

Programmable biquad 3, N1 coefficient byte[7:0]

Programmable biquad 3, N2 coefficient byte[31:24]

Programmable biquad 3, N2 coefficient byte[23:16]

Programmable biquad 3, N2 coefficient byte[15:8]

Programmable biquad 3, N2 coefficient byte[7:0]

Programmable biquad 3, D1 coefficient byte[31:24]

Programmable biquad 3, D1 coefficient byte[23:16]

Programmable biquad 3, D1 coefficient byte[15:8]

Programmable biquad 3, D1 coefficient byte[7:0]

Programmable biquad 3, D2 coefficient byte[31:24]

Programmable biquad 3, D2 coefficient byte[23:16]

Programmable biquad 3, D2 coefficient byte[15:8]

Programmable biquad 3, D2 coefficient byte[7:0]

Programmable biquad 4, N0 coefficient byte[31:24]

Programmable biquad 4, N0 coefficient byte[23:16]

Programmable biquad 4, N0 coefficient byte[15:8]

Programmable biquad 4, N0 coefficient byte[7:0]

Programmable biquad 4, N1 coefficient byte[31:24]

Programmable biquad 4, N1 coefficient byte[23:16]

Programmable biquad 4, N1 coefficient byte[15:8]

Programmable biquad 4, N1 coefficient byte[7:0]

Programmable biquad 4, N2 coefficient byte[31:24]

Programmable biquad 4, N2 coefficient byte[23:16]

Programmable biquad 4, N2 coefficient byte[15:8]

Programmable biquad 4, N2 coefficient byte[7:0]

Programmable biquad 4, D1 coefficient byte[31:24]

Programmable biquad 4, D1 coefficient byte[23:16]

Programmable biquad 4, D1 coefficient byte[15:8]

Programmable biquad 4, D1 coefficient byte[7:0]

Programmable biquad 4, D2 coefficient byte[31:24]

Programmable biquad 4, D2 coefficient byte[23:16]

Programmable biquad 4, D2 coefficient byte[15:8]

Programmable biquad 4, D2 coefficient byte[7:0]

Programmable biquad 5, N0 coefficient byte[31:24]

Programmable biquad 5, N0 coefficient byte[23:16]

Programmable biquad 5, N0 coefficient byte[15:8]

Programmable biquad 5, N0 coefficient byte[7:0]

Programmable biquad 5, N1 coefficient byte[31:24]

Programmable biquad 5, N1 coefficient byte[23:16]

Programmable biquad 5, N1 coefficient byte[15:8]

Programmable biquad 5, N1 coefficient byte[7:0]

Programmable biquad 5, N2 coefficient byte[31:24]

Programmable biquad 5, N2 coefficient byte[23:16]

Programmable biquad 5, N2 coefficient byte[15:8]

Programmable biquad 5, N2 coefficient byte[7:0]

0xFF

0x00

0x7F

0xFF

0x00

0x7F

0xFF

0x00

BQ3_N0_BYT4[7:0]

BQ3_N1_BYT1[7:0]

BQ3_N1_BYT2[7:0]

BQ3_N1_BYT3[7:0]

BQ3_N1_BYT4[7:0]

BQ3_N2_BYT1[7:0]

BQ3_N2_BYT2[7:0]

BQ3_N2_BYT3[7:0]

BQ3_N2_BYT4[7:0]

BQ3_D1_BYT1[7:0]

BQ3_D1_BYT2[7:0]

BQ3_D1_BYT3[7:0]

BQ3_D1_BYT4[7:0]

BQ3_D2_BYT1[7:0]

BQ3_D2_BYT2[7:0]

BQ3_D2_BYT3[7:0]

BQ3_D2_BYT4[7:0]

BQ4_N0_BYT1[7:0]

BQ4_N0_BYT2[7:0]

BQ4_N0_BYT3[7:0]

BQ4_N0_BYT4[7:0]

BQ4_N1_BYT1[7:0]

BQ4_N1_BYT2[7:0]

BQ4_N1_BYT3[7:0]

BQ4_N1_BYT4[7:0]

BQ4_N2_BYT1[7:0]

BQ4_N2_BYT2[7:0]

BQ4_N2_BYT3[7:0]

BQ4_N2_BYT4[7:0]

BQ4_D1_BYT1[7:0]

BQ4_D1_BYT2[7:0]

BQ4_D1_BYT3[7:0]

BQ4_D1_BYT4[7:0]

BQ4_D2_BYT1[7:0]

BQ4_D2_BYT2[7:0]

BQ4_D2_BYT3[7:0]

BQ4_D2_BYT4[7:0]

BQ5_N0_BYT1[7:0]

BQ5_N0_BYT2[7:0]

BQ5_N0_BYT3[7:0]

BQ5_N0_BYT4[7:0]

BQ5_N1_BYT1[7:0]

BQ5_N1_BYT2[7:0]

BQ5_N1_BYT3[7:0]

BQ5_N1_BYT4[7:0]

BQ5_N2_BYT1[7:0]

BQ5_N2_BYT2[7:0]

BQ5_N2_BYT3[7:0]

BQ5_N2_BYT4[7:0]

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表7-97. Page 2 Programmable Coefficient Registers (continued)

Address

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

Acronym

Register Name

Reset Value

0x00

0x7F

0xFF

0x00

BQ5_D1_BYT1[7:0]

Programmable biquad 5, D1 coefficient byte[31:24]

Programmable biquad 5, D1 coefficient byte[23:16]

Programmable biquad 5, D1 coefficient byte[15:8]

Programmable biquad 5, D1 coefficient byte[7:0]

Programmable biquad 5, D2 coefficient byte[31:24]

Programmable biquad 5, D2 coefficient byte[23:16]

Programmable biquad 5, D2 coefficient byte[15:8]

Programmable biquad 5, D2 coefficient byte[7:0]

Programmable biquad 6, N0 coefficient byte[31:24]

Programmable biquad 6, N0 coefficient byte[23:16]

Programmable biquad 6, N0 coefficient byte[15:8]

Programmable biquad 6, N0 coefficient byte[7:0]

Programmable biquad 6, N1 coefficient byte[31:24]

Programmable biquad 6, N1 coefficient byte[23:16]

Programmable biquad 6, N1 coefficient byte[15:8]

Programmable biquad 6, N1 coefficient byte[7:0]

Programmable biquad 6, N2 coefficient byte[31:24]

Programmable biquad 6, N2 coefficient byte[23:16]

Programmable biquad 6, N2 coefficient byte[15:8]

Programmable biquad 6, N2 coefficient byte[7:0]

Programmable biquad 6, D1 coefficient byte[31:24]

Programmable biquad 6, D1 coefficient byte[23:16]

Programmable biquad 6, D1 coefficient byte[15:8]

Programmable biquad 6, D1 coefficient byte[7:0]

Programmable biquad 6, D2 coefficient byte[31:24]

Programmable biquad 6, D2 coefficient byte[23:16]

Programmable biquad 6, D2 coefficient byte[15:8]

Programmable biquad 6, D2 coefficient byte[7:0]

BQ5_D1_BYT2[7:0]

BQ5_D1_BYT3[7:0]

BQ5_D1_BYT4[7:0]

BQ5_D2_BYT1[7:0]

BQ5_D2_BYT2[7:0]

BQ5_D2_BYT3[7:0]

BQ5_D2_BYT4[7:0]

BQ6_N0_BYT1[7:0]

BQ6_N0_BYT2[7:0]

BQ6_N0_BYT3[7:0]

BQ6_N0_BYT4[7:0]

BQ6_N1_BYT1[7:0]

BQ6_N1_BYT2[7:0]

BQ6_N1_BYT3[7:0]

BQ6_N1_BYT4[7:0]

BQ6_N2_BYT1[7:0]

BQ6_N2_BYT2[7:0]

BQ6_N2_BYT3[7:0]

BQ6_N2_BYT4[7:0]

BQ6_D1_BYT1[7:0]

BQ6_D1_BYT2[7:0]

BQ6_D1_BYT3[7:0]

BQ6_D1_BYT4[7:0]

BQ6_D2_BYT1[7:0]

BQ6_D2_BYT2[7:0]

BQ6_D2_BYT3[7:0]

BQ6_D2_BYT4[7:0]

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7.6.3.2 Programmable Coefficient Registers: Page 3

This register page (shown in 表 7-98) consists of the programmable coefficients for the biquad 7 to biquad 12

filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also

supports (by default) auto-incremented pages for the I²C writes and reads. After a transaction of register address

0x7F, the device auto increments to the next page at register 0x08 to transact the next coefficient value.

表7-98. Page 3 Programmable Coefficient Registers

ADDR

0x00

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

REGISTER

RESET

0x00

0x7F

0xFF

0x00

0x7F

0xFF

0x00

0x7F

0xFF

DESCRIPTION

PAGE[7:0]

Device page register

BQ7_N0_BYT1[7:0]

BQ7_N0_BYT2[7:0]

BQ7_N0_BYT3[7:0]

BQ7_N0_BYT4[7:0]

BQ7_N1_BYT1[7:0]

BQ7_N1_BYT2[7:0]

BQ7_N1_BYT3[7:0]

BQ7_N1_BYT4[7:0]

BQ7_N2_BYT1[7:0]

BQ7_N2_BYT2[7:0]

BQ7_N2_BYT3[7:0]

BQ7_N2_BYT4[7:0]

BQ7_D1_BYT1[7:0]

BQ7_D1_BYT2[7:0]

BQ7_D1_BYT3[7:0]

BQ7_D1_BYT4[7:0]

BQ7_D2_BYT1[7:0]

BQ7_D2_BYT2[7:0]

BQ7_D2_BYT3[7:0]

BQ7_D2_BYT4[7:0]

BQ8_N0_BYT1[7:0]

BQ8_N0_BYT2[7:0]

BQ8_N0_BYT3[7:0]

BQ8_N0_BYT4[7:0]

BQ8_N1_BYT1[7:0]

BQ8_N1_BYT2[7:0]

BQ8_N1_BYT3[7:0]

BQ8_N1_BYT4[7:0]

BQ8_N2_BYT1[7:0]

BQ8_N2_BYT2[7:0]

BQ8_N2_BYT3[7:0]

BQ8_N2_BYT4[7:0]

BQ8_D1_BYT1[7:0]

BQ8_D1_BYT2[7:0]

BQ8_D1_BYT3[7:0]

BQ8_D1_BYT4[7:0]

BQ8_D2_BYT1[7:0]

BQ8_D2_BYT2[7:0]

BQ8_D2_BYT3[7:0]

BQ8_D2_BYT4[7:0]

BQ9_N0_BYT1[7:0]

BQ9_N0_BYT2[7:0]

BQ9_N0_BYT3[7:0]

Programmable biquad 7, N0 coefficient byte[31:24]

Programmable biquad 7, N0 coefficient byte[23:16]

Programmable biquad 7, N0 coefficient byte[15:8]

Programmable biquad 7, N0 coefficient byte[7:0]

Programmable biquad 7, N1 coefficient byte[31:24]

Programmable biquad 7, N1 coefficient byte[23:16]

Programmable biquad 7, N1 coefficient byte[15:8]

Programmable biquad 7, N1 coefficient byte[7:0]

Programmable biquad 7, N2 coefficient byte[31:24]

Programmable biquad 7, N2 coefficient byte[23:16]

Programmable biquad 7, N2 coefficient byte[15:8]

Programmable biquad 7, N2 coefficient byte[7:0]

Programmable biquad 7, D1 coefficient byte[31:24]

Programmable biquad 7, D1 coefficient byte[23:16]

Programmable biquad 7, D1 coefficient byte[15:8]

Programmable biquad 7, D1 coefficient byte[7:0]

Programmable biquad 7, D2 coefficient byte[31:24]

Programmable biquad 7, D2 coefficient byte[23:16]

Programmable biquad 7, D2 coefficient byte[15:8]

Programmable biquad 7, D2 coefficient byte[7:0]

Programmable biquad 8, N0 coefficient byte[31:24]

Programmable biquad 8, N0 coefficient byte[23:16]

Programmable biquad 8, N0 coefficient byte[15:8]

Programmable biquad 8, N0 coefficient byte[7:0]

Programmable biquad 8, N1 coefficient byte[31:24]

Programmable biquad 8, N1 coefficient byte[23:16]

Programmable biquad 8, N1 coefficient byte[15:8]

Programmable biquad 8, N1 coefficient byte[7:0]

Programmable biquad 8, N2 coefficient byte[31:24]

Programmable biquad 8, N2 coefficient byte[23:16]

Programmable biquad 8, N2 coefficient byte[15:8]

Programmable biquad 8, N2 coefficient byte[7:0]

Programmable biquad 8, D1 coefficient byte[31:24]

Programmable biquad 8, D1 coefficient byte[23:16]

Programmable biquad 8, D1 coefficient byte[15:8]

Programmable biquad 8, D1 coefficient byte[7:0]

Programmable biquad 8, D2 coefficient byte[31:24]

Programmable biquad 8, D2 coefficient byte[23:16]

Programmable biquad 8, D2 coefficient byte[15:8]

Programmable biquad 8, D2 coefficient byte[7:0]

Programmable biquad 9, N0 coefficient byte[31:24]

Programmable biquad 9, N0 coefficient byte[23:16]

Programmable biquad 9, N0 coefficient byte[15:8]

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表7-98. Page 3 Programmable Coefficient Registers (continued)

ADDR

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

REGISTER

RESET

0xFF

0x00

0x7F

0xFF

0x00

0x7F

0xFF

0x00

DESCRIPTION

BQ9_N0_BYT4[7:0]

Programmable biquad 9, N0 coefficient byte[7:0]

Programmable biquad 9, N1 coefficient byte[31:24]

Programmable biquad 9, N1 coefficient byte[23:16]

Programmable biquad 9, N1 coefficient byte[15:8]

Programmable biquad 9, N1 coefficient byte[7:0]

Programmable biquad 9, N2 coefficient byte[31:24]

Programmable biquad 9, N2 coefficient byte[23:16]

Programmable biquad 9, N2 coefficient byte[15:8]

Programmable biquad 9, N2 coefficient byte[7:0]

Programmable biquad 9, D1 coefficient byte[31:24]

Programmable biquad 9, D1 coefficient byte[23:16]

Programmable biquad 9, D1 coefficient byte[15:8]

Programmable biquad 9, D1 coefficient byte[7:0]

Programmable biquad 9, D2 coefficient byte[31:24]

Programmable biquad 9, D2 coefficient byte[23:16]

Programmable biquad 9, D2 coefficient byte[15:8]

Programmable biquad 9, D2 coefficient byte[7:0]

Programmable biquad 10, N0 coefficient byte[31:24]

Programmable biquad 10, N0 coefficient byte[23:16]

Programmable biquad 10, N0 coefficient byte[15:8]

Programmable biquad 10, N0 coefficient byte[7:0]

Programmable biquad 10, N1 coefficient byte[31:24]

Programmable biquad 10, N1 coefficient byte[23:16]

Programmable biquad 10, N1 coefficient byte[15:8]

Programmable biquad 10, N1 coefficient byte[7:0]

Programmable biquad 10, N2 coefficient byte[31:24]

Programmable biquad 10, N2 coefficient byte[23:16]

Programmable biquad 10, N2 coefficient byte[15:8]

Programmable biquad 10, N2 coefficient byte[7:0]

Programmable biquad 10, D1 coefficient byte[31:24]

Programmable biquad 10, D1 coefficient byte[23:16]

Programmable biquad 10, D1 coefficient byte[15:8]

Programmable biquad 10, D1 coefficient byte[7:0]

Programmable biquad 10, D2 coefficient byte[31:24]

Programmable biquad 10, D2 coefficient byte[23:16]

Programmable biquad 10, D2 coefficient byte[15:8]

Programmable biquad 10, D2 coefficient byte[7:0]

Programmable biquad 11, N0 coefficient byte[31:24]

Programmable biquad 11, N0 coefficient byte[23:16]

Programmable biquad 11, N0 coefficient byte[15:8]

Programmable biquad 11, N0 coefficient byte[7:0]

Programmable biquad 11, N1 coefficient byte[31:24]

Programmable biquad 11, N1 coefficient byte[23:16]

Programmable biquad 11, N1 coefficient byte[15:8]

Programmable biquad 11, N1 coefficient byte[7:0]

Programmable biquad 11, N2 coefficient byte[31:24]

Programmable biquad 11, N2 coefficient byte[23:16]

Programmable biquad 11, N2 coefficient byte[15:8]

Programmable biquad 11, N2 coefficient byte[7:0]

Programmable biquad 11, D1 coefficient byte[31:24]

BQ9_N1_BYT1[7:0]

BQ9_N1_BYT2[7:0]

BQ9_N1_BYT3[7:0]

BQ9_N1_BYT4[7:0]

BQ9_N2_BYT1[7:0]

BQ9_N2_BYT2[7:0]

BQ9_N2_BYT3[7:0]

BQ9_N2_BYT4[7:0]

BQ9_D1_BYT1[7:0]

BQ9_D1_BYT2[7:0]

BQ9_D1_BYT3[7:0]

BQ9_D1_BYT4[7:0]

BQ9_D2_BYT1[7:0]

BQ9_D2_BYT2[7:0]

BQ9_D2_BYT3[7:0]

BQ9_D2_BYT4[7:0]

BQ10_N0_BYT1[7:0]

BQ10_N0_BYT2[7:0]

BQ10_N0_BYT3[7:0]

BQ10_N0_BYT4[7:0]

BQ10_N1_BYT1[7:0]

BQ10_N1_BYT2[7:0]

BQ10_N1_BYT3[7:0]

BQ10_N1_BYT4[7:0]

BQ10_N2_BYT1[7:0]

BQ10_N2_BYT2[7:0]

BQ10_N2_BYT3[7:0]

BQ10_N2_BYT4[7:0]

BQ10_D1_BYT1[7:0]

BQ10_D1_BYT2[7:0]

BQ10_D1_BYT3[7:0]

BQ10_D1_BYT4[7:0]

BQ10_D2_BYT1[7:0]

BQ10_D2_BYT2[7:0]

BQ10_D2_BYT3[7:0]

BQ10_D2_BYT4[7:0]

BQ11_N0_BYT1[7:0]

BQ11_N0_BYT2[7:0]

BQ11_N0_BYT3[7:0]

BQ11_N0_BYT4[7:0]

BQ11_N1_BYT1[7:0]

BQ11_N1_BYT2[7:0]

BQ11_N1_BYT3[7:0]

BQ11_N1_BYT4[7:0]

BQ11_N2_BYT1[7:0]

BQ11_N2_BYT2[7:0]

BQ11_N2_BYT3[7:0]

BQ11_N2_BYT4[7:0]

BQ11_D1_BYT1[7:0]

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表7-98. Page 3 Programmable Coefficient Registers (continued)

ADDR

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

REGISTER

RESET

0x00

0x7F

0xFF

0x00

DESCRIPTION

BQ11_D1_BYT2[7:0]

Programmable biquad 11, D1 coefficient byte[23:16]

Programmable biquad 11, D1 coefficient byte[15:8]

Programmable biquad 11, D1 coefficient byte[7:0]

Programmable biquad 11, D2 coefficient byte[31:24]

Programmable biquad 11, D2 coefficient byte[23:16]

Programmable biquad 11, D2 coefficient byte[15:8]

Programmable biquad 11, D2 coefficient byte[7:0]

Programmable biquad 12, N0 coefficient byte[31:24]

Programmable biquad 12, N0 coefficient byte[23:16]

Programmable biquad 12, N0 coefficient byte[15:8]

Programmable biquad 12, N0 coefficient byte[7:0]

Programmable biquad 12, N1 coefficient byte[31:24]

Programmable biquad 12, N1 coefficient byte[23:16]

Programmable biquad 12, N1 coefficient byte[15:8]

Programmable biquad 12, N1 coefficient byte[7:0]

Programmable biquad 12, N2 coefficient byte[31:24]

Programmable biquad 12, N2 coefficient byte[23:16]

Programmable biquad 12, N2 coefficient byte[15:8]

Programmable biquad 12, N2 coefficient byte[7:0]

Programmable biquad 12, D1 coefficient byte[31:24]

Programmable biquad 12, D1 coefficient byte[23:16]

Programmable biquad 12, D1 coefficient byte[15:8]

Programmable biquad 12, D1 coefficient byte[7:0]

Programmable biquad 12, D2 coefficient byte[31:24]

Programmable biquad 12, D2 coefficient byte[23:16]

Programmable biquad 12, D2 coefficient byte[15:8]

Programmable biquad 12, D2 coefficient byte[7:0]

BQ11_D1_BYT3[7:0]

BQ11_D1_BYT4[7:0]

BQ11_D2_BYT1[7:0]

BQ11_D2_BYT2[7:0]

BQ11_D2_BYT3[7:0]

BQ11_D2_BYT4[7:0]

BQ12_N0_BYT1[7:0]

BQ12_N0_BYT2[7:0]

BQ12_N0_BYT3[7:0]

BQ12_N0_BYT4[7:0]

BQ12_N1_BYT1[7:0]

BQ12_N1_BYT2[7:0]

BQ12_N1_BYT3[7:0]

BQ12_N1_BYT4[7:0]

BQ12_N2_BYT1[7:0]

BQ12_N2_BYT2[7:0]

BQ12_N2_BYT3[7:0]

BQ12_N2_BYT4[7:0]

BQ12_D1_BYT1[7:0]

BQ12_D1_BYT2[7:0]

BQ12_D1_BYT3[7:0]

BQ12_D1_BYT4[7:0]

BQ12_D2_BYT1[7:0]

BQ12_D2_BYT2[7:0]

BQ12_D2_BYT3[7:0]

BQ12_D2_BYT4[7:0]

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7.6.3.3 Programmable Coefficient Registers: Page 4

This register page (shown in 表 7-99) consists of the programmable coefficients for mixer 1 to mixer 4 and the

first-order IIR filter.

hex2dec (value) / 2³¹

(4)

表7-99. Page 4 Programmable Coefficient Registers

ADDR

REGISTER

RESET

0x00

0x7F

0xFF

0x00

0x7F

0xFF

0x00

0x7F

0xFF

DESCRIPTION

0x00

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

PAGE[7:0]

Device page register

MIX1_CH1_BYT1[7:0]

MIX1_CH1_BYT2[7:0]

MIX1_CH1_BYT3[7:0]

MIX1_CH1_BYT4[7:0]

MIX1_CH2_BYT1[7:0]

MIX1_CH2_BYT2[7:0]

MIX1_CH2_BYT3[7:0]

MIX1_CH2_BYT4[7:0]

MIX1_CH3_BYT1[7:0]

MIX1_CH3_BYT2[7:0]

MIX1_CH3_BYT3[7:0]

MIX1_CH3_BYT4[7:0]

MIX1_CH4_BYT1[7:0]

MIX1_CH4_BYT2[7:0]

MIX1_CH4_BYT3[7:0]

MIX1_CH4_BYT4[7:0]

MIX2_CH1_BYT1[7:0]

MIX2_CH1_BYT2[7:0]

MIX2_CH1_BYT3[7:0]

MIX2_CH1_BYT4[7:0]

MIX2_CH2_BYT1[7:0]

MIX2_CH2_BYT2[7:0]

MIX2_CH2_BYT3[7:0]

MIX2_CH2_BYT4[7:0]

MIX2_CH3_BYT1[7:0]

MIX2_CH3_BYT2[7:0]

MIX2_CH3_BYT3[7:0]

MIX2_CH3_BYT4[7:0]

MIX2_CH4_BYT1[7:0]

MIX2_CH4_BYT2[7:0]

MIX2_CH4_BYT3[7:0]

MIX2_CH4_BYT4[7:0]

MIX3_CH1_BYT1[7:0]

MIX3_CH1_BYT2[7:0]

MIX3_CH1_BYT3[7:0]

MIX3_CH1_BYT4[7:0]

MIX3_CH2_BYT1[7:0]

MIX3_CH2_BYT2[7:0]

MIX3_CH2_BYT3[7:0]

MIX3_CH2_BYT4[7:0]

MIX3_CH3_BYT1[7:0]

MIX3_CH3_BYT2[7:0]

MIX3_CH3_BYT3[7:0]

Digital mixer 1, channel 1 coefficient byte[31:24]

Digital mixer 1, channel 1 coefficient byte[23:16]

Digital mixer 1, channel 1 coefficient byte[15:8]

Digital mixer 1, channel 1 coefficient byte[7:0]

Digital mixer 1, channel 2 coefficient byte[31:24]

Digital mixer 1, channel 2 coefficient byte[23:16]

Digital mixer 1, channel 2 coefficient byte[15:8]

Digital mixer 1, channel 2 coefficient byte[7:0]

Digital mixer 1, channel 3 coefficient byte[31:24]

Digital mixer 1, channel 3 coefficient byte[23:16]

Digital mixer 1, channel 3 coefficient byte[15:8]

Digital mixer 1, channel 3 coefficient byte[7:0]

Digital mixer 1, channel 4 coefficient byte[31:24]

Digital mixer 1, channel 4 coefficient byte[23:16]

Digital mixer 1, channel 4 coefficient byte[15:8]

Digital mixer 1, channel 4 coefficient byte[7:0]

Digital mixer 2, channel 1 coefficient byte[31:24]

Digital mixer 2, channel 1 coefficient byte[23:16]

Digital mixer 2, channel 1 coefficient byte[15:8]

Digital mixer 2, channel 1 coefficient byte[7:0]

Digital mixer 2, channel 2 coefficient byte[31:24]

Digital mixer 2, channel 2 coefficient byte[23:16]

Digital mixer 2, channel 2 coefficient byte[15:8]

Digital mixer 2, channel 2 coefficient byte[7:0]

Digital mixer 2, channel 3 coefficient byte[31:24]

Digital mixer 2, channel 3 coefficient byte[23:16]

Digital mixer 2, channel 3 coefficient byte[15:8]

Digital mixer 2, channel 3 coefficient byte[7:0]

Digital mixer 2, channel 4 coefficient byte[31:24]

Digital mixer 2, channel 4 coefficient byte[23:16]

Digital mixer 2, channel 4 coefficient byte[15:8]

Digital mixer 2, channel 4 coefficient byte[7:0]

Digital mixer 3, channel 1 coefficient byte[31:24]

Digital mixer 3, channel 1 coefficient byte[23:16]

Digital mixer 3, channel 1 coefficient byte[15:8]

Digital mixer 3, channel 1 coefficient byte[7:0]

Digital mixer 3, channel 2 coefficient byte[31:24]

Digital mixer 3, channel 2 coefficient byte[23:16]

Digital mixer 3, channel 2 coefficient byte[15:8]

Digital mixer 3, channel 2 coefficient byte[7:0]

Digital mixer 3, channel 3 coefficient byte[31:24]

Digital mixer 3, channel 3 coefficient byte[23:16]

Digital mixer 3, channel 3 coefficient byte[15:8]

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表7-99. Page 4 Programmable Coefficient Registers (continued)

ADDR

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

REGISTER

MIX3_CH3_BYT4[7:0]

MIX3_CH4_BYT1[7:0]

MIX3_CH4_BYT2[7:0]

MIX3_CH4_BYT3[7:0]

MIX3_CH4_BYT4[7:0]

MIX4_CH1_BYT1[7:0]

MIX4_CH1_BYT2[7:0]

MIX4_CH1_BYT3[7:0]

MIX4_CH1_BYT4[7:0]

MIX4_CH2_BYT1[7:0]

MIX4_CH2_BYT2[7:0]

MIX4_CH2_BYT3[7:0]

MIX4_CH2_BYT4[7:0]

MIX4_CH3_BYT1[7:0]

MIX4_CH3_BYT2[7:0]

MIX4_CH3_BYT3[7:0]

MIX4_CH3_BYT4[7:0]

MIX4_CH4_BYT1[7:0]

MIX4_CH4_BYT2[7:0]

MIX4_CH4_BYT3[7:0]

MIX4_CH4_BYT4[7:0]

IIR_N0_BYT1[7:0]

RESET

0xFF

0x00

0x7F

0xFF

0x7F

0xFF

0x00

DESCRIPTION

Digital mixer 3, channel 3 coefficient byte[7:0]

Digital mixer 3, channel 4 coefficient byte[31:24]

Digital mixer 3, channel 4 coefficient byte[23:16]

Digital mixer 3, channel 4 coefficient byte[15:8]

Digital mixer 3, channel 4 coefficient byte[7:0]

Digital mixer 4, channel 1 coefficient byte[31:24]

Digital mixer 4, channel 1 coefficient byte[23:16]

Digital mixer 4, channel 1 coefficient byte[15:8]

Digital mixer 4, channel 1 coefficient byte[7:0]

Digital mixer 4, channel 2 coefficient byte[31:24]

Digital mixer 4, channel 2 coefficient byte[23:16]

Digital mixer 4, channel 2 coefficient byte[15:8]

Digital mixer 4, channel 2 coefficient byte[7:0]

Digital mixer 4, channel 3 coefficient byte[31:24]

Digital mixer 4, channel 3 coefficient byte[23:16]

Digital mixer 4, channel 3 coefficient byte[15:8]

Digital mixer 4, channel 3 coefficient byte[7:0]

Digital mixer 4, channel 4 coefficient byte[31:24]

Digital mixer 4, channel 4 coefficient byte[23:16]

Digital mixer 4, channel 4 coefficient byte[15:8]

Digital mixer 4, channel 4 coefficient byte[7:0]

Programmable first-order IIR, N0 coefficient byte[31:24]

Programmable first-order IIR, N0 coefficient byte[23:16]

Programmable first-order IIR, N0 coefficient byte[15:8]

Programmable first-order IIR, N0 coefficient byte[7:0]

Programmable first-order IIR, N1 coefficient byte[31:24]

Programmable first-order IIR, N1 coefficient byte[23:16]

Programmable first-order IIR, N1 coefficient byte[15:8]

Programmable first-order IIR, N1 coefficient byte[7:0]

Programmable first-order IIR, D1 coefficient byte[31:24]

Programmable first-order IIR, D1 coefficient byte[23:16]

Programmable first-order IIR, D1 coefficient byte[15:8]

Programmable first-order IIR, D1 coefficient byte[7:0]

IIR_N0_BYT2[7:0]

IIR_N0_BYT3[7:0]

IIR_N0_BYT4[7:0]

IIR_N1_BYT1[7:0]

IIR_N1_BYT2[7:0]

IIR_N1_BYT3[7:0]

IIR_N1_BYT4[7:0]

IIR_D1_BYT1[7:0]

IIR_D1_BYT2[7:0]

IIR_D1_BYT3[7:0]

IIR_D1_BYT4[7:0]

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The PCMD3140-Q1 is a multichannel, pulse-density-modulation (PDM) input to time-division multiplexing (TDM)

or I²S audio output converter that supports output sample rates of up to 768 kHz. The device supports up to four

digital pulse density modulation (PDM) microphones for simultaneous recording applications.

Communication to the PCMD3140-Q1 for configuration of the control registers is supported using an I²C

interface. The device supports a highly flexible, audio serial interface (TDM, I²S, and LJ) to transmit audio data

seamlessly in the system across devices.

8.2 Typical Application

8.2.1 Four-Channel Digital PDM Microphone Recording

图 8-1 shows a typical configuration of the PCMD3140-Q1 for an application using four digital PDM MEMS

microphones with simultaneous recording operation using an I²C control interface and the TDM audio data slave

interface. If the MICBIAS output is not used in the system then the 1-µF capacitor for the MICBIAS pin is not

used.

10 μF

1 μF

VDD

(3.0 V to 3.6 V)

0.1 μF

1 μF

GND

10 μF

VDD

SEL

VSS

CLK

VDD

0.1 μF

GND

DREG

DMIC1

Rterm

0.1 μF

MICBIAS_GPI2

DOUT

GND

VDD

SEL

CLK

VDD

3.3 V

(3.0 V to 3.6 V)

OR

1.8 V

(1.65 V to 1.95 V)

DMIC2

0.1 μF

VSS

DOUT

Rterm

GND

10 μF

VDD

SEL

CLK

VDD

0.1 μF

DMIC3

PCMD3140-Q1

IN2P_GPI1

DOUT

IOVDD

VSS

GND

0.1 μF

VDD

SEL

CLK

IN2M_GPO1

VDD

0.1 μF

GND

Rterm

DMIC4

Thermal Pad

(VSS)

DOUT

VSS

Rterm

GND

IN1P

IN1M

R Ω

Host

Processor

图8-1. Four-Channel Digital PDM Microphone Recording Diagram

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8.2.1.1 Design Requirements

The supply decoupling capacitors used must be ceramic with low ESR. 表8-1 lists the design parameters for this

application.

表8-1. Design Parameters

KEY PARAMETER

SPECIFICATION

AVDD

3.3 V

AVDD supply current consumption

IOVDD

10 mA (PLL on, four-channel recording, f_S= 48 kHz, PDMCLKx = 64 × f_S)

1.8 V or 3.3 V

8.2.1.2 Detailed Design Procedure

This section describes the necessary steps to configure the PCMD3140-Q1 for this specific application. The

following steps provide a sequence of items that must be executed in the time between powering the device up

and reading data from the device or transitioning from one mode to another mode of operation.

1. Apply power to the device:

a. Power-up the IOVDD and AVDD power supplies

b. Wait for at least 1 ms to allow the device to initialize the internal registers initialization

c. The device now goes into sleep shutdown mode (low-power mode < 10 µA)

2. Transition from sleep mode to active mode whenever required for the recording operation:

a. Wake up the device by writing to P0_R2 to disable sleep mode

b. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence

c. Override the default configuration registers or programmable coefficients value as required (this step is

optional)

d. Configure channel 1 to channel 2 (CHx_INSRC) for the digital microphone as the input source for

recording

e. Configure GPO1 (GPO1_CFG) and GPIO1 (GPIO1_CFG) as the PDMCLK output

f. Configure GPIx (GPI1x_CFG) as PDMDINx

g. Enable all desired input channels by writing to P0_R115

h. Enable all desired audio serial interface output channels by writing to P0_R116

i. Power-up the PDM converter and PLL by writing to P0_R117

j. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

This specific step can be done at any point in the sequence after step a.

See the 节7.3.2 section for supported sample rates and the BCLK to FSYNC ratio.

k. The device recording data is now sent to the host processor using the TDM audio serial data bus

3. Transition from active mode to sleep mode (again) as required in the system for low-power operation:

a. Enter sleep mode by writing to P0_R2 to enable sleep mode

b. Wait at least 6 ms (when FSYNC = 48 kHz) for the volume to ramp down and for all blocks to power

down

c. Read P0_R119 to check the device shutdown and sleep mode status

d. If the device P0_R119_D7 status bit is 1'b1 then stop FSYNC and BCLK in the system

e. The device now goes into sleep mode (low-power mode < 10 µA) and retains all register values

4. Transition from sleep mode to active mode (again) as required for the recording operation:

a. Wake up the device by writing to P0_R2 to disable sleep mode

b. Wait at least 1 ms to allow the device to complete the internal wake-up sequence

c. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

d. The device recording data are now sent to the host processor using the TDM audio serial data bus

5. Repeat step 3 and step 4 as required for mode transitions and step 2 to step 4 for configuration changes.

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8.2.1.2.1 Example Device Register Configuration Script for EVM Setup

This section provides a typical EVM I²C register control script that shows how to set up the PCMD3140-Q1 in a

4-channel digital PDM microphone recording mode.

# Key: w 9C XX YY ==> write to I2C address 0x9C, to register 0xXX, data 0xYY

#

# ==> comment delimiter

# The following list gives an example sequence of items that must be executed in the time

# between powering the device up and reading data from the device. Note that there are

# other valid sequences depending on which features are used.

#

# See the PCMD3140EVM user guide for jumper settings and audio connections.

#

# PDM 8-channel : PDMDIN1 - Ch1 and Ch2, PDMDIN2 - Ch3 and Ch4,

#

PDMDIN3 - Ch5 and Ch6, PDMDIN4 - Ch7 and Ch8

# PDMCLKx = 2.8224 MHz (PDMCLKx/FSYNC = 64)

# FSYNC = 44.1 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)

################################################################

#

# Power up IOVDD and AVDD power supplies

# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.

# Wait for 1ms.

#

# Wake-up device by I2C write into P0_R2 using internal AREG

w 9C 02 81

#

# Configure CH2_INSRC as Digital PDM Input by I2C write into P0_R65

w 9C 41 40

#

# Configure MICBIAS_GPI2 as Digital PDM Input by I2C write into P0_R59

w 9C 3B 70

#

# Configure GPO1 as PDMCLK by I2C write into P0_R34

w 9C 22 41

#

# Configure GPI1 and GPI2 as PDMDIN1 and PDMDIN2 by I2C write into P0_R43

w 9C 2B 45

#

# Enable Input Ch-1 to Ch-4 by I2C write into P0_R115

w 9C 73 F0

#

# Enable ASI Output Ch-1 to Ch-4 slots by I2C write into P0_R116

w 9C 74 F0

#

# Power-up ADC and PLL by I2C write into P0_R117

w 9C 75 60

#

# Apply FSYNC = 44.1 kHz and BCLK = 11.2896 MHz and

# Start recording data by host on ASI bus with TDM protocol 32-bits channel wordlength

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8.2.1.3 Application Curves

Measurements are done on the EVM by feeding the device PDM digital input signal using audio precision. In the

system application, the device performance is expected to be limited by the single-bit PDM modulator digital

microphone output performance.

0

-20

-60

Channel-1

Channel-2

Channel-3

Channel-4

Channel-1

Channel-2

Channel-3

Channel-4

-70

-40

-80

-60

-80

-90

-100

-120

-140

-160

-180

-200

-100

-110

-120

-130

20 30 4050 70 100

200 300 500

1000 2000

5000 10000 20000

PCMD

-130

-115

-100

-85

-70

-55

-40

-25

-10 -1

Frequency (Hz)

Input Amplitude (dB)

PTCHMDD+

4th-order PDM modulator with PDMCLKx = 2.8224 MHz

图8-2. FFT With a –60-dBr Input

图8-3. THD+N vs Input Amplitude

8.3 What to Do and What Not to Do

In the VAD mode of operation, there are some limitations on interrupt generation when auto wake up is enabled.

For details about these limitations, see the Using the Voice Activity Detector (VAD) in the TLV320ADC5120 and

TLV320ADC6120 application report.

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9 Power Supply Recommendations

The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, only

initiate the I²C transactions after all supplies are stable to initialize the device.

For the supply power-up requirement, t₁and t₂must be at least 2 ms to allow the device to initialize the internal

registers. See the 节 7.4 section for details on how the device operates in various modes after the device power

supplies are settled to the recommended operating voltage levels. For the supply power-down requirement, t₃

and t₄must be at least 10 ms. This timing (as shown in 图 9-1) allows the device to ramp down the volume on

the record data, power down the analog and digital blocks, and put the device into shutdown mode. The device

can also be immediately put into shutdown mode by ramping down power supplies, but doing so causes an

abrupt shutdown.

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AVDD

t₁

t₃

IOVDD

I2C bus transaction for PCMD3140-Q1

t₄

t₂

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Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a

power-up event is at least 100 ms. For a supply ramp rate slower than 0.1 V/ms, the host device must apply a

software reset as the first transaction before configuring the device. Make sure that all digital input pins are at

valid input levels and not toggling during supply sequencing.

The PCMD3140-Q1 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG,

and an analog regulator, AREG. However, if the AVDD voltage is less than 1.98 V in the system, then short the

AREG and AVDD pins onboard and do not enable the internal AREG by keeping the AREG_SELECT bit to 1b'0

(default value) of P0_R2. If the AVDD supply used in the system is higher than 2.7 V, then the host device can

set AREG_SELECT to 1'b1 when exiting sleep mode to allow the device internal regulator to generate the AREG

supply.

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10 Layout

10.1 Layout Guidelines

Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in

the context of a specific PCB design. However, the following guidelines can optimize the device performance:

• Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, which is the area

directly under the device, to the ground planes. This connection helps dissipate heat from the device.

• The decoupling capacitors for the power supplies must be placed close to the device pins.

• The supply decoupling capacitors must be used ceramic type with low ESR.

• Avoid crossing digital and analog signals to prevent undesirable crosstalk.

• The device internal voltage references must be filtered using external capacitors. Place the filter capacitors

near the VREF pin for optimal performance.

• Directly tap the MICBIAS pin to avoid common impedance when routing the biasing or supply traces for

multiple microphones to avoid coupling across microphones.

• Directly short the VREF and MICBIAS external capacitors ground terminal to the AVSS pin without using any

vias for this connection trace.

• Place the MICBIAS capacitor (with low equivalent series resistance) close to the device with minimal trace

impedance.

• Use ground planes to provide the lowest impedance for power and signal current between the device and the

decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and

all device grounds must be connected directly to that area.

10.2 Layout Example

10:VSS

16:AVDD

17:AREG

9:IOVDD

8:FSYNC

7:BCLK

21:VSS

18:VREF

19:PDMDIN2_GPI2

20:VSS

6:SDOUT

Populate this capacitor if

PDMDIN2_GPI2 is used as MICBIAS

图10-1. Layout Example

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Multiple TLV320ADCx140 Devices With Shared TDM and I²C Bus application report

• Texas Instruments, Configuring and Operating TLV320ADCx120 as an Audio Bus Master application report

• Texas Instruments, TLV320ADCx140 Sampling Rates and Programmable Processing Blocks Supported

application report

• Texas Instruments, TLV320ADCx140 Programmable Biquad Filter Configuration and Applications application

report

• Texas Instruments, TLV320ADCx120 Power Consumption Matrix Across Various Usage Scenarios

application report

• Texas Instruments, Using the Voice Activity Detector (VAD) in the TLV320ADC5120 and TLV320ADC6120

application report

• Texas Instruments, ADCx120EVM-PDK Evaluation module user's guide

• Texas Instruments, PurePath^™Console Graphical Development Suite for Audio System Design and

Development

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

PurePath^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

WQFN - 0.8 mm max height

RTE0020A

PLASTIC QUAD FLATPACK- NO LEAD

3.1

2.9

A

B

PIN 1 INDEX AREA

3.1

2.9

C

0.8 MAX

SEATING PLANE

0.08

C

0.05

0.00

1.5

SQ

1.4 0.1

4X (SQ 0.2)

TYP

(0.1)

6

10

5

9

8X 0.4625

0.225

8X

4

0.125

0.1

11

C A B

0.05

C

SYMM

21

1.5

14

1

12X 0.5

0.3

16X

0.2

0.1

C A B

PIN1 ID

(OPTIONAL)

15

20

19

16

0.05

C

0.5

0.3

16X

SYMM

4225900/A 06/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RTE0020A

(2.825)

(2.8)

(SQ 1.4)

4X (0.575)

4X (0.175)

16X (0.6)

4X (0.575)

15

19

16

20

8X (0.4625)

4X (0.175)

14

1

16X (0.25)

12X (0.5)

(2.825)

(2.8)

SYMM

21

2X (0.45)

11

4

(R 0.05) TYP

(Ø 0.2) VIA

TYP

5

10

2X (0.45)

9

6

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4225900/A 06/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

.

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

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EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

RTE0020A

PLASTIC QUAD FLATPACK- NO LEAD

(2.825)

(2.8)

4X (0.575)

4X (0.175)

(SQ 1.3)

16X (0.6)

4X (0.575)

19

16

15

20

8X (0.4625)

16X (0.25)

4X (0.175)

14

21

1

(2.825)

(2.8)

SYMM

12X (0.5)

11

4

(R 0.05) TYP

METAL TYP

5

10

9

6

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

86% PRINTED COVERAGE BY AREA

SCALE: 20X

4225900/A 06/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

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PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

A

RTE0020A

3.1

2.9

B

PIN 1 INDEX AREA

3.1

2.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

1.5

SQ

1.4±0.1

4X (SQ 0.2)

TYP

(0.1)

6

10

5

9

8X 0.4625

0.225

0.125

0.1

8X

4

11

C

A B

0.05

C

SYMM

21

1.5

14

1

12X 0.5

0.3

0.2

0.1

16X

0.5

C A B

PIN1 ID

(OPTIONAL)

15

20

19

16

0.05

C

16X

SYMM

0.3

4225900/A 06/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

RTE0020A

PLASTIC QUAD FLATPACK- NO LEAD

(2.825)

(2.8)

(SQ 1.4)

4X (0.575)

4X (0.175)

16X (0.6)

4X (0.575)

15

19

16

20

8X (0.4625)

4X (0.175)

14

1

16X (0.25)

12X (0.5)

(2.825)

(2.8)

SYMM

21

2X (0.45)

11

4

(R 0.05) TYP

(Ø 0.2) VIA

TYP

5

10

2X (0.45)

9

6

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MAX

0.07 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225900/A 06/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

.

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

RTE0020A

PLASTIC QUAD FLATPACK- NO LEAD

(2.825)

(2.8)

4X (0.575)

4X (0.175)

(SQ 1.3)

16X (0.6)

4X (0.575)

19

16

15

20

8X (0.4625)

4X (0.175)

21

1

14

16X (0.25)

12X (0.5)

(2.825)

SYMM

(2.8)

11

4

(R 0.05) TYP

METAL TYP

5

10

9

6

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

86% PRINTED COVERAGE BY AREA

SCALE: 20X

4225900/A 06/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	PCMD3140-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类、127dB SNR、768kHz、四通道、PDM 输入到 TDM 或 I²S 输出转换器光电二极管转换器
文件：	总112页 (文件大小：5452K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCMD3140-Q1 [TI]

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