PCMD3180IRTWR [TI]
8 通道 PDM 输入至 TDM 或 I2S 输出转换器 | RTW | 24 | -40 to 125;
| 型号： | PCMD3180IRTWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 通道 PDM 输入至 TDM 或 I2S 输出转换器 | RTW | 24 | -40 to 125 光电二极管 转换器 |
| 文件： | 总113页 (文件大小：4107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCMD3180
SBASA14 –MAY 2020
PCMD3180 Octal-Channel, PDM Input to TDM or I2S Output Converter
1 Features
2 Applications
1
•
8-channel PDM microphones simultaneous
conversion
PDM input to TDM or I2S output converter
performance:
•
•
•
•
•
•
Video doorbell
Smart speakers
•
Building security gateway
IP network cameras
–
127-dB dynamic range (DR) with high
performance 5th order PDM input
GPS personal navigation device
Video conference systems
–
117-dB dynamic range (DR) with high
performance 4th order PDM input
3 Description
The PCMD3180 is
•
Channel summing mode, DR performance with
high performance 4th order PDM input:
a high-performance, pulse-
density-modulation (PDM) input to time-division
multiplexing (TDM) or I2S output converter that
supports simultaneous sampling of up to eight digital
channels for the PDM microphone input. The device
integrates programable digital volume control, a
microphone bias voltage, a phase-locked loop (PLL),
a programmable high-pass filter (HPF), biquad filters,
low-latency filter modes, and allows for output sample
rates up to 768 kHz. The device supports time-
division multiplexing (TDM), I2S, or left-justified (LJ)
audio formats, and can be controlled with either the
I2C or SPI interface. Additionally, the PCMD3180
supports master and slave mode selection for the
audio bus interface operation. These integrated high-
performance features, along with the ability to be
powered from a single-supply of 3.3 V or 1.8 V, make
the device an excellent choice for space-constrained
audio systems in far-field microphone recording
applications.
–
–
120-dB, 2-channel summing
123-dB, 4-channel summing
•
•
•
Programmable PDM clock output :
768 kHz to 6.144 MHz
Programmable output sample rate (fS) :
8 kHz to 768 kHz
Programmable channel settings:
–
–
–
–
–
Digital volume control: –100 dB to 27 dB
Gain calibration with 0.1-dB resolution
Phase calibration with 163-ns resolution
•
•
•
•
•
•
•
Microphone bias or supply voltage generation
Low-latency signal processing filter selection
Programmable HPF and biquad digital filters
I2C or SPI controls
Integrated high-performance audio PLL
Automatic clock divider setting configurations
Audio serial data interface:
The PCMD3180 is specified from –40°C to +125°C,
and is offered in a 24-pin WQFN package.
Device Information(1)
–
–
–
Format: TDM, I2S, or left-justified (LJ)
Word length: 16 bits, 20 bits, 24 bits, or 32 bits
Master or slave interface
PART NUMBER
PCMD3180
PACKAGE
BODY SIZE (NOM)
4.00 mm × 4.00 mm with
0.5-mm pitch
WQFN (24)
•
•
•
Single-supply operation: 3.3 V or 1.8 V
I/O-supply operation: 3.3 V or 1.8 V
Power consumption for 1.8-V supply:
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Block Diagram
–
–
2.9 mW/channel at 16-kHz sample rate
2.5 mW/channel at 48-kHz sample rate
SHDNZ
PDMDIN1_GPI1
PLL and Clock Generation
GPIO1
PDMCLK1_GPO1
PDMDIN2_GPI2
PDMCLK2_GPO2
FSYNC
BCLK
8-Channel
Digital PDM
Microphones
Simultaneous
Conversion
Programmable
Digital Filters,
Biquads
Audio Serial
Interface
SDOUT
PDMDIN3_GPI3
PDMCLK3_GPO3
(TDM, I2S, LJ)
SDA_SSZ
PDMDIN4_GPI4
PDMCLK4_GPO4
MICBIAS
SCL_MOSI
MICBIAS, Regulators and
Voltage Reference
I2C or SPI Control
Interface
ADDR0_SCLK
ADDR1_MISO
VREF
Thermal Pad
(VSS)
AVDD
DREG
AVSS
IOVDD
AREG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCMD3180
SBASA14 –MAY 2020
www.ti.com
Table of Contents
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 49
7.5 Programming........................................................... 50
7.6 Register Maps......................................................... 54
Application and Implementation ........................ 98
8.1 Application Information............................................ 98
8.2 Typical Applications ................................................ 98
8.3 What to Do and What Not to Do ........................... 103
Power Supply Recommendations.................... 104
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements: I2C Interface.......................... 9
6.7 Switching Characteristics: I2C Interface.................... 9
6.8 Timing Requirements: SPI Interface....................... 10
6.9 Switching Characteristics: SPI Interface................. 10
6.10 Timing Requirements: TDM, I2S or LJ Interface... 10
8
9
10 Layout................................................................. 105
10.1 Layout Guidelines ............................................... 105
10.2 Layout Example .................................................. 105
11 Device and Documentation Support ............... 106
11.1 Documentation Support ...................................... 106
6.11 Switching Characteristics: TDM, I2S or LJ
11.2 Receiving Notification of Documentation
Updates.................................................................. 106
Interface ................................................................... 10
11.3 Support Resources ............................................. 106
11.4 Trademarks......................................................... 106
11.5 Electrostatic Discharge Caution.......................... 106
11.6 Glossary.............................................................. 106
6.12 Timing Requirements: PDM Digital Microphone
Interface ................................................................... 11
6.13 Switching Characteristics: PDM Digial Microphone
Interface ................................................................... 11
6.14 Typical Characteristics.......................................... 13
12 Mechanical, Packaging, and Orderable
7
Detailed Description ............................................ 15
Information ......................................................... 106
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
May 2020
*
Initial release.
2
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5 Pin Configuration and Functions
RTW Package
24-Pin WQFN With Exposed Thermal Pad
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
AVDD
Analog supply
Analog supply
Analog power (1.8 V or 3.3 V, nominal)
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) or external
analog power (1.8 V, nominal). Connect a 10 µF and 0.1 µF low ESR capacitors in
parallel to analog ground (AVSS)
2
AREG
3
4
5
VREF
AVSS
Analog
Analog supply
Analog
Analog reference voltage filter output. Connect a 1 µF to analog ground (AVSS)
Analog ground. Short this pin directly to the board ground plane.
MICBIAS output. Connect a 1 µF to analog ground (AVSS)
MICBIAS
PDM microphone data input 1 or general-purpose digital input 1 (multipurpose functions
such as digital microphone data, PLL input clock source, and so forth)
6
PDMDIN1_GPI1
PDMCLK1_GPO1
PDMDIN2_GPI2
PDMCLK2_GPO2
PDMDIN3_GPI3
PDMCLK3_GPO3
PDMDIN4_GPI4
Digital input
Digital output
Digital input
Digital output
Digital input
Digital output
Digital input
PDM microphone clock output 1 or general-purpose digital output 1 (multipurpose
functions such as digital microphone clock, interrupt, and so forth)
7
PDM microphone data input 2 or general-purpose digital input 2 (multipurpose functions
such as digital microphone data, PLL input clock source, and so forth)
8
PDM microphone clock output 2 or general-purpose digital output 2 (multipurpose
functions such as digital microphone clock, interrupt, and so forth)
9
PDM microphone data input 3 or general-purpose digital input 3 (multipurpose functions
such as digital microphone data, PLL input clock source, and so forth)
10
11
12
PDM microphone clock output 3 or general-purpose digital output 3 (multipurpose
functions such as digital microphone clock, interrupt, and so forth)
PDM microphone data input 4 or general-purpose digital input 4 (multipurpose functions
such as digital microphone data, PLL input clock source, and so forth)
PDM microphone clock output 4 or general-purpose digital output 4 (multipurpose
functions such as digital microphone clock, interrupt, and so forth)
13
14
15
PDMCLK4_GPO4
SHDNZ
Digital output
Digital input
Digital I/O
Device hardware shutdown and reset (active low)
For I2C operation: I2C slave address A1 pin
For SPI operation: SPI slave output pin
ADDR1_MISO
For I2C operation: I2C slave address A0 pin
For SPI operation : SPI serial bit clock
16
17
ADDR0_SCLK
SCL_MOSI
Digital input
Digital input
For I2C operation: clock pin for I2C control bus
For SPI operation: SPI slave input pin
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
SDA_SSZ
IOVDD
For I2C operation: data pin for I2C control bus
For SPI operation: SPI slave-select pin
18
19
20
Digital I/O
Digital supply
Digital I/O
Digital I/O power supply (1.8 V or 3.3 V, nominal)
General-purpose digital input/output 1 (multipurpose functions such as digital
microphones clock or data, PLL input clock source, interrupt, and so forth)
GPIO1
21
22
23
SDOUT
BCLK
Digital output
Digital I/O
Audio serial data interface bus output
Audio serial data interface bus bit clock
FSYNC
Digital I/O
Audio serial data interface bus frame synchronization signal
Digital regulator output voltage for digital core supply (1.5 V, nominal). Connect a 10 µF
and 0.1 µF low ESR capacitors in parallel to device ground (VSS)
24
DREG
Digital supply
Ground supply
Thermal pad shorted to internal device ground. Short the thermal pad directly to the
board ground plane.
Thermal Pad
Thermal Pad (VSS)
4
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6 Specifications
6.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
3.9
UNIT
V
AVDD to AVSS
Supply voltage
AREG to AVSS
2.0
IOVDD to VSS (thermal pad)
AVSS to VSS (thermal pad)
3.9
Ground voltage differences
0.3
V
Digital input except PDMDINx_GPIx pins voltage to
VSS (thermal pad)
–0.3
–0.3
IOVDD + 0.3
AVDD + 0.3
Digital input voltage
Temperature
V
Digital input PDMDINx_GPIx pins voltage to VSS
(thermal pad)
Operating ambient, TA
Junction, TJ
–40
–40
–65
125
150
150
°C
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER
Analog supply voltage AVDD to AVSS (AREG is generated using onchip regulator) -
AVDD 3.3-V operation
3.0
1.7
3.3
1.8
3.6
1.9
AVDD,
V
V
AREG(1)
Analog supply voltage AVDD and AREG to AVSS (AREG internal regulator is
shutdown) - AVDD 1.8-V operation
IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation
IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation
3.0
3.3
1.8
3.6
IOVDD
1.65
1.95
INPUTS
Digital input except PDMDINx_GPIx pins voltage to VSS (thermal pad)
Digital input PDMDINx_GPIx pins voltage to VSS (thermal pad)
0
0
IOVDD
AVDD
V
V
TEMPERATURE
TA
Operating ambient temperature
–40
125
°C
OTHERS
GPIOx or GPIx (used as MCLK input) clock frequency
36.864
400
MHz
pF
SCL and SDA bus capacitance for I2C interface supports standard-mode and fast-
mode
Cb
CL
SCL and SDA bus capacitance for I2C interface supports fast-mode plus
Digital output load capacitance
550
50
20
pF
(1) AVSS and VSS (thermal pad): all ground pins must be tied together and must not differ in voltage by more than 0.2 V.
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6.4 Thermal Information
PCMD3180
RTW (WQFN)
24 PINS
32.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
25.0
11.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
11.9
RθJC(bot)
2.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, PDMCLKx = 64 × fS, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode, PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PERFORMANCE FOR PDM INPUT CONVERSION
No signal, input generated using 5th order PDM
modulator
128
118
127
117
Signal-to-noise ratio, A-
weighted(1)(2)(3)
SNR
DR
dB
No signal, input generated using 4th order PDM
modulator
–60-dB full-scale signal input, input generated using 5th
order PDM modulator
Dynamic range, A-
weighted(2)(3)
dB
–60-dB full-scale signal input, input generated using 4th
order PDM modulator
OTHER PARAMETERS
Digital volume control
Programmable 0.5-dB steps
–100
27
dB
range
PDMCLKx output rate
Output data sample rate
Programmable
Programmable
0.7056
7.35
6.144
768
MHz
kHz
Output data sample word
length
Programmable
16
32
Bits
Hz
Digital high-pass filter
cutoff frequency
First-order IIR filter with programmable coefficients, –3-
dB point (default setting)
12
MICBIAS programmed to VREF and VREF programmed
to either 2.75 V, 2.5 V, or 1.375 V
VREF
MICBIAS voltage
V
Bypass to AVDD with 20-mA load
AVDD – 0.2
DIGITAL I/O
All digital pins except PDMDINx_GPIx, SDA and SCL,
IOVDD 1.8-V operation
0.35 ×
IOVDD
–0.3
–0.3
Low-level digital input logic
voltage threshold
VIL
V
V
V
All digital pins except PDMDINx_GPIx, SDA and SCL,
IOVDD 3.3-V operation
0.8
All digital pins except PDMDINx_GPIx, SDA and SCL,
IOVDD 1.8-V operation
0.65 ×
IOVDD
IOVDD +
0.3
High-level digital input logic
voltage threshold
VIH
All digital pins except PDMDINx_GPIx, SDA and SCL,
IOVDD 3.3-V operation
IOVDD +
0.3
2
All digital pins except PDMCLKx_GPOx, SDA and SCL,
IOL = –2 mA, IOVDD 1.8-V operation
0.45
0.4
Low-level digital output
voltage
VOL
All digital pins except PDMCLKx_GPOx, SDA and SCL,
IOL = –2 mA, IOVDD 3.3-V operation
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with no signal, measured A-weighted over a 20-Hz to 20-
kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) The device performance parameters, SNR, DR and THD+N, are mainly limited by single-bit PDM modulator generated data output. The
THD+N peformance for single-bit PDM modulator output itself is generally not so good for signal above –10-dB full-scale. The datasheet
measured numbers are with using audio equipments consist of high performance PDM modulator output generator.
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Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, PDMCLKx = 64 × fS, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode, PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All digital pins except PDMCLKx_GPOx, SDA and SCL,
IOH = 2 mA, IOVDD 1.8-V operation
IOVDD –
0.45
High-level digital output
voltage
VOH
V
All digital pins except PDMCLKx_GPOx, SDA and SCL,
IOH = 2 mA, IOVDD 3.3-V operation
2.4
–0.5
Low-level digital input logic
voltage threshold
VIL(I2C)
SDA and SCL
0.3 x IOVDD
V
V
V
V
High-level digital input logic
voltage threshold
IOVDD +
0.5
VIH(I2C)
VOL1(I2C)
VOL2(I2C)
SDA and SCL
0.7 x IOVDD
Low-level digital output
voltage
SDA, IOL(I2C) = –3 mA, IOVDD > 2 V
SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V
0.4
Low-level digital output
voltage
0.2 x IOVDD
SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode
SDA, VOL(I2C) = 0.4 V, fast-mode plus
3
Low-level digital output
current
IOL(I2C)
mA
20
0.25 ×
IOVDD
SHDNZ pin, AVDD 1.8-V operation
SHDNZ pin, AVDD 3.3-V operation
SHDNZ pin, AVDD 1.8-V operation
–0.3
–0.3
V
V
V
Low-level digital input logic
voltage threshold
VIL(SHDNZ)
0.9
0.75 ×
IOVDD
IOVDD +
0.3
High-level digital input logic
voltage threshold
VIH(SHDNZ)
IOVDD +
0.3
SHDNZ pin, AVDD 3.3-V operation
2.25
–5
V
Input logic-low leakage for
digital inputs
IIL
All digital pins except PDMDINx_GPIx pins, input = 0 V
0.1
0.1
5
5
µA
µA
Input logic-high leakage for All digital pins except PDMDINx_GPIx pins, input =
IIH
–5
digital inputs
IOVDD
0.35 ×
AVDD
All PDMDINx_GPIx digital pins, AVDD 1.8-V operation
All PDMDINx_GPIx digital pins, AVDD 3.3-V operation
All PDMDINx_GPIx digital pins, AVDD 1.8-V operation
All PDMDINx_GPIx digital pins, AVDD 3.3-V operation
–0.3
–0.3
Low-level digital input logic
voltage threshold
VIL(GPIx)
V
V
0.8
AVDD + 0.3
AVDD + 0.3
0.45
0.65 ×
AVDD
High-level digital input logic
voltage threshold
VIH(GPIx)
2
All PDMCLKx_GPOx digital pins, IOL = –2 mA, AVDD
1.8-V operation
Low-level digital output
voltage
VOL(GPOx)
V
V
All PDMCLKx_GPOx digital pins, IOL = –2 mA, AVDD
3.3-V operation
0.4
All PDMCLKx_GPOx digital pins, IOH = 2 mA, AVDD 1.8-
V operation
AVDD –
0.45
High-level digital output
voltage
VOH(GPOx)
All PDMCLKx_GPOx digital pins, IOH = 2 mA, AVDD 3.3-
V operation
2.4
–5
–5
Input logic-high leakage for
digital inputs
IIL(GPIx)
IIH(GPIx)
CIN
All PDMDINx_GPIx digital pins, input = 0 V
All PDMDINx_GPIx digital pins, input = AVDD
All digital pins
0.1
0.1
5
5
5
µA
µA
pF
Input logic-high leakage for
digital inputs
Input capacitance for
digital inputs
Pulldown resistance for
digital I/O pins when
asserted on
RPD
20
kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD SHDNZ = 0, AVDD = 3.3 V
1
1
SHDNZ = 0, AVDD = 1.8 V, external AREG supply
(AREG shorted to AVDD)
IAVDD
Current consumption in
hardware shutdown mode
µA
IIOVDD
IIOVDD
SHDNZ = 0, all external clocks stopped, IOVDD = 3.3 V
SHDNZ = 0, all external clocks stopped, IOVDD = 1.8 V
0.1
0.1
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Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, PDMCLKx = 64 × fS, 32-bit audio data,
BCLK = 256 × fS, TDM slave mode, PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IAVDD
IAVDD
All external clocks stopped, AVDD = 3.3 V
5
All external clocks stopped, AVDD = 1.8 V, external
AREG supply (AREG shorted to AVDD)
Current consumption in
sleep mode (software
shutdown mode)
5
µA
IIOVDD
IIOVDD
IAVDD
All external clocks stopped, IOVDD = 3.3 V
All external clocks stopped, IOVDD = 1.8 V
AVDD = 3.3 V
0.1
0.1
11.9
Current consumption with
8-channel PDM input
recording, fS = 48 kHz,
PDMCLKx = 64 × fS, PLL
on and BCLK = 256 × fS
AVDD = 1.8 V, external AREG supply (AREG shorted to
AVDD)
IAVDD
11.3
mA
mA
IIOVDD
IIOVDD
IAVDD
IOVDD = 3.3 V
IOVDD = 1.8 V
AVDD = 3.3 V
0.7
0.4
7.2
Current consumption with
4-channel PDM input
recording, fS = 16 kHz,
PDMCLKx = 96 × fS, PLL
on and BCLK = 256 × fS
AVDD = 1.8 V, external AREG supply (AREG shorted to
AVDD)
IAVDD
6.5
IIOVDD
IIOVDD
IOVDD = 3.3 V
IOVDD = 1.8 V
0.2
0.1
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6.6 Timing Requirements: I2C Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 1 for timing diagram
MIN
NOM
MAX
UNIT
STANDARD-MODE
fSCL
SCL clock frequency
0
4
100
kHz
Hold time (repeated) START condition. After this period, the first clock pulse is
generated.
tHD;STA
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
4.7
4
μs
μs
μs
μs
ns
ns
ns
μs
μs
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
4.7
0
3.45
Data setup time
250
SDA and SCL rise time
1000
300
tf
SDA and SCL fall time
tSU;STO
tBUF
Setup time for STOP condition
Bus free time between a STOP and START condition
4
4.7
FAST-MODE
fSCL
SCL clock frequency
0
400
kHz
Hold time (repeated) START condition. After this period, the first clock pulse is
generated.
tHD;STA
0.6
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
1.3
0.6
0.6
0
μs
μs
μs
μs
ns
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
0.9
Data setup time
100
20
SDA and SCL rise time
300
300
20 ×
(IOVDD /
5.5 V)
tf
SDA and SCL fall time
ns
tSU;STO
Setup time for STOP condition
0.6
1.3
μs
μs
tBUF
Bus free time between a STOP and START condition
FAST-MODE PLUS
fSCL
SCL clock frequency
0
1000
kHz
Hold time (repeated) START condition. After this period, the first clock pulse is
generated.
tHD;STA
0.26
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
0.5
0.26
0.26
0
μs
μs
μs
μs
ns
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
Data setup time
50
SDA and SCL rise time
120
120
20 ×
(IOVDD /
5.5 V)
tf
SDA and SCL fall time
ns
tSU;STO
tBUF
Setup time for STOP condition
0.26
0.5
μs
μs
Bus free time between a STOP and START condition
6.7 Switching Characteristics: I2C Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 1 for timing diagram
PARAMETER
TEST CONDITIONS
Standard-mode
MIN
250
250
TYP
MAX
1250
850
UNIT
td(SDA)
SCL to SDA delay
Fast-mode
ns
Fast-mode plus
400
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6.8 Timing Requirements: SPI Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 2 for timing diagram
MIN
40
18
18
16
16
20
8
NOM
MAX
UNIT
t(SCLK)
tH(SCLK)
tL(SCLK)
tLEAD
SCLK period
ns
SCLK high pulse duration
SCLK low pulse duration
Enable lead time
ns
ns
ns
tTRAIL
Enable trail time
ns
tDSEQ
Sequential transfer delay
MOSI data setup time
MOSI data hold time
SCLK rise time
ns
tSU(MOSI)
tHLD(MOSI)
tr(SCLK)
tf(SCLK)
ns
8
ns
10% - 90% rise time
90% - 10% fall time
6
6
ns
SCLK fall time
ns
6.9 Switching Characteristics: SPI Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 2 for timing diagram
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
16
UNIT
ns
ta(MISO)
td(MISO)
tdis(MISO)
MISO access time
SCLK to MISO delay
MISO disable time
50% of SCLK to 50% of MISO
16
ns
20
ns
6.10 Timing Requirements: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram
MIN
40
18
18
8
NOM
MAX
UNIT
t(BCLK)
BCLK period
ns
(1)
tH(BCLK)
tL(BCLK)
tSU(FSYNC)
tHLD(FSYNC)
tr(BCLK)
BCLK high pulse duration
BCLK low pulse duration
FSYNC setup time
FSYNC hold time
BCLK rise time
ns
(1)
ns
ns
8
ns
10% - 90% rise time
90% - 10% fall time
10
10
ns
tf(BCLK)
BCLK fall time
ns
(1) The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is
latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
6.11 Switching Characteristics: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
BCLK to SDOUT delay
50% of BCLK to 50% of SDOUT
18
ns
FSYNC to SDOUT delay in TDM
or LJ mode (for MSB data with
TX_OFFSET = 0)
50% of FSYNC to 50% of
SDOUT
18
ns
BCLK output clock frequency:
master mode
f(BCLK)
24.576
MHz
ns
(1)
BCLK high pulse duration:
master mode
tH(BCLK)
tL(BCLK)
td(FSYNC)
14
14
BCLK low pulse duration: master
mode
ns
BCLK to FSYNC delay: master
mode
50% of BCLK to 50% of FSYNC
18
ns
tr(BCLK)
tf(BCLK)
BCLK rise time: master mode
BCLK fall time: master mode
10% - 90% rise time
90% - 10% fall time
8
8
ns
ns
(1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched on
the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
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6.12 Timing Requirements: PDM Digital Microphone Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 4 for timing diagram
MIN
30
0
NOM
MAX
UNIT
tSU(PDMDINx)
tHLD(PDMDINx)
PDMDINx setup time
PDMDINx hold time
ns
ns
6.13 Switching Characteristics: PDM Digial Microphone Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 4 for timing diagram
PARAMETER
TEST CONDITIONS
MIN
0.768
72
TYP
MAX
UNIT
MHz
ns
f(PDMCLK)
tH(PDMCLK)
tL(PDMCLK)
tr(PDMCLK)
tf(PDMCLK)
PDMCLK clock frequency
PDMCLK high pulse duration
PDMCLK low pulse duration
PDMCLK rise time
6.144
72
ns
10% - 90% rise time
18
18
ns
PDMCLK fall time
90% - 10% fall time
ns
SDA
tBUF
tHD;STA
tLOW
tr
td(SDA)
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
STO
STA
tf
STA
STO
Figure 1. I2C Interface Timing Diagram
SSZ
tDSEQ
tLAG
t(SCLK)
tf(SCLK)
tLEAD
tr(SCLK)
SCLK
tL(SCLK)
tH(SCLK)
td(MISO)
tdis(MISO)
MISO
MOSI
MSB OUT
LSB OUT
BIT6...1
BIT6...1
ta(MISO)
tSU(MOSI) tHLD(MOSI)
MSB IN
LSB IN
Figure 2. SPI Interface Timing Diagram
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FSYNC
tSU(FSYNC)
tHLD(FSYNC)
t(BCLK)
tL(BCLK)
BCLK
tH(BCLK)
tr(BCLK)
tf(BCLK)
td(FSYNC)
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
SDOUT
Figure 3. TDM (With BCLK_POL = 1), I2S, and LJ Interface Timing Diagram
tSU(PDMDINx)
tHLD(PDMDINx) tSU(PDMDINx)
tHLD(PDMDINx)
tH(PDMCLK)
tL(PDMCLK)
PDMCLK
t(PDMCLK)
tf(PDMCLK)
tr(PDMCLK)
PDMDINx
Falling Edge Captured
Rising Edge Captured
Figure 4. PDM Digital Microphone Interface Timing Diagram
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6.14 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, PDMCLKx = 64 × fS, 32-bit audio
data, BCLK = 256 × fS, TDM slave mode, PLL on, and linear phase decimation filter (unless otherwise noted); all performance
measurements are done with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted). All measurements
are done by feeding the device PDM digital input signal using audio precision
-70
-80
-70
-80
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
-90
-90
-100
-110
-120
-130
-140
-100
-110
-120
-130
-140
-130
-115
-100
-85
-70
-55
-40
-25
-10
20
50
100
500
1000
5000 10000 20000
PDM_
Input Amplitude (dB)
Frequency (Hz)
PTDHMD+_
Fifth order PDM modulator with PDMCLKx = 3.072 MHz
Fifth order PDM modulator with PDMCLKx = 3.072 MHz
Figure 5. THD+N vs Input Amplitude
Figure 6. THD+N vs Input Frequency With a –20-dBr Input
20
10
0
Channel-1
Channel-2
-20
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
0
-40
-10
-20
-30
-40
-50
-60
-60
-80
-100
-120
-140
-160
-180
-200
-70
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
-80
-90
-100
-110
-120
20
50 100
500 1000
5000 10000
100000
20
50
100
500
1000
5000 10000 20000
PDM_
Frequency (Hz)
Freq
Frequency (Hz)
PDM_
Fifth order PDM modulator with PDMCLKx = 3.072 MHz
Fifth order PDM modulator with PDMCLKx = 3.072 MHz
Figure 7. Frequency Response With a –20-dBr Input
Figure 8. FFT With a –60-dBr Input
-60
-60
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
-70
-80
-80
Channel-7
Channel-8
Channel-7
Channel-8
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10 -1
20
50
100
500
1000
5000 10000 20000
PDM_
Input Amplitude (dB)
Frequency (Hz)
PTDHMD+_
Fourth order PDM modulator with PDMCLKx = 3.072 MHz
Fourth order PDM modulator with PDMCLKx = 3.072 MHz
Figure 9. THD+N vs Input Amplitude
Figure 10. THD+N vs Input Frequency With a –20-dBr Input
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, PDMCLKx = 64 × fS, 32-bit audio
data, BCLK = 256 × fS, TDM slave mode, PLL on, and linear phase decimation filter (unless otherwise noted); all performance
measurements are done with a 20-kHz, low-pass filter and an A-weighted filter (unless otherwise noted). All measurements
are done by feeding the device PDM digital input signal using audio precision
20
0
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
10
-20
0
-40
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-60
-80
-100
-120
-140
-160
-180
-200
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
20
50 100
500 1000
5000 10000
100000
20
50
100
500
1000
5000 10000 20000
PDM_
Frequency (Hz)
Freq
Frequency (Hz)
PDM_
Fourth order PDM modulator with PDMCLKx = 3.072 MHz
Fourth order PDM modulator with PDMCLKx = 3.072 MHz
Figure 11. Frequency Response With a –20-dBr Input
Figure 12. FFT With a –60-dBr Input
-40
-40
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-50
-50
-60
-60
Channel-7
Channel-8
Channel-7
Channel-8
-70
-70
-80
-90
-80
-90
-100
-110
-100
-110
-130
-115
-100
-85
-70
-55
-40
-25
-10 -1
20
50
100
500
1000
5000 10000 20000
PDM_
Input Amplitude (dB)
Frequency (Hz)
PTDHMD+_
Fourth order PDM modulator with PDMCLKx = 1.536 MHz
Fourth order PDM modulator with PDMCLKx = 1.536 MHz
Figure 13. THD+N vs Input Amplitude
Figure 14. THD+N vs Input Frequency With a –20-dBr Input
20
10
0
Channel-1
Channel-2
-20
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
0
-40
-10
-20
-30
-40
-50
-60
-60
-80
-100
-120
-140
-160
-180
-200
-70
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
-80
-90
-100
-110
-120
20
50 100
500 1000
5000 10000
100000
20
50
100
500
1000
5000 10000 20000
PDM_
Frequency (Hz)
Freq
Frequency (Hz)
PDM_
Fourth order PDM modulator with PDMCLKx = 1.536 MHz
Fourth order PDM modulator with PDMCLKx = 1.536 MHz
Figure 15. Frequency Response With a –20-dBr Input
Figure 16. FFT With a –60-dBr Input
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7 Detailed Description
7.1 Overview
The PCMD3180 is a high-performance, low-power, flexible, 8-channel, pulse-density-modulation (PDM) input to
time-division multiplexing (TDM) or I2S audio output converter with extensive feature integration. This device is
intended for applications in voice-activated systems, portable computing, communication, and entertainment
applications. The low power consumption makes this device is suitable for battery powered portable audio
systems. This device integrates a host of features that reduces cost, board space, and power consumption in
space-constrained, battery-powered, consumer, home, and industrial applications.
The PCMD3180 consists of the following blocks:
•
Eight-channel, pulse density modulation (PDM) digital microphone interface with high-performance decimation
filter
•
•
•
•
•
•
•
Low-noise, microphone bias output to power the digital microphone
Programmable decimation filters with linear-phase or low-latency filter
Programmable digital volume control, biquad filters for each channel
Programmable phase and gain calibration with fine resolution for each channel
Programmable high-pass filter (HPF), and digital channel mixer
Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
Integrated digital and analog voltage regulators to support single-supply operation
Communication to the PCMD3180 to configure the control registers is supported using an I2C or SPI interface.
The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or left-justified
(LJ)] to transmit audio data seamlessly in the system across devices.
The device can support multiple devices by sharing the common I2C and TDM buses across devices. Moreover,
the device includes a daisy-chain feature and a secondary audio serial output data pin. These features relax the
shared TDM bus timing requirements and board design complexities when operating multiple devices for
applications requiring high audio data bandwidth.
Table 1 lists the reference abbreviations used throughout this document to registers that control the device.
Table 1. Abbreviations for Register References
REFERENCE
ABBREVIATION
DESCRIPTION
EXAMPLE
Single data bit. The value of a
single bit in a register.
Page y, register z, bit k
Py_Rz_Dk
Page 4, register 36, bit 0 = P4_R36_D0
Range of data bits. A range of
data bits (inclusive).
Page y, register z, bits k-m
Page y, register z
Py_Rz_D[k:m]
Py_Rz
Page 4, register 36, bits 3-0 = P4_R36_D[3:0]
Page 4, register 36 = P4_R36
One entire register. All eight
bits in the register as a unit.
Range of registers. A range of
registers in the same page.
Page y, registers z-n
Py_Rz-Rn
Page 4, registers 36, 37, 38 = P4_R36-R38
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7.2 Functional Block Diagram
Audio Clock Generation
Multifunction Pins
(Interrupt, PLL Input Clock)
PLL
(Input Clock Source - BCLK, GPIOx,
GPIx)
GPIO1
PDMDIN1_GPI1
PDMCLK1_GPO1
8-Channel Digital PDM
Microphones
Simultaneous
SDOUT
BCLK
High Performance
Digital Filters
(Low Latency LPF,
Programmable
Biquads)
PDMDIN2_GPI2
PDMCLK2_GPO2
Conversion
Audio Serial
Interface (TDM,
I2S, LJ)
and
PDMDIN3_GPI3
PDMCLK3_GPO3
General Purpose Input
and Output
PDMDIN4_GPI4
PDMCLK4_GPO4
FSYNC
I2C or SPI Control
Interface
Programmable
Microphone Bias
Regulators, Current Bias
and Voltage Reference
MICBIAS
SHDNZ
7.3 Feature Description
7.3.1 Serial Interfaces
This device has two serial interfaces: control and audio data. The control serial interface is used for device
configuration. The audio data serial interface is used for transmitting audio data to the host device.
7.3.1.1 Control Serial Interfaces
The device contains configuration registers and programmable coefficients that can be set to the desired values
for a specific system and application use. All these registers can be accessed using either I2C or SPI
communication to the device. For more information, see the Programming section.
7.3.1.2 Audio Serial Interfaces
Digital audio data flows between the host processor and the PCMD3180 on the digital audio serial interface
(ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S
or left-justified protocols format, programmable data length options, very flexible master-slave configurability for
bus clock lines and the ability to communicate with multiple devices within a system directly.
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Feature Description (continued)
The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0],
P0_R7_D[7:6] register bits. As shown in Table 2 and Table 3, these modes are all most significant byte (MSB)-
first, pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16,
20, 24, or 32 bits by configuring the ASI_WLEN[1:0], P0_R7_D[5:4] register bits.
Table 2. Audio Serial Interface Format
P0_R7_D[7:6] : ASI_FORMAT[1:0]
AUDIO SERIAL INTERFACE FORMAT
00 (default)
Time division multiplexing (TDM) mode
01
10
11
Inter IC sound (I2S) mode
Left-justified (LJ) mode
Reserved (do not use this setting)
Table 3. Audio Output Channel Data Word-Length
P0_R7_D[5:4] : ASI_WLEN[1:0]
AUDIO OUTPUT CHANNEL DATA WORD-LENGTH
00
01
Output channel data word-length set to 16 bits
Output channel data word-length set to 20 bits
Output channel data word-length set to 24 bits
Output channel data word-length set to 32 bits
10
11 (default)
The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the
same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio
data across the serial bus. The number of bit-clock cycles in a frame must accommodate multiple device active
output channels with the programmed data word length.
A frame consists of multiple time-division channel slots (up to 64) to allow all output channel audio data
transmissions to complete on the audio bus by a device or multiple PCMD3180 devices sharing the same audio
bus. The device supports up to eight output channels that can be configured to place their audio data on bus slot
0 to slot 63. Table 4 lists the output channel slot configuration settings. In I2S and LJ mode, the slots are divided
into two sets, left-channel slots and right-channel slots, as described in the Inter IC Sound (I2S) Interface and
Left-Justified (LJ) Interface sections.
Table 4. Output Channel Slot Assignment Settings
P0_R11_D[5:0] : CH1_SLOT[5:0]
00 0000 = 0d (default)
00 0001 = 1d
OUTPUT CHANNEL 1 SLOT ASSIGNMENT
Slot 0 for TDM or left slot 0 for I2S, LJ.
Slot 1 for TDM or left slot 1 for I2S, LJ.
…
…
01 1111 = 31d
10 0000 = 32d
…
Slot 31 for TDM or left slot 31 for I2S, LJ.
Slot 32 for TDM or right slot 0 for I2S, LJ.
…
11 1110 = 62d
11 1111 = 63d
Slot 62 for TDM or right slot 30 for I2S, LJ.
Slot 63 for TDM or right slot 31 for I2S, LJ.
Similarly, the slot assignment setting for output channel 2 to channel 8 can be done using the CH2_SLOT
(P0_R12) to CH8_SLOT (P0_R18) registers, respectively.
The slot word length is the same as the output channel data word length set for the device. The output channel
data word length must be set to the same value for all PCMD3180 devices if all devices share the same ASI bus
in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available bus
bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data word
length configured.
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The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by
up to 31 cycles of the bit clock. Table 5 lists the programmable offset configuration settings.
Table 5. Programmable Offset Settings for the ASI Slot Start
P0_R8_D[4:0] : TX_OFFSET[4:0]
PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START
0 0000 = 0d (default)
The device follows the standard protocol timing without any offset.
Slot start is offset by one BCLK cycle, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to
standard protocol timing.
0 0001 = 1d
......
......
Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to
standard protocol timing.
1 1110 = 30d
Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to
standard protocol timing.
1 1111 = 31d
The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio
data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using
the FSYNC_POL, P0_R7_D3 register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK,
which can be set using the BCLK_POL, P0_R7_D2 register bit.
7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data
first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and
each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.
Figure 17 to Figure 20 illustrate the protocol timing for TDM operation with various configurations.
FSYNC
BCLK
SDOUT
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-2 to Slot-7
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
Figure 17. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
nth Sample
Slot-0
(Word Length : N)
(n+1)th Sample
Slot-2 to Slot-7
(Word Length : N)
TX_OFFSET = 2
TX_OFFSET = 2
Figure 18. TDM Mode Protocol Timing (TX_OFFSET = 2)
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FSYNC
BCLK
1
0
N-1
2
1
0
N-1 N-2 N-3
2
1
0
2
1
0
N-1 N-2 N-3
0
N-1 N-2
3
2
1
0
N-1
SDOUT
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
Slot-2 to Slot-7
(Word Length : N)
TX_OFFSET = 2
nth Sample
Figure 19. TDM Mode Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 2)
FSYNC
BCLK
SDOUT
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-2 to Slot-7
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
Figure 20. TDM Mode Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)
For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels times the programmed word length of the output channel data.
The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well. For a
higher BCLK frequency operation, using TDM mode with a TX_OFFSET value higher than 0 is recommended.
7.3.1.2.2 Inter IC Sound (I2S) Interface
The standard I2S protocol is defined for only two channels: left and right. The device extends the same protocol
timing for multichannel operation. In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of
BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the
remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of
BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission,
the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge
of BCLK. Figure 21 to Figure 24 illustrate the protocol timing for I2S operation with various configurations.
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
Figure 21. I2S Mode Standard Protocol Timing (TX_OFFSET = 0)
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FSYNC
BCLK
SDOUT
N-1
1
0
N-1 N-2
1
0
N-1
1
0
N-1
N-1
1
0
1
0
Left
Slot-0
(Word Length : N) (Word Length : N)
Left
Slot-2 to Slot-3
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 1
TX_OFFSET = 1
TX_OFFSET = 1
nth Sample
Figure 22. I2S Protocol Timing (TX_OFFSET = 1)
FSYNC
BCLK
N-1 N-2
1
0
N-1 N-2
0
0
N-1
1
0
N-1
1
0
N-1 N-2
0
N-1
1
0
N-1 N-2
1
0
SDOUT
Left
Slot-0
(Word Length : N)
(n+1)th Sample
Left
Slot-1 to Slot-3
(Word Length : N)
Right
Slot-1 to Slot-3
(Word Length : N)
nth Sample
Figure 23. I2S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
Figure 24. I2S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)
For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the programmed word length
of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater
than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high
pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots
times the data word length configured.
7.3.1.2.3 Left-Justified (LJ) Interface
The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol
timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle
after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK.
Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB
of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data
bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining
right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. Figure 25 to Figure 28
illustrate the protocol timing for LJ operation with various configurations.
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FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
Figure 25. LJ Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
1
0
N-1 N-2
1
0
N-1
1
0
N-1
N-1
1
0
1
0
Left
Slot-0
(Word Length : N) (Word Length : N)
Left
Slot-2 to Slot-3
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 2
TX_OFFSET = 2
TX_OFFSET = 2
nth Sample
Figure 26. LJ Protocol Timing (TX_OFFSET = 2)
FSYNC
BCLK
N-1 N-2
1
0
N-1 N-2
0
0
N-1
1
0
N-1
1
0
N-1 N-2
0
N-1
1
0
N-1 N-2
1
0
SDOUT
Left
Slot-0
(Word Length : N)
(n+1)th Sample
Left
Slot-1 to Slot-3
(Word Length : N)
Right
Slot-1 to Slot-3
(Word Length : N)
nth Sample
Figure 27. LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 1
TX_OFFSET = 1
TX_OFFSET = 1
nth Sample
Figure 28. LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1)
For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the programmed word length
of the output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater
than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC low
pulse must be number of BCLK cycles wide that is greater than or equal to the number of active right slots times
the data word length configured. For a higher BCLK frequency operation, using LJ mode with a TX_OFFSET
value higher than 0 is recommended.
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7.3.1.3 Using Multiple Devices With Shared Buses
The device has many supported features and flexible options that can be used in the system to seamlessly
connect multiple PCMD3180 devices by sharing a single common I2C control bus and an audio serial interface
bus. This architecture enables multiple applications to be applied to a system that require a microphone array for
beam-forming operation, audio conferencing, noise cancellation, and so forth. Figure 29 shows a diagram of
multiple PCMD3180 devices in a configuration where the control and audio data buses are shared.
Control Bus œ I2C Interface
PCMD3180
U1
PCMD3180
U2
PCMD3180
U3
PCMD3180
U4
Host Processor
Audio Data Bus œ TDM, I2S, LJ Interface
Figure 29. Multiple PCMD3180 Devices With Shared Control and Audio Data Buses
The PCMD3180 consists of the following features to enable seamless connection and interaction of multiple
devices using a shared bus:
•
•
•
•
•
•
•
•
•
•
Supports up to four pin-programmable I2C slave addresses
I2C broadcast simultaneously writes to (or triggers) all PCMD3180 devices
Supports up to 64 configuration output channel slots for the audio serial interface
Tri-state feature (with enable and disable) for the unused audio data slots of the device
Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus
The GPIO1 or GPOx pin can be configured as a secondary output data lane for the audio serial interface
The GPIO1 or GPIx pin can be used in a daisy-chain configuration of multiple PCMD3180 devices
Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface
Programmable master and slave options for the audio serial interface
Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices
The system can also connect multiple PCMD3180 devices in combination with TLV320ADCx140 devices by
sharing a single common I2C control bus and an audio serial interface bus. See the Multiple TLV320ADCx140
Devices With Shared TDM and I2C Bus application report for further details.
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7.3.2 Phase-Locked Loop (PLL) and Clock Generation
The device has a smart auto-configuration block to generate all necessary internal clocks required for the PDM
clock generation and the digital filter engine used for signal processing. This configuration is done by monitoring
the frequency of the FSYNC and BCLK signal on the audio bus.
The device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to
FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming.
Table 6 and Table 7 list the supported FSYNC and BCLK frequencies.
Table 6. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
RATIO
FSYNC
(8 kHz)
FSYNC
(16 kHz)
FSYNC
(24 kHz)
FSYNC
(32 kHz)
FSYNC
(48 kHz)
FSYNC
(96 kHz)
FSYNC
(192 kHz)
FSYNC
(384 kHz)
FSYNC
(768 kHz)
16
24
Reserved
Reserved
0.256
0.256
0.384
0.512
0.768
1.024
1.536
2.048
3.072
4.096
6.144
8.192
16.384
Reserved
0.384
0.576
0.512
0.768
0.768
1.152
1.536
2.304
3.072
4.608
6.144
12.288
9.216
18.432
32
0.768
1.024
1.536
3.072
6.144
12.288
24.576
48
0.384
1.152
1.536
2.304
4.608
9.216
18.432
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64
0.512
1.536
2.048
3.072
6.144
12.288
24.576
96
0.768
2.304
3.072
4.608
9.216
18.432
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
192
256
384
512
1024
2048
1.024
3.072
4.096
6.144
12.288
18.432
24.576
Reserved
Reserved
Reserved
Reserved
24.576
1.536
4.608
6.144
9.216
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2.048
6.144
8.192
12.288
18.432
24.576
Reserved
Reserved
3.072
9.216
12.288
16.384
Reserved
Reserved
4.096
12.288
24.576
Reserved
8.192
16.384
Table 7. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
RATIO
FSYNC
(7.35 kHz)
FSYNC
FSYNC
FSYNC
FSYNC
(44.1 kHz)
FSYNC
FSYNC
FSYNC
FSYNC
(14.7 kHz) (22.05 kHz) (29.4 kHz)
(88.2 kHz) (176.4 kHz) (352.8 kHz) (705.6 kHz)
16
24
Reserved
Reserved
Reserved
0.3528
Reserved
0.3528
0.4704
0.7056
0.9408
1.4112
1.8816
2.8224
3.7632
5.6448
7.5264
15.0528
Reserved
0.3528
0.5292
0.7056
1.0584
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
22.5792
Reserved
0.4704
0.7056
0.7056
1.0584
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
16.9344
32
0.9408
1.4112
2.8224
5.6448
11.2896
22.5792
48
1.4112
2.1168
4.2336
8.4672
16.9344
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64
0.4704
1.8816
2.8224
5.6448
11.2896
16.9344
22.5792
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
22.5792
96
0.7056
2.8224
4.2336
8.4672
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
192
256
384
512
1024
2048
0.9408
3.7632
5.6448
11.2896
16.9344
22.5792
Reserved
Reserved
Reserved
Reserved
1.4112
5.6448
8.4672
1.8816
7.5264
11.2896
16.9344
22.5792
Reserved
Reserved
2.8224
11.2896
15.0528
Reserved
Reserved
3.7632
7.5264
15.0528
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The status register ASI_STS, P0_R21, captures the device auto detect result for the FSYNC frequency and the
BCLK to FSYNC ratio. If the device finds any unsupported combinations of FSYNC frequency and BCLK to
FSYNC ratios, the device generates an ASI clock-error interrupt and mutes the record channels accordingly.
The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the
PDM clock generation and digital filter engine, as well as other control blocks. The device also supports an
option to use BCLK, GPIO1, or the GPIx pin (as MCLK) as the audio clock source without using the PLL to
reduce power consumption. However, the PDM microphone performance may degrade based on jitter from the
external clock source, and some processing features may not be supported if the external audio clock source
frequency is not high enough. Therefore, TI recommends using the PLL for high-performance applications. More
details and information on how to configure and use the device in low-power mode without using the PLL are
discussed in the TLV320ADCx140 Power Consumption Matrix Across Various Usage Scenario application report.
The device also supports an audio bus master mode operation using the GPIO1 or GPIx pin (as MCLK) as the
reference input clock source and supports various flexible options and a wide variety of system clocks. More
details and information on master mode configuration and operation are discussed in the Configuring and
Operating the TLV320ADCx140 as Audio Bus Master application report.
The audio bus clock error detection and auto-detect feature automatically generates all internal clocks, but can
be disabled using the ASI_ERR, P0_R9_D5 and AUTO_CLK_CFG, P0_R19_D6, register bits, respectively. In
the system, this disable feature can be used to support custom clock frequencies that are not covered by the
auto detect scheme. For such application use cases, care must be taken to ensure that the multiple clock
dividers are all configured appropriately. Therefore, TI recommends using the PPC3 GUI for device configuration
settings; for more details see the ADCx140EVM-PDK user's guide and the PurePath™ Console Graphical
Development Suite for Audio System Design and Development.
7.3.3 Reference Voltage
The PCMD3180 achieves low-noise performance by internally generating a low-noise reference voltage. This
reference voltage is generated using a band-gap circuit with high PSRR performance and must be filtered
externally using a 1-µF capacitor connected from the VREF pin to analog ground (AVSS).
The value of this reference voltage can be configured using the P0_R59_D[1:0] register bits and must be set to
an appropriate value based on the AVDD supply voltage available in the system. The default VREF value is set
to 2.75 V, which require minimum AVDD voltage for this mode is 3 V. Table 8 lists the various VREF settings
supported along with required AVDD range for that configuration.
Table 8. VREF Programmable Settings
P0_R59_D[1:0] : VREF_SEL[1:0]
VREF OUTPUT VOLTAGE
AVDD RANGE REQUIREMENT
3 V to 3.6 V
00 (default)
2.75 V
2.5 V
01
10
11
2.8 V to 3.6 V
1.375 V
Reserved
1.7 V to 1.9 V
Reserved
To achieve low-power consumption, this audio reference block is powered down as described in the Sleep Mode
or Software Shutdown section. When exiting sleep mode, the audio reference block is powered up using the
internal fast-charge scheme and the VREF pin settles to its steady-state voltage after the settling time (a function
of the decoupling capacitor on the VREF pin). This time is approximately equal to 3.5 ms when using a 1-μF
decoupling capacitor. If a higher-value decoupling capacitor is used on the VREF pin, the fast-charge setting
must be reconfigured using the VREF_QCHG, P0_R2_D[4:3] register bits, which support options of 3.5 ms
(default), 10 ms, 50 ms, or 100 ms.
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7.3.4 Microphone Bias
The device integrates a built-in, low-noise programmable microphone bias pin that can be used in the system for
providing the supply to the MEMS digital microphone. The MICBIAS pin must be connected to external 1-µF to
analog ground (AVSS). The MICBIAS pin supports up to 20 mA of load current that can be used for multiple
microphones. When using this MICBIAS pin for biasing or supplying to multiple microphones, avoid any common
impedance on the board layout for the MICBIAS connection to minimize coupling across microphones. In system,
if MICBIAS pin is used as supply for digital microphones then TI recommends to use MICBIAS configuration as
AVDD, so that the digital microphone's PDMCLKx and PDMDINx signals can be directly interface to PCMD3180
without using any external level shifters. Table 9 shows the available microphone bias programmable options.
Table 9. MICBIAS Programmable Settings
P0_R59_D[6:4] : MBIAS_VAL[2:0]
P0_R59_D[1:0] : VREF_SEL[1:0]
MICBIAS OUTPUT VOLTAGE
2.75 V (same as the VREF output)
2.5 V (same as the VREF output)
1.375 V (same as the VREF output)
Reserved (do not use these settings)
Same as AVDD
00 (default)
000 (default)
01
10
001 to 101
110
XX
XX
XX
111
Reserved (do not use this setting)
The microphone bias output can be powered on or powered off (default) by configuring the MICBIAS_PDZ,
P0_R117_D7 register bit. Additionally, the device provides an option to configure the GPIO1 or GPIx pin to
directly control the microphone bias output powering on or off. This feature is useful to control the microphone
directly without engaging the host for I2C or SPI communication. The MICBIAS_PDZ, P0_R117_D7 register bit
value is ignored if the GPIO1 or GPIx pin is configured to set the microphone bias on or off.
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7.3.5 Digital PDM Microphone Record Channel
The device interfaces up to eight digital pulse-density-modulation (PDM) microphones for simultaneous
conversion and uses high-order and high-performance decimation filters to generate pulse code modulation
(PCM) output data that can be transmitted on the audio serial interface to the host using either time-division
multiplexing (TDM), I2S, or left-justified (LJ) audio formats.
The device internally generates PCMCLK with a programmable frequency of either 6.144 MHz, 3.072 MHz,
1.536 MHz, or 768 kHz (for output data sample rates in multiples or submultiples of 48 kHz) or 5.6448 MHz,
2.8224 MHz, 1.4112 MHz, or 705.6 kHz (for output data sample rates in multiples or submultiples of 44.1 kHz)
using the PDMCLK_DIV[1:0], P0_R31_D[1:0] register bits. PDMCLK can be routed on the PDMCLKx_GPOx pin.
This clock can be connected to the external digital microphone device. The device also support control register to
independently configure each channel PDMDINx data to be latched using either rising edge or falling edge.
Figure 30 shows a connection diagram of the digital PDM microphones.
VDD
VDD
VDD
DATA
AVDD
Digital
PDM
SEL Microphone
U1
CLK
GND
GND
PCMD3180
VDD
VDD
PDMDINx_GPIx
DATA
CLK
Digital
PDM
SEL Microphone
U2
PDMCLKx_GPOx
GND
GND
Figure 30. Digital PDM Microphones Connection Diagram to the PCMD3180
The single-bit output of the external digital microphone device can be connected to the GPIx pin. This single data
line can be shared by two digital microphones to place their data on the opposite edge of PDMCLK. Internally,
the device latches the steady value of the data on the rising edge of PDMCLK or the falling edge of PDMCLK
based on the configuration register bits set in P0_R32_D[7:4]. Figure 31 shows the digital PDM microphone
interface timing diagram.
PDMCLK
PDMDINx
D1[n]
D2[n]
D1[n+1]
D2[n+1]
D1[n+2]
Mic-1
Data
Mic-2
Data
Mic-1
Data
Mic-2
Data
Mic-1
Data
(n+1)th Sample
(n+2)th Sample
nth Sample
Figure 31. Digital PDM Microphone Protocol Timing Diagram
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7.3.6 Signal-Chain Processing
The PCMD3180 signal chain is comprised of high-performance, low-power and highly flexible and programmable
digital processing blocks. The high performance and flexibility combined with a compact package makes the
PCMD3180 optimized for a wide variety of end-equipments and applications that require multichannel audio
capture. Figure 32 shows a conceptual block diagram that highlights the various building blocks used in the
signal chain, and how the blocks interact in the signal chain.
PDMCLK
High Performance
Decimation
Filters
PDM
Interface
Digital Microphone
Phase
Calibration
PDMDIN
Output
Channel
Data to ASI
Digital Summer/Mixer
(Applies to Ch1-Ch4
only)
Gain
Calibration
Biquad
Filters
Digital Volume
Control (DVC)
HPF
Ch1-Ch4 Processed Data after Gain
Calibration
Figure 32. Signal-Chain Processing Flowchart
The device supports up to eight digital PDM microphone recording channels for simultaneous operation. The
signal chain consists of various highly programmable digital processing blocks such as phase calibration, gain
calibration, high-pass filter, digital summer or mixer, biquad filters, and volume control. The details on these
processing blocks are discussed further in this section. Channels 1 to 4 in the signal chain block diagram of
Figure 32 are as described in this section, however, channels 5 to 8 do not support the digital summer or mixer
option.
The desired input channels for recording can be enabled or disabled by using the IN_CH_EN (P0_R115)
register, and the output channels for the audio serial interface can be enabled or disabled by using the
ASI_OUT_EN (P0_R116) register. In general, the device supports simultaneous power-up and power-down of all
active channels for simultaneous recording. However, based on the application needs, if some channels must be
powered-up or powered-down dynamically when the other channel recording is on, then that use case is
supported by setting the DYN_CH_PUPD_EN, P0_R117_D4 register bit to 1'b1 but do not power-down channel
1 in this mode of operation.
The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal to
be recorded by using a 176.4-kHz (or higher) sample rate.
For output sample rates of 48 kHz or lower, the device supports all features for 8-channel recording and various
programmable processing blocks. However, for output sample rates higher than 48 kHz, there are limitations in
the number of simultaneous channel recordings supported and the number of biquad filters and such. See the
TLV320ADCx140 Sampling Rates and Programmable Processing Blocks Supported application report for further
details.
7.3.6.1 Programmable Digital Volume Control
The device has a programmable digital volume control with a range from –100 dB to 27 dB in steps of 0.5 dB
with the option to mute the channel recording. The digital volume control value can be changed dynamically while
the channel is powered-up and recording. During volume control changes, the soft ramp-up or ramp-down
volume feature is used internally to avoid any audible artifacts. Soft-stepping can be entirely disabled using the
DISABLE_SOFT_STEP (P0_R108_D4) register bit.
The digital volume control setting is independently available for each output channel, including the digital
microphone record channel. However, the device also supports an option to gang-up the volume control setting
for all channels together using the channel 1 digital volume control setting, regardless if channel 1 is powered up
or powered down. This gang-up can be enabled using the DVOL_GANG (P0_R108_D7) register bit.
Table 10 shows the programmable options available for the digital volume control.
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Table 10. Digital Volume Control (DVC) Programmable Settings
P0_R62_D[7:0] : CH1_DVOL[7:0]
0000 0000 = 0d
DVC SETTING FOR OUTPUT CHANNEL 1
Output channel 1 DVC is set to mute
0000 0001 = 1d
0000 0010 = 2d
0000 0011 = 3d
…
Output channel 1 DVC is set to –100 dB
Output channel 1 DVC is set to –99.5 dB
Output channel 1 DVC is set to –99 dB
…
1100 1000 = 200d
1100 1001 = 201d (default)
1100 1010 = 202d
…
Output channel 1 DVC is set to –0.5 dB
Output channel 1 DVC is set to 0 dB
Output channel 1 DVC is set to 0.5 dB
…
1111 1101 = 253d
1111 1110 = 254d
1111 1111 = 255d
Output channel 1 DVC is set to 26 dB
Output channel 1 DVC is set to 26.5 dB
Output channel 1 DVC is set to 27 dB
Similarly, the digital volume control setting for output channel 2 to channel 8 can be configured using the
CH2_DVOL (P0_R67) to CH8_DVOL (P0_R97) register bits, respectively.
The internal digital processing engine soft ramps up the volume from a muted level to the programmed volume
level when the channel is powered up, and the internal digital processing engine soft ramps down the volume
from a programmed volume to mute when the channel is powered down. This soft-stepping of volume is done to
prevent abruptly powering up and powering down the record channel. This feature can also be entirely disabled
using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.
7.3.6.2 Programmable Channel Gain Calibration
Along with the programmable channel gain and digital volume, this device also provides programmable channel
gain calibration. The gain of each channel can be finely calibrated or adjusted in steps of 0.1 dB for a range of
–0.8-dB to 0.7-dB gain error. This adjustment is useful when trying to match the gain across channels resulting
from external components and microphone sensitivity. This feature, in combination with the regular digital volume
control, allows the gains across all channels to be matched for a wide gain error range with a resolution of
0.1 dB. Table 11 shows the programmable options available for the channel gain calibration.
Table 11. Channel Gain Calibration Programmable Settings
P0_R63_D[7:4] : CH1_GCAL[3:0]
CHANNEL GAIN CALIBRATION SETTING FOR INPUT CHANNEL 1
Input channel 1 gain calibration is set to –0.8 dB
Input channel 1 gain calibration is set to –0.7 dB
…
0000 = 0d
0001 = 1d
…
1000 = 8d (default)
…
Input channel 1 gain calibration is set to 0 dB
…
1110 = 14d
1111 = 15d
Input channel 1 gain calibration is set to 0.6 dB
Input channel 1 gain calibration is set to 0.7 dB
Similarly, the channel gain calibration setting for input channel 2 to channel 8 can be configured using the
CH2_GCAL (P0_R68) to CH8_GCAL (P0_R98) register bits, respectively.
7.3.6.3 Programmable Channel Phase Calibration
In addition to the gain calibration, the phase delay in each channel can be finely calibrated or adjusted in steps of
one modulator clock cycle for a cycle range of 0 to 255 for the phase error. The modulator clock is 6.144 MHz
(the output data sample rate is multiples or submultiples of 48 kHz) or 5.6448 MHz (the output data sample rate
is multiples or submultiples of 44.1 kHz) irrespective of the PDMCLK frequency used for digital microphone. This
feature is very useful for many applications that must match the phase with fine resolution between each
channel, including any phase mismatch across channels resulting from external components or microphones.
Table 12 shows the available programmable options for channel phase calibration.
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Table 12. Channel Phase Calibration Programmable Settings
P0_R64_D[7:0] : CH1_PCAL[7:0]
CHANNEL PHASE CALIBRATION SETTING FOR INPUT CHANNEL 1
Input channel 1 phase calibration with no delay
0000 0000 = 0d (default)
0000 0001 = 1d
0000 0010 = 2d
…
Input channel 1 phase calibration delay is set to one cycle of the modulator clock
Input channel 1 phase calibration delay is set to two cycles of the modulator clock
…
1111 1110 = 254d
1111 1111 = 255d
Input channel 1 phase calibration delay is set to 254 cycles of the modulator clock
Input channel 1 phase calibration delay is set to 255 cycles of the modulator clock
Similarly, the channel phase calibration setting for input channel 2 to channel 8 can be configured using the
CH2_PCAL (P0_R69) to CH8_PCAL (P0_R99) register bits, respectively.
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7.3.6.4 Programmable Digital High-Pass Filter
To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data,
the device supports a programmable high-pass filter (HPF). The HPF is not a channel-independent filter setting
but is globally applicable for all the channels. This HPF is constructed using the first-order infinite impulse
response (IIR) filter, and is efficient enough to filter out possible DC components of the signal. Table 13 shows
the predefined –3-dB cutoff frequencies available that can be set by using the HPF_SEL[1:0] register bits of
P0_R107. Additionally, to achieve a custom –3-dB cutoff frequency for a specific application, the device also
allows the first-order IIR filter coefficients to be programmed when the HPF_SEL[1:0] register bits are set to
2'b00. Figure 33 illustrates a frequency response plot for the HPF filter.
Table 13. HPF Programmable Settings
P0_R107_D[1:0] :
HPF_SEL[1:0]
-3-dB CUTOFF FREQUENCY
SETTING
-3-dB CUTOFF FREQUENCY AT
16-kHz SAMPLE RATE
-3-dB CUTOFF FREQUENCY AT
48-kHz SAMPLE RATE
00
01 (default)
10
Programmable 1st-order IIR filter
0.00025 × fS
Programmable 1st-order IIR filter
Programmable 1st-order IIR filter
4 Hz
32 Hz
128 Hz
12 Hz
96 Hz
0.002 × fS
11
0.008 × fS
384 Hz
3
0
-3
-6
-9
-12
-15
-18
-21
-24
-27
-30
-33
-36
-39
-42
-45
5E-5
HPF -3 dB Cutoff = 0.00025 ì fS
HPF -3 dB Cutoff = 0.002 ì fS
HPF -3 dB Cutoff = 0.008 ì fS
0.0001
0.0005
0.001
Normalized Frequency (1/fS)
0.005
0.01
0.05
D003
Figure 33. HPF Filter Frequency Response Plot
Equation 1 gives the transfer function for the first-order programable IIR filter:
00 + 01VF1
231 F &1VF1
: ;
* V =
(1)
The frequency response for this first-order programmable IIR filter with default coefficients is flat at a gain of 0 dB
(all-pass filter). The host device can override the frequency response by programming the IIR coefficients in
Table 14 to achieve the desired frequency response for high-pass filtering or any other desired filtering. If
HPF_SEL[1:0] are set to 2'b00, the host device must write these coefficients values for the desired frequency
response before powering-up any PDM channel for recording. These programmable coefficients are 32-bit, two’s
complement numbers. Table 14 shows the filter coefficients for the first-order IIR filter.
Table 14. 1st-Order IIR Filter Coefficients
FILTER
COEFFICIENT
DEFAULT COEFFICIENT
VALUE
COEFFICIENT REGISTER
MAPPING
FILTER
N0
N1
D1
0x7FFFFFFF
0x00000000
0x00000000
P4_R72-R75
P4_R76-R79
P4_R80-R83
Programmable 1st-order IIR filter (can be
allocated to HPF or any other desired filter)
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7.3.6.5 Programmable Digital Biquad Filters
The device supports up to 12 programmable digital biquad filters. These highly efficient filters achieve the desired
frequence response. In digital signal processing, a digital biquad filter is a second-order, recursive linear filter
with two poles and two zeros. Equation 2 gives the transfer function of each biquad filter:
00 + 201VF1 + 02VF2
231 F 2&1VF1 F &2VF2
: ;
* V =
(2)
The frequency response for the biquad filter section with default coefficients is flat at a gain of 0dB (all-pass
filter). The host device can override the frequency response by programming the biquad coefficients to achieve
the desired frequency response for a low-pass, high-pass, or any other desired frequency shaping. The
programmable coefficients for the mixer operation are located in the Programmable Coefficient Registers: Page =
0x02 and Programmable Coefficient Registers: Page = 0x03 sections. If biquad filtering is required, then the host
device must write these coefficients values before powering up any PDM channels for recording. These
programmable coefficients are 32-bit, two’s complement numbers. As described in Table 15, these biquad filters
can be allocated for each output channel based on the BIQUAD_CFG[1:0] register setting of P0_R108. By
setting BIQUAD_CFG[1:0] to 2'b00, the biquad filtering for all record channels is disabled and the host device
can choose this setting if no additional filtering is required for the system application. See the TLV320ADCx140
Programmable Biquad Filter Configuration and Applications application report for further details.
Table 15. Biquad Filter Allocation to the Record Output Channel
RECORD OUTPUT CHANNEL ALLOCATION USING P0_R108_D[6:5] REGISTER SETTING
BIQUAD_CFG[1:0] = 2'b01
(1 Biquad per Channel)
BIQUAD_CFG[1:0] = 2'b10 (Default)
(2 Biquads per Channel)
BIQUAD_CFG[1:0] = 2'b11
(3 Biquads per Channel)
PROGRAMMABLE
BIQUAD FILTER
SUPPORTS ALL 8 CHANNELS
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Not used
SUPPORTS UP TO 6 CHANNELS
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 5
Allocated to output channel 6
Allocated to output channel 5
Allocated to output channel 6
SUPPORTS UP TO 4 CHANNELS
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Biquad filter 1
Biquad filter 2
Biquad filter 3
Biquad filter 4
Biquad filter 5
Biquad filter 6
Biquad filter 7
Biquad filter 8
Biquad filter 9
Biquad filter 10
Biquad filter 11
Biquad filter 12
Not used
Not used
Not used
Allocated to output channel 5
Allocated to output channel 6
Allocated to output channel 7
Allocated to output channel 8
Table 16 shows the biquad filter coefficients mapping to the register space.
Table 16. Biquad Filter Coefficients Register Mapping
PROGRAMMABLE BIQUAD
FILTER
BIQUAD FILTER COEFFICIENTS
REGISTER MAPPING
PROGRAMMABLE BIQUAD
FILTER
BIQUAD FILTER COEFFICIENTS
REGISTER MAPPING
Biquad filter 1
Biquad filter 2
Biquad filter 3
Biquad filter 4
Biquad filter 5
Biquad filter 6
P2_R8-R27
P2_R28-R47
P2_R48-R67
P2_R68-R87
P2_R88-R107
P2_R108-R127
Biquad filter 7
Biquad filter 8
Biquad filter 9
Biquad filter 10
Biquad filter 11
Biquad filter 12
P3_R8-R27
P3_R28-R47
P3_R48-R67
P3_R68-R87
P3_R88-R107
P3_R108-R127
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7.3.6.6 Programmable Channel Summer and Digital Mixer
For applications that require an even higher SNR than that supported for each channel, the device digital
summing mode can be used. In this mode, the digital record data are summed up across the channel with an
equal weightage factor, which helps in reducing the effective record noise. Table 17 lists the configuration
settings available for channel summing mode.
Table 17. Channel Summing Mode Programmable Settings
SNR AND DYNAMIC RANGE
P0_R107_D[3:2] : CH_SUM[2:0]
CHANNEL SUMMING MODE FOR INPUT CHANNELS
Channel summing mode is disabled
BOOST
00 (Default)
Not applicable
Output channel 1 = (input channel 1 + input channel 2) / 2
Output channel 2 = (input channel 1 + input channel 2) / 2
Output channel 3 = (input channel 3 + input channel 4) / 2
Output channel 4 = (input channel 3 + input channel 4) / 2
3-dB boost in SNR and dynamic
range
01
3-dB boost in SNR and dynamic
range
Output channel 1 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
Output channel 2 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
6-dB boost in SNR and dynamic
range
10
11
Output channel 3 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
Output channel 4 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
Reserved (do not use this setting)
Not applicable
The device additionally supports a fully programmable mixer feature that can mix the various input channels with
their custom programmable scale factor to generate the final output channels. The programmable mixer feature
is available only if CH_SUM[2:0] is set to 2'b00. The mixer function is only supported for input channel 1 to
channel 4. Figure 34 shows a block diagram that describes the mixer 1 operation to generate output channel 1.
The programmable coefficients for the mixer operation are located in the Programmable Coefficient Registers:
Page = 0x04 section. All mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format.
The value of 0x7FFFFFFF is equivalent to +1 (0-dB gain), the value 0x00000000 is equivalent to mute (zero
data), and any values in between set the mixer attenuation computed using Equation 3. If the MSB is set to '1'
then the attenuation remains the same but the signal phase is inverted.
hex2dec (value) / 231
(3)
Attenuated by
MIX1_CH1
factor
Input Channel-1
Processed Data
Attenuated by
MIX1_CH2
factor
Input Channel-2
Processed Data
Output Channel-1
Routed to Bi-Quad
Filter
+
Attenuated by
MIX1_CH3
factor
Input Channel-3
Processed Data
Attenuated by
MIX1_CH4
factor
Input Channel-4
Processed Data
Figure 34. Programmable Digital Mixer Block Diagram
A similar mixer operation is performed by mixer 2, mixer 3, and mixer 4 to generate output channel 2, channel 3,
and channel 4, respectively.
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7.3.6.7 Configurable Digital Decimation Filters
The device record channel includes a high dynamic range, built-in digital decimation filter to process the
oversampled PDM data stream from the digital microphone to generate digital data at the same Nyquist sampling
rate as the FSYNC rate. The decimation filter can be chosen from three different types, depending on the
required frequency response, group delay, and phase linearity requirements for the target application. The
selection of the decimation filter option can be done by configuring the DECI_FILT, P0_R107_D[5:4] register bits.
Table 18 shows the configuration register setting for the decimation filter mode selection for the record channel.
Table 18. Decimation Filter Mode Selection for the Record Channel
P0_R107_D[5:4] : DECI_FILT[1:0]
DECIMATION FILTER MODE SELECTION
Linear phase filters are used for the decimation
00 (default)
01
10
11
Low latency filters are used for the decimation
Ultra-low latency filters are used for the decimation
Reserved (do not use this setting)
7.3.6.7.1 Linear Phase Filters
The linear phase decimation filters are the default filters set by the device and can be used for all applications
that require a perfect linear phase with zero-phase deviation within the pass-band specification of the filter. The
filter performance specifications and various plots for all supported output sampling rates are listed in this
section.
7.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
Figure 35 and Figure 36 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 8 kHz or 7.35 kHz. Table 19 lists the specifications for a decimation filter with an
8-kHz or 7.35-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 35. Linear Phase Decimation Filter Magnitude
Response
Figure 36. Linear Phase Decimation Filter Pass-Band
Ripple
Table 19. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
MIN
–0.05
72.7
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
81.2
17.1
1/fS
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7.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
Figure 37 and Figure 38 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 16 kHz or 14.7 kHz. Table 20 lists the specifications for a decimation filter with an
16-kHz or 14.7-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 37. Linear Phase Decimation Filter Magnitude
Response
Figure 38. Linear Phase Decimation Filter Pass-Band
Ripple
Table 20. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
MIN
–0.05
73.3
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
95.0
15.7
1/fS
7.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
Figure 39 and Figure 40 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 24 kHz or 22.05 kHz. Table 21 lists the specifications for a decimation filter with an
24-kHz or 22.05-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 39. Linear Phase Decimation Filter Magnitude
Response
Figure 40. Linear Phase Decimation Filter Pass-Band
Ripple
Table 21. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
MIN
–0.05
73.0
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
96.4
16.6
1/fS
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7.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
Figure 41 and Figure 42 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 32 kHz or 29.4 kHz. Table 22 lists the specifications for a decimation filter with an
32-kHz or 29.4-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 41. Linear Phase Decimation Filter Magnitude
Response
Figure 42. Linear Phase Decimation Filter Pass-Band
Ripple
Table 22. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
MIN
–0.05
73.7
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
107.2
16.9
1/fS
7.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
Figure 43 and Figure 44 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 48 kHz or 44.1 kHz. Table 23 lists the specifications for a decimation filter with an
48-kHz or 44.1-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 43. Linear Phase Decimation Filter Magnitude
Response
Figure 44. Linear Phase Decimation Filter Pass-Band
Ripple
Table 23. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.8
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
98.1
17.1
1/fS
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7.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
Figure 45 and Figure 46 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 96 kHz or 88.2 kHz. Table 24 lists the specifications for a decimation filter with an
96-kHz or 88.2-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 45. Linear Phase Decimation Filter Magnitude
Response
Figure 46. Linear Phase Decimation Filter Pass-Band
Ripple
Table 24. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
MIN
–0.05
73.6
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
97.9
17.1
1/fS
7.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
Figure 47 and Figure 48 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 192 kHz or 176.4 kHz. Table 25 lists the specifications for a decimation filter with an
192-kHz or 176.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
0.15
0.2
Normalized Frequency (1/fS)
0.25
0.3
0.35
0.4
D001
D001
Figure 47. Linear Phase Decimation Filter Magnitude
Response
Figure 48. Linear Phase Decimation Filter Pass-Band
Ripple
Table 25. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.3 × fS
Frequency range is 0.473 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.3 × fS
MIN
–0.05
70.0
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
111.0
11.9
1/fS
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7.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
Figure 49 and Figure 50 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 384 kHz or 352.8 kHz. Table 26 lists the specifications for a decimation filter with an
384-kHz or 352.8-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
0.15
Normalized Frequency (1/fS)
0.2
0.25
0.3
D001
D001
Figure 49. Linear Phase Decimation Filter Magnitude
Response
Figure 50. Linear Phase Decimation Filter Pass-Band
Ripple
Table 26. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.212 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.212 × fS
MIN
–0.05
70.0
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
Group delay or latency
dB
108.8
7.2
1/fS
7.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
Figure 51 and Figure 52 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 768 kHz or 705.6 kHz. Table 27 lists the specifications for a decimation filter with an
768-kHz or 705.6-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
Normalized Frequency (1/fS)
0.15
0.2
D001
D001
Figure 51. Linear Phase Decimation Filter Magnitude
Response
Figure 52. Linear Phase Decimation Filter Pass-Band
Ripple
Table 27. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.113 × fS
Frequency range is 0.58 × fS to 2 × fS
Frequency range is 2 × fS onwards
MIN
–0.05
75.0
TYP
MAX
UNIT
Pass-band ripple
0.05
dB
Stop-band attenuation
dB
88.0
Group Delay or Latency Frequency range is 0 to 0.113 × fS
5.9
1/fS
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7.3.6.7.2 Low-Latency Filters
For applications where low latency with minimal phase deviation (within the audio band) is critical, the low-
latency decimation filters on the PCMD3180 can be used. The device supports these filters with a group delay of
approximately seven samples with an almost linear phase response within the 0.365 × fS frequency band. This
section provides the filter performance specifications and various plots for all supported output sampling rates for
the low-latency filters.
7.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
Figure 53 shows the magnitude response and Figure 54 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 16 kHz or 14.7 kHz. Table 28 lists the specifications for a decimation
filter with a 16-kHz or 14.7-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
Figure 54. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 53. Low-Latency Decimation Filter Magnitude
Response
Table 28. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.451 × fS
Frequency range is 0.61 × fS onwards
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
MIN
–0.05
87.3
TYP
MAX
UNIT
dB
Pass-band ripple
0.05
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.6
1/fS
–0.022
–0.21
0.022
0.25
1/fS
Degrees
38
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7.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
Figure 55 shows the magnitude response and Figure 56 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 24 kHz or 22.05 kHz. Table 29 lists the specifications for a decimation
filter with a 24-kHz or 22.05-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
Figure 56. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 55. Low-Latency Decimation Filter Magnitude
Response
Table 29. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.01
87.2
TYP
MAX
UNIT
dB
Pass-band ripple
Frequency range is 0 to 0.459 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.5
1/fS
–0.026
–0.26
0.026
0.30
1/fS
Degrees
7.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
Figure 57 shows the magnitude response and Figure 58 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 32 kHz or 29.4 kHz. Table 30 lists the specifications for a decimation
filter with a 32-kHz or 29.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
Figure 58. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 57. Low-Latency Decimation Filter Magnitude
Response
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Table 30. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
–0.04
88.3
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.457 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
8.7
1/fS
–0.026
–0.26
0.026
0.31
1/fS
Degrees
7.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
Figure 59 shows the magnitude response and Figure 60 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 48 kHz or 44.1 kHz. Table 31 lists the specifications for a decimation
filter with a 48-kHz or 44.1-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
Figure 60. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 59. Low-Latency Decimation Filter Magnitude
Response
Table 31. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.452 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
MIN
–0.015
86.4
TYP
MAX
UNIT
dB
Pass-band ripple
0.015
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.7
1/fS
–0.027
–0.25
0.027
0.30
1/fS
Degrees
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7.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
Figure 61 shows the magnitude response and Figure 62 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 96 kHz or 88.2 kHz. Table 32 lists the specifications for a decimation
filter with a 96-kHz or 88.2-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
Figure 62. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 61. Low-Latency Decimation Filter Magnitude
Response
Table 32. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Frequency range is 0 to 0.466 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
MIN
–0.04
86.3
TYP
MAX
UNIT
dB
Pass-band ripple
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.7
1/fS
–0.027
–0.26
0.027
0.30
1/fS
Degrees
7.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
Figure 63 shows the magnitude response and Figure 64 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 192 kHz or 176.4 kHz. Table 33 lists the specifications for a decimation
filter with a 192-kHz or 176.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
Figure 64. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 63. Low-Latency Decimation Filter Magnitude
Response
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Table 33. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 463 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
MIN
–0.03
85.6
TYP
MAX
UNIT
dB
0.03
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.7
1/fS
–0.027
–0.26
0.027
0.30
1/fS
Degrees
7.3.6.7.3 Ultra-Low-Latency Filters
For applications where ultra-low latency (within the audio band) is critical, the ultra-low-latency decimation filters
on the PCMD3180 can be used. The device supports these filters with a group delay of approximately four
samples with an almost linear phase response within the 0.325 × fS frequency band. This section provides the
filter performance specifications and various plots for all supported output sampling rates for the ultra-low-latency
filters.
7.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
Figure 65 shows the magnitude response and Figure 66 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 16 kHz or 14.7 kHz. Table 34 lists the specifications for a decimation
filter with a 16-kHz or 14.7-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
Figure 66. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Figure 65. Ultra-Low-Latency Decimation Filter Magnitude
Response
Table 34. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.45 × fS
MIN
–0.05
TYP
MAX
UNIT
dB
0.05
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
87.2
dB
4.3
1/fS
–0.512
–10.0
0.512
14.2
1/fS
Degrees
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7.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
Figure 67 shows the magnitude response and Figure 68 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 24 kHz or 22.05 kHz. Table 35 lists the specifications for a decimation
filter with a 24-kHz or 22.05-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
Figure 68. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Figure 67. Ultra-Low-Latency Decimation Filter Magnitude
Response
Table 35. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.46 × fS
MIN
–0.01
TYP
MAX
UNIT
dB
0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
87.1
dB
4.1
1/fS
–0.514
–10.0
0.514
14.3
1/fS
Degrees
7.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
Figure 69 shows the magnitude response and Figure 70 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 32 kHz or 29.4 kHz. Table 36 lists the specifications for a decimation
filter with an 32-kHz or 29.4-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
Figure 70. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Figure 69. Ultra-Low-Latency Decimation Filter Magnitude
Response
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Table 36. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
–0.04
88.3
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.457 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
5.2
1/fS
–0.492
–9.5
0.492
13.5
1/fS
Degrees
7.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
Figure 71 shows the magnitude response and Figure 72 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 48 kHz or 44.1 kHz. Table 37 lists the specifications for a decimation
filter with a 48-kHz or 44.1-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
Figure 72. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Figure 71. Ultra-Low-Latency Decimation Filter Magnitude
Response
Table 37. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.452 × fS
MIN
–0.015
TYP
MAX
UNIT
dB
0.015
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
86.4
dB
4.1
1/fS
–0.525
–10.3
0.525
14.5
1/fS
Degrees
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7.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
Figure 73 shows the magnitude response and Figure 74 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 96 kHz or 88.2 kHz. Table 38 lists the specifications for a decimation
filter with a 96-kHz or 88.2-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
5
10
0
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
3
2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-4
-5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
Figure 74. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Figure 73. Ultra-Low-Latency Decimation Filter Magnitude
Response
Table 38. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.466 × fS
MIN
–0.04
TYP
MAX
UNIT
dB
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.1625 × fS
Frequency range is 0 to 0.1625 × fS
Frequency range is 0 to 0.1625 × fS
86.3
dB
3.7
1/fS
–0.091
–0.86
0.091
1.30
1/fS
Degrees
7.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
Figure 75 shows the magnitude response and Figure 76 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 192 kHz or 176.4 kHz. Table 39 lists the specifications for a decimation
filter with a 192-kHz or 176.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
5
10
0
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
3
2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-4
-5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
Figure 76. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Figure 75. Ultra-Low-Latency Decimation Filter Magnitude
Response
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Table 39. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.463 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.085 × fS
Frequency range is 0 to 0.085 × fS
Frequency range is 0 to 0.085 × fS
MIN
–0.03
85.6
TYP
MAX
UNIT
dB
0.03
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
3.7
1/fS
–0.024
–0.12
0.024
0.18
1/fS
Degrees
7.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
Figure 77 shows the magnitude response and Figure 78 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 384 kHz or 352.8 kHz. Table 40 lists the specifications for a decimation
filter with a 384-kHz or 352.8-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
2
10
0
1.6
1.2
0.8
0.4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.4
-0.8
-1.2
-1.6
-2
Pass-Band Ripple
Phase Deviation
0
0.05
0.1 0.15
Normalized Frequency (1/fS)
0.2
0.25
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
Figure 78. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 77. Ultra-Low-Latency Decimation Filter Magnitude
Response
Table 40. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.1 × fS
MIN
–0.04
TYP
MAX
UNIT
dB
0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.56 × fS onwards
Frequency range is 0 to 0.157 × fS
Frequency range is 0 to 0.157 × fS
Frequency range is 0 to 0.157 × fS
70.1
dB
4.1
1/fS
–0.18
–0.85
0.18
2.07
1/fS
Degrees
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7.3.7 Interrupts, Status, and Digital I/O Pin Multiplexing
Certain events in the device may require host processor intervention and can be used to trigger interrupts to the
host processor. One such event is an audio serial interface (ASI) bus error. The device powers down the record
channels if any faults are detected with the ASI bus error clocks, such as:
•
•
•
Invalid FSYNC frequency
Invalid SBCLK to FSYNC ratio
Long pauses of the SBCLK or FSYNC clocks
When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After
all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record
channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the
clock error interrupt mask register bit INT_MASK0[7], P0_R51_D7 is set low. The clock fault is also available for
readback in the latched fault status register bit INT_LTCH0, P0_R54, which is a read-only register. Reading the
latched fault status register, INT_LTCH0, clears all latched fault status. The device can be additionally configured
to route the internal IRQ interrupt signal on the GPIO1 or GPOx pins and also can be configured as open-drain
outputs so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices.
The IRQ interrupt signal can either be configured as active low or active high polarity by setting the INT_POL,
P0_R50_D7 register bit. This signal can also be configured as a single pulse or a series of pulses by
programming the INT_EVENT[1:0], P0_R50_D[6:5] register bits. If the interrupts are configured as a series of
pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine
the cause of the interrupt.
The device also supports read-only live-status registers to determine if the channels are powered up or down and
if the device is in sleep mode or not. These status registers are located in P0_R118, DEV_STS0 and P0_R119,
DEV_STS1.
The device has a multifunctional GPIO1 pin that can be configured for a desired specific function. Additionally,
PDMINx_GPIx and PDMCLKx_GPOx can be repurposed as multifunction pins GPIx and GPOx respectively, as
required for system application. The maximum number of GPO pins supported by the device is four and the
maximum number of GPI pins are four. Table 41 shows all possible allocations of these multifunctional pins for
the various features.
Table 41. Multifunction Pin Assignments
ROW
—
Pin Function(1)
GPIO1
GPO1
GPO2
GPO3
GPO4
GPI1
GPI2
GPI3
GPI4
—
—
GPIO1_CFG GPO1_CFG GPO2_CFG GPO3_CFG GPO4_CFG
GPI1_CFG
GPI2_CFG
GPI3_CFG
GPI4_CFG
—
P0_R33[7:4] P0_R34[7:4] P0_R35[7:4] P0_R36[7:4] P0_R37[7:4] P0_R43[6:4] P0_R43[2:0] P0_R44[6:4] P0_R44[2:0]
A
Pin disabled
S(2)
S (default)
S (default)
S (default)
S (default)
S (default)
NS(3)
NS
S (default)
NS
S (default)
NS
S (default)
NS
General-purpose output
(GPO)
B
C
D
E
F
S
S
S
S
S
S
S
S
S
Interrupt output (IRQ)
S (default)
NS
NS
NS
Secondary ASI output
(SDOUT2)(4)
S
S
S
S
S
S
S
NS
NS
NS
NS
PDM clock output (PDMCLK)
S
S
S
S
NS
NS
NS
NS
MiCBIAS on/off input
(BIASEN)
NS
NS
NS
NS
NS
NS
NS
NS
G
H
I
General-purpose input (GPI)
Master clock input (MCLK)
ASI daisy-chain input (SDIN)
PDM data input 1 (PDMDIN1)
PDM data input 2 (PDMDIN2)
PDM data input 3 (PDMDIN3)
PDM data input 4 (PDMDIN4)
S
S
S
S
S
S
S
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
J
K
L
M
(1) Only the GPIO1 pin is with reference to the IOVDD supply, the other GPOx and GPIx pins are with reference to the AVDD supply and
their primary pin functions are for the PDMCLK or PDMDIN function.
(2) S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
(3) NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
(4) For the high-speed ASI output, GPIO1 must be used instead of GPOx for the secondary ASI output. GPOx can be used only if the bus
speed requirement is less than 6.144 MHz.
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Each GPOx or GPIOx pin can be independently set for the desired drive configurations setting using the
GPOx_DRV[3:0] or GPIO1_DRV[3:0] register bits. Table 42 lists the drive configuration settings.
Table 42. GPIO or GPOx Pins Drive Configuration Settings
P0_R33_D[3:0] : GPIO1_DRV[3:0]
GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1
The GPIO1 pin is set to high impedance (floated)
000
001
The GPIO1 pin is set to be driven active low or active high
The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)
The GPIO1 pin is set to be driven active low or Hi-Z (floated)
The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high
The GPIO1 pin is set to be driven Hi-Z (floated) or active high
Reserved (do not use these settings)
010 (default)
011
100
101
110 and 111
Similarly, the GPO1 to GPO4 pins can be configured using the GPO1_DRV(P0_R34) to GPO4_DRV(P0_R37)
register bits, respectively.
When configured as a general-purpose output (GPO), the GPIO1 or GPOx pin values can be driven by writing
the GPIO_VAL or GPOx_VAL, P0_R41 registers. The GPIO_MON, P0_R42 register can be used to readback
the status of the GPIO1 pin when configured as a general-purpose input (GPI). Similarly, the GPI_MON, P0_R47
register can be used to readback the status of the GPIx pins when configured as a general-purpose input (GPI).
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7.4 Device Functional Modes
7.4.1 Hardware Shutdown
The device enters hardware shutdown mode when the SHDNZ pin is asserted low or the AVDD supply voltage is
not applied to the device. In hardware shutdown mode, the device consumes the minimum quiescent current
from the AVDD supply. All configuration registers and programmable coefficients lose their value in this mode,
and I2C or SPI communication to the device is not supported.
If the SHDNZ pin is asserted low when the device is in active mode, the device ramps down volume on the
record data, powers down the analog and digital blocks, and puts the device into hardware shutdown mode in 25
ms (typical). The device can also be immediately put into hardware shutdown mode from active mode if the
SHDNZ_CFG[1:0], P0_R5_D[3:2], register bits are set to 2'b00. After the SHDNZ pin is asserted low, and after
the device enters hardware shutdown mode, keep the SHDNZ pin low for at least 1 ms before releasing SHDNZ
for further device operation.
Assert the SHDNZ pin high only when the IOVDD supply settles to a steady voltage level. When the SHDNZ pin
goes high, the device sets all configuration registers and programmable coefficients to their default values, and
then enters sleep mode.
7.4.2 Sleep Mode or Software Shutdown
In sleep mode or software shutdown mode, the device consumes very low quiescent current from the AVDD
supply and, at the same time, allows the I2C or SPI communication to wake the device for active operation.
The device can also enter sleep mode when the host device sets the SLEEP_ENZ, P0_R2_D0 bit to 1'b0. If the
SLEEP_ENZ bit is asserted low when the device is in active mode, the device ramps down the volume on the
record data, powers down the analog and digital blocks, and enters sleep mode. However, the device still
continues to retain the last programmed value of the device configuration registers and programmable
coefficients.
In sleep mode, do not perform any I2C or SPI transactions, except for exiting sleep mode in order to enter active
mode. After entering sleep mode, wait at least 10 ms before starting I2C or SPI transactions to exit sleep mode.
While exiting sleep mode, the host device must configure the PCMD3180 to use either an external 1.8-V AREG
supply (default setting) or an on-chip-regulator-generated AREG supply. To configure the AREG supply, write to
AREG_SELECT, bit D7 in the same P0_R2 register.
7.4.3 Active Mode
If the host device exits sleep mode by setting the SLEEP_ENZ bit to 1'b1, the device enters active mode. In
active mode, I2C or SPI transactions can be done to configure and power-up the device for active operation.
After entering active mode, wait at least 1 ms before starting any I2C or SPI transactions in order to allow the
device to complete the internal wake-up sequence.
After configuring all other registers for the target application and system settings, configure the input and output
channel enable registers, P0_R115 (IN_CH_EN) and P0_R116 (ASI_OUT_CH_EN), respectively. Lastly,
configure the device power-up register, P0_R117 (PWR_CFG). All the programmable coefficient values must be
written before powering up the respective channel.
In active mode, the power-up and power-down status of various blocks is monitored by reading the read-only
device status bits located in the P0_R117 (DEV_STS0) and P0_R118 (DEV_STS1) registers.
7.4.4 Software Reset
A software reset can be done any time by asserting the SW_RESET bit, P0_R1_D0, which is a self-clearing bit.
This software reset immediately shuts down the device, and restores all device configuration registers and
programmable coefficients to their default values.
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7.5 Programming
The device contains configuration registers and programmable coefficients that can be set to the desired values
for a specific system and application use. These registers are called device control registers and are each eight
bits in width, mapped using a page scheme.
Each page contains 128 configuration registers. All device configuration registers are stored in page 0, which is
the default page setting at power up and after a software reset. All programmable coefficient registers are located
in page 2, page 3, and page 4. The current page of the device can be switched to a new desired page by using
the PAGE[7:0] bits located in register 0 of every page.
7.5.1 Control Serial Interfaces
The device control registers can be accessed using either I2C or SPI communication to the device.
By monitoring the SDA_SSZ, SCL_MOSI, ADDR0_SCLK, and ADDR1_MISO device pins, which are the
multiplexed pins for the I2C or SPI Interface, the device automatically detects whether the host device is using
I2C or SPI communication to configure the device. For a given end application, the host device must always use
either the I2C or SPI interface, but not both, to configure the device.
7.5.1.1 I2C Control Interface
The device supports the I2C control protocol as a slave device, and is capable of operating in standard mode,
fast mode, and fast mode plus. The I2C control protocol requires a 7-bit slave address. The five most significant
bits (MSBs) of the slave address are fixed at 10011 and cannot be changed. The two least significant bits (LSBs)
are programmable and are controlled by the ADDR0_SCLK and ADDR1_MISO pins. These two pins must
always be either pulled to VSS or IOVDD. If the I2C_BRDCAST_EN (P0_R2_D2) bit is set to 1'b1, then the I2C
slave address is fixed to 1001100 in order to allow simultaneous I2C broadcast communication to all PCMD3180
devices in the system. Table 43 lists the four possible device addresses resulting from this configuration.
Table 43. I2C Slave Address Settings
ADDR1_MISO
ADDR0_SCLK
I2C_BRDCAST_EN (P0_R2_D2)
I2C SLAVE ADDRESS
1001 100
0
0
1
1
X
0
1
0
1
X
0 (default)
0 (default)
0 (default)
0 (default)
1
1001 101
1001 110
1001 111
1001 100
7.5.1.1.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system using serial data transmission. The address and data 8-bit bytes are transferred MSB first. In addition,
each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer
operation begins with the master device driving a start condition on the bus and ends with the master device
driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is at logic high
to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition
indicates a stop. Normal data-bit transitions must occur within the low time of the clock period.
The master device drives a start condition followed by the 7-bit slave address and the read/write (R/W) bit to
open communication with another device and then waits for an acknowledgment condition. The slave device
holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the master
device transmits the next byte of the sequence. Each slave device is addressed by a unique 7-bit slave address
plus the R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-
AND connection.
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There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master device generates a stop condition to release the bus. Figure 79 shows a generic data
transfer sequence.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
Figure 79. Typical I2C Sequence
In the system, use external pullup resistors for the SDA and SCL signals to set the logic high level for the bus.
The SDA and SCL voltages must not exceed the device supply voltage, IOVDD.
7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
The device I2C interface supports both single-byte and multiple-byte read/write operations for all registers. During
multiple-byte read operations, the device responds with data, a byte at a time, starting at the register assigned,
as long as the master device continues to respond with acknowledges.
The device supports sequential I2C addressing. For write transactions, if a register is issued followed by data for
that register and all the remaining registers that follow, a sequential I2C write transaction takes place. For I2C
sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines how many registers are written.
7.5.1.1.2.1 I2C Single-Byte Write
As shown in Figure 80, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C
slave address and the read/write bit, the device responds with an acknowledge bit (ACK). Next, the master
device transmits the register byte corresponding to the device internal register address being accessed. After
receiving the register byte, the device again responds with an acknowledge bit (ACK). Then, the master transmits
the byte of data to be written to the specified register. When finished, the slave device responds with an
acknowledge bit (ACK). Finally, the master device transmits a stop condition to complete the single-byte data
write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5 A4
A3 A2 A1 A0
Stop
2
I C Device Address and
Read/Write Bit
Register
Data Byte
Condition
Figure 80. I2C Single-Byte Write Transfer
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7.5.1.1.2.2 I2C Multiple-Byte Write
As shown in Figure 81, a multiple-byte data write transfer is identical to a single-byte data write transfer except
that multiple data bytes are transmitted by the master device to the slave device. After receiving each data byte,
the device responds with an acknowledge bit (ACK). Finally, the master device transmits a stop condition after
the last data-byte write transfer.
Register
Figure 81. I2C Multiple-Byte Write Transfer
7.5.1.1.2.3 I2C Single-Byte Read
As shown in Figure 82, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C slave address and the read/write bit. For the data read transfer, both a write
followed by a read are done. Initially, a write is done to transfer the address byte of the internal register address
to be read. As a result, the read/write bit is set to 0.
After receiving the slave address and the read/write bit, the device responds with an acknowledge bit (ACK). The
master device then sends the internal register address byte, after which the device issues an acknowledge bit
(ACK). The master device transmits another start condition followed by the slave address and the read/write bit
again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the device transmits the data byte
from the register address being read. After receiving the data byte, the master device transmits a not-
acknowledge (NACK) followed by a stop condition to complete the single-byte data read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
2
2
Stop
Condition
I C Device Address and
Read/Write Bit
Register
I C Device Address and
Read/Write Bit
Data Byte
Figure 82. I2C Single-Byte Read Transfer
7.5.1.1.2.4 I2C Multiple-Byte Read
As shown in Figure 83, a multiple-byte data read transfer is identical to a single-byte data read transfer except
that multiple data bytes are transmitted by the device to the master device. With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte. After receiving the last
data byte, the master device transmits a not-acknowledge (NACK) followed by a stop condition to complete the
data read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
2
2
Register
Stop
Condition
I C Device Address and
Read/Write Bit
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Figure 83. I2C Multiple-Byte Read Transfer
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7.5.1.2 SPI Control Interface
The general SPI protocol allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions by taking the slave-select pin SSZ from high
to low. The SPI slave devices (such as the PCMD3180) depend on a master to start and synchronize
transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins
shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). When the byte
shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.
The PCMD3180 supports a standard SPI control protocol with a clock polarity setting of 0 (typical microprocessor
SPI control bit CPOL = 0) and a clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). The
SSZ pin can remain low between transmissions; however, the device only interprets the first eight bits
transmitted after the falling edge of SSZ as a command byte, and the next eight bits as a data byte only if writing
to a register. The device is entirely controlled by registers. Reading and writing these registers is accomplished
by an 8-bit command sent to the MOSI pin prior to the data for that register. Table 44 shows the command
structure. The first seven bits specify the address of the register that is being written or read, from 0 to 127
(decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the serial bus.
In the case of a register write, set the R/W bit to 0. A second byte of data is sent to the MOSI pin and contains
the data to be written to the register. A register read is accomplished in a similar fashion. The 8-bit command
word sends the 7-bit register address, followed by the R/W bit equal to 1 to signify a register read. The 8-bit
register data is then clocked out of the device on the MISO pin during the second eight SCLK clocks in the
frame. The device supports sequential SPI addressing for a multiple-byte data write/read transfer until the SSZ
pin is pulled high. A multiple-byte data write or read transfer is identical to a single-byte data write or read
transfer, respectively, until all data byte transfers complete. The host device must keep the SSZ pin low during all
data byte transfers. Figure 84 shows the single-byte write transfer and Figure 85 illustrates the single-byte read
transfer.
Table 44. SPI Command Word
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDR(6)
ADDR(5)
ADDR(4)
ADDR(3)
ADDR(2)
ADDR(1)
ADDR(0)
R/WZ
SS
SCLK
MOSI
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
D(7)
D(6)
D(0)
7-bit Register Address
Write
8-bit Register Data
Hi-Z
Hi-Z
MISO
Figure 84. SPI Single-Byte Write Transfer
SS
SCLK
MOSI
Hi-Z
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
Don’t Care
7-bit Register Address
Read
8-bit Register Data
Hi-Z
MISO
D(7)
D(6)
D(0)
Figure 85. SPI Single-Byte Read Transfer
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7.6 Register Maps
This section describes the control registers for the device in detail. All these registers are eight bits in width and
allocated to device configuration and programmable coefficients settings. These registers are mapped internally
using a page scheme that can be controlled using either I2C or SPI communication to the device. Each page
contains 128 bytes of registers. All device configuration registers are stored in page 0, which is the default page
setting at power up (and after a software reset). All programmable coefficient registers are located in page 2,
page 3, and page 4. The device current page can be switch to a new desired page by using the PAGE[7:0] bits
located in register 0 of every page.
Do not read from or write to reserved pages or reserved registers. Write only default values for the reserved bits
in the valid registers.
The procedure for register access across pages is:
•
•
•
•
•
Select page N (write data N to register 0 regardless of the current page number)
Read or write data from or to valid registers in page N
Select the new page M (write data M to register 0 regardless of the current page number)
Read or write data from or to valid registers in page M
Repeat as needed
7.6.1 Device Configuration Registers
This section describes the device configuration registers for page 0.
7.6.1.1 Register Summary Table Page=0x00
ADDRESS
0x00
0x01
0x02
0x05
0x07
0x08
0x09
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x29
0x2A
0x2B
0x2C
REGISTER
PAGE_CFG
DESCRIPTION
SECTION
Device page register
Software reset register
Sleep mode register
PAGE_CFG Register (P0_R0)
SW_RESET Register (P0_R1)
SLEEP_CFG Register (P0_R2)
SHDN_CFG Register (P0_R5)
ASI_CFG0 Register (P0_R7)
ASI_CFG1 Register (P0_R8)
ASI_CFG2 Register (P0_R9)
ASI_CH1 Register (P0_R11)
ASI_CH2 Register (P0_R12)
ASI_CH3 Register (P0_R13)
ASI_CH4 Register (P0_R14)
ASI_CH5 Register (P0_R15)
ASI_CH6 Register (P0_R16)
ASI_CH7 Register (P0_R17)
ASI_CH8 Register (P0_R18)
MST_CFG0 Register (P0_R19)
MST_CFG1 Register (P0_R20)
ASI_STS Register (P0_R21)
CLK_SRC Register (P0_R22)
PDMCLK_CFG Register (P0_R31)
PDMIN_CFG Register (P0_R32)
GPIO_CFG0 Register (P0_R33)
GPO_CFG0 Register (P0_R34)
GPO_CFG1 Register (P0_R35)
GPO_CFG2 Register (P0_R36)
GPO_CFG3 Register (P0_R37)
GPO_VAL Register (P0_R41)
GPIO_MON Register (P0_R42)
GPI_CFG0 Register (P0_R43)
GPI_CFG1 Register (P0_R44)
SW_RESET
SLEEP_CFG
SHDN_CFG
ASI_CFG0
ASI_CFG1
ASI_CFG2
ASI_CH1
Shutdown configuration register
ASI configuration register 0
ASI configuration register 1
ASI configuration register 2
Channel 1 ASI slot configuration register
Channel 2 ASI slot configuration register
Channel 3 ASI slot configuration register
Channel 4 ASI slot configuration register
Channel 5 ASI slot configuration register
Channel 6 ASI slot configuration register
Channel 7 ASI slot configuration register
Channel 8 ASI slot configuration register
ASI master mode configuration register 0
ASI master mode configuration register 1
ASI bus clock monitor status register
Clock source configuration register 0
PDM clock generation configuration register
PDM DINx sampling edge register
GPIO configuration register 0
ASI_CH2
ASI_CH3
ASI_CH4
ASI_CH5
ASI_CH6
ASI_CH7
ASI_CH8
MST_CFG0
MST_CFG1
ASI_STS
CLK_SRC
PDMCLK_CFG
PDMIN_CFG
GPIO_CFG0
GPO_CFG0
GPO_CFG1
GPO_CFG2
GPO_CFG3
GPO_VAL
GPIO_MON
GPI_CFG0
GPI_CFG1
GPO configuration register 0
GPO configuration register 1
GPO configuration register 2
GPO configuration register 3
GPIO, GPO output value register
GPIO monitor value register
GPI configuration register 0
GPI configuration register 1
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Register Maps (continued)
0x2F
0x32
0x33
0x36
0x3B
0x3C
0x3E
0x3F
0x40
0x41
0x43
0x44
0x45
0x46
0x48
0x49
0x4A
0x4B
0x4D
0x4E
0x4F
0x50
0x52
0x53
0x54
0x55
0x57
0x58
0x59
0x5A
0x5C
0x5D
0x5E
0x5F
0x61
0x62
0x63
0x6B
0x6C
0x73
0x74
0x75
0x76
0x77
0x7E
GPI_MON
GPI monitor value register
GPI_MON Register (P0_R47)
INT_CFG
Interrupt configuration register
INT_CFG Register (P0_R50)
INT_MASK0 Register (P0_R51)
INT_LTCH0 Register (P0_R54)
BIAS_CFG Register (P0_R59)
CH1_CFG0 Register (P0_R60)
CH1_CFG2 Register (P0_R62)
CH1_CFG3 Register (P0_R63)
CH1_CFG4 Register (P0_R64)
CH2_CFG0 Register (P0_R65)
CH2_CFG2 Register (P0_R67)
CH2_CFG3 Register (P0_R68)
CH2_CFG4 Register (P0_R69)
CH3_CFG0 Register (P0_R70)
CH3_CFG2 Register (P0_R72)
CH3_CFG3 Register (P0_R73)
CH3_CFG4 Register (P0_R74)
CH4_CFG0 Register (P0_R75)
CH4_CFG2 Register (P0_R77)
CH4_CFG3 Register (P0_R78)
CH4_CFG4 Register (P0_R79)
CH5_CFG0 Register (P0_R80)
CH5_CFG2 Register (P0_R82)
CH5_CFG3 Register (P0_R83)
CH5_CFG4 Register (P0_R84)
CH6_CFG0 Register (P0_R85)
CH6_CFG2 Register (P0_R87)
CH6_CFG3 Register (P0_R88)
CH6_CFG4 Register (P0_R89)
CH7_CFG0 Register (P0_R90)
CH7_CFG2 Register (P0_R92)
CH7_CFG3 Register (P0_R93)
CH7_CFG4 Register (P0_R94)
CH8_CFG0 Register (P0_R95)
CH8_CFG2 Register (P0_R97)
CH8_CFG3 Register (P0_R98)
CH8_CFG4 Register (P0_R99)
DSP_CFG0 Register (P0_R107)
DSP_CFG1 Register (P0_R108)
IN_CH_EN Register (P0_R115)
ASI_OUT_CH_EN Register (P0_R116)
PWR_CFG Register (P0_R117)
DEV_STS0 Register (P0_R118)
DEV_STS1 Register (P0_R119)
I2C_CKSUM Register (P0_R126)
INT_MASK0
INT_LTCH0
BIAS_CFG
CH1_CFG0
CH1_CFG2
CH1_CFG3
CH1_CFG4
CH2_CFG0
CH2_CFG2
CH2_CFG3
CH2_CFG4
CH3_CFG0
CH3_CFG2
CH3_CFG3
CH3_CFG4
CH4_CFG0
CH4_CFG2
CH4_CFG3
CH4_CFG4
CH5_CFG0
CH5_CFG2
CH5_CFG3
CH5_CFG4
CH6_CFG0
CH6_CFG2
CH6_CFG3
CH6_CFG4
CH7_CFG0
CH7_CFG2
CH7_CFG3
CH7_CFG4
CH8_CFG0
CH8_CFG2
CH8_CFG3
CH8_CFG4
DSP_CFG0
DSP_CFG1
IN_CH_EN
ASI_OUT_CH_EN
PWR_CFG
DEV_STS0
DEV_STS1
I2C_CKSUM
Interrupt mask register 0
Latched interrupt readback register 0
MICBIAS and VREF configuration register
Channel 1 configuration register 0
Channel 1 configuration register 2
Channel 1 configuration register 3
Channel 1 configuration register 4
Channel 2 configuration register 0
Channel 2 configuration register 2
Channel 2 configuration register 3
Channel 2 configuration register 4
Channel 3 configuration register 0
Channel 3 configuration register 2
Channel 3 configuration register 3
Channel 3 configuration register 4
Channel 4 configuration register 0
Channel 4 configuration register 2
Channel 4 configuration register 3
Channel 4 configuration register 4
Channel 5 configuration register 0
Channel 5 configuration register 2
Channel 5 configuration register 3
Channel 5 configuration register 4
Channel 6 configuration register 0
Channel 6 configuration register 2
Channel 6 configuration register 3
Channel 6 configuration register 4
Channel 7 configuration register 0
Channel 7 configuration register 2
Channel 7 configuration register 3
Channel 7 configuration register 4
Channel 8 configuration register 0
Channel 8 configuration register 2
Channel 8 configuration register 3
Channel 8 configuration register 4
DSP configuration register 0
DSP configuration register 1
Input channel enable configuration register
ASI output channel enable configuration register
Power up configuration register
Device status value register 0
Device status value register 1
I2C checksum register
Table 45 lists the access codes used for the PCMD3180 registers.
Table 45. PCMD3180 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
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Table 45. PCMD3180 Access Type Codes (continued)
Access Type
Code
Description
R-W
R/W
Read or write
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
7.6.1.2 Register Descriptions
7.6.1.2.1 PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
The device memory map is divided into pages. This register sets the page.
Figure 86. PAGE_CFG Register
7
6
5
4
3
2
1
0
PAGE[7:0]
R/W-0h
Table 46. PAGE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PAGE[7:0]
R/W
0h
These bits set the device page.
0d = Page 0
1d = Page 1
...
255d = Page 255
7.6.1.2.2 SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
This register is the software reset register. Asserting a software reset places all register values in their default
power-on-reset (POR) state.
Figure 87. SW_RESET Register
7
6
5
4
3
2
1
0
Reserved
R-0h
SW_RESET
R/W-0h
Table 47. SW_RESET Register Field Descriptions
Bit
7-1
0
Field
Type
R
Reset
0h
Description
Reserved
SW_RESET
Reserved
R/W
0h
Software reset. This bit is self clearing.
0d = Do not reset
1d = Reset
7.6.1.2.3 SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
This register configures the regulator, VREF quick charge, I2C broadcast and sleep mode.
Figure 88. SLEEP_CFG Register
7
6
5
4
3
2
1
0
AREG_SELEC
T
I2C_BRDCAST
_EN
Reserved
R/W-0h
VREF_QCHG[1:0]
R/W-0h
Reserved
R-0h
SLEEP_ENZ
R/W-0h
R/W-0h
R/W-0h
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Table 48. SLEEP_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
AREG_SELECT
R/W
0h
The analog supply selection from either the internal regulator supply or the
external AREG supply.
0d = External 1.8-V AREG supply (use this setting when AVDD is 1.8 V and
short AREG with AVDD)
1d = Internally generated 1.8-V AREG supply using an on-chip regulator
(use this setting when AVDD is 3.3 V)
6-5
4-3
Reserved
R/W
R/W
0h
0h
Reserved
VREF_QCHG[1:0]
The duration of the quick-charge for the VREF external capacitor is set using
an internal series impedance of 200 ohm.
0d = VREF quick-charge duration of 3.5 ms (typical)
1d = VREF quick-charge duration of 10 ms (typical)
2d = VREF quick-charge duration of 50 ms (typical)
3d = VREF quick-charge duration of 100 ms (typical)
2
I2C_BRDCAST_EN
R/W
0h
I2C broadcast addressing setting.
0d = I2C broadcast mode disabled; the I2C slave address is determined
based on the ADDR pins
1d = I2C broadcast mode enabled; the I2C slave address is fixed at 1001
100
1
0
Reserved
R
0h
0h
Reserved
SLEEP_ENZ
R/W
Sleep mode setting.
0d = Device is in sleep mode
1d = Device is not in sleep mode
7.6.1.2.4 SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
This register configures the device shutdown
Figure 89. SHDN_CFG Register
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R/W-0h
SHDNZ_CFG[1:0]
R/W-1h
DREG_KA_TIME[1:0]
R/W-1h
Table 49. SHDN_CFG Register Field Descriptions
Bit
7-6
5-4
3-2
Field
Type
R
Reset
0h
Description
Reserved
Reserved
Reserved
R/W
R/W
0h
Reserved
SHDNZ_CFG[1:0]
1h
Shutdown configuration.
0d = DREG is powered down immediately after SHDNZ asserts
1d = DREG remains active to enable a clean shut down until a time-out is
reached; after the time-out period, DREG is forced to power off
2d = DREG remains active until the device cleanly shuts down
3d = Reserved
1-0
DREG_KA_TIME[1:0]
R/W
1h
These bits set how long DREG remains active after SHDNZ asserts.
0d = DREG remains active for 30 ms (typical)
1d = DREG remains active for 25 ms (typical)
2d = DREG remains active for 10 ms (typical)
3d = DREG remains active for 5 ms (typical)
7.6.1.2.5 ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
This register is the ASI configuration register 0.
Figure 90. ASI_CFG0 Register
7
6
5
4
3
2
1
0
ASI_FORMAT[1:0]
R/W-0h
ASI_WLEN[1:0]
R/W-3h
FSYNC_POL
R/W-0h
BCLK_POL
R/W-0h
TX_EDGE
R/W-0h
TX_FILL
R/W-0h
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Table 50. ASI_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
ASI_FORMAT[1:0]
R/W
0h
ASI protocol format.
0d = TDM mode
1d = I2S mode
2d = LJ (left-justified) mode
3d = Reserved
5-4
ASI_WLEN[1:0]
R/W
3h
ASI word or slot length.
0d = 16 bits
1d = 20 bits
2d = 24 bits
3d = 32 bits
3
2
1
FSYNC_POL
BCLK_POL
TX_EDGE
R/W
R/W
R/W
0h
0h
0h
ASI FSYNC polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
ASI BCLK polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
ASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in bit 2
(BCLK_POL)
1d = Inverted following edge (half cycle delay) with respect to the default
edge setting
0
TX_FILL
R/W
0h
ASI data output (on the primary and secondary data pin) for any unused
cycles
0d = Always transmit 0 for unused cycles
1d = Always use Hi-Z for unused cycles
7.6.1.2.6 ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
This register is the ASI configuration register 1.
Figure 91. ASI_CFG1 Register
7
6
5
4
3
2
1
0
TX_LSB
R/W-0h
TX_KEEPER[1:0]
R/W-0h
TX_OFFSET[4:0]
R/W-0h
Table 51. ASI_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TX_LSB
R/W
0h
ASI data output (on the primary and secondary data pin) for LSB
transmissions.
0d = Transmit the LSB for a full cycle
1d = Transmit the LSB for the first half cycle and Hi-Z for the second half
cycle
6-5
4-0
TX_KEEPER[1:0]
R/W
R/W
0h
0h
ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled
1d = Bus keeper is always enabled
2d = Bus keeper is enabled during LSB transmissions only for one cycle
3d = Bus keeper is enabled during LSB transmissions only for one and half
cycles
TX_OFFSET[4:0]
ASI data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left
and right slot 0) offset of one BCLK cycle with respect to standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left
and right slot 0) offset of two BCLK cycles with respect to standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is
the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left
and right slot 0) offset of 31 BCLK cycles with respect to standard protocol
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7.6.1.2.7 ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
This register is the ASI configuration register 2.
Figure 92. ASI_CFG2 Register
7
6
5
4
3
2
1
0
ASI_ERR_RCO
V
ASI_DAISY
R/W-0h
Reserved
R-0h
ASI_ERR
R/W-0h
Reserved
R-0h
R/W-0h
Table 52. ASI_CFG2 Register Field Descriptions
Bit
Field
ASI_DAISY
Type
Reset
Description
7
R/W
0h
ASI daisy chain connection.
0d = All devices are connected in the common ASI bus
1d = All devices are daisy-chained for the ASI bus
6
5
Reserved
ASI_ERR
R
0h
0h
Reserved
R/W
ASI bus error detection.
0d = Enable bus error detection
1d = Disable bus error detection
4
ASI_ERR_RCOV
Reserved
R/W
R
0h
0h
ASI bus error auto resume.
0d = Enable auto resume after bus error recovery
1d = Disable auto resume after bus error recovery and remain powered
down until the host configures the device
3-0
Reserved
7.6.1.2.8 ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
This register is the ASI slot configuration register for channel 1.
Figure 93. ASI_CH1 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH1_OUTPUT
R/W-0h
CH1_SLOT[5:0]
R/W-0h
Table 53. ASI_CH1 Register Field Descriptions
Bit
7
Field
Reserved
Type
R
Reset
0h
Description
Reserved
6
CH1_OUTPUT
R/W
0h
Channel 1 output line.
0d = Channel 1 output is on the ASI primary output pin (SDOUT)
0d = Channel 1 output is on the ASI secondary output pin (GPIO1 or GPOx)
5-0
CH1_SLOT[5:0]
R/W
0h
Channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
7.6.1.2.9 ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
This register is the ASI slot configuration register for channel 2.
Figure 94. ASI_CH2 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH2_OUTPUT
R/W-0h
CH2_SLOT[5:0]
R/W-1h
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Table 54. ASI_CH2 Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
CH2_OUTPUT
Reserved
6
R/W
0h
Channel 2 output line.
0d = Channel 2 output is on the ASI primary output pin (SDOUT)
0d = Channel 2 output is on the ASI secondary output pin (GPIO1 or GPOx)
5-0
CH2_SLOT[5:0]
R/W
1h
Channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
7.6.1.2.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
This register is the ASI slot configuration register for channel 3.
Figure 95. ASI_CH3 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH3_OUTPUT
R/W-0h
CH3_SLOT[5:0]
R/W-2h
Table 55. ASI_CH3 Register Field Descriptions
Bit
7
Field
Reserved
Type
R
Reset
0h
Description
Reserved
6
CH3_OUTPUT
R/W
0h
Channel 3 output line.
0d = Channel 3 output is on the ASI primary output pin (SDOUT)
0d = Channel 3 output is on the ASI secondary output pin (GPIO1 or GPOx)
5-0
CH3_SLOT[5:0]
R/W
2h
Channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
7.6.1.2.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
This register is the ASI slot configuration register for channel 4.
Figure 96. ASI_CH4 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH4_OUTPUT
R/W-0h
CH4_SLOT[5:0]
R/W-3h
Table 56. ASI_CH4 Register Field Descriptions
Bit
7
Field
Reserved
Type
R
Reset
0h
Description
Reserved
6
CH4_OUTPUT
R/W
0h
Channel 4 output line.
0d = Channel 4 output is on the ASI primary output pin (SDOUT)
0d = Channel 4 output is on the ASI secondary output pin (GPIO1 or GPOx)
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Table 56. ASI_CH4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
CH4_SLOT[5:0]
R/W
3h
Channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
7.6.1.2.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
This register is the ASI slot configuration register for channel 5.
Figure 97. ASI_CH5 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH5_OUTPUT
R/W-0h
CH5_SLOT[5:0]
R/W-4h
Table 57. ASI_CH5 Register Field Descriptions
Bit
7
Field
Reserved
Type
R
Reset
0h
Description
Reserved
6
CH5_OUTPUT
R/W
0h
Channel 5 output line.
0d = Channel 5 output is on the ASI primary output pin (SDOUT)
0d = Channel 5 output is on the ASI secondary output pin (GPIO1 or GPOx)
5-0
CH5_SLOT[5:0]
R/W
4h
Channel 5 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
7.6.1.2.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
This register is the ASI slot configuration register for channel 6.
Figure 98. ASI_CH6 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH6_OUTPUT
R/W-0h
CH6_SLOT[5:0]
R/W-5h
Table 58. ASI_CH6 Register Field Descriptions
Bit
7
Field
Reserved
CH6_OUTPUT
Type
R
Reset
0h
Description
Reserved
6
R/W
0h
Channel 6 output line.
0d = Channel 6 output is on the ASI primary output pin (SDOUT)
0d = Channel 6 output is on the ASI secondary output pin (GPIO1 or GPOx)
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Table 58. ASI_CH6 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
CH6_SLOT[5:0]
R/W
5h
Channel 6 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
7.6.1.2.14 ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
This register is the ASI slot configuration register for channel 7.
Figure 99. ASI_CH7 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH7_OUTPUT
R/W-0h
CH7_SLOT[5:0]
R/W-6h
Table 59. ASI_CH7 Register Field Descriptions
Bit
7
Field
Reserved
Type
R
Reset
0h
Description
Reserved
6
CH7_OUTPUT
R/W
0h
Channel 7 output line.
0d = Channel 7 output is on the ASI primary output pin (SDOUT)
0d = Channel 7 output is on the ASI secondary output pin (GPIO1 or GPOx)
5-0
CH7_SLOT[5:0]
R/W
6h
Channel 7 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
7.6.1.2.15 ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
This register is the ASI slot configuration register for channel 8.
Figure 100. ASI_CH8 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH8_OUTPUT
R/W-0h
CH8_SLOT[5:0]
R/W-7h
Table 60. ASI_CH8 Register Field Descriptions
Bit
7
Field
Reserved
Type
R
Reset
0h
Description
Reserved
6
CH8_OUTPUT
R/W
0h
Channel 8 output line.
0d = Channel 8 output is on the ASI primary output pin (SDOUT)
0d = Channel 8 output is on the ASI secondary output pin (GPIO1 or GPOx)
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Table 60. ASI_CH8 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
CH8_SLOT[5:0]
R/W
7h
Channel 8 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
7.6.1.2.16 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
This register is the ASI master mode configuration register 0.
Figure 101. MST_CFG0 Register
7
6
5
4
3
2
1
0
MST_SLV_CF AUTO_CLK_C AUTO_MODE_ BCLK_FSYNC_
FS_MODE
R/W-0h
MCLK_FREQ_SEL[2:0]
R/W-2h
G
FG
PLL_DIS
GATE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 61. MST_CFG0 Register Field Descriptions
Bit
Field
MST_SLV_CFG
Type
Reset
Description
7
R/W
0h
ASI master or slave configuration register setting.
0d = Device is in slave mode (both BCLK and FSYNC are inputs to the
device)
1d = Device is in master mode (both BCLK and FSYNC are generated from
the device)
6
AUTO_CLK_CFG
R/W
0h
Automatic clock configuration setting.
0d = Auto clock configuration is enabled (all internal clock divider and PLL
configurations are auto derived)
1d = Auto clock configuration is disabled (custom mode and device GUI
must be used for the device configuration settings)
5
4
AUTO_MODE_PLL_DIS
BCLK_FSYNC_GATE
R/W
R/W
0h
0h
Automatic mode PLL setting.
0d = PLL is enabled in auto clock configuration
1d = PLL is disabled in auto clock configuration
BCLK and FSYNC clock gate (valid when the device is in master mode).
0d = Do not gate BCLK and FSYNC
1d = Force gate BCLK and FSYNC when being transmitted from the device
in master mode
3
FS_MODE
R/W
R/W
0h
2h
Sample rate setting (valid when the device is in master mode).
0d = fS is a multiple (or submultiple) of 48 kHz
1d = fS is a multiple (or submultiple) of 44.1 kHz
2-0
MCLK_FREQ_SEL[2:0]
These bits select the MCLK (GPIO or GPIx) frequency for the PLL source
clock input (valid when the device is in master mode and
MCLK_FREQ_SEL_MODE = 0).
0d = 12 MHz
1d = 12.288 MHz
2d = 13 MHz
3d = 16 MHz
4d = 19.2 MHz
5d = 19.68 MHz
6d = 24 MHz
7d = 24.576 MHz
7.6.1.2.17 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
This register is the ASI master mode configuration register 1.
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Figure 102. MST_CFG1 Register
7
6
5
4
3
2
1
0
FS_RATE[3:0]
R/W-4h
FS_BCLK_RATIO[3:0]
R/W-8h
Table 62. MST_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
FS_RATE[3:0]
R/W
4h
Programmed sample rate of the ASI bus (not used when the device is
configured in slave mode auto clock configuration).
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 15d = Reserved
3-0
FS_BCLK_RATIO[3:0]
R/W
8h
Programmed BCLK to FSYNC frequency ratio of the ASI bus (not used
when the device is configured in slave mode auto clock configuration).
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d to 15d = Reserved
7.6.1.2.18 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
This register s the ASI bus clock monitor status register
Figure 103. ASI_STS Register
7
6
5
4
3
2
1
0
FS_RATE_STS[3:0]
R-Fh
FS_RATIO_STS[3:0]
R-Fh
Table 63. ASI_STS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
FS_RATE_STS[3:0]
R
Fh
Detected sample rate of the ASI bus.
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 14d = Reserved
15d = Invalid sample rate
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Table 63. ASI_STS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
FS_RATIO_STS[3:0]
R
Fh
Detected BCLK to FSYNC frequency ratio of the ASI bus.
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d to 14d = Reserved
15d = Invalid ratio
7.6.1.2.19 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
This register is the clock source configuration register.
Figure 104. CLK_SRC Register
7
6
5
4
3
2
1
0
DIS_PLL_SLV_ MCLK_FREQ_
MCLK_RATIO_SEL[2:0]
R/W-2h
Reserved
R-0h
CLK_SRC
SEL_MODE
R/W-0h
R/W-0h
Table 64. CLK_SRC Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DIS_PLL_SLV_CLK_SRC R/W
0h
Audio root clock source setting when the device is configured with the PLL
disabled in the auto clock configuration for slave mode
(AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source
1d = MCLK (GPIO or GPIx) is used as the audio root clock source (the
MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting)
6
MCLK_FREQ_SEL_MODE R/W
0h
2h
Master mode MCLK (GPIO or GPIx) frequency selection mode (valid when
the device is in auto clock configuration).
0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19)
configuration
1d = MCLK frequency is specified as a multiple of FSYNC in the
MCLK_RATIO_SEL (P0_R22) configuration
5-3
MCLK_RATIO_SEL[2:0]
R/W
These bits select the MCLK (GPIO or GPIx) to FSYNC ratio for master
mode or when MCLK is used as the audio root clock source in slave mode.
0d = Ratio of 64
1d = Ratio of 256
2d = Ratio of 384
3d = Ratio of 512
4d = Ratio of 768
5d = Ratio of 1024
6d = Ratio of 1536
7d = Ratio of 2304
2-0
Reserved
R
0h
Reserved
7.6.1.2.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
This register is the PDM clock generation configuration register.
Figure 105. PDMCLK_CFG Register
7
6
5
4
3
2
1
0
Reserved
R/W-0h
Reserved
R/W-10h
PDMCLK_DIV[1:0]
R/W-0h
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Table 65. PDMCLK_CFG Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
Reset
0h
Description
Reserved
Reserved
Reserved
6-2
1-0
Reserved
10h
0h
PDMCLK_DIV[1:0]
PDMCLK divider value.
0d = PDMCLK is 2.8224 MHz or 3.072 MHz
1d = PDMCLK is 1.4112 MHz or 1.536 MHz
2d = PDMCLK is 705.6 kHz or 768 kHz
3d = PDMCLK is 5.6448 MHz or 6.144 MHz
7.6.1.2.21 PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
This register is the PDM DINx sampling edge configuration register.
Figure 106. PDMIN_CFG Register
7
6
5
4
3
2
1
0
PDMDIN1_ED PDMDIN2_ED PDMDIN3_ED PDMDIN4_ED
Reserved
R-0h
GE
GE
GE
GE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 66. PDMIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PDMDIN1_EDGE
PDMDIN2_EDGE
PDMDIN3_EDGE
PDMDIN4_EDGE
Reserved
R/W
0h
PDMCLK latching edge used for channel 1 and channel 2 data.
0d = Channel 1 data are latched on the negative edge, channel 2 data are
latched on the positive edge
1d = Channel 1 data are latched on the positive edge, channel 2 data are
latched on the negative edge
6
R/W
R/W
R/W
R
0h
0h
0h
0h
PDMCLK latching edge used for channel 3 and channel 4 data.
0d = Channel 3 data are latched on the negative edge, channel 4 data are
latched on the positive edge
1d = Channel 3 data are latched on the positive edge, channel 4 data are
latched on the negative edge
5
PDMCLK latching edge used for channel 5 and channel 6 data.
0d = Channel 5 data are latched on the negative edge, channel 6 data are
latched on the positive edge
1d = Channel 5 data are latched on the positive edge, channel 6 data are
latched on the negative edge
4
PDMCLK latching edge used for channel 7 and channel 8 data.
0d = Channel 7 data are latched on the negative edge, channel 8 data are
latched on the positive edge
1d = Channel 7 data are latched on the positive edge, channel 8 data are
latched on the negative edge
3-0
Reserved
7.6.1.2.22 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
This register is the GPIO configuration register 0.
Figure 107. GPIO_CFG0 Register
7
6
5
4
3
2
1
0
GPIO1_CFG[3:0]
R/W-2h
Reserved
R-0h
GPIO1_DRV[2:0]
R/W-2h
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Table 67. GPIO_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPIO1_CFG[3:0]
R/W
2h
GPIO1 configuration.
0d = GPIO1 is disabled
1d = GPIO1 is configured as a general-purpose output (GPO)
2d = GPIO1 is configured as a device interrupt output (IRQ)
3d = GPIO1 is configured as a secondary ASI output (SDOUT2)
4d = GPIO1 is configured as a PDM clock output (PDMCLK)
5d to 7d = Reserved
8d = GPIO1 is configured as an input to control when MICBIAS turns on or
off (MICBIAS_EN)
9d = GPIO1 is configured as a general-purpose input (GPI)
10d = GPIO1 is configured as a master clock input (MCLK)
11d = GPIO1 is configured as an ASI input for daisy-chain (SDIN)
12d = GPIO1 is configured as a PDM data input for channel 1 and channel 2
(PDMDIN1)
13d = GPIO1 is configured as a PDM data input for channel 3 and channel 4
(PDMDIN2)
14d = GPIO1 is configured as a PDM data input for channel 5 and channel 6
(PDMDIN3)
15d = GPIO1 is configured as a PDM data input for channel 7 and channel 8
(PDMDIN4)
3
Reserved
R
0h
2h
Reserved
2-0
GPIO1_DRV[2:0]
R/W
GPIO1 output drive configuration (not used when GPIO1 is configured as
SDOUT2).
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved
7.6.1.2.23 GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
This registeris the GPO configuration register 0.
Figure 108. GPO_CFG0 Register
7
6
5
4
3
2
1
0
GPO1_CFG[3:0]
R/W-0h
Reserved
R-0h
Table 68. GPO_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPO1_CFG[3:0]
R/W
0h
PDMCLK1_GPO1 (GPO1) configuration.
0d = GPO1 is disabled
1d = GPO1 is configured as a general-purpose output (GPO)
2d = GPO1 is configured as a device interrupt output (IRQ)
3d = GPO1 is configured as a secondary ASI output (SDOUT2)
4d = GPO1 is configured as a PDM clock output (PDMCLK)
5d to 15d = Reserved
3-0
Reserved
R
0h
Reserved
7.6.1.2.24 GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
This registeris the GPO configuration register 1.
Figure 109. GPO_CFG1 Register
7
6
5
4
3
2
1
0
GPO2_CFG[3:0]
R/W-0h
Reserved
R-0h
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Table 69. GPO_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPO2_CFG[3:0]
R/W
0h
PDMCLK2_GPO2 (GPO2) configuration.
0d = GPO2 is disabled
1d = GPO2 is configured as a general-purpose output (GPO)
2d = GPO2 is configured as a device interrupt output (IRQ)
3d = GPO2 is configured as a secondary ASI output (SDOUT2)
4d = GPO2 is configured as a PDM clock output (PDMCLK)
5d to 15d = Reserved
3-0
Reserved
R
0h
Reserved
7.6.1.2.25 GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
This registeris the GPO configuration register 2.
Figure 110. GPO_CFG2 Register
7
6
5
4
3
2
1
0
GPO3_CFG[3:0]
R/W-0h
Reserved
R-0h
Table 70. GPO_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPO3_CFG[3:0]
R/W
0h
PDMCLK3_GPO3 (GPO3) configuration.
0d = GPO3 is disabled
1d = GPO3 is configured as a general-purpose output (GPO)
2d = GPO3 is configured as a device interrupt output (IRQ)
3d = GPO3 is configured as a secondary ASI output (SDOUT2)
4d = GPO3 is configured as a PDM clock output (PDMCLK)
5d to 15d = Reserved
3-0
Reserved
R
0h
Reserved
7.6.1.2.26 GPO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
This registeris the GPO configuration register 3.
Figure 111. GPO_CFG3 Register
7
6
5
4
3
2
1
0
GPO4_CFG[3:0]
R/W-0h
Reserved
R-0h
Table 71. GPO_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPO4_CFG[3:0]
R/W
0h
PDMCLK4_GPO4 (GPO4) configuration.
0d = GPO4 is disabled
1d = GPO4 is configured as a general-purpose output (GPO)
2d = GPO4 is configured as a device interrupt output (IRQ)
3d = GPO4 is configured as a secondary ASI output (SDOUT2)
4d = GPO4 is configured as a PDM clock output (PDMCLK)
5d to 15d = Reserved
3-0
Reserved
R
0h
Reserved
7.6.1.2.27 GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
This register is the GPIO and GPO output value register.
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Figure 112. GPO_VAL Register
7
6
5
4
3
2
1
0
GPIO1_VAL
R/W-0h
GPO1_VAL
R/W-0h
GPO2_VAL
R/W-0h
GPO3_VAL
R/W-0h
GPO4_VAL
R/W-0h
Reserved
R-0h
Table 72. GPO_VAL Register Field Descriptions
Bit
Field
GPIO1_VAL
Type
Reset
Description
7
R/W
0h
GPIO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
6
5
GPO1_VAL
GPO2_VAL
GPO3_VAL
GPO4_VAL
Reserved
R/W
R/W
R/W
R/W
R
0h
0h
0h
0h
0h
GPO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
GPO2 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
4
GPO3 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
3
GPO4 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
2-0
Reserved
7.6.1.2.28 GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
This register is the GPIO monitor value register.
Figure 113. GPIO_MON Register
7
6
5
4
3
2
1
0
GPIO1_MON
R-0h
Reserved
R-0h
Table 73. GPIO_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPIO1_MON
R
0h
GPIO1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
6-0
Reserved
R
0h
Reserved
7.6.1.2.29 GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
This register is the GPI configuration register 0.
Figure 114. GPI_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
GPI1_CFG[2:0]
R/W-0h
Reserved
R-0h
GPI2_CFG[2:0]
R/W-0h
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Table 74. GPI_CFG0 Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
GPI1_CFG[2:0]
Reserved
6-4
R/W
0h
PDMDIN1_GPI1 (GPI1) configuration.
0d = GPI1 is disabled
1d = GPI1 is configured as a general-purpose input (GPI)
2d = GPI1 is configured as a master clock input (MCLK)
3d = GPI1 is configured as an ASI input for daisy-chain (SDIN)
4d = GPI1 is configured as a PDM data input for channel 1 and channel 2
(PDMDIN1)
5d = GPI1 is configured as a PDM data input for channel 3 and channel 4
(PDMDIN2)
6d = GPI1 is configured as a PDM data input for channel 5 and channel 6
(PDMDIN3)
7d = GPI1 is configured as a PDM data input for channel 7 and channel 8
(PDMDIN4)
3
Reserved
R
0h
0h
Reserved
2-0
GPI2_CFG[2:0]
R/W
PDMDIN2_GPI2 (GPI2) configuration.
0d = GPI2 is disabled
1d = GPI2 is configured as a general-purpose input (GPI)
2d = GPI2 is configured as a master clock input (MCLK)
3d = GPI2 is configured as an ASI input for daisy-chain (SDIN)
4d = GPI2 is configured as a PDM data input for channel 1 and channel 2
(PDMDIN1)
5d = GPI2 is configured as a PDM data input for channel 3 and channel 4
(PDMDIN2)
6d = GPI2 is configured as a PDM data input for channel 5 and channel 6
(PDMDIN3)
7d = GPI2 is configured as a PDM data input for channel 7 and channel 8
(PDMDIN4)
7.6.1.2.30 GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
This register is the GPI configuration register 1.
Figure 115. GPI_CFG1 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
GPI3_CFG[2:0]
R/W-0h
Reserved
R-0h
GPI4_CFG[2:0]
R/W-0h
Table 75. GPI_CFG1 Register Field Descriptions
Bit
7
Field
Reserved
Type
R
Reset
0h
Description
Reserved
6-4
GPI3_CFG[2:0]
R/W
0h
PDMDIN3_GPI3 (GPI3) configuration.
0d = GPI3 is disabled
1d = GPI3 is configured as a general-purpose input (GPI)
2d = GPI3 is configured as a master clock input (MCLK)
3d = GPI3 is configured as an ASI input for daisy-chain (SDIN)
4d = GPI3 is configured as a PDM data input for channel 1 and channel 2
(PDMDIN1)
5d = GPI3 is configured as a PDM data input for channel 3 and channel 4
(PDMDIN2)
6d = GPI3 is configured as a PDM data input for channel 5 and channel 6
(PDMDIN3)
7d = GPI3 is configured as a PDM data input for channel 7 and channel 8
(PDMDIN4)
3
Reserved
R
0h
Reserved
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Table 75. GPI_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
GPI4_CFG[2:0]
R/W
0h
PDMDIN4_GPI4 (GPI4) configuration.
0d = GPI4 is disabled
1d = GPI4 is configured as a general-purpose input (GPI)
2d = GPI4 is configured as a master clock input (MCLK)
3d = GPI4 is configured as an ASI input for daisy-chain (SDIN)
4d = GPI4 is configured as a PDM data input for channel 1 and channel 2
(PDMDIN1)
5d = GPI4 is configured as a PDM data input for channel 3 and channel 4
(PDMDIN2)
6d = GPI4 is configured as a PDM data input for channel 5 and channel 6
(PDMDIN3)
7d = GPI4 is configured as a PDM data input for channel 7 and channel 8
(PDMDIN4)
7.6.1.2.31 GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
This regiser is the GPI monitor value register.
Figure 116. GPI_MON Register
7
6
5
4
3
2
1
0
GPI1_MON
R-0h
GPI2_MON
R-0h
GPI3_MON
R-0h
GPI4_MON
R-0h
Reserved
R-0h
Table 76. GPI_MON Register Field Descriptions
Bit
Field
GPI1_MON
Type
Reset
Description
7
R
0h
GPI1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
6
5
GPI2_MON
GPI3_MON
GPI4_MON
Reserved
R
R
R
R
0h
0h
0h
0h
GPI2 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
GPI3 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
4
GPI4 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
3-0
Reserved
7.6.1.2.32 INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
This regiser is the interrupt configuration register.
Figure 117. INT_CFG Register
7
6
5
4
3
2
1
0
LTCH_READ_
Reserved
CFG
INT_POL
R/W-0h
INT_EVENT[1:0]
R/W-0h
Reserved
R-0h
RR/W-0-h0h
Table 77. INT_CFG Register Field Descriptions
Bit
Field
INT_POL
Type
Reset
Description
7
R/W
0h
Interrupt polarity.
0d = Active low (IRQZ)
1d = Active high (IRQ)
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Table 77. INT_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-5
INT_EVENT[1:0]
R/W
0h
Interrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event
1d = Reserved
2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any
unmasked latched interrupts event
3d = INT asserts for 2 ms (typical) one time on each pulse for any
unmasked interrupts event
4-3
2
Reserved
R
0h
0h
Reserved
LTCH_READ_CFG
R/W
Interrupt latch registers readback configuration.
0d = All interrupts can be read through the LTCH registers
1d = Only unmasked interrupts can be read through the LTCH registers
1-0
Reserved
R
0h
Reserved
7.6.1.2.33 INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
This register is the interrupt masks register 0.
Figure 118. INT_MASK0 Register
7
6
5
4
3
2
1
0
INT_MASK0[7] INT_MASK0[6]
R/W-1h R/W-1h
Reserved
R/W-1h
Reserved
R/W-1h
Reserved
R/W-1h
Reserved
R/W-1h
Reserved
R/W-1h
Reserved
R/W-1h
Table 78. INT_MASK0 Register Field Descriptions
Bit
Field
INT_MASK0[7]
Type
Reset
Description
7
R/W
1h
ASI clock error mask.
0d = Do not mask
1d = Mask
6
INT_MASK0[6]
Reserved
R/W
R/W
1h
PLL Lock interrupt mask.
0d = Do not mask
1d = Mask
5-0
3Fh
Reserved
7.6.1.2.34 INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
This register is the latched Interrupt readback register 0.
Figure 119. INT_LTCH0 Register
7
6
5
4
3
2
1
0
INT_LTCH0[7] INT_LTCH0[6]
R-0h R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Table 79. INT_LTCH0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH0[7]
INT_LTCH0[6]
Reserved
R
0h
Interrupt caused by an ASI bus clock error (self-clearing bit).
0d = No interrupt
1d = Interrupt
6
R
R
0h
0h
Interrupt caused by PLL LOCK (self-clearing bit).
0d = No interrupt
1d = Interrupt
5-0
Reserved
7.6.1.2.35 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
This register is the MICBIAS and VREF configuration register
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Figure 120. BIAS_CFG Register
7
6
5
4
3
2
1
0
Reserved
R-0h
MBIAS_VAL[2:0]
R/W-0h
Reserved
R-0h
VREF_SEL[1:0]
R/W-0h
Table 80. BIAS_CFG Register Field Descriptions
Bit
7
Field
Reserved
Type
R
Reset
0h
Description
Reserved
6-4
MBIAS_VAL[2:0]
R/W
0h
MICBIAS value.
0d = Microphone bias is set to VREF (2.750 V, 2.500 V, or 1.375 V)
1d to 5d = Reserved 2d = Reserved
6d = Microphone bias is set to AVDD
7d = Reserved
3-2
1-0
Reserved
R
0h
0h
Reserved
VREF_SEL[1:0]
R/W
VREF voltage setting (configure this setting based on the AVDD supply
minimum voltage used).
0d = VREF is set to 2.75 V
1d = VREF is set to 2.5 V
2d = VREF is set to 1.375 V (this option must be used for 1.8 V AVDD)
3d = Reserved
7.6.1.2.36 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
This register is configuration register 0 for channel 1.
Figure 121. CH1_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R/W-0h
CH1_INSRC[1:0]
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
Reserved
R/W-0h
Table 81. CH1_CFG0 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
0h
Description
Reserved
Reserved
6-5
CH1_INSRC[1:0]
0h
Channel 1 input configuration.
0d = Input source is not enabled
1d = Reserved
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN1 and PDMCLK)
3d = Reserved
4-0
Reserved
R/W
0h
Reserved
7.6.1.2.37 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
This register is configuration register 2 for channel 1.
Figure 122. CH1_CFG2 Register
7
6
5
4
3
2
1
0
CH1_DVOL[7:0]
R/W-C9h
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Table 82. CH1_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH1_DVOL[7:0]
R/W
C9h
Channel 1 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
7.6.1.2.38 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
This register is configuration register 3 for channel 1.
Figure 123. CH1_CFG3 Register
7
6
5
4
3
2
1
0
CH1_GCAL[3:0]
R/W-8h
Reserved
R-0h
Table 83. CH1_CFG3 Register Field Descriptions
Bit
Field
CH1_GCAL[3:0]
Type
Reset
Description
7-4
R/W
8h
Channel 1 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
7.6.1.2.39 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
This register is configuration register 4 for channel 1.
Figure 124. CH1_CFG4 Register
7
6
5
4
3
2
1
0
CH1_PCAL[7:0]
R/W-0h
Table 84. CH1_CFG4 Register Field Descriptions
Bit
Field
CH1_PCAL[7:0]
Type
Reset
Description
7-0
R/W
0h
Channel 1 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
7.6.1.2.40 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
This register is configuration register 0 for channel 2.
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Figure 125. CH2_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R/W-0h
CH2_INSRC[1:0]
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
Reserved
R/W-0h
Table 85. CH2_CFG0 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
0h
Description
Reserved
Reserved
6-5
CH2_INSRC[1:0]
0h
Channel 2 input configuration.
0d = Input source is not enabled
1d = Reserved
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN1 and PDMCLK)
3d = Reserved
4-0
Reserved
R/W
0h
Reserved
7.6.1.2.41 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
This register is configuration register 2 for channel 2.
Figure 126. CH2_CFG2 Register
7
6
5
4
3
2
1
0
CH2_DVOL[7:0]
R/W-C9h
Table 86. CH2_CFG2 Register Field Descriptions
Bit
Field
CH2_DVOL[7:0]
Type
Reset
Description
7-0
R/W
C9h
Channel 2 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
7.6.1.2.42 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
This register is configuration register 3 for channel 2.
Figure 127. CH2_CFG3 Register
7
6
5
4
3
2
1
0
CH2_GCAL[3:0]
R/W-8h
Reserved
R-0h
Table 87. CH2_CFG3 Register Field Descriptions
Bit
Field
CH2_GCAL[3:0]
Type
Reset
Description
7-4
R/W
8h
Channel 2 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
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Table 87. CH2_CFG3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
Reserved
R
0h
Reserved
7.6.1.2.43 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
This register is configuration register 4 for channel 2.
Figure 128. CH2_CFG4 Register
7
6
5
4
3
2
1
0
CH2_PCAL[7:0]
R/W-0h
Table 88. CH2_CFG4 Register Field Descriptions
Bit
Field
CH2_PCAL[7:0]
Type
Reset
Description
7-0
R/W
0h
Channel 2 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
7.6.1.2.44 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
This register is configuration register 0 for channel 3.
Figure 129. CH3_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R/W-0h
CH3_INSRC[1:0]
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
Reserved
R/W-0h
Table 89. CH3_CFG0 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
0h
Description
Reserved
Reserved
6-5
CH3_INSRC[1:0]
0h
Channel 3 input configuration.
0d = Input source is not enabled
1d = Reserved
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN2 and PDMCLK)
3d = Reserved
4-0
Reserved
R/W
0h
Reserved
7.6.1.2.45 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
This register is configuration register 2 for channel 3.
Figure 130. CH3_CFG2 Register
7
6
5
4
3
2
1
0
CH3_DVOL[7:0]
R/W-C9h
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Table 90. CH3_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH3_DVOL[7:0]
R/W
C9h
Channel 3 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
7.6.1.2.46 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
This register is configuration register 3 for channel 3.
Figure 131. CH3_CFG3 Register
7
6
5
4
3
2
1
0
CH3_GCAL[3:0]
R/W-8h
Reserved
R-0h
Table 91. CH3_CFG3 Register Field Descriptions
Bit
Field
CH3_GCAL[3:0]
Type
Reset
Description
7-4
R/W
8h
Channel 3 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
7.6.1.2.47 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
This register is configuration register 4 for channel 3.
Figure 132. CH3_CFG4 Register
7
6
5
4
3
2
1
0
CH3_PCAL[7:0]
R/W-0h
Table 92. CH3_CFG4 Register Field Descriptions
Bit
Field
CH3_PCAL[7:0]
Type
Reset
Description
7-0
R/W
0h
Channel 3 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
7.6.1.2.48 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
This register is configuration register 0 for channel 4.
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Figure 133. CH4_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R/W-0h
CH4_INSRC[1:0]
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
Reserved
R/W-0h
Table 93. CH4_CFG0 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
0h
Description
Reserved
Reserved
6-5
CH4_INSRC[1:0]
0h
Channel 4 input configuration.
0d = Input source is not enabled
1d = Reserved
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN2 and PDMCLK)
3d = Reserved
4-0
Reserved
R/W
0h
Reserved
7.6.1.2.49 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
This register is configuration register 2 for channel 4.
Figure 134. CH4_CFG2 Register
7
6
5
4
3
2
1
0
CH4_DVOL[7:0]
R/W-C9h
Table 94. CH4_CFG2 Register Field Descriptions
Bit
Field
CH4_DVOL[7:0]
Type
Reset
Description
7-0
R/W
C9h
Channel 4 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
7.6.1.2.50 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
This register is configuration register 3 for channel 4.
Figure 135. CH4_CFG3 Register
7
6
5
4
3
2
1
0
CH4_GCAL[3:0]
R/W-8h
Reserved
R-0h
Table 95. CH4_CFG3 Register Field Descriptions
Bit
Field
CH4_GCAL[3:0]
Type
Reset
Description
7-4
R/W
8h
Channel 4 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
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Table 95. CH4_CFG3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
Reserved
R
0h
Reserved
7.6.1.2.51 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
This register is configuration register 4 for channel 4.
Figure 136. CH4_CFG4 Register
7
6
5
4
3
2
1
0
CH4_PCAL[7:0]
R/W-0h
Table 96. CH4_CFG4 Register Field Descriptions
Bit
Field
CH4_PCAL[7:0]
Type
Reset
Description
7-0
R/W
0h
Channel 4 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
7.6.1.2.52 CH5_CFG0 Register (page = 0x00, address = 0x50) [reset = 0h]
This register is configuration register 0 for Channel 5.
Figure 137. CH5_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH5_INSRC[1:0]
R/W-0h
Reserved
R-0h
Table 97. CH5_CFG0 Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved
6-5
CH5_INSRC[1:0]
R/W
0h
Channel 5 Input Configuration
0d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN3 and PDMCLK)
1d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN3 and PDMCLK)
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN3 and PDMCLK)
3d = Reserved
4-0
Reserved
R
0h
Reserved
7.6.1.2.53 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
This register is configuration register 2 for Channel 5.
Figure 138. CH5_CFG2 Register
7
6
5
4
3
2
1
0
CH5_DVOL[7:0]
R/W-C9h
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Table 98. CH5_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH5_DVOL[7:0]
R/W
C9h
Channel 5 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
7.6.1.2.54 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
This register is configuration register 3 for Channel 5.
Figure 139. CH5_CFG3 Register
7
6
5
4
3
2
1
0
CH5_GCAL[3:0]
R/W-8h
Reserved
R-0h
Table 99. CH5_CFG3 Register Field Descriptions
Bit
Field
CH5_GCAL[3:0]
Type
Reset
Description
7-4
R/W
8h
Channel 5 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
7.6.1.2.55 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
This register is configuration register 4 for Channel 5.
Figure 140. CH5_CFG4 Register
7
6
5
4
3
2
1
0
CH5_PCAL[7:0]
R/W-0h
Table 100. CH5_CFG4 Register Field Descriptions
Bit
Field
CH5_PCAL[7:0]
Type
Reset
Description
7-0
R/W
0h
Channel 5 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
7.6.1.2.56 CH6_CFG0 Register (page = 0x00, address = 0x55) [reset = 0h]
This register is configuration register 0 for Channel 6.
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Figure 141. CH6_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH6_INSRC[1:0]
R/W-0h
Reserved
R-0h
Table 101. CH6_CFG0 Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved
6-5
CH6_INSRC[1:0]
R/W
0h
Channel 6 Input Configuration
0d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN3 and PDMCLK)
1d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN3 and PDMCLK)
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN3 and PDMCLK)
3d = Reserved
4-0
Reserved
R
0h
Reserved
7.6.1.2.57 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
This register is configuration register 2 for Channel 6.
Figure 142. CH6_CFG2 Register
7
6
5
4
3
2
1
0
CH6_DVOL[7:0]
R/W-C9h
Table 102. CH6_CFG2 Register Field Descriptions
Bit
Field
CH6_DVOL[7:0]
Type
Reset
Description
7-0
R/W
C9h
Channel 6 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
7.6.1.2.58 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
This register is configuration register 3 for Channel 6.
Figure 143. CH6_CFG3 Register
7
6
5
4
3
2
1
0
CH6_GCAL[3:0]
R/W-8h
Reserved
R-0h
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Table 103. CH6_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH6_GCAL[3:0]
R/W
8h
Channel 6 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
7.6.1.2.59 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
This register is configuration register 4 for Channel 6.
Figure 144. CH6_CFG4 Register
7
6
5
4
3
2
1
0
CH6_PCAL[7:0]
R/W-0h
Table 104. CH6_CFG4 Register Field Descriptions
Bit
Field
CH6_PCAL[7:0]
Type
Reset
Description
7-0
R/W
0h
Channel 6 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
7.6.1.2.60 CH7_CFG0 Register (page = 0x00, address = 0x5A) [reset = 0h]
This register is configuration register 0 for Channel 7.
Figure 145. CH7_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH7_INSRC[1:0]
R/W-0h
Reserved
R-0h
Table 105. CH7_CFG0 Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved
6-5
CH7_INSRC[1:0]
R/W
0h
Channel 7 Input Configuration
0d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN4 and PDMCLK)
1d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN4 and PDMCLK)
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN4 and PDMCLK)
3d = Reserved
4-0
Reserved
R
0h
Reserved
7.6.1.2.61 CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
This register is configuration register 2 for Channel 7.
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Figure 146. CH7_CFG2 Register
7
6
5
4
3
2
1
0
CH7_DVOL[7:0]
R/W-C9h
Table 106. CH7_CFG2 Register Field Descriptions
Bit
Field
CH7_DVOL[7:0]
Type
Reset
Description
7-0
R/W
C9h
Channel 7 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
7.6.1.2.62 CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
This register is configuration register 3 for Channel 7.
Figure 147. CH7_CFG3 Register
7
6
5
4
3
2
1
0
CH7_GCAL[3:0]
R/W-8h
Reserved
R-0h
Table 107. CH7_CFG3 Register Field Descriptions
Bit
Field
CH7_GCAL[3:0]
Type
Reset
Description
7-4
R/W
8h
Channel 7 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
7.6.1.2.63 CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
This register is configuration register 4 for Channel 7.
Figure 148. CH7_CFG4 Register
7
6
5
4
3
2
1
0
CH7_PCAL[7:0]
R/W-0h
Table 108. CH7_CFG4 Register Field Descriptions
Bit
Field
CH7_PCAL[7:0]
Type
Reset
Description
7-0
R/W
0h
Channel 7 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
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7.6.1.2.64 CH8_CFG0 Register (page = 0x00, address = 0x5F) [reset = 0h]
This register is configuration register 0 for Channel 8.
Figure 149. CH8_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
CH8_INSRC[1:0]
R/W-0h
Reserved
R-0h
Table 109. CH8_CFG0 Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved
6-5
CH8_INSRC[1:0]
R/W
0h
Channel 8 Input Configuration
0d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN4 and PDMCLK)
1d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN4 and PDMCLK)
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN4 and PDMCLK)
3d = Reserved
4-0
Reserved
R
0h
Reserved
7.6.1.2.65 CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
This register is configuration register 2 for Channel 8.
Figure 150. CH8_CFG2 Register
7
6
5
4
3
2
1
0
CH8_DVOL[7:0]
R/W-C9h
Table 110. CH8_CFG2 Register Field Descriptions
Bit
Field
CH8_DVOL[7:0]
Type
Reset
Description
7-0
R/W
C9h
Channel 8 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
7.6.1.2.66 CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
This register is configuration register 3 for Channel 8.
Figure 151. CH8_CFG3 Register
7
6
5
4
3
2
1
0
CH8_GCAL[3:0]
R/W-8h
Reserved
R-0h
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Table 111. CH8_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH8_GCAL[3:0]
R/W
8h
Channel 8 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
7.6.1.2.67 CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
This register is configuration register 4 for Channel 8.
Figure 152. CH8_CFG4 Register
7
6
5
4
3
2
1
0
CH8_PCAL[7:0]
R/W-0h
Table 112. CH8_CFG4 Register Field Descriptions
Bit
Field
CH8_PCAL[7:0]
Type
Reset
Description
7-0
R/W
0h
Channel 8 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
7.6.1.2.68 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
This register is the digital signal processor (DSP) configuration register 0.
Figure 153. DSP_CFG0 Register
7
6
5
4
3
2
1
0
Reserved
R-0h
DECI_FILT[1:0]
R/W-0h
CH_SUM[1:0]
R/W-0h
HPF_SEL[1:0]
R/W-1h
Table 113. DSP_CFG0 Register Field Descriptions
Bit
7-6
5-4
Field
Type
R
Reset
0h
Description
Reserved
Reserved
DECI_FILT[1:0]
R/W
0h
Decimation filter response.
0d = Linear phase
1d = Low latency
2d = Ultra-low latency
3d = Reserved
3-2
CH_SUM[1:0]
R/W
0h
Channel summation mode for higher SNR
0d = Channel summation mode is disabled
1d = 2-channel summation mode is enabled to generate a (CH1 + CH2) / 2
and a (CH3 + CH4) / 2 output
2d = 4-channel summation mode is enabled to generate a (CH1 + CH2 +
CH3 + CH4) / 4 output
3d = Reserved
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Table 113. DSP_CFG0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
HPF_SEL[1:0]
R/W
1h
High-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default
coefficient values in P4_R72 to P4_R83 set as the all-pass filter
1d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is selected
2d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected
3d = HPF with a cutoff of 0.008 x fS (384 Hz at fS = 48 kHz) is selected
7.6.1.2.69 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
This register is the digital signal processor (DSP) configuration register 1.
Figure 154. DSP_CFG1 Register
7
6
5
4
3
2
1
0
DISABLE_SOF
T_STEP
DVOL_GANG
R/W-0h
BIQUAD_CFG[1:0]
R/W-2h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
R/W-0h
Table 114. DSP_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DVOL_GANG
R/W
0h
DVOL control ganged across channels.
0d = Each channel has its own DVOL CTRL settings as programmed in the
CHx_DVOL bits
1d = All active channels must use the channel 1 DVOL setting (CH1_DVOL)
irrespective of whether channel 1 is turned on or not
6-5
BIQUAD_CFG[1:0]
R/W
2h
Number of biquads per channel configuration.
0d = No biquads per channel; biquads are all disabled
1d = 1 biquad per channel
2d = 2 biquads per channel
3d = 3 biquads per channel
4
DISABLE_SOFT_STEP
Reserved
R/W
R/W
0h
0h
Soft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled
1d = Soft-stepping disabled
3-0
Reserved
7.6.1.2.70 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
This register is the input channel enable configuration register.
Figure 155. IN_CH_EN Register
7
6
5
4
3
2
1
0
IN_CH1_EN
R/W-1h
IN_CH2_EN
R/W-1h
IN_CH3_EN
R/W-1h
IN_CH4_EN
R/W-1h
IN_CH5_EN
R/W-0h
IN_CH6_EN
R/W-0h
IN_CH7_EN
R/W-0h
IN_CH8_EN
R/W-0h
Table 115. IN_CH_EN Register Field Descriptions
Bit
Field
IN_CH1_EN
Type
Reset
Description
7
R/W
1h
Input channel 1 enable setting.
0d = Channel 1 is disabled
1d = Channel 1 is enabled
6
5
4
IN_CH2_EN
IN_CH3_EN
IN_CH4_EN
R/W
R/W
R/W
1h
1h
1h
Input channel 2 enable setting.
0d = Channel 2 is disabled
1d = Channel 2 is enabled
Input channel 3 enable setting.
0d = Channel 3 is disabled
1d = Channel 3 is enabled
Input channel 4 enable setting.
0d = Channel 4 is disabled
1d = Channel 4 is enabled
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Table 115. IN_CH_EN Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
IN_CH5_EN
R/W
0h
Input channel 5 enable setting.
0d = Channel 5 is disabled
1d = Channel 5 is enabled
2
1
0
IN_CH6_EN
IN_CH7_EN
IN_CH8_EN
R/W
R/W
R/W
0h
0h
0h
Input channel 6 enable setting.
0d = Channel 6 is disabled
1d = Channel 6 is enabled
Input channel 7 enable setting.
0d = Channel 7 is disabled
1d = Channel 7 is enabled
Input channel 8 enable setting.
0d = Channel 8 is disabled
1d = Channel 8 is enabled
7.6.1.2.71 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
This register is the ASI output channel enable configuration register.
Figure 156. ASI_OUT_CH_EN Register
7
6
5
4
3
2
1
0
ASI_OUT_CH1 ASI_OUT_CH2 ASI_OUT_CH3 ASI_OUT_CH4 ASI_OUT_CH5 ASI_OUT_CH6 ASI_OUT_CH7 ASI_OUT_CH8
_EN
_EN
_EN
_EN
_EN
_EN
_EN
_EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 116. ASI_OUT_CH_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
2
1
0
ASI_OUT_CH1_EN
ASI_OUT_CH2_EN
ASI_OUT_CH3_EN
ASI_OUT_CH4_EN
ASI_OUT_CH5_EN
ASI_OUT_CH6_EN
ASI_OUT_CH7_EN
ASI_OUT_CH8_EN
R/W
0h
ASI output channel 1 enable setting.
0d = Channel 1 output slot is in a tri-state condition
1d = Channel 1 output slot is enabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
ASI output channel 2 enable setting.
0d = Channel 2 output slot is in a tri-state condition
1d = Channel 2 output slot is enabled
ASI output channel 3 enable setting.
0d = Channel 3 output slot is in a tri-state condition
1d = Channel 3 output slot is enabled
ASI output channel 4 enable setting.
0d = Channel 4 output slot is in a tri-state condition
1d = Channel 4 output slot is enabled
ASI output channel 5 enable setting.
0d = Channel 5 output slot is in a tri-state condition
1d = Channel 5 output slot is enabled
ASI output channel 6 enable setting.
0d = Channel 6 output slot is in a tri-state condition
1d = Channel 6 output slot is enabled
ASI output channel 7 enable setting.
0d = Channel 7 output slot is in a tri-state condition
1d = Channel 7 output slot is enabled
ASI output channel 8 enable setting.
0d = Channel 8 output slot is in a tri-state condition
1d = Channel 8 output slot is enabled
7.6.1.2.72 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
This register is the power-up configuration register.
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Figure 157. PWR_CFG Register
7
6
5
4
3
2
1
0
DYN_CH_PUP
D_EN
MICBIAS_PDZ
R/W-0h
PDM_PDZ
R/W-0h
PLL_PDZ
R/W-0h
DYN_MAXCH_SEL[1:0]
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
R/W-0h
Table 117. PWR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MICBIAS_PDZ
R/W
0h
Power control for MICBIAS.
0d = Power down MICBIAS
1d = Power up MICBIAS
6
5
4
PDM_PDZ
R/W
R/W
R/W
0h
0h
0h
Power control for PDM channels.
0d = Power down all PDM channels
1d = Power up all enabled PDM channels
PLL_PDZ
Power control for the PLL.
0d = Power down the PLL
1d = Power up the PLL
DYN_CH_PUPD_EN
Dynamic channel power-up, power-down enable.
0d = Channel power-up, power-down is not supported if any channel
recording is on
1d = Channel can be powered up or down individually, even if channel
recording is on
3-2
DYN_MAXCH_SEL[1:0]
R/W
0h
Dynamic mode maximum channel select configuration.
0d = Channel 1 and channel 2 are used with dynamic channel power-up,
power-down feature enabled
1d = Channel 1 to channel 4 are used with dynamic channel power-up,
power-down feature enabled
2d = Channel 1 to channel 6 are used with dynamic channel power-up,
power-down feature enabled
3d = Channel 1 to channel 8 are used with dynamic channel power-up,
power-down feature enabled
1
0
Reserved
Reserved
R/W
R
0h
0h
Reserved
Reserved
7.6.1.2.73 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
This register is the device status value register 0.
Figure 158. DEV_STS0 Register
7
6
5
4
3
2
1
0
CH1_STATUS CH2_STATUS CH3_STATUS CH4_STATUS CH5_STATUS CH6_STATUS CH7_STATUS CH8_STATUS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 118. DEV_STS0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
CH1_STATUS
CH2_STATUS
CH3_STATUS
CH4_STATUS
CH5_STATUS
R
0h
PDM channel 1 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
R
R
R
R
0h
0h
0h
0h
PDM channel 2 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
PDM channel 3 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
PDM channel 4 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
PDM channel 5 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
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Table 118. DEV_STS0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
CH6_STATUS
R
0h
PDM channel 6 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
1
0
CH7_STATUS
CH8_STATUS
R
R
0h
0h
PDM channel 7 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
PDM channel 8 power status.
0d = PDM channel is powered down
1d = PDM channel is powered up
7.6.1.2.74 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
This register is the device status value register 1.
Figure 159. DEV_STS1 Register
7
6
5
4
3
2
1
0
MODE_STS[2:0]
R-4h
Reserved
R-0h
Table 119. DEV_STS1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
MODE_STS[2:0]
R
4h
Device mode status.
4d = Device is in sleep mode or software shutdown mode
6d = Device is in active mode with all PDM channels turned off
7d = Device is in active mode with at least one PDM channel turned on
4-0
Reserved
R
0h
Reserved
7.6.1.2.75 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
This register returns the I2C transactions checksum value.
Figure 160. I2C_CKSUM Register
7
6
5
4
3
2
1
0
I2C_CKSUM[7:0]
R/W-0h
Table 120. I2C_CKSUM Register Field Descriptions
Bit
Field
I2C_CKSUM[7:0]
Type
Reset
Description
7-0
R/W
0h
These bits return the I2C transactions checksum value. Writing to this
register resets the checksum to the written value. This register is updated on
writes to other registers on all pages.
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7.6.2 Programmable Coefficient Registers
7.6.2.1 Programmable Coefficient Registers: Page = 0x02
This register page (shown in Table 121) consists of the programmable coefficients for the biquad 1 to biquad 6
filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also
supports (by default) auto-incremented pages for the I2C and SPI burst writes and reads. After a transaction of
register address 0x7F, the device auto increments to the next page at register 0x08 to transact the next
coefficient value. These programmable coefficients are 32-bit, two’s complement numbers. For a successful
coefficient register transaction, the host device must write and read all the four bytes starting with the most
significant byte (BYT1) for a target coefficient register transaction. While using SPI for a coefficient register read
transaction, the device gives out first byte as dummy read byte therefore the host must read five bytes which
includes first byte as dummy read byte and the last four bytes corresponds to the coefficient register value
starting with the most significant byte (BYT1).
Table 121. Page 0x02 Programmable Coefficient Registers
ADDRESS
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
REGISTER
RESET
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DESCRIPTION
PAGE[7:0]
Device page register
BQ1_N0_BYT1[7:0]
BQ1_N0_BYT2[7:0]
BQ1_N0_BYT3[7:0]
BQ1_N0_BYT4[7:0]
BQ1_N1_BYT1[7:0]
BQ1_N1_BYT2[7:0]
BQ1_N1_BYT3[7:0]
BQ1_N1_BYT4[7:0]
BQ1_N2_BYT1[7:0]
BQ1_N2_BYT2[7:0]
BQ1_N2_BYT3[7:0]
BQ1_N2_BYT4[7:0]
BQ1_D1_BYT1[7:0]
BQ1_D1_BYT2[7:0]
BQ1_D1_BYT3[7:0]
BQ1_D1_BYT4[7:0]
BQ1_D2_BYT1[7:0]
BQ1_D2_BYT2[7:0]
BQ1_D2_BYT3[7:0]
BQ1_D2_BYT4[7:0]
BQ2_N0_BYT1[7:0]
BQ2_N0_BYT2[7:0]
BQ2_N0_BYT3[7:0]
BQ2_N0_BYT4[7:0]
BQ2_N1_BYT1[7:0]
BQ2_N1_BYT2[7:0]
BQ2_N1_BYT3[7:0]
BQ2_N1_BYT4[7:0]
BQ2_N2_BYT1[7:0]
BQ2_N2_BYT2[7:0]
BQ2_N2_BYT3[7:0]
BQ2_N2_BYT4[7:0]
BQ2_D1_BYT1[7:0]
BQ2_D1_BYT2[7:0]
BQ2_D1_BYT3[7:0]
BQ2_D1_BYT4[7:0]
BQ2_D2_BYT1[7:0]
Programmable biquad 1, N0 coefficient byte[31:24]
Programmable biquad 1, N0 coefficient byte[23:16]
Programmable biquad 1, N0 coefficient byte[15:8]
Programmable biquad 1, N0 coefficient byte[7:0]
Programmable biquad 1, N1 coefficient byte[31:24]
Programmable biquad 1, N1 coefficient byte[23:16]
Programmable biquad 1, N1 coefficient byte[15:8]
Programmable biquad 1, N1 coefficient byte[7:0]
Programmable biquad 1, N2 coefficient byte[31:24]
Programmable biquad 1, N2 coefficient byte[23:16]
Programmable biquad 1, N2 coefficient byte[15:8]
Programmable biquad 1, N2 coefficient byte[7:0]
Programmable biquad 1, D1 coefficient byte[31:24]
Programmable biquad 1, D1 coefficient byte[23:16]
Programmable biquad 1, D1 coefficient byte[15:8]
Programmable biquad 1, D1 coefficient byte[7:0]
Programmable biquad 1, D2 coefficient byte[31:24]
Programmable biquad 1, D2 coefficient byte[23:16]
Programmable biquad 1, D2 coefficient byte[15:8]
Programmable biquad 1, D2 coefficient byte[7:0]
Programmable biquad 2, N0 coefficient byte[31:24]
Programmable biquad 2, N0 coefficient byte[23:16]
Programmable biquad 2, N0 coefficient byte[15:8]
Programmable biquad 2, N0 coefficient byte[7:0]
Programmable biquad 2, N1 coefficient byte[31:24]
Programmable biquad 2, N1 coefficient byte[23:16]
Programmable biquad 2, N1 coefficient byte[15:8]
Programmable biquad 2, N1 coefficient byte[7:0]
Programmable biquad 2, N2 coefficient byte[31:24]
Programmable biquad 2, N2 coefficient byte[23:16]
Programmable biquad 2, N2 coefficient byte[15:8]
Programmable biquad 2, N2 coefficient byte[7:0]
Programmable biquad 2, D1 coefficient byte[31:24]
Programmable biquad 2, D1 coefficient byte[23:16]
Programmable biquad 2, D1 coefficient byte[15:8]
Programmable biquad 2, D1 coefficient byte[7:0]
Programmable biquad 2, D2 coefficient byte[31:24]
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Table 121. Page 0x02 Programmable Coefficient Registers (continued)
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
BQ2_D2_BYT2[7:0]
BQ2_D2_BYT3[7:0]
BQ2_D2_BYT4[7:0]
BQ3_N0_BYT1[7:0]
BQ3_N0_BYT2[7:0]
BQ3_N0_BYT3[7:0]
BQ3_N0_BYT4[7:0]
BQ3_N1_BYT1[7:0]
BQ3_N1_BYT2[7:0]
BQ3_N1_BYT3[7:0]
BQ3_N1_BYT4[7:0]
BQ3_N2_BYT1[7:0]
BQ3_N2_BYT2[7:0]
BQ3_N2_BYT3[7:0]
BQ3_N2_BYT4[7:0]
BQ3_D1_BYT1[7:0]
BQ3_D1_BYT2[7:0]
BQ3_D1_BYT3[7:0]
BQ3_D1_BYT4[7:0]
BQ3_D2_BYT1[7:0]
BQ3_D2_BYT2[7:0]
BQ3_D2_BYT3[7:0]
BQ3_D2_BYT4[7:0]
BQ4_N0_BYT1[7:0]
BQ4_N0_BYT2[7:0]
BQ4_N0_BYT3[7:0]
BQ4_N0_BYT4[7:0]
BQ4_N1_BYT1[7:0]
BQ4_N1_BYT2[7:0]
BQ4_N1_BYT3[7:0]
BQ4_N1_BYT4[7:0]
BQ4_N2_BYT1[7:0]
BQ4_N2_BYT2[7:0]
BQ4_N2_BYT3[7:0]
BQ4_N2_BYT4[7:0]
BQ4_D1_BYT1[7:0]
BQ4_D1_BYT2[7:0]
BQ4_D1_BYT3[7:0]
BQ4_D1_BYT4[7:0]
BQ4_D2_BYT1[7:0]
BQ4_D2_BYT2[7:0]
BQ4_D2_BYT3[7:0]
BQ4_D2_BYT4[7:0]
BQ5_N0_BYT1[7:0]
BQ5_N0_BYT2[7:0]
BQ5_N0_BYT3[7:0]
BQ5_N0_BYT4[7:0]
BQ5_N1_BYT1[7:0]
BQ5_N1_BYT2[7:0]
BQ5_N1_BYT3[7:0]
BQ5_N1_BYT4[7:0]
BQ5_N2_BYT1[7:0]
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
Programmable biquad 2, D2 coefficient byte[23:16]
Programmable biquad 2, D2 coefficient byte[15:8]
Programmable biquad 2, D2 coefficient byte[7:0]
Programmable biquad 3, N0 coefficient byte[31:24]
Programmable biquad 3, N0 coefficient byte[23:16]
Programmable biquad 3, N0 coefficient byte[15:8]
Programmable biquad 3, N0 coefficient byte[7:0]
Programmable biquad 3, N1 coefficient byte[31:24]
Programmable biquad 3, N1 coefficient byte[23:16]
Programmable biquad 3, N1 coefficient byte[15:8]
Programmable biquad 3, N1 coefficient byte[7:0]
Programmable biquad 3, N2 coefficient byte[31:24]
Programmable biquad 3, N2 coefficient byte[23:16]
Programmable biquad 3, N2 coefficient byte[15:8]
Programmable biquad 3, N2 coefficient byte[7:0]
Programmable biquad 3, D1 coefficient byte[31:24]
Programmable biquad 3, D1 coefficient byte[23:16]
Programmable biquad 3, D1 coefficient byte[15:8]
Programmable biquad 3, D1 coefficient byte[7:0]
Programmable biquad 3, D2 coefficient byte[31:24]
Programmable biquad 3, D2 coefficient byte[23:16]
Programmable biquad 3, D2 coefficient byte[15:8]
Programmable biquad 3, D2 coefficient byte[7:0]
Programmable biquad 4, N0 coefficient byte[31:24]
Programmable biquad 4, N0 coefficient byte[23:16]
Programmable biquad 4, N0 coefficient byte[15:8]
Programmable biquad 4, N0 coefficient byte[7:0]
Programmable biquad 4, N1 coefficient byte[31:24]
Programmable biquad 4, N1 coefficient byte[23:16]
Programmable biquad 4, N1 coefficient byte[15:8]
Programmable biquad 4, N1 coefficient byte[7:0]
Programmable biquad 4, N2 coefficient byte[31:24]
Programmable biquad 4, N2 coefficient byte[23:16]
Programmable biquad 4, N2 coefficient byte[15:8]
Programmable biquad 4, N2 coefficient byte[7:0]
Programmable biquad 4, D1 coefficient byte[31:24]
Programmable biquad 4, D1 coefficient byte[23:16]
Programmable biquad 4, D1 coefficient byte[15:8]
Programmable biquad 4, D1 coefficient byte[7:0]
Programmable biquad 4, D2 coefficient byte[31:24]
Programmable biquad 4, D2 coefficient byte[23:16]
Programmable biquad 4, D2 coefficient byte[15:8]
Programmable biquad 4, D2 coefficient byte[7:0]
Programmable biquad 5, N0 coefficient byte[31:24]
Programmable biquad 5, N0 coefficient byte[23:16]
Programmable biquad 5, N0 coefficient byte[15:8]
Programmable biquad 5, N0 coefficient byte[7:0]
Programmable biquad 5, N1 coefficient byte[31:24]
Programmable biquad 5, N1 coefficient byte[23:16]
Programmable biquad 5, N1 coefficient byte[15:8]
Programmable biquad 5, N1 coefficient byte[7:0]
Programmable biquad 5, N2 coefficient byte[31:24]
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Table 121. Page 0x02 Programmable Coefficient Registers (continued)
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
BQ5_N2_BYT2[7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Programmable biquad 5, N2 coefficient byte[23:16]
Programmable biquad 5, N2 coefficient byte[15:8]
Programmable biquad 5, N2 coefficient byte[7:0]
Programmable biquad 5, D1 coefficient byte[31:24]
Programmable biquad 5, D1 coefficient byte[23:16]
Programmable biquad 5, D1 coefficient byte[15:8]
Programmable biquad 5, D1 coefficient byte[7:0]
Programmable biquad 5, D2 coefficient byte[31:24]
Programmable biquad 5, D2 coefficient byte[23:16]
Programmable biquad 5, D2 coefficient byte[15:8]
Programmable biquad 5, D2 coefficient byte[7:0]
Programmable biquad 6, N0 coefficient byte[31:24]
Programmable biquad 6, N0 coefficient byte[23:16]
Programmable biquad 6, N0 coefficient byte[15:8]
Programmable biquad 6, N0 coefficient byte[7:0]
Programmable biquad 6, N1 coefficient byte[31:24]
Programmable biquad 6, N1 coefficient byte[23:16]
Programmable biquad 6, N1 coefficient byte[15:8]
Programmable biquad 6, N1 coefficient byte[7:0]
Programmable biquad 6, N2 coefficient byte[31:24]
Programmable biquad 6, N2 coefficient byte[23:16]
Programmable biquad 6, N2 coefficient byte[15:8]
Programmable biquad 6, N2 coefficient byte[7:0]
Programmable biquad 6, D1 coefficient byte[31:24]
Programmable biquad 6, D1 coefficient byte[23:16]
Programmable biquad 6, D1 coefficient byte[15:8]
Programmable biquad 6, D1 coefficient byte[7:0]
Programmable biquad 6, D2 coefficient byte[31:24]
Programmable biquad 6, D2 coefficient byte[23:16]
Programmable biquad 6, D2 coefficient byte[15:8]
Programmable biquad 6, D2 coefficient byte[7:0]
BQ5_N2_BYT3[7:0]
BQ5_N2_BYT4[7:0]
BQ5_D1_BYT1[7:0]
BQ5_D1_BYT2[7:0]
BQ5_D1_BYT3[7:0]
BQ5_D1_BYT4[7:0]
BQ5_D2_BYT1[7:0]
BQ5_D2_BYT2[7:0]
BQ5_D2_BYT3[7:0]
BQ5_D2_BYT4[7:0]
BQ6_N0_BYT1[7:0]
BQ6_N0_BYT2[7:0]
BQ6_N0_BYT3[7:0]
BQ6_N0_BYT4[7:0]
BQ6_N1_BYT1[7:0]
BQ6_N1_BYT2[7:0]
BQ6_N1_BYT3[7:0]
BQ6_N1_BYT4[7:0]
BQ6_N2_BYT1[7:0]
BQ6_N2_BYT2[7:0]
BQ6_N2_BYT3[7:0]
BQ6_N2_BYT4[7:0]
BQ6_D1_BYT1[7:0]
BQ6_D1_BYT2[7:0]
BQ6_D1_BYT3[7:0]
BQ6_D1_BYT4[7:0]
BQ6_D2_BYT1[7:0]
BQ6_D2_BYT2[7:0]
BQ6_D2_BYT3[7:0]
BQ6_D2_BYT4[7:0]
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7.6.2.2 Programmable Coefficient Registers: Page = 0x03
This register page (shown in Table 122) consists of the programmable coefficients for the biquad 7 to biquad 12
filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also
supports (by default) auto-incremented pages for the I2C and SPI burst writes and reads. After a transaction of
register address 0x7F, the device auto increments to the next page at register 0x08 to transact the next
coefficient value. These programmable coefficients are 32-bit, two’s complement numbers. For a successful
coefficient register transaction, the host device must write and read all the four bytes starting with the most
significant byte (BYT1) for a target coefficient register transaction. While using SPI for a coefficient register read
transaction, the device gives out first byte as dummy read byte therefore the host must read five bytes which
includes first byte as dummy read byte and the last four bytes corresponds to the coefficient register value
starting with the most significant byte (BYT1).
Table 122. Page 0x03 Programmable Coefficient Registers
ADDR
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
REGISTER
RESET
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DESCRIPTION
PAGE[7:0]
Device page register
BQ7_N0_BYT1[7:0]
BQ7_N0_BYT2[7:0]
BQ7_N0_BYT3[7:0]
BQ7_N0_BYT4[7:0]
BQ7_N1_BYT1[7:0]
BQ7_N1_BYT2[7:0]
BQ7_N1_BYT3[7:0]
BQ7_N1_BYT4[7:0]
BQ7_N2_BYT1[7:0]
BQ7_N2_BYT2[7:0]
BQ7_N2_BYT3[7:0]
BQ7_N2_BYT4[7:0]
BQ7_D1_BYT1[7:0]
BQ7_D1_BYT2[7:0]
BQ7_D1_BYT3[7:0]
BQ7_D1_BYT4[7:0]
BQ7_D2_BYT1[7:0]
BQ7_D2_BYT2[7:0]
BQ7_D2_BYT3[7:0]
BQ7_D2_BYT4[7:0]
BQ8_N0_BYT1[7:0]
BQ8_N0_BYT2[7:0]
BQ8_N0_BYT3[7:0]
BQ8_N0_BYT4[7:0]
BQ8_N1_BYT1[7:0]
BQ8_N1_BYT2[7:0]
BQ8_N1_BYT3[7:0]
BQ8_N1_BYT4[7:0]
BQ8_N2_BYT1[7:0]
BQ8_N2_BYT2[7:0]
BQ8_N2_BYT3[7:0]
BQ8_N2_BYT4[7:0]
BQ8_D1_BYT1[7:0]
BQ8_D1_BYT2[7:0]
BQ8_D1_BYT3[7:0]
BQ8_D1_BYT4[7:0]
BQ8_D2_BYT1[7:0]
BQ8_D2_BYT2[7:0]
BQ8_D2_BYT3[7:0]
Programmable biquad 7, N0 coefficient byte[31:24]
Programmable biquad 7, N0 coefficient byte[23:16]
Programmable biquad 7, N0 coefficient byte[15:8]
Programmable biquad 7, N0 coefficient byte[7:0]
Programmable biquad 7, N1 coefficient byte[31:24]
Programmable biquad 7, N1 coefficient byte[23:16]
Programmable biquad 7, N1 coefficient byte[15:8]
Programmable biquad 7, N1 coefficient byte[7:0]
Programmable biquad 7, N2 coefficient byte[31:24]
Programmable biquad 7, N2 coefficient byte[23:16]
Programmable biquad 7, N2 coefficient byte[15:8]
Programmable biquad 7, N2 coefficient byte[7:0]
Programmable biquad 7, D1 coefficient byte[31:24]
Programmable biquad 7, D1 coefficient byte[23:16]
Programmable biquad 7, D1 coefficient byte[15:8]
Programmable biquad 7, D1 coefficient byte[7:0]
Programmable biquad 7, D2 coefficient byte[31:24]
Programmable biquad 7, D2 coefficient byte[23:16]
Programmable biquad 7, D2 coefficient byte[15:8]
Programmable biquad 7, D2 coefficient byte[7:0]
Programmable biquad 8, N0 coefficient byte[31:24]
Programmable biquad 8, N0 coefficient byte[23:16]
Programmable biquad 8, N0 coefficient byte[15:8]
Programmable biquad 8, N0 coefficient byte[7:0]
Programmable biquad 8, N1 coefficient byte[31:24]
Programmable biquad 8, N1 coefficient byte[23:16]
Programmable biquad 8, N1 coefficient byte[15:8]
Programmable biquad 8, N1 coefficient byte[7:0]
Programmable biquad 8, N2 coefficient byte[31:24]
Programmable biquad 8, N2 coefficient byte[23:16]
Programmable biquad 8, N2 coefficient byte[15:8]
Programmable biquad 8, N2 coefficient byte[7:0]
Programmable biquad 8, D1 coefficient byte[31:24]
Programmable biquad 8, D1 coefficient byte[23:16]
Programmable biquad 8, D1 coefficient byte[15:8]
Programmable biquad 8, D1 coefficient byte[7:0]
Programmable biquad 8, D2 coefficient byte[31:24]
Programmable biquad 8, D2 coefficient byte[23:16]
Programmable biquad 8, D2 coefficient byte[15:8]
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Table 122. Page 0x03 Programmable Coefficient Registers (continued)
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
BQ8_D2_BYT4[7:0]
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Programmable biquad 8, D2 coefficient byte[7:0]
Programmable biquad 9, N0 coefficient byte[31:24]
Programmable biquad 9, N0 coefficient byte[23:16]
Programmable biquad 9, N0 coefficient byte[15:8]
Programmable biquad 9, N0 coefficient byte[7:0]
Programmable biquad 9, N1 coefficient byte[31:24]
Programmable biquad 9, N1 coefficient byte[23:16]
Programmable biquad 9, N1 coefficient byte[15:8]
Programmable biquad 9, N1 coefficient byte[7:0]
Programmable biquad 9, N2 coefficient byte[31:24]
Programmable biquad 9, N2 coefficient byte[23:16]
Programmable biquad 9, N2 coefficient byte[15:8]
Programmable biquad 9, N2 coefficient byte[7:0]
Programmable biquad 9, D1 coefficient byte[31:24]
Programmable biquad 9, D1 coefficient byte[23:16]
Programmable biquad 9, D1 coefficient byte[15:8]
Programmable biquad 9, D1 coefficient byte[7:0]
Programmable biquad 9, D2 coefficient byte[31:24]
Programmable biquad 9, D2 coefficient byte[23:16]
Programmable biquad 9, D2 coefficient byte[15:8]
Programmable biquad 9, D2 coefficient byte[7:0]
Programmable biquad 10, N0 coefficient byte[31:24]
Programmable biquad 10, N0 coefficient byte[23:16]
Programmable biquad 10, N0 coefficient byte[15:8]
Programmable biquad 10, N0 coefficient byte[7:0]
Programmable biquad 10, N1 coefficient byte[31:24]
Programmable biquad 10, N1 coefficient byte[23:16]
Programmable biquad 10, N1 coefficient byte[15:8]
Programmable biquad 10, N1 coefficient byte[7:0]
Programmable biquad 10, N2 coefficient byte[31:24]
Programmable biquad 10, N2 coefficient byte[23:16]
Programmable biquad 10, N2 coefficient byte[15:8]
Programmable biquad 10, N2 coefficient byte[7:0]
Programmable biquad 10, D1 coefficient byte[31:24]
Programmable biquad 10, D1 coefficient byte[23:16]
Programmable biquad 10, D1 coefficient byte[15:8]
Programmable biquad 10, D1 coefficient byte[7:0]
Programmable biquad 10, D2 coefficient byte[31:24]
Programmable biquad 10, D2 coefficient byte[23:16]
Programmable biquad 10, D2 coefficient byte[15:8]
Programmable biquad 10, D2 coefficient byte[7:0]
Programmable biquad 11, N0 coefficient byte[31:24]
Programmable biquad 11, N0 coefficient byte[23:16]
Programmable biquad 11, N0 coefficient byte[15:8]
Programmable biquad 11, N0 coefficient byte[7:0]
Programmable biquad 11, N1 coefficient byte[31:24]
Programmable biquad 11, N1 coefficient byte[23:16]
Programmable biquad 11, N1 coefficient byte[15:8]
Programmable biquad 11, N1 coefficient byte[7:0]
Programmable biquad 11, N2 coefficient byte[31:24]
Programmable biquad 11, N2 coefficient byte[23:16]
Programmable biquad 11, N2 coefficient byte[15:8]
BQ9_N0_BYT1[7:0]
BQ9_N0_BYT2[7:0]
BQ9_N0_BYT3[7:0]
BQ9_N0_BYT4[7:0]
BQ9_N1_BYT1[7:0]
BQ9_N1_BYT2[7:0]
BQ9_N1_BYT3[7:0]
BQ9_N1_BYT4[7:0]
BQ9_N2_BYT1[7:0]
BQ9_N2_BYT2[7:0]
BQ9_N2_BYT3[7:0]
BQ9_N2_BYT4[7:0]
BQ9_D1_BYT1[7:0]
BQ9_D1_BYT2[7:0]
BQ9_D1_BYT3[7:0]
BQ9_D1_BYT4[7:0]
BQ9_D2_BYT1[7:0]
BQ9_D2_BYT2[7:0]
BQ9_D2_BYT3[7:0]
BQ9_D2_BYT4[7:0]
BQ10_N0_BYT1[7:0]
BQ10_N0_BYT2[7:0]
BQ10_N0_BYT3[7:0]
BQ10_N0_BYT4[7:0]
BQ10_N1_BYT1[7:0]
BQ10_N1_BYT2[7:0]
BQ10_N1_BYT3[7:0]
BQ10_N1_BYT4[7:0]
BQ10_N2_BYT1[7:0]
BQ10_N2_BYT2[7:0]
BQ10_N2_BYT3[7:0]
BQ10_N2_BYT4[7:0]
BQ10_D1_BYT1[7:0]
BQ10_D1_BYT2[7:0]
BQ10_D1_BYT3[7:0]
BQ10_D1_BYT4[7:0]
BQ10_D2_BYT1[7:0]
BQ10_D2_BYT2[7:0]
BQ10_D2_BYT3[7:0]
BQ10_D2_BYT4[7:0]
BQ11_N0_BYT1[7:0]
BQ11_N0_BYT2[7:0]
BQ11_N0_BYT3[7:0]
BQ11_N0_BYT4[7:0]
BQ11_N1_BYT1[7:0]
BQ11_N1_BYT2[7:0]
BQ11_N1_BYT3[7:0]
BQ11_N1_BYT4[7:0]
BQ11_N2_BYT1[7:0]
BQ11_N2_BYT2[7:0]
BQ11_N2_BYT3[7:0]
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Table 122. Page 0x03 Programmable Coefficient Registers (continued)
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
BQ11_N2_BYT4[7:0]
BQ11_D1_BYT1[7:0]
BQ11_D1_BYT2[7:0]
BQ11_D1_BYT3[7:0]
BQ11_D1_BYT4[7:0]
BQ11_D2_BYT1[7:0]
BQ11_D2_BYT2[7:0]
BQ11_D2_BYT3[7:0]
BQ11_D2_BYT4[7:0]
BQ12_N0_BYT1[7:0]
BQ12_N0_BYT2[7:0]
BQ12_N0_BYT3[7:0]
BQ12_N0_BYT4[7:0]
BQ12_N1_BYT1[7:0]
BQ12_N1_BYT2[7:0]
BQ12_N1_BYT3[7:0]
BQ12_N1_BYT4[7:0]
BQ12_N2_BYT1[7:0]
BQ12_N2_BYT2[7:0]
BQ12_N2_BYT3[7:0]
BQ12_N2_BYT4[7:0]
BQ12_D1_BYT1[7:0]
BQ12_D1_BYT2[7:0]
BQ12_D1_BYT3[7:0]
BQ12_D1_BYT4[7:0]
BQ12_D2_BYT1[7:0]
BQ12_D2_BYT2[7:0]
BQ12_D2_BYT3[7:0]
BQ12_D2_BYT4[7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Programmable biquad 11, N2 coefficient byte[7:0]
Programmable biquad 11, D1 coefficient byte[31:24]
Programmable biquad 11, D1 coefficient byte[23:16]
Programmable biquad 11, D1 coefficient byte[15:8]
Programmable biquad 11, D1 coefficient byte[7:0]
Programmable biquad 11, D2 coefficient byte[31:24]
Programmable biquad 11, D2 coefficient byte[23:16]
Programmable biquad 11, D2 coefficient byte[15:8]
Programmable biquad 11, D2 coefficient byte[7:0]
Programmable biquad 12, N0 coefficient byte[31:24]
Programmable biquad 12, N0 coefficient byte[23:16]
Programmable biquad 12, N0 coefficient byte[15:8]
Programmable biquad 12, N0 coefficient byte[7:0]
Programmable biquad 12, N1 coefficient byte[31:24]
Programmable biquad 12, N1 coefficient byte[23:16]
Programmable biquad 12, N1 coefficient byte[15:8]
Programmable biquad 12, N1 coefficient byte[7:0]
Programmable biquad 12, N2 coefficient byte[31:24]
Programmable biquad 12, N2 coefficient byte[23:16]
Programmable biquad 12, N2 coefficient byte[15:8]
Programmable biquad 12, N2 coefficient byte[7:0]
Programmable biquad 12, D1 coefficient byte[31:24]
Programmable biquad 12, D1 coefficient byte[23:16]
Programmable biquad 12, D1 coefficient byte[15:8]
Programmable biquad 12, D1 coefficient byte[7:0]
Programmable biquad 12, D2 coefficient byte[31:24]
Programmable biquad 12, D2 coefficient byte[23:16]
Programmable biquad 12, D2 coefficient byte[15:8]
Programmable biquad 12, D2 coefficient byte[7:0]
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7.6.2.3 Programmable Coefficient Registers: Page = 0x04
This register page (shown in Table 123) consists of the programmable coefficients for mixer 1 to mixer 4 and the
first-order IIR filter.All mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format. The
value of 0x7FFFFFFF is equivalent to +1 (0-dB gain), the value 0x00000000 is equivalent to mute (zero data)
and all values in between set the mixer attenuation computed using Equation 4. If the MSB is set to '1' then the
attenuation remains the same but the signal phase is inverted. All IIR filter programmable coefficients are 32-bit,
two’s complement numbers. For a successful coefficient register transaction, the host device must write and read
all the four bytes starting with the most significant byte (BYT1) for a target coefficient register transaction. While
using SPI for a coefficient register read transaction, the device gives out first byte as dummy read byte therefore
the host must read five bytes which includes first byte as dummy read byte and the last four bytes corresponds
to the coefficient register value starting with the most significant byte (BYT1).
hex2dec (value) / 231
(4)
Table 123. Page 0x04 Programmable Coefficient Registers
ADDR
REGISTER
RESET
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DESCRIPTION
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
PAGE[7:0]
Device page register
MIX1_CH1_BYT1[7:0]
MIX1_CH1_BYT2[7:0]
MIX1_CH1_BYT3[7:0]
MIX1_CH1_BYT4[7:0]
MIX1_CH2_BYT1[7:0]
MIX1_CH2_BYT2[7:0]
MIX1_CH2_BYT3[7:0]
MIX1_CH2_BYT4[7:0]
MIX1_CH3_BYT1[7:0]
MIX1_CH3_BYT2[7:0]
MIX1_CH3_BYT3[7:0]
MIX1_CH3_BYT4[7:0]
MIX1_CH4_BYT1[7:0]
MIX1_CH4_BYT2[7:0]
MIX1_CH4_BYT3[7:0]
MIX1_CH4_BYT4[7:0]
MIX2_CH1_BYT1[7:0]
MIX2_CH1_BYT2[7:0]
MIX2_CH1_BYT3[7:0]
MIX2_CH1_BYT4[7:0]
MIX2_CH2_BYT1[7:0]
MIX2_CH2_BYT2[7:0]
MIX2_CH2_BYT3[7:0]
MIX2_CH2_BYT4[7:0]
MIX2_CH3_BYT1[7:0]
MIX2_CH3_BYT2[7:0]
MIX2_CH3_BYT3[7:0]
MIX2_CH3_BYT4[7:0]
MIX2_CH4_BYT1[7:0]
MIX2_CH4_BYT2[7:0]
MIX2_CH4_BYT3[7:0]
MIX2_CH4_BYT4[7:0]
MIX3_CH1_BYT1[7:0]
MIX3_CH1_BYT2[7:0]
MIX3_CH1_BYT3[7:0]
MIX3_CH1_BYT4[7:0]
MIX3_CH2_BYT1[7:0]
MIX3_CH2_BYT2[7:0]
Digital mixer 1, channel 1 coefficient byte[31:24]
Digital mixer 1, channel 1 coefficient byte[23:16]
Digital mixer 1, channel 1 coefficient byte[15:8]
Digital mixer 1, channel 1 coefficient byte[7:0]
Digital mixer 1, channel 2 coefficient byte[31:24]
Digital mixer 1, channel 2 coefficient byte[23:16]
Digital mixer 1, channel 2 coefficient byte[15:8]
Digital mixer 1, channel 2 coefficient byte[7:0]
Digital mixer 1, channel 3 coefficient byte[31:24]
Digital mixer 1, channel 3 coefficient byte[23:16]
Digital mixer 1, channel 3 coefficient byte[15:8]
Digital mixer 1, channel 3 coefficient byte[7:0]
Digital mixer 1, channel 4 coefficient byte[31:24]
Digital mixer 1, channel 4 coefficient byte[23:16]
Digital mixer 1, channel 4 coefficient byte[15:8]
Digital mixer 1, channel 4 coefficient byte[7:0]
Digital mixer 2, channel 1 coefficient byte[31:24]
Digital mixer 2, channel 1 coefficient byte[23:16]
Digital mixer 2, channel 1 coefficient byte[15:8]
Digital mixer 2, channel 1 coefficient byte[7:0]
Digital mixer 2, channel 2 coefficient byte[31:24]
Digital mixer 2, channel 2 coefficient byte[23:16]
Digital mixer 2, channel 2 coefficient byte[15:8]
Digital mixer 2, channel 2 coefficient byte[7:0]
Digital mixer 2, channel 3 coefficient byte[31:24]
Digital mixer 2, channel 3 coefficient byte[23:16]
Digital mixer 2, channel 3 coefficient byte[15:8]
Digital mixer 2, channel 3 coefficient byte[7:0]
Digital mixer 2, channel 4 coefficient byte[31:24]
Digital mixer 2, channel 4 coefficient byte[23:16]
Digital mixer 2, channel 4 coefficient byte[15:8]
Digital mixer 2, channel 4 coefficient byte[7:0]
Digital mixer 3, channel 1 coefficient byte[31:24]
Digital mixer 3, channel 1 coefficient byte[23:16]
Digital mixer 3, channel 1 coefficient byte[15:8]
Digital mixer 3, channel 1 coefficient byte[7:0]
Digital mixer 3, channel 2 coefficient byte[31:24]
Digital mixer 3, channel 2 coefficient byte[23:16]
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Table 123. Page 0x04 Programmable Coefficient Registers (continued)
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
MIX3_CH2_BYT3[7:0]
MIX3_CH2_BYT4[7:0]
MIX3_CH3_BYT1[7:0]
MIX3_CH3_BYT2[7:0]
MIX3_CH3_BYT3[7:0]
MIX3_CH3_BYT4[7:0]
MIX3_CH4_BYT1[7:0]
MIX3_CH4_BYT2[7:0]
MIX3_CH4_BYT3[7:0]
MIX3_CH4_BYT4[7:0]
MIX4_CH1_BYT1[7:0]
MIX4_CH1_BYT2[7:0]
MIX4_CH1_BYT3[7:0]
MIX4_CH1_BYT4[7:0]
MIX4_CH2_BYT1[7:0]
MIX4_CH2_BYT2[7:0]
MIX4_CH2_BYT3[7:0]
MIX4_CH2_BYT4[7:0]
MIX4_CH3_BYT1[7:0]
MIX4_CH3_BYT2[7:0]
MIX4_CH3_BYT3[7:0]
MIX4_CH3_BYT4[7:0]
MIX4_CH4_BYT1[7:0]
MIX4_CH4_BYT2[7:0]
MIX4_CH4_BYT3[7:0]
MIX4_CH4_BYT4[7:0]
IIR_N0_BYT1[7:0]
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Digital mixer 3, channel 2 coefficient byte[15:8]
Digital mixer 3, channel 2 coefficient byte[7:0]
Digital mixer 3, channel 3 coefficient byte[31:24]
Digital mixer 3, channel 3 coefficient byte[23:16]
Digital mixer 3, channel 3 coefficient byte[15:8]
Digital mixer 3, channel 3 coefficient byte[7:0]
Digital mixer 3, channel 4 coefficient byte[31:24]
Digital mixer 3, channel 4 coefficient byte[23:16]
Digital mixer 3, channel 4 coefficient byte[15:8]
Digital mixer 3, channel 4 coefficient byte[7:0]
Digital mixer 4, channel 1 coefficient byte[31:24]
Digital mixer 4, channel 1 coefficient byte[23:16]
Digital mixer 4, channel 1 coefficient byte[15:8]
Digital mixer 4, channel 1 coefficient byte[7:0]
Digital mixer 4, channel 2 coefficient byte[31:24]
Digital mixer 4, channel 2 coefficient byte[23:16]
Digital mixer 4, channel 2 coefficient byte[15:8]
Digital mixer 4, channel 2 coefficient byte[7:0]
Digital mixer 4, channel 3 coefficient byte[31:24]
Digital mixer 4, channel 3 coefficient byte[23:16]
Digital mixer 4, channel 3 coefficient byte[15:8]
Digital mixer 4, channel 3 coefficient byte[7:0]
Digital mixer 4, channel 4 coefficient byte[31:24]
Digital mixer 4, channel 4 coefficient byte[23:16]
Digital mixer 4, channel 4 coefficient byte[15:8]
Digital mixer 4, channel 4 coefficient byte[7:0]
Programmable first-order IIR, N0 coefficient byte[31:24]
Programmable first-order IIR, N0 coefficient byte[23:16]
Programmable first-order IIR, N0 coefficient byte[15:8]
Programmable first-order IIR, N0 coefficient byte[7:0]
Programmable first-order IIR, N1 coefficient byte[31:24]
Programmable first-order IIR, N1 coefficient byte[23:16]
Programmable first-order IIR, N1 coefficient byte[15:8]
Programmable first-order IIR, N1 coefficient byte[7:0]
Programmable first-order IIR, D1 coefficient byte[31:24]
Programmable first-order IIR, D1 coefficient byte[23:16]
Programmable first-order IIR, D1 coefficient byte[15:8]
Programmable first-order IIR, D1 coefficient byte[7:0]
IIR_N0_BYT2[7:0]
IIR_N0_BYT3[7:0]
IIR_N0_BYT4[7:0]
IIR_N1_BYT1[7:0]
IIR_N1_BYT2[7:0]
IIR_N1_BYT3[7:0]
IIR_N1_BYT4[7:0]
IIR_D1_BYT1[7:0]
IIR_D1_BYT2[7:0]
IIR_D1_BYT3[7:0]
IIR_D1_BYT4[7:0]
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PCMD3180 is a multichannel, pulse-density-modulation (PDM) input to time-division multiplexing (TDM) or
I2S audio output converter that supports output sample rates of up to 768 kHz. The device supports up to eight
digital pulse density modulation (PDM) microphones for simultaneous recording applications.
Communication to the PCMD3180 for configuration of the control registers is supported using an I2C or SPI
interface. The device supports a highly flexible, audio serial interface (TDM, I2S, and LJ) to transmit audio data
seamlessly in the system across devices.
8.2 Typical Applications
8.2.1 Eight-Channel Digital PDM Microphone Recording
Figure 161 shows a typical configuration of the PCMD3180 for an application using eight digital PDM MEMS
microphones with simultaneous recording operation using an I2C control interface and the TDM audio data slave
interface. If the MICBIAS output is not used in the system then the 1 µF capacitor for the MICBIAS pin is not
must.
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Typical Applications (continued)
10 ꢀF
1 ꢀF
VDD
(3.0 V to 3.6 V)
0.1 ꢀF
0.1 ꢀF
1 ꢀF
1 ꢀF
GND
GND
GND
GND
10 ꢀF
VDD
SEL
CLK
VDD
0.1 ꢀF
GND
DREG
DMIC1
Rterm
0.1 ꢀF
PDMDIN1_GPI1
VSS
DOUT
GND
VDD
CLK
PDMCLK1_GPO1
VDD
0.1 ꢀF
GND
3.3 V
(3.0 V to 3.6 V)
OR
SEL
VSS
Rterm
DMIC2
DOUT
Rterm
Rterm
10 ꢀF
VDD
SEL
CLK
1.8 V
(1.65 V to 1.95 V)
VDD
0.1 ꢀF
GND
DMIC3
PDMDIN2_GPI2
PDMCLK2_GPO2
DOUT
IOVDD
VSS
0.1 ꢀF
VDD
SEL
VSS
CLK
VDD
0.1 ꢀF
GND
GND
Rterm
DMIC4
PCMD3180
Thermal Pad
(VSS)
DOUT
Rterm
Rterm
GND
VDD
SEL
VSS
CLK
VDD
0.1 ꢀF
GND
DMIC5
ADDR1_MISO
(ADDR1)
PDMDIN3_GPI3
PDMCLK3_GPO3
DOUT
GND
GND
VDD
SEL
CLK
VDD
0.1 ꢀF
GND
Rterm
DMIC6
ADDR0_SCLK
(ADDR0)
VSS
DOUT
Rterm
Rterm
VDD
SEL
CLK
VDD
0.1 ꢀF
GND
DMIC7
PDMDIN4_GPI4
PDMCLK4_GPO4
VSS
DOUT
VDD
CLK
VDD
0.1 ꢀF
GND
SEL
VSS
Rterm
DMIC8
DOUT
R ꢁ
R ꢁ
Rterm
Host
Processor
Figure 161. Eight-Channel Digital PDM Microphone Recording Diagram
8.2.1.1 Design Requirements
The supply decoupling capacitors must be used ceramic type with low ESR. Table 124 lists the design
parameters for this application.
Table 124. Design Parameters
KEY PARAMETER
SPECIFICATION
AVDD
3.3 V
11.7 mA (PLL on, eight-channel recording, fS = 48 kHz, PDMCLKx =
= 64 × fS)
AVDD supply current consumption
IOVDD
1.8 V or 3.3 V
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8.2.1.2 Detailed Design Procedure
This section describes the necessary steps to configure the PCMD3180 for this specific application. The
following steps provide a sequence of items that must be executed in the time between powering the device up
and reading data from the device or transitioning from one mode to another mode of operation.
1. Apply power to the device:
a. Power up the IOVDD and AVDD power supplies, keeping the SHDNZ pin voltage low
b. The device now goes into hardware shutdown mode (ultra-low-power mode < 1 µA)
2. Transition from hardware shutdown mode to sleep mode (or software shutdown mode):
a. Release SHDNZ only when the IOVDD and AVDD power supplies settle to the steady-state operating
voltage
b. Wait for at least 1 ms to allow the device to initialize the internal registers initialization
c. The device now goes into sleep mode (low-power mode < 10 µA)
3. Transition from sleep mode to active mode whenever required for the recording operation:
a. Wake up the device by writing to P0_R2 to disable sleep mode
b. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence
c. Override the default configuration registers or programmable coefficients value as required (this step is
optional)
d. Configure channel 1 to channel 4 (CHx_INSRC) for the digital microphone as the input source for
recording
e. Configure GPO1 to GPO4 (GPOx_CFG) as the PDMCLK output
f. Configure GPI1 to GPI4 (GPI1x_CFG) as PDMDIN1 to PDMDIN4, respectively
g. Enable all desired input channels by writing to P0_R115
h. Enable all desired audio serial interface output channels by writing to P0_R116
i. Power-up the PDM converter and PLL by writing to P0_R117
j. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
This specific step can be done at any point in the sequence after step a.
See the Phase-Locked Loop (PLL) and Clock Generation section for supported sample rates and the
BCLK to FSYNC ratio.
k. The device recording data is now sent to the host processor using the TDM audio serial data bus
4. Transition from active mode to sleep mode (again) as required in the system for low-power operation:
a. Enter sleep mode by writing to P0_R2 to enable sleep mode
b. Wait at least 6 ms (when FSYNC = 48 kHz) for the volume to ramp down and for all blocks to power
down
c. Read P0_R119 to check the device shutdown and sleep mode status
d. If the device P0_R119_D7 status bit is 1'b1 then stop FSYNC and BCLK in the system
e. The device now goes into sleep mode (low-power mode < 10 µA) and retains all register values
5. Transition from sleep mode to active mode (again) as required for the recording operation:
a. Wake up the device by writing to P0_R2 to disable sleep mode
b. Wait at least 1 ms to allow the device to complete the internal wake-up sequence
c. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
d. The device recording data are now sent to the host processor using the TDM audio serial data bus
6. Repeat step 4 and step 5 as required for mode transitions
7. Assert the SHDNZ pin low to enter hardware shutdown mode (again) at any time
8. Follow step 2 onwards to exit hardware shutdown mode (again)
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8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
This section provides a typical EVM I2C register control script that shows how to set up the PCMD3180 in an
eight-channel digital PDM microphone recording mode.
# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#
#
# ==> comment delimiter
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the PCMD3180EVM user guide for jumper settings and audio connections.
#
# PDM 8-channel : PDMDIN1 - Ch1 and Ch2, PDMDIN2 - Ch3 and Ch4,
#
PDMDIN3 - Ch5 and Ch6, PDMDIN4 - Ch7 and Ch8
# PDMCLKx = 2.8224 MHz (PDMCLKx/FSYNC = 64)
# FSYNC = 44.1 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
# Wake-up device by I2C write into P0_R2 using internal AREG
w 98 02 81
#
# Configure CH1_INSRC as Digital PDM Input by I2C write into P0_R60
w 98 3C 40
#
# Configure CH2_INSRC as Digital PDM Input by I2C write into P0_R65
w 98 41 40
#
# Configure CH3_INSRC as Digital PDM Input by I2C write into P0_R70
w 98 46 40
#
# Configure CH4_INSRC as Digital PDM Input by I2C write into P0_R75
w 98 4B 40
#
# Configure PDMCLK1_GPO1 as PDMCLK by I2C write into P0_R34
w 98 22 41
#
# Configure PDMCLK1_GPO2 as PDMCLK by I2C write into P0_R35
w 98 23 41
#
# Configure PDMCLK1_GPO3 as PDMCLK by I2C write into P0_R36
w 98 24 41
#
# Configure PDMCLK1_GPO4 as PDMCLK by I2C write into P0_R37
w 98 25 41
#
# Configure PDMDIN1_GPI1 and PDMDIN2_GPI2 as PDMDIN1 and PDMDIN2 by I2C write into P0_R43
w 98 2B 45
#
# Configure PDMDIN3_GPI3 and PDMDIN4_GPI4 as PDMDIN3 and PDMDIN4 by I2C write into P0_R44
w 98 2C 67
#
# Enable Input Ch-1 to Ch-8 by I2C write into P0_R115
w 98 73 FF
#
# Enable ASI Output Ch-1 to Ch-8 slots by I2C write into P0_R116
w 98 74 FF
#
# Power-up PDM converter and PLL by I2C write into P0_R117
w 98 75 60
#
# Apply FSYNC = 44.1 kHz and BCLK = 11.2896 MHz and
# Start recording data by host on ASI bus with TDM protocol 32-bits channel wordlength
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8.2.1.3 Application Curves
Measurements are done on the EVM by feeding the device PDM digital input signal using audio precision. In the
system application, the device performance is expected to be limited by single-bit PDM modulator digital
microphone output performance.
-60
0
Channel-1
Channel-1
Channel-2
Channel-2
-20
Channel-3
Channel-3
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
-70
-80
Channel-4
Channel-5
Channel-6
Channel-7
Channel-8
-40
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
-120
-105
-90
-75
-60
-45
-30
-15
-1
20
50
100
500
1000
5000 10000 20000
Input Amplitude (dB)
PTCHMDD+
Frequency (Hz)
Freq
PCMD
Fourth order PDM modulator with PDMCLKx = 2.8224 MHz
Fourth order PDM modulator with PDMCLKx = 2.8224 MHz
Figure 163. THD+N vs Input Amplitude
Figure 162. FFT With a –60-dBr Input
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8.3 What to Do and What Not to Do
In master mode operation with I2S or LJ format, the device generates FSYNC half a cycle earlier than the normal
protocol timing behavior expected. This timing behavior can still function for most of the system, however for
further details and a suggested workaround for this weakness, see the Configuring and Operating the
TLV320ADCx140 as Audio Bus Master application report.
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9 Power Supply Recommendations
The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, keep
the SHDNZ pin low until the IOVDD supply voltage settles to a stable and supported operating voltage range.
After all supplies are stable, set the SHDNZ pin high to initialize the device.
For the supply power-up requirement, t1 and t2 must be at least 100 µs. For the supply power-down requirement,
t3 and t4 must be at least 10 ms. This timing (as shown in Figure 164) allows the device to ramp down the
volume on the record data, power down the analog and digital blocks, and put the device into hardware
shutdown mode. The device can also be immediately put into hardware shutdown mode from active mode if
SHDNZ_CFG[1:0] is set to 2'b00 using the P0_R5_D[3:2] bits. In that case, t3 and t4 are required to be at least
100 µs.
AVDD
t1
t3
IOVDD
SHDNZ
t4
t2
Figure 164. Power-Supply Sequencing Requirement Timing Diagram
Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a
power-up event is at least 100 ms. For supply ramp rate slower than 0.1 V/ms, host device must apply a
software reset as first transaction before doing any device configuration.
After releasing SHDNZ, or after a software reset, delay any additional I2C or SPI transactions to the device for at
least 2 ms to allow the device to initialize the internal registers. See the Device Functional Modes section for
details on how the device operates in various modes after the device power supplies are settled to the
recommended operating voltage levels.
The PCMD3180 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG, and
an analog regulator, AREG. However, if the AVDD voltage is less than 1.98 V in the system, then short the
AREG and AVDD pins onboard and do not enable the internal AREG by keeping the AREG_SELECT bit to 1b'0
(default value) of P0_R2. If the AVDD supply used in the system is higher than 2.7 V, then the host device can
set AREG_SELECT to 1'b1 while exiting sleep mode to allow the device internal regulator to generate the AREG
supply.
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10 Layout
10.1 Layout Guidelines
Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in
the context of a specific PCB design. However, the following guidelines can optimize the device performance:
•
Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, which is the area
directly under the device, to the ground planes. This connection helps dissipate heat from the device.
•
•
•
The decoupling capacitors for the power supplies must be placed close to the device pins.
The supply decoupling capacitors must be used ceramic type with low ESR.
Route the analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing
digital and analog signals to prevent undesirable crosstalk.
•
•
•
•
•
The device internal voltage references must be filtered using external capacitors. Place the filter capacitors
near the VREF pin for optimal performance.
Directly tap the MICBIAS pin to avoid common impedance when routing the biasing or supply traces for
multiple microphones to avoid coupling across microphones.
Directly short the VREF and MICBIAS external capacitors ground terminal to the AVSS pin without using any
vias for this connection trace.
Place the MICBIAS capacitor (with low equivalent series resistance) close to the device with minimal trace
impedance.
Use ground planes to provide the lowest impedance for power and signal current between the device and the
decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and
all device grounds must be connected directly to that area.
10.2 Layout Example
Audio output interface connections
24
1
SDA_SSZ
AVDD
AREG
VREF
AVSS
VSS
SCL_MOSI
ADD0_SCLK
ADD1_MISO
MICBIAS
SHDNZ
Audio input signal connections
Figure 165. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, Multiple TLV320ADCx140 Devices With Shared TDM and I2C Bus application report
Texas Instruments, Configuring and Operating the TLV320ADCx140 as Audio Bus Master application report
Texas Instruments, TLV320ADCx140 Sampling Rates and Programmable Processing Blocks Supported
application report
•
Texas Instruments, TLV320ADCx140 Programmable Bi-Quad Filter Configuration and Application application
report
•
•
Texas Instruments, Analog Microphone and ADC System in Far-field Application application report
Texas Instruments, TLV320ADCx140 Power Consumption Matrix Across Various Usage Scenarios
application report
•
•
Texas Instruments, ADCx140EVM-PDK user's guide
Texas Instruments, PurePath™ Console Graphical Development Suite for Audio System Design and
Development
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
PurePath, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCMD3180IRTWR
PCMD3180IRTWT
ACTIVE
ACTIVE
WQFN
WQFN
RTW
RTW
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
PDM3180
PDM3180
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2021
Addendum-Page 2
GENERIC PACKAGE VIEW
RTW 24
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224801/A
www.ti.com
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