PCSD93501QRYCTQ1 [TI]
同步降压单片智能功率级 | RYC | 16 | -40 to 150;
| 型号： | PCSD93501QRYCTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 同步降压单片智能功率级 | RYC | 16 | -40 to 150 |
| 文件： | 总14页 (文件大小：1164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD93501-Q1
ZHCSR15A – OCTOBER 2022 – REVISED DECEMBER 2022
CSD93501-Q1 同步降压单片智能功率级
1 特性
3 说明
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30A TDC 电流，60A 峰值工作电流能力
CSD93501-Q1 是一款经过高度优化的智能功率级，适
用于具有 5V 输入的高功率、高密度应用（包括汽车应
用）。这款产品将驱动器 IC 和功率 MOSFET 集成在
一个硅片上，用于完善功率级开关功能。它还集成了准
确电流检测和温度感测功能，以简化系统设计并提高准
确度。此单片设计可实现高开关频率，具有高效率、低
噪声以及高电流和温度检测精度。此产品采用小型 3.5
x 6.25mm QFN 封装。该 PCB 封装已经过优化，可帮
助减少设计时间并轻松完成总体系统设计。
2MHz、5Vin、1Vo 时峰值系统效率为 91.2%
工作频率高（高达 2.2 MHz）
温度补偿双向电流感应
模拟温度输出
兼容 3.3V 和 5V PWM 信号
三态 PWM 输入
集成自举开关
优化了击穿保护死区时间
故障保护
CSD93501-Q1 提供的主要差异化特性包括：基于高侧
FET 电流检测的逐周期电流限制/保护、过热保护、负
过流检测和开路引脚检测，可提高系统可靠性。
– 过热 (OT)
– 逐脉冲过流限制
– Catatraphic 过流保护 (OCP)
故障检测
器件信息
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器件型号
封装(1)
封装尺寸（标称值）
– 高侧短路 (HSS)
CSD93501-Q1
WQFN
3.5 mm × 6.25 mm
– 逐脉冲负过流 (negOC) 检测
体中断 (BB) 模式和二极管仿真模式 (DEM) 运行
3.5 x 6.25mm QFN 封装
超低电感封装
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(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
系统已优化的 PCB 空间占用
符合 AEC-Q100 1 级标准
2 应用
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多相同步降压转换器
– 高频应用
– 大电流、低占空比应用
简化版应用
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS757
CSD93501-Q1
ZHCSR15A – OCTOBER 2022 – REVISED DECEMBER 2022
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Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
7 Device and Documentation Support..............................6
7.1 Device Support........................................................... 6
7.2 Documentation Support.............................................. 6
7.3 接收文档更新通知....................................................... 6
7.4 支持资源......................................................................6
7.5 Trademarks.................................................................6
7.6 Electrostatic Discharge Caution..................................6
7.7 术语表......................................................................... 6
8 Mechanical, Packaging, and Orderable Information....7
8.1 Package Option Addendum........................................8
8.2 Tape and Reel Information..........................................9
4 Revision History
Changes from Revision * (October 2022) to Revision A (December 2022)
Page
Max Peak Output Current updated to 60A (from 75A)........................................................................................4
Max Operating Junction Temperature updated to 125C (from 150C).................................................................4
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•
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5 Pin Configuration and Functions
6
5
4
3
2
1
PWM
AGND
BOOT
16 EN
15
7
8
LSET
BOOTR
17
VIN
9
VIN
14 VIN
18
PGND
PGND
13 PGND
10
11
VSW
12
VDRV
图 5-1. RYC Package, 18-PIn WQFN-FCRLF (Top View)
表 5-1. Pin Functions
PIN
DESCRIPTION
NAME
AGND
VDD
NO.
1
Analog ground.
2
Supply voltage for internal circuitry. This pin should be bypassed directly to AGND.
External reference voltage input for current sensing amplifier.
Output of current sensing amplifier. V(IOUT) - V(REFIN) is proportional to the phase current.
REFIN
IOUT
3
4
Temperature Amplifier Output. Reports a voltage proportional to the IC temperature. An ORing diode is
integrated in the IC. When used in multiphase applications, a single wire can be used to connect the
TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3V if
any one of the thermal shutdown, over current protection, or high-side short detection circuits is tripped.
TAO/FLT
5
Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high.
Logic high sets control FET gate high and sync FET gate low. Either body break or DCM will be inabled
if PWM stays in Hi-Z for greater than the tri-state shutdown hold-off time (tSHT).
PWM
6
7
8
Bootstrap capacitor connection. Connect a minimum 0.1 µF 10V X7R ceramic capacitor from BOOT to
BOOTR pin. The bootstrap capacitor provides the charge to switch the HS FET. The bootstrap diode is
integrated.
BOOT
BOOTR
Bootstrap capacitor connectioin return path for the HS FET floating driver. Connected to VSW node
internally. Connect a minimum 0.1 µF 10V X7R ceramic capacitor from BOOT to BOOTR pin. The
bootstrap capacitor provides the charge to switch the HS FET. The bootstrap diode is integrated.
VIN
9, 14, 17
Input voltage ping. Connect input capacitors close to this pin.
PGND
VSW
VDRV
LSET
10, 13, 18
Power ground.
11
12
15
Phase node connecting the HS FET source and LS FET drain; pin connection to the output inductor.
Supply voltage for the gate drivers. This pin should be bypassed to PGND.
A resistor from this pin to PGND sets the inductor value for the internal current sensing circuitry.
Enable input pin. The gate driver responds to PWM input when EN is logic high. When EN is logic low,
both FET gates are actively driven off.
EN
16
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6 Specifications
6.1 Absolute Maximum Ratings
TA = 25℃ (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
11
11
11
6
UNIT
VIN to PGND
VIN to VSW
V
V
V
V
V
VSW to PGND
VDD to AGND
VDDRV to PGND
6
EN, TAO/FLT,
LSET to AGND
-0.3
-0.3
-0.3
VDD + 0.3
V
V
V
IOUT, REFIN,
VOS, PWM to
PGND
6
BOOT to
VDD + 0.3
BOOTR(2)
BOOT to PGND
-0.3
-40
-55
17
150
150
V
TJ
Operating junction temperature
Storage temperature
°C
°C
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
PARAMETER
MIN
MAX
UNIT
Human body model (HBM), per AEC-
Q101-001, level H2, all pins
-2000
2000
Charged device model (CDM), per AEC-
Q100-011, level C4B, corner pins
V(ESD)
Electrostatic discharge
-750
-500
750
500
V
Charged device model (CDM), per AEC-
Q100-011, level C4B, all other pins
6.3 Recommended Operating Conditions
TA = 25 ℃ (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VDD
VDRV
VIN
Driver Supply Voltage
Gate Drive Voltage
Input Supply Voltage(2)
Output Voltage
4.5
4.5
2.7
5.5
5.5
5.5
2
V
V
VOUT
V
PWM to PGND
5.5
30
V
ITDC
Thermal Design Current
Peak Output Current
Switching Frequency
A
VIN = 5V, VDD = 5V, VDRV = 5V, VOUT = 1V, fSW = 1000
kHz
IOUT-PK
fSW
60
A
CBST = 0.1 µF (min) VIN = 5V, VOUT = 1V
2200
kHz
fSW = 1 MHz, for transient response, not for steady
state operation
DMAX
Max Duty Cycle
90
20
%
Minimum PWM On Time
ns
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6.3 Recommended Operating Conditions (continued)
TA = 25 ℃ (unless otherwise noted)(1)
MIN
MAX
UNIT
Operating Junction
Temperature
TJ
-40
125
°C
(1) Exposure to operating conditions beyond those specified in Recommended Operating Conditions may affect the long term reliability of
the device.
(2) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
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7 Device and Documentation Support
7.1 Device Support
7.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
7.2 Documentation Support
7.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
7.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
7.5 Trademarks
TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
7.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
7.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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8.1 Package Option Addendum
Package
Type
Package
Drawing
MSL Peak
Temp (3)
Orderable Device
Status (1)
Pins
Package Qty
Eco Plan (2)
Lead/Ball Finish
Op Temp (°C) Device Marking(4)(5)
Level-3-260C-168
HR
PCSD93501QRYCTQ1 PRE_PROD
WQFN
RYC
16
500
PB-Free (RoHS Exempt)
CU NIPDAU
–40 to 125
P501Q102
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided
by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider
certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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8.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
PCSD93501QRYCTQ1
WQFN
RYC
16
500
330
12.4
3.80
6.55
0.95
8.00
12.00
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
RYC 16
SPQ
Length (mm) Width (mm)
338 355
Height (mm)
PCSD93501QRYCTQ1
WQFN
500
50
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PACKAGE OUTLINE
WQFN-FCRLF - 0.7 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RYC0016A
6.35
6.15
B
A
3.6
3.4
PIN 1 INDEX AREA
(0.20)
0.10 MIN
(0.1) TYP
SECTION A-A
TYPICAL
0.7
0.6
C
SEATING PLANE
0.01
0.00
0.08
C
0.23
0.13
34X
0.3
0.2
A
16X
(0.375)
(0.35)
10
0.1
0.05
C
B
(0.20) TYP
(0.12) TYP
C
6
9
0.9±0.1
A
A
11
2X 2.5
0.000 PKG ℄
0.55
16X
0.45
2
1
0.9±0.1
12
16
14
13
3X (0.625)
32X 0.5
PIN 1 ID
3X (0.5)
(OPTIONAL)
2X 5.5
4226155/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN-FCRLF - 0.7 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RYC0016A
(0.05) MIN
ALL AROUND
TYP
4X (0.375)
16
14
13
4X (0.5)
(1.6)
12
1
6X (1.08)
(0.9)
2
2X (0.6)
11
0.000 PKG ℄
2X (2.5)
8X (0.7)
2X (0.6)
(0.9)
6X (1.08)
6
(1.6)
(Ø0.2) TYP
9
10
(R 0.05) TYP
(0.325) TYP
34X (0.25)
32X (0.5)
2X (5.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226155/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN-FCRLF - 0.7 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RYC0016A
4X (0.375)
16
14
13
4X (0.5)
(1.6)
12
1
2
18
11
17
2X (2.5)
0.000 PKG ℄
3X (1.63)
8X (0.7)
6
(1.6)
9
(1.04)
10
(R 0.05) TYP
2X (0.98)
32X (0.5)
(0.325) TYP
34X (0.25)
5X (0.375)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SOLDER PASTE COVERAGE:
PIN 17 : 86%
PIN 18 : 81%
SCALE: 15X
4226155/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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重要声明和免责声明
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保。
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