PGA103 [TI]
可编程增益放大器;
| 型号： | PGA103 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 可编程增益放大器 放大器 |
| 文件： | 总10页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
PGA103
Programmable Gain
AMPLIFIER
FEATURES
● DIGITALLY PROGRAMABLE GAINS:
DESCRIPTION
The PGA103 is a programmable-gain amplifier for
general purpose applications. Gains of 1, 10, or 100 are
digitally selected by two CMOS/TTL-compatible in-
puts. The PGA103 is ideal for systems that must
handle wide dynamic range signals.
G=1, 10, 100V/V
● CMOS/TTL-COMPATIBLE INPUTS
● LOW GAIN ERROR: ±0.05% max, G=10
● LOW OFFSET VOLTAGE DRIFT: 2µV/°C
● LOW QUIESCENT CURRENT: 2.6mA
● LOW COST
The PGA103’s high speed circuitry provides fast set-
tling time, even at G=100 (8µs to 0.01%). Bandwidth
is 250kHz at G=100, yet quiescent current is only
2.6mA. It operates from ±4.5V to ±18V power
supplies.
● 8-PIN PLASTIC DIP, SO-8 PACKAGES
The PGA103 is available in 8-pin plastic DIP and
SO-8 surface-mount packages, specified for the –40°C
to +85°C temperature range.
APPLICATIONS
● DATA ACQUISITION SYSTEMS
● GENERAL PURPOSE ANALOG BOARDS
● MEDICAL INSTRUMENTATION
V+
V–
8
6
4
7
VO
PGA103
VIN
3
VO = G • VIN
1
2
GAIN
A1
A0
1
0
0
1
0
1
0
10
100
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
Telex: 066-6491
•
Street Address: 6730 S. Tucson Blvd.
• Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111
•
•
•
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1993 Burr-Brown Corporation
PDS-1208B
Printed in U.S.A. November, 1993
SBOS031
SPECIFICATIONS
ELECTRICAL
TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise specified.
PGA103P, U
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
INPUT
Offset Voltage, RTI
G = 1
TA = +25°C
±200
±100
±100
±1500
±500
±500
µV
µV
µV
G = 10
G = 100
vs Temperature
G = 1
G = 10
TA = TMIN to TMAX
±5
±2
±2
µV/°C
µV/°C
µV/°C
G = 100
vs Power Supply
G = 1
G = 10
G = 100
Impedance
VS = ±4.5V to ±18V
30
10
10
70
35
35
µV/V
µV/V
µV/V
108 || 2
Ω || pF
INPUT BIAS CURRENT
Initial Bias Current
vs Temperature
±50
±100
±150
nA
pA/°C
NOISE VOLTAGE, RTI
f = 10Hz
f = 100Hz
f = 1kHz
fB = 0.1Hz to 10Hz
G = 100, RS = 0Ω
16
11
11
0.6
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
NOISE CURRENT
f = 10Hz
f = 1kHz
2.8
0.3
76
pA/√Hz
pA/√Hz
pAp-p
fB = 0.1Hz to 10Hz
GAIN
Gain Error
G = 1
G = 10
G = 100
Gain vs Temperature
G = 1
±0.005
±0.02
±0.04
±0.02
±0.05
±0.2
%
%
%
±2
±10
±30
ppm/°C
ppm/°C
ppm/°C
G = 10
G = 100
Nonlinearity
G = 1
G = 10
G = 100
±0.001
±0.002
±0.004
±0.003
±0.005
±0.01
% of FSR
% of FSR
% of FSR
OUTPUT
Voltage, Positive
Negative
Load Capacitance, max
Short-Circuit Current
(V+) –3.5
(V–) +3.5
(V+) –2.5
(V–) +2.5
1000
V
V
pF
mA
±25
FREQUENCY RESPONSE
Bandwidth, –3dB
G = 1
G = 10
G = 100
1.5
750
250
9
MHz
kHz
kHz
V/µs
Slew Rate
VO = ±10V
Settling Time, 0.1%
G = 1
G = 10
2
2.2
6.5
µs
µs
µs
G = 100
Settling Time, 0.01%
G = 1
G = 10
G = 100
Overload Recovery
2.5
2.5
8
µs
µs
µs
µs
50% Overdrive
2.5
DIGITAL LOGIC INPUTS
Digital Low Voltage
Digital Low or High Current
Digital High Voltage
–5.6
2
0.8
V+
V
µA
V
1
®
2
PGA103
SPECIFICATIONS (CONT)
ELECTRICAL
TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise specified.
PGA103P, U
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
POWER SUPPLY
Voltage Range
Current
±4.5
±15
±2.6
±18
±3.5
V
mA
VIN = 0V
TEMPERATURE RANGE
Specification
Operating
–40
–40
+85
+125
°C
°C
θJA: P or U Package
100
°C/W
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................................. ±18V
Analog Input Voltage Range ..................................................... V– to V+
Logic Input Voltage Range ........................................................ V– to V+
Output Short Circuit (to ground) ............................................ Continuous
Operating Temperature ................................................ –40°C to +125°C
Storage Temperature .................................................... –40°C to +125°C
Junction Temperature ...................................................................+150°C
Lead Temperature (soldering,10s) .............................................. +300°C
Top View
DIP/SO-8
A0
1
8
V+
A1
Ground
VIN
2
3
4
7
6
5
VO
V–
NC
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER(1)
ORDERING INFORMATION
PGA103P
PGA103U
8-Pin Plastic DIP
SO-8 Surface-Mount
006
182
MODEL
PACKAGE
TEMPERATURE RANGE
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
PGA103P
PGA103U
8-Pin Plastic DIP
SO-8 Surface-Mount
–40°C to +85°C
–40°C to +85°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
PGA103
DICE INFORMATION
PAD
FUNCTION
1
2
A0
A1
Ground
VIN
NC
6
NC
NC
NC
NC
3A, 3B, 3C(1)
4A, 4B, 4C(2)
6
7
8
V–
VO
V+
7
4C
NC: No Connection
NOTES: (1) Connect all three indicated pads. (2) Connect
all three indicated pads.
Substrate Bias: Internally connected to V– power supply.
8
1
2
MECHANICAL INFORMATION
3A
3B
3C
4A
4B
MILS (0.001")
MILLIMETERS
Die Size
Die Thickness
Min. Pad Size
69 x 105 ±5
20 ±3
1.75 x 2.67 ±0.13
0.51 ±0.08
4 x 4
0.1 x 0.1
PGA103 DIE TOPOGRAPHY
Backing
Gold
TYPICAL PERFORMANCE CURVES
TA = +25°C, VS = ±15V unless otherwise noted.
VOLTAGE GAIN vs FREQUENCY
50
POWER SUPPLY REJECTION vs FREQUENCY
120
100
80
60
40
20
0
G=100
40
30
G=100
G=10
G=10
20
10
G=1
G=1
0
–10
10k
100k
Frequency (Hz)
1M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
®
4
PGA103
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VS = ±15V unless otherwise noted.
INPUT CURRENT NOISE vs FREQUENCY
INPUT VOLTAGE NOISE vs FREQUENCY
1000
100
10
100
10
1
G=1
G=10
G=100
1
Bandwidth
Limited
All Gains
0.1
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
SMALL SIGNAL RESPONSE
QUIESCENT CURRENT vs TEMPERATURE
4
3
G=1
G=10
G=100
2
1
0
2µs/div
–50
–25
0
25
50
75
100
125
Temperature (°C)
LARGE SIGNAL RESPONSE
G=10
G=1
G=100
2µs/div
®
5
PGA103
Some applications select gain of the PGA103 with switches
or jumpers. Figure 2 shows pull-up resistors connected to
assure a noise-free logic “1” when the switch or jumper is
off or open. Fixed-gain applications can connect the logic
inputs directly to V+ or ground (or other valid logic level)
without a series resistor.
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the PGA103. Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the device pins as shown.
V+
V–
V+ V–
+15V –15V
0.1µF
0.1µF
8
6
4
7
PGA103
VIN
100kΩ
VO
A
8
0
3
A
1
1
2
6
V+
4
7
100kΩ
VO = G • VIN
PGA103
VIN
3
A0
GAIN
S1
S0
A1
1
1
10
100
Closed Closed
Closed Open
Open Closed
S1
S0
2
Not Valid Open Open
FIGURE 2. Switch or Jumper-Selected Gains.
GAIN
A1
A0
1
10
0
0
1
1
0
1
0
1
OFFSET TRIMMING
Logic 0: (–5.6) ≤ V ≤ 0.8V
Logic 1: 2V ≤ V ≤ (V+)
Logic voltages referred to pin 3.
100
Offset voltage is laser-trimmed to typically less than 200µV
(referred to input) in all three gains. The input-referred offset
voltage can be different for each gain.
Not Valid
NOTE: (1) Low impedance ground connection required for good gain
accuracy—see text.
FIGURE 1. Basic Connections.
+15V –15V
The input and output are referred to the ground terminal,
pin 3. This must be a low-impedance connection to assure
good gain accuracy. A resistance of 0.1Ω in series with the
ground pin will cause the gain in G=100 to decrease by
approximately 0.2%.
VIN
VO = G (VIN – VTRIM)
PGA103
A0
3
A1
1
VTRIM
2
(1)
+15V
DIGITAL INPUTS
OPA602
±5mV
The digital inputs, A0 and A1, select the gain according to
the logic table in Figure 1. The digital inputs interface
directly to common CMOS and TTL logic components. The
logic inputs are referenced to the ground terminal, pin 3.
100kΩ
50kΩ
Trim Range
33Ω
Logic threshold voltage
is altered by VTRIM
OK for VTRIM ≤ 100mV.
–15V
The logic table in Figure 1 shows that logic “1” on both A0
and A1 is invalid. This logic code will not cause damage, but
the amplifier output will not be predictable while this code
is selected. The output will recover when a valid code is
selected.
.
NOTE: (1) Op amp buffer is required to preserve good gain accuracy—see
text.
The digital inputs are not latched, so a change in logic inputs
immediately selects a new gain. Switching time of the logic
is approximately 0.5µs. The time to respond to gain change
is equal to the switching time plus the time it takes the
amplifier to settle to a new output voltage in the newly
selected gain (see settling time specifications).
FIGURE 3. Offset Voltage Trim Circuit.
Figure 3 shows a circuit used to trim the offset voltage of the
PGA103. An op amp buffers the trim voltage to provide a
low impedance at the ground terminal. This is required to
maintain accurate gain. Remember that the logic inputs, A0
and A1, are referenced to this ground connection, so the
logic threshold voltage will be affected by the trim voltage.
This is insignificant if the offset adjustment is used only to
trim offset voltage. If a large offset is used (greater than
0.1V), be sure that the logic input signals provide valid logic
levels when referred to the voltage at the ground terminal,
pin 3.
Many applications use an external logic latch to access gain
control signals from a high speed data bus. Using an external
latch isolates the high speed digital bus from sensitive
analog circuitry. Locate the latch circuitry as far as practical
from analog circuitry to avoid coupling digital noise into the
analog circuitry.
®
6
PGA103
V+ V–
V+ V–
G1 = 1, 2, 4, 8
+15V –15V
G2 = 1, 10, 100
8
6
G = 0.1, 1, 10
VO
–
+
VIN
D1
D2
102kΩ
7
4
VO
PGA103
PGA205
PGA103
VIN
A0
A0
VIN
3
G = G1 • G2
A1
A1
1
Accepts inputs
to ±120V.
2
11.3kΩ
True
instrumentation
amplifier input.
D1, D2; IN4148
A1 A0
GAIN
1
2
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
FIGURE 5. Wide Input Voltage Range Amplifer.
4
8
10
20
40
80
100
200
400
800
FIGURE 4. Programmable Gain Instrumentation Amplifier.
G1
G2 = 1, 10, 100
MODEL
CHARACTERISTICS
+
–
VIN
INA103
INA105
INA106
INA114
INA117
INA111
INA131
Low Noise, 1nV/√Hz IA
G = 1 Difference Amp
G = 10 Difference Amp
Resistor-Programmed Gain, Precision
±200V C-M Input Range Difference Amp
FET Input, High Speed IA
Precision, G = 100 IA
VO
G = G1 • G2
PGA103
INA
VIN
A1 A0
FIGURE 6. Instrumentation Amplifier with Programmable Gain Output Amp.
®
7
PGA103
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PGA103U
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
PGA
103U
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PGA103U
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 1
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
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Copyright © 2022, Texas Instruments Incorporated
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