PGA203KP [TI]
数控（二进制模型增益 1、2、4、8）可编程增益仪表放大器 | N | 14 | -25 to 85;
| 型号： | PGA203KP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 数控（二进制模型增益 1、2、4、8）可编程增益仪表放大器 | N | 14 | -25 to 85 放大器 仪表 光电二极管 仪表放大器 |
| 文件： | 总14页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
PGA202/203
Digitally Controlled Programmable-Gain
INSTRUMENTATION AMPLIFIER
FEATURES
APPLICATIONS
● DIGITALLY PROGRAMMABLE GAINS:
DECADE MODEL—PGA202
GAINS OF 1, 10, 100, 1000
BINARY MODEL—PGA203
GAINS OF 1, 2, 4, 8
● DATA ACQUISITION SYSTEMS
● AUTO-RANGING CIRCUITS
● DYNAMIC RANGE EXPANSION
● REMOTE INSTRUMENTATION
● TEST EQUIPMENT
● LOW BIAS CURRENT: 50pA max
● FAST SETTLING: 2µs to 0.01%
● LOW NON-LINEARITY: 0.012% max
● HIGH CMRR: 80dB min
● NEW TRANSCONDUCTANCE CIRCUITRY
● LOW COST
DESCRIPTION
VOS Adjust
The PGA202 is a monolithic instrumentation ampli-
fier with digitally controlled gains of 1, 10, 100, and
1000. The PGA203 provides gains of 1, 2, 4, and 8.
Both have TTL or CMOS-compatible inputs for easy
microprocessor interface. Both have FET inputs and a
new transconductance circuitry that keeps the band-
width nearly constant with gain. Gain and offsets are
laser trimmed to allow use without any external com-
ponents. Both amplifiers are available in ceramic or
plastic packages. The ceramic package is specified
over the full industrial temperature range while the
plastic package covers the commercial range.
6
9
10
Filter B
5.3pF*
30kΩ*
+VIN
Sense
VOUT
VREF
11
12
4
8
7
Front
End
and
I1
–
+
Logic
Circuits
+VIN
I2
30kΩ*
5.3pF*
5
Filter A
*±20%
1
2
14
A0 A1 Digital Common
Covered by U.S. PATENT #4,883,422
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
• Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111
•
•
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1989 Burr-Brown Corporation
PDS-1006C
Printed in U.S.A. August, 1993
SBOS002
SPECIFICATIONS
ELECTRICAL
At +25°C, VCC = ±15V unless otherwise noted.
PGA202/203AG(1)
PGA202/203BG(1)
PGA202/203KP(1)
PARAMETER
CONDITION
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
GAIN
Error (2)
G < 1000
G = 1000
G < 1000
G = 1000
G < 100
0.05
0.1
0.002
0.02
3
0.25
1
0.015
0.06
25
*
0.15
0.5
0.012
0.04
15
*
*
*
*
*
*
*
*
*
*
*
%
%
%
0.08
Nonlinearity
*
*
*
*
*
%
Gain vs Temperature
ppm/°C
ppm/°C
ppm/°C
G = 100
G = 1000
40
100
120
300
60
150
RATED OUTPUT
Voltage
Over Specified Temperature
Current
Impedance
|IOUT| ≤ 5mA
See Typical Perf. Curve
±10
±5
±12
±9
±10
0.5
*
*
*
*
*
*
*
*
*
±10
*
V
V
mA
Ω
|VOUT
|
≤ 10V
*
ANALOG INPUTS
Common-Mode Range
Absolute Max Voltage(3)
Impedance, Differential
Common-Mode
±10
±13
*
*
*
*
V
V
No Damage
±VCC
*
*
*
10 || 3
10 || 1
*
*
*
*
GΩ || pF
GΩ || pF
OFFSET VOLTAGE (RTI)
Initial Offset at 25°C(4)
±(0.5 +
5/G)
±(3 +
50/G)
50
±(2 +
24/G)
±(24 +
*
*
±(1 +
12/G)
±(12 +
*
*
mV
vs Temperature
µV/°C
240/G)
120/G)
Offset vs Time
Offset vs Supply
*
*
*
*
µV/Month
µV/V
10 ≤ VCC ≤ 15
10 +
250/G
100 +
900/G
50 +
450/G
*
INPUT BIAS CURRENT
Initial Bias Current: at 25°C
at 85°C
Initial Offset Current:at 25°C
at 85°C
10
640
5
50
3200
25
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
pA
pA
pA
pA
320
1600
COMMON-MODE REJECTION RATIO
G = 1
G = 10
G = 100
G = 1000
80
86
92
94
100
110
120
120
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
dB
dB
dB
dB
INPUT NOISE
Noise Voltage 0.1 to 10Hz
1.7
12
*
*
*
*
µVp-p
nV/√Hz
Noise Density at 10kHz (5)
OUTPUT NOISE
Noise Voltage 0.1 to 10Hz
32
400
*
*
*
*
µVp-p
nV/√Hz
Density at 1kHz (5)
DYNAMIC RESPONSE
Frequency Response
G < 1000
G = 1000
G < 1000
G = 1000
1000
250
400
100
20
2
10
5
10
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
kHz
kHz
kHz
kHz
V/µs
µs
µs
µs
µs
Full Power Bandwidth
Slew Rate
10
15
*
Settling Time (0.01%)(7)
G < 1000
G = 1000
G < 1000
G = 1000
Overload Recovery Time(7)
DIGITAL INPUTS
Digital Common Range
Input Low Threshold (6)
Input Low Current
Input High Voltage
Input High Current
–VCC
2.4
VCC – 8
0.8
10
*
*
*
*
*
*
*
*
*
*
V
V
µA
V
10
*
*
µA
POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current
±15
*
*
*
*
V
V
mA
±6
±18
*
*
*
*
6.5
TEMPERATURE RANGE
Specification
Operating
–25
–55
–65
85
125
150
*
*
*
*
*
*
0
–25
–40
70
85
100
°C
°C
°C
Storage
θJA
100
*
*
°C/W
* Same as the PGA202/203AG
NOTES: (1) All specifications apply to both the PGA202 and the PGA203. Values given for a gain of 10 are the same for a gain of 8 and other values may be interpolated.
(2) Measured with a 10k load. (3) The analog inputs are internally diode clamped. (4) Adjustable to zero. (5) VNOISE (RTI) = √(VN INPUT)
2 + (VN OUTPUT/Gain)2.
(6) Threshold voltages are referenced to Digital Common. (7) From input change or gain change.
®
2
PGA202/203
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Top View
DIP
Supply Voltage ................................................................................... ±18V
Internal Power Dissipation ............................................................. 750mW
Analog and Digital Inputs ..................................................... ±(VCC + 0.5V)
Operating Temperature Range:
G Package ............................................................... –55°C to +125°C
P Package ............................................................... –40°C to +100°C
Lead Temperature (soldering, 10s) .................................................. 300°C
Output Short Circuit Duration ................................................... Continuous
Junction Temperature ...................................................................... 175°C
A0
A1
1
2
3
4
5
6
7
14 Digital Common
13 –VCC
+VCC
12 VOUT
VREF
11 VOUT Sense
10 Filter B
Filter A
VOS Adjust
–VIN
9
8
VOS Adjust
+VIN
PACKAGE INFORMATION
PACKAGE DRAWING
NUMBER(1)
MODEL
PACKAGE
14-Pin Plastic DIP
14-Pin Ceramic DIP
14-Pin Ceramic DIP
14-Pin Plastic DIP
14-Pin Ceramic DIP
14-Pin Ceramic DIP
PGA202KP
PGA202AG
PGA202BG
PGA203KP
PGA203AG
PGA203BG
010
169
169
010
169
169
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ORDERING INFORMATION
TEMPERATURE
RANGE
OFFSET VOLTAGE
MAX (mV)
MODEL
GAINS
PACKAGE
PGA202KP
PGA202AG
PGA202BG
1, 10, 100, 1000
1, 10, 100, 1000
1, 10, 100, 1000
Plastic DIP
Ceramic DIP
Ceramic DIP
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
±(2 + 24/G)
±(2 + 24/G)
±(1 + 12/G)
PGA203KP
PGA203AG
PGA203BG
1, 2, 4, 8
1, 2, 4, 8
1, 2, 4, 8
Plastic DIP
Ceramic DIP
Ceramic DIP
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
±(2 + 24/G)
±(2 + 24/G)
±(1 + 12/G)
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
PGA202/203
TYPICAL PERFORMANCE CURVES
TA = +25°C, VS = ±15V unless otherwise noted.
GAIN vs FREQUENCY
80
GAIN ERROR vs FREQUENCY
10
1
60
40
G = 1000
10–1
20
G = 1
0
10–2
10–3
–20
–40
102
103
Frequency (Hz)
104
105
106
107
1
10
102
103
104
105
1
10
Frequency (Hz)
CMRR vs FREQUENCY
PSRR vs FREQUENCY
G = 100
160
160
G = 100, 1000
120
80
120
80
G = 1000
G = 10
G = 10
G = 1
G = 1
40
40
0
0
–40
–40
1
10
102
103
Frequency (Hz)
104
105
106
1
10
102
103
104
105
106
Frequency (Hz)
INPUT NOISE vs FREQUENCY
OUTPUT NOISE vs FREQUENCY
104
103
104
103
102
102
10
1
10
1
1
10
102
103
104
105
1
10
102
103
104
105
Frequency (Hz)
Frequency (Hz)
®
4
PGA202/203
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VS = ±15V unless otherwise noted.
QUIESCENT CURRENT vs POWER SUPPLY
INPUT BIAS CURRENT vs POWER SUPPLY
10
8
12
11
10
9
6
4
2
0
8
7
0
6
9
12
15
18
6
9
12
15
18
Power Supply (±V)
Power Supply (±V)
OUTPUT SWING vs POWER SUPPLY
TA = +25°C
INPUT RANGE vs POWER SUPPLY
15
10
16
12
8
TA = –25°C
5
0
4
0
6
9
12
15
18
6
9
12
15
18
Power Supply (±V)
Power Supply (±V)
OUTPUT SWING vs LOAD
SETTLING TIME vs FILTER CAPACITOR
15
10
5
10
8
6
4
2
0
–4
0
500
1000
1500
2000
0
10
20
30
Load ( Ω)
Filter Capacitor (pF)
®
5
PGA202/203
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VS = ±15V unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
INPUT BIAS CURRENT vs TEMPERATURE
10
8
103
102
10
1
6
4
2
0
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
CURRENT LIMIT vs TEMPERATURE
SLEW RATE vs TEMPERATURE
25
20
15
10
25
20
15
10
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
LARGE SIGNAL RESPONSE
OUTPUT SWING vs TEMPERATURE
14
12
10
8
G = 10
6
–50
–25
0
25
50
75
100
1µs/Div
Temperature (°C)
®
6
PGA202/203
TYPICAL PERFORMANCE
DIN
CURVES (CONT)
TA = +25°C, VCC = ±15V unless otherwise noted.
1
2
14
8
7
SMALL SIGNAL RESPONSE
+
–
11
4
12
VIN
VOUT
PGA202
13
3
RL
G = 10
+VCC –VCC
1µs/Div
FIGURE 1. Basic Circuit Connections.
OFFSET ADJUSTMENT
DISCUSSION OF
PERFORMANCE
Figure 2 shows the offset adjustment circuits for the PGA202/
203. The input offset and the output offset are both sepa-
rately adjustable. Notice that because the PGA202/203 change
between four different input stages to change gain, the input
offset voltage will change slightly with gain. For systems
using computer autozeroing techniques, neither offset nor
drift is a major concern, but it should be noted that since the
input offset does change with gain, these systems should
perform an autozero cycle after each gain change for opti-
mum performance.
A simplified diagram of the PGA202/203 is shown on the
first page. The design consists of a digitally controlled,
differential transconductance front end stage using precision
FET buffers and the classical transimpedance output stage.
Gain switching is accomplished with a novel current steer-
ing technique that allows for fast settling when changing
gains. The result is a high performance, programmable
instrumentation amplifier with excellent speed and gain
accuracy.
In the output offset adjustment circuit, the choice of the
buffering op amp is very important. The op amp needs to
have low output impedance and a wide bandwidth to main-
tain full accuracy over the entire frequency range of the
PGA202/203. For these reasons we recommend the OPA602
as an excellent choice for this application.
The input stage uses a new circuit topology that includes
FET buffers to give extremely low input bias currents. The
differential input voltage is converted into a differential
output current with the transconductance gain selected by
steering the input stage bias current between four identical
input stages differing only in the value of the gain setting
resistor. Each input stage is individually laser-trimmed for
input offset, offset drift, and gain.
+VCC
The output stage is a differential transimpedance amplifier.
Unlike the classical difference amplifier output stage, the
common-mode rejection is not limited by the resistor match-
ing. However, the output resistors are laser-trimmed to help
minimize the output offset and drift.
50k
Ω
+VCC
6
8
7
9
+
11
12
VIN
VOUT
PGA202
BASIC CONNECTIONS
–
10kΩ
4
Figure 1 shows the proper connections for power supply and
signal. The power supplies should be decoupled with 1µF
tantalum capacitors placed as close to the amplifier as
possible for maximum performance. To avoid gain and
CMR errors introduced by the external components, you
should connect the grounds as indicated. Any resistance in
the sense line (pin 11) or the VREF line (pin 4) will lead to
a gain error, so these lines should be kept as short as
possible. To also maintain stability, avoid capacitance from
the output to the input or the offset adjust pins.
100kΩ
100Ω
+
–VCC
–
OPA602
FIGURE 2. Offset Adjustment Circuits.
®
7
PGA202/203
GAIN SELECTION
OUTPUT SENSE
Gain selection is accomplished by the application of a 2-bit
digital word to the gain select inputs. Table I shows the gains
for the different possible values of the digital input word.
The logic inputs are referred to their own separate digital
common pin, which can be connected to any voltage be-
tween the minus supply and 8V below the positive supply.
The gains are all internally trimmed to an initial accuracy of
better than 0.1%, so no external gain adjustment is required.
However, if necessary the gains can be increased by the use
of an external attenuator around the output stage as shown in
Figure 3. Recommended resistor values for certain selected
output gains are given in Table II.
An output sense has been provided to allow greater accuracy
in connecting the load. By attaching this feedback point to
the load at the load site, IR drops due to the load currents are
eliminated since they are inside the feedback loop. Proper
connection is shown in Figure 1. When more current is
required, a power booster can be placed in the feedback loop
as shown in Figure 4. Buffer errors are minimized by the
loop gain of the output amplifier.
14
8
+
11
12
PGA202
ERROR
PGA203
ERROR
VOUT
VIN
OPA633
PGA202
7
4
A1
A0
GAIN
GAIN
–
2
RL
0
0
1
1
0
1
0
1
1
10
100
1000
0.05%
0.05%
0.05%
0.10%
1
2
4
8
0.05%
0.05%
0.05%
0.05%
1
A0
A1
TABLE I. Software Gain Selection.
OUTPUT GAIN
R1
R2
FIGURE 4. Current Boosting the Output.
2
5
10
5kΩ
2kΩ
1kΩ
5kΩ
8kΩ
9kΩ
OUTPUT FILTERING
The summing nodes of the output amplifier have also been
made available to allow for output filtering. By placing
matched capacitors in parallel with the existing internal
capacitors as shown in Figure 5, you can lower the fre-
quency response of the output amplifier. This will reduce the
noise of the amplifier, at the cost of a slower response. The
nominal frequency responses for some selected values of
capacitor are shown in Table III.
TABLE II. Output Stage Gain Control.
8
+
11
12
VOUT
VIN
PGA202
7
–
4
R1
R2
+
OPA602
–
CEXT
10
8
+
11
12
VIN
FIGURE 3. Gain Increase with Buffered Attenuator.
VOUT
PGA202
7
4
–
COMMON-MODE INPUT RANGE
5
Unlike the classical three op amp type of circuit, the input
common-mode range of the PGA202/203 does not depend
on the differential input and the gain. In the standard three
op amp circuit, the input common-mode signal must be kept
below the maximum output voltage of the input amplifier
minus 1/2 the final output voltage. If, for example, these
amplifiers can swing ±12V, then to get 12V at the output you
must restrict the input common-mode voltage to only 6V.
The circuitry of the PGA202/203 is such that the common-
mode input range applies to either input pin regardless of the
output voltage.
CEXT
FIGURE 5. Output Filtering.
CUTOFF FREQUENCY
C1 AND C2
1MHz
100kHz
10kHz
None
47pF
525pF
TABLE III. Output Frequency vs Filter Capacitors.
®
8
PGA202/203
INPUT CHARACTERISTICS
Because the PGA202/203 have FET inputs, the bias currents
drawn through input source resistors have a negligible effect
on DC accuracy. The picoamp currents produce no more
than microvolts through megohm sources. The inputs are
also internally diode clamped to the supplies. Thus, input
filtering and input series protection are easily achievable.
14
8
7
+
11
4
VOUT
12
PGA203
ISO
102
–
2
1
A return path for the input bias currents must always be
provided to prevent the charging of any stray capacitance.
Otherwise, the amplifier could wander and saturate. A 1MΩ
to 10MΩ resistor from the input to common will return
floating sources such as thermocouples and AC-coupled
inputs (see Applications Section, Figures 8 and 9.)
+5
RL
Digital
Opto-
Coupler
DIN
DYNAMIC PERFORMANCE
The PGA202 and the PGA203 are fast-settling FET input
programmable gain instrumentation amplifiers. Careful at-
tention to minimize stray capacitance is necessary to achieve
specified performance. High source resistance will interact
with the input capacitance to reduce speed and overall
bandwidth. Also, to maintain stability, avoid capacitance
from the output to the input or the offset adjust pins.
FIGURE 6. Isolated Programmable Gain Instrumentation
Amplifier.
Applications with balanced source impedance will provide
the best performance. In some applications, mismatched
source impedances may be required. If the impedance in the
negative input exceeds that in the positive input, stray
capacitance from the output will create a net negative feed-
back and improve the stability of the circuit. If, however, the
impedance in the positive input is greater, then the feedback
due to stray capacitance will be positive and instability may
result. The degree of positive feedback will, of course,
depend on the source impedance imbalance as well as the
board layout and the operating gain. The addition of a small
bypass capacitor of about 5 to 50pF directly across the input
terminals of the PGIA will generally eliminate any instabil-
ity arising from these stray capacitances. CMR errors due to
the source imbalance will also be reduced by the addition of
this capacitor.
14
8
+
11
VOUT
12
VIN
PGA202
7
4
–
2
1
+
–
Down
VREF
10V
2-Bit
Up/Down
Counter
Dual
Comparator
R1
10kΩ
OSC
–
+
Up
R2
Ω
1k
The PGA202 and the PGA203 are designed for fast settling
in response to changes in either the input voltage or the gain.
The bandwidth and the settling times are mostly determined
by the output stage and are therefore independent of gain,
except at the highest gain of the PGA202 where other factors
in the input stage begin to dominate.
FIGURE 7. Auto Gain Ranging.
1µF
14
8
+
11
4
VOUT
APPLICATIONS
12
VIN
PGA202
1µF
7
In addition to general purpose applications, the PGA202/203
are designed to handle two important and demanding classes
of applications: inputs with high source impedances, and
rapid scanning data acquisition systems requiring fast set-
tling time. Because the user has access to output sense and
output common pins, current sources can also be constructed
with a minimum of external components. Some basic appli-
cation circuits are shown in Figures 6 through 12.
–
2
1
1MΩ 1MΩ
Gain Control
FIGURE 8. AC-Coupled Differential Amplifier for
Frequencies Above 0.16Hz.
®
9
PGA202/203
8
7
+
11
4
12
VIN
PGA202
14
8
7
+
11
4
–
VOUT
2
12
PGA203
1
1
–
A0
A1
2
VOUT
1
1MΩ
2
8
7
+
11
4
12
PGA202
Gain Control
–
VOUT = 2G VIN
FIGURE 9. Floating Source Programmable Gain Instrumen-
tation Amplifier.
FIGURE 11. Programmable Differential In/Differential Out
Amplifier.
+
OPA27
–
+VCC
14
14
10kΩ
8
8
+
+
11
11
VOUT
12
R
12
VIN
200Ω
PGA203
PGA203
10kΩ
7
7
4
4
–
–
10k
Ω
2
2
1
1
–
OPA27
R
+
IOUT
Gain Control
Gain Control
RL
FIGURE 10. Low Noise Differential Amplifier with Gains of
100, 200, 400, 800.
FIGURE 12. Programmable Current Source.
A3
A2
A1
A0
GAIN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
4
8
10
20
40
80
100
200
400
800
1000
2000
4000
8000
14
8
+
11
14
12
8
7
VIN
+
PGA202
11
4
VOUT
12
7
4
–
PGA203
2
1
–
2
1
A2 A3
A0 A1
FIGURE 13. Cascaded Amplifiers.
®
10
PGA202/203
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PGA202KP
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-25 to 85
PGA202KP
Samples
Samples
PGA202KPG4
PGA203KP
LIFEBUY
ACTIVE
PDIP
PDIP
N
N
14
14
25
25
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
N / A for Pkg Type
N / A for Pkg Type
-25 to 85
-25 to 85
PGA202KP
PGA203KP
PGA203KPG4
LIFEBUY
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-25 to 85
PGA203KP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PGA202KP
PGA202KPG4
PGA203KP
N
N
N
N
PDIP
PDIP
PDIP
PDIP
14
14
14
14
25
25
25
25
506
506
506
506
13.97
13.97
13.97
13.97
11230
11230
11230
11230
4.32
4.32
4.32
4.32
PGA203KPG4
Pack Materials-Page 1
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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